19-2655; Rev 2; 10/04 Low-Cost, Voltage-Output, 16-Bit DACs with Internal Reference in MAX The MAX5200-MAX5203 serial input, voltage-output, 16-bit digital-to-analog converters (DACs) provide monotonic 16-bit output over temperature without any adjustments. The MAX5200/MAX5201 operate from a +5V single power supply featuring an internal reference of +2.5V and an internal gain of 2, while the MAX5202/ MAX5203 operate from a +3V or +3.3V single power supply featuring an internal reference of +1.5V and an internal gain of 2. The MAX5200-MAX5203 DAC output range is typically from 0 to VDD. The MAX5200-MAX5203 feature a hardware reset input (CLR) that, when pulled low, clears the output to zero code 0000 hex (MAX5201/MAX5203) or resets the output to midscale code 8000 hex (MAX5200/MAX5202). The 3-wire serial interface is compatible with SPITM/QSPITM/MICROWIRETM. All devices have a lowpower shutdown mode that reduces the supply current consumption to 1A. The MAX5200-MAX5203 are available in a space-saving 10-pin MAX(R) package and are guaranteed over the extended temperature range (-40C to +105C). Refer to the MAX5204-MAX5207 data sheet for external reference versions. Features Guaranteed 16-Bit Monotonic Internal Reference 10-Pin 5mm 3mm MAX Package Rail-to-Rail Output Amplifier Single-Supply Operation +5V (MAX5200/MAX5201) +3V, +3.3V (MAX5202/MAX5203) Low Power Consumption: 0.8mA Shutdown Mode Reduces Supply Current to 1A SPI/QSPI/MICROWIRE-Compatible 3-Wire Serial Interface Power-On-Reset Sets Output to Midscale (MAX5200/MAX5202) Zero Scale (MAX5201/MAX5203) Applications Low-Cost VCO/VCXO Frequency Control Ordering Information PART TEMP RANGE PIN-PACKAGE Industrial Process Control MAX5200AEUB -40C to +105C 10 MAX High-Resolution Offset Adjustment MAX5200BEUB -40C to +105C 10 MAX MAX5200ACUB 0C to +70C 10 MAX MAX5201AEUB -40C to +105C 10 MAX MAX5201BEUB -40C to +105C 10 MAX MAX5201ACUB 0C to +70C 10 MAX Pin Configuration TOP VIEW CLR 1 REF 2 MAX5200- MAX5203 MAX5202AEUB -40C to +105C 10 MAX 10 DGND MAX5202BEUB -40C to +105C 10 MAX 9 SCLK MAX5202ACUB 0C to +70C 10 MAX AGND 3 8 DIN MAX5203AEUB -40C to +105C 10 MAX VDD 4 7 LDAC MAX5203BEUB -40C to +105C 10 MAX OUT 5 6 CS MAX5203ACUB 0C to +70C 10 MAX MAX Selector Guide appears at end of data sheet. SPI/QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. MAX is a registered trademark of Maxim Integrated Products, Inc. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. 1 MAX5200-MAX5203 General Description MAX5200-MAX5203 Low-Cost, Voltage-Output, 16-Bit DACs with Internal Reference in MAX ABSOLUTE MAXIMUM RATINGS VDD to AGND, DGND ...............................................-0.3V to +6V AGND to DGND...................................................-0.3V to +0.3V REF, OUT to AGND....................................-0.3V to (VDD + 0.3V) CLR, LDAC, SCLK, DIN, CS to DGND .......-0.3V to (VDD + 0.3V) Maximum Current into Any Pin............................................50mA Continuous Power Dissipation (TA = +70C) 10-Pin MAX (derate 5.6mW/C above +70C) ........444.4mW Operating Temperature Ranges MAX520_CUB .....................................................0C to +70C MAX520_EUB ...............................................-40C to +105C Junction Temperature ......................................................+150C Storage Temperature Range .............................-60C to +150C Lead Temperature (soldering, 10s) .................................+300C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS--MAX5200/MAX5201 (VDD = +4.75V to +5.25V, fSCLK = 10MHz (50% duty cycle), output load = 10k in parallel with 250pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX MAX520_AEUB 10 20 MAX520_ACUB 10 20 MAX520_BEUB 20 40 UNITS STATIC PERFORMANCE (Note 1) Resolution Integral Nonlinearity (Note 2) Differential Nonlinearity (Note 2) N INL DNL 16 MAX520_A_UB (Note 3) 1 MAX520_BEUB (0C to +105C) (Note 3) 1 MAX520_BEUB (-40C to 0C) 2 Inferred from measurement at 1C00 hex and FFFF hex Offset Error Bits 3 LSB LSB 25 mV Gain Error GE Within DAC output range (Note 4) 0.01 1 %FSR Power-Supply Rejection PSR VDD = 5V 5%, midscale input 0.06 0.5 mV/V DYNAMIC PERFORMANCE DAC Output Range Output-Voltage Slew Rate (Note 2) SR 0 to VDD V 0.6 V/s Output Settling Time To 1LSB of FS, VSTEP = 0.25 x VREF to 0.75 x VREF 25 s Output Noise DAC code = 8400 hex, 10kHz 175 nV/Hz DAC Glitch Impulse Major carry transition (code 7FFF hex to code 8000 hex) 10 nVs Digital Feedthrough Code = 0000 hex; CS = VDD; LDAC = 0; SCLK, DIN = 0 or VDD 10 nVs Wake-Up Time From software shutdown to 90% of output code = FFFF hex, CREF = 0.1F 50 s Power-Up Time From power applied to 90% of output code = FFFF hex 10 ms 2 _______________________________________________________________________________________ Low-Cost, Voltage-Output, 16-Bit DACs with Internal Reference in MAX (VDD = +4.75V to +5.25V, fSCLK = 10MHz (50% duty cycle), output load = 10k in parallel with 250pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 2.48 2.5 2.52 V INTERNAL REFERENCE VREF Output Voltage TA = +25C VREF Tempco TA = 0C to +70C 15 TA = -40C to +105C 20 ppm/C DIGITAL INPUTS (DIN, SCLK, CS, CLR, LDAC) Input High Voltage VIH Input Low Voltage VIL Input Hysteresis 2.4 VHYST Input Leakage IIN Input Capacitance CIN V 0.8 200 Digital inputs = 0 or VDD V mV 1 15 A pF POWER REQUIREMENTS Positive Power Supply VDD Positive Supply Current IDD Shutdown Supply Current ISHDN 4.75 All digital inputs at 0 or VDD (Note 5) All digital inputs at 0 or VDD 5.25 V 0.8 1.5 mA 1 10 A 10 MHz TIMING CHARACTERISTICS SCLK Frequency fSCLK SCLK Clock Period tCP 100 ns SCLK Pulse Width High tCH 40 ns SCLK Pulse Width Low tCL 40 ns DIN Setup Time tDS 40 ns ns DIN Hold Time tDH 0 CS Fall to SCLK Rise Setup Time tCSS 40 ns SCLK Rise to CS Rise Hold Time tCSH 0 ns SCLK Rise to CS Fall Ignore tCS0 10 ns CS Rise to SCLK Rise Ignore tCS1 40 ns LDAC Pulse Width tLDAC 40 ns CS Rise to LDAC Low Setup tLDACS 40 ns SCLK Fall to CS Fall Ignore tCSOL 10 ns CS Pulse Width Low for Shutdown tCSWL 40 ns CS Pulse Width High tCSWH 100 ns _______________________________________________________________________________________ 3 MAX5200-MAX5203 ELECTRICAL CHARACTERISTICS--MAX5200/MAX5201 (continued) MAX5200-MAX5203 Low-Cost, Voltage-Output, 16-Bit DACs with Internal Reference in MAX ELECTRICAL CHARACTERISTICS--MAX5202/MAX5203 (VDD = +2.7V to +3.6V, fSCLK = 10MHz (50% duty cycle), output load = 10k in parallel with 250pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX MAX520_AEUB 10 20 MAX520_ACUB 10 20 MAX520_BEUB 20 40 UNITS STATIC PERFORMANCE (Note 1) Resolution Integral Nonlinearity (Note 2) Differential Nonlinearity (Note 2) N INL DNL 16 MAX520_A_UB (Note 3) 1 MAX520_BEUB (0C to +105C) (Note 3) 1 MAX520_BEUB (-40C to 0C) 2 Inferred from measurement at 3800 hex and FFFF hex Offset Error Bits LSB LSB 3 25 mV Gain Error GE Within DAC output range (Note 4) 0.01 1.0 %FSR Power-Supply Rejection PSR VDD = 3V 10%, midscale input 0.06 0.5 mV/V DYNAMIC PERFORMANCE DAC Output Range Voltage-Output Slew Rate (Note 2) SR 0 to VDD V 0.6 V/s Output Settling Time To 1 LSB of FS, VSTEP = 0.25 VREF to 0.75 VREF 25 s Output Noise Code = 8400 hex, 10kHz 175 nV/Hz Reference Feedthrough Code = 0000 hex at 100kHz, VREF = 1VP-P 1 mVP-P DAC Glitch Impulse Major carry transition (code 7FFF hex to code 8000 hex) 10 nVs Digital Feedthrough Code = 0000 hex; CS = VDD; LDAC = 0; SCLK, DIN = 0 or VDD levels 10 nVs Wake-Up Time From software shutdown to 90% of output code = FFFF hex 50 s Power-Up Time From power applied to 90% of output code = FFFF hex 10 ms 4 _______________________________________________________________________________________ Low-Cost, Voltage-Output, 16-Bit DACs with Internal Reference in MAX (VDD = +2.7V to +3.6V, fSCLK = 10MHz (50% duty cycle), output load = 10k in parallel with 250pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 1.46 1.5 1.54 V INTERNAL REFERENCE VREF Output Voltage TA = +25C VREF Tempco TA = 0C to +70C 15 TA = -40C to +105C 20 ppm/C DIGITAL INPUTS (DIN, SCLK, CS, CLR, LDAC) Input High Voltage VIH Input Low Voltage VIL Input Hysteresis 2.1 VHYST Input Leakage IIN Input Capacitance CIN V 0.6 200 Digital inputs = 0 or VDD V mV 1 15 A pF POWER REQUIREMENTS Positive Power Supply VDD Positive Supply Current IDD Shutdown Supply Current ISHDN 2.7 All digital inputs at 0 or VDD (Note 5) All digital inputs at 0 or VDD 3.6 V 0.8 1.5 mA 1 10 A 10 MHz TIMING CHARACTERISTICS SCLK Frequency fSCLK SCLK Clock Period tCP 100 ns SCLK Pulse Width High tCH 40 ns SCLK Pulse Width Low tCL 40 ns DIN Setup Time tDS 40 ns DIN Hold Time tDH 0 ns CS Fall to SCLK Rise Setup Time tCSS 40 ns SCLK Rise to CS Rise Hold Time tCSH 0 ns SCLK Rise to CS Fall Ignore tCS0 10 ns CS Rise to SCLK Rise Ignore tCS1 40 ns LDAC Pulse Width tLDAC 40 ns CS Rise to LDAC Low Setup tLDACS 40 ns SCLK Fall to CS Fall Ignore tCSOL 10 ns CS Pulse Width Low for Shutdown tCSWL 40 ns CS Pulse Width High tCSWH 100 ns Note 1: Note 2: Note 3: Note 4: Note 5: Static performance tested at VDD = +5.0V (MAX5200/MAX5201) and at VDD = +3.0V (MAX5202/MAX5203). INL and DNL are guaranteed for outputs between 0.5V to (VDD - 0.5V). Guaranteed monotonic. VREF = 2.5V (MAX5200/MAX5201) and VREF = 1.5V (MAX5202/MAX5203). RL = , digital inputs are at VDD or DGND. _______________________________________________________________________________________ 5 MAX5200-MAX5203 ELECTRICAL CHARACTERISTICS--MAX5202/MAX5203 (continued) Typical Operating Characteristics (VDD = +5V, TA = +25C, unless otherwise noted.) INL (LSB) 0.8 0.7 0.6 0.5 0 25 50 8 0.50 4 0.25 0 0 -4 -0.25 -8 -0.50 -12 -0.75 -16 -1.00 75 85 0 10,000 20,000 30,000 40,000 50,000 60,000 70,000 MAX5200 toc03 0.75 0 10,000 20,000 30,000 40,000 50,000 60,000 70,000 TEMPERATURE (C) DAC CODE DAC CODE GAIN ERROR vs. TEMPERATURE OFFSET ERROR vs. TEMPERATURE HALF-SCALE OUTPUT SETTLING TIME (CODE FROM 4000H TO C000H) 0.08 0.30 OFFSET ERROR (mV) 0.06 0.04 0.02 0 -0.02 -0.04 MAX5200 toc06a 0.40 MAX5200 toc04 0.10 MAX5200 toc05 -40 -20 1.00 MAX5200 toc02 12 DNL (LSB) 0.9 0.20 LARGE SIGNAL (1V/div) 0.10 -0.10 SMALL SIGNAL (1mV/div) -0.20 -0.06 RLOAD = 10k CLOAD = 250pF -0.30 -0.08 -0.10 -0.40 -40 -20 0 20 40 60 80 -40 -20 TEMPERATURE (C) 0 20 40 60 80 40s/div TEMPERATURE (C) HALF-SCALE OUTPUT SETTLING TIME (CODE FROM C000H TO 4000H) OUTPUT NOISE DENSITY vs. FREQUENCY MAX5200 toc06b 700 LARGE SIGNAL (1V/div) SMALL SIGNAL (1mV/div) OUT 1V/div OUT 1mV/div VOLTAGE NOISE DENSITY (nV/Hz) DAC CODE = 8400 HEX RLOAD = 10k CLOAD = 250pF 600 500 400 300 200 100 0 40s/div 100 1k 10k FREQUENCY (Hz) 6 OUT 1V/div 0 MAX5200 toc07 SUPPLY CURRENT (mA) 16 MAX5200 toc01 1.0 DIFFERENTIAL NONLINEARITY vs. CODE INTEGRAL NONLINEARITY vs. CODE SUPPLY CURRENT vs. TEMPERATURE GAIN ERROR (%FSR) MAX5200-MAX5203 Low-Cost, Voltage-Output, 16-Bit DACs with Internal Reference in MAX _______________________________________________________________________________________ 100k OUT 1mV/div Low-Cost, Voltage-Output, 16-Bit DACs with Internal Reference in MAX SOURCE-CURRENT CAPABILITY CODE = FFFF HEX CODE = C000 HEX 2.5 2.0 CODE = 8000 HEX 1.5 4.0 3.5 OUTPUT VOLTAGE (V) 3.0 OUT (AC-COUPLED, 5mV/div) 2.5 2.0 CODE = 4000 HEX 1.5 1.0 1.0 0.5 0.5 0 CODE = 0000 HEX 0 10 20 30 40 0 SOURCE CURRENT (mA) 3 6 9 12 15 1s/div SINK CURRENT (mA) SHUTDOWN CURRENT vs. TEMPERATURE MAJOR-CARRY OUTPUT GLITCH (CODE FROM 7FFFH TO 8000H) MAX5200 toc11 1.00 MAX5200 toc12 0 0.75 OUT (AC-COUPLED, 5mV/div) SHUTDOWN CURRENT (A) OUTPUT VOLTAGE (V) 3.5 MAX5200 toc10 MAX5200 toc09 4.0 3.0 4.5 MAX5200 toc08 4.5 MAJOR-CARRY OUTPUT GLITCH (CODE FROM 8000H TO 7FFFH) SINK-CURRENT CAPABILITY 0.50 0.25 0 -0.25 -0.50 -0.75 -1.00 1s/div -40 -20 0 20 40 60 80 TEMPERATURE (C) _______________________________________________________________________________________ 7 MAX5200-MAX5203 Typical Operating Characteristics (continued) (VDD = +5V, TA = +25C, unless otherwise noted.) Low-Cost, Voltage-Output, 16-Bit DACs with Internal Reference in MAX MAX5200-MAX5203 Pin Description PIN NAME FUNCTION 1 CLR Reset DAC Active-Low Input. Pull CLR low to reset the DAC output to midscale output (8000 hex) for MAX5200/MAX5202 and to zero-scale output (0000 hex) for MAX5201/MAX5203. For normal operation, connect CLR to VDD. 2 REF Reference Voltage Output. Provides a +2.5V (MAX5200/MAX5201) or +1.5V (MAX5202/MAX5203) nominal output. For improved noise performance, bypass with a minimum 0.1F capacitor to AGND. 3 AGND Analog Ground Positive Supply Voltage. Bypass VDD to AGND with a 10F capacitor in parallel with a 0.1F capacitor. 4 VDD 5 OUT 6 CS 7 LDAC Load DAC Input 8 DIN Serial Data Input 9 SCLK Serial Clock Input. Duty cycle must be 40% to 60%. 10 DGND Digital Ground DAC Output Voltage Active-Low Chip-Select Input Detailed Description The MAX5200-MAX5203 serial 16-bit, voltage-output DACs are easily configured with a 3-wire serial interface. These devices offer full 16-bit performance with less than 20LSB integral linearity error and less than 1LSB differential linearity error, thus ensuring monotonic performance. Serial data transfer minimizes the number of package pins required. The MAX5200- MAX5203 include control-logic circuitry, a 16-bit data-in shift register, and a DAC register. In addition, these devices employ a precision-bandgap reference and trimmed internal resistors to produce a gain of 2V/V, maximizing the output voltage swing. The MAX5200-MAX5203 output is buffered and the fullscale output voltage is 2 VREF. The MAX5200-MAX5203 feature a hardware reset input (CLR) that, when pulled low, clears the DAC output to zero code 0000H (MAX5201/MAX5203) or resets the DAC output to midscale code 8000 hex (MAX5200/ MAX5202). For normal operation, connect CLR to VDD. Internal Reference The MAX5200/MAX5201 (+5V supply) include an internal reference of 2.5V while the MAX5202/MAX5203 (+3V supply) include an internal reference of 1.5V. The DAC output range is from 0 to 2 VREF. Do not drive external circuitry from this reference. To improve DAC output noise performance, bypass with a low leakage 0.1F minimum capacitor to AGND. 8 REF VDD BANDGAP REF MAX5200- MAX5203 16-BIT DAC OUT CLR 16-BIT DATA LATCH CS SCLK DIN LDAC CONTROL LOGIC SERIAL INPUT REGISTER AGND DGND Figure 1. MAX5200-MAX5203 Simplified Functional Diagram Digital Interface The MAX5200-MAX5203 digital interface is a standard 3-wire connection compatible with SPI/QSPI/ MICROWIRE and most DSP interfaces. All of the digital input pins (CS, SCLK, DIN, CLR, and LDAC) are TTL compatible. SCLK can accept clock frequencies as high as 10MHz for a +5V supply and 10MHz for a +3V or +3.3V supply. One of two methods can be used when interfacing and updating the MAX5200-MAX5203. The first requires three digital inputs: CS, DIN, and SCLK (Figure 2). The active-low chip-select input (CS) enables the serial _______________________________________________________________________________________ Low-Cost, Voltage-Output, 16-Bit DACs with Internal Reference in MAX MAX5200-MAX5203 tCP tCH SCLK tCL tCS1 tCSS tCSH tDH tDS CS tCS0 tCSWH D15 DIN D14 D0 NOTE: LDAC IS LOGIC LOW. Figure 2. 3-Wire Interface Timing Diagram data loading at the data input (DIN). Pull CS low and clock in each bit of the 16-bit digital word on the rising edge of the serial clock (SCLK). Two 8-bit bytes can be used, and do not require any additional time between them. Pulling CS high after loading the 16-bit word transfers that code into the DAC register and then updates the output. If CS is not kept low during the entire loading of the 16-bit word, data is corrupted. In this case, a new 16-bit word must be loaded. LDAC must be kept low at all times for the above instructions. An alternate method of interfacing and updating the MAX5200-MAX5203 can be done with a fourth digital input, the active-low load DAC (LDAC). LDAC allows the output to update asynchronously after CS goes high. It is useful when updating multiple MAX5200- MAX5203s synchronously when sharing a single LDAC and CS line. LDAC must be kept high at all times during the data-loading sequence and must only be asserted when CS is high. Asserting LDAC when CS is low can cause corrupted data. To operate the MAX5200-MAX5203 using LDAC, pull LDAC high, pull CS low, load the 16-bit word as described in the previous paragraph, and pull CS high again. Following these commands, the DAC output only updates when LDAC is asserted low (Figure 3). Shutdown Mode The low-power shutdown mode reduces supply current to typically 1A and a maximum of 10A. Shutdown mode is not activated through command words, as is common among D/A converters. These devices require careful manipulation of CS and SCLK (Figure 4). Shutting Down To shut down the MAX5200-MAX5203, change the state of SCLK (either a high to low or low to high transition can be used) and pulse two falling CS edges. In order to keep the device in shutdown mode, SCLK must not change state. SCLK must remain in the state it is in after the two CS pulses. Waking Up There are two methods to wake up the MAX5200- MAX5203. Pulse one falling CS edge or transition SCLK. It takes 50s typically from the CS falling edge or SCLK transition for the DAC to return to normal operation. Power-On Reset The MAX5200-MAX5203 have a power-on reset circuit to set the DAC's output to a known state when VDD is first applied. The MAX5200/MAX5202 reset to midscale (code 8000 hex) upon power-up. The MAX5201/MAX5203 reset to zero scale (code 0000 hex) upon power-up. This ensures that unwanted output voltages do not occur immediately following a system power-up, such as a loss of power. It is required to apply VDD first before any other inputs (DIN, SCLK, CLR, LDAC, and CS). _______________________________________________________________________________________ 9 MAX5200-MAX5203 Low-Cost, Voltage-Output, 16-Bit DACs with Internal Reference in MAX tCP tCH SCLK tCL tCS1 tCSS tCSH tDH tDS CS tCS0 tCSWH D15 DIN D14 D0 tLDACS tLDAC LDAC Figure 3. 4-Wire Interface Timing Diagram tCS0L SHUTDOWN WAKE-UP SCLK tCSWL CS tCSWH A. WAKING UP USING A THIRD FALLING EDGE ON CS. SHUTDOWN tCS0L WAKE-UP SCLK CS tCSWL tCSWH B. WAKING UP USING A TRANSITION ON SCLK. Figure 4. Shutdown Timing Applications Information Power-Supply and Bypassing Considerations Bypass the power supply with a 10F capacitor in parallel with a 0.1F capacitor to AGND. Minimize lead lengths to reduce lead inductance. If noise becomes an issue, use shielding and/or ferrite beads to increase isolation. 10 Output Buffer The MAX5200-MAX5203 include low-offset, low-noise buffers enabling the output to source 15mA or sink 5mA. The output buffer operates at a slew rate of 0.6V/s. With a 1/4 FS to 3/4 FS output transition, the buffer output typically settles to 1 LSB in less than 25s. The MAX5200-MAX5203 output buffers provide a low 0.2 typical output impedance. The MAX5200- MAX5203 buffer amplifiers typically produce 175nV/Hz noise at 10kHz. ______________________________________________________________________________________ Low-Cost, Voltage-Output, 16-Bit DACs with Internal Reference in MAX MAX5200-MAX5203 VDD 10F 0.1F MC68XXXX PCS0 MOSI SCLK CLR CS DIN SCLK LDAC +5V MAX5200- MAX5203 DGND OUT BIPOLAR OUT AGND REF MAX400 (VREF) -5V Figure 5. MAX5200-MAX5203 Typical Operating Circuit--Bipolar Output Table 1. Bipolar Code Table DAC LATCH CONTENTS MSB ANALOG OUTPUT, VOUT LSB 1111 1111 1111 1111 +VREF x (32,767 / 32,768) 1000 0000 0000 0001 +VREF x (1 / 32,768) 1000 0000 0000 0000 0V 0111 1111 1111 1111 -VREF x (1 / 32,768) 0000 0000 0000 0000 -VREF x (32,768 / 32,768) Bipolar Configuration The MAX5200-MAX5203 are designed for unipolar operation, but can be used in bipolar applications with an external amplifier and resistors. Figure 5 shows the MAX5200-MAX5203 configured for bipolar operation. The op amp is set for unity gain. Table 1 lists the offset binary code for this circuit. The output voltage range is VREF. Layout Considerations Digital and AC transient signals coupling to AGND can create noise at the output. Connect AGND to the highest quality ground available. Use proper grounding techniques, such as a multilayer board with a lowinductance ground plane. Wire-wrapped boards and sockets are not recommended. For optimum system performance, use printed circuit (PC) boards with separate analog and digital ground planes. Connect the two ground planes together at the low-impedance power-supply source. Connect DGND and AGND pins together at the IC. The best ground connection is achieved by connecting the DAC's DGND and AGND together, and then connecting that point to the system analog ground plane. If the DAC's DGND is connected to the system digital ground, digital noise can get through the DAC's analog portion. Chip Information TRANSISTOR COUNT: 8764 PROCESS: BiCMOS ______________________________________________________________________________________ 11 MAX5200-MAX5203 Low-Cost, Voltage-Output, 16-Bit DACs with Internal Reference in MAX Selector Guide INTEGRAL NONLINEARITY (LSB, MAX) SUPPLY VOLTAGE RANGE (V) REFERENCE INPUT RANGE (V) POWER-ON-RESET VALUE MAX5200AEUB 20 4.75 to 5.25 2.5 Midscale MAX5200ACUB 20 4.75 to 5.25 2.5 Midscale MAX5200BEUB 40 4.75 to 5.25 2.5 Midscale MAX5201AEUB 20 4.75 to 5.25 2.5 Zero MAX5201ACUB 20 4.75 to 5.25 2.5 Zero MAX5201BEUB 40 4.75 to 5.25 2.5 Zero MAX5202AEUB 20 2.7 to 3.6 1.5 Midscale MAX5202ACUB 20 2.7 to 3.6 1.5 Midscale MAX5202BEUB 40 2.7 to 3.6 1.5 Midscale MAX5203AEUB 20 2.7 to 3.6 1.5 Zero MAX5203ACUB 20 2.7 to 3.6 1.5 Zero MAX5203BEUB 40 2.7 to 3.6 1.5 Zero PART 12 ______________________________________________________________________________________ Low-Cost, Voltage-Output, 16-Bit DACs with Internal Reference in MAX 10LUMAX.EPS e 4X S 10 10 H 0 0.500.1 0.60.1 1 1 0.60.1 BOTTOM VIEW TOP VIEW D2 MILLIMETERS INCHES MAX DIM MIN 0.043 A 0.006 A1 0.002 A2 0.030 0.037 0.120 D1 0.116 0.118 D2 0.114 E1 0.116 0.120 0.118 0.114 E2 0.199 0.187 H 0.0157 0.0275 L L1 0.037 REF b 0.007 0.0106 e 0.0197 BSC c 0.0035 0.0078 0.0196 REF S 0 6 MAX MIN 1.10 0.05 0.15 0.75 0.95 2.95 3.05 2.89 3.00 2.95 3.05 2.89 3.00 4.75 5.05 0.40 0.70 0.940 REF 0.270 0.177 0.500 BSC 0.200 0.090 0.498 REF 0 6 E2 GAGE PLANE A2 c A b A1 E1 D1 L L1 FRONT VIEW SIDE VIEW PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE, 10L uMAX/uSOP APPROVAL DOCUMENT CONTROL NO. 21-0061 REV. I 1 1 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13 (c) 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. MAX5200-MAX5203 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)