September 1996
NDT3055L
N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description Features
_______________________________________________________________________________________________
Absolute Maximum Ratings TA = 25°C unless otherwise noted
SymbolParameter NDT3055LUnits
VDSS Drain-Source Voltage 60 V
VGSS Gate-Source Voltage - Continuous ±20 V
IDDrain Current - Continuous (Note 1a) ±3.7A
- Pulsed±25
PDMaximum Power Dissipation (Note 1a) 3W
(Note 1b) 1.3
(Note 1c) 1.1
TJ,TSTG Operating and Storage Temperature Range -65 to 150 °C
THERMAL CHARACTERISTICS
RθJA Thermal Resistance, Junction-to-Ambient (Note 1a) 42 °C/W
RθJC Thermal Resistance, Junction-to-Case (Note 1) 12 °C/W
* Order option J23Z for cropped center drain lead.
NDT3055L Rev. D2
Power SOT logic level N-Channel enhancement
mode field effect transistors are produced using
National's proprietary, high cell density, DMOS
technology. This very high density process is
especially tailored to minimize on-state resistance
and provide superior switching performance. These
devices are particularly suited for low voltage
applications such as DC motor control and DC/DC
conversion where fast switching, low in-line power
loss, and resistance to transients are needed.
3.7A, 60V. RDS(ON) = 0.12Ω @ VGS = 4.5V.
Low drive requirements allowing operation
directly from logic drivers. VGS(TH) < 2.0V.
High density cell design for extremely low RDS(ON).
High power and current handling capability in a
widely used surface mount package.
D
DS
G
D
S
G
N
Electrical Characteristics (TA = 25°C unless otherwise noted)
SymbolParameter Conditions Min TypMax Units
OFF CHARACTERISTICS
BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA 60 V
IDSS Zero Gate Voltage Drain CurrentVDS = 60 V, VGS = 0 V 1µA
TJ = 125°C 50 µA
IGSSF Gate - Body Leakage, ForwardVGS = 20 V, VDS = 0 V100 nA
IGSSR Gate - Body Leakage, Reverse VGS = -20 V, VDS= 0 V-100 nA
ON CHARACTERISTICS (Note 2)
VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250 µA 11.7 2 V
TJ = 125°C 0.61.31.6
RDS(ON) Static Drain-Source On-Resistance VGS = 4.5 V, ID = 3.7 A 0.1050.12Ω
TJ = 125°C 0.170.24
VGS = 10 V, ID = 3.9 A 0.1
ID(on) On-State Drain CurrentVGS = 5 V, VDS = 10 V10 A
gFS Forward Transconductance VDS = 5 V, ID = 3.7 A 6S
DYNAMIC CHARACTERISTICS
Ciss Input Capacitance VDS = 25 V, VGS = 0 V,
f = 1.0 MHz
435 pF
Coss Output Capacitance 120 pF
Crss Reverse Transfer Capacitance 30 pF
SWITCHING CHARACTERISTICS (Note 2)
tD(on) Turn - On Delay Time VDD = 25 V, ID = 1 A,
VGS = 10 V, RGEN = 6 Ω820 ns
trTurn - On Rise Time 420 ns
tD(offf) Turn - Off Delay Time 24 50 ns
tfTurn - Off Fall Time 720 ns
QgTotal Gate Charge VDS = 40 V,
ID = 3.7 A, VGS = 10 V
13.520 nC
Qgs Gate-Source Charge 1.5 3 nC
Qgd Gate-Drain Charge 4 8 nC
NDT3055L Rev. D2
Electrical Characteristics (TA = 25°C unless otherwise noted)
SymbolParameter Conditions Min TypMax Units
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
ISMaximum Continuos Source-Drain Diode Forward Current2.5A
VSD Source-Drain Diode Forward Voltage VGS = 0 V, IS = 1.5 A (Note 2) 0.861.2V
Notes:
1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the
drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design.
PD(t)=TJ
−
TA
RθJA
(
t
)=TJ
−
TA
RθJC
+
RθCA
(
t
)=ID
2(t)×RDS(ON)@TJ
Typical RθJA using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
a. 42oC/W when mounted on a 1 in2 pad of 2oz copper.
b. 95oC/W when mounted on a 0.066 in2 pad of 2oz copper.
c. 110oC/W when mounted on a 0.0123 in2 pad of 2oz copper.
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
NDT3055L Rev. D2
1a 1b 1c
NDT3055L Rev. D2
Figure 1. On-Region Characteristics. Figure 2. On-Resistance Variation with
Gate Voltage and Drain Current.
Figure 3. On-Resistance Variation
with Temperature.
Figure 4. On-Resistance Variation with
Drain Current and Temperature.
Figure 6. Gate Threshold Variation
with Temperature.
Figure 5. Drain Current Variation with
Gate Voltage and Temperature.
0 3 6 9 12 15
0.5
1
1.5
2
2.5
I , DRAIN CURRENT (A)
DRAIN-SOURCE ON-RESISTANCE
V = 3.0V
GS
D
R , NORMALIZED
DS(on)
4.0V
6.0V
10V
3.5V
4.5V
5.0V
-50 -25 025 50 75 100 125 150
0.6
0.8
1
1.2
1.4
1.6
1.8
T , JUNCTION TEMPERATURE (°C)
DRAIN-SOURCE ON-RESISTANCE
J
R , NORMALIZED
DS(ON)
I = 3.7A
V = 4.5V
D
GS
0246810
0
0.5
1
1.5
2
2.5
3
I , DRAIN CURRENT (A)
DRAIN-SOURCE ON-RESISTANCE
T = 125°C
J
25°C
-55°C
D
V = 4.5 V
GS
R , NORMALIZED
DS(on)
11.5 22.5 33.5 4
0
2
4
6
8
10
V , GATE TO SOURCE VOLTAGE (V)
I , DRAIN CURRENT (A)
25°C
125°C
V = 15V
DS
GS
D
T = -55°C
J
-50 -25 0 25 50 75 100 125 150
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
T , JUNCTION TEMPERATURE (°C)
GATE-SOURCE THRESHOLD VOLTAGE (V)
J
I = 250µA
D
V = V
DS GS
V , NORMALIZED
th
0 1 2 3 4 5
0
5
10
15
20
V , DRAIN-SOURCE VOLTAGE (V)
I , DRAIN-SOURCE CURRENT (A)
6.0V 5.5V
4.5V
V = 10V
GS
DS
D
5.0V
2.5V
3.0V
4.0V
Typical Electrical Characteristics (continued)
NDT3055L Rev. D2
Figure 7. Breakdown Voltage
Variation with Temperature.
Figure 8. Body Diode Forward
Voltage Variation with Current
and Temperature.
Figure 9. Capacitance Characteristics. Figure 10. Gate Charge Characteristics.
Typical Electrical Characteristics (continued)
-50 -25 025 50 75 100 125 150
0.9
0.95
1
1.05
1.1
1.15
T , JUNCTION TEMPERATURE (°C)
DRAIN-SOURCE BREAKDOWN VOLTAGE (V)
I = 250µA
D
J
BV , NORMALIZED
DSS
0.4 0.6 0.8 11.2 1.4
0.1
0.2
0.3
0.5
1
2
3
5
10
V , BODY DIODE FORWARD VOLTAGE (V)
I , REVERSE DRAIN CURRENT (A)
T = 125°C
J
25°C
-55°C
V = 0V
GS
SD
S
0246810 12 14
0
2
4
6
8
10
Q , GATE CHARGE (nC)
V , GATE-SOURCE VOLTAGE (V)
I = 3.7A
D
g
GS
V = 10V
DS
40V
20V
0.1 0.2 0.5 1 2 5 10 20 50
10
20
30
50
100
200
300
500
1000
V , DRAIN TO SOURCE VOLTAGE (V)
CAPACITANCE (pF)
DS
C
iss
C
oss
C
rss
f = 1 MHz
V = 0V
GS
G
D
S
VDD
RL
V
V
IN
OUT
VGS
DUT
RGEN
Figure 11. Switching Test Circuit. Figure 12. Switching Waveforms.
10%
50%
90%
10%
90%
90%
50%
VIN
VOUT
on off
d(off) f
r
d(on)
t t
tt
t
t
INVERTED
10%
NDT3055L Rev. D2
0 2 4 6 8 10
0
2
4
6
8
10
I , DRAIN CURRENT (A)
g , TRANSCONDUCTANCE (SIEMENS)
T = -55°C
J
25°C
D
FS
V = 15V
DS
125°C
0.1 0.2 0.5 1 2 5 10 20 60 100
0.01
0.03
0.1
0.3
1
3
10
40
V , DRAIN-SOURCE VOLTAGE (V)
I , DRAIN CURRENT (A)
DS
D
10ms
100ms
10s
DC
1s
RDS(ON) Limit
100us
1ms
V = 4.5V
SINGLE PULSE
R = 42 C/W
T = 25°C
GS
A
θJA o
Figure 13. Transconductance Variation
with Drain Current and Temperature. Figure 14. Maximum Safe Operating Area.
Typical Electrical Characteristics (continued)
Figure 15. Transient Thermal Response Curve.
Note: Thermal characterization performed using the conditions described in note 1c. Transient thermal
response will change depending on the circuit board design.
0.0001 0.001 0.01 0.1 110 100 300
0.001
0.002
0.005
0.01
0.02
0.05
0.1
0.2
0.5
1
t , TIME (sec)
TRANSIENT THERMAL RESISTANCE
r(t), NORMALIZED EFFECTIVE
1
Single Pulse
D = 0.5
0.1
0.05
0.02
0.01
0.2
Duty Cycle, D = t / t
12
R (t) = r(t) * R
R = See Note 1 c
θJA
θJA
θJA
T - T = P * R (t)
θJA
A
J
P(pk)
t
1 t
2