1
®
FN9220.1
ISL9012
Dual LDO with Low Noise, Low IQ, and
High PSRR
ISL9012 is a high performance dual LDO capable of
sourcing 150mA current from channel 1 and 300mA from
channel 2. The device has a low standby current and high-
PSRR and is stable with output capacitance of 1µF to 10µF
with ESR of up to 200mΩ.
The device integrates a Power-On-Reset (POR) function for
the VO2 output. The POR delay for VO2 can be externally
programmed by connecting a timing capacitor to the CPOR
pin. A reference bypass pin is also provided for connecting a
noise-filtering capacitor for low noise and high PSRR
applications.
The quiescent current is typically only 45µA with both LDO’s
enabled and active. Separate enable pins control each
individual LDO output. When both enable pins are low, the
device is in shutdown, typically drawing less than 0.1µA.
Several combinations of voltage outputs are standard.
Others are available on request. Output voltage options for
each LDO range from 1.2V to 3.6V.
Pinout
ISL9012
10-PIN 3X3 DFN
TOP VIEW
Features
• Integrates two high performance LDOs
- VO1 - 150mA output
- VO2 - 300mA output
• Excellent transient response to large current steps
• Excellent load regulation:
• <1% voltage change across full range of load current
• High PSRR: 70dB @ 1kHz
• Wide input voltage capability: 2.3V - 6.5V
• Extremely low quiescent current: 45µA (both LDOs on)
• Low dropout voltage: typically 120mV @ 150mA
• Low output noise: typically 30µVrms @ 100µA(1.5V)
• Stable with 1-10µF ceramic capacitors
• Separate enable pins for each LDO
• POR output, with adjustable delay time indicates when the
VO2 output is good
• Soft-start to limit input current surge during enable
• Current limit and overheat protection
• ±1.8% accuracy over all operating conditions
• Tiny 10 Ld 3x3mm DFN package
• -40°C to +85°C operating temperature range
• Pin compatible with Micrel MIC2212
• Pb-free plus anneal available (RoHS compliant)
Applications
• PDAs, Cell Phones and Smart Phones
• Portable Instruments, MP3 Players
• Handheld Devices including Medical Handhelds
VIN
EN1
EN2
CBYP
CPOR
VO1
VO2
POR
NC
GND
2
3
4
1
5
9
8
7
10
6
Data Sheet December 21, 2005
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2005. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
2FN9220.1
December 21, 2005
Ordering Information
PART NUMBER
(Notes 1, 2, 3) PART MARKING VO1 VOLTAGE VO2 VOLTAGE TEMP RANGE (°C)
PACKAGE
(Pb-free) PKG. DWG. #
ISL9012IRNNZ DCTA 3.3V 3.3V -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9012IRNJZ DAPA 3.3V 2.8V -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9012IRNFZ DARA 3.3V 2.5V -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9012IRMNZ DCYA 3.0V 3.3V -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9012IRMMZ DAAK 3.0V 3.0V -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9012IRMGZ DCBC 3.0V 2.7V -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9012IRLLZ DAAJ 2.9V 2.9V -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9012IRKKZ DASA 2.85V 2.85V -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9012IRKJZ DATA 2.85V 2.8V -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9012IRKFZ DAVA 2.85V 2.5V -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9012IRKCZ DAAB 2.85V 1.8V -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9012IRJNZ DCBD 2.8V 3.3V -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9012IRJMZ DAAH 2.8V 3.0V -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9012IRJRZ DAAG 2.8V 2.6V -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9012IRJCZ DAAF 2.8V 1.8V -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9012IRJBZ DAWA 2.8V 1.5V -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9012IRGCZ DAAE 2.7V 1.8V -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9012IRFJZ DAYA 2.5V 2.8V -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9012IRFDZ DCBK 2.5V 2.0V -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9012IRFCZ DCBL 2.5V 2.0V -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9012IRPLZ DAAD 1.85V 2.9V -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9012IRCJZ DCBN 1.8V 2.8V -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9012IRCCZ DCBP 1.8V 1.8V -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9012IRBJZ DAAC 1.5V 2.8V -40 to +85 10 Ld 3x3 DFN L10.3x3C
NOTES:
1. Add -T to part number for tape and reel.
2. For other output voltages, contact Intersil Marketing.
3. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
ISL9012
3FN9220.1
December 21, 2005
Absolute Maximum Ratings Thermal Information
Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.1V
All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to (VIN+0.3)V
Recommended Operating Conditions
Ambient Temperature Range (TA) . . . . . . . . . . . . . . .-40°C to +85°C
Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 to 6.5V
Thermal Resistance (Notes 1, 2) θJA (°C/W) θJC (°C/W)
3x3 DFN Package . . . . . . . . . . . . . . . . 50 10
Junction Temperature Range . . . . . . . . . . . . . . . . .-40°C to +125°C
Operating Temperature Range . . . . . . . . . . . . . . . . .-40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2. θJC, “case temperature” location is at the center of the exposed metal pad on the package underside. See Tech Brief TB379.
Electrical Specifications Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature
range of the device as follows:
TA = -40°C to +85°C; VIN = (VO+0.5V) to 6.5V with a minimum VIN of 2.3V; CIN = 1µF; CO = 1µF;
CBYP = 0.01µF; CPOR = 0.01µF
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
DC CHARACTERISTICS
Supply Voltage VIN 2.3 6.5 V
Ground Current Quiescent condition: IO1 = 0µA; IO2 = 0µA
IDD1 One LDO active 25 40 µA
IDD2 Both LDO active 45 60 µA
Shutdown Current IDDS @25°C 0.1 1.0 µA
UVLO Threshold VUV+ 1.9 2.1 2.3 V
VUV- 1.6 1.8 2.0 V
Regulation Voltage Accuracy Variation from nominal voltage output, VIN = VO+0.5 to 5.5V,
TJ= -40°C to 125°C
-1.8 +1.8 %
Line Regulation VIN = (VOUT + 1.0V relative to highest output voltage) to 5.5V -0.2 0 0.2 %/V
Load Regulation IOUT = 100µA to 150mA (VO1 and VO2) 0.1 0.7 %
IOUT = 100µA to 300mA (VO2) 1.0 %
Maximum Output Current IMAX VO1: Continuous 150 mA
VO2: Continuous 300 mA
Internal Current Limit ILIM 350 475 600 mA
Dropout Voltage (Note 4) VDO1 IO = 150mA; VO > 2.1V (VO1) 125 200 mV
VDO2 IO = 300mA; VO < 2.5V (VO2) 300 500 mV
VDO3 IO = 300mA; 2.5V ≤ VO ≤ 2.8V (VO2) 250 400 mV
VDO4 IO = 300mA; VO > 2.8V (VO2) 200 325 mV
Thermal Shutdown Temperature TSD+ 145 °C
TSD- 110 °C
AC CHARACTERISTICS
Ripple Rejection IO = 10mA, VIN = 2.8V(min), VO = 1.8V, CBYP = 0.1µF
@ 1kHz 70 dB
@ 10kHz 55 dB
@ 100kHz 40 dB
Output Noise Voltage IO = 100µA, VO = 1.5V, TA = 25°C, CBYP = 0.1µF
BW = 10Hz to 100kHz (Note 3)
30 µVrms
ISL9012
4FN9220.1
December 21, 2005
DEVICE START-UP CHARACTERISTICS
Device Enable TIme TEN Time from assertion of the ENx pin to when the output voltage
reaches 95% of the VO(nom)
250 500 µs
LDO Soft-start Ramp Rate TSSR Slope of linear portion of LDO output voltage ramp during start-
up
30 60 µs/V
EN1, EN2 PIN CHARACTERISTICS
Input Low Voltage VIL -0.3 0.5 V
Input High Voltage VIH 1.4 VIN+0.3 V
Input Leakage Current IIL, IIH 0.1 µA
Pin Capacitance CPIN Informative 5 pF
POR PIN CHARACTERISTICS
POR Thresholds VPOR+ As a percentage of nominal output voltage 91 94 97 %
VPOR- 87 90 93 %
POR Delay TPLH CPOR = 0.01µF 100 200 300 ms
TPHL 25 µs
POR Pin Output Low Voltage VOL @IOL = 1.0mA 0.2 V
POR Pin Internal Pull-up
Resistance
RPOR 78 100 130 kΩ
NOTES:
3. Guaranteed by design and characterization.
4. VOx = 0.98 * VOx(NOM); Valid for VOx greater than 1.85V.
Electrical Specifications Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature
range of the device as follows:
TA = -40°C to +85°C; VIN = (VO+0.5V) to 6.5V with a minimum VIN of 2.3V; CIN = 1µF; CO = 1µF;
CBYP = 0.01µF; CPOR = 0.01µF (Continued)
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
VPOR+ VPOR+
VPOR-
<tPHL
tPLH tPHL
VO2
POR
EN2
TEN
VPOR-
FIGURE 1. TIMING PARAMETER DEFINITION
ISL9012
5FN9220.1
December 21, 2005
Typical Performance Curves
FIGURE 2. OUTPUT VOLTAGE vs INPUT VOLTAGE (3.3V
OUTPUT)
FIGURE 3. OUTPUT VOLTAGE CHANGE vs LOAD CURRENT
FIGURE 4. OUTPUT VOLTAGE CHANGE vs TEMPERATURE FIGURE 5. OUTPUT VOLTAGE vs INPUT VOLTAGE
(VO1 = 3.3V)
FIGURE 6. OUTPUT VOLTAGE vs INPUT VOLTAGE
(VO2 = 2.8V)
FIGURE 7. VO1 DROPOUT VOLTAGE vs LOAD CURRENT
OUTPUT VOLTAGE, VO (%)
INPUT VOLTAGE (V)
-0.6
-0.2
0.2
0.6
-0.8
3.8 4.2 6.25.8 6.63.4 4.6 5.0 5.4
-0.4
0.0
0.4
0.8
VO = 3.3V
85°C
-40°C
25°C
ILOAD = 0mA
0.04
0.06
-0.06
-0.10 100 200 300 4000
LOAD CURRENT - IO (mA)
OUTPUT VOLTAGE CHANGE (%)
-0.02
0.00
0.02
0.08
0.10
-0.04
-0.08
50 150 250 350
VIN = 3.8V
VO = 3.3V
85°C
-40°C
25°C
0.04
0.06
-0.06
-0.10
-10 20 50 110-40
TEMPERATURE (°C)
OUTPUT VOLTAGE CHANGE (%)
-0.02
0.00
0.02
0.08
0.10
-0.04
-0.08
-25 5 35 8065 95 125
VIN = 3.8V
VO = 3.3V
ILOAD = 0mA
OUTPUT VOLTAGE, VO (V)
INPUT VOLTAGE (V)
3.0
3.1
3.2
3.3
3.4
2.9
2.8 3.1 3.6 4.1 4.6 5.1 6.15.6
IO = 150mA
IO = 0mA
VO1 = 3.3V
6.5
2.5
2.6
2.7
2.8
2.9
2.4
2.3 2.63.13.64.14.65.1 6.1
INPUT VOLTAGE (V)
OUTPUT VOLTAGE, VO (V)
5.6
IO = 0mA
IO = 300mA
VO2 = 2.8V
IO = 150mA
6.5
200
250
300
350
150
100
50
0
50 100 150 200 250 300 350 4000
OUTPUT LOAD (mA)
DROPOUT VOLTAGE, VDO (mV)
VO2 = 2.8V
VO1 = 3.3V
ISL9012
6FN9220.1
December 21, 2005
FIGURE 8. VO1 DROPOUT VOLTAGE vs LOAD CURRENT FIGURE 9. GROUND CURRENT vs INPUT VOLTAGE
FIGURE 10. GROUND CURRENT vs LOAD FIGURE 11. GROUND CURRENT vs TEMPERATURE
FIGURE 12. POWER-UP/POWER-DOWN FIGURE 13. POWER-UP/POWER-DOWN WITH POR SIGNALS
Typical Performance Curves (Continued)
100
125
150
175
75
50
25
0
25 50 75 100 125 150 175 2000
OUTPUT LOAD (mA)
DROPOUT VOLTAGE, VDO (mV)
VO1 = 3.3V
85°C25°C-40°C
30
35
40
45
55
25 4.0 5.0 6.5
INPUT VOLTAGE (V)
GROUND CURRENT (µA)
50
3.0 3.5 4.58 5.5 6.0
IO(BOTH CHANNELS) = 0µA
VO1 = 3.3V
VO2 = 2.8V
-40°C
25°C
125°C
200
160
100
20
0
50 100 150 200 250 4000
LOAD CURRENT (mA)
GROUND CURRENT (µA)
350300
VO1 = 3.3V
VIN = 3.8V
VO2 = 2.8V
40
60
80
120
140
180
85°C
-40°C
25°C
35
25
-10 20 50 110-40
TEMPERATURE (°C)
GROUND CURRENT (µA)
45
50
55
40
30
-25 5 35 8065 95 125
VIN = 3.8V
VO = 3.3V
ILOAD = 0µA
BOTH OUTPUTS ON
2
3
4
5
1
0
1234567 10
TIME (s)
VOLTAGE (V)
89
VO2
VO1
VIN
0
VO1 = 3.3V
VO2 = 2.8V
IL1 = 150mA
IL2 = 300mA
1.5
2.0
2.5
3.0
1.0
0.5
0.5 1.0 1.5 2.0 2.5 3.0 3.5 5.00
TIME (s)
VOLTAGE (V)
4.0 4.5
VO-1
POR
VO-2
0
3.5 VO1 = 3.3V
VO2 = 2.8V
IL1 = 150mA
IL2 = 300mA
CPOR = 0.1µF
ISL9012
7FN9220.1
December 21, 2005
FIGURE 14. TURN ON/TURN OFF RESPONSE FIGURE 15. LINE TRANSIENT RESPONSE, 3.3V OUTPUT
FIGURE 16. LINE TRANSIENT RESPONSE, 2.8V OUTPUT FIGURE 17. LOAD TRANSIENT RESPONSE
FIGURE 18. PSRR vs FREQUENCY FIGURE 19. SPECTRAL NOISE DENSITY vs FREQUENCY
Typical Performance Curves (Continued)
1
3
0
2
0
100 200 300 400 500 600 700 8000
TIME (µs)
VO1 (V)VEN (V)
5
VO1 = 3.3V
VIN = 5.0V
IL1 = 150mA
CL1, CL2 = 1µF
CBYP = 0.01µF
900 1000
VO2 (10mV/DIV)
IL2 = 300mA
VO2 = 2.8V
400µs/DIV
VO = 3.3V
ILOAD = 150mA
3.6V
4.3V
10mV/DIV
CLOAD = 1µF
CBYP = 0.01µF
400µs/DIV
VO = 2.8V
ILOAD = 300mA
3.5V
4.2V
10mV/DIV
CLOAD = 1µF
CBYP = 0.01µF
100µs/DIV
VO (25mV/DIV)
ILOAD
300mA
100µA
VIN = 2.8V
VO = 1.8V
0.1 1 10 100 1000
FREQUENCY (kHz)
0
10
20
30
40
50
60
70
80
90
100
PSRR (dB)
VIN = 3.6V
VO = 1.8V
IO = 10mA
CBYP = 0.01µF
CLOAD = 1µF
SPECTRAL NOISE DENSITY (nV/√Hz)
1000
100
10
1
0.1
10 100 1K 10K 100K 1M
FREQUENCY (Hz)
VIN = 3.6V
VO = 1.8V
ILOAD = 10mA
CBYP = 0.01µF
CIN = 1µF
CLOAD = 1µF
ISL9012
8FN9220.1
December 21, 2005
Pin Description
Typical Application
PIN #
PIN
NAME TYPE DESCRIPTION
1 VIN Analog I/O Supply Voltage / LDO Input:
Connect a 1µF capacitor to GND.
2 EN1 Low Voltage Compatible
CMOS Input
LDO-1 Enable.
3 EN2 Low Voltage Compatible
CMOS Input
LDO-2 Enable.
4 CBYP Analog I/O Reference Bypass Capacitor Pin:
Optionally connect capacitor of value 0.01µF to 1µF between this pin and GND to tune in the
desired noise and PSRR performance.
5 CPOR Analog I/O POR Delay Setting Capacitor Pin:
Connect a capacitor between this pin and GND to delay the POR output release after LDO-2
output reaches 94% of its specified voltage level (200ms delay per 0.01µF).
6 GND Ground GND is the connection to system ground. Connect to PCB Ground plane.
7 NC NC No Connection.
8POR
Open Drain Output (1mA) Open-drain POR Output for LDO-2 (active-low).
9VO2
Analog I/O LDO-2 Output:
Connect capacitor of value 1µF to 10µF to GND (1µF recommended).
10 VO1 Analog I/O LDO-1 Output:
Connect capacitor of value 1µF to 10µF to GND (1µF recommended).
C1, C4, C5: 1µF X5R ceramic capacitor
C2: 0.01µF X5R ceramic capacitor
ISL9012
VIN
EN1
EN2
CBYP
CPOR
VO1
VO2
POR
NC
GND
10
9
8
7
6
1
2
3
4
5
VIN (2.3-6.5V)
Enable 1
Enable 2
Vout 1
Vout 2
RESET
C1 C2 C3 C4 C5
C3: 0.01µF X5R ceramic capacitor
OFF
ON
OFF
ON
(200ms delay, C3=0.01µF)
Vout2 too low
Vout 2 OK
R1
R1: 100kΩ resistor, 5%
ISL9012
9FN9220.1
December 21, 2005
Block Diagram
Functional Description
The ISL9012 contains all circuitry required to implement two
high performance LDO’s. High performance is achieved
through a circuit that delivers fast transient response to
varying load conditions. In a quiescent condition, the
ISL9012 adjusts its biasing to achieve the lowest standby
current consumption.
The device also integrates current limit protection, smart
thermal shutdown protection, staged turn-on and soft-start.
Smart Thermal shutdown protects the device against
overheating. Staged turn-on and soft-start minimize start-up
input current surges without causing excessive device turn-
on time.
Power Control
The ISL9012 has two separate enable pins, EN1 and EN2,
to individually control power to each of the LDO outputs.
When both EN1 and EN2 are low, the device is in shutdown
mode. During this condition, all on-chip circuits are off, and
the device draws minimum current, typically less than 0.1µA.
When one or both of the enable pins are asserted, the
device first polls the output of the UVLO detector to ensure
that VIN voltage is at least about 2.1V. Once verified, the
device initiates a start-up sequence. During the start-up
sequence, trim settings are first read and latched. Then,
sequentially, the bandgap, reference voltage and current
generation circuitry power up. Once the references are
stable, a fast-start circuit quickly charges the external
reference bypass capacitor (connected to the CBYP pin) to
the proper operating voltage. After the bypass capacitor has
been charged, the LDO’s power up.
If EN1 is brought high, and EN2 is goes high before the VO1
output stablizes, the ISL9012 delays the VO2 turn-on until
the VO1 output reaches its target level. This minimizes input
current surge due to concurrent turn-on.
LDO
ERROR
AMPLIFIER
IS2
1V
QEN2
LDO-2
LDO-1
POR
COMPARATOR
VOK2
POR
VREF
TRIM
VIN
VO1
VO2
POR
CPORCBYPGND
EN2
EN1 CONTROL
LOGIC
POR
DELAY
VOLTAGE
REFERENCE
GENERATOR
BANDGAP AND
TEMPERATURE
SENSOR
UVLO
VOK2
1.00V
0.94V
0.90V
IS1
IS2
QEN1
QEN2
VO2
~1.0V
ISL9012
10 FN9220.1
December 21, 2005
If EN2 is brought high, and EN1 goes high before the VO2
output stablizes, the ISL9012 delays the VO1 turn-on until
the VO2 output reaches its target level.
If both EN1 and EN2 are high, the VO1 output has priority,
and is always powered up first.
During operation, whenever the VIN voltage drops below
about 1.8V, the ISL9012 immediately disables both LDO
outputs. When VIN rises back above 2.1V, the device re-
initiates its start-up sequence and LDO operation will
resume automatically.
Reference Generation
The reference generation circuitry includes a trimmed
bandgap, a trimmed voltage reference divider, a trimmed
current reference generator, and an RC noise filter. The filter
includes the external capacitor connected to the CBYP pin.
A 0.01µF capacitor connected CBYP implements a 100Hz
lowpass filter, and is recommended for most high
performance applications. For the lowest noise application, a
0.1µF or greater CBYP capacitor should be used. This filters
the reference noise to below the 10Hz – 1kHz frequency
band, which is crucial in many noise-sensitive applications.
The bandgap generates a zero temperature coefficient (TC)
voltage for the reference divider. The reference divider
provides the regulation reference, POR detection thresholds,
and other voltage references required for current generation
and over-temperature detection.
The current generator outputs references required for
adaptive biasing as well as references for LDO output
current limit and thermal shutdown determination.
LDO Regulation and Programmable Output Divider
The LDO Regulator is implemented with a high-gain
operational amplifier driving a PMOS pass transistor. The
design of the ISL9012 provides a regulator that has low
quiescent current, fast transient response, and overall
stability across all operating and load current conditions.
LDO stability is guaranteed for a 1µF to 10µF output
capacitor that has a tolerance better than 20% and ESR less
than 200mΩ. The design is performance-optimized for a 1µF
capacitor. Unless limited by the application, use of an output
capacitor value above 4.7µF is not recommended as LDO
performance improvement is minimal.
Soft-start circuitry integrated into each LDO limits the initial
ramp-up rate to about 30µs/V to minimize current surge. The
ISL9012 provides short-circuit protection by limiting the
output current to about 475mA.
Each LDO uses an independently trimmed 1V reference. An
internal resistor divider drops the LDO output voltage down
to 1V. This is compared to the 1V reference for regulation.
The resistor division ratio is programmed in the factory to
one of the following output voltages: 1.5V, 1.8V, 1.85, 2.5V,
2.6, 2.7, 2.8V, 2.85V, 2.9, 3.0, and 3.3V.
Power On Reset Generation
LDO-2 has a Power-on Reset signal generation circuit which
outputs to the POR pin. The POR signal is generated as
follows:
A POR comparator continuously monitors the voltage of the
LDO-2 output. The LDO enters a power-good state when the
output voltage is above 94% of the expected output voltage
for a period exceeding the LDO PGOOD entry delay time. In
the power-good state, the open-drain POR output is in a
high-impedance state. An external resistor can be added
between the POR output and either LDO output or the input
voltage, VIN.
The power-good state is exited when the LDO-2 output falls
below 90% of the expected output voltage for a period longer
than the PGOOD exit delay time. While power-good is false,
the ISL9012 pulls the respective POR pin low.
The PGOOD entry and exit delays are determined by the
value of the external capacitor connected to the CPOR pin.
For a 0.01µF capacitor, the entry and exit delays are 200ms
and 25µs respectively. Larger or smaller capacitor values will
yield proportionately longer or shorter delay times. The POR
exit delay should never be allowed to be less than 10µs to
ensure sufficient immunity against transient induced false
POR triggering.
Overheat Detection
The bandgap outputs a proportional-to-temperature current
that is indicative of the temperature of the silicon. This
current is compared with references to determine if the
device is in danger of damage due to overheating. When the
die temperature reaches about 145°C, one or both of the
LDO’s momentarily shut down until the die cools sufficiently.
In the overheat condition, only the LDO sourcing more than
50mA will be shut off. This does not affect the operation of
the other LDO. If both LDOs source more than 50mA and an
overheat condition occurs, both LDO outputs are disabled.
Once the die temperature falls back below about 110°C, the
disabled LDO(s) are re-enabled and soft-start automatically
takes place.
ISL9012
11
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN9220.1
December 21, 2005
ISL9012
Dual Flat No-Lead Plastic Package (DFN)
//
NX (b)
SECTION "C-C"
FOR ODD TERMINAL/SIDE
e
CC
5
C
L
TERMINAL TIP
(A1)
BOTTOM VIEW
A
6
AREA
INDEX
C
C
0.10
0.08
SIDE VIEW
0.15
2X
E
A
B
C0.15
D
TOP
VIEW
CB
2X
6
8
AREA
INDEX
NX L
E2
E2/2
REF.
e
N
(Nd-1)Xe
(DATUM A)
(DATUM B)
5
0.10
87
D2
BAC
N-1
12
PLANE
SEATING
C
A
A3
NX b
D2/2
NX k
9L
M
L10.3x3C
10 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE
SYMBOL
MILLIMETERS
NOTESMIN NOMINAL MAX
A 0.80 0.90 1.00 -
A1 - - 0.05 -
A3 0.20 REF -
b 0.18 0.25 0.30 5, 8
D 3.00 BSC -
D2 2.23 2.38 2.48 7, 8
E 3.00 BSC -
E2 1.49 1.64 1.74 7, 8
e 0.50 BSC -
k0.20 - - -
L 0.30 0.40 0.50 8
N102
Nd 5 3
Rev. 0 3/05
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd refers to the number of terminals on D.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
9. COMPLIANT TO JEDEC MO-229-WEED-3 except for
dimensions E2 & D2.
