1
FEATURES
DESCRIPTION
1
2
3
4
8
7
6
5
VCC
R
D
GND
A
B
Z
Y
SN65LVDM179D (Marked as DM179 or LVM179)
SN65LVDM179DGK (Marked as M79)
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
NC
R
RE
DE
D
GND
GND
VCC
VCC
A
B
Z
Y
NC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1B
1A
1R
RE
2R
2A
2B
GND
VCC
1D
1Y
1Z
DE
2Z
2Y
2D
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1B
1A
1R
1DE
2R
2A
2B
GND
VCC
1D
1Y
1Z
2DE
2Z
2Y
2D
SN65LVDM180D (Marked as LVDM180)
SN65LVDM180PW (Marked as LVDM180)
(TOP VIEW)
SN65LVDM050D (Marked as LVDM050)
SN65LVDM050PW (Marked as LVDM050)
(TOP VIEW)
SN65LVDM051D (Marked as LVDM051)
SN65LVDM051PW (Marked as LVDM051)
(TOP VIEW)
R
DY
Z
A
B
R
DY
Z
A
B
DE
RE
2
3
2
5
4
3
5
6
8
7
9
10
12
11
2D
1D 1Y
1Z
2Y
2Z
DE 9
15
12
14
13
10
11
2R
1R 1A
1B
2A
2B
RE 5
3
4
2
1
6
7
1R
1D 1Y
1Z
1A
1B
1DE 3
15
4
14
13
2
1
2R
2D 2Y
2Z
2A
2B
2DE 5
9
12
10
11
6
7
SN65LVDM179 , SN65LVDM180SN65LVDM050 , SN65LVDM051
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.................................................................................................................................................... SLLS324J – DECEMBER 1998 – REVISED JULY 2009
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
•Low-Voltage Differential 50- ΩLine Drivers andReceivers
•Typical Full-Duplex Signaling Rates of 100Mbps (See Table 1 )•Bus-Terminal ESD Exceeds 12 kV•Operates From a Single 3.3-V Supply•Low-Voltage Differential Signaling With TypicalOutput Voltages of 340 mV With a 50- ΩLoad•Valid Output With as Little as 50-mV InputVoltage Difference•Propagation Delay Times– Driver: 1.7 ns Typical– Receiver: 3.7 ns Typical•Power Dissipation at 200 MHz– Driver: 50 mW Typical– Receiver: 60 mW Typical•LVTTL Input Levels Are 5-V Tolerant•Driver Is High Impedance When Disabled orWith V
CC
< 1.5 V•Receiver Has Open-Circuit Failsafe
The SN65LVDM179, SN65LVDM180,SN65LVDM050, and SN65LVDM051 are differentialline drivers and receivers that use low-voltagedifferential signaling (LVDS) to achieve high signalingrates. These circuits are similar to TIA/EIA-644standard compliant devices (SN65LVDS)counterparts, except that the output current of thedrivers is doubled. This modification provides aminimum differential output voltage magnitude of 247mV across a 50- Ωload simulating two transmissionlines in parallel. This allows having data buses withmore than one driver or with two line terminationresistors. The receivers detect a voltage difference of50 mV with up to 1 V of ground potential differencebetween a transmitter and receiver.
The intended application of these devices andsignaling techniques is point-to-point half duplex,baseband data transmission over a controlledimpedance media of approximately 100 Ωcharacteristic impedance.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 1998 – 2009, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
DESCRIPTION (CONTINUED)
FUNCTION TABLES
SN65LVDM179 , SN65LVDM180SN65LVDM050 , SN65LVDM051
SLLS324J – DECEMBER 1998 – REVISED JULY 2009 ....................................................................................................................................................
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate anddistance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to theenvironment, and other application-specific characteristics.
The SN65LVDM179, SN65LVDM180, SN65LVDM050, and SN65LVDM051 are characterized for operation from– 40 ° C to 85 ° C.
Table 1. Maximum Recommended Operating Speeds
Part Number All Buffers Active Rx Buffer Only Tx Buffer Only
SN65LVDM179 150 Mbps 150 Mbps 500 MbpsSN65LVDM180 150 Mbps 150 Mbps 500 MbpsSN65LVDM050 100 Mbps 100 Mbps 400 MbpsSN65LVDM051 100 Mbps 100 Mbps 400 Mbps
AVAILABLE OPTIONS
PACKAGET
A
SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE(D) (DGK) (PW)
SN65LVDM050D — SN65LVDM050PWSN65LVDM051D — SN65LVDM051PW– 40 ° C to 85 ° C
SN65LVDM179D SN65LVDM179DGK —SN65LVDM180D — SN65LVDM180PW
SN65LVDM179 RECEIVER
INPUTS OUTPUT
(1)
V
ID
= V
A
– V
B
RV
ID
≥50 mV H50 MV < V
ID
< 50 mV ?V
ID
≤– 50 mV LOpen H
(1) H = high level, L = low level, ? = indeterminate
SN65LVDM179 DRIVER
INPUT
(1)
OUTPUTS
(1)
D Y ZL L HH H LOpen L H
(1) H = high level, L = low level
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EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
300 kΩ
50 Ω
VCC
7 V
D or RE
Input
300 kΩ
50 Ω
VCC
7 V
DE
Input
5 Ω
10 kΩ
7 V
Y or Z
Output
VCC
7 V
VCC
7 V
R Output
VCC
5 Ω
B InputA Input
300 kΩ300 kΩ
7 V
SN65LVDM179 , SN65LVDM180SN65LVDM050 , SN65LVDM051
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.................................................................................................................................................... SLLS324J – DECEMBER 1998 – REVISED JULY 2009
SN65LVDM180, SN65LVDM050, and SN65LVDM051 RECEIVER
INPUTS
(1)
OUTPUT
(1)
V
ID
= V
A
– V
B
RE RV
ID
≥50 mV L H50 MV < V
ID
< 50 mV L ?V
ID
≤– 50 mV L LOpen L HX H Z
(1) H = high level, L = low level, Z = high impedance, X = don ' t care
SN65LVDM180, SN65LVDM050, and SN65LVDM051 DRIVER
INPUTS
(1)
OUTPUTS
(1)
D DE Y ZL H L HH H H LOpen H L HX L Z Z
(1) H = high level, L = low level, Z = high impedance, X = don ' t care
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ABSOLUTE MAXIMUM RATINGS
DISSIPATION RATING TABLE
RECOMMENDED OPERATING CONDITIONS
2.4 *
ŤVIDŤ
2
ŤVIDŤ
2
SN65LVDM179 , SN65LVDM180SN65LVDM050 , SN65LVDM051
SLLS324J – DECEMBER 1998 – REVISED JULY 2009 ....................................................................................................................................................
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over operating free-air temperature range (unless otherwise noted)
(1)
UNIT
V
CC
Supply voltage range
(2)
– 0.5 V to 4 VD, R, DE, RE – 0.5 V to 6 VVoltage range
Y, Z, A, and B – 0.5 V to 4 VY, Z, A, B , and GND
(3)
CLass 3, A:12 kV, B:600 VElectrostatic discharge
All Class 3, A:7 kV, B:500 VContinuous power dissipation See Dissipation Rating TableStorage temperature range – 65 ° C to 150 ° C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.(3) Tested in accordance with MIL-STD-883C Method 3015.7.
T
A
≤25 ° C DERATING FACTOR T
A
= 85 ° CPACKAGE
POWER RATING ABOVE T
A
= 25 ° C
(1)
POWER RATING
D(8) 635 mW 5.1 mW/ ° C 330 mWD(14) 987 mW 7.9 mW/ ° C 513 mWD(16) 1110 mW 8.9 mW/ ° C 577 mWDGK 424 mW 3.4 mW/ ° C 220 mWPW (14) 736 mW 5.9 mW/ ° C 383 mWPW (16) 839 mW 6.7 mW/ ° C 437 mW
(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no airflow.
MIN NOM MAX UNIT
V
CC
Supply voltage 3 3.3 3.6 VV
O
Driver output voltage 0 2.4 VV
IH
High-level input voltage 2 VV
IL
Low-level input voltage 0.8 V|V
ID
| Magnitude of differential input voltage 0.1 0.6 V
V
IC
Common-mode input voltage (see Figure 6) V
V
CC
-0.8T
A
Operating free-air temperature — 40 85 ° C
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DEVICE ELECTRICAL CHARACTERISTICS
DRIVER ELECTRICAL CHARACTERISTICS
SN65LVDM179 , SN65LVDM180SN65LVDM050 , SN65LVDM051
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.................................................................................................................................................... SLLS324J – DECEMBER 1998 – REVISED JULY 2009
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
SN65LVDM179 No receiver load, driver R
L
= 50 Ω10 15 mADriver and receiver enabled, no receiver load,
10 15driver R
L
= 50 Ω
Driver enabled, receiver disabled, R
L
= 50 Ω9 13SN65LVDM180 mADriver disabled, receiver enabled, no load 1.7 5Disabled 0.5 2I
CC
Supply current Drivers and receivers enabled, no receiver loads,
19 27driver R
L
= 50 Ω
Drivers enabled, receivers disabled, R
L
= 50 Ω16 24SN65LVDM050 mADrivers disabled, receivers enabled, no loads 4 6Disabled 0.5 1Drivers enabled, no receiver loads, driver R
L
= 50 Ω19 27SN65LVDM051 mADrivers disabled, no loads 4 6
(1) All typical values are at 25 ° C and with a 3.3 V supply.
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
|V
OD
| Differential output voltage magnitude 247 340 454R
L
= 50 Ω, See Figure 1 and Figure 2 mVChange in differential output voltage magnitudeΔ|V
OD
| – 50
(1)
50between logic statesV
OC(SS)
Steady-state common-mode output voltage 1.125 1.2 1.375 VChange in steady-state common-mode outputΔV
OC(SS)
See Figure 3 – 50 50 mVvoltage between logic statesV
OC(PP)
Peak-to-peak common-mode output voltage 50 150 mVDE – 20 – 0.5I
IH
High-level input current V
IH
= 5 V µAD 2 20DE – 10 – 0.5I
IL
Low-level input current V
IL
= 0.8 V µAD 2 10V
OY
or V
OZ
= 0 V 7 10I
OS
Short-circuit output current mAV
OD
= 0 V 7 10V
O
= 0 V or 2.4 V, other outputI
OZ
High-impedance output current – 47 47 µAat 1.2 V, DE AT 0.8 VV
CC
= 0 V, V
O
= 0 V or 2.4 V, otherI
O(OFF)
Power-off output current – 47 47 µAoutput at 1.2 V, DE AT 0.8 VC
IN
Input capacitance 3 pF
(1) The algebraic convention in which the least positive (most negative) value is designated minimum is used in this datasheet.
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RECEIVER ELECTRICAL CHARACTERISTICS
DRIVER SWITCHING CHARACTERISTICS
SN65LVDM179 , SN65LVDM180SN65LVDM050 , SN65LVDM051
SLLS324J – DECEMBER 1998 – REVISED JULY 2009 ....................................................................................................................................................
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over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
V
IT+
Positive-going differential input voltage threshold 50See Figure 5 and Table 2 mVV
IT-
Negative-going differential input voltage threshold – 50V
OH
High-level output voltage I
OH
= -8 mA 2.4 VV
OL
Low-level output voltage I
OL
= 8 mA 0.4 VV
I
= 0 – 20 – 11I
I
Input current (A or B inputs) µAV
I
= 2.4 V – 3 – 1.2I
I(OFF)
Power-off input current (A or B inputs) V
CC
= 0 – 20 20 µAI
IH
High-level input current (enables) V
IH
= 5 V 10 µAI
IL
Low-level input current (enables) V
IL
= 0.8 V 10 µAI
OZ
High-impedance output current V
O
= 0 or 5 V – 10 10 µAC
I
Input capacitance 5 pF
(1) All typical values are at 25 ° C and with a 3.3-V supply.
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
t
PLH
Propagation delay time, low-to-high-level output 1.7 2.7 nst
PHL
Propagation delay time, high-to-low-level output 1.7 2.7 nst
r
Differential output signal rise time 0.6 1 nsR
L
= 50 Ω,t
f
Differential output signal fall time C
L
= 10 pF, 0.6 1 nsSee Figure 6t
sk(p)
Pulse skew (|t
pHL
– t
pLH
|) 250 pst
sk(o)
Channel-to-channel output skew
(2)
100 pst
sk(pp)
Part-to-part skew
(3)
1 nst
PZH
Propagation delay time, high-impedance-to-high-level output 6 10 nst
PZL
Propagation delay time, high-impedance-to-low-level output 6 10 nsSee Figure 7t
PHZ
Propagation delay time, high-level-to-high-impedance output 4 10 nst
PLZ
Propagation delay time, low-level-to-high-impedance output 5 10 ns
(1) All typical values are at 25 ° C and with a 3.3-V supply.(2) t
sk(o)
is the maximum delay time difference between drivers on the same device.(3) t
sk(pp)
is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devicesoperate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
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RECEIVER SWITCHING CHARACTERISTICS
PARAMETER MEASUREMENT INFORMATION
DRIVER
VOD
VOZ
VOY
VOC
VI
IOY
IOZ
IIA
Z
Y
VOY )VOZ
2
Driver Enable
SN65LVDM179 , SN65LVDM180SN65LVDM050 , SN65LVDM051
www.ti.com
.................................................................................................................................................... SLLS324J – DECEMBER 1998 – REVISED JULY 2009
over recommended operating conditions (unless otherwise noted)
TYP
(PARAMETER TEST CONDITIONS MIN MAX UNIT1)
t
PLH
Propagation delay time, low-to-high-level output 3.7 4.5 nst
PHL
Propagation delay time, high-to-low-level output C
L
= 10 pF, See Figure 6 3.7 4.5 nst
sk(p)
Pulse skew (|t
pHL
- t
pLH
|) 0.1 nst
sk(o)
Channel-to-channel output skew 0.2 nst
sk(pp)
Part-to-part skew
(2)
1 nst
r
Output signal rise time 0.7 1.5 nsC
L
= 10 pF, See Figure 6t
f
Output signal fall time 0.9 1.5 nst
PZH
Propagation delay time, high-level-to-high-impedance output 2.5 nst
PZL
Propagation delay time, low-level-to-low-impedance output 2.5 nsSee Figure 7t
PHZ
Propagation delay time, high-impedance-to-high-level output 7 nst
PLZ
Propagation delay time, low-impedance-to-high-level output 4 ns
(1) All typical values are at 25 ° C and with a 3.3-V supply.(2) t
sk(pp)
is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devicesoperate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
Figure 1. Driver Voltage and Current Definitions
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2 V
1.4 V
0.8 V
100%
80%
20%
0%
0 V
VOD(H)
VOD(L)
Output
Input
tPHL
tPLH
tftr
_
+
VOD 50 Ω
3.75 kΩ
3.75 kΩ
0 ≤ Vtest ≤ 2.4 V
Y
Z
DA
Input
VOC
Z
Y
Input
CL = 10 pF
(2 Places)
3 V
0 V
VOC(PP) VOC(SS)
VOC
25 Ω, ±1% (2 Places)
Driver Enable
SN65LVDM179 , SN65LVDM180SN65LVDM050 , SN65LVDM051
SLLS324J – DECEMBER 1998 – REVISED JULY 2009 ....................................................................................................................................................
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PARAMETER MEASUREMENT INFORMATION (continued)
A. All input pulses are supplied by a generator having the following characteristics: t
r
or t
f
≤1 ns, pulse repetition rate(PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns . C
L
includes instrumentation and fixture capacitance within 0,06 mm ofthe D.U.T.
Figure 2. Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal
A. All input pulses are supplied by a generator having the following characteristics: t
r
or t
f
≤1 ns, pulse repetition rate(PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns . C
L
includes instrumentation and fixture capacitance within 0,06 mm ofthe D.U.T. The measurement of V
OC(PP)
is made on test equipment with a -3 dB bandwidth of at least 300 MHz.
Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
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1.2 V
Z
Y
0.8 V or 2 V
25 Ω, ±1% (2 Places)
CL = 10 pF
(2 Places)
DE VOY VOZ
2 V
0.8 V
tPHZ
tPZH
tPLZ
tPZL
1.4 V
~1.4 V
1.2 V
1.25 V
1.2 V
~1 V
1.15 V
DE
VOY or VOZ
VOZ or VOY
D at 2 V and input to DE
D at 0.8 V and input to DE
SN65LVDM179 , SN65LVDM180SN65LVDM050 , SN65LVDM051
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.................................................................................................................................................... SLLS324J – DECEMBER 1998 – REVISED JULY 2009
PARAMETER MEASUREMENT INFORMATION (continued)
A. All input pulses are supplied by a generator having the following characteristics: t
r
or t
f
≤1 ns, pulse repetition rate(PRR) = 0.5 Mpps, pulse width = 500 ± 10 ns . C
L
includes instrumentation and fixture capacitance within 0,06 mm ofthe D.U.T.
Figure 4. Enable and Disable Time Circuit and Definitions
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RECEIVER
SN65LVDM179 , SN65LVDM180SN65LVDM050 , SN65LVDM051
SLLS324J – DECEMBER 1998 – REVISED JULY 2009 ....................................................................................................................................................
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PARAMETER MEASUREMENT INFORMATION (continued)
Figure 5. Receiver Voltage Definitions
Table 2. Receiver Minimum and Maximum Input Threshold Test Voltages
RESULTING DIFFERENTIAL RESULTING COMMON-MODEAPPLIED VOLTAGES
INPUT VOLTAGE INPUT VOLTAGE(V)
(mV) (V)
V
IA
V
IB
V
ID
V
IC
1.225 1.175 50 1.21.175 1.225 – 50 1.22.375 2.325 50 2.352.325 2.375 – 50 2.350.05 0 50 0.050 0.05 – 50 0.051.5 0.9 600 1.20.9 1.5 – 600 1.22.4 1.8 600 2.11.8 2.4 – 600 2.10.6 0 600 0.30 0.6 – 600 0.3
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VOH
VOL
1.4 V
VO
VIA
VIB
VID
1.4 V
1 V
0.4 V
0 V
−0.4 V
tPHL tPLH
tr
tf
0.4 V
2.4 V
VIB
VID
VIA VO
CL
10 pF
SN65LVDM179 , SN65LVDM180SN65LVDM050 , SN65LVDM051
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.................................................................................................................................................... SLLS324J – DECEMBER 1998 – REVISED JULY 2009
A. All input pulses are supplied by a generator having the following characteristics: t
r
or t
f
≤1 ns, pulse repetition rate(PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns. C
L
includes instrumentation and fixture capacitance within 0,06 mm ofthe D.U.T.
Figure 6. Timing Test Circuit and Waveforms
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tPZH
VTEST
A
tPZH tPHZ
VOH
1.4 V
VOH −0.5 V
0 V
2 V
1.4 V
0.8 V
0 V
1.4 V
RE
R
tPZL
VTEST
A
tPZL tPLZ
2.5 V
1.4 V
VOL +0.5 V VOL
2 V
1.4 V
0.8 V
2.5 V
1 V
RE
R
VO
CL
10 pF +
−
500 Ω
1.2 V B
A
RE
Inputs
NOTE A: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5
Mpps, pulse width = 500 ± 10 ns. CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T.
SN65LVDM179 , SN65LVDM180SN65LVDM050 , SN65LVDM051
SLLS324J – DECEMBER 1998 – REVISED JULY 2009 ....................................................................................................................................................
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Figure 7. Enable/Disable Time Test Circuit and Waveforms
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TYPICAL CHARACTERISTICS
IOL − Low-Level Output Current − mA
1
080
2
VCC = 3.3 V
TA = 25°C
3
124
VOL− Low-Level Output Voltage − V
4
6 102
IOH − High-Level Output Current − mA
1
.5
0−4 −6
3
0
1.5
VCC = 3.3 V
TA = 25°C
2
2.5
−8−2
VOH− High-Level Output V oltage − V
3.5
0IOH − High-Level Output Current − mA
4
0−80
2
−20
VOH
−40 −60
3
1
− High-Level Output Voltage − V
VCC = 3.3 V
TA = 25°C
0IOL − Low-Level Output Current − mA
5
060
2
10
VOL
20 30
3
1
− Low-Level Output Votlage − V
40 50
4
VCC = 3.3 V
TA = 25°C
SN65LVDM179 , SN65LVDM180SN65LVDM050 , SN65LVDM051
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.................................................................................................................................................... SLLS324J – DECEMBER 1998 – REVISED JULY 2009
DRIVER DRIVERLOW-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT VOLTAGEvs vsLOW-LEVEL OUTPUT CURRENT HIGH-LEVEL OUTPUT CURRENT
Figure 8. Figure 9.
RECEIVER RECEIVERHIGH-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGEvs vsHIGH-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT CURRENT
Figure 10. Figure 11.
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−50 TA − Free-Air Temperature − °C
2.5
1.5 50 90
2
−10
tPLH − High-To-Low Propagation Delay Time − ns
−30 30 70
10
VCC = 3.6 V
VCC = 3.3 V
VCC = 3 V
−50 TA − Free-Air Temperature − °C
2.5
1.5 50 90
2
−10
tPLH − Low-To-High Propagation Delay Time − ns
−30 30 70
10
VCC = 3.6 V
VCC = 3.3 V
VCC = 3 V
−50 TA − Free-Air Temperature − °C
4.5
2.5 50 90
3.5
−10
tPLH − Low-To-High Level Propagation Delay Time − ns
−30 30 70
10
VCC = 3.6 V
VCC = 3 V
4
3
VCC = 3.3 V
−50 TA − Free−Air Temperature − °C
4.5
2.5 50 90
3.5
−10
tPLH
−30 30 70
10
VCC = 3.6 V
VCC = 3 V
4
3
VCC = 3.3 V
− High-To-Low Level Propagation Dealy Time − ns
SN65LVDM179 , SN65LVDM180SN65LVDM050 , SN65LVDM051
SLLS324J – DECEMBER 1998 – REVISED JULY 2009 ....................................................................................................................................................
www.ti.com
TYPICAL CHARACTERISTICS (continued)
DRIVER DRIVERHIGH-TO-LOW LEVEL PROPAGATION DELAY TIME LOW-TO-HIGH LEVEL PROPAGATION DELAY TIMEvs vsFREE-AIR TEMPERATURE FREE-AIR TEMPERATURE
Figure 12. Figure 13.
RECEIVER RECEIVERHIGH-TO-LOW LEVEL PROPAGATION DELAY TIME LOW-TO-HIGH LEVEL PROPAGATION DELAY TIMEvs vsFREE-AIR TEMPERATURE FREE-AIR TEMPERATURE
Figure 14. Figure 15.
14 Submit Documentation Feedback Copyright © 1998 – 2009, Texas Instruments Incorporated
Product Folder Link(s): SN65LVDM179 SN65LVDM180 SN65LVDM050 SN65LVDM051
APPLICATION INFORMATION
Equipment
HewlettPackardHP6624A
DCPowerSupply
BenchTestBoard
AgilentParBERT
(E4832A)
TektronixTDS7404
RealTimeScope
(c)(a) (b)
SN65LVDM179 , SN65LVDM180SN65LVDM050 , SN65LVDM051
www.ti.com
.................................................................................................................................................... SLLS324J – DECEMBER 1998 – REVISED JULY 2009
•Hewlett Packard HP6624A DC power supply•Tektronix TDS7404 Real Time Scope•Agilent ParBERT E4832A
Figure 16. Equipment Setup
a. Tx + Rx running at 150 Mbps; Channel 1: R, Channel 2: Y-Zb. Rx only running at 150 Mbps; Channel 1: Rc. Tx only running at 500 Mbps; Channel 1: Y-Z
Figure 17. Typical Eye Patterns SN65LVDM179: (T = 25 ° C; V
CC
= 3.6 V; PRBS = 2
23-1
)
Copyright © 1998 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): SN65LVDM179 SN65LVDM180 SN65LVDM050 SN65LVDM051
(c)(a) (b)
(c)(a) (b)
(c)(a) (b)
SN65LVDM179 , SN65LVDM180SN65LVDM050 , SN65LVDM051
SLLS324J – DECEMBER 1998 – REVISED JULY 2009 ....................................................................................................................................................
www.ti.com
a. Tx + Rx running at 150 Mbps; Channel 1: R, Channel 2: Y-Zb. Rx only running at 150 Mbps; Channel 1: Rc. Tx only running at 500 Mbps; Channel 1: Y-Z
Figure 18. Typical Eye Patterns SN65LVDM180: (T = 25 ° C; V
CC
= 3.6 V; PRBS = 2
23-1
)
a. All buffers running at 100 Mbps; Channel 1: R, Channel 2: 2R, Channel 3: 1Y-1Z, Channel 4: 2Y-2Z,b. Rx buffers only running at 100 Mbps; Channel 1: R, Channel 2: 2Rc. Tx buffers only running at 400 Mbps; Channel 3: 1Y-1Z, Channel 4: 2Y-2Z,
Figure 19. Typical Eye Patterns SN65LVDM050: (T = 25 ° C; V
CC
= 3.6 V; PRBS = 2
23-1
)
a. All buffers running at 100 Mbps; Channel 1: R, Channel 2: 2R, Channel 3: 1Y-1Z, Channel 4: 2Y-2Z,b. Rx buffers only running at 100 Mbps; Channel 1: R, Channel 2: 2Rc. Tx buffers only running at 400 Mbps; Channel 3: 1Y-1Z, Channel 4: 2Y-2Z,
Figure 20. Typical Eye Patterns SN65LVDM051: (T = 25 ° C; V
CC
= 3.6 V; PRBS = 2
23-1
)
16 Submit Documentation Feedback Copyright © 1998 – 2009, Texas Instruments Incorporated
Product Folder Link(s): SN65LVDM179 SN65LVDM180 SN65LVDM050 SN65LVDM051
10
0.1 1M Data Rate - Hz
1
100k 10M 100M
100
Transmission Distance - m
1000
5% Jitter
30% Jitter
24 AWG UTP 96 Ω (PVC Dielectric)
FAIL SAFE
Rt = 100 Ω (Typ)
300 kΩ300 kΩ
VCC
VIT ≈ 2.3 V
A
BY
SN65LVDM179 , SN65LVDM180SN65LVDM050 , SN65LVDM051
www.ti.com
.................................................................................................................................................... SLLS324J – DECEMBER 1998 – REVISED JULY 2009
The devices are generally used as building blocks for high-speed point-to-point data transmission. Grounddifferences are less than 1 V with a low common-mode output and balanced interface for low noise emissions.Devices can interoperate with RS-422, PECL, and IEEE-P1596. Drivers/receivers maintain ECL speeds withoutthe power and dual supply requirements.
Figure 21. Data Transmission Distance Versus Rate
One of the most common problems with differential signaling applications is how the system responds when nodifferential voltage is present on the signal pair. The LVDS receiver is like most differential line receivers, in thatits output logic state can be indeterminate when the differential input voltage is between – 50 mV and 50 mV andwithin its recommended input common-mode voltage range. TI's LVDS receiver is different; however, in the wayit handles the open-input circuit situation.
Open-circuit means that there is little or no input current to the receiver from the data line itself. This could bewhen the driver is in a high-impedance state or the cable is disconnected. When this occurs, the LVDS receiverpulls each line of the signal pair to near V
CC
through 300-k Ωresistors as shown in Figure 22 . The fail-safefeature uses an AND gate with input voltage thresholds at about 2.3 V to V
CC
– 0.4 V to detect this condition andforce the output to a high-level, regardless of the differential input voltage.
Figure 22. Open-Circuit Fail Safe of the LVDS Receiver
It is only under these conditions that the output of the receiver is valid with less than a 50-mV differential inputvoltage magnitude. The presence of the termination resistor, R
t
, does not affect the fail-safe function as long as itis connected as shown in the figure. Other termination circuits may allow a dc current to ground that could defeatthe pullup currents from the receiver and the fail-safe feature.
Copyright © 1998 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): SN65LVDM179 SN65LVDM180 SN65LVDM050 SN65LVDM051
SN65LVDM179 , SN65LVDM180SN65LVDM050 , SN65LVDM051
SLLS324J – DECEMBER 1998 – REVISED JULY 2009 ....................................................................................................................................................
www.ti.com
REVISION HISTORY
Changes from Revision I (January 2009) to Revision J ................................................................................................. Page
•Changed value from 40 to -40 ............................................................................................................................................... 4•Deleted value 85 from NOM value and moved to max .......................................................................................................... 4
18 Submit Documentation Feedback Copyright © 1998 – 2009, Texas Instruments Incorporated
Product Folder Link(s): SN65LVDM179 SN65LVDM180 SN65LVDM050 SN65LVDM051
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
SN65LVDM050D ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDM050DG4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDM050DR ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDM050DRG4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDM050PW ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDM050PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDM050PWR ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDM050PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDM051D ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDM051DG4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDM051DR ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDM051DRG4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDM051PW ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDM051PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDM051PWR ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDM051PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDM179D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
SN65LVDM179DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDM179DGK ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDM179DGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDM179DGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDM179DGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDM179DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDM179DRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDM180D ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDM180DG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDM180DR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDM180DRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDM180PW ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDM180PWG4 ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDM180PWR ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDM180PWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 3
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN65LVDM050, SN65LVDM051 :
•Automotive: SN65LVDM050-Q1, SN65LVDM051-Q1
NOTE: Qualified Version Definitions:
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN65LVDM050DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
SN65LVDM050PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN65LVDM051DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
SN65LVDM051PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN65LVDM179DGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
SN65LVDM179DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN65LVDM180DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN65LVDM180PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN65LVDM050DR SOIC D 16 2500 367.0 367.0 38.0
SN65LVDM050PWR TSSOP PW 16 2000 367.0 367.0 35.0
SN65LVDM051DR SOIC D 16 2500 367.0 367.0 38.0
SN65LVDM051PWR TSSOP PW 16 2000 367.0 367.0 35.0
SN65LVDM179DGKR VSSOP DGK 8 2500 358.0 335.0 35.0
SN65LVDM179DR SOIC D 8 2500 340.5 338.1 20.6
SN65LVDM180DR SOIC D 14 2500 367.0 367.0 38.0
SN65LVDM180PWR TSSOP PW 14 2000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 2
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