Datasheet A S 5 11 5 Programmable 360 Magnetic Angle Encoder with Buffered SINE & COSINE Output Signals 1 General Description 2 Key Features Contactless angular position encoding The AS5115 is a contactless rotary encoder sensor for accurate angular measurement over a full turn of 360 and over an extended ambient temperature range of -40C to +150C. High precision analog output Based on an integrated Hall element array, the angular position of a simple two-pole magnet is translated into analog output voltages. The angle information is provided by means of buffered sine and cosine voltages. This approach gives maximum flexibility in system design, as it can be directly integrated into existing architectures and optimized for various applications in terms of speed and accuracy. An SSI Interface is implemented for signal path configuration as well as a one time programmable register block (OTP), which allows the customer to adjust the signal path gain to adjust for different mechanical constraints and magnetic field. Buffered Sine and Cosine signals SSI Interface Low power mode Two programmable output modes: Differential or Single ended Wide magnetic field input range: 20 - 80 mT Wide temperature range: -40C to +150C Fully automotive qualified to AEC-Q100, grade 0 SSOP-16 package 3 Applications The AS5115 is ideal for several automotive and industrial applications. Figure 1. AS5115 Block Diagram PROG OTP Register AS5115 Digital Part CS DCLK DIO SSI Interface Power Management Buffer Stage VDD VSS SINP/SINN SINN/SINP/CM_SIN Buffer Stage Hall Array & Frontend Amplifier www.austriamicrosystems.com/AS5115 COSP/COSN COSN/COSP/CM_COS Revision 1.11 1 - 20 AS5115 Datasheet - C o n t e n t s Contents 1 General Description .................................................................................................................................................................. 1 2 Key Features............................................................................................................................................................................. 1 3 Applications............................................................................................................................................................................... 1 4 Pin Assignments ....................................................................................................................................................................... 3 4.1 Pin Descriptions.................................................................................................................................................................................... 3 5 Absolute Maximum Ratings ...................................................................................................................................................... 4 6 Electrical Characteristics........................................................................................................................................................... 5 6.1 Timing Characteristics .......................................................................................................................................................................... 6 7 Detailed Description.................................................................................................................................................................. 7 7.1 Sleep Mode .......................................................................................................................................................................................... 7 7.2 SSI Interface......................................................................................................................................................................................... 7 7.3 Device Communication / Programming ................................................................................................................................................ 8 7.4 Waveform - Digital Interface at Normal Operation Mode................................................................................................................... 10 7.5 Waveform - Digital Interface at Extended Mode ................................................................................................................................ 10 7.6 Waveform - Digital Interface at Analog Readback of the Zener Diodes ............................................................................................ 11 7.7 EasyZapp OTP Content ..................................................................................................................................................................... 11 7.8 Analog Sin/Cos Outputs with External Interpolator ............................................................................................................................ 12 7.9 OTP Programming and Verification .................................................................................................................................................... 13 7.10 Pre-programmed Version ................................................................................................................................................................. 15 8 Application Information ........................................................................................................................................................... 16 9 Package Drawings and Markings ........................................................................................................................................... 17 10 Ordering Information............................................................................................................................................................. 19 www.austriamicrosystems.com/AS5115 Revision 1.11 2 - 20 AS5115 Datasheet - P i n A s s i g n m e n t s 4 Pin Assignments Figure 2. Pin Assignments (Top View) DCLK 1 16 VDD CS 2 15 TB0 DIO 3 14 TB1 TC 4 13 TB2 A_TST 5 12 TB3 PROG 6 11 COSN/COSP/CM_COS VSS 7 10 COSP/COSN SINP/SINN 8 9 AS5115 SINN/SINP/CM_SIN 4.1 Pin Descriptions Table 1. Pin Descriptions Pin Name Pin Number DCLK 1 CS 2 DIO 3 Digital input/output Data I/O for digital interface, Scan input TC 4 Analog input/output Test coil A_TST 5 Analog output/Digital output Analog test pin, Scan output PROG 6 VSS 7 SINP/SINN 8 SINN/SINP/CM_SIN 9 COSP/COSN 10 COSN/COSP/CM_COS 11 TB3 12 TB2 13 TB1 14 TB0 15 Analog output Test bus, analog output VDD 16 Supply pad Digital + analog supply www.austriamicrosystems.com/AS5115 Pin Type Description Digital input with Schmitt Clock input for digital interface trigger Clock input for digital interface, Scan enable OTP Programming Pad Supply pad Also used as VSS of test coil + EasyZapp (double bond) Analog output Buffered analog output Analog output/Digital input Test bus, analog output Test bus, analog output; external clock sync. prod. test Revision 1.11 3 - 20 AS5115 Datasheet - A b s o l u t e M a x i m u m R a t i n g s 5 Absolute Maximum Ratings Stresses beyond those listed in Table 2 may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in Electrical Characteristics on page 5 is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 2. Absolute Maximum Ratings Parameter Min Max Units Comments Electrical Parameters Supply voltage (VDD) -0.3 7 V Input pin voltage (V_in) -0.3 VDD+0.3 V Input current (latchup immunity), I_scr -100 100 mA Norm: EIA/JESD78 Class II Level A 2 kV Norm: JESD22-A114E Electrostatic Discharge Electrostatic discharge (ESD) Continuous Power Dissipation Total power dissipation (Ptot) 275 mW Package thermal resistance (_JA) 27 C/W 150 C Velocity =0; Multi Layer PCB; Jedec Standard Testboard Temperature Ranges and Storage Conditions Storage temperature (T_strg) -65 Package body temperature (T_body) Humidity non-condensing Moisture Sensitive Level (MSL) www.austriamicrosystems.com/AS5115 5 260 C 85 % 3 Norm: IPC/JEDEC J-STD-020. The reflow peak soldering temperature (body temperature) specified is in accordance with IPC/JEDEC J-STD-020 "Moisture/Reflow Sensitivity Classification for NonHermetic Solid State Surface Mount Devices". The lead finish for Pb-free leaded packages is matte tin (100% Sn). Represents a maximum floor time of 168h Revision 1.11 4 - 20 AS5115 Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s 6 Electrical Characteristics Unless otherwise noted in this specification, all defined tolerances of parameters are assured over the whole operation conditions range and also over lifetime. Table 3. Operating Conditions Symbol Parameter Condition Min Typ VDD Positive Supply Voltage VSS Negative Supply Voltage 0.0 0.0 V T_amb Ambient temperature -40 150 C Max Unit 4.5 Max Unit 5.5 V Table 4. DC/AC Characteristics for Digital Inputs and Outputs Symbol Parameter Condition Min Typ CMOS Input V_IH High level input voltage 0.7 * VDD VDD V V_IL Low level input voltage 0 0.3 * VDD V I_LEAK Input Leakage Current 1 A CMOS Output V_OH High level output voltage 4mA VDD - 0.5 VDD V V_OL Low level output voltage 4mA 0 VSS + 0.4 V C_L Capacitive Load 35 pF 1 A Max Unit CMOS Output Tristate I_OZ Tristate Leakage Current Table 5. Magnetic Input Specification Symbol Parameter Condition Min Typ BZpp Magnetic input field amplitude Peak to peak at the radius (=1mm) of the hall array 32 160 mT B_offset Magnetic field offset Within the linear range of the magnet -10 +10 mT frot Rotational speed Maximum 30,000 RPM 0 500 Hz Max Unit 28 mA 1.275 ms 30 s Table 6. Electrical System Specifications Symbol Parameter Condition IDD Current Consumption Maximum value derived at maximum I_H (Hall Bias Current) tpower_on Power up time tprop Propagation delay M Magnetic Sensitivity VPP Analog output voltage amplitude (peak to peak) AMTemp AM tracking accuracy over temperature -40C to 150C AM Sin / Cos Amplitude mismatch Voffset1 Voffset2 DCoffdrift Min Typ -40C to 150C 18 Version: AS5115 10 Version: AS5115A 20.72 28 35.28 1.38 1.94 2.5 V -1 +1 % 25C -2 +2 % Output DC offset voltage At no input signal; programmable OTP setting (see page 8) 1.47 1.5 1.53 2.45 2.5 2.55 DC Offset Drift -40C to 150C -50 www.austriamicrosystems.com/AS5115 Revision 1.11 22 60 +50 mV / mT V V/C 5 - 20 AS5115 Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s Table 6. Electrical System Specifications Symbol Parameter Condition Min VOUT Analog output range VSS + 0.25 IOUT Output Current -1 CLOAD Capacitive Load Typ Max Unit VDD - 0.5 V 1 mA 1000 pF 6.1 Timing Characteristics Table 7. Timing Characteristics Symbol Parameter Condition Min Typ Max Unit t1_3 Chip select to positive edge of DCLK 30 - ns t2_3 Chip select to drive bus externally 0 - ns t3 Setup time command bit Data valid to positive edge of DCLK 30 - ns t4 Hold time command bit Data valid after positive edge of DCLK 15 - ns t5 Float time Positive edge of DCLK for last command bit to bus float t6 Bus driving time Positive edge of DCLK for last command bit to bus drive t7 Data valid time Positive edge of DCLK to bus valid t8 Hold time data bit Data valid after positive edge of DCLK t9_3 Hold time chip select Positive edge DCLK to negative edge of chip select t10_3 Bus floating time Negative edge of chip select to float bus t11 t12 t13_3 - ns - ns ns see Figure 5 and Figure 6 - ns - ns - 30 ns Setup time data bit at write access Data valid to positive edge of DCLK 30 - ns Hold time data bit at write access Data valid after positive edge of DCLK 15 - ns - 30 ns Bus floating time Negative edge of chip select to float bus Remark: The digital interface will be reset during the low phase of the CS signal. www.austriamicrosystems.com/AS5115 Revision 1.11 6 - 20 AS5115 Datasheet - D e t a i l e d D e s c r i p t i o n 7 Detailed Description The benefits of AS5115 are as follows: Complete system-on-chip, no angle calibration required Ideal for applications in harsh environments due to magnetic sensing principle High reliability due to non-contact sensing Robust system, tolerant to horizontal misalignment, temperature variations and external magnetic fields 7.1 Sleep Mode The target is to provide the possibility to reduce the total current consumption. No output signal will be provided when the IC is in sleep mode. Enabling or disabling sleep mode is done by sending the SLEEP or WAKEUP commands via. the SSI interface. Analog blocks are powered down with respect to fast wake up time. 7.2 SSI Interface The setup for the device is handled by the digital interface. Each communication starts with the rising edge of the chip select signal. The synchronization between the internal free running analog clock oscillator and the external used digital clock source for the digital interface is done in a way that the digital clock frequency can vary in a wide range. Table 8. SSI Interface Pin Description Port Symbol Chip select CS DCLK DCLK Bidirectional data input output DIO Function Indicates the start of a new access cycle to the device CS = LO reset of the digital interface Clock source for the communication over the digital interface Command and data information over one single line The first bit of the command defines a read or write access Table 9. SSI Interface Parameter Description Symbol Parameter f_DCLK Clock frequency at normal operation f_EZ_RW Clock frequency at easy zap read write access at easy zap access f_EZ_PROG Clock frequency program OTP f_EZ_ARB Notes The nominal value for the clock frequency can be derived from a 10MHz oscillator source. Min Typ Max Unit no limit 5 6 MHz no limit 5 6 kHz 200 - 650 kHz no limit 156.3 162.5 kHz Correct access to the programmable zener diode block needs a strict timing - the zap pulse is exact one period. The nominal value for the clock frequency can be derived from a 10MHz oscillator source. 20pF external load allowed. Clock frequency at easy zap analog readback The nominal value for the clock frequency can be derived from a 10MHz oscillator source. Parameter Notes Interface General at normal mode Protocol: 5 command bit + 16 data input output Command 5-bit command: cmd<4:0> bit<21:16> Data 16-bit data: data<15:0> bit<15:0> Interface General at extended mode Protocol: 5 command bit + 46 data input output www.austriamicrosystems.com/AS5115 Revision 1.11 7 - 20 AS5115 Datasheet - D e t a i l e d D e s c r i p t i o n Parameter Notes Command 5-bit command: cmd<4:0> bit<50:46> Data 34-bit data: data<45:0> bit<45:0> Interface Modes Normal read operation mode cmd<4:0> = <00xxx> 1 DCLK per data bit Extended read operation mode cmd<4:0> = <01xxx> 4 DCLK per data bit Normal write operation mode cmd<4:0> = <10xxx> 1 DCLK per data bit Extended write operation mode cmd<4:0> = <11xxx> 4 DCLK per data bit 7.3 Device Communication / Programming Table 10. Digital Interface at Normal Mode # command bin mode 15 14 23 WRITE_CONFIG 10111 write go2sleep gen_rst 13 16 EN_PROG 10000 write 1 0 0 12 11 0 1 10 1 Name 9 8 analog_sig OB_bypassed 0 0 7 6 5 4 3 2 1 0 1 0 1 0 1 1 1 0 Functionality go2sleep Enter/leave low power mode (no output signals) gen_rst Generates global reset analog_sig Switches the channels to the test bus after the PGA OB_bypassed Disable and bypass output buffer for testing purpose Table 11. Digital Interface at Extended Mode Factory Settings User Settings # command bin mode 31 WRITE_OTP 11111 xt write r r r r r r r 25 PROG_OTP 11001 xt write r r r r r r 15 RD_OTP 01111 xt read r r r r r r 9 RD_OTP_ANA 01001 xt read <45:44> <43: 26> <25:23> <22:20> <19:18> <17:14> <13> <12> <11> <10> <9> <8:7> <6> <5:0> r invert_ channel cm_sin cm_cos gain dc_ offset hall_ bias r r invert_ channel cm_sin cm_cos gain dc_ offset hall_ bias r r invert_ channel cm_sin cm_cos gain dc_ offset hall_ bias Note: "r" stands for reserved bits. They must not be modified, unless otherwise noted. Remark: 1. Send EN PROG (command 16) in normal mode before accessing the OTP in extended mode. 2. OTP assignment will be defined/updated. Name Functionality invert_channel Inverts SIN and COS channel before the PGA for inverted output function (0 SIN/COS, 1 SINN/COSN) cm_sin Common mode voltage output enabled at SINN / CM pin (0 differential, 1 common) cm_cos Common mode voltage output enabled at COSN / CM pin (0 differential, 1 common) gain PGA gain setting (influences overall magnetic sensitivity), 2-bit dc_offset Output DC bias offset (0 Voffset1=1.5V, 1 Voffset2=2.5V) Hall_b www.austriamicrosystems.com/AS5115 Hall bias setting (influences overall magnetic sensitivity), 6-bit Revision 1.11 8 - 20 AS5115 Datasheet - D e t a i l e d D e s c r i p t i o n Figure 3. Sensitivity Gain Settings - Relative Sensitivity in % Magnetic Sensitivity vs. OTP Hall Current & PGA Gain Setting 600 550 Relative Sensitivity in % 500 450 400 M_PGA_00 350 M_PGA_01 M_PGA_10 300 M_PGA_11 250 200 150 100 0 10 20 30 40 50 60 Hall Current OTP setting (6 bits) The amplitude of the output signal is programmable via sensitivity (6bit) and/or gain (2bit) settings (see Figure 3). Figure 4. Sensitivity Gain Settings - Sensitivity [mV/mT] Magnetic Sensitivity vs. OTP Hall Current & PGA Gain Setting 70 60 Sensitivity [mV/mT] 50 M_PGA_00 40 M_PGA_01 M_PGA_10 30 M_PGA_11 20 10 0 0 10 20 30 40 50 60 Hall Current OTP setting (6 bits) www.austriamicrosystems.com/AS5115 Revision 1.11 9 - 20 AS5115 Datasheet - D e t a i l e d D e s c r i p t i o n 7.4 Waveform - Digital Interface at Normal Operation Mode Figure 5. Digital Interface at Normal Operation Mode CMD_PHASE DATA_PHASE DCLK t9_3 t1_3 CS t5 t2_3 DIO CMD4 t3 t4 DIO CMD3 CMD2 CMD1 CMD0 t7 t6 t8 D14 D15 D13 t13_3 t12 D15 D14 READ D0 t11 DIO CMD t10_3 D13 WRITE D0 7.5 Waveform - Digital Interface at Extended Mode In the extended mode, the digital interface needs four clocks for one data bit due to the internal structure. During this time, the device is able to handle internal signals for special access (e.g. the easy zap interface). Figure 6. Digital Interface at Extended Mode CMD_PHASE DATA_PHASE DCLK t1_3 t9_3 CS DIO CMD4 t3 DIO t7 t5 t2_3 CMD3 CMD2 CMD1 CMD0 t4 D45 t11 DIO www.austriamicrosystems.com/AS5115 t10_3 t8 t6 D44 Revision 1.11 READ D0 t13_3 t12 D45 CMD D44 D0 WRITE 10 - 20 AS5115 Datasheet - D e t a i l e d D e s c r i p t i o n 7.6 Waveform - Digital Interface at Analog Readback of the Zener Diodes To be sure that all Zener-Diodes are correctly burned, an analog readback mechanism is defined. Perform the `READ OTP ANA' sequence according to the command table and measure the value of the diode at the end of each phase. Figure 7. Digital Interface at Analog Readback of Zener Diodes CMD_PHASE DATA_PHASE_EXTENDED EXT D45 EXT D44 EXT D1 OTP D44 OTP D43 OTP D0 EXT D0 DCLK CS DIO CMD4 CMD3 CMD2 CMD1 CMD0 OTP D45 PROG perform analog measurements at PROG Table 12. Serial Bit Sequence (16-bit read / write) Write Command C4 C3 C2 C1 Read / Write Data C0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 7.7 One Time Programming Content The AS5115 die has an integrated 46-bit OTP ROM (Easyzapp) for trimming and configuration purposes. The PROM can be programmed via. the serial interface. For irreversible programming, an external programming voltage at PROG pin is needed. For security reasons, the factory trim bits can be locked by a lock bit. As shown in the table below, the OTP holds 46 bits. Bit number 44 and 45 are used for OTP testing purposes and ESD protection of the remaining cells. Name Bit Count OTP Start OTP End Access Comments Hall_b 6 0 5 user Sets overall sensitivity dc_offset 1 6 6 user Output DC offset setting gain 2 7 8 user Output Buffer Gain setting Lock 1 13 13 austriamicrosystems invert_channel 1 11 11 user Inverts SIN and COS channel before the PGA for inverted output function cm_sin 1 10 10 user Common mode voltage output enabled at SINN / CM pin cm_cos 1 9 9 user Common mode voltage output enabled at COSN / CM pin Set in production test Remark: OTP assignment will be defined/updated. www.austriamicrosystems.com/AS5115 Revision 1.11 11 - 20 AS5115 Datasheet - D e t a i l e d D e s c r i p t i o n 7.8 Analog Sin/Cos Outputs with External Interpolator Figure 8. Sine and Cosine Outputs for External Angle Calculation +5V VDD 100k VDD VDD PROG SINN/SINP/CM_SIN D A SINP/SINN Micro Controller AS5130 AS5115 100n COSN/COSP/CM_COS D A COSP/COSN VSS VSS VSS Notes: 1. We recommend to use a 100k pull-up resistance. 2. Default conditions for unused pins are: DCLK, CS, DIO, TC, A_TST, TBO, TB1, TB2, TB3 connect to VSS The AS5115 provides analog Sine and Cosine outputs (SINP, COSP) of the Hall array front-end for test purposes. These outputs allow the user to perform the angle calculation by an external ADC + C, e.g. to compute the angle with a high resolution. The signal lines must be kept as short as possible. In the case of longer lines, they must be shielded in order to achieve best noise performance. Through the programming of one bit, you have the possibility to choose between the analog Sine and Cosine outputs (SINP, COSP) and their inverted signals (SINN, COSN). Furthermore, by programming the bits <9:10> you can enable the common mode output signals of SIN and COS. www.austriamicrosystems.com/AS5115 Revision 1.11 12 - 20 AS5115 Datasheet - D e t a i l e d D e s c r i p t i o n 7.9 OTP Programming and Verification Figure 9. OTP Programming Connection +5V VDD VDD VDD CS Output DCLK I/O Micro Controller AS5115 Output AS5130 DIO 8.0 - 8.5V + VSS 100n PROG 10F 100n VSS - VSS Special Case Standard Case maximum parasitic cable inductance VSUPPLY L<50nH Vzapp C1 100nF VSUPPLY L<50nH VDD Vprog C2 VDD Vprog PROG GND C1 PROM Cell 100nF 10F C2 PROG GND PROM Cell 10F Remove for normal operation Note: The maximum capacitive load at PROG in normal operation should be less than 20pF. However, during programming the capacitors C1+C2 are needed to buffer the programming voltage during current spikes, but they must be removed for normal operation. To overcome this contradiction, the recommendation is to add a diode (4148 or similar) between PROG and VDD as shown in Figure 9 (special case setup), if the capacitors can not be removed at final assembly. Due to D1, the capacitors C1+C2 are loaded with VDD - 0.7V at startup, hence not influencing the readout of the internal OTP registers. During programming the OTP, the diode ensures that no current is flowing from PROG (8V - 8.5V) to VDD (5V). In the standard case (see Figure 9), the verification of a correct OTP readout can be done by analog readback of the OTP register. As long as the PROG pin is accessible it is recommended to use standard setup. In case the PROG pin is not accessible at final assembly, the special setup is recommended. www.austriamicrosystems.com/AS5115 Revision 1.11 13 - 20 AS5115 Datasheet - D e t a i l e d D e s c r i p t i o n For programming of the OTP, an additional voltage has to be applied to the pin PROG. It has to be buffered by a fast 100nF capacitor (ceramic) and a 10F capacitor. The information to be programmed is set by command 25. The OTP bits 16 until 45 are used for AMS factory trimming and cannot be overwritten. Symbol Parameter Min Max Unit VDD Supply Voltage 5 5.5 V GND Ground level 0 0 V V_zapp Programming Voltage 8 8.5 V T_zapp Temperature 0 85 C f_clk CLK Frequency 100 kHz Note At pin PROG At pin DCLK After programming, the programmed OTP bits can be verified in two ways: By Digital Verification: This is simply done by sending a READ OTP command (#15). The structure of this register is the same as for the OTP PROG or OTP WRITE commands. By Analog Verification: By switching into Extended Mode and sending an ANALOG OTP READ command (#9), pin PROG becomes an output, sending an analog voltage with each clock representing a sequence of the bits in the OTP register (starting with D45). A voltage of <500mV indicates a correctly programmed bit ("1") while a voltage level between 2V and 3.5V indicates a correctly unprogrammed bit ("0"). Any voltage level in between indicates incorrect programming. Figure 10. Analog OTP Verification +5V VDD VDD VDD CS Output DCLK I/O DIO Micro Controller AS5115 Output AS5130 100n PROG VSS VSS V VSS www.austriamicrosystems.com/AS5115 Revision 1.11 14 - 20 AS5115 Datasheet - D e t a i l e d D e s c r i p t i o n 7.10 Pre-programmed Version Table 13. Pre-programmed Version Sensitivity Output Output DC Offset AS5115 YYWWMZZ Not programmed 1.5V 0 Not programmed Untrimmed AS5115A YYWWMZZ 28 mV/mT 2.5V 1 00 12.15A Version Marking AS5115 AS5115A www.austriamicrosystems.com/AS5115 Revision 1.11 PGA Gain Setting Hall Bias Current 15 - 20 AS5115 Datasheet - A p p l i c a t i o n I n f o r m a t i o n 8 Application Information Figure 11. Vertical Cross Section of SSOP-16 Notes: 1. All dimensions in mm. www.austriamicrosystems.com/AS5115 Revision 1.11 16 - 20 AS5115 Datasheet - P a c k a g e D r a w i n g s a n d M a r k i n g s 9 Package Drawings and Markings The devices are available in a 16-Lead Shrink Small Outline package. Figure 12. Package Drawings and Dimensions Symbol A A1 A2 b c D E E1 e L L1 L2 R N Min 1.73 0.05 1.68 0.22 0.09 5.90 7.40 5.00 0.55 0.09 0 Nom 1.86 0.13 1.73 0.30 0.17 6.20 7.80 5.30 0.65 BSC 0.75 1.25 REF 0.25 BSC 4 16 Max 1.99 0.21 1.78 0.38 0.25 6.50 8.20 5.60 0.95 8 Notes: 1. Dimensions and tolerancing conform to ASME Y14.5M-1994. 2. All dimensions are in millimeters. Angles are in degrees. Marking: YYWWMZZ. YY WW M ZZ Last two digits of the manufacturing year Manufacturing week Plant identifier Assembly traceability code www.austriamicrosystems.com/AS5115 Revision 1.11 17 - 20 AS5115 Datasheet - R e v i s i o n H i s t o r y Revision History Revision Date 1.0 Jul 03, 2008 Initial revision 1.1 Jul 15, 2008 Key Features and pin description updated. 1.2 Jul 14, 2009 Updated min, typ, max values for `Power up time' parameter in Table 6. Nov 30, 2009 Deleted `Displacement' parameter from Table 5. Updated the following parameters in Table 6: - Values and conditions updated for 1. Propagation delay 2. Amplitude ratio tracking accuracy over temperature 3. DC Offset Drift - Deleted the `Output Offset' parameter from the table. Updated following bits related information on page 8 - invert_channel, cm_sin, cm_cos, gain, dc_offset, Hall_b Inserted Figure 3 and Figure 4 Updated Key Features (page 1), Table 11, and Figure 8 Hall Array Radius value updated from 1.1mm to 1mm 1.3 Owner Description apg 1.4 Dec 11, 2009 Updated values for `Magnetic Sensitivity' parameter in Table 6. Mar 02, 2010 Updated `Interface General at extended mode' (see Table 9) Updated values for `Power up time' parameter in Table 6. Added pin type in Table 1, updated reserved bits information in Table 11. Mar 19, 2010 Added `Current Consumption' parameter in Table 6. 1.5 Updated Table 5 and Table 6. Nov 10, 2010 sti 1.6 Feb 07, 2011 mub 1.7 Feb 16, 2011 sti Mar 22, 2011 mub Updated Package Drawings and Markings (page 17). Apr 07, 2011 apg Deleted Tubes variant in Ordering Information (page 19). 1.8 1.10 1.11 Updated Table 5. Updated Key Features, OTP Programming and Verification, Table 4, Table 6. May 26, 2011 Jun 10, 2011 1.9 Added Figure 11. Updated Package Drawings and Markings (page 17), Table 2 and Table 5. Removed magnet related detailed info. mub Updated Absolute Maximum Ratings (page 4). Sep 19, 2011 Updated Ordering Information (page 19). Dec 14, 2011 Added subversion AS5115A info in the datasheet. Feb 10, 2012 Updated Figure 9 added Note on page13. ekno Updated Table 6 and Figure 9 Mar 06, 2012 Note: Typos may not be explicitly mentioned under revision history. www.austriamicrosystems.com/AS5115 Revision 1.11 18 - 20 AS5115 Datasheet - O r d e r i n g I n f o r m a t i o n 10 Ordering Information The devices are available as the standard products shown in Table 14. Table 14. Ordering Information Ordering Code AS5115-HSSP AS5115A-HSSP Description Delivery Form Buffered Sine and Cosine output signals Package Tape & Reel 16-pin SSOP Tape & Reel 16-pin SSOP Note: All products are RoHS compliant and austriamicrosystems green. Buy our products or get free samples online at ICdirect: http://www.austriamicrosystems.com/ICdirect Technical Support is available at http://www.austriamicrosystems.com/Technical-Support For further information and requests, please contact us mailto: sales@austriamicrosystems.com or find your local distributor at http://www.austriamicrosystems.com/distributor www.austriamicrosystems.com/AS5115 Revision 1.11 19 - 20 AS5115 Datasheet - C o p y r i g h t s Copyrights Copyright (c) 1997-2012, austriamicrosystems AG, Tobelbaderstrasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered (R). All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. All products and companies mentioned are trademarks or registered trademarks of their respective companies. Disclaimer Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems AG rendering of technical or other services. Contact Information Headquarters austriamicrosystems AG Tobelbaderstrasse 30 A-8141 Unterpremstaetten, Austria Tel: +43 (0) 3136 500 0 Fax: +43 (0) 3136 525 01 For Sales Offices, Distributors and Representatives, please visit: http://www.austriamicrosystems.com/contact www.austriamicrosystems.com/AS5115 Revision 1.11 20 - 20