LH28F008SAT-12 - Sharp Electronics Corp.

LH28F008SA

8M (1M × 8) Flash Memory

Figure 1. 40-Pin TSOP Configuration

FEATURES

•Ver y High-Perfor mance Read

– 85 ns Maximum Access Time

•High-Density Symmetrically Blocked

Architecture

– Sixteen 64K Blocks

•Extended Cycling Capability

– 100,000 Block Erase Cycles

– 1.6 Million Block Erase Cycles per Chip

•Automated Byte Wr ite and Block Erase

– Command User Interface

– Status Register

•System Perfor mance Enhancements

–RY»/BY» Status Output

– Erase Suspend Capability

•Deep-Powerdown Mode

– 0.20 µA ICC Typical

•SRAM-Compatibl e Write Interface

•Hardware Data Protection Feature

– Erase/Write Lockout during

Pow er Transitions

•Independent Software Vendor Support

– Microsoft Flash File System™ (FFS)

•ETOX™ Nonvolatile Flash Technology

– 12 V Byte Write/Bloc k Erase

•Industr y Standard Packaging

– 40-Pin 1.2 mm × 10 mm × 20 mm

TSOP (Type I) Package

– 44-Pin 600-mil SOP Package

28F008SA-1

TOP VIEW40-PIN TSOP

34

RY/BY

38 WE

13 28 DQ

1NC

PWD

GND

LH28F008SA 8M (1M × 8) Flash Memory

28F008SA-16

TOP VIEW

38



42 A

13 32

44-PIN SOP



RY/BY

GND

GND V

22 23

Figure 2. 44-Pin SOP Configuration

INTRODUCTION

SHARP’S LH28F008SA 8M Flash File™ Memory is

the highest density nonvolatile read/write solution for

solid state storage. The LH28F008SA’s extended

cycling, symmetrically blocked architecture, f ast access

time, write automation and low power consumption pro-

vide a more reliable, lower power, lighter weight and

higher performance alternative to traditional rotating disk

technology. The LH28F008SA brings new capabilities

to por table computing. Application and operating sys-

tem software stored in resident flash memory arrays

provide instant-on rapid execute-in-place and protec-

tion from obsolescence through in-system software

updates. Resident software also extends system bat-

tery life and increases relaibility by reducing disk drive

accesses.

For high density data acquisition applications, the

LH28F008SA offers a more cost-effective and reliable

alternative to SRAM and battery. Traditional high

density embedded applications, such as telecommuni-

cations, can take advantage of the LH28F008SA’s

nonv olatility , b locking and minimal system code require-

ments for flexible firmware and modular software

designs.

The LH28F008SA is offered in 40-pin TSOP (stan-

dard) package. Pin assignments simplify board layout

when integrating multiple devices in a flash memory

array or subsystem. This device uses an integrated

Command User Interf ace and state machine for simpli-

fied block erasure and byte write. The LH28F008SA

memory map consists of 16 separately erasable

64K b locks .

SHARP’s LH28F008SA employs advanced CMOS

circuitry for systems requiring low power consumption

and noise immunity. Its 85 ns access time provides

superior performance when compared with magnetic

storage media. A deep powerdo wn mode lowers power

consumption to 1 µW typical through V CC, crucial in por-

table computing, handheld instrumentation and other

low-power applications. The PWD power control input

also provides absolute data protection during system

power up/do wn.

DESCRIPTION

The LH28F008SA is a high-performance 8M

(8,388,608 bit) memory organized at 1M (1,048,576

bytes) of 8 bits each. Sixteen 64K (65,536 Byte) bloc ks

are included on the LH28F008SA. A memory map is

shown in Figure 4 of this specification. A block erase

operation erases one of the sixteen blocks of memory

in typically 1.6 seconds, independent of the remaining

blocks. Each block can be independently erased and

written 100,000 cyles. Erase Suspend mode allows sys-

tem software to suspend block erase to read data or

execute code from any other block of the LH28F008SA.

The LH28F008SA is available in the 40-pin TSOP

(Thin Small Outline Package, 1.2 mm thick) package.

Pinouts are shown in Figure 1 of this specification.

The Command User Interface serves as the inter-

face between the microprocessor or microcontroller and

the internal operation of the LH28F008SA.

Byte Write and Block Erase Automation allow byte

write and block erase operations to be executed using

a two-write command sequence to the Command User

Interface. The internal W rite State Machine (WSM)

automatically executes the algorithms and timings nec-

essary for byte write and block erase operations,

including v erifications, thereby unb urdening the micro-

processor or microcontroller . Writing of memory data is

perfor med in byte increments typically within 9 µs, an

80% improv ement over current flash memory products.

IPP b yte write and bloc k erase currents are 10 mA typi-

cal, 30 mA maximum. VPP byte write and block erase

voltage is 11.4 V to 12.5 V.

The Status Register indicates the status of the WSM

and when the WSM successfully completes the desired

byte write or b loc k er ase operation.

8M (1M × 8) Flash Memory LH28F008SA

Figure 3. LH28F008SA Block Diagram

OUTPUT

BUFFER

IDENTIFIER

STATUS

INPUT

BUFFER

- A

- DQ

ADDRESS

LATCH

I/O LOGIC

DATA

COMPARATOR

WRITE STATE

MACHINE RY/BY

PWD

PROGRAM/

ERASE

VOLTAGE

SWITCH

Y-GATING

OUTPUT

MULTIPLEXER

Y-DECODER

X-DECODER

COMMAND

USER

INTERFACE

INPUT

BUFFER

. . .

ADDRESS

COUNTER V

GND

16 64KB BLOCKS

28F008SA-2

LH28F008SA 8M (1M × 8) Flash Memory

PIN DESCRIPTION

SYMBOL TYPE NAME AND FUNCTION

A0 - A19 INPUT ADDRESS INPUTS: For memory addresses. Addresses are internally latched during

a writ e cycle.

DQ0 - DQ7INPUT/OUTPUT

DATA INPUT/OUTPUTS: Inputs data and commands during Command User Interface

write cycles; outputs data during memory array. Status Register and Identifier read

cycles. The data pins are active high and float to tri-state off when the chip is deselected

or the outputs are disabled. Data is internally latched during a write cycle.

»INPUT CHIP ENABLE: Activates the device’s control logic input buffers, decoders, and

sense amplifiers. CE

» i s ac tive l ow: CE

» high deselects the memory device and

reduces power consumption to standby levels.

PWD INPUT POWERDOWN: Puts the device in deep powerdown mode. PWD is active low; PWD

high gates normal operation. PWD also locks out block erase or byte write

operations when active low, providing data protection during power transitions.

»INPUT OUTPUT ENABLE: Gates the device’s outputs through the data buffers during a

read cycle. OE

» is active low.

WE INPUT WRITE ENABLE: Controls writes to the Command User Interface and array blocks.

WE is active low. Addresses and data are latched on the rising edge of the

WE P ul se .

» /BY

»OUTPUT

READY/BUSY: Indicates the status of the internal Write State Machine. When low, it

indicates that the WSM is performing a block erase or byte write operation. RY

»/BY

high indicates that the WSM is ready for new commands, block erase is suspended or

the device is in deep powerdown mode. RY

»/BY

»is always active and does NOT float

to tri-state off when the chip is deselected or data outputs are disabled.

VPP SUPPLY BLOCK ERASE/BYTE WRITE POWER SUPPLY: for erasing blocks of the array or

writing bytes of each block.

NOTE: With VPP < VPPLMAX, memory contents cannot be altered.

VCC DEVICE POWER SUPPLY: (5 V ±10%, 5 V ±5%)

GND SUPPLY GROUND

8M (1M × 8) Flash Memory LH28F008SA

Commands are written using standard microproces-

sor write timings. Command User Interface contents

serve as input to the WSM, which controls the block

erase and byte write circuitry. Write cycles also inter-

nally latch addresses and data needed f or byte write or

bloc k erase operations. With the appropriate command

written to the register, standard microprocessor read

timings output array data, access the intelligent identi-

fier codes, or output byte write and block erase status

f or verification.

The RY»/BY» output gives an additional indicator of

WSM activity, providing capability for both hardware sig-

nal of status (v ersus software polling) and status mask-

ing (interrupt masking for background erase, for

example). Status polling using RY»/BY» minimizes both

CPU overhead and system power consumption. When

low, RY»/BY» indicates that the WSM is perf orming a bloc k

erase or byte write operation. RY»/BY» high indicates that

the WSM is ready for new commands, block erase is

suspended or the de vice is in deep power do wn mode.

Maximum access time is 85 ns (tACC) over the com-

mercial temperature range (0°C to +70°C) and over V CC

supply voltage range (4.5 V to 5.5 V and 4.75 V to

5.25 V). ICC activ e current (CMOS Read) is 20 mA typi-

cal, 35 mA maximum at 8 MHz.

When the CE» and PWD pins are at VCC, the ICC

CMOS Standb y mode is enabled.

A Deep P owerdown mode is enab led when the PWD

pin is at GND, minimizing power consumption and pro-

viding write protection. ICC current in deep pow er down

is 0.20 µA typical. Reset time of 400 ns is required from

PWD switching high until outputs are valid to read

attempts. Equivalently, the device has a wake time of

1 µs from PWD high until writes to the Command User

Interface are recognized by the LH28F008SA. With PWD

at GND, the WSM is reset and the Status Register is

cleared.

PRINCIPLES OF OPERATION

The LH28F008SA includes on-chip write automation

to manage write and erase functions. The W rite State

Machine allows f or 100% TTL-lev el control inputs; fixed

power supplies during block erasure and byte write; and

minimal processor overhead with SRAM like interface

timings.

After initial device powerup, or after return from deep

powerdown mode (see Bus Operations), the

LH28F008SA functions as a read-only memory. Manipu-

lation of external memory-control pins allow arra y read,

standby and output disable operations. Both Status

through the Command User Interface when VPP = VPPL.

This same subset of operations is also available when

high voltage is applied to the VPP pin. In addition, high

voltage on VPP enables successful block erasure and

byte writing of the de vice . All functions associated with

altering memory contents - byte write, block erase,

status and intelligent identifier - are accessed via the

Command User Interface and verified through the

Status Register .

Figure 4. Memor y Map

MEMORY MAP

FFFFF

F0000

EFFFF

E0000

DFFFF

D0000

CFFFF

C0000

BFFFF

B0000

AFFFF

A0000

9FFFF

90000

8FFFF

80000

7FFFF

70000

6FFFF

60000

5FFFF

50000

4FFFF

40000

3FFFF

30000

2FFFF

20000

1FFFF

10000

0FFFF

00000

64KB BLOCK

28F008SA-4

LH28F008SA 8M (1M × 8) Flash Memory

Figure 3. LH28F008SA Array Interface to 386SL Microprocessor Superset through PI Bus

(Including RY»/BY» Masking and Selective Powerdown), for DRAM

Backup during System SUSPEND, Resident O/S and

Applications and Motherboard Solid-State Disk.

LATCH

XCVR

82360SL

CONTROLLER

80386SL

µPLD

LH28F008SA

CS

TO OTHER

LH28F008SA's

EPLD(s)

RESET

PWRGOOD

PSTART

PCMD

PM/IO

PW/R

FLSHDCS

PRDY

CTRL

RY/BY1

RY/BY2

VGACS

INT

28F008SA-3

SBHE

SA0 - SA16

LA17 - LA20 SA1 - SA16

LA17 - LA20

SA0

LA21 - LA22 A0 - A19

A0 - A19

VPP

VPP

SWITCH

DQ0 - DQ7

FD0 - FD7

FD8 - FD15

SD0 - SD15

RY/BY

VPP

SBHE

RY/BY

FROM OTHER

LH28F008SA's

PWD

TO OTHER

LH28F008SA

PAIRS

PWD

RY/BY

CSL1CE

WR WE

CS1

CS2

CS3

RD OE

CSH1

GPIO

RESET

12 V

RY/BY

PWD

8M (1M × 8) Flash Memory LH28F008SA

Interface software to initiate and poll progress of

internal byte write and block erase can be stored in an y

of the LH28F008SA bloc ks . This code is copied to , and

executed from, system RAM during actual flash memory

update. After successful completion of byte write

and/or block erase, code/data reads from the

LH28F008SA are again possible via the Read Array

command. Erase suspend/resume capability allows

system software to suspend block erase to read data

and e xecute code from any other block.

Command User Interface and

Write A utomation

An on-chip state machine controls block erase and

byte write, freeing the system processor f or other tasks.

After receiving the Erase Setup and Erase Confirm com-

mands, the state machine controls b lock pre-condition-

ing and erase, returning progress via the Status Register

and R Y»/BY» output. Byte write is similarly controlled, af-

ter destination address and expected data are supplied.

The program and erase algorithms of past standard

Flash memories are now regulated by the state ma-

chine, including pulse repetition where required and in-

ternal v erification and margining of data.

Data Protection

Depending on the application, the system designer

may choose to make the VPP power switchable (avail-

able only when memory byte writes/block erases are

required) or hardwired to VPPH. When V PP =

VPPL, memory contents cannot be altered. The

LH28F008SA Command User interface architecture pro-

vides protection from unwanted b yte write or block erase

operations even when high voltage is applied to VPP.

Additionally, all functions are disabled whene v er V CC is

below the write lockout voltage VLKO, or when PWD is

at VIL. The LH28F008SA accomodates either design

practice and encourages optimization of the processor-

memory interf ace.

The two-step byte write/block erase Command User

Interface wr ite sequence provides additional software

write protection.

BUS OPERATION

Flash memory reads, erases and writes in-system

via the local CPU. All bus cycles to or from the flash

memory conform to standard microprocessor bus

cycles.

Read

The LH28F008SA has three read modes. The

memor y can be read from any of its blocks, and infor-

mation can be read from the intelligent identifier or Sta-

tus Register. VPP can be at either VPPL or VPPH.

Bus Operations

NOTES:

1. Refer to DC Characteristics. When VPP = VPPL, memory contents can be read but not wr itten or erased.

2. X can be VIL or VIH for control pins and addresses, and VPPL or VPPH for VPP. See DC Character istics for VPPL and VPPH voltages.

3. RY»/BY» is VOL when the Write State Machine is executing internal block erase or byte write algor ithms. It is V OH when the WSM is

not busy, in Er ase Suspend mode or deep powerdown mode.

4. Command writes involving block erase or byte write are only successfully executed when VPP = VPPH.

5. Refer to the Command Definitions Ta ble for valid DIN during a wr ite operation.

MODE PWD CE

»OE

»WE A0VPP DQ0 - DQ7RY

»/BY

»NOTE

Read VIH VIL VIL VIH XXD

OUT X1, 2, 3

Output Di sable VIH VIL VIH VIH XXHigh-Z X 3

Standby VIH VIH XXXXHigh-Z X 3

Deep Power Down VIL XXXXXHigh-ZV

Intelligent Identifier (Mfr) VIH VIL VIL VIH VIL X89HV

Intelli gent Identif ier (Device) VIH VIL VIL VIH VIH XA2HV

Write VIH VIL VIH VIL XX D

IN X3, 4, 5

LH28F008SA 8M (1M × 8) Flash Memory

The first task is to write the appropr iate read mode

command to the Command User Interf ace (arra y, intel-

ligent identifier, or Status Register). The LH28F008SA

automatically resets to Read Array mode upon initial

device powerup or after exit from deep powerdown. The

LH28F008SA has four control pins, two of which must

be logically active to obtain data at the outputs. Chip

Enable (CE») is the device selection control, and when

active enables the selected memory device. Output

Enable (OE

»

) is the data input/output (DQ0 - DQ7)

direction control, and when activ e drives data from the

selected memory onto the I/O bus . PWD and WE

»

must

also be at VIH. Figure 8 illustrates read b us cycle wa ve-

forms.

Output Disable

With OE

»

at a logic-high level (VIH), the device out-

puts are disabled. Output pins (DQ0 - DQ7) are placed

in a high-impedance state.

Standby

CE» at a logic-high le vel (VIH) places the LH28F008SA

in standby mode. Standby operation disables much of

the LH28F008SA’s circuitry and substantially reduces

device power consumption. The outputs (DQ0 - DQ7)

are placed in a high-impedance state independent of

the status of OE

»

. If the LH28F008SA is deselected dur-

ing block erase or byte write, the device will continue

functioning and consuming normal active power until

the operation completes.

Deep Power-Down

The LH28F008SA offers a deep power-down feature,

entered when PWD is at VIL. Current draw through VCC

is 0.20 µA typical in deep powerdown mode, with cur-

rent draw through VPP typically 0.1 µA. During read

modes, PWD-low deselects the memory, places output

drivers in a high-impedence state and turns off all inter-

nal circuits. The LH28F008SA requires time tPHQV (see

AC Characteristics-Read-Only Operations) after return

from powerdown until initial memory access outputs are

valid. After this wak eup interval, normal operation is re-

stored. The Command User interface is reset to Read

Array, and the upper 5 bits of the Status Register are

cleared to v alue 100,000, upon return to normal opera-

tion.

During block erase or byte write modes, PWD low

will abort either operation. Memory contents of the bloc k

being altered are no longer valid as the data will be par-

tially written or erased. Time tPHWL after PWD goes to

logic-high (VIH) is required before another command can

be written.

COMMAND BUS

CYCLES

REQ'D

FIRST BUS CYCLE SECOND BUS CYCLE NOTE

OPER. ADDRESS DATA OPER. ADDRESS DATA

Read Array/Reset 1 Write X FFH 1

Intelligent Identifier 3 Write X 90H Read IA IID 2, 3, 4

Read Status Register 2 Write X 70H Read X SRD 3

Clear Status Register 1 Write X 50H

Erase Setup/Erase Confirm 2 Write BA 20H Write BA D0H 2

Erase Suspend/Erase Resume 2 Write X B0H Write X D0H

Byte Wri te Se tup/Writ e 2 Wri te WA 40H Write WD WD 2, 3, 5

Alternate Byte Write Setup/Write 2 Write WA 10H Write WD WD 2, 3, 5

Command Definitions

NOTES:

1. Bus operations are defined in Bus Operations Table.

2. IA = Identifier Address: D0H for manufacturer code, 01H for device code.

BA = Address within the block being erased.

WA = Address of memor y location to be written.

3. SRD = Data read from Status Register. See Status Register Definitions Table for a descr iption of the Status Register bits.

WD = Data to be written at location WA. Data is latched on the rising edge of WE

»

IID = Data read from intelligent identifiers.

4. Following the intelligent identifier command, two read operations access manufacture and device codes.

5. Either 40H or 10H are recognized by the WSM as the Byte Write Setup command.

6. Commands other than those shown above are reser ved by Intel for future device implementations and should not be used.

8M (1M × 8) Flash Memory LH28F008SA

Intelligent Identifier Operation

The intelligent identifier operation outputs the manu-

facturer code 89H; and the device code, A2H for the

LH28F008SA. The system CPU can then automatically

match the device with its proper block erase and byte

write algorithms.

The manufacturer and device-codes are read via the

Command User Interface. Following a write of 90H to

the Command User Interface, a read from address

location 00000H outputs the manuf acturer code (89H).

A read from address 00001H outputs the device code

(A2H). It is not necessary to have high voltage applied

to VPP to read the intelligent identifiers from the Com-

mand User Interf ace.

Write

Writes to the Command User Interface enab le read-

ing of device data and intelligent identifiers. They also

control inspection and clearing of the Status Register.

Additionally, when VPP = VPPH, the Command User

Interface controls bloc k erasure and byte write. The con-

tents of the interface register serve as input to the inter-

nal state machine.

The Command User Interface itself does not occupy

an addressable memory location. The interface register

is a latch used to store the command and address and

data information needed to ex ecute the command. Erase

Setup and Erase Confirm commands require both

appropriate command data and an address within the

block to be erased. The Byte Write Setup command

requires both appropriate command data and the ad-

dress of the location to be written, while the Byte Write

command consists of the data to be written and the

address of the location to be written.

The Command User Interface is written by bringing

»

to a logic-low level (VIL) while CE» is low . Addresses

and data are latched on the rising edge of WE

»

. Stan-

dard microprocessor write timings are used.

Ref er to A C Write Characteristics and the A C W a ve-

f orms for Write Operations, Figure 9, for specific timing

parameters.

COMMAND DEFINITIONS

When VPPL is applied to the VPP pin, read operations

from the Status Register, intelligent identifiers, or arra y

blocks are enabled. Placing VPPH on VPP enab les suc-

cessful byte write and b lock erase operations as well.

Device operations are selected by writing specific

commands into the Command User Interface. Command

Definitions Table defines the LH28F008SA commands.

WSMS ESS ES BWS VPPS R R R

76543210

SR.7 = WRITE STATE MACHINE STATUS (WSMS)

1 = Ready

0 = Busy

SR.6 = ERASE-SUSPEND STATUS (ESS)

1 = Erase Suspended

0 = Erase in Progress/Completed

SR.5 = ERASE STATUS (ES)

1 = Error in Block Erasure

0 = Successful Block Erase

SR.4 = BYTE WRITE STATUS (BWS)

1 = Error in Byte Write

0 = Successful Byte Write

SR.3 = VPP STATUS (VPPS)

1 = VPP Low Detect, Operation Abor t

0 = VPP OK

NOTES:

1. RY»/BY» or the Wr ite State Machine Status bit must first be

checked to deter mine byte write or block erase operation,

before the Byte Wr ite or Erase Status bit are checked to

success.

2. If the Byte Write AND Erase Status bits are set to '1's

dur ing a block erase attempt, an improper command se-

quence was entered. Attempt the operation again.

3 . If VPP low status is detected, the Status Register must be

cleared before another byte write or block erase operation

is attempted. The VPP Status bit, unlike an A/D converter,

does not provide continuous indication of VPP level. The

WSM interrogates the VPP level only after the byte wr ite or

block erase command sequences have been entered and

infor ms the system if VPP has not been switched on. The

VPP Status bit is not gauranteed to repor t accurate feed-

back between VPPL and VPPH.

4. SR.2 - SR.0 = Reserved for future enhancements.

These bits are reser ved for future use and should be

masked out when polling the Status Register.

Status Register Definitions

LH28F008SA 8M (1M × 8) Flash Memory

Read Array Command

Upon initial de vice powerup and after e xit from deep

powerdown mode, the LH28F008SA defaults to Read

Array mode. This operation is also initiated by writing

FFH into the Command User Interf ace. Microprocessor

read cycles retriev e arra y data. The de vice remains en-

ab led f or reads until the Command User Interf ace con-

tents are altered. Once the internal Write State Machine

has star ted a block erase or byte write operation, the

device will not recognize the Read Arra y command, until

the WSM has completed its operation. The Read Arra y

command is functional when VPP = VPPL or VPPH.

Intelligent Identifier Command

The LH28F008SA contains an intelligent identifier

operation, initiated by writing 90H into the Command

User Interface. Following the command write, a read

cycle from address 00000H retriev es the manuf acturer

code of 89H. A read cycle from address 00001H

returns the device code of A2H. To terminate the opera-

tion, it is necessary to write another valid command into

the register. Like the Read Array command, the intelli-

gent identifier command is functional when VPP = VPPL

or VPPH.

Read Status Register Command

The LH28F008SA contains a Status Register which

may be read to deter mine when a byte write or block

erase operation is complete, and whether that opera-

tion completed successfully. The Status Register may

be read at any time by writing the Read Status Register

command (70H) to the Command User Interf ace. After

writing this command, all subsequent read operations

output data from the Status Register , until another valid

command is written to the Command User Interface.

The contents of the Status Register are latched on the

falling edge of OE

»

or CE», whichever occurs last in the

read cycle. OE

»

or CE» must to toggled to VIH before

further reads to update the Status Register latch.

The Read Status Register command functions when

VPP = VPPL or VPPH.

Clear Status Register Command

The Erase Status and Byte Write Status bits are set

to '1's by the Write State Machine and can only be reset

by the Clear Status Register Command. These bits

indicate v arious f ailure conditions (see Status Register

Definitions). By allowing system software to control the

resetting of these bits, several operations may be per-

formed (such as cumulatively writing several bytes or

erasing multiple blocks in sequence). The Status Reg-

ister may then be polled to determine if an error

occurred during that sequence. This adds flexibility to

the way the device may be used.

Additionally, the VPP Status bit (SR.3) MUST be re-

set by system software before further byte writes or block

erases are attempted. To clear the Status Register , the

Clear Status Register command (50H) is written to the

Command User Interface. The Clear Status Register

command is functional when VPP = VPPL or VPPH.

Erase Setup/Erase Confirm Commands

Erase is executed one block at a time, initiated by a

two-cycle command sequence. An Erase Setup com-

mand (20H) is first written to the Command User Inter-

face, followed by the Erase Confir m command (D0H).

These commands require both appropriate sequenc-

ing and an address within the block to be erased to FFH.

Bloc k preconditioning, erase and v erify are all handled

internally by the Write State Machine, invisible to the

system. After the two-command erase sequence is writ-

ten to it, the LH28F008SA automatically outputs Status

The CPU can detect the completion of the erase e vent

by analyzing the output of the RY»/BY» pin, or the WSM

Status bit of the Status Register.

When erase is completed, the Erase Status bit should

be checked. If erase error is detected, the Status Reg-

ister should be cleared. The Command User Interface

remains in Read Status Register mode until further com-

mands are issued to it.

This two-step sequence of set-up followed by

execution insures that memory contents are not

accidentially erased. Also, reliable block erasure can only

occur when VPP = VPPH. In the absence of this high

voltage, memory contents are protected against era-

sure. If block erase is attempted while VPP = VPPL, the

VPP Status bit will be set to '1'. Erase attempts while

VPPL

< VPP < VPPH produce spurious results and should

not be attempted.

Erase Suspend/Erase Resume Commands

The Erase Suspend command allows block erase

interruption in order to read data from another bloc k of

memory. Once the erase process starts, writing the

Erase Suspend command (B0H) to the Command User

Interface requests that the WSM suspend the erase

sequence at a predeter mined point in the erase algo-

rithm. The LH28F008SA continues to output Status

mand is written to it. P olling the WSM Status and Erase

Suspend Status bits will determined when the erase

operation has been suspended (both will be set to '1').

RY»/BY» will also transition to VOH.

8M (1M × 8) Flash Memory LH28F008SA

At this point, a Read Arra y command can be written

to the Command User Interface to read data from blocks

other than that which is suspended. The only other valid

commands at this time are Read Status Register (70H)

and Erase Resume (D0H), at which time the WSM will

continue with the erase process. The Erase Suspend

Status and WSM Status bits of the Status Register will

be automatically cleared and R Y »/BY» will return to VOL.

After the Erase Resume command is written to it, the

LH28F008SA automatically outputs Status Register data

when read (see Erase Suspend/Resume

Flowchart). VPP must remain at VPPH while the

LH28F008SA is in Erase Suspend.

Byte Write Setup/Write Commands

Byte write is ex ecuted by a two-command sequence.

The Byte Write Setup command (40H) is written to the

Command User Interface, followed by a second write

specifying the address and data (latched on the rising

edge of WE

»

) to be written. The WSM then takes over,

controlling the byte write and write verify algorithms

internally. After the two-command byte write sequence

is written to it, the LH28F008SA automatically outputs

Status Register data when read (see Byte Write Flow-

chart). The CPU can detect the completion of the byte

write ev ent by analyzing the output of the R Y»/BY» pin, or

the WSM Status bit of the Status Register. Only the Read

Status Register command is valid while byte write is

active.

When byte wr ite is complete, the Byte Write Status

bit should be checked. If byte write error is detected,

the Status Register should be cleared. The internal

WSM v erify only detects errors f or '1's that do not suc-

cessfully write to '0's. The Command User Interf ace re-

mains in Read Status Register mode until further

commands are issued to it. If byte write is attempted

while VPP = V PPL, the VPP Status bit will be set to '1'.

Byte write attempts while VPPL < VPP < VPPH produce

spurious results and should not be attempted.

EXTENDED BLOCK ERASE/BYTE

WRITE CYCLING

The LH28F008SA is designed for 100,000 byte write/

block erase cycles on each of the sixteen 64K blocks.

Low electric fields, adv anced oxides and minimal oxide

area per cell subjected to the tunneling electric field

combine to greatly reduce oxide stress and the prob-

ability of failure. A 20M solid-state drive using an array

of LH28F008SAs has a MTBF (Mean Time Between

Failure) of 33.3 million hours(1), over 600 times more

reliable than equiv alent rotating disk technology.

AUTOMATED BYTE WRITE

The LH28F008SA integrates the Quick-Pulse pro-

gramming algorithm using the Command User Interface,

Status Register and Write State Machine (WSM).

On-chip integration dramatically simplifies system soft-

ware and provides processor interface timings to the

Command User Interface and Status Register. WSM

operation, internal verify and V PP high voltage presence

are monitored and reported via the RY»/BY» output and

appropriate Status Register bits. Figure 5 sho ws a sys-

tem software flo wchart for de vice b yte write. The entire

sequence is performed with VPP at VPPH.

Byte write abort occurs when PWD transitions to VIL,

or VPP drops to VPPL. Although the WSM is halted, byte

data is partially written at the location where b yte write

aborted. Block erasure, or a repeat of byte write, is re-

quired to initialize this data to a kno wn v alue .

AUTOMATED BLOCK ERASE

As above, the Quick-Erase algorithm is now imple-

mented internally, including all preconditioning of bloc k

data. WSM operation, erase success and VPP high volt-

age presence are monitored and reported through

RY»/BY» and the Status Register. Additionally, if a com-

mand other than Erase Confirm is written to the device

f ollo wing Erase Setup, both the Erase Status and Byte

Write Status bits will be set to '1's. When issuing the

Erase Setup and Erase Confirm commands, they should

be written to an address within the address range of the

block to be erased. Figure 6 shows a system software

flowchart for block erase.

Erase typically takes 1.6 seconds per block.

The Erase Suspend/Erase Resume command

sequence allows suspension of this er ase operation to

read data from a b lock other than that in which erase is

being performed. A system software flowchart is shown

in Figure 7.

The entire sequence is perf ormed with VPP at VPPH.

Abor t occurs when PWD transitions to VIL or VPP fails

to VPPL, while erase is in progress. Block data is par-

tially erased b y this oper ation, and a repeat of erase is

required to obtain a fully erased b loc k.

LH28F008SA 8M (1M × 8) Flash Memory

DESIGN CONSIDERATIONS

Three-Line Output Control

The LH28F008SA will often be used in large memory

arra ys . Intel provides three control inputs to accommo-

date multiple memory connections. Three-line control

provides f or:

•Lowest possib le memory power dissipation

•Complete assurance that data b us contention will

not occur

To efficiently use these control input, an address de-

coder should enable CE », while OE

»

should be connected

to all memor y devices and the system’s READ control

line. This assures that only selected memor y devices

have active outputs while deselected memory devices

are in Standby Mode. Finally, PWD should either be tied

to the system RESET, or connected to VCC if un used.

NOTE:

1. Assumptions: 10K file wr itten ever y 10 minutes.

(20M array 10K file) = 2,000 file writes before erase required.

(2000 files writes/erase) × (100,000 cycles per LH28F008SA

block) = 200 million file writes. (200 × 106 file writes) × 10

minutes/write) × 1 hr/60 minutes) = 33.3 × 102 MTBF.

RY»/BY» and Byte Write/Block Erase Polling

RY»/BY» is a full CMOS output that provides a hard-

ware method of detecting byte write and block erase

completion. It tr ansitions low time tWHRL after a write or

erase command sequence is written to the

LH28F008SA, and retur ns to VOH when the WSM has

finished e x ecuting the internal algorithm.

RY»/BY» can be connected to the interrupt input of the

system CPU or controller. It is active at all times, not

instated if the LH28F008SA CE » or OE

»

inputs are brought

to VIH. RY»/BY» is also VOH when the device is in Erase

Suspend or deep pow erdo wn modes.

Power Supply Decoupling

Flash memory power switching characteristics

require careful device decoupling. System designers are

interested in 3 supply current issues: standby current

levels (ISB), active current levels (ICC) and transient

peaks produced by falling and rising edges of CE». T ran-

sient current magnitudes depend on the device outputs’

capacitive and inductive loading. Two-line control and

proper decoupling capacitor selection will supress tran-

sient v oltage peaks. Each device should ha v e a 0.1 µF

ceramic capacitor connected between each VCC and

GND, and between its VPP and GND. These high fre-

quency, low inherent-inductance capacitors should be

placed as close as possible to package leads. Addition-

ally, for every 8 devices, a 4.7 µF electrolytic capacitor

should be placed at the array’s power supply connec-

tion between VCC and GND . The bulk capacitor will ov er-

come voltage slumps caused by PC board trace

inductances.

VPP Trace on Printed Circuit Boards

Writing flash memories, while they reside in the

target system, requires that the printed circuit board

designer pay attention to the VPP power supply trace.

The VPP pin supplies the memory cell current for writ-

ing and erasing. Use similar trace widths and la yout con-

siderations given to the VCC power bu s. Adequate VPP

Supply traces and decoupling will decrease VPP volt-

age spikes and ov ershoots.

VCC, VPP, PWD Transitions and the

Command/Status Registers

Byte write and block er ase completion are not guar-

anteed if VPP drops below VPPH. If the VPP Status bit

of the Status Register (SR.3) is set to '1', a Clear Status

write/block erase attempts are allowed by the WSM.

Otherwise, the Byte Write (SR.4) or Erase (SR.5) Sta-

tus bits of the Status Register will be set to '1's if error is

detected. PWD transitions to VIL during byte write and

block erase also abort the operations. Data is partially

altered in either case, and the command sequence must

be repeated after normal operation is restored. De vice

poweroff, or PWD transitions to VIL, clear the Status

The Command User Interface latches commands as

issued b y system software and is not altered b y VPP or

CE» transitions or WSM actions. Its state upon power

up , after e xit from deep pow erdo wn or after VCC tr ansi-

tions below VLKO, is Read Arra y Mode.

After byte write or block erase is complete, even

after VPP tr ansitions down to VPPL, the Command User

Interface must be reset to Read Array mode via the Read

Array command if access to the memory array is

desired.

Power Up/Down Protection

The LH28F008SA is designed to offer protection

against accidental block erasure or byte writing during

power tr ansitions. Upon power-up , the LH28F008SA is

indifferent as to which power supply, VPP or VCC, pow-

ers up first. Power supply sequencing is not required.

Inter nal circuitr y in the LH28F008SA ensures that the

Command User Interface is reset to the Read Array

mode on pow er up.

8M (1M × 8) Flash Memory LH28F008SA

Figure 5. Automated Byte Write Flowchart

START BUS

OPERATION COMMAND COMMENTS

WRITE 40H (10H),

BYTE ADDRESS

WRITE BYTE

ADDRESS/DATA

WSM

READY? NO

YES

FULL STATUS

CHECK IF DESIRED

BYTE WRITE

COMPLETED

BYTE WRITE

SUCCESSFUL

RANGE

ERROR

BYTE WRITE

ERROR

STATUS REGISTER

DATA READ

(see above)

SR.3 = 0

SR.4 = 0

Write

Standby/Read

Byte Write

Setup

Byte Write

Data = 40H (10H)

Addr = Byte to be written

Data to be written

Addr = Byte to be written

Check RY/BY

= Ready, V

= Busy

Repeat for subsequent bytes.

Full status check can be done after each byte or after a

sequence of bytes.

Write FFH after the last byte write operation to reset the

device to Read Array Mode.

Read Status Register

Check SR.7

1 = Ready, 0 = Busy

Toggle OE or CE to update

Status Register

BUS

OPERATION COMMAND

FULL STATUS CHECK PROCEDURE

COMMENTS

Optional

Read

Standby

CPU may already have read

Status Register data in WSM

Ready polling above

Check SR.3

1 = V

Low Detect

Check SR.4

1 = Byte Write Error

SR.3 must be cleared, if set during a byte write attempt,

before further attempts are allowed by the Write State

Machine.

SR.4 is only cleared by the Clear Status Register Command,

in cases where multiple bytes are written before full status is

checked.

If error is detected, clear the Status Register before

attempting retry or other error recovery.

28F008SA-5

LH28F008SA 8M (1M × 8) Flash Memory

Figure 6. Automated Block Erase Flowchar t

START BUS

OPERATION COMMAND COMMENTS

WRITE 20H

BLOCK ADDRESS

WRITE D0H

BLOCK ADDRESS

WSM

READY? NO

YES

ERASE SUSPEND

LOOP

YES

FULL STATUS

CHECK IF DESIRED

BLOCK ERASE

COMPLETED

BLOCK ERASE

SUCCESSFUL

VPP RANGE

ERROR

COMMAND

SEQUENCE

ERROR

STATUS REGISTER

DATA READ

(see above)

SUSPEND

ERASE?

SR.3 = 0

SR.4, 5 = 1

Write

Standby/Read

Erase

Setup

Erase

Data = 20H

Addr = Within block to be

erased

Data = D0H

Addr = Within block to be

erased

Check RY/BY

VOH = Ready, VOL = Busy

Repeat for subsequent bytes.

Full status check can be done after each block or after a

sequence of blocks.

Write FFH after the last block erase operation to reset the

device to Read Array Mode.

Read Status Register

Check SR.7

1 = Ready, 0 = Busy

Toggle OE or CE to update

Status Register

BUS

OPERATION COMMAND

FULL STATUS CHECK PROCEDURE

COMMENTS

Optional

Read

Standby

CPU may already have read

Status Register data in WSM

Ready polling above

Check SR.3

1 = VPP Low Detect

Check SR.4, 5

Both 1 = Command Sequence

Error

Check SR.5

1 = Block Erase Error

SR.3 must be cleared, if set during a block erase attempt,

before further attempts are allowed by the Write State

Machine.

SR.5 is only cleared by the Clear Status Register Command,

in cases where multiple blocks are erased before full status is

checked.

If error is detected, clear the Status Register before attempting

retry or other error recovery.

28F008SA-6

BLOCK ERASE

ERROR

SR.5 = 0

8M (1M × 8) Flash Memory LH28F008SA

Figure 7. Erase Suspend/Erase Resume Flowchart

START BUS

OPERATION COMMAND COMMENTS

READ STATUS

SR.7 = 1

SR.6 = 1

YES

CONTINUE ERASE

Write

Standby/Read

Standby

Write

Write Erase Resume

Read Array

Read

Erase

Suspend

Read

Status Register

Check RY/BY

= Ready,

= Busy or Read

Status Register

Check SR.7

1 = Ready, 0 = Busy

Toggle OE or CE to Update

Status Register

Check SR.6

1 = Suspended

Data = FFH

Read array data from block

other than that being erased.

Data = D0H

28F008SA-7

WRITE B0H

WRITE 70H

WRITE FFH

ERASE HAS

COMPLETED

WRITE D0H

DONE

READING



Data = B0H

Data = 70H

A system designer must guard against spurious

writes for VCC voltages abo ve VLKO when VPP is activ e.

Since both WE

»

and CE» must be low for a command

write, driving either to VIH will inhibit writes. The Com-

mand User Interface architecture provides an added

le vel of protection since alteration of memory contents

only occurs after successful completion of the two-setup

command sequences.

Finally, the device is disab led until PWD is brought to

VIH, regardless of the state of its control inputs. This

provides an additional le vel of memory protection.

Power Dissipation

When designing por table systems, designers must

consider battery power consumption not only during

device operation, but also for data retention during

system idle time. Flash nonvolatility increases usable

battery life, because the LH28F008SA does not con-

sume any power to retain code or data when the sys-

tem is off.

In addition, the LH28F008SA’s deep powerdown

mode ensures extremely low power dissipation even

when system power is applied. For example, por table

PCs and other power sensitive applications, using an

array of LH28F008SAs for solid-state storage, can lower

PWD to VIL in standby or sleep modes , producing neg-

ligible power consumption. If access to the LH28F008SA

is again needed, the part can again be read, following

the tPHQV and tPHWL wakeup cycles required after PWD

is first raised back to VIH. See AC Characteristics - Read-

Only and Write Operations and Figures 8 and 9 f or more

information.

LH28F008SA 8M (1M × 8) Flash Memory

WARNING: Stressing the device beyond the “Abso-

lute Maximum Ratings” may cause permanent dam-

age. These are stress ratings only. Operation beyond

the “Operating Conditions” is not recommended and

extended exposure bey ond the “Operating Conditions”

ma y aff ect de vice reliability.

SYMBOL PARAMETER MIN. MAX. UNITS NOTE

TAOperating Temperature 0 70.0 °C

VCC VCC Supply Voltage (10%) 4.50 5.50 V 5

VCC VCC Supply Voltage (5%) 4.75 5.25 V 5

NOTES:

1. Operating temperature is for commercial product defined by this specification.

2. Minimum DC voltage is -0.5 V on input/output pins. Dur ing transitions, this level may undershoot to -2.0 V for per iods < 20 ns.

Maximum DC voltage on input/output pins is VCC + 0.5 V which, dur ing transitions, may overshoot to VCC + 2.0 V for per iods < 20 ns.

3. Maximum DC voltage on VPP may overshoot to +14.0 V for per iods < 20 ns.

4. Output shor ted for no more than one second. No more than one output shor ted at a time.

5. 5% VCC specification reference the LH28F008SA-85 in its High Speed configuration, 10% VCC specifications reference the

LH28F008SA-85 in its Standard configuration, and the LH28F008SA-12.

ABSOLUTE MAXIMUM RATINGS*

Operating T emperature

During Read ......................................... 0°C to +70°C1

During Block Erase/Byte Write ...............0°C to +70°C

Temperature Under Bias .....................-10°C to +80°C

Storage Temperature.........................-65°C to +125°C

Voltage on Any Pin (except V CC and VPP)

with Respect to GND .....................-2.0 V to +7.0 V2

VPP Progr am Voltage with Respect to GND during

Block Erase/Byte Write .............-2.0 V to +14.0 V2, 3

VCC Supply Voltage with Respect

to GND...........................................-2.0 V to +7.0 V2

Output Short Circuit Current.......................... 100 mA4

DC CHARACTERISTICS

SYMBOL PARAMETER TYP. MIN. MAX. UNITS TEST CONDITIONS NOTE

ILI Input Load Current ±1.0 µA VCC = VCC MAX., VIN = VCC or GND 1

ILO Output Leakage Current ±10.0 µA VCC = VCC MAX., VOUT = VCC or GND 1

ICCS VCC Standby Current

1.0 2.0 mA VCC = VCC MAX., CE

» = PWD = VIH 1, 3

30 100.0 µA VCC = VCC MAX.,

» = PWD = Vcc ±0.2 V

ICCD VCC Deep Power Down

Current 0.20 1.2 µA PWD = GND ±0.2

IOUT (RY

»/BY

») = 0 mA 1

ICCR VCC Read Current

20 35.0 mA VCC = VCC MAX., CE

» = GND

f = 8 MHz, IOUT = 0 mA

CMOS Inputs 1

25 50.0 mA VCC = VCC MAX., CE

» = VIL

f = 8 MHz, IOUT = 0 mA

TTL Inputs

OPERATING CONDITIONS

8M (1M × 8) Flash Memory LH28F008SA

DC Characteristics (Continued)

SYMBOL PARAMETER TYP. MIN. MAX. UNITS TEST CONDITIONS NOTE

ICCW VCC Byte Write Current 10 30 mA Byte Write in Progress 1

ICCE VCC Block Erase Current 10 30 mA Block Erase in Progress 1

ICCES VCC Erase Suspend Current 5 10 mA Block Erase Suspended

» = VIH 1, 2

IPPS VPP Standby Current ±1 ±10 µA VPP ≤ VCC 1

90 200 µA VPP ≤ VCC

IPPD VPP Deep Power Down Current 0.10 5.0 µA PWD = GND ±0.2 V 1

IPPW VPP Byte Write Current 10 30 mA VPP = VPPH

Byte Write in Progress 1

IPPE VPP Block Erase Current 10 30 mA VPP = VPPH,

Block Erase in Progress 1

IPPES VPP Erase Suspend Current 90 200 µA VPP = VPPH,

Block Erase Suspended 1

VIL Input Low Voltage -0.5 0.8 V

VIH Input High Voltage 2.0 VCC + 0.5 V

VOL Output Low Voltage 0.45 V VCC = VCC MIN.

IOL = 5.8 mA 3

VOH Output High Voltage 2.4 V VCC = VCC MIN.

IOL = 2.5 mA 3

VPPL VPP duri ng Normal Operations 0.0 6.5 V 4

VPPH VPP during Write/Erase

Operations 12 11.4 12.6 V

VLKO VCC Erase/Write Lock Voltage 2.0 V

Capacitance5

TA = 25°C , f = 1MHz

SYMBOL PARAMETER TYP. MAX. UNITS TEST CONDITIONS

CIN Input Capacitance 6 8 pF VIN = 0 V

COUT Output Capacitance 8 12 pF VIN = 0 V

NOTES:

1. All currents are in RMS unless otherwise noted. Typical values at VCC = 5.0 V, VPP = 12.0 V, T = 25°C.

These currents are valid for all product versions (package and speeds).

2. ICCES is specified with the device deseleted. If the LH28F008SA is read while in Erase Suspend Mode,

current draw is the sum of ICCES and I CCR.

3. Includes RY»/BY».

4. Block Erases/Byte Wr ites are inhibited when VPP = VPPL and not guaranteed in the range between V PPH and VPPL.

5. Sampled, not 100% tested.

LH28F008SA 8M (1M × 8) Flash Memory

AC INPUT/OUTPUT

REFERENCE WA VEFORM1

AC TESTING LOAD CIRCUIT1

INPUT TEST POINTS OUTPUT

2.4

0.45

2.0

0.8 2.0

0.8

28F008SA-8

NOTE:

AC test inputs are driven at V

(2.4 V

TTL

) for a Logic '1' and V

OL

(0.45 V

TTL

) for a Logic '0.' Input timing begins at V

(2.0 V

TTL

)

and V

(0.8 V

TTL

). Output timing ends at V

and V

. Input rise

and fall times (10% to 90%) < 10 ns.

INPUT TEST POINTS OUTPUT

3.0

0.0 1.5 1.5

28F008SA-9

NOTE:

AC test inputs are driven at 3.0 V for a Logic '1' and 0.0 V for a

Logic '0'. Input timing begins, and output timing ends at 1.5 V.

Input rise and fall times (10% to 90%) < 10 ns.

28F008SA-10

DEVICE

UNDER

TEST

NOTE:

= 100 pF

Includes Jig Capacitance

= 3.3 kΩ

1.3 V

1N914

OUT

28F008SA-11

DEVICE

UNDER

TEST

NOTE:

= 30 pF

Includes Jig Capacitance

= 3.3 kΩ

1.3 V

1N914

OUT

HIGH SPEED AC INPUT/OUTPUT

REFERENCE W A VEFORM2

HIGH SPEED A C TESTING LOAD CIRCUIT2

NOTES:

1. Testing characteristics for LH28F008SA-85 in Standard

configuration, and LH28F008SA-12.

2. Testing characteristics for LH28F008SA-85 in

High Speed configuration

8M (1M × 8) Flash Memory LH28F008SA

AC CHARACTERISTICS - Read Only Operations1

SYMBOL PARAMETER

LH28F008SA-854

VCC ± 5% LH28F008SA-855

VCC ± 10% LH28F008SA-125

VCC ± 10% UNIT NOTE

MIN. MAX. MIN. MAX. MIN. MAX.

tAVAV tAC Read Cycle Time 85 90 120 ns

tAVQV tACC Address to Output Delay 85 90 120 ns

tELQV tCE CE

» to Output Delay 85 90 120 ns 2

tPHQV tPWH PWD High to Output Delay 400 400 400 ns

tGLQV tOE OE

» to Output Delay 404550ns2

ELQX tLZ CE

» to Output Low Z 0 0 0 ns 3

tEHQZ tHZ CE

» High to Output High Z 55 55 55 ns 3

tGLQX tOLZ OE

» to Output Low Z 0 0 0 ns 3

tGHQZ tDF OE

» High to Output High Z 30 30 30 ns 3

tOH

Outp ut Hol d fro m

Addresses, CE

» or OE

change, whichever is first 000ns3

NOTES:

1. See AC Input/Output Reference Waveform for timing measurements.

2. OE

»

may be delayed up to tCE - tOE after the falling edge of CE» without impact on tCE.

3. Sampled, not 100% tested.

4. See High Speed AC Input/Output Reference Wavefor ms and High Speed AC Testing Load circuits for testing characteristics.

5. See AC Input/Output Reference Waveforms and AC Testing Load Circuits for testing characteristics.

LH28F008SA 8M (1M × 8) Flash Memory

Figure 8. AC Waveform for Read Operations

28F008SA-12

AVAV

ADDRESSES STABLE

VCC POWER-UP STANDBY

DEVICE AND

ADDRESS 

SELECTION OUTPUTS

ENABLED DATA

VALID STANDBY VCC

POWER-DOWN

ADDRESSES (A) V

CE (E) V

GLQV

ELQV

GLQX

ELQX

AVQV

PHQV

EHQZ

GHQZ

OE (G) V

WE (W) V

DATA (D/Q) V

5.0 V

GND

PWD (P) V

HIGH-Z HIGH-Z

VALID OUTPUT

. . .

8M (1M × 8) Flash Memory LH28F008SA

A C CHARACTERISTICS - Write Operations 1

SYMBOL PARAMETER

LH28F008SA-857

VCC ± 5% LH28F008SA-858

VCC ± 10% LH28F008SA-128

VCC ± 10% UNIT NOTE

MIN. MAX. MIN. MAX. MIN. MAX.

tAVAV tWC Write Cycle Time 85 90 120 ns

tPHWL tPS PWD Hig h Recove ry t o WE

Going Low 1 1 1 µs

ELWL tCS CE

» Setup to WE Going Low 10 10 10 ns

tWLWH tWP WE Pulse Width 40 40 40 ns

tVPWH tVPS VPP Setup to W E Going High 100 100 100 ns 2

tAVWH tAS Address Setup to WE

Going High 40 40 40 ns 3

tDVWH tOS Data Setup to WE

Going High 40 40 40 ns

tWHDX tDH Data Hold from WE High 5 5 5 ns

tWHAX tAH Address Hold from WE High 5 5 5 ns

tWHEH tOH OE

» Hold from WE High 10 10 10 ns

tWHWL tWHP WE Pulse Width High 30 30 30 ns

tWHRL WE Hi gh t o RY

»/BY

» Goi ng

Low 100 100 100 ns

tWHQV1Duration of Byte Write

Operation 666µs

WHQV2Duration of Block Erase

Operation 0.3 0.3 0.3 s

tWHGL Write Recovery before Read 0 0 0 µs

tQVVL tVPH VPP Hold from Valid SRD,

» /BY

» High 000ns

NOTES:

1. Read timing characteristics during erase and byte write operations are the same as during read-only operations.

Refer to AC Character istics for Read-Only Operations.

2. Sampled, not 100% tested.

3. Refer to Command Definitions Table for Valid AIN for byte wr ite or block erasure.

4. Refer to Command Definitions Table for valid DIN for byte wr ite or block erasure.

5. The on-chip Write State Machine incorporates all byte write and block erase system functions and overhead of standard Intel flash

memor y, including byte program and verify (byte write) and block precondition, precondition ver ify, erase and erase ver ify (block erase).

6. Byte write and block erase durations are measure to completion (SR.7 = 1. RY»/BY» = VOH). VPP should be held at VPPH until determina-

tion of byte write/block erase success (SR.3/4/5 = 0).

7. See High Speed AC Input/Output Reference Waveforms and High Speed AC Testing Load Circuits for testing characteristics.

8. See AC Input/Output Reference Waveforms and AC Testing Load Circuits for testing characteristics.

LH28F008SA 8M (1M × 8) Flash Memory

Figure 9. AC Waveform for Write Operations

PARAMETER LH28F008SA-85 LH28F008SA-12 UNIT NOTE

TYP.1MIN. MAX. TYP.1MIN. MAX.

Block Erase Tim e 1.6 10 1.6 10 s 2

Block Write Time 0.6 2.1 0.6 2.1 s 2

BLOCK ERASE AND BYTE WRITE PERFORMANCE

NOTES:

1. 25°C , 12.0 VPP.

2. Excludes System-Level Overhead.

ADDRESSES (A) V

VALID

SRD

CE (E) V

PWD (P)

RY/BY (R)

(V)

PPH

PPL

28F008SA-13

HIGH-Z

WRITE BYTE

WRITE OR

ERASE SETUP

COMMAND

CC

POWER-UP

AND STANDBY

WRITE VALID

ADDRESS AND DATA

(BYTE WRITE) OR

ERASE CONFIRM

COMMAND

AUTOMATED

BYTE WRITE

OR ERASE

DELAY READ STATUS

ARRAY COMMAND

OE (G) V

WE (W)

DATA (D/Q)

AVAV

ELWL

WHEH

WHGL

AVWH

WHQV1, 2

WHWL

WLWH

DVWH

WHDX

PHWL

VPWH

WHRL

QVVL

WHAX

8M (1M × 8) Flash Memory LH28F008SA

ALTERNATIVE CE» - CONTROLLED WRITES

SYMBOL PARAMETER

LH28F008SA-856

VCC ± 5% LH28F008SA-857

VCC ± 10% LH28F008SA-127

VCC ± 10% UNIT NOTE

MIN. MAX. MIN. MAX. MIN. MAX.

tAVAV tWC Write Cycle Time 85 90 120 ns

tPHEL tPS PWD High Recovery to CE

Going Low 1 1 1 µs 2

WLEL tWS WE Setup to CE

» Going Low 000ns

ELEH tCP CE

» Pulse Width 50 50 50 ns

tVPEH tVPS VPP Setup to CE

» Going High 100 100 100 ns 2

AVEH tAS Address Setup to CE

» Going

High 40 40 40 ns 3

tDVEH tDS Da ta Setup to C E

» Going High 40 40 40 ns 4

tEHDX tDH Data Hold from CE

» High 555ns

EHAX tAH Address Hold from CE

» High 555ns

EHWH tWH WE Hold from CE

» High 000ns

EHEL tEPH CE

» Pulse Width High 25 25 25 ns

tEHRL CE

» High to RY

»/BY

Going Low 100 100 100 ns

tEHOV1 Duration of Byte Write

Operation 6 6 6 µs 5

EHOV2 Duration of Block Erase

Operation 0.3 0.3 0.3 s 5

tEHGL Write Recovery before Read 0 0 0 µs

tQVVL tVPH VPP Hold from Valid SRD,

» /BY

» High 0 0 0 ns2, 5

NOTE:

1. Chip-Enable Controlled Writes: Wr ite operations are driven by the valid combinations of CE» and WE

»

. In systems where

CE» defines the wr ite pulsewidth (within a longer WE

»

timing waveform), all setup, hold and inactive WE

»

times should be

measured relative to the CE» wavefo r m.

2. Sampled, not 100% tested.

3. Refer to Command Definitions Table for valid AIN for byte write or block erasure.

4. Refer to Command Definitions Table for valid DIN for byte write or block erasure.

5. Byte wr ite and block erase durations are measured to completion (SR.7 = 1, RY »/BY» = VOH). VPP should be held at VPPH until

deter mination of byte write/block erase success (SR.3/4/5 = 0).

6. See High Speed AC Input/Output Reference Wavefor ms and High Speed AC Testing Load Circuits for testing characteristics.

7. See AC Input/Output Reference Wavefor ms and AC Testing Load Circuits for testing characteristics.

LH28F008SA 8M (1M × 8) Flash Memory

Figure 10. Alternate AC Waveform for Write Operations

ADDRESSES (A) VIH

VIL AIN

AIN

DIN DIN DIN

VALID

SRD

VIH

VIL

VIH

VIL

WE (W) VIH

VIL

PWD (P)

RY/BY (R)

VIH

VIL

VIH

VIL

VPP (V)

VPPH

VPPL

28F008SA-14

HIGH-Z

WRITE BYTE

WRITE OR

ERASE SETUP

COMMAND

VCC

POWER-UP

AND STANDBY

WRITE VALID

ADDRESS AND DATA

(BYTE WRITE) OR

ERASE CONFIRM

COMMAND

AUTOMATED

BYTE WRITE

OR ERASE

DELAY READ STATUS

ARRAY COMMAND

OE (G) VIH

VIL

CE (E)

DATA (D/Q)

VOH

VOL

tAVAV

tWLEL

tEHWH

tEHGL

tAVEH

tEHQV1, 2

tEHEL

tELEH tDVEH

tEHDX

tPHEL

tVPEH

tEHRL

tQVVL

tEHAX

8M (1M × 8) Flash Memory LH28F008SA

DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT

MINIMUM LIMIT

44SOP (SOP044-P-0600)

16.40 [0.646]

15.60 [0.614]

13.40 [0.528]

13.00 [0.512] 14.40 [0.567]

28.40 [1.118]

28.00 [1.102]

0.15 [0.006]

1.275 [0.050]

0.25 [0.010]

0.05 [0.002]

1.275 [0.050]

2.9 [0.114]

2.5 [0.098]

0.20 [0.008]

0.10 [0.004]

0.50 [0.020]

0.30 [0.012]

1.27 [0.050]

TYP.

44 23

221

3.25 [0.128]

2.45 [0.096]

44SOP

2.9 [0.114]

2.5 [0.098]

1.275 [0.050]

0.25 [0.010]

0.05 [0.002]

0.80 [0.031]

0 - 10°

SEE

DETAIL

LH28F008SA 8M (1M × 8) Flash Memory

ORDERING INFORMATION

T 40-pin, 1.2 mm x 10 mm x 20 mm TSOP (Type I) (TSOP040-P-1020)

N 44-pin, 600-mil SOP (SOP044-P-0600)

LH28F008SA

Device Type X

Package

28F008SA-15

Example: LH28F008SAT-85 (8M (1M x 8) Flash Memory, 85 ns, 40-pin TSOP)

8M (1M x 8) Flash Memory

-##

Speed

85 85

12 120 Access Time (ns)

DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT

MINIMUM LIMIT

40TSOP (TSOP040-P-1020)

40TSOP

DETAIL

SEE DETAIL 1.19

[0.047]

MAX.

0 - 10°

0.22 [0.009]

0.02 [0.001]

1.10 [0.043]

0.90 [0.035]

0.49 [0.019]

0.39 [0.015]

0.49 [0.019]

0.39 [0.015]

0.125 [0.005]

10.20 [0.402]

9.80 [0.386]

0.50 [0.020]

TYP.

0.25 [0.010]

0.15 [0.006]

18.60 [0.732]

18.20 [0.717]

19.30 [0.760]

18.70 [0.736]

20.30 [0.799]

19.70 [0.776] 0.18 [0.007]

0.08 [0.003]

1

20 21

40

SHARP reserves the right to make changes in specifications at any time and without notice. SHARP does not assume any responsibility

for the use of any circuitry described; no circuit patent licenses are implied.

NORTH AMERICA EUROPE ASIA

SHARP Electronics Corporation

Microelectronics Group

5700 NW Pacific Rim Blvd., M/S 20

Camas, WA 98607, U.S.A.

Phone: (360) 834-2500

Telex: 49608472 (SHARPCAM)

Facsimile: (360) 834-8903

http://www.sharpmeg.com

SHARP Electronics (Europe) GmbH

Microelectronics Division

Sonninstraße 3

20097 Hamburg, Germany

Phone: (49) 40 2376-2286

Telex: 2161867 (HEEG D)

Facsimile: (49) 40 2376-2232

LIFE SUPPORT POLICY

SHARP components should not be used in medical devices with life support functions or in safety equipment (or similiar applications

where component failure would result in loss of life or physical harm) without the written approval of an officer of the SHARP Corporation.

SHARP Corporation

Integrated Circuits Group

2613-1 Ichinomoto-Cho

Tenri-City, Nara, 632, Japan

Phone: (07436) 5-1321

Telex: LABOMETA-B J63428

Facsimile: (07436) 5-1532



WARRANTY

SHARP warrants to Customer that the Products will be free from defects in material and workmanship under normal use and service for 

a period of one year from the date of invoice. Customer's exclusive remedy for breach of this warranty is that SHARP will either (i) repair 

or replace, at its option, any Product which fails during the warranty period because of such defect (if Customer promptly reported the

failure to SHARP in writing) or, (ii) if SHARP is unable to repair or replace, SHARP will refund the purchase price of the Product upon its

return to SHARP. This warranty does not apply to any Product which has been subjected to misuse, abnormal service or handling, or

which has been altered or modified in design or construction, or which has been serviced or repaired by anyone other than SHARP. The

warranties set forth herein are in lieu of, and exclusive of, all other warranties, express or implied.

ALL EXPRESS AND IMPLIED

WARRANTIES OF

MERCHANTABILITY, FITNESS FOR USE AND FITNESS FOR A PARTICULAR PURPOSE ARE SPECIFICALLY

EXCLUDED.

Issued J uly 1994

8M (1M × 8) Flash Memory LH28F008SA