128MB, 256MB, 512MB (x72, ECC) 184-PIN REGISTERED DDR SDRAM DIMM REGISTERED DDR SDRAM DIMM MT9VDDF1672 - 128MB MT9VDDF3272 - 256MB MT9VDDF6472 - 512MB For the latest data sheet, please refer to the Microna Web site: www.micron.com/moduleds Features Figure 1: 184-Pin DIMM (MO-206) * 184-pin, dual, in-line memory module (DIMM) * Fast data transfer rates PC 1600, PC2100, or PC2700 * Utilizes 200MT/s, 266 MT/s, and 333 MT/s DDR SDRAM components * Registered Inputs with one-clock delay * Phase-lock loop (PLL) clock driver to reduce loading * ECC, 1-bit error detection and correction * 128MB (16 Meg x 72); 256MB (32 Meg x 72); and 512MB (64 Meg x 72) * VDD = VDDQ = +2.5V * VDDSPD = +2.3V to +3.6V * 2.5V I/O (SSTL_2 compatible) * Commands entered on each positive CK edge * DQS edge-aligned with data for READs; centeraligned with data for WRITEs * Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle * Bidirectional data strobe (DQS) transmitted/received with data--i.e., source-synchronous data capture * Differential clock inputs CK and CK# * Four internal device banks for concurrent operation * Programmable burst lengths: 2, 4, or 8 * Auto precharge option * Auto Refresh and Self Refresh Modes * 15.625s (128MB) or 7.8125s (256MB, 512MB) maximum average periodic refresh interval * Serial Presence-Detect (SPD) with EEPROM * Programmable READ CAS latency * Gold edge contacts Table 1: OPTIONS MARKING * Package 184-pin DIMM (Standard) 184-pin DIMM (Lead-free) * Frequency/CAS Latency2 6ns/167 MHz (33 MT/s) CL = 2.5 7.5ns/133 MHz (266 MT/s) CL = 2 7.5ns/133 MHz (266 MT/s) CL = 2 7.5ns/133 MHz (266 MT/s) CL = 2.5 10ns/100 MHz (200 MT/s) CL = 2 NOTE: G Y -335 -262 -26A -265 -202 1. Consult factory for availability of lead-free products. 2. CL = CAS (READ) Latency; Registered mode will add one clock cycle to CL. Address Table Refresh Count Row Addressing Device Bank Addressing Device Configuration Column Addressing Module Rank Addressing 09005aef807d56a1 DDF9C16_32_64x72G_D.fm - Rev. D 9/03 EN 128MB 256MB 512MB 4K 4K (A0-A11) 4 (BA0, BA1) 16 Meg x 8 1K (A0-A9) 1 (S0#) 8K 8K (A0-A12) 4 (BA0, BA1) 32 Meg x 8 1K (A0-A9) 1 (S0#) 8K 8K (A0-A12) 4 (BA0, BA1) 64 Meg x 8 2K (A0-A9, A11) 1 (S0#) 1 (c)2003 Micron Technology, Inc. 128MB, 256MB, 512MB (x72, ECC) 184-PIN REGISTERED DDR SDRAM DIMM Table 2: Part Numbers and Timing Parameters PART NUMBER MT9VDDF1672G-335__ MT9VDDF1672Y-335__ MT9VDDF1672G-262__ MT9VDDF1672Y-262__ MT9VDDF1672G-26A__ MT9VDDF1672Y-26A__ MT9VDDF1672G-265__ MT9VDDF1672Y-265__ MT9VDDF1672G-202__ MT9VDDF1672Y-202__ MT9VDDF3272G-335__ MT9VDDF3272Y-335__ MT9VDDF3272G-262__ MT9VDDF3272Y-262__ MT9VDDF3272G-26A__ MT9VDDF3272Y-26A__ MT9VDDF3272G-265__ MT9VDDF3272Y-265__ MT9VDDF3272G-202__ MT9VDDF3272Y-202__ MT9VDDF6472G-335__ MT9VDDF6472Y-335__ MT9VDDF6472G-262__ MT9VDDF6472Y-262__ MT9VDDF6472G-26A__ MT9VDDF6472Y-26A__ MT9VDDF6472G-265__ MT9VDDF6472Y-265__ MT9VDDF6472G-202__ MT9VDDF6472Y-202__ MODULE DENSITY CONFIGURATION MODULE BANDWIDTH MEMORY CLOCK/ DATA RATE LATENCY (CL - tRCD - tRP) 128MB 128MB 128MB 128MB 128MB 128MB 128MB 128MB 128MB 128MB 256MB 256MB 256MB 256MB 256MB 256MB 256MB 256MB 256MB 256MB 512MB 512MB 512MB 512MB 512MB 512MB 512MB 512MB 512MB 512MB 16 Meg x 72 16 Meg x 72 16 Meg x 72 16 Meg x 72 16 Meg x 72 16 Meg x 72 16 Meg x 72 16 Meg x 72 16 Meg x 72 16 Meg x 72 32 Meg x 72 32 Meg x 72 32 Meg x 72 32 Meg x 72 32 Meg x 72 32 Meg x 72 32 Meg x 72 32 Meg x 72 32 Meg x 72 32 Meg x 72 64 Meg x 72 64 Meg x 72 64 Meg x 72 64 Meg x 72 64 Meg x 72 64 Meg x 72 64 Meg x 72 64 Meg x 72 64 Meg x 72 64 Meg x 72 2.7 GB/s 2.7 GB/s 2.1 GB/s 2.1 GB/s 2.1 GB/s 2.1 GB/s 2.1 GB/s 2.1 GB/s 1.6 GB/s 1.6 GB/s 2.7 GB/s 2.7 GB/s 2.1 GB/s 2.1 GB/s 2.1 GB/s 2.1 GB/s 2.1 GB/s 2.1 GB/s 2.1 GB/s 1.6 GB/s 2.7 GB/s 2.7 GB/s 2.1 GB/s 2.1 GB/s 2.1 GB/s 2.1 GB/s 2.1 GB/s 2.1 GB/s 2.1 GB/s 1.6 GB/s 6ns/333 MT/s 6ns/333 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 10ns/200 MT/s 10ns/200 MT/s 6ns/333 MT/s 6ns/333 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 10ns/200 MT/s 6ns/333 MT/s 6ns/333 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 10ns/200 MT/s 2.5-3-3 2.5-3-3 2-2-2 2-2-2 2-3-3 2-3-3 2.5-3-3 2.5-3-3 2-2-2 2-2-2 2.5-3-3 2.5-3-3 2-2-2 2-2-2 2-3-3 2-3-3 2.5-3-3 2.5-3-3 2-2-2 2-2-2 2.5-3-3 2.5-3-3 2-2-2 2-2-2 2-3-3 2-3-3 2.5-3-3 2.5-3-3 2-2-2 2-2-2 NOTE: All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current revision codes. Example: MT9VDDF3272G-265B1. 09005aef807d56a1 DDF9C16_32_64x72G_D.fm - Rev. D 9/03 EN 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. 128MB, 256MB, 512MB (x72, ECC) 184-PIN REGISTERED DDR SDRAM DIMM Table 3: Pin Assignment (184-Pin DIMM Front) Table 4: Pin Assignment (184-Pin DIMM Back) PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 93 VSS 94 DQ4 95 DQ5 96 VDDQ 97 DM0 98 DQ6 99 DQ7 100 VSS 101 NC 102 NC 103 NC 104 VDDQ 105 DQ12 106 DQ13 107 DM1 108 VDD 109 DQ14 110 DQ15 111 DNU 112 VDDQ 113 NC 114 DQ20 115 NC/A121 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 VREF DQ0 VSS DQ1 DQS0 DQ2 VDD DQ3 NC RESET# VSS DQ8 DQ9 DQS1 VDDQ DNU DNU VSS DQ10 DQ11 CKE0 VDDQ DQ16 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 DQ17 DQS2 VSS A9 DQ18 A7 VDDQ DQ19 A5 DQ24 VSS DQ25 DQS3 A4 VDD DQ26 DQ27 A2 VSS A1 CB0 CB1 VDD 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 DQS8 A0 CB2 VSS CB3 BA1 DQ32 VDDQ DQ33 DQS4 DQ34 VSS BA0 DQ35 DQ40 VDDQ WE# DQ41 CAS# VSS DQS5 DQ42 DQ43 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 VDD NC DQ48 DQ49 VSS DNU DNU VDDQ DQS6 DQ50 DQ51 VSS NC DQ56 DQ57 VDD DQS7 DQ58 DQ59 VSS DNU SDA SCL 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 VSS DQ21 A11 DM2 VDD DQ22 A8 DQ23 VSS A6 DQ28 DQ29 VDDQ DM3 A3 DQ30 VSS DQ31 CB4 CB5 VDDQ CK0 CK0# 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 VSS DM8 A10 CB6 VDDQ CB7 VSS DQ36 DQ37 VDD DM4 DQ38 DQ39 VSS DQ44 RAS# DQ45 VDDQ S0# DNU DM5 VSS DQ46 DQ47 NC VDDQ DQ52 DQ53 NC VDD DM6 DQ54 DQ55 VDDQ NC DQ60 DQ61 VSS DM7 DQ62 DQ63 VDDQ SA0 SA1 SA2 VDDSPD NOTE: 1. Pin 115 is NC for 128MB, or A12 for 256MB and 512MB. Figure 2: Pin Locations Front View U12 U1 U2 U3 U4 U6 U5 U11 U7 U8 U9 U13 U10 PIN 52 PIN 1 PIN 53 PIN 92 Back View No Components This Side of Module PIN 184 PIN 145 PIN 144 Indicates a VDD or VDDQ pin 09005aef807d56a1 DDF9C16_32_64x72G_D.fm - Rev. D 9/03 EN 3 PIN 93 Indicates a VSS pin Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. 128MB, 256MB, 512MB (x72, ECC) 184-PIN REGISTERED DDR SDRAM DIMM Table 5: Pin Descriptions Pin numbers may not correlate with symbols. Refer to Pin Assignment tables on page 3 for more information PIN NUMBERS SYMBOL TYPE 10 Reset# Input 63, 65, 154 WE#, CAS#, RAS# 137, 138 CK0, CK0# 21 CKE0 157 S0# 52, 59 BA0, BA1 27, 29, 32, 37, 41, 43, 48, 115 (256MB, 512MB), 118, 122, 125, 130, 141 A0-A11 (128MB) A0-A12 (256MB, 512MB) 97, 107, 119, 129, 140, 149, 159, 169, 177 DM0-DM8 5, 14, 25, 36, 47, 56, 67, 78, 86 DQS0-DQS8 44, 45, 49, 51, 134, 135, 142, 144 CB0-CB7 09005aef807d56a1 DDF9C16_32_64x72G_D.fm - Rev. D 9/03 EN DESCRIPTION Asynchronously forces all registered ouputs LOW when RESET# is LOW. This signal can be used during power-up to ensure CKE is LOW and DQs are High-Z. Input Command Inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered. Input Clock: CK, CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK,and negative edge of CK#. Output data (DQ and DQS) is referenced to the crossings of CK and CK#. Input Clock Enable: CKE HIGH activates and CKE LOW deactivates the internal clock, input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all device banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any device bank). CKE is synchronous for POWER-DOWN entry and exit, and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit and for disabling the outputs. CKE must be maintained HIGH throughout read and write accesses. Input buffers (excluding CK, CK# and CKE) are disabled during POWER-DOWN. Input buffers (excluding CKE) are disabled during SELF REFRESH. CKE is an SSTL_2 input but will detect an LVCMOS LOW level after VDD is applied and until CKE is first brought HIGH. After CKE is brought HIGH, it becomes an SSTL_2 input only. Input Chip Selects: S# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when S# is registered HIGH. S# is considered part of the command code. Input Bank Address: BA0 and BA1 define to which device bank an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. Input Address Inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/ WRITE commands, to select one location out of the memory array in the respective device bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one device bank (A10 LOW, device bank selected by BA0, BA1) or all device banks (A10 HIGH). The address inputs also provide the op-code during a MODE REGISTER SET command. BA0 and BA1 define which mode register (mode register or extended mode register) is loaded during the LOAD MODE REGISTER command. Input Data Write Mask: DM LOW allows WRITE operation. DM HIGH blocks WRITE operation. DM state does not affect READ command. Input/ Data Strobe: Output with READ data, input with WRITE data. Output DQS is edge-aligned with READ data, centered in WRITE data. Used to capture data. Input/ Check Bits: ECC, 1-bit error detection and correction. Output 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. 128MB, 256MB, 512MB (x72, ECC) 184-PIN REGISTERED DDR SDRAM DIMM Table 5: Pin Descriptions Pin numbers may not correlate with symbols. Refer to Pin Assignment tables on page 3 for more information PIN NUMBERS SYMBOL 2, 4, 6, 8, 12,13, 19, 20, 23, 24, 28, 31, 33, 35, 39, 40, 53, 55, 57, 60, 61, 64, 68, 69, 72, 73, 79, 80, 83, 84, 87, 88, 94, 95, 98, 99, 105, 106, 109, 110, 114, 117, 121, 123, 126, 127, 131, 133, 146, 147, 150, 151, 153, 155, 161, 162, 165, 166, 170, 171, 174, 175, 178, 179 92 DQ0-DQ63 181, 182, 183 SA0-SA2 91 SDA 1 15, 22, 30, 54, 62, 77, 96, 104, 112, 128, 136, 143, 156, 164, 172, 180 7, 38, 46, 70, 85, 108, 120, 148, 168 3, 11, 18, 26, 34, 42, 50, 58, 66, 74, 81, 89, 93, 100, 116, 124, 132, 139, 145, 152, 160, 176 184 16, 17, 75, 76, 90, 111, 158 9, 71, 82, 101, 102, 103, 113, 115 (128MB), 163, 167, 173 VREF VDDQ 09005aef807d56a1 DDF9C16_32_64x72G_D.fm - Rev. D 9/03 EN SCL TYPE DESCRIPTION Input/ Data I/Os: Data bus. Output Input Serial Clock for Presence-Detect: SCL is used to synchronize the presence-detect data transfer to and from the module. Input Presence-Detect Address Inputs: These pins are used to configure the presence-detect device. Input/ Serial Presence-Detect Data: SDA is a bidirectional pin used to Output transfer addresses and data into and out of the presence-detect portion of the module. Input SSTL_2 reference voltage. Supply DQ Power Supply: +2.5V 0.2V. VDD Supply Power Supply: +2.5V 0.2V. VSS Supply Ground. VDDSPD DNU NC Supply Serial EEPROM positive power supply: +2.3V to +3.6V -- Do Not Use: Thes pins are not connected on these modules, but are assigned pins on other modules in this product family -- No Connect: These pins should be left unconnected. 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. 128MB, 256MB, 512MB (x72, ECC) 184-PIN REGISTERED DDR SDRAM DIMM Figure 3: Functional Block Diagram RS0# DQS0 DQS4 DM0 DM4 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM CS# DQS DQ DQ DQ DQ U1 DQ DQ DQ DQ DQS1 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM CS# DQS DQ DQ DQ U6 DQ DQ DQ DQ DQ DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM CS# DQS DQ DQ DQ U7 DQ DQ DQ DQ DQ DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM CS# DQS DQ DQ DQ U8 DQ DQ DQ DQ DQ DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM CS# DQS DQ DQ DQ U9 DQ DQ DQ DQ DQ DQS5 DM1 DM5 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM CS# DQS DQ DQ DQ DQ U2 DQ DQ DQ DQ DQS2 DQS6 DM2 DM6 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM CS# DQS DQ DQ DQ U3 DQ DQ DQ DQ DQ DQS3 DQS7 DM3 DM7 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM CS# DQS DQ DQ DQ DQ U4 DQ DQ DQ DQ CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DM CS# DQS DQ DQ DQ DQ U5 DQ DQ DQ DQ DQS8 DM8 120 CK0 CK0# U12 PLL U10 SCL WP SERIAL PD A0 A1 A2 SDA DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM REGISTER X 2 SA0 SA1 SA2 U11, U13 S0# BA0, BA1 A0-A11(128MB) A0-A12 (256MB, 512MB) RAS# CAS# CKE0 WE# CK R E G I S T E R S RS0#: DDR SDRAMs RBA0, RBA1: DDR SDRAMs RA0-RA11: DDR SDRAMs RA0-RA12: DDR SDRAMs RRAS#: DDR SDRAMs RCAS#: DDR SDRAMs VDDSPD SPD / EEPROM VDDQ DDR SDRAMs VDD DDR SDRAMs VREF DDR SDRAMs VSS DDR SDRAMs RCKE0: DDR SDRAMs RWE#: DDR SDRAMs RESET# CK# NOTE: 1. Unless otherwise noted, resistor values are 22W. 2. Per industry standard, Micron utilizes various component speed grades as referenced in the Module Part Numbering Guide at www.micron.com/numberguide. 09005aef807d56a1 DDF9C16_32_64x72G_D.fm - Rev. D 9/03 EN 6 MT46V16M8FB = DDR SDRAMs for 128MB Module MT46V32M8FB = DDR SDRAMs for 256MB Module MT46V64M8FB = DDR SDRAMs for 512MB Module Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. 128MB, 256MB, 512MB (x72, ECC) 184-PIN REGISTERED DDR SDRAM DIMM General Description The MT9VDDF1672, MT9VDDF3272, and MT9VDDF6472 are high-speed, CMOS, dynamic random-access, 128MB, 256MB, and 512MB memory modules organized in x72 (ECC) configuration. DDR SDRAM modules uss internally configured quad-bank DDR SDRAM devices. DDR SDRAM modules use a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR SDRAM module effectively consists of a single 2n-bit wide, one-clock-cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins. A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is an intermittent strobe transmitted by the DDR SDRAM during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. DDR SDRAM modules operate from differential clock inputs (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. Read and write accesses to DDR SDRAM modules are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the device bank and row to be accessed [BA0, BA1 select devices bank; A0-A11 (128MB), or A0-A12 (256MB, 512MB) select device row]. The address bits registered coincident with the READ or WRITE command are used to select the device bank and starting device column location for the burst access. DDR SDRAM modules provide for programmable READ or WRITE burst lengths of 2, 4, or 8 locations. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. 09005aef807d56a1 DDF9C16_32_64x72G_D.fm - Rev. D 9/03 EN The pipelined, multibank architecture of DDR SDRAM modules allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time. An auto refresh mode is provided, along with a power-saving power-down mode. All inputs are compatible with the JEDEC Standard for SSTL_2. All outputs are SSTL_2, Class II compatible. For more information regarding DDR SDRAM operation, refer to the 128Mb, 256Mb, and 512Mb DDR SDRAM component data sheets. PLL and Register Operation These DDR SDRAM modules operate in registered mode, where the command/address input signals are latched in the registers on the rising clock edge and sent to the DDR SDRAM devices on the following rising clock edge (data access is delayed by one clock cycle). A phase-lock loop (PLL) on the module receives and redrives the differential clock signals (CK, CK#) to the DDR SDRAM devices. The registers and PLL minimize system and clock loading. Serial Presence-Detect Operation These DDR SDRAM modules incorporate serial presence-detect (SPD). The SPD function is implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256 bytes. The first 128 bytes can be programmed by Micron to identify the module type and various SDRAM organizations and timing parameters. The remaining 128 bytes of storage are available for use by the customer. System READ/ WRITE operations between the master (system logic) and the slave EEPROM device (DIMM) occur via a standard I2C bus using the DIMM's SCL (clock) and SDA (data) signals, together with SA (2:0), which provide eight unique DIMM/EEPROM addresses. Write protect (WP) is tied to ground on the module, permanently disabling hardware write protect. Mode Register Definition The mode register is used to define the specific mode of operation of the DDR SDRAM device. This definition includes the selection of a burst length, a burst type, a CAS latency and an operating mode, as shown in Figure 4, Mode Register Definition Diagram, on page 8. The mode register is programmed via the MODE REGISTER SET command (with BA0 = 0 and BA1 = 0) and will retain the stored information until it is programmed again or the device loses power (except for bit A8, which is self-clearing). 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. 128MB, 256MB, 512MB (x72, ECC) 184-PIN REGISTERED DDR SDRAM DIMM Figure 4: Mode Register Definition Diagram Reprogramming the mode register will not alter the contents of the memory, provided it is performed correctly. The mode register must be loaded (reloaded) when all device banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation. Mode register bits A0-A2 specify the burst length, A3 specifies the type of burst (sequential or interleaved), A4-A6 specify the CAS latency, and A7-A11 (128MB) or A7-A12 (256MB, 512MB) specify the operating mode. 128MB Module BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 13 12 0* 0* 11 10 9 8 7 6 5 4 3 2 1 0 Operating Mode CAS Latency BT Burst Length Address Bus Mode Register (Mx) * M13 and M12 (BA1 and BA0) must be "0, 0" to select the base mode register (vs. the extended mode register). 256MB, 512MB Modules BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus Burst Length Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable, as shown in Figure 4, Mode Register Definition Diagram. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1-Ai when the burst length is set to two, by A2-Ai when the burst length is set to four and by A3-Ai when the burst length is set to eight (where Ai is the most significant column address bit for a given configuration. See Note 5 of Table 6, Burst Definition Table, on page 9, for Ai values). The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. The programmed burst length applies to both READ and WRITE bursts. 14 13 12 11 10 9 8 Operating Mode 0* 0* 6 5 4 3 2 1 0 CAS Latency BT Burst Length * M14 and M13 (BA1 and BA0) must be "0, 0" to select the base mode register (vs. the extended mode register). Mode Register (Mx) Burst Length M2 M1 M0 M3 = 0 M3 = 1 0 0 0 Reserved Reserved 0 0 1 2 2 0 1 0 4 4 0 1 1 8 8 1 0 0 Reserved Reserved 1 0 1 Reserved Reserved 1 1 0 Reserved Reserved 1 1 1 Reserved Reserved Burst Type M3 0 Sequential 1 Interleaved CAS Latency M6 M5 M4 Burst Type 0 0 0 Reserved 0 0 1 Reserved 0 1 0 2 0 1 1 Reserved 1 0 0 Reserved 1 0 1 Reserved 1 1 0 2.5 1 1 1 Reserved M12 M11 M10 M9 M8 M7 Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 6, Burst Definition Table, on page 9. 09005aef807d56a1 DDF9C16_32_64x72G_D.fm - Rev. D 9/03 EN 7 8 M6-M0 Operating Mode 0 0 0 0 0 0 Valid Normal Operation 0 0 0 0 1 0 Valid Normal Operation/Reset DLL - - - - - - - All other states reserved Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. 128MB, 256MB, 512MB (x72, ECC) 184-PIN REGISTERED DDR SDRAM DIMM Table 6: Burst Definition Table STARTING COLUMN ADDRESS BURST LENGTH Figure 5: CAS Latency Diagram ORDER OF ACCESSES WITHIN A BURST COMMAND 0 1 0-1 1-0 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 T1 T2 READ NOP NOP T2n T3 T3n CK A0 2 T0 CK# TYPE = TYPE = SEQUENTIAL INTERLEAVED NOP CL = 2 DQS A1 A0 0 0 1 1 4 0 1 0 1 DQ CK# 8 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 COMMAND 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 READ NOP NOP T2n T3 T3n NOP CL = 2.5 DQ Burst Length = 4 in the cases shown Shown with nominal tAC, tDQSCK, and tDQSQ TRANSITIONING DATA DON'T CARE Read Latency 1. For a burst length of two, A1-Ai select the twodata-element block; A0 selects the first access within the block. 2. For a burst length of four, A2-Ai select the fourdata-element block; A0-A1 select the first access within the block. 3. For a burst length of eight, A3-Ai select the eightdata-element block; A0-A2 select the first access within the block. 4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 5. Ai = A9 for 128MB, 256MB Ai = A9, A11 for 512MB The READ latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 2 or 2.5 clocks, as shown in Figure 5, CAS Latency Diagram. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n + m. Table 7, CAS Latency Table, indicates the operating frequencies at which each CAS latency setting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result. Operating Mode CAS Latency Table The normal operating mode is selected by issuing a MODE REGISTER SET command with bits A7-A11 (128MB), or A7-A12 (256MB, 512MB) each set to zero, and bits A0-A6 set to the desired values. A DLL reset is initiated by issuing a MODE REGISTER SET command with bits A7 and A9-A11 (128MB) or A9-A12 (256MB, 512MB) each set to zero, bit A8 set to one, and bits A0A6 set to the desired values. Although not required by the Micron device, JEDEC specifications recommend when a LOAD MODE REGISTER command is issued to ALLOWABLE OPERATING CLOCK FREQUENCY (MHZ) SPEED CL = 2 CL = 2.5 -335 -262 -26A -265 -202 75 f 133 75 f 133 75 f 133 75 f 100 75 f 100 75 f 167 75 f 133 75 f 133 75 f 133 75 f 125 09005aef807d56a1 DDF9C16_32_64x72G_D.fm - Rev. D 9/03 EN T2 DQS NOTE: Table 7: T1 CK A2 A1 A0 0 0 0 0 1 1 1 1 T0 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. 128MB, 256MB, 512MB (x72, ECC) 184-PIN REGISTERED DDR SDRAM DIMM reset the DLL, it should always be followed by a LOAD MODE REGISTER command to select normal operating mode. All other combinations of values for A7-A11 (128MB) or A7-A12 (256MB, 512MB) are reserved for future use and/or test modes. Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. tion. When the device exits self refresh mode, the DLL is enabled automatically. Any time the DLL is enabled, 200 clock cycles must occur before a READ command can be issued. Figure 6: Extended Mode Register Definition Diagram 128MB Module BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus Extended Mode Register The extended mode register controls functions beyond those controlled by the mode register; these additional functions are DLL enable/disable and output drive strength. These functions are controlled via the bits shown in Figure 6, Extended Mode Register Definition Diagram. The extended mode register is programmed via the LOAD MODE REGISTER command to the mode register (with BA0 = 1 and BA1 = 0) and will retain the stored information until it is programmed again or the device loses power. The enabling of the DLL should always be followed by a LOAD MODE REGISTER command to the mode register (BA0/BA1 both LOW) to reset the DLL. The extended mode register must be loaded when all device banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements could result in unspecified operation. 13 12 11 10 9 01 11 8 7 6 5 4 Operating Mode 3 2 1 0 Extended Mode Register (Ex) DS DLL 256MB, 512MB Modules BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 14 13 12 11 10 9 8 7 6 5 Operating Mode 01 11 E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E22 4 3 2 1 0 Address Bus Extended Mode Register (Ex) DS DLL E0 DLL 0 Enable 1 Disable E1 Drive Strength 0 Normal E1, E0 Operating Mode 0 0 0 0 0 0 0 0 0 0 0 Valid Reserved - - - - - - - - - - - - Reserved DLL Enable/Disable NOTE: The DLL must be enabled for normal operation. DLL enable is required during power-up initialization and upon returning to normal operation after having disabled the DLL for the purpose of debug or evalua- 1. BA1 and BA0 (E13 and E12 for 128MB, E14 and E13 for 256MB and 512MB) must be "0, 1" to select the Extended Mode Register (vs. the base Mode Register). 2. The QFC# option is not supported. 09005aef807d56a1 DDF9C16_32_64x72G_D.fm - Rev. D 9/03 EN 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. 128MB, 256MB, 512MB (x72, ECC) 184-PIN REGISTERED DDR SDRAM DIMM Commands The Truth Tables below provides a general reference of available commands. For a more detailed description of commands and operations, refer to the 128Mb, Table 8: 256Mb, and 512Mb DDR SDRAM component data sheets. Truth Table - Commands CKE is HIGH for all commands shown except SELF REFRESH NAME (FUNCTION) CS# RAS# CAS# WE# ADDR NOTES H L L L L L L L L X H L H H H L L L X H H L L H H L L X H H H L L L H L X X Bank/Row Bank/Col Bank/Col X Code X Op-Code 1 1 2 3 3 4 5 6, 7 8 DESELECT (NOP) NO OPERATION (NOP) ACTIVE (Select bank and activate row) READ (Select bank and column, and start READ burst) WRITE (Select bank and column, and start WRITE burst) BURST TERMINATE PRECHARGE (Deactivate row in bank or banks) AUTO REFRESH or SELF REFRESH (Enter self refresh mode) LOAD MODE REGISTER NOTE: 1. DESELECT and NOP are functionally interchangeable. 2. BA0-BA1 provide device bank address and A0-A11 (128MB) or A0-A12 (256MB, 512MB) provide row address. 3. BA0-BA1 provide device bank address; A0-A9 (128MB, 256MB) or A0-A9, A11 (512MB)provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), and A10 LOW disables the auto precharge feature. 4. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for READ bursts with auto precharge enabled and for WRITE bursts. 5. A10 LOW: BA0-BA1 determine which device bank is precharged. A10 HIGH: all device banks are precharged and BA0-BA1 are "Don't Care." 6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW. 7. Internal refresh counter controls row addressing; all inputs and I/Os are "Don't Care" except for CKE. 8. BA0-BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register; BA0 = 1, BA1 = 0 select extended mode register; other combinations of BA0-BA1 are reserved). A0-A11 (128MB) or A0-A12 (256MB, 512MB) provide the op-code to be written to the selected mode register. Table 9: Truth Table - DM Operation Used to mask write data; provided coincident with the corresponding data NAME (FUNCTION) WRITE Enable WRITE Inhibit 09005aef807d56a1 DDF9C16_32_64x72G_D.fm - Rev. D 9/03 EN 11 DM DQS L H Valid X Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. 128MB, 256MB, 512MB (x72, ECC) 184-PIN REGISTERED DDR SDRAM DIMM ABSOLUTE MAXIMUM RATINGS Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other condi- tions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Voltage on VDD Supply Relative to VSS . . . . . . . . . . . . . . . . . . . . . -1V to +3.6V Voltage on VDDQ Supply Relative to VSS . . . . . . . . . . . . . . . . . . . . -1V to +3.6V Voltage on VREF and Inputs Relative to VSS . . . . . . . . . . . . . . . . . . . . -1V to +3.6V Voltage on I/O Pins Relative to VSS . . . . . . . . . . . . . -0.5V to VDDQ +0.5V Operating Temperature TA (ambient) . . . . . . . . . . . . . . . . . . . . .. 0C to +70C Storage Temperature (plastic) . . . . . . -55C to +150C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 9W Short Circuit Output Current. . . . . . . . . . . . . . . 50mA Table 10: DC Electrical Characteristics and Operating Conditions Notes: 1-5, 14; notes appear on pages 20-23; 0C TA +70C PARAMETER/CONDITION Supply Voltage I/O Supply Voltage I/O Reference Voltage I/O Termination Voltage (system) Input High (Logic 1) Voltage Input Low (Logic 0) Voltage INPUT LEAKAGE CURRENT Any input 0V VIN VDD, VREF pin 0V VIN 1.35V (All other pins not under test = 0V) SYMBOL VDD VDDQ VREF VTT VIH(DC) VIL(DC) Command/ Address, RAS#, CAS#, WE#, S#, CKE CK, CK# DM DQ, DQS OUTPUT LEAKAGE CURRENT (DQs are disabled; 0V VOUT VDDQ) OUTPUT LEVELS High Current (VOUT = VDDQ - 0.373V, minimum VREF, minimum VTT) Low Current (VOUT = 0.373V, maximum VREF, maximum VTT) MIN MAX UNITS NOTES V V V V V V 32, 36 32, 36, 39 6, 39 7, 39 25 25 A 49 2.3 2.7 2.3 2.7 0.49 x VDDQ 0.51 x VDDQ VREF - 0.04 VREF + 0.04 VREF + 0.15 VDD + 0.3 -0.3 VREF - 0.15 -5 5 II IOZ -10 -2 -5 10 2 5 A 49 IOH IOL -16.8 16.8 - - mA mA 33, 34 Table 11: AC Input Operating Conditions Notes: 1-5, 14; notes appear on pages 20-23; 0C TA +70C; VDD = VDDQ = +2.5V 0.2V PARAMETER/CONDITION Input High (Logic 1) Voltage Input Low (Logic 0) Voltage I/O Reference Voltage 09005aef807d56a1 DDF9C16_32_64x72G_D.fm - Rev. D 9/03 EN SYMBOL MIN MAX UNITS NOTES VIH(AC) VIL(AC) VREF(AC) VREF + 0.310 - 0.49 X VDDQ - VREF - 0.310 0.51 X VDDQ V V V 12, 25, 35 12, 25, 35 6 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. 128MB, 256MB, 512MB (x72, ECC) 184-PIN REGISTERED DDR SDRAM DIMM Table 12: IDD Specifications and Conditions - 128MB DDR SDRAM components only Notes: 1-5, 8, 10, 12, 43; notes appear on pages 20-23; 0C TA +70C; VDD = VDDQ = +2.5V 0.2V MAX PARAMETER/CONDITION SYM -335 -262 -26A/ -265 -202 UNITS NOTES OPERATING CURRENT: One device bank; Active-Precharge; t RC = tRC (MIN); tCK = tCK (MIN); DQ, DM and DQS inputs changing once per clock cyle; Address and control inputs changing once every two clock cycles OPERATING CURRENT: One device bank; Active -Read Precharge; Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks idle; Power-down mode; tCK = tCK (MIN); CKE = (LOW) IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle; tCK = tCK MIN; CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device bank; Active-Precharge; tRC = tRAS (MAX); t CK = tCK (MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle t RC = tRC (MIN) AUTO REFRESH CURRENT t RC = 15.625s SELF REFRESH CURRENT: CKE 0.2V OPERATING CURRENT: Four device bank interleaving READs (BL = 4) with auto precharge, tRC = tRC (MIN); t CK = tCK (MIN); Address and control inputs change only during Active READ, or WRITE commands IDD0 1,125 990 945 945 mA 20, 44 IDD1 1,215 1,080 1,080 1,080 mA 20, 44 IDD2P 27 27 27 27 mA 21, 28, 46 IDD2F 405 405 360 360 mA 47 IDD3P 225 225 180 180 mA 21, 28, 46 IDD3N 450 450 405 405 mA 42 IDD4R 1,260 1,170 1,125 1,125 mA 20, 44 IDD4W 1,260 1,125 1,080 1,080 mA 20 IDD5 IDD5A IDD6 IDD7 2,385 45 27 3,195 1,980 45 27 2,970 1,980 45 18 2,925 1,980 45 18 2,925 mA mA mA mA 20, 46 24, 46 9 20, 45 09005aef807d56a1 DDF9C16_32_64x72G_D.fm - Rev. D 9/03 EN 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. 128MB, 256MB, 512MB (x72, ECC) 184-PIN REGISTERED DDR SDRAM DIMM Table 13: IDD Specifications and Conditions - 256MB DDR SDRAM components only Notes: 1-5, 8, 10, 12, 43; notes appear on pages 20-23; 0C TA +70C; VDD = VDDQ = +2.5V 0.2V MAX PARAMETER/CONDITION SYM -335 -262 -26A/ -265 -202 UNITS NOTES OPERATING CURRENT: One device bank; Active-Precharge; t RC = tRC (MIN); tCK = tCK (MIN); DQ, DM and DQS inputs changing once per clock cyle; Address and control inputs changing once every two clock cycles OPERATING CURRENT: One device bank; Active -Read Precharge; Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks idle; Power-down mode; tCK = tCK (MIN); CKE = (LOW) IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle; tCK = tCK MIN; CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device bank; Active-Precharge; tRC = tRAS (MAX); t CK = tCK (MIN); DQ, DM andDQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle t RC = tRC (MIN) AUTO REFRESH CURRENT t RC = 7.8125s SELF REFRESH CURRENT: CKE 0.2V OPERATING CURRENT: Four device bank interleaving READs (BL = 4) with auto precharge, tRC = tRC (MIN); t CK = tCK (MIN); Address and control inputs change only during Active READ, or WRITE commands IDD0 1,125 1,125 945 1,080 mA 20, 44 IDD1 1,530 1,440 1,305 1,395 mA 20, 44 IDD2P 36 36 36 36 mA 21, 28, 46 IDD2F 450 405 405 405 mA 47 IDD3P 270 225 225 270 mA 21, 28, 46 IDD3N 540 450 450 450 mA 42 IDD4R 1,575 1,350 1,350 1,575 mA 20, 44 IDD4W 1,395 1,215 1,215 1,710 mA 20 IDD5 IDD5A IDD6 IDD7 2,295 54 36 3,645 2,115 54 36 3,150 2,115 54 36 3,150 2,205 54 36 3,285 mA mA mA mA 20, 46 24, 46 9 20, 45 09005aef807d56a1 DDF9C16_32_64x72G_D.fm - Rev. D 9/03 EN 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. 128MB, 256MB, 512MB (x72, ECC) 184-PIN REGISTERED DDR SDRAM DIMM Table 14: IDD Specifications and Conditions - 512MB DDR SDRAM components only Notes: 1-5, 8, 10, 12, 43; notes appear on pages 20-23; 0C TA +70C; VDD = VDDQ = +2.5V 0.2V MAX PARAMETER/CONDITION SYM -335 -262 -26A/ -265 -202 UNITS NOTES OPERATING CURRENT: One device bank; Active-Precharge; t RC = tRC (MIN); tCK = tCK (MIN); DQ, DM and DQS inputs changing once per clock cyle; Address and control inputs changing once every two clock cycles OPERATING CURRENT: One device bank; Active -Read Precharge; Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks idle; Power-down mode; tCK = tCK (MIN); CKE = (LOW) IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle; tCK = tCK MIN; CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device bank; Active-Precharge; tRC = tRAS (MAX); t CK = tCK (MIN); DQ, DM andDQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle t RC = tRC (MIN) AUTO REFRESH CURRENT t RC = 7.8125s SELF REFRESH CURRENT: CKE 0.2V OPERATING CURRENT: Four device bank interleaving READs (BL = 4) with auto precharge, tRC = tRC (MIN); t CK = tCK (MIN); Address and control inputs change only during Active READ, or WRITE commands IDD0 1,170 1,170 1,035 1,035 mA 20, 44 IDD1 1,440 1,440 1,305 1,305 mA 20, 44 IDD2P 45 45 45 45 mA 21, 28, 46 IDD2F 405 405 360 360 mA 47 IDD3P 315 315 270 270 mA 21, 28, 46 IDD3N 405 405 360 360 mA 42 IDD4R 1,485 1,485 1,305 1,305 mA 20, 44 IDD4W 1,395 1,395 1,215 1,215 mA 20 IDD5 IDD5A IDD6 IDD7 2,610 90 45 3,645 2,610 90 45 3,600 2,520 90 45 3,150 2,520 90 45 3,150 mA mA mA mA 20, 46 24, 46 9 20, 45 09005aef807d56a1 DDF9C16_32_64x72G_D.fm - Rev. D 9/03 EN 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. 128MB, 256MB, 512MB (x72, ECC) 184-PIN REGISTERED DDR SDRAM DIMM Table 15: Capacitance Note: 11; notes appear on pages 20-23 PARAMETER Input/Output Capacitance: DQ, DQS, DM Input Capacitance: Command and Address, S#, CKE Input Capacitance: CK, CK# SYMBOL MIN MAX UNITS CI0 CI1 CI2 4 2.5 5 3.5 4 pF pF pF - Table 16: DDR SDRAM Component Electrical Characteristics and Recommended AC Operating Conditions (-335, -262) Notes: 1-5, 8, 10, 12; notes appear on pages 20-23; 0C TA +70C; VDD = VDDQ = +2.5V 0.2V AC CHARACTERISTICS -335 PARAMETER Access window of DQs from CK/CK# CK high-level width CK low-level width Clock cycle time SYMBOL MIN t CL= 2.5 CL = 2 DQ and DM input hold time relative to DQS DQ and DM input setup time relative to DQS DQ and DM input pulse width (for each input) Access window of DQS from CK/CK# DQS input high pulse width DQS input low pulse width DQS-DQ skew, DQS to last DQ valid, per group, per access Write command to first DQS latching transition DQS falling edge to CK rising - setup time DQS falling edge from CK rising - hold time Half clock period Data-out high-impedance window from CK/CK# Data-out low-impedance window from CK/CK# Address and control input hold time (fast slew rate) Address and control input setup time (fast slew rate) Address and control input hold time (slow slew rate) Address and control input setup time (slow slew rate) LOAD MODE REGISTER command cycle time DQ-DQS hold, DQS to first DQ to go non-valid, per access Data hold skew factor ACTIVE to PRECHARGE command ACTIVE to READ with Auto precharge 128MB command 256MB, 512MB ACTIVE to ACTIVE/AUTO REFRESH command period AUTO REFRESH command period ACTIVE to READ or WRITE delay PRECHARGE command period DQS read preamble 09005aef807d56a1 DDF9C16_32_64x72G_D.fm - Rev. D 9/03 EN AC CH t CL t CK (2.5) t CK (2) t DH t DS t DIPW t DQSCK t DQSH t DQSL t DQSQ t DQSS t DSS t DSH t HP t HZ t LZ t IHF t ISF t IHS t ISS t MRD t QH t QHS t RAS t RAP t RAP t RC t RFC t RCD t RP t RPRE t 16 -0.7 0.45 0.45 6 7.5 0.45 0.45 1.75 -0.60 0.35 0.35 0.75 0.2 0.2 t -262 MAX MIN MAX +0.7 0.55 0.55 13 13 -0.75 0.45 0.45 7.5 7.5/10 0.5 0.5 1.75 -0.75 0.35 0.35 +0.75 0.55 0.55 13 13 +0.60 0.35 1.25 CH, tCL +0.70 -0.70 0.75 0.75 0.80 0.80 12 t HP - tQHS 0.50 42 120,000 18 18 60 72 18 18 0.9 1.1 +0.75 0.5 0.75 1.25 0.2 0.2 t CH, tCL +0.75 -0.75 0.90 0.90 1 1 15 t HP - tQHS 0.50 42 120,000 15 15 60 75 15 15 0.9 1.1 UNITS NOTES ns CK t CK ns ns ns ns ns ns t CK t CK ns t CK t CK t CK ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns t CK t 26 26 40, 48 40, 48 23, 27 23, 27 27 22, 23 30 16, 37 16, 38 12 12 12 12 22, 23 31 41 46 37 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. 128MB, 256MB, 512MB (x72, ECC) 184-PIN REGISTERED DDR SDRAM DIMM Table 16: DDR SDRAM Component Electrical Characteristics and Recommended AC Operating Conditions (-335, -262) (Continued) Notes: 1-5, 8, 10, 12; notes appear on pages 20-23; 0C TA +70C; VDD = VDDQ = +2.5V 0.2V AC CHARACTERISTICS -335 PARAMETER DQS read postamble ACTIVE bank a to ACTIVE bank b command DQS write preamble DQS write preamble setup time DQS write postamble Write recovery time Internal WRITE to READ command delay Data valid output window REFRESH to REFRESH command interval REFRESH to REFRESH command interval Average periodic refresh interval Average periodic refresh interval Terminating voltage delay to VDD Exit SELF REFRESH to non-READ command Exit SELF REFRESH to READ command 09005aef807d56a1 DDF9C16_32_64x72G_D.fm - Rev. D 9/03 EN SYMBOL MIN t RPST RRD t WPRE t WPRES t WPST t WR t WTR na t 128MB 256MB, 512MB 128MB 256MB, 512MB t REFC t REFI t VTD XSNR t XSRD t 17 MAX 0.4 0.6 12 0.25 0 0.4 0.6 15 1 t QH - tDQSQ 140.6 70.3 15.6 7.8 0 75 200 -262 MIN UNITS NOTES MAX 0.4 0.6 12 0.25 0 0.4 0.6 15 1 t QH - tDQSQ 140.6 70.3 15.6 7.8 0 75 200 t CK ns t CK ns t CK ns t CK ns s s s s ns ns t CK 18, 19 17 22 21 21 21 21 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. 128MB, 256MB, 512MB (x72, ECC) 184-PIN REGISTERED DDR SDRAM DIMM Table 17: DDR SDRAM Component Electrical Characteristics and Recommended AC Operating Conditions (-26A, -265, -202) Notes: 1-5, 14; notes appear on pages 20-23; 0C TA +70C; VDD = VDDQ = +2.5V 0.2V AC CHARACTERISTICS -26A/-265 PARAMETER Access window of DQs from CK/CK# CK high-level width CK low-level width Clock cycle time SYMBOL MIN t CL= 2.5 CL = 2 DQ and DM input hold time relative to DQS DQ and DM input setup time relative to DQS DQ and DM input pulse width (for each input) Access window of DQS from CK/CK# DQS input high pulse width DQS input low pulse width DQS-DQ skew, DQS to last DQ valid, per group, per access Write command to first DQS latching transition DQS falling edge to CK rising - setup time DQS falling edge from CK rising - hold time Half clock period Data-out high-impedance window from CK/CK# Data-out low-impedance window from CK/CK# Address and control input hold time (fast slew rate) Address and control input setup time (fast slew rate) Address and control input hold time (slow slew rate) Address and control input setup time (slow slew rate) LOAD MODE REGISTER command cycle time DQ-DQS hold, DQS to first DQ to go non-valid, per access Data hold skew factor ACTIVE to PRECHARGE command ACTIVE to READ with Auto precharge 128MB command 256MB, 512MB ACTIVE to ACTIVE/AUTO REFRESH command period AUTO REFRESH command period ACTIVE to READ or WRITE delay PRECHARGE command period DQS read preamble DQS read postamble ACTIVE bank a to ACTIVE bank b command DQS write preamble DQS write preamble setup time DQS write postamble Write recovery time Internal WRITE to READ command delay Data valid output window 09005aef807d56a1 DDF9C16_32_64x72G_D.fm - Rev. D 9/03 EN AC CH t CL t CK (2.5) t CK (2) t DH t DS t DIPW t DQSCK t DQSH t DQSL t DQSQ t DQSS t DSS t DSH t HP t HZ t LZ t IHF t ISF t IHS t ISS t MRD t QH t QHS t RAS t 18 -0.75 0.45 0.45 7.5 7.5/10 0.5 0.5 1.75 -0.75 0.35 0.35 -202 MAX MIN MAX +0.75 0.55 0.55 13 13 -0.8 0.45 0.45 8 10 0.6 0.6 2 -0.8 0.35 0.35 +0.8 0.55 0.55 13 13 +0.75 0.5 1.25 +0.8 0.6 1.25 0.75 0.75 0.2 0.2 0.2 0.2 t t CH, tCL CH, tCL +0.75 +0.8 -0.75 -0.8 0.90 1.1 0.90 1.1 1 1.1 1 1.1 15 16 t t HP - tQHS HP - tQHS 0.75 1 40 120,000 40 120,000 t RAS(MIN ) - (Burst Length * tCK/2) t RAP 20 20 t RC 65 70 t RFC 75 80 t RCD 20 20 t RP 20 20 t RPRE 0.9 1.1 0.9 1.1 t RPST 0.4 0.6 0.4 0.6 t RRD 15 15 t WPRE 0.25 0.25 t WPRES 0 0 t WPST 0.4 0.6 0.4 0.6 t WR 15 15 t WTR 1 1 t t na QH - tDQSQ QH - tDQSQ UNITS NOTES ns CK t CK ns ns ns ns ns ns t CK t CK ns t CK t CK t CK ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns t CK t CK ns t CK ns t CK ns t CK ns t 26 26 40, 48 40, 48 23, 27 23, 27 27 22, 23 30 16, 37 16, 38 12 12 12 12 22, 23 31 41 46 37 18, 19 17 22 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. 128MB, 256MB, 512MB (x72, ECC) 184-PIN REGISTERED DDR SDRAM DIMM Table 17: DDR SDRAM Component Electrical Characteristics and Recommended AC Operating Conditions (-26A, -265, -202) (Continued) Notes: 1-5, 14; notes appear on pages 20-23; 0C TA +70C; VDD = VDDQ = +2.5V 0.2V AC CHARACTERISTICS -26A/-265 PARAMETER REFRESH to REFRESH command interval REFRESH to REFRESH command interval Average periodic refresh interval Average periodic refresh interval Terminating voltage delay to VDD Exit SELF REFRESH to non-READ command Exit SELF REFRESH to READ command 09005aef807d56a1 DDF9C16_32_64x72G_D.fm - Rev. D 9/03 EN SYMBOL MIN 128MB 256MB, 512MB 128MB 256MB, 512MB REFC t REFI t VTD XSNR t XSRD 19 MIN 140.6 70.3 15.6 7.8 t t MAX -202 0 75 200 140.6 70.3 15.6 7.8 0 80 200 UNITS NOTES MAX s s s s ns ns t CK 21 21 21 21 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. 128MB, 256MB, 512MB (x72, ECC) 184-PIN REGISTERED DDR SDRAM DIMM Notes 1. All voltages referenced to VSS. 2. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Outputs measured with equivalent load: 12. VTT Output (VOUT) 50 Reference Point 30pF 13. 4. AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK/CK#), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals used to test the device is 1V/ns in the range between VIL(AC) and VIH(AC). 5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above [below] the DC input LOW [HIGH] level). 6. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise (non-common mode) on VREF may not exceed 2 percent of the DC value. Thus, from VDDQ/2, VREF is allowed 25mV for DC error and an additional 25mV for AC noise. This measurement is to be taken at the nearest VREF by-pass capacitor. 7. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF. 8. IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time at CL = 2 for -262, -26A, and -202, CL = 2.5 for -335 and -265 with the outputs open. 9. Enables on-chip refresh and address counters. 10. IDD specifications are tested after the device is properly initialized, and is averaged at the defined cycle rate. 11. This parameter is sampled. VDD = +2.5V 0.2V, VDDQ = +2.5V 0.2V, VREF = VSS, f = 100 MHz, TA = 09005aef807d56a1 DDF9C16_32_64x72G_D.fm - Rev. D 9/03 EN 14. 15. 16. 17. 18. 19. 20. 21. 20 25C, VOUT(DC) = VDDQ/2, VOUT (peak to peak) = 0.2V. DM input is grouped with I/O pins, reflecting the fact that they are matched in loading. Command/Address input slew rate = 0.5V/ns. For -335, -262, -26A, and -265, with slew rates 1V/ns and faster, tIS and tIH are reduced to 900ps. If the slew rate is less than 0.5V/ ns, timing must be derated: tIS has an additional 50ps per each 100mV/ ns reduction in slew rate from the 500mV/ns, while tIH remains constant. If the slew rate exceeds 4.5V/ns, functionality is uncertain. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which CK and CK# cross; the input reference level for signals other than CK/CK# is VREF. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE 0.3 x VDDQ is recognized as LOW. The output timing reference level, as measured at the timing reference point indicated in Note 3, is VTT. t HZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (HZ) or begins driving (LZ). If DQS transitions to HIGH above VIH (DC) MIN, then it must not transition to LOW below VIH (DC) MIN prior to tDQSH (MIN). This is not a device limit. The device will operate with a negative value, but system performance could be degraded due to bus turnaround. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The case shown (DQS going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in progress, DQS could be HIGH during this time, depending on tDQSS. MIN (tRC or tRFC) for IDD measurements is the smallest multiple of tCK that meets the minimum absolute value for the respective parameter. tRAS (MAX) for IDD measurements is the largest multiple of tCK that meets the maximum absolute value for tRAS. The refresh period is 64ms. This equates to an average refresh rate of 15.625s (128MB) or 7.8125s (256MB, 512MB). However, an AUTO REFRESH command must be asserted at least once every 140.6s (128MB) or 70.3s (256MB, 512MB); burst refreshing or posting by the DRAM controller greater than eight refresh cycles is not allowed. Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. 128MB, 256MB, 512MB (x72, ECC) 184-PIN REGISTERED DDR SDRAM DIMM 22. The valid data window is derived by achieving other specifications: tHP (tCK/2), tDQSQ, and tQH (tQH = tHP - tQHS). The data valid window derates directly porportional with the clock duty cycle and a practical data valid window can be derived. The clock is allowed a maximum duty cycle variation of 45/55. Functionality is uncertain when operating beyond a 45/55 ratio. Figure 7, Derating Data Valid Window, shows derating curves for duty cycles between 50/50 and 45/55. 23. Each byte lane as a corresponding DQS. 24. This limit is actually a nominal value and does not result in a fail value. CKE is HIGH during REFRESH command period (tRFC [MIN]) else CKE is LOW (i.e., during standby). 25. To maintain a valid level, the transitioning edge of the input must: a. Sustain a constant slew rate from the current AC level through to the target AC level, VIL (AC) or VIH (AC). 26. 27. 28. 29. 30. b. Reach at least the target AC level. c. After the AC target level is reached, continue to maintain at least the target DC level, VIL (DC) or VIH (DC). JEDEC specifies CK and CK# input slew rate must be 1V/ns (2V/ns differentially). DQ and DM input slew rates must not deviate from DQS by more than 10 percent. If the DQ/ DM/DQS slew rate is less than 0.5V/ns, timing must be derated: 50ps must be added to tDS and t DH for each 100mv/ns reduction in slew rate. If slew rate exceeds 4V/ns, functionality is uncertain. VDD must not vary more than 4 percent if CKE is not active while any bank is active. The clock is allowed up to 150ps of jitter. Each timing parameter is allowed to vary by the same amount. t HP min is the lesser of tCL minimum and tCH minimum actually applied to the device CK and CK# inputs, collectively during bank active. Figure 7: Derating Data Valid Window (tQH - tDQSQ) 3.8 3.750 3.700 3.6 3.400 3.350 3.4 3.650 3.600 3.550 3.500 3.450 3.300 3.400 3.250 3.200 3.150 3.2 NA -335 -262/-26A/-265 @ tCK = 10ns -202 @ tCK = 10ns -262/-26A/-265 @ tCK = 7.5ns -202 @ tCK = 8ns ns 3.0 2.8 2.6 3.100 2.500 2.463 2.425 2.388 2.4 3.350 2.313 2.275 3.250 3.050 3.000 2.350 3.300 2.238 2.200 2.950 2.163 2.2 2.900 2.125 2.0 1.8 50/50 49.5/50.5 49/51 48.5/52.5 48/52 47.5/53.5 47/53 46.5/54.5 46/54 45.5/55.5 45/55 Clock Duty Cycle 09005aef807d56a1 DDF9C16_32_64x72G_D.fm - Rev. D 9/03 EN 21 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. 128MB, 256MB, 512MB (x72, ECC) 184-PIN REGISTERED DDR SDRAM DIMM 31. READs and WRITEs with auto precharge are not allowed to be issued until tRAS(MIN) can be satisfied prior to the internal precharge command being issued. 32. Any positive glitch in the nominal voltage must be less than 1/3 of the clock and not more than +400mV (2.9V max), whichever is less. Any negative glitch must be less than 1/3 of the clock cycle and not exceed -300mV (2.2V min), whichever is more positive. However, the DC average cannot be below 2.3V minimum. 33. Normal Output Drive Curves: a. The full variation in driver pull-down current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure 8, Pull-Down Characteristics. b. The variation in driver pull-down current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure 8, Pull-Down Characteristics. c. The full variation in driver pull-up current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure 9, Pull-Up Characteristics. d. The variation in driver pull-up current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure 9, Pull-Up Characteristics. e. The full variation in the ratio of the maximum to minimum pull-up and pull-down current should be between 0.71 and 1.4, for device drain-to-source voltages from 0.1V to 1.0V, and at the same voltage and temperature. f. The full variation in the ratio of the nominal pull-up to pull-down current should be unity 10 percent, for device drain-to-source voltages from 0.1V to 1.0V. The voltage levels used are derived from a minimum VDD level and the referenced test load. In practice, the voltage levels obtained from a properly terminated bus will provide significantly different voltage values. VIH overshoot: VIH(MAX) = VDDQ + 1.5V for a pulse width 3ns and the pulse width can not be greater than 1/3 of the cycle rate. VIL undershoot: VIL(MIN) = -1.5V for a pulse width 3ns and the pulse width can not be greater than 1/3 of the cycle rate. VDD and VDDQ must track each other. This maximum value is derived from the referenced test load. In practice, the values obtained in a typical terminated design may reflect up to 310ps less for tHZ (MAX) and the last DVW. tHZ (MAX) will prevail over tDQSCK (MAX) + tRPST (MAX) condition. tLZ (MIN) will prevail over t DQSCK (MIN) + tRPRE (MAX) condition. For slew rates greater than 1V/ns the (LZ) transition will start about 310ps earlier. During initialization, VDDQ, VTT, and VREF must be equal to or less than VDD + 0.3V. Alternatively, VTT may be 1.35V maximum during power up, even if VDD/VDDQ are 0V, provided a minimum of 42W of series resistance is used between the VTT supply and the input pin. The current Micron part operates below the slowest JEDEC operating frequency of 83 MHz. As such, future die may not reflect this option. t RAP tRCD. Does not apply to -335 speed grade. 34. 35. 36. 37. 38. 39. 40. 41. Figure 8: Pull-Down Characteristics Figure 9: Pull-Up Characteristics 0 160 -20 um 140 Maxim Maximum -40 120 IOUT (mA) 80 Nominal low 60 -80 -100 Nom inal low -120 -140 Minimum 40 Nominal high -60 high IOUT (mA) Nominal 100 Min imu m -160 20 -180 -200 0 0.0 0.5 1.0 1.5 2.0 0.0 2.5 09005aef807d56a1 DDF9C16_32_64x72G_D.fm - Rev. D 9/03 EN 0.5 1.0 1.5 2.0 2.5 VDDQ - VOUT (V) VOUT (V) 22 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. 128MB, 256MB, 512MB (x72, ECC) 184-PIN REGISTERED DDR SDRAM DIMM 42. For -335, -262, -26A and -265, IDD3N is specified to be 35mA at 100 MHz. 43. When an input signal is HIGH or LOW, it is defined as a steady state logic HIGH or LOW. 44. Random addressing changing and 50 percent of data changing at every transfer. 45. Random addressing changing and 100 percent of data changing at every transfer. 46. CKE must be active (high) during the entire time a refresh command is executed. That is, from the time the AUTO REFRESH command is registered, CKE must be active at each rising clock edge, until t REF later. 09005aef807d56a1 DDF9C16_32_64x72G_D.fm - Rev. D 9/03 EN 47. IDD2N specifies the DQ, DQS, and DM to be driven to a valid high or low logic level. IDD2Q is similar to IDD2F except IDD2Q specifies the address and control inputs to remain stable. Although IDD2F, IDD2N, and IDD2Q are similar, IDD2F is "worst case." 48. Whenever the operating frequency is altered, not including jitter, the DLL is required to be reset. This is followed by 200 clock cycles (before READ commands). 49. Leakage number reflects the worst case leakage possible through the module pin, not what each memory device contributes. 23 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. 128MB, 256MB, 512MB (x72, ECC) 184-PIN REGISTERED DDR SDRAM DIMM Table 18: Register Timing Requirements and Switching Characteristics Note: 1 0C TA 70C VDD = 2.5V 0.2V REGISTER SSTL (bit pattern by JESD82-3 or JESD82-4) SYMBOL PARAMERTER fclock Clock Frequency tpd Clock to Output Time tPHL Reset To Output Time tw Pulse Duration tact Differential Inputs Active Time Differential Inputs Inactive Time Setup Time, Fast Slew Rate Setup Time, Slow Slew Rate Hold Time, Fast Slew Rate Hold Time, Slow Slew Rate tinact tsu th CONDITION MIN MAX UNITS - 200 MHz 30pF to GND and 50 Ohms to Vtt 1.1 2.8 ns - 5 ns CK, CK# HIGH or LOW 2.5 - ns - 22 ns 2 - 22 ns 3 0.75 0.9 0.75 0.9 - ns ns ns ns 4, 6 5, 6 4, 6 5, 6 Data Before CK HIGH, CK# LOW Data After CK HIGH, CK# LOW NOTES NOTE: 1. Timing and switching specifications for the register listed above are critical for proper operation of the DDR SDRAM Registered DIMMs. These are meant to be a subset of the parameters for the specific device used on the module. Detailed information for this register is available in JEDEC Standard JESD82. 2. Data inputs must be low a minimum time of tact max, after RESET# is taken HIGH. 3. Data and clock inputs must be held at valid levels (not floating) a minimum time of tinact max, after RESET# is taken LOW. 4. For data signal input slew rate 1 V/ns. 5. For data signal input slew rate 0.5 V/ns and < 1V/ns. 6. CK, CK# signals input slew rate 1V/ns. 09005aef807d56a1 DDF9C16_32_64x72G_D.fm - Rev. D 9/03 EN 24 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. 128MB, 256MB, 512MB (x72, ECC) 184-PIN REGISTERED DDR SDRAM DIMM Table 19: PLL Clock Driver Timing Requirements and Switching Characteristics Note: 1 TA = 0-70C VDD = 2.5V 0.2V PARAMETER SYMBOL MIN NOMINAL MAX UNITS NOTES CK 60 - 170 MHz 2, 3 DC 40 - 60 % STAB - - 100 ms -75 - 75 ps AE -50 0 50 ps SKO - - 100 ps Operating Clock Frequency f Inupt Duty Cycle t Stabilization Time t Cycle to Cycle Jitter t JITCC t Static Phase Offeset Output Clock Skew t 4 5 Period Jitter t JITPER -75 - 75 ps 6 Half-Period Jitter t JITHPER -100 - 100 ps 6 Input Clock Slew Rate t LSI 1.0 - 4 V/ns Output Clock Slew Rate t LSO 1.0 - 2 V/ns 7 NOTE: 1. Timing and switching specifications for the PLL listed above are critical for proper operation of the DDR SDRAM Registered DIMMs. These are meant to be a subset of the parameters for the specific device used on the module. Detailed information for this PLL is available in JEDEC Standard JESD82. 2. The PLL must be able to handle spread spectrum induced skew. 3. Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not required to meet the other timing parameters. (Used for low-speed system debug.) 4. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal after power up. 5. Static Phase Offset does not include Jitter. 6. Period Jitter and Half-Period Jitter specifications are separate specifications that must be met independently of each other. 7. The Output Slew Rate is determined from the IBIS model: VDD CDCV857 VCK R=60 R=60 VDD/2 VCK GND 09005aef807d56a1 DDF9C16_32_64x72G_D.fm - Rev. D 9/03 EN 25 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. 128MB, 256MB, 512MB (x72, ECC) 184-PIN REGISTERED DDR SDRAM DIMM SPD Clock and Data Conventions SPD Acknowledge Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (Figure 10, Data Validity, and Figure 11, Definition of Start and Stop). Acknowledge is a software convention used to indicate successful data transfers. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data (Figure 12, Acknowledge Response From Receiver). The SPD device will always respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a WRITE operation have been selected, the SPD device will respond with an acknowledge after the receipt of each subsequent eight-bit word. In the read mode the SPD device will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the slave will continue to transmit data. If an acknowledge is not detected, the slave will terminate further data transmissions and await the stop condition to return to standby power mode. SPD Start Condition All commands are preceded by the start condition, which is a HIGH-to-LOW transition of SDA when SCL is HIGH. The SPD device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. SPD Stop Condition All communications are terminated by a stop condition, which is a LOW-to-HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the SPD device into standby power mode. Figure 10: Data Validity Figure 11: Definition of Start and Stop SCL SCL SDA SDA DATA STABLE DATA CHANGE DATA STABLE START BIT STOP BIT Figure 12: Acknowledge Response From Receiver SCL from Master 8 9 Data Output from Transmitter Data Output from Receiver Acknowledge 09005aef807d56a1 DDF9C16_32_64x72G_D.fm - Rev. D 9/03 EN 26 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. 128MB, 256MB, 512MB (x72, ECC) 184-PIN REGISTERED DDR SDRAM DIMM Table 20: EEPROM Device Select Code The most significant bit (b7) is sent first DEVICE TYPE IDENTIFIER SELECT CODE CHIP ENABLE RW b7 b6 b5 b4 b3 b2 b1 b0 1 0 0 1 1 1 0 0 SA2 SA2 SA1 SA1 SA0 SA0 RW RW Memory Area Select Code (two arrays) Protection Register Select Code Table 21: EEPROM Operating Modes MODE RW BIT WC BYTES 1 0 1 1 0 0 VIH or VIL VIH or VIL VIH or VIL VIH or VIL VIL VIL 1 1 1 1 1 16 Current Address Read Random Address Read Sequential Read Byte Write Page Write INITIAL SEQUENCE START, Device Select, RW = `1' START, Device Select, RW = `0', Address reSTART, Device Select, RW = `1' Similar to Current or Random Address Read START, Device Select, RW = `0' START, Device Select, RW = `0' Figure 13: SPD EEPROM Timing Diagram tF t HIGH tR t LOW SCL t SU:STA t HD:STA t SU:DAT t HD:DAT t SU:STO SDA IN t DH t AA t BUF SDA OUT UNDEFINED 09005aef807d56a1 DDF9C16_32_64x72G_D.fm - Rev. D 9/03 EN 27 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. 128MB, 256MB, 512MB (x72, ECC) 184-PIN REGISTERED DDR SDRAM DIMM Table 22: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced to VDDSPD; VDDSPD = +2.3V to +3.6V PARAMETER/CONDITION SYMBOL MIN MAX UNITS Supply Voltage Input High Voltage: Logic 1; All inputs Input Low Voltage: Logic 0; All inputs Output Low Voltage: IOUT = 3mA Input Leakage Current: VIN = GND to VDD Output Leakage Current: VOUT = GND to VDD Standby Current: Power Supply Current, READ: SCL clock frequency = 100 KHz VDDSPD VIH VIL VOL ILI ILO ISB ICCR 2.3 VDDSPD X 0.7 -0.6 - 0.10 0.05 1.6 0.4 3.6 VDDSPD + 0.5 VDDSPD x 0.3 0.4 3 3 4 1 V V V V A A A mA Powr Supply Current, WRITE: SCL clock frequency = 100 KHz ICCW 2 3 mA Table 23: Serial Presence-Detect EEPROM AC Operating Conditions All voltages referenced to VDDSPD; VDDSPD = +2.3V to +3.6V PARAMETER/CONDITION SYMBOL t AA BUF t DH t F t HD:DAT t HD:STA t HIGH t I t LOW t R f SCL t SU:DAT t SU:STA t SU:STO t WRC SCL LOW to SDA data-out valid Time the bus must be free before a new transition can start Data-out hold time SDA and SCL fall time Data-in hold time Start condition hold time Clock HIGH period Noise suppression time constant at SCL, SDA inputs Clock LOW period SDA and SCL rise time SCL clock frequency Data-in setup time Start condition setup time Stop condition setup time WRITE cycle time t MIN MAX UNITS NOTES 0.2 1.3 200 0.9 s s ns ns s s s ns s s KHz ns s s ms 1 300 0 0.6 0.6 50 1.3 0.3 400 100 0.6 0.6 10 2 2 3 4 NOTE: 1. To aviod spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA. 2. This parameter is sampled. 3. For a reSTART condition, or following a WRITE cycle. 4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write sequence to the end of the EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address. 09005aef807d56a1 DDF9C16_32_64x72G_D.fm - Rev. D 9/03 EN 28 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. 128MB, 256MB, 512MB (x72, ECC) 184-PIN REGISTERED DDR SDRAM DIMM Table 24: Serial Presence-Detect Matrix "1"/"0": Serial Data, "driven to HIGH"/"driven to LOW" BYTE DESCRIPTION ENTRY (VERSION) 0 1 2 3 Number of SPD Bytes Used by Micron Total Number of Bytes in SPD Device Fundamental Memory Type Number of Row Addresses on Assembly Number of Column Addresses on Assembly Number of Physical Banks on DIMM Module Data Width Module Data Width (Continued) Module Voltage Interface Levels SDRAM Cycle Time, (tCK) (CAS Latency = 2.5) (See note 1) 128 256 SDRAM DDR 12 or 13 80 08 07 0C 80 08 07 0D 80 08 07 0D 10, 11 0A 0A 0B 1 72 0 SSTL 2.5V 6ns(-335) 7ns (-262/-26A) 7.5ns (-265) 8ns (-202) 0.7(-335) 0.75ns (-262/-26A/-265) 0.8ns (-202) ECC 15.62 or 7.81s/SELF 8 01 48 00 04 60 70 75 80 70 75 80 02 80 08 01 48 00 04 60 70 75 80 70 75 80 02 82 08 01 48 00 04 60 70 75 80 70 75 80 02 82 08 8 1 clock 08 01 08 01 08 01 2, 4, 8 4 2, 2.5 0 1 Registered, PLL/Diff. Clock Fast/Concurrent AP 7.5ns (-335/-262/-26A) 10ns (-265/-202) 0.70ns (-335) 0.75ns (-262/-26A/-265) 0.8ns (-202) N/A 0E 04 0C 01 02 26 0E 04 0C 01 02 26 0E 04 0C 01 02 26 C0 75 A0 70 75 80 00 C0 75 A0 70 75 80 00 C0 75 A0 70 75 80 00 N/A 00 00 00 48 3C 50 30 3C 48 3C 50 30 3C 48 3C 50 30 3C 4 5 6 7 8 9 10 SDRAM Access From Clock,(tAC) (CAS Latency = 2.5) 11 12 13 Module Configuration Type Refresh Rate/Type SDRAM Device Width (Primary SDRAM) Error-checking SDRAM Data Width Minimum Clock Delay, Back-to-Back Random Column Access Burst Lengths Supported Number of Banks on SDRAM Device CAS Latencies Supported CS Latency WE Latency SDRAM Module Attributes 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 SDRAM Device Attributes: General SDRAM Cycle Time, (tCK), CAS Latency = 2 SDRAM Access from CK , (tAC), CAS Latency = 2 SDRAM Cycle Time, (tCK), CAS Latency = 1.5 SDRAM Access from CK , (tAC), CAS Latency = 1.5 Minimum Row Precharge Time, (tRP) MT9VDDF1672 MT9VDDF3272 MT9VDDF6472 18ns (-335) 15ns (-262) 20ns (-202/-265/-26A) 12ns (-335) Minimum Row Active to Row Active, 15ns (-262/-26A/-265/-202) (tRRD) 09005aef807d56a1 DDF9C16_32_64x72G_D.fm - Rev. D 9/03 EN 29 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. 128MB, 256MB, 512MB (x72, ECC) 184-PIN REGISTERED DDR SDRAM DIMM Table 24: Serial Presence-Detect Matrix "1"/"0": Serial Data, "driven to HIGH"/"driven to LOW" BYTE DESCRIPTION ENTRY (VERSION) t 29 Minimum RAS# to CAS# Delay, ( RCD) 30 Minimum RAS# Pulse Width, (tRAS) (See note 2) 31 32 Module Rank Density Address and Command Setup Time, (tIS) (See note 3) 33 Address and Command Hold Time, (tIH) (See note 3) 34 Data/ Data Mask Input Setup Time, (tDS) 35 Data/ Data Mask Input Hold Time, (tDH) 36-40 Reserved 41 Min Active Auto Refresh Time (tRC) 42 43 44 45 Minimum Auto Refresh to Active/ Auto Refresh Command Period, (tRFC) SDRAM Device Max Cycle Time (tCKMAX) SDRAM Device Max DQS-DQ Skew Time (tDQSQ) SDRAM Device Max Read Data Hold Skew Factor (tQHS) 46 47 48-61 62 63 Reserved DIMM Height Reserved SPD Revision Checksum For Bytes 0-62 64 65-71 72 73-90 91 92 Manufacturer's JEDEC ID Code Manufacturer's JEDEC ID Code Manufacturing Location Module Part Number (ASCII) PCB Identification Code Identification Code (Continued) 09005aef807d56a1 DDF9C16_32_64x72G_D.fm - Rev. D 9/03 EN MT9VDDF1672 MT9VDDF3272 MT9VDDF6472 18ns (-335) 15ns (-262) 20ns (-202/-265/-26A) 42ns (-335) 45ns (-262/-26A/-265) 40ns (-202) 128MB or 256MB 0.80ns (-335) 1ns (-262/-26A/-265) 1.1ns (-202) 0.80ns (-335) 1ns (-262/-26A/-265) 1.1ns (-202) 0.45ns (-335) 0.50ns (-262/-26A/-265) 0.60ns (-202) 0.45ns (-335) 0.50ns (-262/-26A/-265) 0.60ns (-202) 60ns (-335/-262) 65ns (-26A/-265) 70ns (-202) 72ns (-335) 75ns (-262/-26A/-265) 80ns (-202) 12ns (-335) 13ns (-262/-26A/-265/-202) 0.4ns (-335) 0.5ns (-262/-26A/-265) 0.6ns (-202) 0.5ns (-335) 0.75ns (-262/-26A/-265) 1.0ns (-202) Release 1.0 -335 -262 -26A -265 -202 MICRON (Continued) 01-12 1-9 0 30 48 3C 50 2A 2D 28 20 80 A0 B0 80 A0 B0 45 50 60 45 50 60 00 3C 41 46 48 4B 50 30 34 28 32 3C 50 75 A0 00 01 00 10 12 EF 1C 4C E7 2C FF 01-0C Variable Data 01-09 00 48 3C 50 2A 2D 28 40 80 A0 B0 80 A0 B0 45 50 60 45 50 60 00 3C 41 46 48 4B 50 30 34 28 32 3C 50 75 A0 00 01 00 10 35 D2 FF 2F CA 2C FF 01-0C Variable Data 01-09 00 48 3C 50 2A 2D 28 40 80 A0 B0 80 A0 B0 45 50 60 45 50 60 00 3C 41 46 48 4B 50 30 34 28 32 3C 50 75 A0 00 01 00 10 76 13 40 70 0B 2C FF 01-0C Variable Data 01-09 00 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. 128MB, 256MB, 512MB (x72, ECC) 184-PIN REGISTERED DDR SDRAM DIMM Table 24: Serial Presence-Detect Matrix "1"/"0": Serial Data, "driven to HIGH"/"driven to LOW" BYTE 93 94 95-98 99-127 DESCRIPTION ENTRY (VERSION) MT9VDDF1672 MT9VDDF3272 MT9VDDF6472 Variable Data Variable Data Variable Data - Year of Manufacture in BCD Week of Manufacture in BCD Module Serial Number Manufacturer-specific Data (RSVD) Variable Data Variable Data Variable Data - Variable Data Variable Data Variable Data - NOTE: 1. Value for -26A tCK set to 7ns (0x70) for optimum BIOS compatibility. Actual device spec. vaule is 7.5ns. 2. The value of tRAS used for -26A/-265 modules is calculated from tRC - tRP. Actual device spec value is 40 ns. 3. The JEDEC SPD specification allows fast or slow slew rate values for these bytes. The worst-case (slow slew rate) value is repesented here. Systems requiring the fast slew rate setup and hold values are supported, provided the faster minimum slew rate is met. 09005aef807d56a1 DDF9C16_32_64x72G_D.fm - Rev. D 9/03 EN 31 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. 128MB, 256MB, 512MB (x72, ECC) 184-PIN REGISTERED DDR SDRAM DIMM Figure 14: 184-PIN DIMM DDR Modules FRONT VIEW 0.125 (3.175) MAX 5.256 (133.50) 5.244 (133.20) 0.079 (2.00) R (4X) U12 U1 U2 U3 U4 U6 U5 U11 U7 U8 U9 1.131 (28.73) 1.119 (28.42) U13 0.098 (2.50) D (2X) 0.700 (17.78) TYP. U10 0.091 (2.30) TYP. 0.035 (0.90) R PIN 1 0.050 (1.27) 0.040 (1.02) TYP. TYP. 2.55 (64.77) 0.091 (2.30) TYP. 0.394 (10.00) TYP. 0.250 (6.35) TYP. 1.95 (49.53) 0.054 (1.37) 0.046 (1.17) PIN 92 4.750 (120.65) BACK VIEW No Components This Side of Module PIN 184 PIN 93 NOTE: All dimensions in inches (millimeters) MAX or typical where noted. MIN Data Sheet Designation Released (No Mark): This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range for production devices. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. (R) 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc. 09005aef807d56a1 DDF9C16_32_64x72G_D.fm - Rev. D 9/03 EN 32 Micron Technology, Inc., reserves the right to change products or specifications without notice.. (c)2003 Micron Technology, Inc