09005aef807d56a1
DDF9C16_32_64x72G_D.fm - Rev. D 9/03 EN 1©2003 Micron Technology, Inc.
128MB, 256MB, 512MB (x72, ECC)
184-PIN REGISTERED DDR SDRAM DIMM
REGISTERED
DDR SDRAM DIMM
MT9VDDF1672 – 128MB
MT9VDDF3272 – 256MB
MT9VDDF6472 – 512MB
For the latest data sheet, please refer to the Micronâ Web
site: www.micron.com/moduleds
Features
• 184-pin, dual, in-line memory module (DIMM)
• Fast data transfer rates PC 1600, PC2100, or PC2700
• Utilizes 200MT/s, 266 MT/s, and 333 MT/s DDR
SDRAM components
• Registered Inputs with one-clock delay
• Phase-lock loop (PLL) clock driver to reduce loading
• ECC, 1-bit error detection and correction
• 128MB (16 Meg x 72); 256MB (32 Meg x 72); and
512MB (64 Meg x 72)
•V
DD = VDDQ = +2.5V
•V
DDSPD = +2.3V to +3.6V
• 2.5V I/O (SSTL_2 compatible)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• Internal, pipelined double data rate (DDR)
architecture; two data accesses per clock cycle
• Bidirectional data strobe (DQS) transmitted/received
with data—i.e., source-synchronous data capture
• Differential clock inputs CK and CK#
• Four internal device banks for concurrent operation
• Programmable burst lengths: 2, 4, or 8
• Auto precharge option
• Auto Refresh and Self Refresh Modes
• 15.625µs (128MB) or 7.8125µs (256MB, 512MB)
maximum average periodic refresh interval
• Serial Presence-Detect (SPD) with EEPROM
• Programmable READ CAS latency
•Gold edge contacts
Figure 1: 184-Pin DIMM (MO-206)
NOTE: 1. Consult factory for availability of lead-free prod-
ucts.
2. CL = CAS (READ) Latency; Registered mode will
add one clock cycle to CL.
OPTIONS MARKING
•Package
184-pin DIMM (Standard) G
184-pin DIMM (Lead-free) Y
•Frequency/CAS Latency
2
6ns/167 MHz (33 MT/s) CL = 2.5 -335
7.5ns/133 MHz (266 MT/s) CL = 2 -262
7.5ns/133 MHz (266 MT/s) CL = 2 -26A
7.5ns/133 MHz (266 MT/s) CL = 2.5 -265
10ns/100 MHz (200 MT/s) CL = 2 -202
Table 1: Address Table
128MB 256MB 512MB
Refresh Count 4K 8K 8K
Row Addressing 4K (A0–A11) 8K (A0–A12) 8K (A0–A12)
Device Bank Addressing 4 (BA0, BA1) 4 (BA0, BA1) 4 (BA0, BA1)
Device Configuration 16 Meg x 8 32 Meg x 8 64 Meg x 8
Column Addressing 1K (A0–A9) 1K (A0–A9) 2K (A0–A9, A11)
Module Rank Addressing 1 (S0#) 1 (S0#) 1 (S0#)
128MB, 256MB, 512MB (x72, ECC)
184-PIN REGISTERED DDR SDRAM DIMM
09005aef807d56a1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDF9C16_32_64x72G_D.fm - Rev. D 9/03 EN 2©2003 Micron Technology. Inc.
Table 2: Part Numbers and Timing Parameters
PART NUMBER MODULE
DENSITY
CONFIGURATION MODULE
BANDWIDTH
MEMORY CLOCK/
DATA RATE
LATENCY
(CL - tRCD - tRP)
MT9VDDF1672G-335__ 128MB 16 Meg x 72 2.7 GB/s 6ns/333 MT/s 2.5-3-3
MT9VDDF1672Y-335__ 128MB 16 Meg x 72 2.7 GB/s 6ns/333 MT/s 2.5-3-3
MT9VDDF1672G-262__ 128MB 16 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2-2-2
MT9VDDF1672Y-262__ 128MB 16 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2-2-2
MT9VDDF1672G-26A__ 128MB 16 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2-3-3
MT9VDDF1672Y-26A__ 128MB 16 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2-3-3
MT9VDDF1672G-265__ 128MB 16 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3
MT9VDDF1672Y-265__ 128MB 16 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3
MT9VDDF1672G-202__ 128MB 16 Meg x 72 1.6 GB/s 10ns/200 MT/s 2-2-2
MT9VDDF1672Y-202__ 128MB 16 Meg x 72 1.6 GB/s 10ns/200 MT/s 2-2-2
MT9VDDF3272G-335__ 256MB 32 Meg x 72 2.7 GB/s 6ns/333 MT/s 2.5-3-3
MT9VDDF3272Y-335__ 256MB 32 Meg x 72 2.7 GB/s 6ns/333 MT/s 2.5-3-3
MT9VDDF3272G-262__ 256MB 32 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2-2-2
MT9VDDF3272Y-262__ 256MB 32 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2-2-2
MT9VDDF3272G-26A__ 256MB 32 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2-3-3
MT9VDDF3272Y-26A__ 256MB 32 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2-3-3
MT9VDDF3272G-265__ 256MB 32 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3
MT9VDDF3272Y-265__ 256MB 32 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3
MT9VDDF3272G-202__ 256MB 32 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2-2-2
MT9VDDF3272Y-202__ 256MB 32 Meg x 72 1.6 GB/s 10ns/200 MT/s 2-2-2
MT9VDDF6472G-335__ 512MB 64 Meg x 72 2.7 GB/s 6ns/333 MT/s 2.5-3-3
MT9VDDF6472Y-335__ 512MB 64 Meg x 72 2.7 GB/s 6ns/333 MT/s 2.5-3-3
MT9VDDF6472G-262__ 512MB 64 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2-2-2
MT9VDDF6472Y-262__ 512MB 64 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2-2-2
MT9VDDF6472G-26A__ 512MB 64 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2-3-3
MT9VDDF6472Y-26A__ 512MB 64 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2-3-3
MT9VDDF6472G-265__ 512MB 64 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3
MT9VDDF6472Y-265__ 512MB 64 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3
MT9VDDF6472G-202__ 512MB 64 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2-2-2
MT9VDDF6472Y-202__ 512MB 64 Meg x 72 1.6 GB/s 10ns/200 MT/s 2-2-2
NOTE:
All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for
current revision codes. Example: MT9VDDF3272G-265B1.
128MB, 256MB, 512MB (x72, ECC)
184-PIN REGISTERED DDR SDRAM DIMM
09005aef807d56a1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDF9C16_32_64x72G_D.fm - Rev. D 9/03 EN 3©2003 Micron Technology. Inc.
NOTE:
1. Pin 115 is NC for 128MB, or A12 for 256MB and 512MB.
Figure 2: Pin Locations
Table 3: Pin Assignment
(184-Pin DIMM Front)
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL
1VREF 24 DQ17 47 DQS8 70 VDD
2DQ025 DQS2 48 A0 71 NC
3V
SS 26 VSS 49 CB2 72 DQ48
4DQ127 A9 50 VSS 73 DQ49
5DQS028 DQ18 51 CB3 74 VSS
6DQ229 A7 52 BA1 75 DNU
7VDD 30 VDDQ 53 DQ32 76 DNU
8DQ331DQ1954 VDDQ 77 VDDQ
9NC32 A5 55 DQ33 78 DQS6
10 RESET# 33 DQ24 56 DQS4 79 DQ50
11 VSS 34 VSS 57 DQ34 80 DQ51
12 DQ8 35 DQ25 58 VSS 81 VSS
13 DQ9 36 DQS3 59 BA0 82 NC
14 DQS1 37 A4 60 DQ35 83 DQ56
15 VDDQ 38 VDD 61 DQ40 84 DQ57
16 DNU 39 DQ26 62 VDDQ 85 VDD
17 DNU 40 DQ27 63 WE# 86 DQS7
18 VSS 41 A2 64 DQ41 87 DQ58
19 DQ10 42 VSS 65 CAS# 88 DQ59
20 DQ11 43 A1 66 VSS 89 VSS
21 CKE0 44 CB0 67 DQS5 90 DNU
22 VDDQ 45 CB1 68 DQ42 91 SDA
23 DQ16 46 VDD 69 DQ43 92 SCL
Table 4: Pin Assignment
(184-Pin DIMM Back)
PIN
SYMBOL PIN SYMBOL PIN SYMBOL
PIN
SYMBOL
93 VSS 116 VSS 139 VSS 162 DQ47
94 DQ4 117 DQ21 140 DM8 163 NC
95 DQ5 118 A11 141 A10 164 VDDQ
96 VDDQ 119 DM2 142 CB6 165 DQ52
97 DM0 120 VDD 143 VDDQ 166 DQ53
98 DQ6 121 DQ22 144 CB7 167 NC
99 DQ7 122 A8 145 VSS 168 VDD
100 VSS 123 DQ23 146 DQ36 169 DM6
101 NC 124 VSS 147 DQ37 170 DQ54
102 NC 125 A6 148 VDD 171 DQ55
103 NC 126 DQ28 149 DM4 172 VDDQ
104 VDDQ 127 DQ29 150 DQ38 173 NC
105 DQ12 128 VDDQ 151 DQ39 174 DQ60
106 DQ13 129 DM3 152 VSS 175 DQ61
107 DM1 130 A3 153 DQ44 176 VSS
108 VDD 131 DQ30 154 RAS# 177 DM7
109 DQ14 132 VSS 155 DQ45 178 DQ62
110 DQ15 133 DQ31 156 VDDQ 179 DQ63
111 DNU 134 CB4 157 S0# 180 VDDQ
112 VDDQ 135 CB5 158 DNU 181 SA0
113 NC 136 VDDQ 159 DM5 182 SA1
114 DQ20 137 CK0 160 VSS 183 SA2
115
NC/A12
1
138 CK0# 161 DQ46 184 VDDSPD
No Components This Side of Module
Back View
Front View
PIN 93
PIN 144
PIN 145
PIN 184
PIN 1 PIN 52 PIN 53 PIN 92
U1
U2 U3 U4 U5
U12
U11 U13
U6 U7 U8 U9
U10
Indicates a V
DD
or V
DDQ
pin Indicates a V
SS
pin
128MB, 256MB, 512MB (x72, ECC)
184-PIN REGISTERED DDR SDRAM DIMM
09005aef807d56a1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDF9C16_32_64x72G_D.fm - Rev. D 9/03 EN 4©2003 Micron Technology. Inc.
Table 5: Pin Descriptions
Pin numbers may not correlate with symbols. Refer to Pin Assignment tables on page 3 for more information
PIN NUMBERS SYMBOL TYPE DESCRIPTION
10 Reset# Input Asynchronously forces all registered ouputs LOW when RESET#
is LOW. This signal can be used during power-up to ensure CKE
is LOW and DQs are High-Z.
63, 65, 154 WE#, CAS#, RAS# Input Command Inputs: RAS#, CAS#, and WE# (along with S#) define
the command being entered.
137, 138 CK0, CK0# Input Clock: CK, CK# are differential clock inputs. All address and
control input signals are sampled on the crossing of the positive
edge of CK,and negative edge of CK#. Output data (DQ and
DQS) is referenced to the crossings of CK and CK#.
21 CKE0 Input Clock Enable: CKE HIGH activates and CKE LOW deactivates the
internal clock, input buffers and output drivers. Taking CKE
LOW provides PRECHARGE POWER-DOWN and SELF REFRESH
operations (all device banks idle), or ACTIVE POWER-DOWN
(row ACTIVE in any device bank). CKE is synchronous for
POWER-DOWN entry and exit, and for SELF REFRESH entry. CKE
is asynchronous for SELF REFRESH exit and for disabling the
outputs. CKE must be maintained HIGH throughout read and
write accesses. Input buffers (excluding CK, CK# and CKE) are
disabled during POWER-DOWN. Input buffers (excluding CKE)
are disabled during SELF REFRESH. CKE is an SSTL_2 input but
will detect an LVCMOS LOW level after VDD is applied and until
CKE is first brought HIGH. After CKE is brought HIGH, it
becomes an SSTL_2 input only.
157 S0# Input Chip Selects: S# enables (registered LOW) and disables
(registered HIGH) the command decoder. All commands are
masked when S# is registered HIGH. S# is considered part of the
command code.
52, 59 BA0, BA1 Input Bank Address: BA0 and BA1 define to which device bank an
ACTIVE, READ, WRITE, or PRECHARGE command is being
applied.
27, 29, 32, 37, 41, 43, 48,
115 (256MB, 512MB),
118, 122, 125, 130, 141
A0-A11
(128MB)
A0-A12
(256MB, 512MB)
Input Address Inputs: Provide the row address for ACTIVE commands,
and the column address and auto precharge bit (A10) for READ/
WRITE commands, to select one location out of the memory
array in the respective device bank. A10 sampled during a
PRECHARGE command determines whether the PRECHARGE
applies to one device bank (A10 LOW, device bank selected by
BA0, BA1) or all device banks (A10 HIGH). The address inputs
also provide the op-code during a MODE REGISTER SET
command. BA0 and BA1 define which mode register (mode
register or extended mode register) is loaded during the LOAD
MODE REGISTER command.
97, 107, 119, 129, 140,
149, 159, 169, 177
DM0-DM8 Input Data Write Mask: DM LOW allows WRITE operation. DM HIGH
blocks WRITE operation. DM state does not affect READ
command.
5, 14, 25, 36, 47, 56, 67,
78, 86
DQS0-DQS8 Input/
Output
Data Strobe: Output with READ data, input with WRITE data.
DQS is edge-aligned with READ data, centered in WRITE data.
Used to capture data.
44, 45, 49, 51, 134, 135,
142, 144
CB0-CB7 Input/
Output
Check Bits: ECC, 1-bit error detection and correction.
128MB, 256MB, 512MB (x72, ECC)
184-PIN REGISTERED DDR SDRAM DIMM
09005aef807d56a1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDF9C16_32_64x72G_D.fm - Rev. D 9/03 EN 5©2003 Micron Technology. Inc.
2, 4, 6, 8, 12,13, 19, 20,
23, 24, 28, 31, 33, 35, 39,
40, 53, 55, 57, 60, 61, 64,
68, 69, 72, 73, 79, 80, 83,
84, 87, 88, 94, 95, 98, 99,
105, 106, 109, 110, 114,
117, 121, 123, 126, 127,
131, 133, 146, 147, 150,
151, 153, 155, 161, 162,
165, 166, 170, 171, 174,
175, 178, 179
DQ0-DQ63 Input/
Output
Data I/Os: Data bus.
92 SCL Input Serial Clock for Presence-Detect: SCL is used to synchronize the
presence-detect data transfer to and from the module.
181, 182, 183 SA0-SA2 Input Presence-Detect Address Inputs: These pins are used to
configure the presence-detect device.
91 SDA Input/
Output
Serial Presence-Detect Data: SDA is a bidirectional pin used to
transfer addresses and data into and out of the presence-detect
portion of the module.
1V
REF Input SSTL_2 reference voltage.
15, 22, 30, 54, 62, 77, 96,
104, 112, 128, 136, 143,
156, 164, 172, 180
VDDQ Supply DQ Power Supply: +2.5V ±0.2V.
7, 38, 46, 70, 85, 108, 120,
148, 168
VDD Supply Power Supply: +2.5V ±0.2V.
3, 11, 18, 26, 34, 42, 50,
58, 66, 74, 81, 89, 93, 100,
116, 124, 132, 139, 145,
152, 160, 176
VSS Supply Ground.
184 VDDSPD Supply Serial EEPROM positive power supply: +2.3V to +3.6V
16, 17, 75, 76, 90, 111,
158
DNU — Do Not Use: Thes pins are not connected on these modules, but
are assigned pins on other modules in this product family
9, 71, 82, 101, 102, 103,
113, 115 (128MB), 163,
167, 173
NC — No Connect: These pins should be left unconnected.
Table 5: Pin Descriptions
Pin numbers may not correlate with symbols. Refer to Pin Assignment tables on page 3 for more information
PIN NUMBERS SYMBOL TYPE DESCRIPTION
128MB, 256MB, 512MB (x72, ECC)
184-PIN REGISTERED DDR SDRAM DIMM
09005aef807d56a1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDF9C16_32_64x72G_D.fm - Rev. D 9/03 EN 6©2003 Micron Technology. Inc.
Figure 3: Functional Block Diagram
A0
SA0
SERIAL PD SDA
A1
SA1
A2
SA2
S0#
BA0, BA1
A0-A11(128MB)
A0-A12 (256MB, 512MB)
RAS#
RS0#: DDR SDRAMs
RBA0, RBA1: DDR SDRAMs
RA0-RA11: DDR SDRAMs
RA0-RA12: DDR SDRAMs
RRAS#: DDR SDRAMs
RCAS#: DDR SDRAMs
RCKE0: DDR SDRAMs
RWE#: DDR SDRAMs
RESET#
CAS#
CKE0
WE#
CK
CK#
VREF
VSS
DDR SDRAMs
DDR SDRAMs
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
U9
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
U7
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
U6
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
U5
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
U4
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
U2
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM CS# DQS
U1
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM0
RS0#
U3
R
E
G
I
S
T
E
R
S
PLL
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
REGISTER X 2
SCL
DM CS# DQS
DM CS# DQS
DM CS# DQS
DQS0
DM4
DQS4
DM1
DQS1
DM5
DQS5
DM2
DQS2
DM6
DQS6
DM CS# DQS
U8
DM CS# DQS
DM CS# DQS DM CS# DQS
DM CS# DQS
DM3
DQS3
DM7
DQS7
DM8
DQS8
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
VDDQ
VDD DDR SDRAMs
DDR SDRAMs
CK0
CK0#
120 U12
U10
U11, U13
SPD / EEPROM
VDDSPD
WP
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
NOTE:
1. Unless otherwise noted, resistor values are 22W.
2. Per industry standard, Micron utilizes various component speed grades as ref-
erenced in the Module Part Numbering Guide at www.micron.com/number-
guide.
MT46V16M8FB = DDR SDRAMs for 128MB Module
MT46V32M8FB = DDR SDRAMs for 256MB Module
MT46V64M8FB = DDR SDRAMs for 512MB Module
128MB, 256MB, 512MB (x72, ECC)
184-PIN REGISTERED DDR SDRAM DIMM
09005aef807d56a1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDF9C16_32_64x72G_D.fm - Rev. D 9/03 EN 7©2003 Micron Technology. Inc.
General Description
The MT9VDDF1672, MT9VDDF3272, and
MT9VDDF6472 are high-speed, CMOS, dynamic ran-
dom-access, 128MB, 256MB, and 512MB memory
modules organized in x72 (ECC) configuration. DDR
SDRAM modules uss internally configured quad-bank
DDR SDRAM devices.
DDR SDRAM modules use a double data rate archi-
tecture to achieve high-speed operation. The double
data rate architecture is essentially a 2n-prefetch
architecture with an interface designed to transfer two
data words per clock cycle at the I/O pins. A single
read or write access for the DDR SDRAM module effec-
tively consists of a single 2n-bit wide, one-clock-cycle
data transfer at the internal DRAM core and two corre-
sponding n-bit wide, one-half-clock-cycle data trans-
fers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted
externally, along with data, for use in data capture at
the receiver. DQS is an intermittent strobe transmitted
by the DDR SDRAM during READs and by the memory
controller during WRITEs. DQS is edge-aligned with
data for READs and center-aligned with data for
WRITEs.
DDR SDRAM modules operate from differential
clock inputs (CK and CK#); the crossing of CK going
HIGH and CK# going LOW will be referred to as the
positive edge of CK. Commands (address and control
signals) are registered at every positive edge of CK.
Input data is registered on both edges of DQS, and out-
put data is referenced to both edges of DQS, as well as
to both edges of CK.
Read and write accesses to DDR SDRAM modules
are burst oriented; accesses start at a selected location
and continue for a programmed number of locations
in a programmed sequence. Accesses begin with the
registration of an ACTIVE command, which is then fol-
lowed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command
are used to select the device bank and row to be
accessed [BA0, BA1 select devices bank; A0–A11
(128MB), or A0–A12 (256MB, 512MB) select device
row]. The address bits registered coincident with the
READ or WRITE command are used to select the
device bank and starting device column location for
the burst access.
DDR SDRAM modules provide for programmable
READ or WRITE burst lengths of 2, 4, or 8 locations. An
auto precharge function may be enabled to provide a
self-timed row precharge that is initiated at the end of
the burst access.
The pipelined, multibank architecture of DDR
SDRAM modules allows for concurrent operation,
thereby providing high effective bandwidth by hiding
row precharge and activation time.
An auto refresh mode is provided, along with a
power-saving power-down mode. All inputs are com-
patible with the JEDEC Standard for SSTL_2. All out-
puts are SSTL_2, Class II compatible. For more
information regarding DDR SDRAM operation, refer to
the 128Mb, 256Mb, and 512Mb DDR SDRAM compo-
nent data sheets.
PLL and Register Operation
These DDR SDRAM modules operate in registered
mode, where the command/address input signals are
latched in the registers on the rising clock edge and
sent to the DDR SDRAM devices on the following ris-
ing clock edge (data access is delayed by one clock
cycle). A phase-lock loop (PLL) on the module receives
and redrives the differential clock signals (CK, CK#) to
the DDR SDRAM devices. The registers and PLL mini-
mize system and clock loading.
Serial Presence-Detect Operation
These DDR SDRAM modules incorporate serial
presence-detect (SPD). The SPD function is imple-
mented using a 2,048-bit EEPROM. This nonvolatile
storage device contains 256 bytes. The first 128 bytes
can be programmed by Micron to identify the module
type and various SDRAM organizations and timing
parameters. The remaining 128 bytes of storage are
available for use by the customer. System READ/
WRITE operations between the master (system logic)
and the slave EEPROM device (DIMM) occur via a
standard I2C bus using the DIMM’s SCL (clock) and
SDA (data) signals, together with SA (2:0), which pro-
vide eight unique DIMM/EEPROM addresses. Write
protect (WP) is tied to ground on the module, perma-
nently disabling hardware write protect.
Mode Register Definition
The mode register is used to define the specific
mode of operation of the DDR SDRAM device. This
definition includes the selection of a burst length, a
burst type, a CAS latency and an operating mode, as
shown in Figure 4, Mode Register Definition Diagram,
on page 8. The mode register is programmed via the
MODE REGISTER SET command (with BA0 = 0 and
BA1 = 0) and will retain the stored information until it
is programmed again or the device loses power (except
for bit A8, which is self-clearing).
128MB, 256MB, 512MB (x72, ECC)
184-PIN REGISTERED DDR SDRAM DIMM
09005aef807d56a1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDF9C16_32_64x72G_D.fm - Rev. D 9/03 EN 8©2003 Micron Technology. Inc.
Reprogramming the mode register will not alter the
contents of the memory, provided it is performed cor-
rectly. The mode register must be loaded (reloaded)
when all device banks are idle and no bursts are in
progress, and the controller must wait the specified
time before initiating the subsequent operation. Vio-
lating either of these requirements will result in
unspecified operation.
Mode register bits A0–A2 specify the burst length,
A3 specifies the type of burst (sequential or inter-
leaved), A4–A6 specify the CAS latency, and A7–A11
(128MB) or A7–A12 (256MB, 512MB) specify the oper-
ating mode.
Burst Length
Read and write accesses to the DDR SDRAM are
burst oriented, with the burst length being program-
mable, as shown in Figure 4, Mode Register Definition
Diagram. The burst length determines the maximum
number of column locations that can be accessed for a
given READ or WRITE command. Burst lengths of 2, 4,
or 8 locations are available for both the sequential and
the interleaved burst types.
Reserved states should not be used, as unknown
operation or incompatibility with future versions may
result.
When a READ or WRITE command is issued, a block
of columns equal to the burst length is effectively
selected. All accesses for that burst take place within
this block, meaning that the burst will wrap within the
block if a boundary is reached. The block is uniquely
selected by A1–Ai when the burst length is set to two,
by A2–Ai when the burst length is set to four and by
A3–Ai when the burst length is set to eight (where Ai is
the most significant column address bit for a given
configuration. See Note 5 of Table 6, Burst Definition
Table, on page 9, for Ai values). The remaining (least
significant) address bit(s) is (are) used to select the
starting location within the block. The programmed
burst length applies to both READ and WRITE bursts.
Burst Type
Accesses within a given burst may be programmed
to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.
The ordering of accesses within a burst is deter-
mined by the burst length, the burst type and the start-
ing column address, as shown in Table 6, Burst
Definition Table, on page 9.
Figure 4: Mode Register Definition
Diagram
M3 = 0
Reserved
2
4
8
Reserved
Reserved
Reserved
Reserved
M3 = 1
Reserved
2
4
8
Reserved
Reserved
Reserved
Reserved
Operating Mode
Normal Operation
Normal Operation/Reset DLL
All other states reserved
0
1
-
0
0
-
0
0
-
0
0
-
0
0
-
0
0
-
Valid
Valid
-
0
1
Burst Type
Sequential
Interleaved
CAS Latency
Reserved
Reserved
2
Reserved
Reserved
Reserved
2.5
Reserved
Burst Length
M0
0
1
0
1
0
1
0
1
Burst LengthCAS Latency BT0*
A9 A7 A6 A5 A4 A3
A8 A2 A1 A0
Mode Register (Mx)
Address Bus
976543
8210
M1
0
0
1
1
0
0
1
1
M2
0
0
0
0
1
1
1
1
M3
M4
0
1
0
1
0
1
0
1
M5
0
0
1
1
0
0
1
1
M6
0
0
0
0
1
1
1
1
M6-M0
M8 M7
Operating Mode
A10
A12 A11
BA0
BA1
10
11
12
13
0*
14
* M14 and M13 (BA1 and BA0)
must be “0, 0” to select the
base mode register (vs. the
extended mode register).
M9M10M12 M11
Burst LengthCAS Latency BT0*0*
A9 A7 A6 A5 A4 A3
A8 A2 A1 A0
Mode Register (Mx)
Address Bus
976543
8210
Operating Mode
A10
A11
BA0
BA1
10
11
12
13
* M13 and M12 (BA1 and BA0)
must be “0, 0” to select the
base mode register (vs. the
extended mode register).
128MB Module
256MB, 512MB Modules
128MB, 256MB, 512MB (x72, ECC)
184-PIN REGISTERED DDR SDRAM DIMM
09005aef807d56a1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDF9C16_32_64x72G_D.fm - Rev. D 9/03 EN 9©2003 Micron Technology. Inc.
NOTE:
1. For a burst length of two, A1–Ai select the two-
data-element block; A0 selects the first access
within the block.
2. For a burst length of four, A2–Ai select the four-
data-element block; A0–A1 select the first access
within the block.
3. For a burst length of eight, A3–Ai select the eight-
data-element block; A0–A2 select the first access
within the block.
4. Whenever a boundary of the block is reached
within a given sequence above, the following
access wraps within the block.
5. Ai = A9 for 128MB, 256MB
Ai = A9, A11 for 512MB
Figure 5: CAS Latency Diagram
Read Latency
The READ latency is the delay, in clock cycles,
between the registration of a READ command and the
availability of the first bit of output data. The latency
can be set to 2 or 2.5 clocks, as shown in Figure 5, CAS
Latency Diagram.
If a READ command is registered at clock edge n,
and the latency is m clocks, the data will be available
nominally coincident with clock edge n + m. Table 7,
CAS Latency Table, indicates the operating frequencies
at which each CAS latency setting can be used.
Reserved states should not be used as unknown
operation or incompatibility with future versions may
result.
Operating Mode
The normal operating mode is selected by issuing a
MODE REGISTER SET command with bits A7–A11
(128MB), or A7–A12 (256MB, 512MB) each set to zero,
and bits A0–A6 set to the desired values. A DLL reset is
initiated by issuing a MODE REGISTER SET command
with bits A7 and A9–A11 (128MB) or A9–A12 (256MB,
512MB) each set to zero, bit A8 set to one, and bits A0-
A6 set to the desired values. Although not required by
the Micron device, JEDEC specifications recommend
when a LOAD MODE REGISTER command is issued to
Table 6: Burst Definition Table
BURST
LENGTH
STARTING
COLUMN
ADDRESS
ORDER OF ACCESSES WITHIN
A BURST
TYPE =
SEQUENTIAL
TYPE =
INTERLEAVED
2
A0
00-1 0-1
11-0 1-0
4
A1 A0
0 0 0-1-2-3 0-1-2-3
0 1 1-2-3-0 1-0-3-2
1 0 2-3-0-1 2-3-0-1
1 1 3-0-1-2 3-2-1-0
8
A2 A1 A0
0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7
0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6
0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5
0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4
1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3
1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2
1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1
1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
Table 7: CAS Latency Table
ALLOWABLE OPERATING
CLOCK FREQUENCY (MHZ)
SPEED CL = 2 CL = 2.5
-335 75 £ f £ 133 75 £ f £ 167
-262 75 £ f £ 133 75 £ f £ 133
-26A 75 £ f £ 133 75 £ f £ 133
-265 75 £ f £ 100 75 £ f £ 133
-202 75 £ f £ 100 75 £ f £ 125
CK
CK#
COMMAND
DQ
DQS
CL = 2
READ NOP NOP NOP
READ NOP NOP NOP
Burst Length = 4 in the cases shown
Shown with nominal tAC, tDQSCK, and tDQSQ
CK
CK#
COMMAND
DQ
DQS
CL = 2.5
T0 T1 T2 T2n T3 T3n
T0 T1 T2 T2n T3 T3n
DON’T CARETRANSITIONING DATA
128MB, 256MB, 512MB (x72, ECC)
184-PIN REGISTERED DDR SDRAM DIMM
09005aef807d56a1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDF9C16_32_64x72G_D.fm - Rev. D 9/03 EN 10 ©2003 Micron Technology. Inc.
reset the DLL, it should always be followed by a LOAD
MODE REGISTER command to select normal operat-
ing mode.
All other combinations of values for A7–A11
(128MB) or A7–A12 (256MB, 512MB) are reserved for
future use and/or test modes. Test modes and
reserved states should not be used because unknown
operation or incompatibility with future versions may
result.
Extended Mode Register
The extended mode register controls functions
beyond those controlled by the mode register; these
additional functions are DLL enable/disable and out-
put drive strength. These functions are controlled via
the bits shown in Figure 6, Extended Mode Register
Definition Diagram. The extended mode register is
programmed via the LOAD MODE REGISTER com-
mand to the mode register (with BA0 = 1 and BA1 = 0)
and will retain the stored information until it is pro-
grammed again or the device loses power. The
enabling of the DLL should always be followed by a
LOAD MODE REGISTER command to the mode regis-
ter (BA0/BA1 both LOW) to reset the DLL.
The extended mode register must be loaded when
all device banks are idle and no bursts are in progress,
and the controller must wait the specified time before
initiating any subsequent operation. Violating either
of these requirements could result in unspecified oper-
ation.
DLL Enable/Disable
The DLL must be enabled for normal operation.
DLL enable is required during power-up initialization
and upon returning to normal operation after having
disabled the DLL for the purpose of debug or evalua-
tion. When the device exits self refresh mode, the DLL
is enabled automatically. Any time the DLL is enabled,
200 clock cycles must occur before a READ command
can be issued.
Figure 6: Extended Mode Register
Definition Diagram
NOTE:
1. BA1 and BA0 (E13 and E12 for 128MB, E14 and E13
for 256MB and 512MB) must be “0, 1” to select the
Extended Mode Register (vs. the base Mode Regis-
ter).
2. The QFC# option is not supported.
Operating Mode
Reserved
Reserved
0
–
0
–
Valid
–
0
1
DLL
Enable
Disable
DLL
1
1
0
1
A9 A7 A6 A5 A4 A3
A8 A2 A1 A0
Extended Mode
Register (Ex)
Address Bus
976543
8210
E0
0
Drive Strength
Normal
E1
E2
2
E0
E1,
Operating Mode
A10
A11A12
BA1 BA0
10
11
12
1314
E3E4
0
–
0
–
0
–
0
–
0
–
E6 E5
E7E8E9
0
–
0
–
E10E11
0
–
E12
DS
DLL
11
01
A9 A7 A6 A5 A4 A3
A8 A2 A1 A0
Extended Mode
Register (Ex)
Address Bus
976543
8210
Operating Mode
A10
A11
BA1 BA0
10
11
12
13
DS
128MB Module
256MB, 512MB Modules
0
–
128MB, 256MB, 512MB (x72, ECC)
184-PIN REGISTERED DDR SDRAM DIMM
09005aef807d56a1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDF9C16_32_64x72G_D.fm - Rev. D 9/03 EN 11 ©2003 Micron Technology. Inc.
Commands
The Truth Tables below provides a general reference
of available commands. For a more detailed descrip-
tion of commands and operations, refer to the 128Mb,
256Mb, and 512Mb DDR SDRAM component data
sheets.
NOTE:
1. DESELECT and NOP are functionally interchangeable.
2. BA0–BA1 provide device bank address and A0–A11 (128MB) or A0–A12 (256MB, 512MB) provide row address.
3. BA0–BA1 provide device bank address; A0–A9 (128MB, 256MB) or A0–A9, A11 (512MB)provide column address; A10
HIGH enables the auto precharge feature (nonpersistent), and A10 LOW disables the auto precharge feature.
4. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for
READ bursts with auto precharge enabled and for WRITE bursts.
5. A10 LOW: BA0–BA1 determine which device bank is precharged. A10 HIGH: all device banks are precharged and
BA0–BA1 are “Don’t Care.”
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8. BA0–BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register;
BA0 = 1, BA1 = 0 select extended mode register; other combinations of BA0–BA1 are reserved). A0–A11 (128MB) or
A0–A12 (256MB, 512MB) provide the op-code to be written to the selected mode register.
Table 8: Truth Table – Commands
CKE is HIGH for all commands shown except SELF REFRESH
NAME (FUNCTION) CS# RAS# CAS# WE# ADDR NOTES
DESELECT (NOP) HX XX X 1
NO OPERATION (NOP) LH HH X 1
ACTIVE (Select bank and activate row) L L H H Bank/Row 2
READ (Select bank and column, and start READ burst) L H L H Bank/Col 3
WRITE (Select bank and column, and start WRITE burst) L H L L Bank/Col 3
BURST TERMINATE LH HL X 4
PRECHARGE (Deactivate row in bank or banks) L L H L Code 5
AUTO REFRESH or SELF REFRESH (Enter self refresh mode) LL LH X 6, 7
LOAD MODE REGISTER L L L L Op-Code 8
Table 9: Truth Table – DM Operation
Used to mask write data; provided coincident with the corresponding data
NAME (FUNCTION) DM DQS
WRITE Enable L Valid
WRITE Inhibit HX
128MB, 256MB, 512MB (x72, ECC)
184-PIN REGISTERED DDR SDRAM DIMM
09005aef807d56a1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDF9C16_32_64x72G_D.fm - Rev. D 9/03 EN 12 ©2003 Micron Technology. Inc.
ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only, and functional
operation of the device at these or any other condi-
tions above those indicated in the operational sections
of this specification is not implied. Exposure to abso-
lute maximum rating conditions for extended periods
may affect reliability.
Voltage on VDD Supply
Relative to VSS. . . . . . . . . . . . . . . . . . . . . -1V to +3.6V
Voltage on VDDQ Supply
Relative to VSS. . . . . . . . . . . . . . . . . . . . -1V to +3.6V
Voltage on VREF and Inputs
Relative to VSS. . . . . . . . . . . . . . . . . . . . -1V to +3.6V
Voltage on I/O Pins
Relative to VSS. . . . . . . . . . . . . -0.5V to VDDQ +0.5V
Operating Temperature
TA (ambient) . . . . . . . . . . . . . . . . . . . . .. 0°C to +70°C
Storage Temperature (plastic) . . . . . .-55°C to +150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 9W
Short Circuit Output Current. . . . . . . . . . . . . . . 50mA
Table 10: DC Electrical Characteristics and Operating Conditions
Notes: 1–5, 14; notes appear on pages 20–23; 0°C £ TA £ +70°C
PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES
Supply Voltage VDD 2.3 2.7 V 32, 36
I/O Supply Voltage VDDQ 2.3 2.7 V 32, 36, 39
I/O Reference Voltage VREF
0.49 x V
DD
Q0.51 x V
DD
Q
V6, 39
I/O Termination Voltage (system) VTT VREF - 0.04 VREF + 0.04 V 7, 39
Input High (Logic 1) Voltage VIH(DC) VREF + 0.15 VDD + 0.3 V 25
Input Low (Logic 0) Voltage VIL(DC) -0.3 VREF - 0.15 V 25
INPUT LEAKAGE CURRENT
Any input 0V £ VIN £ VDD, VREF pin 0V £ VIN £
1.35V (All other pins not under test = 0V)
Command/
Address, RAS#,
CAS#, WE#, S#,
CKE II
-5 5
µA 49
CK, CK# -10 10
DM -2 2
OUTPUT LEAKAGE CURRENT
(DQs are disabled; 0V £ VOUT £ VDDQ)
DQ, DQS IOZ -5 5 µA 49
OUTPUT LEVELS
High Current (V
OUT
= V
DD
Q - 0.373V, minimum V
REF
, minimum V
TT
)
Low Current (V
OUT
= 0.373V, maximum V
REF
, maximum V
TT
)
IOH -16.8 – mA 33, 34
IOL 16.8 – mA
Table 11: AC Input Operating Conditions
Notes: 1–5, 14; notes appear on pages 20–23; 0°C £ TA £ +70°C; VDD = VDDQ = +2.5V ±0.2V
PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES
Input High (Logic 1) Voltage VIH(AC)VREF + 0.310 – V 12, 25, 35
Input Low (Logic 0) Voltage VIL(AC)–VREF - 0.310 V 12, 25, 35
I/O Reference Voltage VREF(AC) 0.49 X VDDQ0.51 X VDDQV 6
128MB, 256MB, 512MB (x72, ECC)
184-PIN REGISTERED DDR SDRAM DIMM
09005aef807d56a1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDF9C16_32_64x72G_D.fm - Rev. D 9/03 EN 13 ©2003 Micron Technology. Inc.
Table 12 : IDD Specifications and Conditions – 128MB
DDR SDRAM components only
Notes: 1–5, 8, 10, 12, 43; notes appear on pages 20–23; 0°C £ TA £ +70°C; VDD = VDDQ = +2.5V ±0.2V
MAX
PARAMETER/CONDITION SYM -335 -262
-26A/
-265 -202 UNITS NOTES
OPERATING CURRENT: One device bank; Active-Precharge;
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN); DQ, DM and DQS inputs
changing once per clock cyle; Address and control inputs
changing once every two clock cycles
IDD01,125 990 945 945 mA 20, 44
OPERATING CURRENT: One device bank; Active -Read
Precharge; Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN);
IOUT = 0mA; Address and control inputs changing once
per clock cycle
IDD1 1,215 1,080 1,080 1,080 mA 20, 44
PRECHARGE POWER-DOWN STANDBY CURRENT: All
device banks idle; Power-down mode; tCK = tCK (MIN);
CKE = (LOW)
IDD2P 27 27 27 27 mA 21, 28,
46
IDLE STANDBY CURRENT: CS# = HIGH; All device banks
idle; tCK = tCK MIN; CKE = HIGH; Address and other
control inputs changing once per clock cycle. VIN = VREF
for DQ, DQS, and DM
IDD2F 405 405 360 360 mA 47
ACTIVE POWER-DOWN STANDBY CURRENT: One device
bank active; Power-down mode; tCK = tCK (MIN);
CKE = LOW
IDD3P 225 225 180 180 mA 21, 28,
46
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH;
One device bank; Active-Precharge; tRC = tRAS (MAX);
tCK = tCK (MIN); DQ, DM and DQS inputs changing twice
per clock cycle; Address and other control inputs
changing once per clock cycle
IDD3N 450 450 405 405 mA 42
OPERATING CURRENT: Burst = 2; Reads; Continuous
burst; One bank active; Address and control inputs
changing once per clock cycle; tCK = tCK (MIN);
IOUT = 0mA
IDD4R 1,260 1,170 1,125 1,125 mA 20, 44
OPERATING CURRENT: Burst = 2; Writes; Continuous
burst; One device bank active; Address and control
inputs changing once per clock cycle; tCK = tCK (MIN);
DQ, DM, and DQS inputs changing twice per clock cycle
IDD4W 1,260 1,125 1,080 1,080 mA 20
AUTO REFRESH CURRENT tRC = tRC (MIN) IDD5 2,385 1,980 1,980 1,980 mA 20, 46
tRC = 15.625µs IDD5A 45 45 45 45 mA 24, 46
SELF REFRESH CURRENT: CKE £ 0.2V IDD6 27 27 18 18 mA 9
OPERATING CURRENT: Four device bank interleaving
READs (BL = 4) with auto precharge, tRC = tRC (MIN);
tCK = tCK (MIN); Address and control inputs change only
during Active READ, or WRITE commands
IDD7 3,195 2,970 2,925 2,925 mA 20, 45
128MB, 256MB, 512MB (x72, ECC)
184-PIN REGISTERED DDR SDRAM DIMM
09005aef807d56a1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDF9C16_32_64x72G_D.fm - Rev. D 9/03 EN 14 ©2003 Micron Technology. Inc.
Table 13: IDD Specifications and Conditions – 256MB
DDR SDRAM components only
Notes: 1–5, 8, 10, 12, 43; notes appear on pages 20–23; 0°C £ TA £ +70°C; VDD = VDDQ = +2.5V ±0.2V
MAX
PARAMETER/CONDITION SYM -335 -262
-26A/
-265 -202 UNITS NOTES
OPERATING CURRENT:
One device bank; Active-Precharge;
tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM and DQS inputs
changing once per clock cyle; Address and control inputs
changing once every two clock cycles
IDD01,125 1,125 945 1,080 mA 20, 44
OPERATING CURRENT: One device bank; Active -Read
Precharge; Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN);
IOUT = 0mA; Address and control inputs changing once
per clock cycle
IDD1 1,530 1,440 1,305 1,395 mA 20, 44
PRECHARGE POWER-DOWN STANDBY CURRENT: All
device banks idle; Power-down mode; tCK = tCK (MIN);
CKE = (LOW)
IDD2P 36 36 36 36 mA 21, 28,
46
IDLE STANDBY CURRENT: CS# = HIGH; All device banks
idle; tCK = tCK MIN; CKE = HIGH; Address and other
control inputs changing once per clock cycle. VIN = VREF
for DQ, DQS, and DM
IDD2F 450 405 405 405 mA 47
ACTIVE POWER-DOWN STANDBY CURRENT: One device
bank active; Power-down mode; tCK = tCK (MIN);
CKE = LOW
IDD3P 270 225 225 270 mA 21, 28,
46
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH;
One device bank; Active-Precharge; tRC = tRAS (MAX);
tCK = tCK (MIN); DQ, DM andDQS inputs changing twice
per clock cycle; Address and other control inputs
changing once per clock cycle
IDD3N 540 450 450 450 mA 42
OPERATING CURRENT: Burst = 2; Reads; Continuous
burst; One bank active; Address and control inputs
changing once per clock cycle; tCK = tCK (MIN);
IOUT = 0mA
IDD4R 1,575 1,350 1,350 1,575 mA 20, 44
OPERATING CURRENT: Burst = 2; Writes; Continuous
burst; One device bank active; Address and control
inputs changing once per clock cycle; tCK = tCK (MIN);
DQ, DM, and DQS inputs changing twice per clock cycle
IDD4W 1,395 1,215 1,215 1,710 mA 20
AUTO REFRESH CURRENT tRC = tRC (MIN) IDD5 2,295 2,115 2,115 2,205 mA 20, 46
tRC = 7.8125µs IDD5A 54 54 54 54 mA 24, 46
SELF REFRESH CURRENT: CKE £ 0.2V IDD6 36 36 36 36 mA 9
OPERATING CURRENT: Four device bank interleaving
READs (BL = 4) with auto precharge, tRC = tRC (MIN);
tCK = tCK (MIN); Address and control inputs change only
during Active READ, or WRITE commands
IDD7 3,645 3,150 3,150 3,285 mA 20, 45
128MB, 256MB, 512MB (x72, ECC)
184-PIN REGISTERED DDR SDRAM DIMM
09005aef807d56a1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDF9C16_32_64x72G_D.fm - Rev. D 9/03 EN 15 ©2003 Micron Technology. Inc.
Table 14: IDD Specifications and Conditions – 512MB
DDR SDRAM components only
Notes: 1–5, 8, 10, 12, 43; notes appear on pages 20–23; 0°C £ TA £ +70°C; VDD = VDDQ = +2.5V ±0.2V
MAX
PARAMETER/CONDITION SYM -335 -262
-26A/
-265 -202 UNITS NOTES
OPERATING CURRENT:
One device bank; Active-Precharge;
tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM and DQS inputs
changing once per clock cyle; Address and control inputs
changing once every two clock cycles
IDD01,170 1,170 1,035 1,035 mA 20, 44
OPERATING CURRENT: One device bank; Active -Read
Precharge; Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN);
IOUT = 0mA; Address and control inputs changing once
per clock cycle
IDD1 1,440 1,440 1,305 1,305 mA 20, 44
PRECHARGE POWER-DOWN STANDBY CURRENT: All
device banks idle; Power-down mode; tCK = tCK (MIN);
CKE = (LOW)
IDD2P 45 45 45 45 mA 21, 28,
46
IDLE STANDBY CURRENT: CS# = HIGH; All device banks
idle; tCK = tCK MIN; CKE = HIGH; Address and other
control inputs changing once per clock cycle. VIN = VREF
for DQ, DQS, and DM
IDD2F 405 405 360 360 mA 47
ACTIVE POWER-DOWN STANDBY CURRENT: One device
bank active; Power-down mode; tCK = tCK (MIN);
CKE = LOW
IDD3P 315 315 270 270 mA 21, 28,
46
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH;
One device bank; Active-Precharge; tRC = tRAS (MAX);
tCK = tCK (MIN); DQ, DM andDQS inputs changing twice
per clock cycle; Address and other control inputs
changing once per clock cycle
IDD3N 405 405 360 360 mA 42
OPERATING CURRENT: Burst = 2; Reads; Continuous
burst; One bank active; Address and control inputs
changing once per clock cycle; tCK = tCK (MIN); IOUT =
0mA
IDD4R 1,485 1,485 1,305 1,305 mA 20, 44
OPERATING CURRENT: Burst = 2; Writes; Continuous
burst; One device bank active; Address and control
inputs changing once per clock cycle; tCK = tCK (MIN);
DQ, DM, and DQS inputs changing twice per clock cycle
IDD4W 1,395 1,395 1,215 1,215 mA 20
AUTO REFRESH CURRENT tRC = tRC (MIN) IDD5 2,610 2,610 2,520 2,520 mA 20, 46
tRC = 7.8125µs IDD5A 90 90 90 90 mA 24, 46
SELF REFRESH CURRENT: CKE £ 0.2V IDD6 45 45 45 45 mA 9
OPERATING CURRENT: Four device bank interleaving
READs (BL = 4) with auto precharge, tRC = tRC (MIN);
tCK = tCK (MIN); Address and control inputs change only
during Active READ, or WRITE commands
IDD7 3,645 3,600 3,150 3,150 mA 20, 45
128MB, 256MB, 512MB (x72, ECC)
184-PIN REGISTERED DDR SDRAM DIMM
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DDF9C16_32_64x72G_D.fm - Rev. D 9/03 EN 16 ©2003 Micron Technology. Inc.
Table 15: Capacitance
Note: 11; notes appear on pages 20–23
PARAMETER SYMBOL MIN MAX UNITS
Input/Output Capacitance: DQ, DQS, DM CI0 45 pF
Input Capacitance: Command and Address, S#, CKE CI1 2.5 3.5 pF
Input Capacitance: CK, CK# CI2 –4pF
Table 16: DDR SDRAM Component Electrical Characteristics and Recommended AC
Operating Conditions (-335, -262)
Notes: 1–5, 8, 10, 12; notes appear on pages 20–23; 0°C £ TA £ +70°C; VDD = VDDQ = +2.5V ±0.2V
AC CHARACTERISTICS -335 -262 UNITS NOTES
PARAMETER
SYMBOL
MIN MAX MIN MAX
Access window of DQs from CK/CK# tAC -0.7 +0.7 -0.75 +0.75 ns
CK high-level width tCH 0.45 0.55 0.45 0.55 tCK 26
CK low-level width tCL 0.45 0.55 0.45 0.55 tCK 26
Clock cycle time CL= 2.5
t
CK (2.5)
6 13 7.5 13 ns 40, 48
CL = 2 tCK (2) 7.5 13
7.5/10
13 ns 40, 48
DQ and DM input hold time relative to DQS tDH 0.45 0.5 ns 23, 27
DQ and DM input setup time relative to DQS tDS 0.45 0.5 ns 23, 27
DQ and DM input pulse width (for each input) tDIPW 1.75 1.75 ns 27
Access window of DQS from CK/CK# tDQSCK -0.60 +0.60 -0.75 +0.75 ns
DQS input high pulse width tDQSH 0.35 0.35 tCK
DQS input low pulse width tDQSL 0.35 0.35 tCK
DQS-DQ skew, DQS to last DQ valid, per group, per access tDQSQ 0.35 0.5 ns 22, 23
Write command to first DQS latching transition tDQSS 0.75 1.25 0.75 1.25 tCK
DQS falling edge to CK rising - setup time tDSS 0.2 0.2 tCK
DQS falling edge from CK rising - hold time tDSH 0.2 0.2 tCK
Half clock period tHP tCH, tCL tCH, tCL ns 30
Data-out high-impedance window from CK/CK# tHZ +0.70 +0.75 ns 16, 37
Data-out low-impedance window from CK/CK# tLZ -0.70 -0.75 ns 16, 38
Address and control input hold time (fast slew rate) tIHF0.75 0.90 ns 12
Address and control input setup time (fast slew rate) tISF0.75 0.90 ns 12
Address and control input hold time (slow slew rate) tIHS0.80 1 ns 12
Address and control input setup time (slow slew rate) tISS0.80 1 ns 12
LOAD MODE REGISTER command cycle time tMRD 12 15 ns
DQ-DQS hold, DQS to first DQ to go non-valid, per access tQH tHP - tQHS tHP - tQHS ns 22, 23
Data hold skew factor tQHS 0.50 0.50 ns
ACTIVE to PRECHARGE command tRAS 42 120,000 42
120,000
ns 31
ACTIVE to READ with Auto precharge
command
128MB tRAP 18 15 ns 41
256MB, 512MB tRAP 18 15 ns
ACTIVE to ACTIVE/AUTO REFRESH command period tRC 60 60 ns
AUTO REFRESH command period tRFC 72 75 ns 46
ACTIVE to READ or WRITE delay tRCD 18 15 ns
PRECHARGE command period tRP 18 15 ns
DQS read preamble tRPRE 0.9 1.1 0.9 1.1 tCK 37
128MB, 256MB, 512MB (x72, ECC)
184-PIN REGISTERED DDR SDRAM DIMM
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DQS read postamble tRPST 0.4 0.6 0.4 0.6 tCK
ACTIVE bank a to ACTIVE bank b command tRRD 12 12 ns
DQS write preamble tWPRE 0.25 0.25 tCK
DQS write preamble setup time tWPRES 0 0 ns 18, 19
DQS write postamble tWPST 0.4 0.6 0.4 0.6 tCK 17
Write recovery time tWR 15 15 ns
Internal WRITE to READ command delay tWTR 1 1 tCK
Data valid output window na tQH - tDQSQ tQH - tDQSQ ns 22
REFRESH to REFRESH command interval 128MB tREFC 140.6 140.6 µs 21
REFRESH to REFRESH command interval 256MB, 512MB 70.3 70.3 µs 21
Average periodic refresh interval 128MB tREFI 15.6 15.6 µs 21
Average periodic refresh interval 256MB, 512MB 7.8 7.8 µs 21
Terminating voltage delay to VDD tVTD 0 0 ns
Exit SELF REFRESH to non-READ command tXSNR 75 75 ns
Exit SELF REFRESH to READ command tXSRD 200 200 tCK
Table 16: DDR SDRAM Component Electrical Characteristics and Recommended AC
Operating Conditions (-335, -262) (Continued)
Notes: 1–5, 8, 10, 12; notes appear on pages 20–23; 0°C £ TA £ +70°C; VDD = VDDQ = +2.5V ±0.2V
AC CHARACTERISTICS -335 -262 UNITS NOTES
PARAMETER
SYMBOL
MIN MAX MIN MAX
128MB, 256MB, 512MB (x72, ECC)
184-PIN REGISTERED DDR SDRAM DIMM
09005aef807d56a1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDF9C16_32_64x72G_D.fm - Rev. D 9/03 EN 18 ©2003 Micron Technology. Inc.
Table 17: DDR SDRAM Component Electrical Characteristics and Recommended AC
Operating Conditions (-26A, -265, -202)
Notes: 1–5, 14; notes appear on pages 20–23; 0°C £ TA £ +70°C; VDD = VDDQ = +2.5V ±0.2V
AC CHARACTERISTICS -26A/-265 -202 UNITS NOTES
PARAMETER
SYMBOL
MIN MAX MIN MAX
Access window of DQs from CK/CK# tAC -0.75 +0.75 -0.8 +0.8 ns
CK high-level width tCH 0.45 0.55 0.45 0.55 tCK 26
CK low-level width tCL 0.45 0.55 0.45 0.55 tCK 26
Clock cycle time CL= 2.5
t
CK (2.5)
7.5 13 8 13 ns 40, 48
CL = 2 tCK (2)
7.5/10
13 10 13 ns 40, 48
DQ and DM input hold time relative to DQS tDH 0.5 0.6 ns 23, 27
DQ and DM input setup time relative to DQS tDS 0.5 0.6 ns 23, 27
DQ and DM input pulse width (for each input) tDIPW 1.75 2 ns 27
Access window of DQS from CK/CK# tDQSCK -0.75 +0.75 -0.8 +0.8 ns
DQS input high pulse width tDQSH 0.35 0.35 tCK
DQS input low pulse width tDQSL 0.35 0.35 tCK
DQS-DQ skew, DQS to last DQ valid, per group, per access tDQSQ 0.5 0.6 ns 22, 23
Write command to first DQS latching transition tDQSS 0.75 1.25 0.75 1.25 tCK
DQS falling edge to CK rising - setup time tDSS 0.2 0.2 tCK
DQS falling edge from CK rising - hold time tDSH 0.2 0.2 tCK
Half clock period tHP tCH, tCL tCH, tCL ns 30
Data-out high-impedance window from CK/CK# tHZ +0.75 +0.8 ns 16, 37
Data-out low-impedance window from CK/CK# tLZ -0.75 -0.8 ns 16, 38
Address and control input hold time (fast slew rate) tIHF0.90 1.1 ns 12
Address and control input setup time (fast slew rate) tISF0.90 1.1 ns 12
Address and control input hold time (slow slew rate) tIHS11.1 ns12
Address and control input setup time (slow slew rate) tISS11.1 ns12
LOAD MODE REGISTER command cycle time tMRD 15 16 ns
DQ-DQS hold, DQS to first DQ to go non-valid, per access tQH tHP - tQHS tHP - tQHS ns 22, 23
Data hold skew factor tQHS 0.75 1 ns
ACTIVE to PRECHARGE command tRAS
40 120,000 40 120,000
ns 31
ACTIVE to READ with Auto precharge
command
128MB tRAP
t
RAS(MIN ) - (Burst Length *
t
CK/2)
ns 41
256MB, 512MB 20 20 ns
ACTIVE to ACTIVE/AUTO REFRESH command period tRC 65 70 ns
AUTO REFRESH command period tRFC 75 80 ns 46
ACTIVE to READ or WRITE delay tRCD 20 20 ns
PRECHARGE command period tRP 20 20 ns
DQS read preamble tRPRE 0.9 1.1 0.9 1.1 tCK 37
DQS read postamble tRPST 0.4 0.6 0.4 0.6 tCK
ACTIVE bank a to ACTIVE bank b command tRRD 15 15 ns
DQS write preamble tWPRE 0.25 0.25 tCK
DQS write preamble setup time tWPRES 0 0 ns 18, 19
DQS write postamble tWPST 0.4 0.6 0.4 0.6 tCK 17
Write recovery time tWR 15 15 ns
Internal WRITE to READ command delay tWTR 1 1 tCK
Data valid output window na tQH - tDQSQ tQH - tDQSQ ns 22
128MB, 256MB, 512MB (x72, ECC)
184-PIN REGISTERED DDR SDRAM DIMM
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DDF9C16_32_64x72G_D.fm - Rev. D 9/03 EN 19 ©2003 Micron Technology. Inc.
REFRESH to REFRESH command interval 128MB tREFC 140.6 140.6 µs 21
REFRESH to REFRESH command interval 256MB, 512MB 70.3 70.3 µs 21
Average periodic refresh interval 128MB tREFI 15.6 15.6 µs 21
Average periodic refresh interval 256MB, 512MB 7.8 7.8 µs 21
Terminating voltage delay to VDD tVTD 0 0 ns
Exit SELF REFRESH to non-READ command tXSNR 75 80 ns
Exit SELF REFRESH to READ command tXSRD 200 200 tCK
Table 17: DDR SDRAM Component Electrical Characteristics and Recommended AC
Operating Conditions (-26A, -265, -202) (Continued)
Notes: 1–5, 14; notes appear on pages 20–23; 0°C £ TA £ +70°C; VDD = VDDQ = +2.5V ±0.2V
AC CHARACTERISTICS -26A/-265 -202 UNITS NOTES
PARAMETER
SYMBOL
MIN MAX MIN MAX
128MB, 256MB, 512MB (x72, ECC)
184-PIN REGISTERED DDR SDRAM DIMM
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DDF9C16_32_64x72G_D.fm - Rev. D 9/03 EN 20 ©2003 Micron Technology. Inc.
Notes
1. All voltages referenced to VSS.
2. Tests for AC timing, IDD, and electrical AC and DC
characteristics may be conducted at nominal ref-
erence/supply voltage levels, but the related spec-
ifications and device operation are guaranteed for
the full voltage range specified.
3. Outputs measured with equivalent load:
4. AC timing and IDD tests may use a VIL-to-VIH
swing of up to 1.5V in the test environment, but
input timing is still referenced to VREF (or to the
crossing point for CK/CK#), and parameter speci-
fications are guaranteed for the specified AC input
levels under normal use conditions. The mini-
mum slew rate for the input signals used to test
the device is 1V/ns in the range between VIL(AC)
and VIH(AC).
5. The AC and DC input level specifications are as
defined in the SSTL_2 Standard (i.e., the receiver
will effectively switch as a result of the signal
crossing the AC input level, and will remain in that
state as long as the signal does not ring back
above [below] the DC input LOW [HIGH] level).
6. VREF is expected to equal VDDQ/2 of the transmit-
ting device and to track variations in the DC level
of the same. Peak-to-peak noise (non-common
mode) on VREF may not exceed ±2 percent of the
DC value. Thus, from VDDQ/2, VREF is allowed
±25mV for DC error and an additional ±25mV for
AC noise. This measurement is to be taken at the
nearest VREF by-pass capacitor.
7. VTT is not applied directly to the device. VTT is a
system supply for signal termination resistors, is
expected to be set equal to VREF and must track
variations in the DC level of VREF.
8. IDD is dependent on output loading and cycle
rates. Specified values are obtained with mini-
mum cycle time at CL = 2 for -262, -26A, and -202,
CL = 2.5 for -335 and -265 with the outputs open.
9. Enables on-chip refresh and address counters.
10. IDD specifications are tested after the device is
properly initialized, and is averaged at the defined
cycle rate.
11. This parameter is sampled. VDD = +2.5V ±0.2V,
VDDQ = +2.5V ±0.2V, VREF = VSS, f = 100 MHz, TA =
25°C, VOUT(DC) = VDDQ/2, VOUT (peak to peak) =
0.2V. DM input is grouped with I/O pins, reflecting
the fact that they are matched in loading.
12. Command/Address input slew rate = 0.5V/ns. For
-335, -262, -26A, and -265, with slew rates 1V/ns
and faster, tIS and tIH are reduced to 900ps. If the
slew rate is less than 0.5V/ ns, timing must be der-
ated: tIS has an additional 50ps per each 100mV/
ns reduction in slew rate from the 500mV/ns,
while tIH remains constant. If the slew rate
exceeds 4.5V/ns, functionality is uncertain.
13. The CK/CK# input reference level (for timing ref-
erenced to CK/CK#) is the point at which CK and
CK# cross; the input reference level for signals
other than CK/CK# is VREF.
14. Inputs are not recognized as valid until VREF stabi-
lizes. Exception: during the period before V
REF
stabilizes, CKE £ 0.3 x VDDQ is recognized as LOW.
15. The output timing reference level, as measured at the
timing reference point indicated in Note 3, is V
TT
.
16. tHZ and tLZ transitions occur in the same access
time windows as valid data transitions. These
parameters are not referenced to a specific voltage
level, but specify when the device output is no
longer driving (HZ) or begins driving (LZ).
17. If DQS transitions to HIGH above VIH (DC) MIN,
then it must not transition to LOW below VIH (DC)
MIN prior to tDQSH (MIN).
18. This is not a device limit. The device will operate
with a negative value, but system performance
could be degraded due to bus turnaround.
19. It is recommended that DQS be valid (HIGH or
LOW) on or before the WRITE command. The
case shown (DQS going from High-Z to logic
LOW) applies when no WRITEs were previously in
progress on the bus. If a previous WRITE was in
progress, DQS could be HIGH during this time,
depending on tDQSS.
20. MIN (tRC or tRFC) for IDD measurements is the
smallest multiple of tCK that meets the minimum
absolute value for the respective parameter. tRAS
(MAX) for IDD measurements is the largest multi-
ple of tCK that meets the maximum absolute
value for tRAS.
21.
The refresh period is 64ms. This equates to an
average refresh rate of 15.625µs (128MB) or
7.8125µs (256MB, 512MB). However, an AUTO
REFRESH command must be asserted at least once
every 140.6µs (128MB) or 70.3µs (256MB, 512MB);
burst refreshing or posting by the DRAM controller
greater than eight refresh cycles is not allowed.
Output
(V
OUT
)
Reference
Point
50
Ω
V
TT
30pF
128MB, 256MB, 512MB (x72, ECC)
184-PIN REGISTERED DDR SDRAM DIMM
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DDF9C16_32_64x72G_D.fm - Rev. D 9/03 EN 21 ©2003 Micron Technology. Inc.
22. The valid data window is derived by achieving
other specifications: tHP (tCK/2), tDQSQ, and tQH
(tQH = tHP - tQHS). The data valid window derates
directly porportional with the clock duty cycle
and a practical data valid window can be derived.
The clock is allowed a maximum duty cycle varia-
tion of 45/55. Functionality is uncertain when
operating beyond a 45/55 ratio. Figure 7, Derating
Data Valid Window, shows derating curves for
duty cycles between 50/50 and 45/55.
23. Each byte lane as a corresponding DQS.
24. This limit is actually a nominal value and does not
result in a fail value. CKE is HIGH during REFRESH
command period (
t
RFC [MIN]) else CKE is LOW (i.e.,
during standby).
25. To maintain a valid level, the transitioning edge of
the input must:
a. Sustain a constant slew rate from the current
AC level through to the target AC level, VIL (AC)
or VIH (AC).
b. Reach at least the target AC level.
c. After the AC target level is reached, continue to
maintain at least the target DC level, VIL (DC)
or VIH (DC).
26. JEDEC specifies CK and CK# input slew rate must
be ³ 1V/ns (2V/ns differentially).
27.
DQ and DM input slew rates must not deviate
from DQS by more than 10 percent. If the DQ/
DM/DQS slew rate is less than 0.5V/ns, timing
must be derated: 50ps must be added to
t
DS and
t
DH for each 100mv/ns reduction in slew rate. If
slew rate exceeds 4V/ns, functionality is uncertain.
28. VDD must not vary more than 4 percent if CKE is
not active while any bank is active.
29. The clock is allowed up to ±150ps of jitter. Each
timing parameter is allowed to vary by the same
amount.
30. tHP min is the lesser of tCL minimum and tCH
minimum actually applied to the device CK and
CK# inputs, collectively during bank active.
Figure 7: Derating Data Valid Window
(tQH – tDQSQ)
3.750 3.700 3.650 3.600 3.550
3.500 3.450
3.400 3.350 3.300 3.250
3.400 3.350 3.300
3.250
3.200 3.150 3.100 3.050
3.000 2.950 2.900
2.500 2.463 2.425 2.388 2.350 2.313 2.275 2.238 2.200 2.163 2.125
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
50/50 49.5/50.5 49/51 48.5/52.5 48/52 47.5/53.5 47/53 46.5/54.5 46/54 45.5/55.5 45/55
Clock Duty Cycle
ns
-335
-262/-26A/-265 @ tCK = 10ns
-202 @ tCK = 10ns
-262/-26A/-265 @ tCK = 7.5ns
-202 @ tCK = 8ns
NA
128MB, 256MB, 512MB (x72, ECC)
184-PIN REGISTERED DDR SDRAM DIMM
09005aef807d56a1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDF9C16_32_64x72G_D.fm - Rev. D 9/03 EN 22 ©2003 Micron Technology. Inc.
31. READs and WRITEs with auto precharge are not
allowed to be issued until tRAS(MIN) can be satis-
fied prior to the internal precharge command
being issued.
32. Any positive glitch in the nominal voltage must be
less than 1/3 of the clock and not more than
+400mV (2.9V max), whichever is less. Any nega-
tive glitch must be less than 1/3 of the clock cycle
and not exceed -300mV (2.2V min), whichever is
more positive. However, the DC average cannot be
below 2.3V minimum.
33. Normal Output Drive Curves:
a. The full variation in driver pull-down current
from minimum to maximum process, tempera-
ture and voltage will lie within the outer bound-
ing lines of the V-I curve of Figure 8, Pull-Down
Characteristics.
b. The variation in driver pull-down current
within nominal limits of voltage and tempera-
ture is expected, but not guaranteed, to lie
within the inner bounding lines of the V-I
curve of Figure 8, Pull-Down Characteristics.
c. The full variation in driver pull-up current from
minimum to maximum process, temperature
and voltage will lie within the outer bounding
lines of the V-I curve of Figure 9, Pull-Up Charac-
teristics.
d. The variation in driver pull-up current within
nominal limits of voltage and temperature is
expected, but not guaranteed, to lie within the
inner bounding lines of the V-I curve of Figure
9, Pull-Up Characteristics.
e. The full variation in the ratio of the maximum
to minimum pull-up and pull-down current
should be between 0.71 and 1.4, for device
drain-to-source voltages from 0.1V to 1.0V, and
at the same voltage and temperature.
f. The full variation in the ratio of the nominal
pull-up to pull-down current should be unity
±10 percent, for device drain-to-source volt-
ages from 0.1V to 1.0V.
34. The voltage levels used are derived from a mini-
mum VDD level and the referenced test load. In
practice, the voltage levels obtained from a prop-
erly terminated bus will provide significantly dif-
ferent voltage values.
35.
V
IH
overshoot: V
IH
(MAX) = V
DDQ
+ 1.5V for a pulse
width
£
3ns and the pulse width can not be greater
than 1/3 of the cycle rate. V
IL
undershoot: V
IL
(MIN)
= -1.5V for a pulse width
£
3ns and the pulse width
can not be greater than 1/3 of the cycle rate.
36. VDD and VDDQ must track each other.
37. This maximum value is derived from the refer-
enced test load. In practice, the values obtained
in a typical terminated design may reflect up to
310ps less for tHZ (MAX) and the last DVW. tHZ
(MAX) will prevail over tDQSCK (MAX) + tRPST
(MAX) condition. tLZ (MIN) will prevail over
tDQSCK (MIN) + tRPRE (MAX) condition.
38. For slew rates greater than 1V/ns the (LZ) transi-
tion will start about 310ps earlier.
39. During initialization, VDDQ, VTT, and VREF must be
equal to or less than VDD + 0.3V. Alternatively, VTT
may be 1.35V maximum during power up, even if
VDD/VDDQ are 0V, provided a minimum of 42W of
series resistance is used between the VTT supply
and the input pin.
40. The current Micron part operates below the slow-
est JEDEC operating frequency of 83 MHz. As
such, future die may not reflect this option.
41. tRAP ³ tRCD. Does not apply to -335 speed grade.
Figure 8: Pull-Down Characteristics Figure 9: Pull-Up Characteristics
160
140
IOUT (mA)
VOUT (V)
Nominal low
Minimum
Nominal high
Maximum
120
100
80
60
40
20
0
0.0 0.5 1.0 1.5 2.0 2.5
VOUT (V)
0
-20
IOUT (mA)
Nominal low
Minimum
Nominal high
Maximum
-40
-60
-80
-100
-120
-140
-160
-180
-200
0.0 0.5 1.0 1.5 2.0 2.5
VDDQ - VOUT (V)
128MB, 256MB, 512MB (x72, ECC)
184-PIN REGISTERED DDR SDRAM DIMM
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DDF9C16_32_64x72G_D.fm - Rev. D 9/03 EN 23 ©2003 Micron Technology. Inc.
42. For -335, -262, -26A and -265, IDD3N is specified to
be 35mA at 100 MHz.
43. When an input signal is HIGH or LOW, it is
defined as a steady state logic HIGH or LOW.
44. Random addressing changing and 50 percent of
data changing at every transfer.
45. Random addressing changing and 100 percent of
data changing at every transfer.
46. CKE must be active (high) during the entire time a
refresh command is executed. That is, from the
time the AUTO REFRESH command is registered,
CKE must be active at each rising clock edge, until
tREF later.
47. IDD2N specifies the DQ, DQS, and DM to be
driven to a valid high or low logic level. IDD2Q is
similar to IDD2F except IDD2Q specifies the
address and control inputs to remain stable.
Although IDD2F, IDD2N, and IDD2Q are similar,
IDD2F is “worst case.”
48. Whenever the operating frequency is altered, not
including jitter, the DLL is required to be reset.
This is followed by 200 clock cycles (before READ
commands).
49. Leakage number reflects the worst case leakage
possible through the module pin, not what each
memory device contributes.
128MB, 256MB, 512MB (x72, ECC)
184-PIN REGISTERED DDR SDRAM DIMM
09005aef807d56a1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDF9C16_32_64x72G_D.fm - Rev. D 9/03 EN 24 ©2003 Micron Technology. Inc.
NOTE:
1. Timing and switching specifications for the register listed above are critical for proper operation of the DDR SDRAM
Registered DIMMs. These are meant to be a subset of the parameters for the specific device used on the module.
Detailed information for this register is available in JEDEC Standard JESD82.
2. Data inputs must be low a minimum time of tact max, after RESET# is taken HIGH.
3. Data and clock inputs must be held at valid levels (not floating) a minimum time of tinact max, after RESET# is taken
LOW.
4. For data signal input slew rate ³ 1 V/ns.
5. For data signal input slew rate ³ 0.5 V/ns and < 1V/ns.
6. CK, CK# signals input slew rate ³ 1V/ns.
Table 18: Register Timing Requirements and Switching Characteristics
Note: 1
REGISTER SYMBOL PARAMERTER CONDITION
0ºC £ TA £ 70ºC
VDD = 2.5V ± 0.2V
UNITS NOTESMIN MAX
SSTL
(bit pattern
by JESD82-3
or JESD82-4)
fclock Clock Frequency - 200 MHz
tpd Clock to Output Time 30pF to GND and
50 Ohms to Vtt
1.1 2.8 ns
tPHL Reset To Output Time - 5 ns
twPulse Duration CK, CK# HIGH or
LOW
2.5 - ns
tact Differential Inputs Active
Time
-22ns 2
tinact Differential Inputs Inactive
Time
-22ns 3
tsu Setup Time, Fast Slew Rate Data Before CK
HIGH, CK# LOW
0.75 - ns 4, 6
Setup Time, Slow Slew Rate 0.9 - ns 5, 6
thHold Time, Fast Slew Rate Data After CK
HIGH, CK# LOW
0.75 - ns 4, 6
Hold Time, Slow Slew Rate 0.9 - ns 5, 6
128MB, 256MB, 512MB (x72, ECC)
184-PIN REGISTERED DDR SDRAM DIMM
09005aef807d56a1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDF9C16_32_64x72G_D.fm - Rev. D 9/03 EN 25 ©2003 Micron Technology. Inc.
NOTE:
1. Timing and switching specifications for the PLL listed above are critical for proper operation of the DDR SDRAM Reg-
istered DIMMs. These are meant to be a subset of the parameters for the specific device used on the module.
Detailed information for this PLL is available in JEDEC Standard JESD82.
2. The PLL must be able to handle spread spectrum induced skew.
3. Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not required
to meet the other timing parameters. (Used for low-speed system debug.)
4. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its
reference signal after power up.
5. Static Phase Offset does not include Jitter.
6. Period Jitter and Half-Period Jitter specifications are separate specifications that must be met independently of each
other.
7. The Output Slew Rate is determined from the IBIS model:
Table 19: PLL Clock Driver Timing Requirements and Switching Characteristics
Note: 1
PARAMETER SYMBOL
TA = 0–70ºC
VDD = 2.5V ± 0.2V
UNITS NOTESMIN NOMINAL MAX
Operating Clock Frequency fCK 60 - 170 MHz 2, 3
Inupt Duty Cycle tDC 40 - 60 %
Stabilization Time tSTAB -- 100ms4
Cycle to Cycle Jitter tJITCC -75 - 75 ps
Static Phase Offeset tÆ-50 0 50 ps 5
Output Clock Skew tSKO-- 100ps
Period Jitter tJITPER -75 - 75 ps 6
Half-Period Jitter tJITHPER -100 - 100 ps 6
Input Clock Slew Rate tLSI1.0 - 4 V/ns
Output Clock Slew Rate tLSO1.0 - 2 V/ns 7
V
DD
/2
GND
V
DD
CDCV857
R=60
Ω
ΩΩ
Ω
R=60
Ω
ΩΩ
Ω
V
CK
V
CK
128MB, 256MB, 512MB (x72, ECC)
184-PIN REGISTERED DDR SDRAM DIMM
09005aef807d56a1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDF9C16_32_64x72G_D.fm - Rev. D 9/03 EN 26 ©2003 Micron Technology. Inc.
SPD Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions (Fig-
ure 10, Data Validity, and Figure 11, Definition of Start
and Stop).
SPD Start Condition
All commands are preceded by the start condition,
which is a HIGH-to-LOW transition of SDA when SCL
is HIGH. The SPD device continuously monitors the
SDA and SCL lines for the start condition and will not
respond to any command until this condition has been
met.
SPD Stop Condition
All communications are terminated by a stop condi-
tion, which is a LOW-to-HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
the SPD device into standby power mode.
SPD Acknowledge
Acknowledge is a software convention used to indi-
cate successful data transfers. The transmitting device,
either master or slave, will release the bus after trans-
mitting eight bits. During the ninth clock cycle, the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data (Figure 12,
Acknowledge Response From Receiver).
The SPD device will always respond with an
acknowledge after recognition of a start condition and
its slave address. If both the device and a WRITE oper-
ation have been selected, the SPD device will respond
with an acknowledge after the receipt of each subse-
quent eight-bit word. In the read mode the SPD device
will transmit eight bits of data, release the SDA line and
monitor the line for an acknowledge. If an acknowl-
edge is detected and no stop condition is generated by
the master, the slave will continue to transmit data. If
an acknowledge is not detected, the slave will termi-
nate further data transmissions and await the stop
condition to return to standby power mode.
Figure 10: Data Validity Figure 11: Definition of Start and Stop
Figure 12: Acknowledge Response From Receiver
SCL
SDA
DATA STABLE DATA STABLEDATA
CHANGE
SCL
SDA
START
BIT
STOP
BIT
SCL from Master
Data Output
from Transmitter
Data Output
from Receiver
98
Acknowledge
128MB, 256MB, 512MB (x72, ECC)
184-PIN REGISTERED DDR SDRAM DIMM
09005aef807d56a1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDF9C16_32_64x72G_D.fm - Rev. D 9/03 EN 27 ©2003 Micron Technology. Inc.
Figure 13: SPD EEPROM Timing Diagram
Table 20: EEPROM Device Select Code
The most significant bit (b7) is sent first
SELECT CODE DEVICE TYPE IDENTIFIER CHIP ENABLE RW
b7 b6 b5 b4 b3 b2 b1 b0
Memory Area Select Code (two arrays) 1 0 1 0 SA2 SA1 SA0 RW
Protection Register Select Code 0 1 1 0 SA2 SA1 SA0 RW
Table 21: EEPROM Operating Modes
MODE RW BIT WC BYTES INITIAL SEQUENCE
Current Address Read 1V
IH or VIL 1START, Device Select, RW = ‘1’
Random Address Read 0VIH or VIL 1START, Device Select, RW = ‘0’, Address
1VIH or VIL 1reSTART, Device Select, RW = ‘1’
Sequential Read 1VIH or VIL ³ 1Similar to Current or Random Address Read
Byte Write 0V
IL 1START, Device Select, RW = ‘0’
Page Write 0VIL £ 16 START, Device Select, RW = ‘0’
SCL
SDA IN
SDA OUT
tLOW
tSU:STA tHD:STA
tFtHIGH tR
tBUF
tDH
tAA
tSU:STO
tSU:DAT
tHD:DAT
UNDEFINED
128MB, 256MB, 512MB (x72, ECC)
184-PIN REGISTERED DDR SDRAM DIMM
09005aef807d56a1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDF9C16_32_64x72G_D.fm - Rev. D 9/03 EN 28 ©2003 Micron Technology. Inc.
NOTE:
1. To aviod spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising
edge of SDA.
2. This parameter is sampled.
3. For a reSTART condition, or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write sequence to the end of
the EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA
remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address.
Table 22: Serial Presence-Detect EEPROM DC Operating Conditions
All voltages referenced to VDDSPD; VDDSPD = +2.3V to +3.6V
PARAMETER/CONDITION SYMBOL MIN MAX UNITS
Supply Voltage VDDSPD 2.3 3.6 V
Input High Voltage: Logic 1; All inputs VIH VDDSPD X 0.7 VDDSPD + 0.5 V
Input Low Voltage: Logic 0; All inputs VIL -0.6 VDDSPD x 0.3 V
Output Low Voltage: IOUT = 3mA VOL –0.4V
Input Leakage Current: VIN = GND to VDD ILI 0.10 3 µA
Output Leakage Current: VOUT = GND to VDD ILO 0.05 3 µA
Standby Current: ISB 1.6 4 µA
Power Supply Current, READ: SCL clock frequency = 100 KHz ICCR0.4 1 mA
Powr Supply Current, WRITE: SCL clock frequency = 100 KHz ICCW23mA
Table 23: Serial Presence-Detect EEPROM AC Operating Conditions
All voltages referenced to VDDSPD; VDDSPD = +2.3V to +3.6V
PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES
SCL LOW to SDA data-out valid tAA 0.2 0.9 µs 1
Time the bus must be free before a new transition can start tBUF 1.3 µs
Data-out hold time tDH 200 ns
SDA and SCL fall time tF300ns2
Data-in hold time tHD:DAT 0 µs
Start condition hold time tHD:STA 0.6 µs
Clock HIGH period tHIGH 0.6 µs
Noise suppression time constant at SCL, SDA inputs tI50ns
Clock LOW period tLOW 1.3 µs
SDA and SCL rise time tR0.3µs2
SCL clock frequency fSCL 400 KHz
Data-in setup time tSU:DAT 100 ns
Start condition setup time tSU:STA 0.6 µs 3
Stop condition setup time tSU:STO 0.6 µs
WRITE cycle time tWRC 10 ms 4
128MB, 256MB, 512MB (x72, ECC)
184-PIN REGISTERED DDR SDRAM DIMM
09005aef807d56a1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDF9C16_32_64x72G_D.fm - Rev. D 9/03 EN 29 ©2003 Micron Technology. Inc.
Table 24: Serial Presence-Detect Matrix
“1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”
BYTE DESCRIPTION ENTRY (VERSION) MT9VDDF1672 MT9VDDF3272 MT9VDDF6472
0Number of SPD Bytes Used by Micron 128 80 80 80
1Total Number of Bytes in SPD Device 256 08 08 08
2Fundamental Memory Type SDRAM DDR 07 07 07
3Number of Row Addresses on
Assembly
12 or 13 0C 0D 0D
4Number of Column Addresses on
Assembly
10, 11 0A 0A 0B
5Number of Physical Banks on DIMM 1010101
6Module Data Width 72 48 48 48
7Module Data Width (Continued) 0000000
8Module Voltage Interface Levels SSTL 2.5V 04 04 04
9SDRAM Cycle Time, (tCK) (CAS
Latency = 2.5) (See note 1)
6ns(-335)
7ns (-262/-26A)
7.5ns (-265)
8ns (-202)
60
70
75
80
60
70
75
80
60
70
75
80
10 SDRAM Access From Clock,(tAC)
(CAS Latency = 2.5)
0.7(-335)
0.75ns (-262/-26A/-265)
0.8ns (-202)
70
75
80
70
75
80
70
75
80
11 Module Configuration Type ECC 02 02 02
12 Refresh Rate/Type 15.62 or 7.81µs/SELF 80 82 82
13 SDRAM Device Width (Primary
SDRAM)
8080808
14 Error-checking SDRAM Data Width 8080808
15 Minimum Clock Delay, Back-to-Back
Random Column Access
1 clock 01 01 01
16 Burst Lengths Supported 2, 4, 8 0E 0E 0E
17 Number of Banks on SDRAM Device 4040404
18 CAS Latencies Supported 2, 2.5 0C 0C 0C
19 CS Latency 0010101
20 WE Latency 1020202
21 SDRAM Module Attributes Registered, PLL/Diff.
Clock
26 26 26
22 SDRAM Device Attributes: General Fast/Concurrent AP C0 C0 C0
23 SDRAM Cycle Time, (tCK), CAS
Latency = 2
7.5ns (-335/-262/-26A)
10ns (-265/-202)
75
A0
75
A0
75
A0
24 SDRAM Access from CK , (tAC), CAS
Latency = 2
0.70ns (-335)
0.75ns (-262/-26A/-265)
0.8ns (-202)
70
75
80
70
75
80
70
75
80
25 SDRAM Cycle Time, (tCK), CAS
Latency = 1.5
N/A 00 00 00
26 SDRAM Access from CK , (tAC), CAS
Latency = 1.5
N/A 00 00 00
27 Minimum Row Precharge Time, (tRP) 18ns (-335)
15ns (-262)
20ns (-202/-265/-26A)
48
3C
50
48
3C
50
48
3C
50
28 Minimum Row Active to Row Active,
(tRRD)
12ns (
-335
)
15ns (-262/-26A/-265/-202)
30
3C
30
3C
30
3C
128MB, 256MB, 512MB (x72, ECC)
184-PIN REGISTERED DDR SDRAM DIMM
09005aef807d56a1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDF9C16_32_64x72G_D.fm - Rev. D 9/03 EN 30 ©2003 Micron Technology. Inc.
29 Minimum RAS# to CAS# Delay, (tRCD) 18ns (-335)
15ns (-262)
20ns (-202/-265/-26A)
48
3C
50
48
3C
50
48
3C
50
30 Minimum RAS# Pulse Width, (tRAS)
(See note 2)
42ns (-335)
45ns (-262/-26A/-265)
40ns (-202)
2A
2D
28
2A
2D
28
2A
2D
28
31 Module Rank Density 128MB or 256MB 20 40 40
32 Address and Command Setup Time,
(tIS) (See note 3)
0.80ns (-335)
1ns (-262/-26A/-265)
1.1ns (-202)
80
A0
B0
80
A0
B0
80
A0
B0
33 Address and Command Hold Time,
(tIH) (See note 3)
0.80ns (-335)
1ns (-262/-26A/-265)
1.1ns (-202)
80
A0
B0
80
A0
B0
80
A0
B0
34 Data/ Data Mask Input Setup Time,
(tDS)
0.45ns (-335)
0.50ns (-262/-26A/-265)
0.60ns (-202)
45
50
60
45
50
60
45
50
60
35 Data/ Data Mask Input Hold Time,
(tDH)
0.45ns (-335)
0.50ns (-262/-26A/-265)
0.60ns (-202)
45
50
60
45
50
60
45
50
60
36-40 Reserved 00 00 00
41 Min Active Auto Refresh Time (tRC) 60ns (-335/-262)
65ns (-26A/-265)
70ns (-202)
3C
41
46
3C
41
46
3C
41
46
42 Minimum Auto Refresh to Active/
Auto Refresh Command Period,
(tRFC)
72ns (-335)
75ns (-262/-26A/-265)
80ns (-202)
48
4B
50
48
4B
50
48
4B
50
43 SDRAM Device Max Cycle Time
(tCKMAX)
12ns (
-335)
13ns (-262/-26A/-265/-202)
30
34
30
34
30
34
44 SDRAM Device Max DQS-DQ Skew
Time (tDQSQ)
0.4ns (-335)
0.5ns (-262/-26A/-265)
0.6ns (-202)
28
32
3C
28
32
3C
28
32
3C
45 SDRAM Device Max Read Data Hold
Skew Factor (tQHS)
0.5ns (-335)
0.75ns (-262/-26A/-265)
1.0ns (-202)
50
75
A0
50
75
A0
50
75
A0
46 Reserved 00 00 00
47 DIMM Height 01 01 01
48–61 Reserved 00 00 00
62 SPD Revision Release 1.0 10 10 10
63 Checksum For Bytes 0-62 -335
-262
-26A
-265
-202
12
EF
1C
4C
E7
35
D2
FF
2F
CA
76
13
40
70
0B
64 Manufacturer’s JEDEC ID Code MICRON 2C 2C 2C
65-71 Manufacturer’s JEDEC ID Code (Continued) FF FF FF
72 Manufacturing Location 01–12 01–0C 01–0C 01–0C
73-90 Module Part Number (ASCII) Variable Data Variable Data Variable Data
91 PCB Identification Code 1-9 01-09 01-09 01-09
92 Identification Code (Continued) 0000000
Table 24: Serial Presence-Detect Matrix
“1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”
BYTE DESCRIPTION ENTRY (VERSION) MT9VDDF1672 MT9VDDF3272 MT9VDDF6472
128MB, 256MB, 512MB (x72, ECC)
184-PIN REGISTERED DDR SDRAM DIMM
09005aef807d56a1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDF9C16_32_64x72G_D.fm - Rev. D 9/03 EN 31 ©2003 Micron Technology. Inc.
NOTE:
1. Value for -26A tCK set to 7ns (0x70) for optimum BIOS compatibility. Actual device spec. vaule is 7.5ns.
2. The value of tRAS used for -26A/-265 modules is calculated from tRC - tRP. Actual device spec value is 40 ns.
3. The JEDEC SPD specification allows fast or slow slew rate values for these bytes. The worst-case (slow slew rate) value
is repesented here. Systems requiring the fast slew rate setup and hold values are supported, provided the faster
minimum slew rate is met.
93 Year of Manufacture in BCD Variable Data Variable Data Variable Data
94 Week of Manufacture in BCD Variable Data Variable Data Variable Data
95-98 Module Serial Number Variable Data Variable Data Variable Data
99-127 Manufacturer-specific Data (RSVD) –––
Table 24: Serial Presence-Detect Matrix
“1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”
BYTE DESCRIPTION ENTRY (VERSION) MT9VDDF1672 MT9VDDF3272 MT9VDDF6472
®
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992
Micron, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc.
128MB, 256MB, 512MB (x72, ECC)
184-PIN REGISTERED DDR SDRAM DIMM
09005aef807d56a1 Micron Technology, Inc., reserves the right to change products or specifications without notice..
DDF9C16_32_64x72G_D.fm - Rev. D 9/03 EN 32 ©2003 Micron Technology, Inc
Figure 14: 184-PIN DIMM DDR Modules
NOTE:
All dimensions in inches (millimeters) or typical where noted.
Data Sheet Designation
Released (No Mark): This data sheet contains mini-
mum and maximum limits specified over the complete
power supply and temperature range for production
devices. Although considered final, these specifica-
tions are subject to change, as further product devel-
opment and data characterization sometimes occur.
U1
U2 U3 U4 U5
U12
U11 U13
U6 U7 U8 U9
U10
No Components This Side of Module
1.131 (28.73)
1.119 (28.42)
PIN 1
0.700 (17.78)
TYP.
0.098 (2.50) D
(2X)
0.091 (2.30) TYP.
0.250 (6.35) TYP.
4.750 (120.65)
0.050 (1.27)
TYP.
0.091 (2.30)
TYP.
0.040 (1.02)
TYP.
0.079 (2.00) R
(4X)
0.035 (0.90) R
PIN 92
FRONT VIEW
0.054 (1.37)
0.046 (1.17)
5.256 (133.50)
5.244 (133.20)
2.55 (64.77) 1.95 (49.53)
0.394 (10.00)
TYP.
0.125 (3.175)
MAX
PIN 184 PIN 93
BACK VIEW
MAX
MIN
