16-Bit Latche
s
CY74FCT16373
T
CY74FCT162373
T
S
CCS054C - August 1994 - Revised October 2003
Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
Copyright © 2003, Texas Instruments Incorporated
Features
•I
off supports partial-power-down mode operation
• Edge-rate control circuitry for significantly improved
noise characteristics
• Typical output skew < 250 ps
• ESD > 2000V
• TSSOP (19.6-mil pitch) and SSOP (25-mil pitch)
packages
• Industrial temperature range of −40˚C to +85˚C
•V
CC = 5V ± 10%
CY74FCT16373T Features:
• 64 mA sink current, 32 mA source current
• Typical VOLP (ground bounce) <1.0V at VCC = 5V,
TA = 25˚C
CY74FCT162373T Features:
• Balanced 24 mA output drivers
• Reduced system switching noise
• Typical VOLP (ground bounce) <0.6V at VCC = 5V,
TA= 25˚C
Functional Description
CY74FCT16373T and CY74FCT162373T are 16-bit D-type
latches designed for use in bus applications requiring high
speed and low power. These devices can be used as two
independent 8-bit latches or as a single 16-bit latch by
connecting the Output Enable (OE) and Latch (LE) inputs.
Flow-through pinout and small shrink packaging aid in
simplifying board layout.
This device is fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device
when it is powered down.
The CY74FCT16373T is ideally suited for driving
high-capacitance loads and low-impedance backplanes.
The CY74FCT162373T has 24-mA balanced output drivers
with current limiting resistors in the outputs. This reduces the
need for external terminating resistors and provides for
minimal undershoot and reduced ground bounce. The
CY74FCT162373T is ideal for driving transmission lines.
Logic Block Diagrams Pin Configuration
D
C
1OE
FCT162373-1
1LE
1D11O1
TO 7 OTHERCHANNELS
D
C
2OE
FCT162373-2
2LE
2D12O1
GND
1
2
3
4
5
6
7
8
9
10
11
12
33
32
31
30
29
25
26
27
28
36
35
1OE
34
SSOP/TSSOP/TVSOP
Top View
13
14
15
16
17
18
19
20
21
22
23
24
45
44
43
42
41
37
38
39
40
48
47
46
1O1
1O2
1O3
1O4
1D1
1D2
1D3
1D4
1LE
GND
GND
VCC
1O7
1O8
1O5
1O6
1D5
1D6
1D7
1D8
VCC
GND
GND
2O3
2O4
2O1
2O2
2D1
2D2
2D3
2D4
GND
GND
VCC
2O7
2O8
2O5
2O6
2D5
2D6
2D7
2D8
VCC
GND
2OE 2LE
FCT162373-3
TO 7 OTHERCHANNELS
CY74FCT16373
T
CY74FCT162373
T
2
Maximum Ratings[2, 3]
(Above which the useful life may be impaired. For user
guidelines, not tested.)
Storage Temperature...................... Com’l −55°C to +125°C
Ambient Temperature with
Power Applied.................................Com’l −55°C to +125°C
DC Input Voltage .................................................−0.5V to +7.0V
DC Output Voltage ..............................................−0.5V to +7.0V
DC Output Current
(Maximum Sink Current/Pin)...........................−60 to +120 mA
Power Dissipation..........................................................1.0W
Static Discharge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
Pin Description
Name Description
D Data Inputs
LE Latch Enable Inputs (Active HIGH)
OE Output Enable Inputs (Active LOW)
O Three-State Outputs
Function Table[1]
Inputs Outputs
D LE OE O
H H L H
L H L L
X L L Q0
X X H Z
Operating Range
Range Ambient
Temperature VCC
Industrial −40°C to +85°C 5V ± 10%
Electrical Characteristics Over the Operating Range
Parameter Description Test Conditions Min. Typ.[4] Max. Unit
VIH Input HIGH Voltage 2.0 V
VIL Input LOW Voltage 0.8 V
VHInput Hysteresis[5] 100 mV
VIK Input Clamp Diode Voltage VCC=Min., IIN=−18 mA −0.7 −1.2 V
IIH Input HIGH Current VCC=Max., VI=VCC ±1µA
IIL Input LOW Current VCC=Max., VI=GND ±1µA
IOZH High Impedance Output Current
(Three-State Output pins) VCC=Max., VOUT=2.7V ±1µA
IOZL High Impedance Output Current
(Three-State Output pins) VCC=Max., VOUT=0.5V ±1µA
IOS Short Circuit Current[6] VCC=Max., VOUT=GND −80 −140 −200 mA
IOOutput Drive Current[6] VCC=Max., VOUT=2.5V −50 −180 mA
IOFF Power-Off Disable VCC=0V, VOUT≤4.5V[7] ±1µA
Output Drive Characteristics for CY74FCT16373T
Parameter Description Test Conditions Min. Typ.[4] Max. Unit
VOH Output HIGH Voltage VCC=Min., IOH=−3 mA 2.5 3.5 V
VCC=Min., IOH=−15 mA 2.4 3.5 V
VCC=Min., IOH=−32 mA 2.0 3.0 V
VOL Output LOW Voltage VCC=Min., IOL=64 mA 0.2 0.55 V
Notes:
1. H = HIGH Voltage Level. L = LOW Voltage Level. X = Don’t Care. Z = High Impedance. Q0=Previous state of flip-flop.
2. Operation beyond the limits set forth may impair the useful life of the device. Unless otherwise noted, these limits are over the operating free-air temperature
range.
3. Unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground.
4. Typical values are at VCC=5.0V, TA= +25˚C ambient.
5. This parameter is specified but not tested.
6. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample
and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of
a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter
tests, IOS tests should be performed last.
7. Tested at +25˚C.
CY74FCT16373
T
CY74FCT162373
T
3
Output Drive Characteristics for CY74FCT162373T
Parameter Description Test Conditions Min. Typ.[4] Max. Unit
IODL Output LOW Current[6] VCC=5V, VIN=VIH or VIL, VOUT=1.5V 60 115 150 mA
IODH Output HIGH Current[6] VCC=5V, VIN=VIH or VIL, VOUT=1.5V −60 −115 −150 mA
VOH Output HIGH Voltage VCC=Min., IOH=−24 mA 2.4 3.3 V
VOL Output LOW Voltage VCC=Min., IOL=24 mA 0.3 0.55 V
Capacitance[5] (TA = +25˚C, f = 1.0 MHz)
Parameter Description Test Conditions Typ.[4] Max. Unit
CIN Input Capacitance VIN = 0V 4.5 6.0 pF
COUT Output Capacitance VOUT = 0V 5.5 8.0 pF
Power Supply Characteristics
Parameter Description Test Conditions Typ.[4] Max. Unit
ICC QuiescentPowerSupply Current VCC=Max. VIN≤0.2V,
VIN≥VCC−0.2V 5 500 µA
∆ICC QuiescentPowerSupplyCurrent
(TTL inputs HIGH) VCC=Max. VIN=3.4V[8] 0.5 1.5 mA
ICCD Dynamic Power Supply
Current[9] VCC=Max., One Input
Toggling, 50% Duty Cycle,
Outputs Open, OE=GND
VIN=VCC or
VIN=GND 60 100 µA/MHz
ICTotal Power Supply Current[10] VCC=Max., f1=10 MHz,
50% Duty Cycle, Outputs
Open, One Bit Toggling,
OE=GND, LE=VCC
VIN=VCC or
VIN=GND 0.6 1.5 mA
VIN=3.4V or
VIN=GND 0.9 2.3 mA
VCC=Max., f1=2.5 MHz,
50% Duty Cycle, Outputs
Open,SixteenBitsToggling,
OE=GND, LE=VCC
VIN=VCC or
VIN=GND 2.4 4.5[11] mA
VIN=3.4V or
VIN=GND 6.4 16.5[11] mA
Notes:
8. Per TTL driven input (VIN=3.4V); all other inputs at VCC or GND.
9. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
10. IC=I
QUIESCENT + IINPUTS + IDYNAMIC
IC=I
CC+∆ICCDHNT+ICCD(f0/2 + f1N1)
ICC = Quiescent Current with CMOS input levels
∆ICC = Power Supply Current for a TTL HIGH input(VIN=3.4V)
DH= Duty Cycle for TTL inputs HIGH
NT= Number of TTL inputs at DH
ICCD = Dynamic Current caused by an input transition pair (HLH or LHL)
f0= Clock frequency for registered devices, otherwise zero
f1= Input signal frequency
N1= Number of inputs changing at f1
All currents are in milliamps and all frequencies are in megahertz.
11. Values for these conditions are examples of the ICC formula. These limits are specified but not tested.
CY74FCT16373
T
CY74FCT162373
T
4
Switching Characteristics Over the Operating Range[12]
CY74FCT16373AT
CY74FCT162373AT
Parameter Description Min. Max. Unit Fig. No.[13]
tPLH
tPHL Propagation Delay D to O 1.5 5.2 ns 1, 3
tPLH
tPHL Propagation Delay
LE to O 2.0 6.7 ns 1, 5
tPZH
tPZL Output Enable Time 1.5 6.1 ns 1, 7, 8
tPHZ
tPLZ Output Disable Time 1.5 5.5 ns 1, 7, 8
tSU Set-Up Time HIGH or LOW, D to LE 2.0 ns 9
tHHold Time HIGH or LOW, D to LE 1.5 ns 9
tWLE Pulse Width HIGH 3.3 ns 5
tSK(O) Output Skew[14] 0.5 ns —
CY74FCT16373CT
CY74FCT162373CT
Parameter Description Min. Max. Unit Fig. No.[13]
tPLH
tPHL Propagation Delay
D to O 1.5 4.2 ns 1, 3
tPLH
tPHL Propagation Delay
LE to O 2.0 5.5 ns 1, 5
tPZH
tPZL Output Enable Time 1.5 5.5 ns 1, 7, 8
tPHZ
tPLZ Output Disable Time 1.5 5.0 ns 1, 7, 8
tSU Set-Up Time HIGH or LOW, D to LE 2.0 ns 9
tHHold Time HIGH or LOW,
D to LE 1.5 ns 9
tWLE Pulse Width HIGH 3.3 ns 5
tSK(O) Output Skew[14] 0.5 ns —
Notes:
12. Minimum limits are specified but not tested on Propagation Delays.
13. See “Parameter Measurement Information” in the General Information section.
14. Skew between any two outputs of the same package switching in the same direction. This parameter is ensured by design.
CY74FCT16373
T
CY74FCT162373
T
5
Ordering Information CY74FCT16373
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
4.2 CY74FCT16373CTPACT Z48 48-Lead (240-Mil) TSSOP Industrial
CY74FCT16373CTPVC/PVCT O48 48-Lead (300-Mil) SSOP
CY74FCT16373CTVR - 48-Lead (173-Mil) TVSOP
5.2 CY74FCT16373ATPACT Z48 48-Lead (240-Mil) TSSOP Industrial
CY74FCT16373ATPVC/PVCT O48 48-Lead (300-Mil) SSOP
CY74FCT16373ATVR - 48-Lead (173-Mil) TVSOP
Ordering Information CY74FCT162373
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
4.2 74FCT162373CTPACT Z48 48-Lead (240-Mil) TSSOP Industrial
CY74FCT162373CTPVC O48 48-Lead (300-Mil) SSOP
74FCT162373CTPVCT O48 48-Lead (300-Mil) SSOP
5.2 74FCT162373ATPACT Z48 48-Lead (240-Mil) TSSOP Industrial
CY74FCT162373ATPVC O48 48-Lead (300-Mil) SSOP
74FCT162373ATPVCT O48 48-Lead (300-Mil) SSOP
CY74FCT16373
T
CY74FCT162373
T
6
Package Diagrams
48-Lead Shrunk Small Outline Package O48
48-Lead Thin Shrunk Small Outline Package Z48
MECHANICAL DATA
MPDS006C – FEBRUAR Y 1996 – REVISED AUGUST 2000
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE
24 PINS SHOWN
14
3,70
3,50 4,90
5,10
20
DIM
PINS **
4073251/E 08/00
1,20 MAX
Seating Plane
0,05
0,15
0,25
0,50
0,75
0,23
0,13
112
24 13
4,30
4,50
0,16 NOM
Gage Plane
A
7,90
7,70
382416
4,90
5,103,70
3,50
A MAX
A MIN
6,60
6,20
11,20
11,40
56
9,60
9,80
48
0,08
M
0,07
0,40
0°–8°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
4040048/E 12/01
48 PINS SHOWN
56
0.730
(18,54)
0.720
(18,29)
4828
0.370
(9,40)
(9,65)
0.380
Gage Plane
DIM
0.420 (10,67)
0.395 (10,03)
A MIN
A MAX
0.010 (0,25)
PINS **
0.630
(16,00)
(15,75)
0.620
0.010 (0,25)
Seating Plane
0.020 (0,51)
0.040 (1,02)
25
24
0.008 (0,203)
0.0135 (0,343)
48
1
0.008 (0,20) MIN
A
0.110 (2,79) MAX
0.299 (7,59)
0.291 (7,39)
0.004 (0,10)
M
0.005 (0,13)
0.025 (0,635)
0°–ā8°
0.005 (0,13)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUAR Y 1998
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
4040078/F 12/97
48 PINS SHOWN
0,25
0,15 NOM
Gage Plane
6,00
6,20 8,30
7,90
0,75
0,50
Seating Plane
25
0,27
0,17
24
A
48
1
1,20 MAX
M
0,08
0,10
0,50
0°–8°
56
14,10
13,90
48
DIM
A MAX
A MIN
PINS **
12,40
12,60
64
17,10
16,90
0,15
0,05
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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