VIN VOUT
GND
OFF
OUT
IN GATE
LM5050-2
Shutdown
GND GND
nFGD
Low= FET On, High= FET Off
+6V to +75V
Status
VLOGIC
Low= OK, High= Fault
RPULL-UP
LM5050-2
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SNVS679B –NOVEMBER 2010–REVISED MARCH 2013
LM5050-2 High Side OR-ing FET Controller
Check for Samples: LM5050-2
1FEATURES DESCRIPTION
The LM5050-2 High Side OR-ing FET Controller
2• Wide Operating Input Voltage Range: +6V to operates in conjunction with an external MOSFET as
+75V an ideal diode rectifier when connected in series with
• +100 Volt Transient Capability a power source. This OR-ing controller allows
• Charge Pump Gate Driver for External N- MOSFETs to replace diode rectifiers in power
distribution networks thus reducing both power loss
Channel MOSFET and voltage drops.
• MOSFET Diagnostic Test Mode The LM5050-2 controller provides charge pump gate
• Fast 50ns Response to Current Reversal drive for an external N-Channel MOSFET and a fast
• 2A Peak Gate Turn-off Current response comparator to turn off the FET when
• Minimum VDS Clamp for Faster Turn-off current flows in the reverse direction. The LM5050-2
can connect power supplies ranging from +6V to
• Package: SOT-6 (Thin SOT23-6) +75V and can withstand transients up to +100V.
APPLICATIONS The LM5050-2 also provides a FET test diagnostic
mode which allows the system controller to test for
• Active OR-ing of Redundant (N+1) Power shorted MOSFETs.
Supplies
Typical Application Circuits
Figure 1. Full Application with MOSFET Diagnostic
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2010–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
OFF
GATE
OUT
IN
1
2
3
6
5
4
nFGD
GND
LM5050MK-2
PS1
PS2
IN GATE OUT
IN GATE OUT
RLOAD
CLOAD
LM5050-2
LM5050-2
GND
GND
LM5050-2
SNVS679B –NOVEMBER 2010–REVISED MARCH 2013
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Figure 2. Typical Redundant Supply Configuration
Connection Diagram
Figure 3. LM5050MK-2
SOT-6 Package (Top View)
PIN DESCRIPTIONS
Pin # Name Function
Open drain output for the FET Test circuit. Status pin used in
conjunction with the OFF test mode pin. When the OFF pin is in the
logic high state, an active low state on nFGD indicates that the forward
1 nFGD voltage (from source to drain) of the external MOSFET is greater than
350 mV. The nFGD pin requires an external pull-up resistor to a voltage
not higher than 5.5V.
2 GND Ground return for the controller
FET Test Mode control input. Logic low or open state at the OFF pin
will deactivate the FET Test Mode. A logic high state at the OFF pin will
pull the GATE pin low and turn off the external MOSFET. If the body
3 OFF diode forward voltage of the MOSFET (from source to drain) is greater
than 350mV when the OFF pin is in the high state, the nFGD pin will
indicate that the MOSFET is not shorted by pulling to the active low
state.
Voltage sense connection to the external MOSFET Source pin and
4 IN supply input to the internal charge pump.
5 GATE Connection to the external MOSFET Gate.
Voltage sense connection to the external MOSFET Drain pin and
6 OUT supply pin for biasing the internal control circuitry.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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SNVS679B –NOVEMBER 2010–REVISED MARCH 2013
Absolute Maximum Ratings (1)(2)
IN, OUT Pins to Ground (3) -0.3V to 100V
GATE Pin to Ground (3) -0.3V to 100V
OFF Pin to Ground -0.3V to 7V
nFGD Pin to Ground (Off) -0.3V to 7V
Storage Temperature Range −65°C to 150°C
ESDHBM (4) 2 kV
MM (5) 150V
Peak Reflow Temperature (6) 260°C, 30sec
(1) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including in-operability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. Operating Range conditions indicate
the conditions at which the device is functional and the device should not be operated beyond such conditions. For specifications and
conditions, see Electrical Characteristics.
(3) The GATE pin voltage is typically 12V above the IN pin voltage when the LM5050-2 is enabled (i.e. OFF Pin is Open or Low, and VIN >
VOUT). Therefore, the Absolute Maximum Rating for the IN pin voltage applies only when the LM5050-2 is disabled (i.e. OFF Pin is logic
high), or for a momentary surge to that voltage since the Absolute Maximum Rating for the GATE pin is also 100V
(4) The Human Body Model (HBM) is a 100 pF capacitor discharged through a 1.5 kΩresistor into each pin. Applicable test standard is
JESD-22-A114-C.
(5) The Machine Model (MM) is a 200 pF capacitor discharged through a 0Ωresistor (i.e. directly) into each pin. Applicable test standard is
JESD-A115-A.
(6) For soldering specifications visit www.ti.com.
Operating Ratings (1)
IN, OUT Pins +6.0V to +75V
OFF Pin Voltage 0.0V to 5.5V
nFGD Voltage (Off) 0.0V to 5.5V
nFGD Sink Current (On) 0 mA to 1 mA
Junction Temperature Range (TJ)−40°C to +125°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including in-operability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. Operating Range conditions indicate
the conditions at which the device is functional and the device should not be operated beyond such conditions. For specifications and
conditions, see Electrical Characteristics.
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Electrical Characteristics
Limits in standard type are for TJ= 25°C only; limits in boldface type apply over the operating junction temperature (TJ)
range of -40°C to +125°C. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical
values represent the most likely parametric norm at TJ= 25°C, and are provided for reference purposes only. Unless
otherwise stated the following conditions apply: VIN = 12.0V, VOUT = 12.0V, VOFF= 0.0V, CGATE= 47 nF, and TJ= 25°C.
Symbol Parameter Conditions Min Typ Max Unit
IN Pin
VIN Operating Supply Range 6.0 -75.0 V
VIN = 6.0V
GATE = Open 180 240 300
VOUT = VIN - 100 mV
VIN = 12.0V
IIN IN Pin current GATE = Open 262 350 440 μA
VOUT = VIN - 100 mV
VIN = 75.0V
GATE = Open 275 355 460
VOUT = VIN - 100 mV
OUT Pin
VIN = 6.0V 74 95 115
VOUT = VIN - 100 mV
VIN = 12.0V
IOUT OUT Pin Current 70 110 160 uA
VOUT = VIN - 100 mV
VIN = 75.0V 35 125 265
VOUT = VIN - 100 mV
GATE Pin
VIN = 6.0V to 75V
IGATE(ON) GATE Pin Source Current VGATE = VIN 18.0 32. 45.0 uA
VOUT = VIN - 175 mV
VIN = 6.0V 6.0 6.8 7.4
VOUT = VIN - 175 mV
VIN = 12.0V
VGS VGATE - VIN in Forward Operation (1) 8.0 11.5 14.7 V
VOUT = VIN - 175 mV
VIN = 75.0V 8.0 11 14.5
VOUT = VIN - 175 mV
CGATE = 0 (2) - 27 100
Gate Capacitance Discharge Time at
tGATE(REV) Forward to Reverse Transition CGATE = 10 nF (2) - 61 - ns
See Figure 4 CGATE = 47 nF (2) - 205 425
Gate Capacitance DischargeTime at
tGATE(OFF) OFF pin Low to High Transition CGATE = 47 nF (3) - 450 - ns
See Figure 5 VGATE = VIN + 3V
IGATE(OFF) GATE Pin Sink Current VOUT > VIN + 100 mV 1.9 2.8 - A
t≤10ms
Reverse VSD Threshold
VSD(REV) VIN - VOUT -37 -27 -17 mV
VIN < VOUT
ΔVSD(REV) Reverse VSD Hysteresis - 10 - mV
VIN = 6.0V 620 33
VIN - VOUT
Regulated Forward VSD Threshold
VSD(REG) mV
VIN > VOUT VIN = 12.0V 216 31
VIN - VOUT
(1) Measurement of VGS voltage (i.e. VGATE - VIN) includes 1 MΩin parallel with CGATE
(2) Time from VIN-VOUT voltage transition from 200mV to -500mV until GATE pin voltage falls to VIN + 1V. See Figure 4
(3) Time from VOFF voltage transition from 0.0V to 5.0V until GATE pin voltage falls to VIN + 1V. See Figure 5
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VIN - VOUT
VGATE - VIN
0.0V
1.0V
0 mV
VSD(REV)
-500 mV
VSD(REG)
200 mV
VGATE
VIN > VOUT
VIN < VOUT
tGATE(OFF)
LM5050-2
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SNVS679B –NOVEMBER 2010–REVISED MARCH 2013
Electrical Characteristics (continued)
Limits in standard type are for TJ= 25°C only; limits in boldface type apply over the operating junction temperature (TJ)
range of -40°C to +125°C. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical
values represent the most likely parametric norm at TJ= 25°C, and are provided for reference purposes only. Unless
otherwise stated the following conditions apply: VIN = 12.0V, VOUT = 12.0V, VOFF= 0.0V, CGATE= 47 nF, and TJ= 25°C.
Symbol Parameter Conditions Min Typ Max Unit
OFF Pin
VOUT = VIN-500 mV
VOFF(IH) OFF Input High Threshold Voltage - 1.55 1.73
VOFF Rising V
VOUT = VIN - 500 mV
VOFF(IL) OFF Input Low Threshold Voltage 1.09 1.41 -
VOFF Falling
ΔVOFF OFF Threshold Voltage Hysteresis VOFF(IH) - VOFF(IL) - 160 - mV
IOFF OFF Pin Internal Pull-down VOFF = 5.0V 2.0 58.0 µA
nFGD Pin
VOFF = 5V
FET Test Threshold Voltage
VSD(TST) VOUT = 12V 250 350 450 mV
VIN < VOUT VIN falling from 12V
ΔVSD(TST) FET Test Threshold Voltage Hysteresis - 95 - mV
nFGD Output Low Voltage VOFF = 5V
nFGDVOL - 630 850 mV
nFGD Output = On InFGD = 1 mA Sinking
nFGD Output Leakage Current VOFF = 0V
nFGDIOL - 0.001 0.7 µA
nFGD Output = Off VnFGD = 5.5V
Figure 4. Gate Off Timing for Forward to Reverse Transition
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Typical Performance Characteristics
Unless otherwise stated VIN = 12V, VOFF = 0.0V, and TJ= 25°C
IIN IOUT
vs vs
VIN VOUT
Figure 6. Figure 7.
VGATE VGS
vs vs
VIN VIN
Figure 8. Figure 9.
VGS
vs
Temperature Forward Gate Charge Time, CGATE = 10 nF
Figure 10. Figure 11.
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Typical Performance Characteristics (continued)
Unless otherwise stated VIN = 12V, VOFF = 0.0V, and TJ= 25°C
Forward Gate Charge Time, CGATE = 47 nF Reverse CGATE Discharge
Figure 12. Figure .
tGATE(REV) OFF Pin Thresholds
vs vs
Temperature Temperature
Figure 13. Figure 14.
OFF Pin Pull-Down CGATE Charge and Discharge
vs vs
VOUT OFF Pin
Figure 15. Figure 16.
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Typical Performance Characteristics (continued)
Unless otherwise stated VIN = 12V, VOFF = 0.0V, and TJ= 25°C
OFF Pin, On to Off Transition OFF Pin, Off to On Transition
Figure 17. Figure .
GATE Pin
vs
(RDS(ON) x IDS)
Figure 18.
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IN OUTGATE
1.5V
OFF
nFGD
GND
LM5050- 2
Reverse
Comparator
LOAD
INPUT
35 µA
17V
350 mV
Forward
Comparator
30 mV
30 µA
30 mV
5 µA
- +
-+
-+
Bias
Circuitry
-+
2A
MOSFET Off
+12V Charge
Pump
LM5050-2
SNVS679B –NOVEMBER 2010–REVISED MARCH 2013
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BLOCK DIAGRAM
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PS1
PS2
IN GATE OUT
IN GATE OUT
RLOAD
CLOAD
LM5050-2
LM5050-2
GND
GND
PS1
PS2
RLOAD
CLOAD
LM5050-2
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SNVS679B –NOVEMBER 2010–REVISED MARCH 2013
APPLICATIONS INFORMATION
FUNCTIONAL DESCRIPTION
Systems that require high availability often use multiple, parallel-connected redundant power supplies to improve
reliability. Schottky OR-ing diodes are typically used to connect these redundant power supplies to a common
point at the load. The disadvantage of using OR-ing diodes is the forward voltage drop, which reduces the
available voltage, and the associated power losses as load currents increase. Using an N-channel MOSFET to
replace the OR-ing diode requires a small increase in the level of complexity, but reduces, or eliminates, the
need for diode heat sinks or large thermal copper area in circuit board layouts for high power applications.
Figure 19. Traditional OR-ing with Diodes
The LM5050-2 is a positive voltage (i.e. high-side) OR-ing controller that will drive an external N-channel
MOSFET to replace an OR-ing diode. The voltage across the MOSFET source and drain pins is monitored by
the LM5050-2 at the IN and OUT pins, while the GATE pin drives the MOSFET to control its operation based on
the monitored source-drain voltage. The resulting behavior is that of an ideal rectifier with source and drain pins
of the MOSFET acting as the anode and cathode pins of a diode respectively.
Figure 20. OR-ing with MOSFETs
IN, GATE AND OUT PINS
When power is initially applied, the load current will flow from source to drain through the body diode of the
MOSFET. The resulting voltage across the body diode will be detected at the LM5050-2 IN and OUT pins which
then begins charging the MOSFET gate through a 30 µA (typical) charge pump current source . In normal
operation, the gate of the MOSFET is charged until it reaches typically 12V above the IN pin. With an IN pin
voltage that is less than approximately 10V, the gate of the MOSFET is charged to typically twice the voltage on
the IN pin.
The LM5050-2 is designed to regulate the MOSFET gate-to-source voltage if the voltage across the MOSFET
source and drain pins falls below the VSD(REG) voltage of 27 mV (typical).
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PS1
PS2
IN GATE OUT
IN GATE OUT
RLOAD
CLOAD
LM5050-2
LM5050-2
GND
GND
COUT
LM5050-2
SNVS679B –NOVEMBER 2010–REVISED MARCH 2013
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If the MOSFET current decreases to the point that the voltage across the MOSFET falls below the VSD(REG)
voltage regulation point of 27 mV (typical), the GATE pin voltage will be decreased until the voltage across the
MOSFET is regulated at 27 mV. If the drain-to-source voltage is greater than VSD(REG) voltage the gate-to-source
will increase, eventually reaching the 12V GATE to IN zener clamp level.
If the MOSFET current reverses, possibly due to failure of the input supply, such that the voltage across the
LM5050-2 IN and OUT pins is more negative than the VSD(REV) voltage of -27 mV (typical), the LM5050-2 will
quickly discharge the MOSFET gate through a strong GATE to IN pin discharge transistor.
If the input supply fails abruptly, as would occur if the supply was shorted directly to ground, a reverse current
will temporarily flow through the MOSFET until the gate can be fully discharged. This reverse current is sourced
from the output load capacitance and from the parallel connected supplies. The LM5050-2 responds to a voltage
reversal condition typically within 27 ns. The actual time required to turn off the MOSFET will depend on the
charge held by gate capacitance of the MOSFET being used. A MOSFET with 47 nF of effective gate
capacitance can be turned off in typically 205 ns. This fast turn off time minimizes voltage disturbances at the
output, as well as the current transients from the redundant supplies.
OFF PIN and nFGD PIN
The OFF pin is a logic level input pin that is used to control the gate drive to the external MOSFET in the FET
Test Mode. The maximum operating voltage on this pin is 5.5V. The nFGD pin is an open drain output pin that
supports a logic level voltage. The maximum operating voltage on this pin is 5.5V.
When the OFF pin is high, the MOSFET is turned off (independent of the sensed IN and OUT voltages) and the
FET Test Mode is activated. In this mode, load current will flow through the body diode of the MOSFET. The
voltage difference between the IN pin and OUT pins will be approximately 700 mV if the MOSFET is operating
normally through the body diode. The FET test comparator of the LM5050-2 monitors the IN to OUT pin voltage
difference with a VSD(TST) threshold of 350 mV (typical). If the IN pin to OUT pin voltage difference is greater than
this threshold, the nFGD pin will switch to a low impedance state and the nFGD pin voltage will be at a logic low.
If the MOSFET is shorted, the voltage difference between the IN pin and the OUT pin will be less than the
VSD(TST) threshold. In this case, the nFGD pin will remain in a high impedance state and the pin voltage can be
pulled high by an external pull-up resistor.
In normal operation the OFF pin must be pulled low (or left open). In this mode, the GATE pin voltage will
depend upon the forward or reverse voltage across the MOSFET source to drain as previously described.
The OFF pin has an internal pull-down of 5 µA (typical). If the OFF function is not required, the pin may be left
open or connected to ground.
While the OFF pin is low the nFGD pin will always be in a high impedance open state.
Several factors can prevent the nFGD pin from indicating that the external MOSFET is operating normally. If the
LM5050-2 is used to connect parallel, redundant power supplies, one of the connected supplies may hold the
OUT pin voltage close enough to the LM5050-2 IN pin voltage that the VSD(TST) threshold is not exceeded.
Additionally, operating with a high output capacitance value and low load current may require a significant
amount of time before the output capacitance is discharged to the point where the VSD(TST) threshold is exceeded
and the nFGD pin switches low.
Figure 21. Typical Connection
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IN GATE OUT CLOAD
LM5050-2
GND
COUT
Parasitic
Inductance
Parasitic
Inductance
Shorted
Input
Reverse Recovery Current
LM5050-2
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SNVS679B –NOVEMBER 2010–REVISED MARCH 2013
SHORT CIRCUIT FAILURE OF AN INPUT SUPPLY
An abrupt zero ohm short circuit across the input supply will cause the highest possible reverse current to flow
while the internal LM5050-2 control circuitry discharges the gate of the MOSFET. During this time, the reverse
current is limited only by the RDS(ON) of the MOSFET, along with parasitic wiring resistances and inductances.
Worst case instantaneous reverse current would be limited to:
ID(REV) = (VOUT - VIN) / RDS(ON) (1)
The internal Reverse Comparator will react, and will start the process of discharging the Gate, when the reverse
current reaches:
ID(REV) = VSD(REV) / RDS(ON) (2)
When the MOSFET is finally switched off, the energy stored in the parasitic wiring inductances will be transferred
to the rest of the circuit. As a result, the LM5050-2 IN pin will see a negative voltage spike while the OUT pin will
see a positive voltage spike. The IN pin can be protected by diode clamping the pin to GND in the negative
direction. The OUT pin can be protected with a TVS protection diode, a local bypass capacitor, or both. In low
voltage applications, the MOSFET drain-to-source breakdown voltage rating may be adequate to protect the
OUT pin (i.e. VIN + V(BR)DSS(MAX) < 75V ), but most MOSFET datasheets do not specifiy the maximum breakdown
rating, so this method should be used with caution.
Figure 22. Input Supply Fault Transients
Table 1. FET Test Status Table
FET nFGD nFGD
OFF FET
Mode Gate VIN - VOUT Pin Pin
Pin Status
Drive Status Voltage
Low or Normal Active - - High Z High
Open Operation > VSD(TST) OK Low Z Low
High FET Test Off < VSD(TST) Not OK High Z High
MOSFET SELECTION
The important MOSFET electrical parameters are the maximum continuous Drain current ID, the maximum
Source current (i.e. body diode), the maximum drain-to-source voltage VDS(MAX), the gate-to-source threshold
voltage VGS(TH), the drain-to-source reverse breakdown voltage V(BR)DSS, and the drain-to-source On resistance
RDS(ON).
The maximum continuous drain current, ID, rating must be exceed the maximum continuous load current. The
rating for the maximum current through the body diode, IS, is typically rated the same as, or slightly higher than
the drain current, but body diode current only flows while the MOSFET gate is being charged to VGS(TH):
Gate Charge Time = Qg/ IGATE(ON) (3)
The maximum drain-to-source voltage, VDS(MAX), must be high enough to withstand the highest differential voltage
seen in the application. This would include any anticipated fault conditions.
The drain-to-source reverse breakdown voltage, V(BR)DSS, may provide some transient protection to the OUT pin
in low voltage applications by allowing conduction back to the IN pin during positive transients at the OUT pin.
The gate-to-source threshold voltage, VGS(TH), should be compatible with the LM5050 gate drive capabilities.
Logic level MOSFETs are recommended, but sub-Logic level MOSFETs can also be used.
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The dominate MOSFET loss for the LM5050 active OR-ing controller is conduction loss due to source-to-drain
current to the output load, and the RDS(ON) of the MOSFET. This conduction loss could be reduced by using a
MOSFET with the lowest possible RDS(ON). However, contrary to popular belief, arbitrarily selecting a MOSFET
based solely on having low RDS(ON) may not always give desirable results for several reasons:
1) Reverse transition detection. Higher RDS(ON) will provide increased voltage information to the LM5050 Reverse
Comparator at a lower reverse current level. This will give an earlier MOSFET turn-off condition should the input
voltage become shorted to ground. This will minimize any disturbance of the redundant bus.
2) Reverse current leakage. In cases where multiple input supplies are closely matched it may be possible for
some small current to flow continuously through the MOSFET drain to source (i.e. reverse) without activating the
LM5050 Reverse Comparator. Higher RDS(ON) will reduce this reverse current level.
3) Cost. Generally, as the RDS(ON) rating goes lower, the cost of the MOSFET goes higher.
Selecting a MOSFET with an RDS(ON) that is too large will result in excessive power dissipation. Additionally, the
MOSFET gate will be charged to the full value that the LM5050 can provide as it attempts to drive the Drain to
Source voltage down to the VSD(REG) of 20 mV typical. This increased Gate charge will require some finite
amount of additional discharge time when the MOSFET needs to be turned off.
As a guideline, it is suggest that RDS(ON) be selected to provide at least 20 mV, and no more than 100 mV, at the
nominal load current.
(20 mV / ID)≤RDS(ON) ≤(100mV / ID) (4)
The thermal resistance of the MOSFET package should also be considered against the anticipated dissipation in
the MOSFET in order to ensure that the junction temperature (TJ) is reasonably well controlled, since the RDS(ON)
of the MOSFET increases as the junction temperature increases.
PDISS = ID2x (RDS(ON)) (5)
Operating with a maximum ambient temperature (TA(MAX)) of 35°C, a load current of 10A, and an RDS(ON) of 10
mΩ, and desiring to keep the junction temperature under 100°C, the maximum junction-to-ambient thermal
resistance rating (θJA) would need to be:
θJA≤(TJ(MAX) - TA(MAX))/(ID2x RDS(ON)) (6)
θJA≤(100°C - 35°C)/(10A x 10A x 0.01Ω) (7)
θJA≤65°C/W (8)
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Product Folder Links: LM5050-2
VIN
48V VOUT
48V
GND
OFF
OUT
IN GATE
LM5050-2
GND GND
Q1
SUM40N15-38
+
D1
SS16T3
D3
SS16T3
D2
SMBJ100A
CIN
1 PF
75V COUT
22 PF
63V
VIN
48V VOUT
48V
GND
OFF
OUT
IN GATE
LM5050-2
GND GND
Q1
SUM40N10-30
+
D1
SS16T3 D2
SMBJ60A
CIN
1 PF
75V COUT
22 PF
63V
VLOGIC
5.0V
R1
100 k:
STATUS nFGD
OFF/ON
VIN
6V to 75V VOUT
GND
OFF
OUT
IN GATE
LM5050-2
GND GND
Q1
SUM40N10-30
D1
B180-13-F
CIN
1 PF
100V
VLOGIC
5.0V
R1
100 k:
STATUS nFGD
OFF/ON
LM5050-2
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SNVS679B –NOVEMBER 2010–REVISED MARCH 2013
TYPICAL APPLICATIONS
Figure 23. Basic Application with Input Transient Protection
Figure 24. Typical +48V Application with Transient Protection
Figure 25. +48V Application with Reversed Input Voltage (VIN = -48V) Protection
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REVISION HISTORY
Changes from Revision A (March 2013) to Revision B Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 15
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PACKAGE OPTION ADDENDUM
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Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LM5050MK-2/NOPB ACTIVE SOT-23-THIN DDC 6 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 SZJB
LM5050MKX-2/NOPB ACTIVE SOT-23-THIN DDC 6 3000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 SZJB
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PACKAGE OPTION ADDENDUM
www.ti.com 28-Feb-2017
Addendum-Page 2
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LM5050MK-2/NOPB SOT-
23-THIN DDC 6 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LM5050MKX-2/NOPB SOT-
23-THIN DDC 6 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Mar-2017
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM5050MK-2/NOPB SOT-23-THIN DDC 6 1000 210.0 185.0 35.0
LM5050MKX-2/NOPB SOT-23-THIN DDC 6 3000 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Mar-2017
Pack Materials-Page 2
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