Document ID#: 080211 Date: Sep 19, 2007
Rev: JVersion: 2
Distribution: Public Document
™
Le79R70
Ringing Subscriber Line Interface Circuit
VE580 Series
APPLICATIONS
Integrated Access Devices (IADs)
Network Interface Units (NIUs)
Cable Modems
DSL Modems
Set Top / House Side Boxes
Intelligent PBX
Pain Gain
FXS Cards
Voice over ISDN or T1/E1
Smart Residential Gateways
WLL, APON, FITL, NGN, and all other short-loop CPE/
Enterprise telephony applications
FEATURES
Ideal for ISDN-TA and set top applications
On-chip ringing with on-chip ring-trip detector
Low Standby state power
Battery operation:
— VBAT1: –40 V to –67 V
— VBAT2: –19 V to VBAT1
On-chip battery switching and feed selection
On-hook transmission
Polarity reversal option
Programmable constant-current feed
Programmable open circuit voltage
Programmable loop-detect threshold
Current gain = 1000
Two-wire impedance set by single component
Ground-key detector
Tip Open state for ground-start lines
Internal VEE regulator (no external –5 V power supply
required)
Two on-chip relay drivers and snubber circuits
Space-saving package options (8x8 QFN)
RELATED LITERATURE
080917 VE790 Series RSLIC Device Product Brief
080158 Le79R70/79/100/101 Ringing SLIC Devices
Technical Overview
080255 Le71HE0040J Evaluation Board User’s Guide
080753 Le58QL02/021/031 QLSLAC™ Data Sheet
ORDERING INFORMATION
1. Zarlink reserves the right to fulfill all orders for this device with
parts marked with the "Am" part number prefix until all inventory
bearing this mark has been depleted. Note that parts marked with
either the "Am" or the "Le" part number prefix are equivalent
devices in terms of form, fit, and function—the prefix appearing on
the topside mark is the only difference.
2. The green package meets RoHS Directive 2002/95/EC of the
European Council to minimize the environmental impact of
electrical equipment.
3. Due to size constraints, QFN devices are marked by omitting the
“Le” prefix and the performance grade dash character. For
example, Le79R70-1QC is marked 79R701QC.
4. For delivery using a tape and reel packing system, add a "T" suffix
to the OPN (Ordering Part Number) when placing an order.
Device1Package Type2, 3 Packing4
Le79R70DJC 32-pin PLCC, No Pol. Rev.
(Green package) Tube
Le79R70-1DJC 32-pin PLCC, Pol. Rev.
(Green package) Tube
Le79R70-1FQC 32-pin QFN, Pol. Rev.
(Green package) Tray
DESCRIPTION
The Le79R70 Ringing Subscriber Line Interface Circuit
(RSLIC) device is a bipolar monolithic SLIC that offers on-chip
ringing. Designers can achieve significant cost reductions at
the system level for short-loop applications by integrating the
ringing function on chip. Examples of such applications would
be ISDN Terminal Adaptors and set top boxes. Using a CMOS-
compatible input waveform and wave shaping R-C network,
the Le79R70 Ringing SLIC device can provide trapezoidal
wave ringing to meet various design requirements.
See the Le79R70 Block Diagram, on page 3.
Le79R70 Data Sheet
2
Zarlink Semiconductor Inc.
TABLE OF CONTENTS
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Related literature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Environmental Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Relay Driver Schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
DC Feed Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Ring-Trip Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Test Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Application Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Physical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
32-Pin PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
32-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Revision A to B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Revision B to C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Revision C to D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Revision D to E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Revision E to F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Revision F to G1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Revision G1 to H1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Revision H1 to I1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Revision I1 to J1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Revision J1 to J2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Le79R70 Data Sheet
3
Zarlink Semiconductor Inc.
PRODUCT DESCRIPTION
The Zarlink family of subscriber line interface circuit (SLIC) products provide the telephone interface functions required
throughout the worldwide market. Zarlink SLIC devices address all major telephony markets including central office (CO),
private branch exchange (PBX), digital loop carrier (DLC), fiber-in-the-loop (FITL), radio-in-the-loop (RITL), hybrid fiber coax
(HFC), and video telephony applications.
The Zarlink SLIC devices offer support of BORSHT (battery feed, over voltage protection, ringing, supervision, hybrid, and test)
functions with features including current limiting, on-hook transmission, polarity reversal, tip-open, and loop-current detection.
These features allow reduction of line card cost by minimizing component count, conserving board space, and supporting
automated manufacturing.
The Zarlink SLIC devices provide the two- to four-wire hybrid function, DC loop feed, and two-wire supervision. Two-wire
termination is programmed by a scaled impedance network. Transhybrid balance can be achieved with an external balance
circuit or simply programmed using a companion Zarlink codec/filter, such as the Le58QL0xx Quad SLAC (QLSLAC™) device.
The Le79R70 Ringing SLIC device is a bipolar monolithic SLIC that offers on-chip ringing. Now designers can achieve significant
cost reductions at the system level for short-loop applications by integrating the ringing function on chip. Examples of such
applications would be ISDN Terminal Adaptors and set top boxes. Using a CMOS-compatible input waveform and wave shaping
R-C network, the Le79R70 Ringing SLIC can provide trapezoidal wave ringing to meet various design requirements.
In order to further enhance the suitability of this device in short-loop, distributed switching applications, Zarlink has maximized
power savings by incorporating battery switching on chip. The Le79R70 Ringing SLIC device switches between two battery
supplies such that in the Off-hook (active) state, a low battery is used to save power. In order to meet the Open Circuit voltage
requirements of fax machines and maintenance termination units (MTU), the SLIC automatically switches to a higher voltage in
the On-hook (standby) state.
Like all of the Zarlink SLIC devices, the Le79R70 Ringing SLIC device supports on-hook transmission, ring-trip detection and
programmable loop-detect threshold. The Le79R70 Ringing SLIC device is a programmable constant-current feed device with
two on-chip relay drivers to operate external relays. This unique device is available in the proven Zarlink 75 V bipolar process.
Figure 1. Le79R70 Block Diagram
E1
D2
D1
Two-Wire
Interface
HPA
HPB
Input Decoder
and Control
Relay
Driver
Ring-Trip
Detector
Power-Feed
Controller
RTRIP1
RTRIP2
BGNDVCC VNEG
RD
RDC
AGND/DGND
VBAT2
A(TIP)
B(RING)
RYOUT1
RDCR
C1
Switch
Driver
VBAT1
RSGL
Ground-Key
Detector
Off-Hook
Detector
Relay
Driver RYOUT2
C2
C3
RSGH
B2EN
RSN
VTX
Signal
Transmission
RINGIN
RYE
DET
Le79R70 Data Sheet
4
Zarlink Semiconductor Inc.
CONNECTION DIAGRAM
1
32-pin QFN
RSN
VNEG
VTX
RDCR
RINGIN
HPA
HPB
RTRIP2
21
20
19
18
17
22
23
24
E1
C3
C2
RYE
RYOUT1
B2EN
VBAT1
D1
2
3
4
5
6
7
8
C1
D2
AGND/
DGND
RSGL
RDC
N/C
RSGH
1091211 1413 1615
RTRIP1
A(TIP)
RD
B(RING)
VBAT2
BGND
VCC
RYOUT2
32 31 30 29 28 27 26 25
DET
Exposed Pad
Notes:
1. Pin 1 is marked for orientation.
2. NC = No connect
3. RSVD = Reserved. Do not connect to this pin.
4. The thermally enhanced QFN package features an exposed pad on the underside which must be electrically tied to VBAT1.
32-Pin PLCC
RTRIP1
4 3 2 1 32 31 30
25
24
23
22
21
20191817161514
13
12
11
10
9
8
7
6
5
D1
HPB
HPA
VNEG
RSN
26
27
28
29
RYOUT1
C2
RYE
VTX
B2EN
RDCR
RYOUT2
VBAT1
E1
C3
D2
NC
RDC
RTRIP2
RINGIN
VCC
VBAT2
BGND
B(RING)
A(TIP)
RD
C1
RSGH
RSGL
AGND/DGND
DET
Le79R70 Data Sheet
5
Zarlink Semiconductor Inc.
Pin Descriptions
Pin Names Type Description
AGND/DGND Gnd Analog and digital ground are connected internally to a single pin.
A(TIP) Output Output of A(TIP) power amplifier.
B2EN Input VBAT2 enable. Logic Low enables operation from VBAT2. Logic High enables operation from VBAT1. TTL
compatible.
BGND Gnd Battery (power) ground
B(RING) Output Output of B(RING) power amplifier.
C3–C1 Input Decoder. TTL compatible. C3 is MSB and C1 is LSB.
D1 Input Relay1 control. TTL compatible. Logic Low activates the Relay1 relay driver.
D2 Input (Option) Relay2 control. TTL compatible. Logic Low activates the Relay2 relay driver.
DET Output Detector. Logic Low indicates that the selected detector is tripped. Logic inputs C3–C1 and E1 select the
detector. Open-collector with a built-in 15 kΩ pull-up resistor.
E1 Input (Option) A logic High selects the off-hook detector. A logic Low selects the ground-key detector. TTL
compatible.
HPA Capacitor High-pass filter capacitor. A(TIP) side of high-pass filter capacitor.
HPB Capacitor High-pass filter capacitor. B(RING) side of high-pass filter capacitor.
RD Resistor Detect resistor. Threshold modification and filter point for the off-hook detector.
RDC Resistor DC feed resistor. Connection point for the DC-feed current programming network, which also connects to the
receiver summing node (RSN). VRDC is negative for normal polarity and positive for reverse polarity.
RDCR —Connection point for feedback during ringing.
RINGIN Input Ring Signal Input. Pin for ring signal input. Square-wave shaped by external RC filter. Requires 50% duty
cycle. CMOS-compatible input.
RSGH Input Saturation Guard High. Pin for resistor to adjust Open Circuit voltage when operating from VBAT1.
RSGL Input Saturation Guard Low. Pin for resistor to adjust the anti-saturation cut-in voltage when operating from both
VBAT1 and VBAT2.
RSN Input The metallic current (AC and DC) between A(TIP) and B(RING) is equal to 1000 x the current into this pin.
The networks that program receive gain, two-wire impedance, and feed resistance all connect to this node.
RTRIP1 Input Ring-trip detector. Ring-trip detector threshold set and filter pin.
RTRIP2 Input Ring-trip detector threshold offset (switch to VBAT1). For power conservation in any non-ringing state, this
switch is open.
RYE Output Common Emitter of RYOUT1/RYOUT2. Emitter output of RYOUT1 and RYOUT2. Normally connected to
relay ground.
RYOUT1 Output Relay/switch driver. Open-collector driver with emitter internally connected to RYE.
RYOUT2 Output (Option) Relay/switch driver. Open-collector driver with emitter internally connected to RYE.
VBAT1 Battery Battery supply and connection to substrate.
VBAT2 Battery Power supply to output amplifiers. Connect to off-hook battery through a diode.
VCC Power Positive analog power supply.
VNEG Power Negative analog power supply. This pin is the return for the internal VEE regulator.
VTX Output Transmit Audio. This output is a 0.5066 gain version of the A(TIP) and B(RING) metallic AC voltage. VTX also
sources the two-wire input impedance programming network.
Exposed Pad Battery This must be electrically tied to VBAT1.
Le79R70 Data Sheet
6
Zarlink Semiconductor Inc.
ABSOLUTE MAXIMUM RATINGS
Stresses above those listed under Absolute Maximum Ratings can cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.
Note:
1. Thermal limiting circuitry on the chip will shut down the circuit at a junction temperature of about 165ºC. Continuous operation above 145ºC
junction temperature may degrade device reliability.
2. The thermal performance of a thermally enhanced package is assured through optimized printed circuit board layout. Specified performance
requires that the exposed thermal pad be soldered to an equally sized exposed copper surface, which, in turn, conducts heat through
multiple vias to a large internal copper plane.
Package Assembly
Green package devices are assembled with enhanced, environmental compatible lead-free, halogen-free, and antimony-free
materials. The leads possess a matte-tin plating which is compatible with conventional board assembly processes or newer lead-
free board assembly processes. The peak soldering temperature should not exceed 245°C during printed circuit board assembly.
Refer to IPC/JEDEC J-Std-020B Table 5-2 for the recommended solder reflow temperature profile.
OPERATING RANGES
Environmental Ranges
Zarlink guarantees the performance of this device over the commercial (0º C to 70º C) temperature range by conducting
electrical characterization and by conducting a production test with single insertion coupled to periodic sampling. These
characterization and test procedures comply with section 4.6.2 of Bellcore GR-357-CORE Component Reliability Assurance
Requirements for Telecommunications Equipment.
Storage temperature –55 to +150°C
Ambient temperature under bias 0 to +70°C
VCC with respect to AGND/DGND 0.4 to + 7 V
VNEG with respect to AGND/DGND 0.4 V to VBAT2
VBAT2 VBAT2 to GND
VBAT1 with respect to AGND/DGND:
Continuous +0.4 to -80 V
10 ms +0.4 to -85 V
BGND with respect to AGND/DGND +3 to -3 V
A (TIP) or B (RING) to BGND:
Continuous VBAT1 – 5 V+ 1 V
10 ms (F = 0.1 Hz) VBAT1 – 10 V+ 5 V
1 µs (F = 0.1 Hz) VBAT1 – 15 V+ 8 V
250 ns (F = 0.1 Hz) VBAT1 – 20 V+ 12 V
Current from A (TIP) or B (RING) ± 150 mA
RYOUT1, RYOUT2 current 75 mA
RYOUT1, RYOUT2 voltage RYE to +7 V
RYOUT1, RYOUT2 transient RYE to +10 V
RYE voltage BGND to VBAT1
C3-C1, D2-D1, E1, B2EN and RINGIN:
Input voltage -0.4 V to VCC + 0.4 V
Maximum continuous power dissipation, TA = 70° C1:
In 32-pin PLCC package 1.67 W
In 32-pin QFN package 3.00 W
Thermal Data: θJA
In 32-pin PLCC package 45° C/W
In 32-pin QFN package225° C/W
ESD Immunity (Human Body Model) JESD22 Class 1C compliant
Le79R70 Data Sheet
7
Zarlink Semiconductor Inc.
Environmental Ranges
Electrical Ranges
Note:
The Operating Ranges define those limits between which the functionality of the device is guaranteed.
Ambient Temperature 0 to 70° C
VCC 4.75 V to 5.25 V
VNEG -4.75 V to VBAT2
VBAT1 -40 to -67 V
VBAT2 -19 V to VBAT1
AGND/DGND 0 V
BGND with respect to AGND/DGND -100 mV to +100 mV
Load resistance on VTX to GND 20 kΩ min
Le79R70 Data Sheet
8
Zarlink Semiconductor Inc.
ELECTRICAL CHARACTERISTICS
Description Test Conditions (See Note 1) Min Typ Max Unit Note
Transmission Performance
2-wire return loss 200 Hz to 3.4 kHz (Test Circuit D) 26 dB 1, 4, 6
ZVTX, analog output impedance 320 Ω4
VVTX, analog output offset voltage –50 +50 mV
ZRSN, analog input impedance 120 Ω4
Overload level, 2-wire and 4-wire, off hook Active state 2.5 Vpk 2a
Overload level, 2-wire On hook, RLAC = 600 Ω0.88 Vrms 2b
THD (Total Harmonic Distortion) +3 dBm, BAT2 = –24 V –64 –50
dB 5
THD, on hook, OHT state 0 dBm, RLAC = 600 Ω,
BAT1 = –67 V
–40
Longitudinal Performance (See Test Circuit C)
Longitudinal to metallic L-T, L-4 balance 200 Hz to 3.4 kHz 40 dB
Longitudinal signal generation 4-L 200 Hz to 800 Hz, Normal polarity 40
Longitudinal current per pin (A or B) Active or OHT state 12 28 mArms 4
Longitudinal impedance at A or B 0 to 100 Hz, TA = +25°C 25 Ω/pin
Idle Channel Noise
C-message weighted noise +7 +14 dBrnC
Psophometric weighted noise –83 –76 dBmp 4
Insertion Loss and Four- to Four-Wire Balance Return Signal (See Test Circuits A and B)
Gain accuracy 4- to 2-wire 0 dBm, 1 kHz –0.20 0+0.20
dB
3
Gain accuracy 2- to 4-wire and
4- to 4-wire
0 dBm, 1 kHz –6.22 –6.02 –5.82
Gain accuracy 4- to 2-wire OHT state, on hook –0.35 0+0.35
Gain accuracy 2- to 4-wire and
4- to 4-wire
OHT state, on hook –6.37 –6.02 –5.77
Gain accuracy over frequency 300 to 3400 Hz
relative to 1 kHz
–0.10 +0.10
Gain tracking +3 dBm to –55 dBm
relative to 0 dBm
–0.10 +0.10 3, 4
Gain tracking
OHT state, on hook
0 dBm to –37 dBm
+3 dBm to 0 dBm
–0.10
–0.35
+0.10
+0.35
3, 4
3
Group delay 0 dBm, 1 kHz 3µs 1, 4, 6
Le79R70 Data Sheet
9
Zarlink Semiconductor Inc.
ELECTRICAL CHARACTERISTICS (CONTINUED)
Description Test Conditions (See Note 1) Min Typ Max Unit Note
Line Characteristics
IL, Loop-current accuracy IL in constant-current region,
B2EN = 0
0.87ILIL1.1IL
mA
IL, Long loops, Active state RLDC = 600 Ω, RSGL = open
RLDC = 750 Ω, RSGL = short
20
20
21.7
IL, Accuracy, Standby state
0.8ILIL1.2IL
IL = constant-current region
TA = 25°C
18 27 39
ILLIM Active, A and B to ground
OHT, A and B to ground
55
55
110
4
IL, Loop current, Open Circuit state RL = 0 100 µA
IA, Pin A leakage, Tip Open state RL = 0 100
IB, Pin B current, Tip Open state B to ground 34 mA
VA, Standby, ground-start signaling A to –48 V = 7 kΩ,
B to ground = 100 Ω
–7.5 –5
V
4
VAB, Open Circuit voltage 42 7
Power Supply Rejection Ratio (VRIPPLE = 100 mVrms), Active Normal State
VCC 50 Hz to 3400 Hz 33 50
dB 5
VNEG 50 Hz to 3400 Hz 30 40
VBAT1 50 Hz to 3400 Hz 30 50
VBAT2 50 Hz to 3400 Hz 30 50
Power Dissipation
On hook, Open Circuit state VBAT1 48 100
mW
On hook, Standby state VBAT2 55 80 9
On hook, OHT state VBAT1 200 300
On hook, Active state VBAT1 220 350
Off hook, Standby state VBAT1 or VBAT2 RL = 300 Ω2000 2800 9
Off hook, OHT state VBAT1 RL = 300 Ω2000 2200
Off hook, Active state VBAT2 RL = 300 Ω550 750
Supply Currents
ICC, On-hook VCC supply current Open Circuit state
Standby state
OHT state
Active state–normal
3.0
3.2
6.2
6.5
4.5
5.5
8.0
9.0
mA
INEG, On-hook VNEG supply current Open Circuit state
Standby state
OHT state
Active state–normal
0.1
0.1
0.7
0.7
0.2
0.2
1.1
1.1
IBAT, On-hook VBAT supply current Open Circuit state
Standby state
OHT state
Active state–normal
0.45
0.6
2.0
2.7
1.0
1.5
4.0
5.0
IL
VBAT1 10 V–
RL400+
--------------------------------------=
Le79R70 Data Sheet
10
Zarlink Semiconductor Inc.
ELECTRICAL CHARACTERISTICS (continued)
RELAY DRIVER SCHEMATIC
Description Test Conditions (See Note 1) Min Typ Max Unit Note
Logic Inputs (C3–C1, D2–D1, E1, and B2EN)
VIH, Input High voltage 2.0 V
VIL, Input Low voltage 0.8
IIH, Input High current –75 40 µA
IIL, Input Low current –400
Logic Output DET
VOL, Output Low voltage IOUT = 0.8 mA, 15 kΩ to VCC 0.40 V
VOH, Output High voltage IOUT = –0.1 mA, 15 kΩ to VCC 2.4
Ring-Trip Detector Input
Ring detect accuracy –10 +10 %
Ring Signal
VAB, Ringing Bat1 = –67 V, ringload = 1570 Ω57 61 Vpk
VAB Ringing offset VRINGIN = 2.5 V 0 V
∆VAB/∆VRINGIN (RINGIN gain) 180 —
Ground-Key Detector Thresholds
Ground-key resistive threshold B to ground 2 5 10 kΩ
Ground-key current threshold B to ground 11 mA
Loop Detector
RLTH, Loop-resistance detect threshold Active, VBAT1
Active, VBAT2
Standby
–20
–20
–12
20
20
12
% 8
Relay Driver Output (RELAY1 and 2)
VOL, On voltage (each output) IOL = 30 mA +0.25 +0.4 V
VOL, On voltage (each output) IOL = 40 mA +0.30 +0.8 4
IOH, Off leakage (each output) VOH = +5 V 100 µA
Zener breakover (each output) IZ = 100 µA 6.6 7.9 V
Zener on voltage (each output) IZ = 30 mA 11
IRTD BAT1 1–
RRT1
----------------------------24µA+
335•=
RYOUT1
BGND
RYOUT2
BGND
RYE
Le79R70 Data Sheet
11
Zarlink Semiconductor Inc.
Notes:
1. Unless otherwise noted, test conditions are BAT1 = –67 V, BAT2 = –24 V, VCC = +5 V, VNEG = –5 V, RL = 600 Ω,
RDC1 = 80 kΩ, RDC2 = 20 kΩ, RD = 75 kΩ, no fuse resistors, CHP = 0.018 µF, CDC = 1.2 µF, D1 = D2 = 1N400x,
two-wire AC input impedance (ZSL) is a 600 Ω resistance synthesized by the programming network shown below.
RSGL = open, RSGH = open, RDCR = 2 kΩ, RRT1 = 430 kΩ, RRT2 = 12 kΩ, CRT = 1.5 µF, RSLEW = 150 kΩ, CSLEW = 0.33 µF.
2. a. Overload level is defined when THD = 1%.
b. Overload level is defined when THD = 1.5%.
3. Balance return signal is the signal generated at VTX by VRX. This specification assumes that the two-wire AC load impedance
matches the programmed impedance.
4. Not tested in production. This parameter is guaranteed by characterization or correlation to other tests.
5. This parameter is tested at 1 kHz in production. Performance at other frequencies is guaranteed by characterization.
6. Group delay can be greatly reduced by using a ZT network such as that shown in Note 1 above. The network reduces the
group delay to less than 2 µs and increases 2WRL. The effect of group delay on line card performance may also be compen-
sated for by synthesizing complex impedance with the QSLAC or DSLAC device.
7. Open Circuit VAB can be modified using RSGH.
8. RD must be greater than 56 kΩ. Refer to Tabl e 2 for typical value of RLTH.
9. Lower power is achieved by switching into low-battery state in standby. Standby loop current is returned to VBAT1 regardless
of the battery selected.
Table 1. SLIC Decoding
(DET) Output
State C3 C2 C1 2-Wire Status E1 = 1 E1 = 0 Battery Selection
00 0 0 Open Circuit Ring trip Ring trip
B2EN
10 0 1 Ringing Ring trip Ring trip
20 1 0 Active Loop detector Ground key
30 1 1 On-hook TX (OHT) Loop detector Ground key
41 0 0 Tip Open Loop detector Ground key B2EN = 1**
51 0 1 Standby Loop detector Ground key VBAT1
6* 1 1 0 Active Polarity Reversal Loop detector Ground key B2EN
7* 1 1 1 OHT Polarity Reversal Loop detector Ground key
Notes:
* Only –1 performance grade devices support polarity reversal.
** For correct ground-start operation using Tip Open, VBAT1 on-hook battery must be used.
RT2 = 150 kΩ CT1 = 60 pF
RT1 = 150 kΩ
VTX
RSN
VRX
RRX = 300 kΩ~
Le79R70 Data Sheet
12
Zarlink Semiconductor Inc.
Table 2. User-Programmable Components
ZT is connected between the VTX and RSN pins. The fuse resistors are
RF, and Z2WIN is the desired 2-wire AC input impedance. When com-
puting ZT, the internal current amplifier pole and any external stray ca-
pacitance between VTX and RSN must be taken into account.
ZRX is connected from VRX to RSN. ZT is defined above, and G42L is the
desired receive gain.
RDC1, RDC2, and CDC form the network connected to the RDC pin.
ILOOP is the desired loop current in the constant-current region.
RDCR1, RDCR2, and CDCR form the network connected to the RDCR pin.
See Applications Circuit for these components.
CDCR sets the ringing time constant, which can be between 15 µs and
150 µs.
for high battery state RD is the resistor connected from the RD pin to GND and RLTH is the
loop-resistance threshold between on-hook and off-hook detection. RD
should be greater than 56 kΩ to guarantee detection will occur in the
Standby state. Choose the value of RD for high battery state; then use
the equation for RLTH to find where the threshold is for low battery.
Loop-Threshold Detect Equations
for high battery This is the same equation as for RD in the preceding equation, except
solved for RLTH.
for low battery
For low battery, the detect threshold is slightly higher, which will avoid
oscillating between states.
RLTH standby < RLTH active VBAT1 < RLTH active VBAT2, which will guar-
antee no unstable states under all operating conditions. This equation
will show at what resistance the standby threshold will be; it is actually
a current threshold rather than a resistance threshold, which is shown
by the Vbat dependency.
ZT500 Z2WIN 2RF
–()=
ZRX
ZL
G42L
------------1000 ZT
•
ZT500 ZL2RF
+()+
--------------------------------------------------
•=
RDC1 RDC2
2500
ILOOP
---------------
=+
RDCR1 RDCR2
+3000
Iringlim
----------------------=
CDC 19 ms RDC1 RDC2
+
RDC1RDC2
---------------------------------
•=
CDCR
RDCR1 RDCR2
+
RDCR1RDCR2
---------------------------------------- •150 µs=
RDRLTH 12.67•=
RLTH
RD
12.67
-------------=
RLTH
RD
11.37
-------------=
RLTH
VBAT1 10–
915
----------------------------- RD
•400–2R
F
–=
Le79R70 Data Sheet
13
Zarlink Semiconductor Inc.
DC FEED CHARACTERISTICS
IL (mA)
030
50
VAB
(Volts)
2) VASL
3) VAPPL
40
30
20
10
5) VAPPH
4) VASH
Figure 1. Typical VAB vs. IL DC Feed Characteristics
Notes:
1. Constant-current region: where
2. Low battery where RSGL = resistor to GND, B2EN = logic Low.
Anti-sat region: where RSGL = resistor to VCC, B2EN = logic Low.
RSGL to VCC must be greater than 100 kΩ.
3.
4. High battery
Anti-sat region: where RSGH = resistor to GND, B2EN = logic High.
where RSGH = resistor to VCC, B2EN = logic High.
RSGH to VCC must be greater than 100 kΩ.
5.
RDC RDC1 RDC2 20 kΩ80 kΩ100 kΩ=+=+=
VBAT1 67 V VBAT2 24 V–=,–=()
VAB ILRL
2500
RDC
-------------RL;==R
LR= L2RF
+
VASL
1000 104 •103RSGL
+()•
6720 10•380 RSGL
•()+
-------------------------------------------------------------------;=
VASL
1000 RSGL 56 103
•–()•
6720 103
•80 RSGL
•()+
---------------------------------------------------------------;=
VAPPL 4.17 VASL
+=
ILOOPL
VAPPL
RDC1 RDC2
+()
600
-------------------------------------- 2 R FRLOOP
++
-------------------------------------------------------------------------------=
VASH VASHH VASL
+=
VASHH
1000 70 103
•RSGH
+()•
1934 103
•31.75 RSGH
•()+
-----------------------------------------------------------------------;=
VASHH
1000 RSGH 2.75 103
•+()•
1934 103
•31.75 RSGH
•()+
-----------------------------------------------------------------------;=
VAPPH 4.17 VASH
+=
ILOOPH
VAPPH
RDC1 RDC2
+()
600
-------------------------------------- 2 R FRLOOP
++
-------------------------------------------------------------------------------=
High Battery Anti-Sat
Low Battery Anti-Sat
1) Constant-Current Region
Le79R70 Data Sheet
14
Zarlink Semiconductor Inc.
RING-TRIP COMPONENTS
where RLRT = Loop-detection threshold resistance for ring trip and CF = Crest factor of ringing signal (≈ 1.25)
RSLEW, CSLEW
Ring waveform rise time ≈ 0.214 • (RSLEW • CSLEW) ≈ tr.
For a 1.25 crest factor @ 20 Hz, tr ≈ 10 mS.
∴ (RSLEW = 150 kΩ, CSLEW = 0.33 µF.)
CSLEW should be changed if a different crest factor is desired.
RRT2 12 kΩ=
CRT 1.5 µF=
RRT1 320 CF VBAT1
VBAT1 5–24µA 320 CF RLRT 150 2RF
++()•••()–
------------------------------------------------------------------------------------------------------------------------------------------
•• RLRT 150 2RF
++()•=
0
A(TIP)
Battery
Figure 2. Ringing Waveforms
B(RING)
This is the best time for
switching between RINGING
and other states for minimizing
detect switching transients.
Ringing Reference
(Input to RSLEW)
A
B
I
L
RSN
RDC
R
DC2
R
DC1
C
DC
SLIC
R
L
a
b
Feed current programmed by RDC1 and RDC2
Figure 3. Feed Programming
Le79R70 Data Sheet
15
Zarlink Semiconductor Inc.
TEST CIRCUITS
RT
RRX
VAB
VL
RL
2
IL2-4 = 20 log (VTX / VAB)
A. Two- to Four-Wire Insertion Loss
A(TIP)
B(RING)
AGND
VTX
RSN
SLIC
RT
VAB
A(TIP)
B(RING)
AGND
VTX
RSN
SLIC
RL
RRX
VRX
IL4-2 = 20 log (VAB / VRX)BRS = 20 log (VTX / VRX)
B. Four- to Two-Wire Insertion Loss and Four- to Four-Wire Balance Return Signal
RT
RRX
RL
2
RL
2
VRX
S1 C
S2
VL
VL
A(TIP)
B(RING)
AGND
VTX
RSN
SLIC
1
ωC<< RL
L-4 Long. Bal. = 20 log (VTX / VL)
L-T Long. Bal. = 20 log (VAB / VL) 4-L Long. Sig. Gen. = 20 log (VL / VRX)
C. Longitudinal Balance
RL
2
VAB
S2 Open, S1 Closed S2 Closed, S1 Open
Le79R70 Data Sheet
16
Zarlink Semiconductor Inc.
TEST CIRCUITS (continued)
VCC
A(TIP)
B(RING)
DET
E1
6.2 kΩ
RL = 600 Ω15 pF
E. Loop-Detector Switching
A(TIP)
B(RING)
F. Ground-Key Switching
RG
D. Two-Wire Return Loss Test Circuit
R
R
Return loss = –20 log (2 VM / VS)
ZD: The desired impedance;
e.g., the characteristic impedance of the line
VM
ZIN
VS
A(TIP)
B(RING)
AGND
VTX
RSN
SLIC
RT2
RRX
CT1
RT1
ZD
G. RFI Test Circuit
50 Ω
L1200 Ω
200 Ω
C1
C2
B
HF
GEN VTX
A
SLIC
under test
L2
CAX
33 nF
CBX
33 nF
RF1
RF2
50 Ω
50 Ω
1.5 Vrms
80% Amplitude
Modulated
100 kHz to 30 MHz
Le79R70 Data Sheet
17
Zarlink Semiconductor Inc.
TEST CIRCUITS (continued)
+5 V
H. Le79R70 Test Circuit
VNEG
VCC
RD
RD
VTX
RSN
RRX
RDC2
RDC1
CDC
RT
RDC
–5 V
VBAT1
DET
D1
BGND
RYOUT1
HPB
CHP
HPA
RTRIP2
RTRIP1
A(TIP)
B(RING)
BAT1
VBAT2
2.2 nF
2.2 nF
VTX
VRX
B2EN
D2
BAT2
A(TIP)
B(RING)
0.1 µF
RYOUT2
C1
C2
C3
D1
D2
E1
RDCR
RDCR
AGND/
DGND
RSLEW
CSLEW
RINGIN
RSGH
RSGL
RSGL
RSGH
RRT1
RRT2
CRT
1.5 µF 75 kΩ
12 kΩ430 kΩ
open
20 kΩ
80 kΩ
2.0 kΩ
100 kΩ
1.2 µF
0.33 µF
See Note.
CAX
CBX
18 nF 300 kΩ300 kΩ
0.1 µF
RYE
open
Note:
The input should be 50% duty cycle CMOS-compatible input.
BATTERY
GROUND
ANALOG
GROUND
DIGITAL
GROUND
Le79R70 Data Sheet
18
Zarlink Semiconductor Inc.
APPLICATION CIRCUIT
Note:
The input should be 50% duty cycle CMOS-compatible input.
I. Application Circuit
+5 V
VNEG
VCC
RD
RD
VTX
RSN
RRX
RDC2
RDC1
CDCR
RT1
RDC
–5 V
VBAT1
DET
D1
BGND
RYOUT1
HPB
HPA
RTRIP2
RTRIP1
BAT1
VBAT2
VTX
VRX
B2EN
D2
BAT2
A(TIP)
B(RING)
0.1 µF
RYOUT2
C1
C2
C3
D1
D2
E1
RDCR1
RDCR
AGND/
DGND
RSLEW
CSLEW
RINGIN
RSGH
RSGL
RSGL
RSGH
RRT1
RRT2
CRT
1.5 µF 66 kΩ
12 kΩ515 kΩ
open
50 kΩ
50 kΩ
15 kΩ
150 kΩ
0.33 µF
See Note.
250 kΩ
0.1 µF
RYE
open
125 kΩ
125 kΩ
CDC
RDCR2
15 kΩ
820 nF
CT
RT2
10 nF
Assumptions:
1. 1.25 CF
2. 25 mA ILOOP
3. 100 mA Ringing Current Limit
4. 5.2 kΩ High Battery Loop Threshold
5. 925 Ω Ringing Loop Threshold
6. 600 Ω Two-wire Impedance,
600 Ω ZL
BATTERY
GROUND
ANALOG
GROUND
DIGITAL
GROUND
Bat1 TISP
61089
7. G42L = 1
8. –67 V Vbat1, –24 V Vbat2
CAX = 2.2 nF
K1K1
K2 K2
G
RFA = 50 Ω
RFB = 50 Ω
A
A
CBX = 2.2 nF
CHP
18 nF
TIP
RING
Le79R70 Data Sheet
19
Zarlink Semiconductor Inc.
PHYSICAL DIMENSIONS
32-Pin PLCC
Note:
Packages may have mold tooling markings on the surface. These markings have no impact on the form, fit or function of the
device. Markings will vary with the mold tool used in manufacturing.
NOTES:
1 Dimensioning and tolerancing conform to ASME Y14,5M-1994.
2 To be measured at seating plan - C - contact point.
3 Dimensions “D1” and “E1” do not include mold protrusion.
Allowable mold protrusion is 0.010 inch per side. Dimensions
“D” and “E” include mold mismatch and determined at the
parting line; that is “D1” and “E1” are measured at the extreme
material condition at the upper or lower parting line.
4 Exact shape of this feature is optional.
5 Details of pin 1 identifier are optional but must be located
within the zone indicated.
6 Sum of DAM bar protrusions to be 0.007 max per lead.
7 Controlling dimension : Inch.
8 Reference document : JEDEC MS-016
32-Pin PLCC
JEDEC # MS-016
S
y
mbol Min Nom Max
A 0.125 -- 0.140
A1 0.075 0.090 0.095
D 0.485 0.490 0.495
D1 0.447 0.450 0.453
D2
E 0.585 0.590 0.595
E1 0.547 0.550 0.553
E2
Ԧ0 deg -- 10 deg
32-Pin PLCC
0.205 REF
0.255 REF
Le79R70 Data Sheet
20
Zarlink Semiconductor Inc.
32-Pin QFN
Note:
Packages may have mold tooling markings on the surface. These markings have no impact on the form, fit or function of the
device. Markings will vary with the mold tool used in manufacturing.
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5M-1994.
2. All dimensions are in millimeters. is in degrees.
3. N is the total number of terminals.
4. The Terminal #1 identifier and terminal numbering convention
shall conform to JEP 95-1 and SSP-012. Details of the
Terminal #1
identifier are optional, but must be located within the zone
indicated. The Terminal #1 identifier may be either a mold or
marked feature.
5. Coplanarity applies to the exposed pad as well as the terminals.
6. Reference Document: JEDEC MO-220.
7. Lead width deviates from the JEDEC MO-220 standard.
32-Pin
Q
FN
Min Nom Max
A 0.80 0.90 1.00
A2
b 0.18 0.23 0.28
D
D2 5.70 5.80 5.90
E
E2 5.70 5.80 5.90
e
L 0.43 0.53 0.63
N
A1 0.00 0.02 0.05
A3
aaa
bbb
ccc
0.57 REF
32 LEAD QFN
Symbol
0.10
0.10
0.20
0.20 REF
32
0.80 BSC
8.00 BSC
8.00 BSC
Le79R70 Data Sheet
21
Zarlink Semiconductor Inc.
REVISION HISTORY
Revision A to B
• Minor changes were made to the data sheet style and format to conform to Zarlink standards.
Revision B to C
• The 28-pin SOIC information and package was added to the Ordering Information and the Connection Dia-
grams sections.
• The physical dimensions (PL032 and SOW28) were added to the Physical Dimensions section.
• Updated the Pin Description table to correct inconsistencies.
Revision C to D
• Changed Ring-Trip Components equation from:
To:
Revision D to E
•In “Ordering Information” section, added description for wafer foundry facility optional character.
Revision E to F
• Updated device name from “Am79R70” to “Le79R70” throughout document.
• Added QFN package to “Connection Diagram,” “Absolute Maximum Ratings,” and “Physical Dimensions.”
• Removed reference to PLCC package type in “General Description.”
• Ordering Information: Temperature statement updated to standard.
• Absolute Maximum Ratings: Notes updated to standard.
• Operating Ranges: Temperature statement updated to standard.
Revision F to G1
• Added green package OPNs to Ordering Information, on page 1
• Added Package Assembly, on page 6
Revision G1 to H1
• Added "Packing" column and Note 5 to Ordering Information, on page 1
• Updated 32QFN drawing in Physical Dimensions, on page 19
Revision H1 to I1
• Added green package OPNs and removed OPN for SOIC package in Ordering Information, on page 1
• Removed SOIC drawing in Physical Dimensions, on page 19
• Added note to Physical Dimensions, on page 19
Revision I1 to J1
• Removed the following OPNs from Ordering Information, on page 1: Le79R70JC, Le79R70-1JC, Le79R70QC, Le79R70-
1QC.
• Changed IL Loop-Current Accuracy from 0.9 to 0.871 in Electrical Characteristics.
Revision J1 to J2
• Enhanced format of package drawings in Physical Dimensions, on page 19
• Added new headers/footers due to Zarlink purchase of Legerity on August 3, 2007
RRT1 300 CF VBAT1
Vbat 3.5–15µA 300 CF RLRT 150 2RF
++()•••()–
------------------------------------------------------------------------------------------------------------------------------------------
•• RLRT 150 2RF
++()•=
RRT1 320 CF VBAT1
Vbat 5–24µA 320 CF RLRT 150 2RF
++()•••()–
-------------------------------------------------------------------------------------------------------------------------------------
•• RLRT 150 2RF
++()•=
www.zarlink.com
Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable.
However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such
information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or
use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual
property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in
certain ways or in combination w it h Z arlink, or non-Zarlink furnished goods or servic es may infringe patents or other intelle ctual property rights owned by Zarlink.
This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part
of any order or contract nor to be regarded as a rep r esentation relating to t he products or services conce r ned. The products, their specificat ions, services and othe r
information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the
capability, performance o r suitability o f any pro duct or service. I nformatio n conce rning po ssible met hods of use is p rovided a s a gu ide o nly and d oes n ot const itute
any guarantee th at such methods of use wil l be satisfactory in a sp ecific piece of equip ment. It is the user ’s responsibilit y to fully determine the performance and
suitability of any equipment usi ng such information and to ensure that any publica tion or data used is up to date and has not been superseded. Manufacturing does
not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in
significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale whi ch are ava ila bl e on reque st.
Purchase of Zarlink’s I2C components conveys a license un der the Philips I2C Patent rights to use thes e components in an I2C System, provided that the system
conforms to the I2C Standard Specif ication as defined by Philips.
Zarlink, ZL, the Zarlink Semiconductor logo and the Legerity logo and combinations thereof, VoiceEdge, VoicePort, SLAC, ISLIC, ISLAC and VoicePath are
trademarks of Zarlink Semiconductor Inc.
TECHNICAL DOCUMENTATION - NOT FOR RESALE
For more information about all Zarlink prod ucts
visit our Web Site at
