AD7291BCPZ-RL7 - Analog Devices - Datasheet.Directory

8-Channel, I2C, 12-Bit SAR ADC

with Temperature Sensor

Data Sheet AD7291

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

FEATURES

12-bit SAR ADC

8 single-ended analog input channels

Analog input range: 0 V to 2.5 V

12-bit temperature-to-digital converter

Temperature sensor accuracy of ±1°C typical

Channel sequencer operation

Specified for VDD of 2.8 V to 3.6 V

Logic voltage VDRIVE = 1.65 V to 3.6 V

Internal 2.5 V reference

I2C-compatible serial interface supports standard and

fast speed modes

Out of range indicator/alert function

Autocycle mode

Power-down current: 12 μA maximum

Temperature range: −40°C to +125°C

20-lead LFCSP package

FUNCTIONAL BLOCK DIAGRAM

TEMP

SENSOR

12-BIT

SUCCESSIVE

APPROXIMATION

ADC

INPUT

MUX

T/H

GND

PD/RST

SCL

SDA

AS1

AS0

DRIVE

IN7

IN0

CO NT R O L L OG I C

C INT E RFACE

SEQUENCER

REF

BUFREF

AD7291

08711-001

ALERT

Figure 1.

GENERAL DESCRIPTION

The AD7291 is a 12-bit, low power, 8-channel, successive

approximation analog-to-digital converter (ADC) with an

internal temperature sensor.

The part operates from a single 3.3 V power supply and features

an I2C-compatible interface. The part contains a 9-channel

multiplexer and a track-and-hold amplifier than can handle

frequencies up to 30 MHz. The device has an on-chip 2.5 V

reference that can be disabled to allow the use of an external

reference.

The AD7291 provides a 2-wire serial interface compatible with

I2C interfaces. The I2C interface supports standard and fast I2C

interface modes. The AD7291 normally remains in a partial

power-down state while not converting and powers up for

conversions. The conversion process can be controlled by a

command mode where conversions occur across I2C write

operations or an autocycle mode selected through software

control.

The AD7291 includes a high accuracy band gap temperature

sensor, which is monitored and digitized by the 12-bit ADC to

give a resolution of 0.25°C.

The AD7291 offers a programmable sequencer, which enables

the selection of a preprogrammable sequence of channels for

conversion.

On-chip limit registers can be programmed with high and low

limits for the conversion results; an out-of-range indicator

output (ALERT) becomes active when the programmed high

or low limits are violated by the conversion result. This output

can be used as an interrupt.

PRODUCT HIGHLIGHTS

1. Ideally suited to monitoring system variables in a variety

of systems including telecommunications, process control,

and industrial control.

2. I2C-compatible serial interface, which supports standard

and fast modes.

3. Automatic partial power-down while not converting to

maximize power efficiency.

4. Channel sequencer operation.

5. Integrated temperature sensor with 0.25°C resolution.

6. Out of range indicator that can be software disabled or

enabled.

Table 1. AD7291 and Related Products

Device Resolution Interface Features

AD7291 12-bit I2C 8-channel, I2C, 12-bit SAR

ADC with temperature sensor

AD7298 12-bit SPI 8-channel, 1 MSPS, 12-bit SAR

ADC with temperature sensor

AD7291 Data Sheet

Rev. B | Page 2 of 28

TABLE OF CONTENTS

Features .............................................................................................. 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

I2C Timing Specifications............................................................ 5

Absolute Maximum Ratings............................................................ 6

Thermal Resistance ...................................................................... 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 8

Terminology .................................................................................... 11

Circuit Information........................................................................ 12

Converter Operation.................................................................. 12

Analog Input ............................................................................... 12

ADC Transfer Function............................................................. 13

Temperature Sensor Operation ................................................ 13

Temperature Sensor Averaging................................................. 13

VDRIVE ............................................................................................ 14

The Internal or External Reference.......................................... 14

Reset ............................................................................................. 14

Internal Register Structure ............................................................ 15

Address Pointer Register ........................................................... 15

Command Register (0x00)........................................................ 17

Voltage Conversion Result Register (0x01) ............................ 18

TSENSE Conversion Result Register (0x02)................................ 18

TSENSE Average Result Register (0x03)...................................... 19

Limit Registers (0x04 to 0x1E) ................................................. 19

Hysteresis Register ..................................................................... 20

Alert Status Register A and Alert Status Register B (0x1F and

0x20)............................................................................................. 20

I2C Interface .................................................................................... 21

Serial Bus Address Byte ............................................................. 21

General I2C Timing.................................................................... 21

Writing to the AD7291 .................................................................. 22

Writing Two Bytes of Data to a 16-Bit Register ..................... 22

Writing to Multiple Registers.................................................... 22

Reading Data From the AD7291.................................................. 23

Reading Two Bytes of Data from a 16-Bit Register ............... 23

Modes of Operation ....................................................................... 24

Command Mode ........................................................................ 24

Autocycle Mode.......................................................................... 26

Outline Dimensions ....................................................................... 27

Ordering Guide .......................................................................... 27

REVISION HISTORY

10/11—Rev. A to Rev. B

Changes to Table 9.......................................................................... 16

8/11—Rev. 0 to Rev. A

Changes to Temperature Sensor—Internal, Accuracy Parameter,

Table 2 ................................................................................................ 3

1/11—Revision 0: Initial Version

Data Sheet AD7291

Rev. B | Page 3 of 28

SPECIFICATIONS

VDD = 2.8 V to 3.6 V; VDRIVE = 1.65 V to 3.6 V; fSCL = 400 kHz, fast SCLK mode; VREF = 2.5 V internal/external; TA = −40°C to +125°C,

unless otherwise noted.

Table 2.

Parameter Min Typ Max Unit1 Test Conditions/Comments

DYNAMIC PERFORMANCE fIN = 1 kHz sine wave

Signal-to-Noise Ratio (SNR)2 70 71 dB

Signal-to-Noise (+ Distortion) Ratio (SINAD)2 70 71 dB

Total Harmonic Distortion (THD)2 −84 −78 dB

Spurious-Free Dynamic Range (SFDR) −85 −80 dB

Intermodulation Distortion (IMD) f

A = 5.4 kHz, fB = 4.6 kHz

Second-Order Terms −88 dB

Third-Order Terms −88 dB

Channel-to-Channel Isolation −100 dB fIN = 10 kHz

Full Power Bandwidth3 30 MHz At 3 dB

10 MHz At 0.1 dB

DC ACCURACY

Resolution 12 Bits

Integral Nonlinearity (INL)2 ±0.5 ±1 LSB

Differential Nonlinearity (DNL)2 ±0.5 ±0.99 LSB Guaranteed no missed codes to 12 bits

Offset Error2 ±2 ±4.5 LSB

Offset Error Matching2 ±2.5 ±4.5 LSB

Offset Temperature Drift 4 ppm/°C

Gain Error2 ±1 ±4 LSB

Gain Error Matching2 ±1 ±2.5 LSB

Gain Temperature Drift 0.5 ppm/°C

ANALOG INPUT

Input Voltage Ranges 0 VREF V

DC Leakage Current ±0.01 ±1 µA

Input Capacitance3 34 pF When in track

8 pF When in hold

REFERENCE INPUT/OUTPUT

Reference Output Voltage4 2.4925 2.5 2.5075 V ±0.3% maximum at 25°C

Long-Term Stability 150 ppm For 1000 hours

Output Voltage Hysteresis 50 ppm

Reference Input Voltage Range5 1 2.5 V

DC Leakage Current ±0.01 ±1 µA External reference applied to Pin VREF

VREF Output Impedance 1 Ω

Reference Temperature Coefficient 12 35 ppm/°C

VREF Noise3 60 µV rms Bandwidth = 10 MHz

LOGIC INPUTS (SDA, SCL)

Input High Voltage, VINH 0.7 × VDRIVE V

Input Low Voltage, VINL 0.3 × VDRIVE V

Input Current, IIN ±0.01 ±1 µA VIN = 0 V or VDRIVE

Input Capacitance, CIN3 6 pF

Input Hysteresis, VHYST 0.1 × VDRIVE V

AD7291 Data Sheet

Rev. B | Page 4 of 28

Parameter Min Typ Max Unit1 Test Conditions/Comments

LOGIC OUTPUTS

Output High Voltage, VOH V

DRIVE − 0.3 V VDRIVE < 1.8

DRIVE − 0.2 V VDRIVE ≥ 1.8

Output Low Voltage, VOL 0.4 V ISINK = 3 mA

0.6 V ISINK = 6 mA

Floating State Leakage Current ±0.01 ±1 µA

Floating State Output Capacitance3 8 pF

TEMPERATURE SENSOR—INTERNAL

Operating Range −40 +125 °C

Accuracy ±1 ±2 °C TA = −40°C to +85°C

±1 ±3 °C TA = 85°C to 125°C

Resolution 0.25 °C LSB size

CONVERSION RATE

Conversion Time 3.2 s

Autocycle Update Rate6 50 s

Throughput Rate 22.22 kSPS fSCL = 400 kHz

POWER REQUIREMENTS Digital inputs = 0 V or VDRIVE

VDD 2.8 3 3.6 V

VDRIVE 1.65 3 3.6 V

ITOTAL 7, 8

Normal Mode (Operational) 2.9 3.5 mA

Normal Mode (Static) 2.9 3.3 mA

Full Power-Down Mode 0.3 1.6 A TA = −40°C to +25°C

1.6 4.5 A TA = >25°C to 85°C

4.9 12 A TA = >85°C to 125°C

Power Dissipation8

Normal Mode (Operational) 8.7 10.5 mW VDD = 3 V, VDRIVE = 3 V

10.4 12.6 mW

Normal Mode (Static) 10.4 11.9 mW

Full Power-Down Mode 1.1 5.8 µW TA = −40°C to +25°C

5.8 16.2 µW TA = >25°C to 85°C

17.6 43.2 µW TA = >85°C to 125°C

1 All specifications expressed in decibels are referred to full-scale input, FSR, and tested with an input signal at 0.5 dB below full scale, unless otherwise specified.

2 See the Terminology section.

3 Sample tested during initial release to ensure compliance.

4 Refers to Pin VREF specified for 25oC.

5 A correction factor may be required on the temperature sensor results when using an external VREF (see the Temperature Sensor Averaging section).

6 Sampled during initial release to ensure compliance; not subject to production testing.

7 ITOTAL is the total current flowing in VDD and VDRIVE.

8 ITOTAL and power dissipation are specified with VDD = VDRIVE = 3.6 V, unless otherwise noted.

Data Sheet AD7291

Rev. B | Page 5 of 28

I2C TIMING SPECIFICATIONS

Guaranteed by initial characterization. All values were measured with the input filtering enabled. CB refers to the capacitive load on the

bus line, with tR and tF measured between 0.3 × VDRIVE and 0.7 × VDRIVE (see Figure 2). VDD = 2.8 V to 3.6 V; VDRIVE = 1.65 V to 3.6 V; VREF =

2.5 V internal/external; TA = −40°C to +125°C, unless otherwise noted.

Table 3.

Limit at TMIN, TMAX

Parameter Conditions Min Typ Max Unit Description

fSCL Standard mode 100 kHz Serial clock frequency

Fast mode 400 kHz

t1 Standard mode 4 µs tHIGH, SCL high time

Fast mode 0.6 µs

t2 Standard mode 4.7 µs tLOW, SCL low time

Fast mode 1.3 µs

t3 Standard mode 250 ns tSU;DAT, data setup time

Fast mode 100 ns

t41 Standard mode 0 3.45 µs tHD;DAT, data hold time

Fast mode 0 0.9 µs

t5 Standard mode 4.7 µs tSU;STA, setup time for a repeated start condition

Fast mode 0.6 µs

t6 Standard mode 4 µs tHD;STA, hold time for a repeated start condition

Fast mode 0.6 µs

t7 Standard mode 4.7 µs tBUF, bus-free time between a stop and a start condition

Fast mode 1.3 µs

t8 Standard mode 4 µs tSU;STO, setup time for a stop condition

Fast mode 0.6 µs

t9 Standard mode 1000 ns tRDA, rise time of the SDA signal

Fast mode 20 + 0.1 CB 300 ns

t10 Standard mode 300 ns tFDA, fall time of the SDA signal

Fast mode 20 + 0.1 CB 300 ns

t11 Standard mode 1000 ns tRCL, rise time of the SCL signal

Fast mode 20 + 0.1 CB 300 ns

t11A Standard mode 1000 ns tRCL1, rise time of the SCL signal after a repeated

Fast mode 20 + 0.1 CB 300 ns start condition and after an acknowledge bit

t12 Standard mode 300 ns tFCL, fall time of the SCL signal

Fast mode 20 + 0.1 CB 300 ns

tSP Fast mode 0 50 ns Pulse width of the suppressed spike

tPOWER-UP 6 ms Power-up and acquisition time

1 A device must provide a data hold time for SDA to bridge the undefined region of the SCL falling edge.

8711-002

SCL

SDA

S = START CONDITION

P = STOP CONDITIO N

P PS

Figure 2. 2-Wire Serial Interface Timing Diagram

AD7291 Data Sheet

Rev. B | Page 6 of 28

ABSOLUTE MAXIMUM RATINGS

Table 4.

Parameter Rating

VDD to GND1, GND −0.3 V to +5 V

VDRIVE to GND1, GND −0.3 V to +5 V

Analog Input Voltage to GND1 −0.3 V to +3 V

Digital Input Voltage to GND1 −0.3 V to VDRIVE + 0.3 V

Digital Output Voltage to GND1 −0.3 V to VDRIVE + 0.3 V

VREF to GND1 −0.3 V to +3 V

GND to GND1 −0.3 V to +0.3 V

Input Current to Any Pin Except Supplies1 ±10 mA

Operating Temperature Range −40°C to +125°C

Storage Temperature Range −65°C to +150°C

Junction Temperature 150°C

Pb-free Temperature, Soldering

Reflow 260(+0)°C

ESD 2 kV

1 Transient currents of up to 100 mA do not cause latch-up.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

THERMAL RESISTANCE

Table 5. Thermal Resistance

Package Type θJA θ

JC Unit

20-Lead LFCSP 52 6.5 °C/W

ESD CAUTION

Data Sheet AD7291

Rev. B | Page 7 of 28

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

SDA

SCL

AS1

ALERT

AS0

IN3

IN5

IN4

IN6

IN7

REF

GND1

CAP

GND

IN1

IN2

IN0

PD/RS

DRIVE

AD7291

TO P VI EW

(Not to Scale)

08711-003

NOTES

1. THE EXPOSED METAL PADDLE ON THE BOTTOM

OF THE LFCSP PACKAGE SHOULD BE SOLDERED

TO PCB GROUND FO R PROPER HEAT DISSIPATION

AND PERFORMANCE.

Figure 3. Pin Configuration

Table 6. Pin Function Descriptions

Pin No. Mnemonic Description

1 to 5,

18 to 20

VIN3, VIN4,

VIN5, VIN6,

VIN7, VIN0,

VIN1, VIN2

Analog Inputs. The AD7291 has eight single-ended analog inputs that are multiplexed into the on-chip track-and-

hold amplifier. Each input channel can accept analog inputs from 0 V to 2.5 V. Any unused input channels should

be connected to GND1 to avoid noise pickup.

6 GND1

Ground. Ground reference point for the internal reference circuitry on the AD7291. All analog input signals and

the external reference signals should be referred to this GND1 voltage. The GND1 pin should be connected to the

ground plane of a system. All ground pins should ideally be at the same potential and must not be more than 0.3 V

apart, even on a transient basis. The VREF pin should be decoupled to this ground pin via a 10 F decoupling

capacitor.

7 VREF Internal Reference/External Reference Supply. The nominal internal reference voltage of 2.5 V appears at this pin.

Provided the output is buffered, the on-chip reference can be taken from this pin and applied externally to the rest

of a system. Decoupling capacitors should be connected to this pin to decouple the reference buffer. For best

performance, it is recommended to use a 10 F decoupling capacitor on this pin to GND1. The internal reference

can be disabled and an external reference supplied to this pin if required. The input voltage range for the external

reference is 2.0 V to 2.5 V.

8 DCAP Decoupling Capacitor Pin. Decoupling capacitors (1 F recommended) are connected to this pin to decouple the

internal LDO.

9 GND Ground. Ground reference point for all analog and digital circuitry on the AD7291. The GND pin should be con-

nected to the ground plane of the system. All ground pins should ideally be at the same potential and must not be

more than 0.3 V apart, even on a transient basis. Both DCAP and VDD pins should be decoupled to this GND pin.

10 VDD Supply Voltage, 2.8 V to 3.6 V. This supply should be decoupled to GND with 10 F and 100 nF decoupling capacitors.

11, 13 AS0, AS1 Logic Input. Together, the logic state of these two inputs selects a unique I2C address for the AD7291. See Table 31

for details. The device address depends on the voltage applied to these pins.

12 ALERT

Digital Output. This pin acts as an out-of-range indicator and, if enabled, becomes active when the conversion

result violates the DATAHIGH or DATALOW register values. See the Limit Registers (0x04 to 0x1E) section.

14 SDA Digital Input/Output. Serial bus bidirectional data. This open-drain output requires a pull-up resistor. The output coding

is straight binary for the voltage channels and twos complement for the temperature sensor result.

15 SCL Digital Input. Serial I2C Bus Clock. This input requires a pull-up resistor. The data transfer rate in I2C mode is

compatible with both 100 kHz and 400 kHz operating modes.

16 VDRIVE Logic Power Supply Input. The voltage supplied at this pin determines the voltage at which the interface operates.

This pin should be decoupled to GND. The voltage range on this pin is 1.65 V to 3.6 V and may be less than the

voltage at VDD but should never exceed it by more than 0.3 V.

17 PD/RST Power-Down Pin. This pin places the part into a full power-down mode and enables power conservation when

operation is not required. This pin can be used to reset the device by toggling the pin low for a minimum of 1 ns and a

maximum of 100 ns. If the maximum time is exceeded, the part enters power-down mode. When placing the device in

full power-down mode, the analog inputs must be returned to 0 V.

EPAD EPAD Exposed Paddle. The exposed metal paddle on the bottom of the LFCSP package should be soldered to PCB

ground for proper functionality and heat dissipation.

AD7291 Data Sheet

Rev. B | Page 8 of 28

TYPICAL PERFORMANCE CHARACTERISTICS

1.0

–1.0

–0.8

–0.6

–0.4

–0.2

0.2

0.4

0.6

0.8

0 0.5 1.0 1.5 2.0 2.5 3.0

INL (LSB)

VREF (V )

08711-012

INL (POSITIVE)

INL (NEGATIVE)

TA = 25°C

DRIVE = 3V

DD = 3V

S = 22. 22 ksps

SCL = 400kHz

–20

–40

–60

–80

–100

–120 02k

= V

DRIVE

= 3V

= 22. 22k sps

SCL

= 400kHz

= 10kHz

SNR = 71.209

THD = – 81.66

4k 6k 8k 10k

AMP LIT UD E (dB)

FREQUENCY (Hz )

08711-009

Figure 4. Typical FFT

Figure 7. INL vs. External VREF

1.0

0.8

0.6

0.4

0.2

–1.0

–0.8

–0.6

–0.4

–0.2

0 500 1000 1500 2000 2500 3000 3500 4096

INL (LSB)

ADC CODE

08711-010

= 25°C

DRIVE

= 3V

REF

= 2. 5V

= 3V

= 22. 22k sps

SCL

= 400kHz

1.0

–1.0

–0.8

–0.6

–0.4

–0.2

0.2

0.4

0.6

0.8

0 0.5 1.0 1.5 2.0 2.5 3.0

DNL (L S B)

VREF (V )

08711-013

DNL (POSITIVE)

DNL (NEGAT IVE)

TA = 25°C

DRIVE = 3V

DD = 3V

S = 22. 22ksps

SCL = 400kHz

Figure 5. Typical ADC INL

Figure 8. DNL vs. External VREF

1.0

0.8

0.6

0.4

0.2

–1.0

–0.8

–0.6

–0.4

–0.2

0 500 1000 1500 2000 2500 3000 3500 4096

DNL (LSB)

ADC CODE

08711-011

= 25°C

DRIVE

= 3V

REF

= 2. 5V

= 3V

= 22. 22k sps

SCL

= 400kHz

11.7

11.6

11.5

11.4

11.3

11.2 0 0.5 1.0 1.5 2.0 2.5

EFFECT IVE NUM BER OF BITS

EXT ERNAL REFERENCE (V)

08711-035

Figure 6. Typical ADC DNL

Figure 9. Effective Number of Bits vs. VREF, fSCL = 400 kHz

Data Sheet AD7291

Rev. B | Page 9 of 28

0.5

1.0

1.5

2.0

2.5

3.0

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5

CURRENT LOAD (mA)

REF

(V)

= V

DRIVE

= 3V

08711-021

Figure 10. VREF vs. Reference Output Drive

0 20406080100

TEMPE

TURE RE ADING ( °C)

TIME ( S econ ds)

08711-014

Figure 11. Response to Thermal Shock from Room Temperature into 50°C

Stirred Oil

–110

–108

–106

–104

–102

–100

–98

–96

–94

–92

–

1k 10k 100k 1M 10M 100M

PSRR (dB)

RIPPLE FREQUENCY (Hz)

= 3V

DRIVE

= 3V

08711-061

Figure 12. PSRR vs. Supply Ripple Frequency Without Supply Decoupling

125

120

115

110

105

100

751 10 100 1k

NOISE

(kHz)

CHANNEL-TO- CHANNE L IS OLATI ON (d B)

08711-018

= V

DRIVE

= 3V

SCL

= 400kHz

Figure 13. Channel-to-Channel Isolation, fIN = 10 kHz

69 022.01.51.00.5

SINAD ( dB)

EXT E RNAL REFE RENCE ( V )

08711-036

DRIVE

= 3V

Figure 14. SINAD vs. Reference Voltage, fSCL = 400 kHz, fs = 22.22 kSPS

–2.0

–1.0

–1.5

–0.5

0.5

1.0

1.5

–40 –25 –10 5 20 35 50 65 80 95 110 125

TEMPERATURE (° C)

TEMPERATURE ERROR (°C)

08711-017

Figure 15. Temperature Accuracy at 3 V

AD7291 Data Sheet

Rev. B | Page 10 of 28

2.5

2.0

1.5

1.0

0.5

02.7 2.9 3.1 3.3 3.52.8 3.0 3.2 3.4 3.6

TOTAL CURRENT (µA)

08711-037

–40°C

+25°C

+85°C

+125°C

DRIVE

= 3V

9.0

8.9

8.8

8.7

8.6

8.5

8.4

8.3

8.2

8.1

8.00 60 120 180 240 300 360 420

SCL FREQUENCY (kHz)

POWER (mW)

08711-062

DRIVE

= 3V

Figure 16. Power vs. Throughput in Normal Mode Figure 17. Full Shutdown Current vs. Supply Voltage for Various

Temperatures

Data Sheet AD7291

Rev. B | Page 11 of 28

TERMINOLOGY

Signal-to-Noise and Distortion Ratio (SINAD)

The measured ratio of signal-to-noise and distortion at the

output of the ADC. The signal is the rms amplitude of the

fundamental. Noise is the sum of all nonfundamental signals

up to half the sampling frequency (fS/2), excluding dc. The

ratio is dependent on the number of quantization levels in the

digitization process; the more levels, the smaller the quantization

noise. The theoretical signal-to-noise and distortion ratio for

an ideal N-bit converter with a sine wave input is given by

Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB

Thus, the SINAD is 74 dB for an ideal 12-bit converter.

Total Harmonic Distortion (THD)

The ratio of the rms sum of harmonics to the fundamental. For

the AD7291, it is defined as

log20)dB( V

VVVVV

THD ++++

where:

V1 is the rms amplitude of the fundamental.

V2, V3, V4, V5, and V6 are the rms amplitudes of the second

through sixth harmonics.

Peak Harmonic or Spurious Noise

The ratio of the rms value of the next largest component in the

ADC output spectrum (up to fS/2 and excluding dc) to the rms

value of the fundamental. Typically, the value of this specification

is determined by the largest harmonic in the spectrum, but for

ADCs where the harmonics are buried in the noise floor, it is a

noise peak.

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa and

fb, any active device with nonlinearities creates distortion

products at sum and difference frequencies of mfa ± nfb, where

m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms

are those for which neither m nor n equals zero. For example,

second-order terms include (fa + fb) and (fa − fb), while third-

order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb).

The AD7291 is tested using the CCIF standard where two input

frequencies near the top end of the input bandwidth are used.

In this case, the second-order terms are usually distanced in

frequency from the original sine waves while the third-order

terms are usually at a frequency close to the input frequencies.

As a result, the second- and third-order terms are specified

separately. The calculation of intermodulation distortion is,

like the THD specification, the ratio of the rms sum of the

individual distortion products to the rms amplitude of the sum

of the fundamentals, expressed in dB.

Aperture Delay

The measured interval between the sampling clock’s leading

edge and the point at which the ADC takes the sample.

Aperture Jitter

This is the sample-to-sample variation in the effective point in

time at which the sample is taken.

Full-Power Bandwidth

The input frequency at which the amplitude of the recon-

structed fundamental is reduced by 0.1 dB or 3 dB for a

full-scale input.

Power Supply Rejection Ratio (PSRR)

PSRR is defined as the ratio of the power in the ADC output at

full-scale frequency, f, to the power of a 100 mV p-p sine wave

applied to the ADC VDD supply of frequency, fS. The frequency

of the input varies from 5 kHz to 25 MHz.

PSRR (dB) = 10 log(Pf/PfS)

where:

Pf is the power at frequency, f, in the ADC output.

PfS is the power at frequency, fS, in the ADC output.

Integral Nonlinearity

The maximum deviation from a straight line passing through

the endpoints of the ADC transfer function. The endpoints are

zero scale, a point 1 LSB below the first code transition, and full

scale, a point 1 LSB above the last code transition.

Differential Nonlinearity

The difference between the measured and the ideal 1 LSB

change between any two adjacent codes in the ADC.

Offset Error

The deviation of the first code transition (00…000) to

(00…001) from the ideal—that is, GND1 + 1 LSB.

Offset Error Match

The difference in offset error between any two channels.

Gain Error

The deviation of the last code transition (111…110) to

(111…111) from the ideal (that is, VREF − 1 LSB) after the offset

error has been adjusted out.

Gain Error Match

The difference in gain error between any two channels.

Track-and-Hold Acquisition Time

The track-and-hold amplifier returns to track mode at the end

of conversion. Track-and-hold acquisition time is the time

required for the output of the track-and-hold amplifier to reach

its final value, within ±1 LSB, after the end of conversion.

AD7291 Data Sheet

Rev. B | Page 12 of 28

CIRCUIT INFORMATION

The AD7291 includes an 8-channel multiplexer, an on-chip

track-and-hold amplifier, an analog-to-digital converter (ADC),

an on-chip oscillator, internal data registers, an internal tempera-

ture sensor, and an I2C-compatible serial interface, all housed in

a 20-lead LFCSP. This package offers considerable space-saving

advantages over alternative solutions. The part can be operated

from a single supply from 2.8 V to 3.6 V and offers 12 bits of

resolution. The AD7291 has eight single-ended input channels

and an on-chip ±12 ppm reference. The analog input range for

the AD7921 is 0 V to VREF. The AD7291 includes a high

accuracy band gap temperature sensor, which is monitored and

digitized by the 12-bit ADC to give a resolution of 0.25°C.

The AD7291 typically remains in a partial power-down state

while not converting. When supplies are first applied, the part

powers up in a partial power-down state. Power-up is initiated

prior to a conversion, and the device returns to partial power-

down mode when the conversion is complete. Conversions can

be initiated by using the autocycle mode or command mode

where wake-up and a conversion occur during a write address

function. When the conversion is complete, the AD7291 again

enters partial power-down mode.

In command mode at the beginning of a read, the AD7291

wakes up completely, that is, becomes fully functional and

completes the conversion while the address is being read out. In

autocylce mode, conversions occur at 50 µs intervals; that is, the

AD7291 exits partial power-down mode and powers up fully at

50 µs intervals. This automatic partial power-down feature

allows power saving between conversions. Any read or write

operation across the I2C interface can occur while the device is

in partial power-down mode.

CONVERTER OPERATION

The AD7291 is a 12-bit successive approximation ADC based

around a capacitive DAC. Figure 18 and Figure 19 show simpli-

fied schematics of the ADC during the acquisition and conversion

phase, respectively. The ADC comprises control logic, SAR,

and a capacitive DAC that are used to add and subtract fixed

amounts of charge from the sampling capacitor to bring the

comparator back into a balanced condition. Figure 18 shows the

acquisition phase. SW2 is closed and SW1 is in Position A, the

comparator is held in a balanced condition, and the sampling

capacitor acquires the signal on the selected VIN channel.

CONTROL

LOGIC

CAPACITIVE

DAC

SW1 SW2

GND1 COMPARATOR

08711-004

Figure 18. ADC Acquisition Phase

When the ADC starts a conversion (see Figure 19), SW2

opens and SW1 moves to Position B, causing the comparator

to become unbalanced. The control logic and the capacitive

DAC are used to add and subtract fixed amounts of charge to

bring the comparator back into a balanced condition. When the

comparator is rebalanced, the conversion is complete. The

control logic generates the ADC output code. Figure 21 shows

the transfer functions of the ADC.

CONTROL

LOGIC

CAPACITIVE

DACE

SW1 SW2

GND1 COMPARATOR

08711-005

Figure 19. ADC Conversion Phase

ANALOG INPUT

Figure 20 shows an equivalent circuit of the analog input struc-

ture of the AD7291. The two diodes, D1 and D2, provide ESD

protection for the analog inputs. Care must be taken to ensure

that the analog input signal never exceeds the internally generated

LDO voltage of 2.5 V (DCAP) by more than 300 mV. This causes

the diodes to become forward biased and start conducting

current into the substrate. The maximum current these diodes

can conduct without causing irreversible damage to the part is

10 mA. Capacitor C1, in Figure 20, is typically about 8 pF and

can primarily be attributed to pin capacitance. Resistor R1 is a

lumped component made up of the on resistance of a switch

(track-and-hold switch) and the on resistance of the input

multiplexer. The total resistance is typically about 155 .

Capacitor C2 is the ADC sampling capacitor and has a

capacitance of 34 pF typically.

8pF

34pF

D2 CONVERSION PHASE: SWITCH OPEN

TRACK PHASE: SWITCH CLOSED

CAP

(2.5

)

08711-006

Figure 20. Equivalent Analog Input Circuit

For ac applications, removing high frequency components

from the analog input signal is recommended by using an RC

low-pass filter on the relevant analog input pin. In applications

where harmonic distortion and signal-to-noise ratios are

critical, the analog input should be driven from a low imped-

ance source. Large source impedances significantly affect the

ac performance of the ADC. This may necessitate the use of

an input buffer amplifier. The choice of the op amp is a function

of the particular application performance criteria.

Data Sheet AD7291

Rev. B | Page 13 of 28

ADC TRANSFER FUNCTION

The output coding of the AD7291 is straight binary for the

analog input channel conversion results and twos complement

for the temperature conversion result. The designed code tran-

sitions occur at successive LSB values (that is, 1 LSB, 2 LSBs,

and so forth). The LSB size is VREF/4096 for the AD7291. The

ideal transfer characteristic for the AD7291 for straight binary

coding is shown in Figure 21.

111...111

111...110

111...000

011...111

000...010

000...001

000...000

1LS B = V

REF

/4096

ANALOG INP UT

NOTES

1. V

REF

IS 2.5V.

ADC CODE

REF

– 1LS B1LSB

08711-007

Figure 21. Straight Binary Transfer Characteristic

TEMPERATURE SENSOR OPERATION

The AD7291 contains one local temperature sensor. The on-chip,

band gap temperature sensor measures the temperature of the

AD7291 die.

The temperature sensor module on the AD7291 is based on the

three current principle (see Figure 22), where three currents are

passed through a diode and the forward voltage drop is

measured, allowing the temperature to be calculated free of

errors caused by series resistance.

I4 × I

INTERNAL

SENSE

TRANSISTOR

BIAS

DIODE

8 × I I

BIAS

OUT+

OUT–

TO ADC

08711-008

Figure 22. Top Level Structure of Internal Temperature Sensor

Each input integrates, in turn, over a period of several hundred

microseconds. This takes place continuously in the background,

leaving the user free to perform conversions on the other

channels. When integration is complete, a signal passes to the

control logic to initiate a conversion automatically.

If the ADC is in command mode and performing a voltage

conversion, the AD7291 waits for it to complete and then

initiates a temperature sensor conversion. If the ADC is not

performing voltage conversions, temperature conversions occur

at 5 ms intervals.

In autocycle mode, the conversion is inserted into an

appropriate place in the current sequence. If the ADC is idle,

the conversion takes place immediately. The TSENSE conversion

result register stores the result of the last conversion on the

temperature channel; this can be read at any time.

Theoretically, the temperature measuring circuit can measure

temperatures from −512°C to +511°C with a resolution of

0.25°C. However, temperatures outside TA (the specified tem-

perature range for the AD7291) are outside the guaranteed

operating temperature range of the device. The temperature

sensor is enabled by setting the TSENSE bit in the command

TEMPERATURE SENSOR AVERAGING

The AD7291 incorporates a temperature sensor averaging

feature to enhance the accuracy of the temperature measure-

ments. The temperature averaging feature is performed

continuously in the background provided the TSENSE bit

in the command register is enabled. The temperature is

measured each time a TSENSE conversion is performed and a

moving average method is used to determine the result in the

TSENSE average result register. The average result is given by the

following equation:

()

ResultCurrentResultAveragePreviousAVGTSENSE _

7+=

The average result is then available in the TSENSE average result

The first TSENSE conversion result given by the AD7291 after the

temperature sensor has been selected in the command register

(Bit D7) is the actual first TSENSE conversion result, and this

result remains valid until the next TSENSE conversion is

completed and the result register is updated.

AD7291 Data Sheet

Rev. B | Page 14 of 28

Temperature Value Format VDRIVE

One LSB of the ADC corresponds to 0.25°C. The temperature

reading from the ADC is stored in a 12-bit twos complement

format, to accommodate both positive and negative tempera-

ture measurements. Sample temperature values are listed in

Table 7 . The temperature conversion formulas are as follows:

VDRIVE controls the voltage at which the serial interface operates.

VDRIVE allows the ADC to easily interface to both 1.8 V and 3 V

processors. For example, if the AD7291 is operated with a VDD

of 3.3 V, the VDRIVE pin can be powered from a 1.8 V supply.

This enables the AD7291 to operate with a larger dynamic

range with a VDD of 3.3 V while still being able to interface to

1.8 V processors. Take care to ensure that VDRIVE does not

exceed VDD by more than 0.3 V (see the Absolute Maximum

Ratings section).

Positive Temperature = ADC Code/4

Negative Temperature = (4096 − ADC Code)/4

The previous formulae are for a VREF of 2.5 V only. If an

external reference is used, the temperature sensor requires an

external reference of between 2 V and 2.5 V for correct

operation. The temperature results (in Celsius) are calculated

using the following formula, where VEXT_REF is the value of the

external reference voltage.

THE INTERNAL OR EXTERNAL REFERENCE

The AD7291 can operate with either the internal 2.5 V on-chip

reference or an externally applied reference. The EXT_REF bit

in the command register is used to determine whether the

internal reference is used. If the EXT_REF bit is selected in the

command register, an external reference can be supplied

through the VREF pin. On power-up, the internal reference is

enabled. Suitable external reference sources for the AD7291

include AD780, AD1582, ADR431, REF193, and ADR391.

15.2733.109

_−

⎟

⎠

⎞

⎜

⎝

⎛+= ADCCode

VeTemperatur REFEXT

Table 7. Temperature Data Format

Temperature (°C) Digital Output

The internal reference circuitry consists of a 2.5 V band gap

reference and a reference buffer. When the AD7291 operates in

internal reference mode, the 2.5 V internal reference is available

at the VREF pin, which should be decoupled to GND1 using a

10 F capacitor. It is recommended that the internal reference

be buffered before applying it elsewhere in the system.

−40 1111 0110 0000

−25 1111 1001 1100

−10 1111 1101 1000

−0.25 1111 1111 1111

0 0000 0000 0000

+0.25 0000 0000 0001

+10 0000 0010 1000 The internal reference is capable of sourcing up to 2 mA of

current when the converter is static. The reference buffer

requires 5.5 ms to power up and charge the 10 F decoupling

capacitor during the power-up time.

+25 0000 0110 0100

+50 0000 1100 1000

+75 0001 0010 1100

+100 0001 1001 0000 RESET

+105 0001 1010 0100

The AD7291 includes a reset feature, which can be used to reset

the device and the content of all internal registers including the

command register to their default state. To activate the reset

operation, the PD/RST pin should be brought low for a

minimum of 1 ns and a maximum of 100 ns and be asynchronous

to the clock; therefore, it can be triggered at any time. If the PD/

RST pin is held low for greater than 100 ns, the part enters full

power-down mode. It is imperative that the PD/RST pin be held

at a stable logic level at all times to ensure normal operation.

+125 0001 1111 0100

Data Sheet AD7291

Rev. B | Page 15 of 28

INTERNAL REGISTER STRUCTURE

The AD7291 contains 34 internal registers (see Figure 23) that

are used to store conversion results, high and low conversion

limits, and information to configure and control the device.

There are 33 data registers and one address pointer register.

Each data register has an address that the address pointer

which registers are read, write, or read/write.

ADDRESS POINTER REGISTER

The address pointer register is the register to which the first

data byte of every write operation is written automatically;

therefore, this register does not have and does not require an

address. The address pointer register is an 8-bit register in

which the six LSBs are used as pointer bits to store an address

that points to one of the AD7291’s data registers. The first byte

following each write address is to the address pointer register,

containing the address of one of the data registers. The six LSBs

select the data register to which subsequent data bytes are

written. Only the six LSBs of this register are used to select a

data register. During power-up, the address pointer register

contains all 0s, pointing to the command register.

Table 8. Address Pointer Register

D1 D0 P5 P4 P3 P2 P1 P0

0 0 Register select

SDA

SCL

DATA

COMMAND

TSENSE CONV

RESULT REGIS TER

TSENSE AVG

RESULT REGIS TER

CH0 DATAHIGH

CH1 DATALOW

CH0 HYSTERES IS

CH1 DATAHIGH

CH1 HYSTERESIS

CH0 DATALOW

CH7 DATAHIGH

CH7 DATALOW

CH7 HYSTERES IS

TSENSE HYSTERESIS

TSENSE DATAHIGH

TSENSE DATALOW

ALERT ST ATUS

REGI STER A

ALERT ST ATUS

REGI STER B

08711-015

VOLT AGE CO NV

RESULT REGIS TER

SERI AL BUS I NTERF ACE

ADDRESS

POINTER

Figure 23. AD7291 Register Structure

AD7291 Data Sheet

Rev. B | Page 16 of 28

Table 9. AD7291 Register Addresses

Hex Code P5 P4 P3 P2 P1 P0 Registers Read/Write

0x00 0 0 0 0 0 0 Command register Write.

0x01 0 0 0 0 0 1 Voltage conversion result register Read.

0x02 0 0 0 0 1 0 TSENSE conversion result register Read.

0x03 0 0 0 0 1 1 TSENSE average result register Read.

0x04 0 0 0 1 0 0 CH0 DATAHIGH register Read/write.

0x05 0 0 0 1 0 1 CH0 DATALOW register Read/write.

0x06 0 0 0 1 1 0 CH0 hysteresis register Read/write.

0x07 0 0 0 1 1 1 CH1 DATAHIGH register Read/write.

0x08 0 0 1 0 0 0 CH1DATALOW register Read/write.

0x09 0 0 1 0 0 1 CH1 hysteresis register Read/write.

0x0A 0 0 1 0 1 0 CH2 DATAHIGH register Read/write.

0x0B 0 0 1 0 1 1 CH2 DATALOW register Read/write.

0x0C 0 0 1 1 0 0 CH2 hysteresis register Read/write.

0x0D 0 0 1 1 0 1 CH3 DATAHIGH register Read/write.

0x0E 0 0 1 1 1 0 CH3 DATALOW register Read/write.

0x0F 0 0 1 1 1 1 CH3 hysteresis register Read/write.

0x10 0 1 0 0 0 0 CH4 DATAHIGH register Read/write.

0x11 0 1 0 0 0 1 CH4 DATALOW register Read/write.

0x12 0 1 0 0 1 0 CH4 hysteresis register Read/write.

0x13 0 1 0 0 1 1 CH5 DATAHIGH register Read/write.

0x14 0 1 0 1 0 0 CH5 DATALOW register Read/write.

0x15 0 1 0 1 0 1 CH5 hysteresis register Read/write.

0x16 0 1 0 1 1 0 CH6 DATAHIGH register Read/write.

0x17 0 1 0 1 1 1 CH6 DATALOW register Read/write.

0x18 0 1 1 0 0 0 CH6 hysteresis register Read/write.

0x19 0 1 1 0 0 1 CH7 DATAHIGH register Read/write.

0x1A 0 1 1 0 1 0 CH7 DATALOW register Read/write.

0x1B 0 1 1 0 1 1 CH7 hysteresis register Read/write.

0x1C 0 1 1 1 0 0 TSENSE DATAHIGH register Read/write.

0x1D 0 1 1 1 0 1 TSENSE DATALOW register Read/write.

0x1E 0 1 1 1 1 0 TSENSE hysteresis register Read/write.

0x1F 0 1 1 1 1 1 Alert Status Register A Read.

0x20 1 0 0 0 0 0 Alert Status Register B Read.

0x3F 1 1 1 1 1 1 Factory test mode The user should not access this register.

Data Sheet AD7291

Rev. B | Page 17 of 28

COMMAND REGISTER (0x00)

The command register is a 16-bit write-only register that is used to set the operating modes of the AD7291. The bit functions are outlined

in Table 10. A two-byte write is necessary when writing to the command register. MSB denotes the first bit in the data stream. During

power-up, the default content of the command register is all 0s.

Table 10. Command Register Bits and Default Settings at Power-Up

MSB LSB

Channel Bit D15 to DB8 D7 D6 D5 D4 D3 D2 D1 D0

Function CH0 to CH7 TSENSE Don’t

care

Noise-delayed

bit trial and

sampling

EXT_REF Polarity of ALERT

pin (active high/

active low)

Clear alert RESET Autocycle

mode

Setting Enable = 1

Disable = 0

Enable = 1

Disable = 0

0 Enable = 1

Disable = 0

Enable = 1

Disable = 0

Active low = 1

Active high = 0

Enable = 1

Disable = 0

Enable = 1

Disable = 0

Enable = 1

Disable = 0

Table 11. Command Register Bit Function Descriptions

Bit Mnemonic Comment

D15 to D8 CH0 to CH7 These 8-channel address bits select the analog input channel(s) to be converted. A 1 in any of Bit D15 to

Bit D8 selects a channel for conversion. If more than one channel bit is set to 1, the AD7291 sequences

through the selected channels, starting with the lowest channel. All unused channels should be set to 0. A

channel or sequence of channels for conversion must be selected in the command register, prior to initiating

a conversion.

D7 TSENSE

This bit enables temperature conversions, which occur in the background at 5 ms intervals. The results can be

read from the TSENSE conversion result register (0x02) and the TSENSE average result register (0x03). For details,

refer to the Temperature Sensor Operation section.

D6 Don’t care

D5 Noise-

delayed bit

trial and

sampling

When this function is enabled, it delays the critical sampling intervals and bit trials when there is activity on

the I2C bus, thus ensuring improved dc performance of the AD7291. When this feature is enabled, the

conversion time may vary. This bit is disabled on power-up, and it is recommended to write a 1 to enable this

feature for normal operation.

D4 EXT_REF

Writing a Logic 1 to this bit enables the use of an external reference. The input voltage range for the external

reference is 2 V to 2.5 V. The external reference should not exceed 2.5 V or the device performance will be

adversely affected. During power-up, the default configuration has the internal reference enabled.

D3 Polarity of

ALERT pin

This bit determines the active polarity of the ALERT pin. The ALERT pin is configured for active low operation

if this bit is set to 1 and active high if this bit is set to 0. The default configuration on power-up is active high (0).

D2 Clear alert

This bit clears the content of the alert status register. Once the content of both alert status registers is cleared,

this bit should be reprogrammed to a Logic 0 to ensure that future alerts are detected.

D1 RESET Setting this bit resets the contents of all internal registers in the AD7291 to their default states including the

command register itself. This bit is automatically returned to 0 once the reset is completed to enable the

internal registers to be reprogrammed.

D0 Autocycle

mode

Writing a 1 to this bit enables the autocycle mode of operation. In this mode, the channels selected in Bit D15

to Bit D8 are continuously converted by the AD7291. This function is used in conjunction with the limit

registers, which can be programmed to issue an alert if the conversion result exceeds the preset limit for any

channel selected for conversion.

AD7291 Data Sheet

Rev. B | Page 18 of 28

Table 12. Channel Selection Bits for Command Register

D15 D14 D13 D12 D11 D10 D9 D8 Selected Analog Input Channel Comments

0 0 0 0 0 0 0 0 No channel selected

0 0 0 0 0 0 0 1 Convert on Channel 7 (VIN7)

0 0 0 0 0 0 1 0 Convert on Channel 6 (VIN6)

0 0 0 0 0 1 0 0 Convert on Channel 5 (VIN5)

0 0 0 0 1 0 0 0 Convert on Channel 4 (VIN4)

0 0 0 1 0 0 0 0 Convert on Channel 3 (VIN3)

0 0 1 0 0 0 0 0 Convert on Channel 2 (VIN2)

0 1 0 0 0 0 0 0 Convert on Channel 1 (VIN1)

1 0 0 0 0 0 0 0 Convert on Channel 0 (VIN0)

If more than one channel is

selected, the AD7291 converts the

selected channels starting with the

lowest channel in the sequence.

Table 13. TSENSE Data Format

Input D11 (MSB) D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 (LSB)

Value (°C) −512 +256 +128 +64 +32 +16 +8 +4 +2 +1 +0.5 +0.25

Sample Delay and Bit Trial Delay

Ideally, no I2C bus activity should occur while an ADC

conversion is taking place. However, this may not be possible,

for example, when operating in autocycle mode. It is therefore

recommended to enable the noise delayed bit trial and sampling

function by writing a 1 to Bit D5 in the command register. This

mechanism delays critical sample intervals and bit trials while

there is activity on the I2C bus. This results in a quiet period for

each bit decision, and conversion results are less susceptible to

interference from external noise.

On power-up, the bit trial and sample interval delay mechanism

is not enabled. It is recommended that this feature should be

enabled for normal operation. When enabled, the AD7291

delays the bit trials, mitigating against the effect of activity on

the I2C bus. In cases where there is excessive activity on the

interface lines, enabling these bits may cause the overall

conversion time to increase.

The AD7291 also incorporates functionality that allows it to

reject glitches shorter than 50 ns. This feature improves the

noise susceptibility of the device.

VOLTAGE CONVERSION RESULT REGISTER (0x01)

The voltage conversion result register is a 16-bit read-only

straight binary format. A 2-byte read is necessary to read data

from this register. Table 14 and Tabl e 15 show the contents of

the first and second bytes of data to be read from the AD7291.

Each AD7291 conversion result consists of four channel address

bits (see Table 14 and Table 15) and the 12-bit data result.

Bit D15 to Bit D12 are the channel address bits that identify

the ADC channel that corresponds to the subsequent result.

Bit D11 to Bit D0 contain the most recent ADC result.

Table 14. Conversion Value Register (First Read)

MSB

D15 D14 D13 D12 D11 D10 D9 D8

ADD3 ADD2 ADD1 ADD0 B11 B10 B9 B8

Table 15. Conversion Value Register (Second Read)

LSB

D7 D6 D5 D4 D3 D2 D1 D0

B7 B6 B5 B4 B3 B2 B1 B0

Table 16. Channel Address Bits for the Result Register

ADD2 ADD2 ADD1 ADD0 Analog Input Channel

0 0 0 0 VIN0

0 0 0 1 VIN1

0 0 1 0 VIN2

0 0 1 1 VIN3

0 1 0 0 VIN4

0 1 0 1 VIN5

0 1 1 0 VIN6

0 1 1 1 VIN7

1 0 0 0 TSENSE

1 0 0 1 TSENSE average result

Temperature Value Format

The temperature reading from the ADC is stored in an 11-bit

twos complement format, D11 to D0, to accommodate both

positive and negative temperature measurements. The tem-

perature data format is provided in Table 1 3 .

TSENSE CONVERSION RESULT REGISTER (0x02)

The TSENSE result register is a 16-bit read-only register used to

store the ADC data generated from the internal temperature

sensor. This register stores the temperature readings from the

ADC in a 12-bit twos complement format, D11 to D0, and

uses Bit D15 to Bit D12 to store the channel address bits.

Conversions take place approximately every 5 ms. Table 13

details the temperature data format that applies to the internal

temperature sensor.

Data Sheet AD7291

Rev. B | Page 19 of 28

Table 17. TSENSE Conversion Result Register (First Read)

MSB

D15 D14 D13 D12 D11 D10 D9 D8

ADD3 ADD2 ADD1 ADD0 B11 B10 B9 B8

Table 18. TSENSE Result Register (Second Read)

LSB

D7 D6 D5 D4 D3 D2 D1 D0

B7 B6 B5 B4 B3 B2 B1 B0

TSENSE AVERAGE RESULT REGISTER (0x03)

The TSENSE average result register is a 16-bit read-only register

used to store the average result from the internal temperature

sensor. This register stores the average temperature readings

from the ADC in an 11-bit twos complement format, D11 to

D0, and uses Bit D15 to Bit D12 to store the channel address

bits. The TSENSE average result register is updated after every

TSENSE conversion is completed. The first TSENSE average

conversion result given by the AD7291 after averaging is

enabled is the actual first TSENSE conversion result. Table 13

details the temperature data format, which applies to the

internal temperature sensor. See the Temperature Sensor

Averaging section for more details.

Table 19. TSENSE Average Result Register (First Read)

MSB

D15 D14 D13 D12 D11 D10 D9 D8

ADD3 ADD2 ADD1 ADD0 B11 B10 B9 B8

Table 20. TSENSE Average Result Register (Second Read)

LSB

D7 D6 D5 D4 D3 D2 D1 D0

B7 B6 B5 B4 B3 B2 B1 B0

LIMIT REGISTERS (0x04 TO 0x1E)

The AD7291 has nine pairs of limit registers. Each pair stores

high and low conversion limits for each analog input channel

and the internal temperature sensor. Each pair of limit registers

has one associated hysteresis register. All 27 registers are 16 bits

wide; only the 12 LSBs of the registers are used for the AD7291.

The four MSBs, D15 and D12, in these registers should contain

0s. During power-up, the contents of the DATAHIGH register for

each analog voltage channel is full scale (0x0FFF), while the

default contents of the DATALOW voltage channels registers is

zero scale (0x0000). The output coding of the AD7291 is twos

complement for the temperature conversion result. The default

content for the TSENSE DATAHIGH register is 0x07FF, while the

default content of the TSENSE DATALOW register is 0x0800. The

AD7291 signals an alert in hardware if the conversion result

moves outside the upper or lower limit set by the limit registers.

DATAHIGH Register

The DATAHIGH registers for CH0 to CH7 and the internal

temperature sensor are 16-bit read/write registers; only the

12 LSBs of each register are used. Bit D15 to Bit D12 are not

used in the register and are set to 0s. This register stores the

upper limit that activates the ALERT output. If the value in the

conversion result register is greater than the value in the

DATAHIGH register, an ALERT occurs for that channel. When

the conversion result returns to a value at least N LSBs below

the DATAHIGH register value, the ALERT output pin is reset. The

value of N is taken from the hysteresis register associated with

that channel. The ALERT pin can also be reset by writing to

Bit D2 in the command register.

Table 21. DATAHIGH Register (First Read/Write)

MSB

D15 D14 D13 D12 D11 D10 D9 D8

0 0 0 0 B11 B10 B9 B8

Table 22. DATAHIGH Register (Second Read/Write)

LSB

D7 D6 D5 D4 D3 D2 D1 D0

B7 B6 B5 B4 B3 B2 B1 B0

DATALOW Register

The DATALOW register for each channel is a 16-bit read/write

Bit D12 are not used in the register and are set to 0s. The

If the value in the TSENSE conversion result register is less than

the value in the DATALOW register, an ALERT occurs for that

channel. When the conversion result returns to a value at least

N LSBs above the DATALOW register value, the ALERT output

pin is reset. The value of N is taken from the hysteresis register

associated with that channel. The ALERT output pin can also be

reset by writing to Bit D2 in the command register.

Table 23. DATALOW Register (First Read/Write)

MSB

D15 D14 D13 D12 D11 D10 D9 D8

0 0 0 0 B11 B10 B9 B8

Table 24. DATALOW Register (Second Read/Write)

LSB

D7 D6 D5 D4 D3 D2 D1 D0

B7 B6 B5 B4 B3 B2 B1 B0

AD7291 Data Sheet

Rev. B | Page 20 of 28

HYSTERESIS REGISTER

Each analog input channel and the internal temperature sensor

has its own hysteresis register, which is a 16-bit read/write

used in the register and are set to 0s. The hysteresis register

stores the hysteresis value, N, when using the limit registers.

Each pair of limit registers has a dedicated hysteresis register.

The hysteresis value determines the reset point for the ALERT

pin if a violation of the limits occurs. For example, if a hysteresis

value of eight LSBs is required on the upper and lower limits of

Channel 0, the 16-bit word, 0000 0000 0000 1000, should be

written to the hysteresis register of CH0, the address of which

is 0x06 (see Table 25 and Table 26). During power-up, the

hysteresis registers content defaults to all zeros (0x0000). If a

hysteresis value is required, that value must be written to the

hysteresis register for the channel in question.

Table 25. Hysteresis Register (First Read/Write Byte)

MSB

D15 D14 D13 D12 D11 D10 D9 D8

0 0 0 0 B11 B10 B9 B8

Table 26. Hysteresis Register (Second Read/Write Byte)

LSB

D7 D6 D5 D4 D3 D2 D1 D0

B7 B6 B5 B4 B3 B2 B1 B0

ALERT STATUS REGISTER A AND ALERT STATUS

The alert status registers are 16-bit, read-only registers that

provide information on an alert event. If a conversion result

activates the ALERT pin, as described in the Limit Registers

(0x04 to 0x1E) section, the alert status register can be read to

gain further information. There are two alert status registers in

the AD7291; Alert Status Register A, which stores alerts for the

analog voltage conversion channels (see Table 27 and Table 28)

and Alert Status Register B, which stores alerts for the internal

temperature sensor only (see Table 29 and Table 30).

Both alert status registers contain two status bits per channel,

one corresponding to the DATAHIGH limit and the other to the

DATALOW limit. The bit with a status of 1 shows where the

violation occurred—that is, on which channel—and whether

the violation occurred on the upper or lower limit. If a second

alert event occurs on the other channel between receiving the

first alert and interrogating the alert status register, the corres-

ponding bit for that alert event is also set. The entire contents

of the alert status register can be cleared by writing 1 to Bit D2

in the command register.

For example, if Bit D14 in Alert Status Register A is set to 1, the

lower limit on Channel 7 (Register 0x1A) has been violated,

while if Bit D11 is set 1, the upper limit on Channel 5 has been

violated (Register 0x13).

The TSENSEHIGH and TSENSE_AVGHIGH alerts are determined

by comparison with the TSENSE DATAHIGH register (Register

0x1C). Likewise, the TSENSELOW and TSENSE_AVGLOW alerts

are determined by comparison with the TSENSE DATALOW register

(Register 0x1D).

Table 27. Alert Status Register A (First Read Byte)

D15 D14 D13 D12 D11 D10 D9 D8

CH7HIGH CH7LOW CH6HIGH CH6LOW CH5HIGH CH5LOW CH4HIGH CH4LOW

Table 28. Alert Status Register A (Second Read Byte)

D7 D6 D5 D4 D3 D2 D1 D0

CH3HIGH CH3LOW CH2HIGH CH2LOW CH1HIGH CH1LOW CH0HIGH CH0LOW

Table 29. Alert Status Register B (First Read Byte)

D15 D14 D13 D12 D11 D10 D9 D8

0 0 0 0 0 0 0 0

Table 30. Alert Status Register B (Second Read Byte)

D7 D6 D5 D4 D3 D2 D1 D0

0 0 0 0 TSENSE_AVGHIGH TSENSE_AVGLOW TSENSEHIGH TSENSELOW

Data Sheet AD7291

Rev. B | Page 21 of 28

I2C INTERFACE

Control of the AD7291 is carried out via the I2C compatible

serial bus. The AD7291 is connected to this bus as a slave device

under the control of a master device such as the processor.

SERIAL BUS ADDRESS BYTE

The first byte the user writes to the device is the slave address

byte. Similar to all I2C-compatible devices, the AD7291 has a

7-bit serial address. The three MSBs of this address are set to

010. The four LSBs are user-programmable by the three-state

input pins, AS0 and AS1, as shown in Table 31.

In Table 31, H means tie the pin to VDRIVE, L means tie the pin

to GND, and NC refers to a pin left floating. Note that in this

final case, the stray capacitance on the pin must be less than

30 pF to allow correct detection of the floating state; therefore,

any PCB trace must be kept as short as possible.

Table 31. Slave Address Control Using Three-State Input Pins

Slave Address (A6 to A0)

AS1 AS0 Binary Hex

H H 010 0000 0x20

H NC 010 0010 0x22

H L 010 0011 0x23

NC H 010 1000 0x28

NC NC 010 1010 0x2A

NC L 010 1011 0x2B

L H 010 1100 0x2C

L NC 010 1110 0x2E

L L 010 1111 0x2F

GENERAL I2C TIMING

Figure 24 shows the timing diagram for general read and write

operations using an I2C-compliant interface.

When no device is driving the bus, both SCL and SDA are high.

This is known as the idle state. When the bus is idle, the master

initiates a data transfer by establishing a start condition, defined

as a high-to-low transition on the serial data line (SDA) while

the serial clock line (SCL) remains high. This indicates that a

data stream follows. The master device is responsible for

generating the clock.

Data is sent over the serial bus in groups of nine bits—eight bits

of data from the transmitter followed by an acknowledge bit

(ACK) from the receiver. Data transitions on the SDA line must

occur during the low period of the clock signal and remain

stable during the high period. The receiver should pull the SDA

line low during the acknowledge bit to signal that the preceding

byte has been received correctly. If this is not the case, cancel

the transaction.

The first byte that the master sends must consist of a 7-bit slave

address, followed by a data direction bit. Each device on the

bus has a unique slave address; therefore, the first byte sets up

communication with a single slave device for the duration of the

transaction.

The transaction can be used either to write to a slave device

(data direction bit = 0) or to read data from it (data direction

bit = 1). In the case of a read transaction, it is often necessary

first to write to the slave device (in a separate write transaction)

to tell it from which register to read. Reading and writing

cannot be combined in one transaction.

When the transaction is complete, the master can keep control

of the bus, initiating a new transaction by generating another

start bit (high-to-low transition on SDA while SCL is high).

This is known as a repeated start (SR). Alternatively, the bus

can be relinquished by releasing the SCL line followed by the

SDA line. This low-to-high transition on SDA while SCL is high

is known as a stop bit (P), and it leaves the I2C bus in its idle

state (no current is consumed by the bus).

The example in Figure 24 shows a simple write transaction

with an AD7291 as the slave device. In this example, the

AD7291 register pointer is being set up for a future read

transaction.

P7 P6 P5 P4 P3 P2 P1 P0

ST ART COND

BY MASTER ACK. BY

AD7291

SLAV E ADDRES S BYT E ACK. BY

AD7291

SCL

REGI S T E R ADDRESS STO P BY

MASTER

USER PROGRAMMABLE 5 LSBs

R/W

A6 A5 A4 A3 A2 A1 A0

8711-040

Figure 24. General I2C Timing

AD7291 Data Sheet

Rev. B | Page 22 of 28

WRITING TO THE AD7291

WRITING TWO BYTES OF DATA TO A 16-BIT

All registers on the AD7921 are 16-bit registers; therefore, two

bytes of data are required to write a value to any one of these

registers. Writing two bytes of data to a register consists of the

following sequence (see Figure 25):

1. The master device asserts a start condition on SDA.

2. The master sends the 7-bit slave address followed by the

write bit (low).

3. The addressed slave device asserts an acknowledge on SDA.

4. The master sends a register address. The slave asserts an

acknowledge on SDA.

5. The master sends the first data byte (most significant).

6. The slave asserts an acknowledge on SDA.

7. The master sends the second data byte (least significant).

8. The slave asserts an acknowledge on SDA.

9. The master asserts a stop condition on SDA to end the

transaction.

WRITING TO MULTIPLE REGISTERS

Writing to multiple address registers consists of the following

steps (see Figure 26):

1. The master device asserts a start condition on SDA.

2. The master sends the 7-bit slave address followed by

the write bit (low).

3. The addressed slave device (AD7291) asserts an

acknowledge on SDA.

4. The master sends a register address, for example, the CH1

DATAHIGH register address.

5. The slave (AD7291) asserts an acknowledge on SDA.

6. The master sends the first data byte.

7. The slave (AD7291) asserts an acknowledge on SDA.

8. The master sends the second data byte.

9. The slave (AD7291) asserts an acknowledge on SDA.

10. The master sends a second register address, for example,

the command register.

11. The slave (AD7291) asserts an acknowledge on SDA.

12. The master sends the first data byte.

13. The slave (AD7291) asserts an acknowledge on SDA.

14. The master sends the second data byte.

15. The slave (AD7291) asserts an acknowledge on SDA.

16. The master asserts a stop condition on SDA to end the

transaction.

The previous example details writing to two registers only (the

CH1 DATAHIGH register address and the command register).

However, the AD7291 can read from multiple registers in one

write operation as shown in Figure 26.

8711-059

SSLAVE ADDRESS 0SA REG PO INTE R SA DATA[15:8] SA PDATA[7:0] SA

FROM MASTER TO SLAVE

FROM SLAVE TO MASTER

S = START CONDIT IO N

SR = REP E ATED START

P = STO P CONDITION

SA = SLAVE ACKNO WLEDGE

A = NOT ACKNOWLE DGE

Figure 25. Writing Two Bytes of Data to a 16-Bit Register

08711-019

...

0SA SASLAV E ADDRES S P OINT T O CH1 DATA

HIGH

REG ( 0x04)

PSASASA DATA[7:0]DATA[15:8]

PO INT T O CO M M AND RE G (0x00)

DATA[15:8] SA SADATA[7:0]

FROM MASTER TO SLAVE

FROM SLAVE TO MASTER

S = START CONDITI ON

SR = REPEATED START

P = STO P CONDITION

SA = SLAVE ACKNOWLEDG E

A = NO T ACKNO WLE DGE

Figure 26. Writing to Multiple Registers

Data Sheet AD7291

Rev. B | Page 23 of 28

READING DATA FROM THE AD7291

READING TWO BYTES OF DATA FROM A 16-BIT

Reading the contents from any of the 16-bit registers is a 2-byte

read operation. In this protocol, the first part of the transaction

writes to the register pointer. When the register address has

been set up, any number of reads can be performed from that

particular register without having to write to the address

pointer register again. When the required number of reads

is completed, the master should not acknowledge the final

byte. This tells the slave to stop transmitting, allowing a stop

condition to be asserted by the master. Further reads from

this register can be performed in a future transaction without

having to rewrite to the register pointer.

If a read from a different address is required, the relevant

and, again, any number of reads from this register can then be

performed. In the following example, the master device reads

three lots of 2-byte data from a slave device but as many lots

consisting of two bytes can be read as required. This protocol

assumes that the particular register address has been set up by

a single-byte write operation to the address pointer register.

Reading two bytes of data from a 16-bit register consists of the

following sequence (see Figure 27):

1. The master device asserts a start condition on SDA.

2. The master sends the 7-bit slave address followed by the

read bit (high).

3. The addressed slave device asserts an acknowledge on SDA.

4. The master receives a data byte.

5. The master asserts an acknowledge on SDA.

6. The master receives a second data byte.

7. The master asserts an acknowledge on SDA.

8. The master receives a data byte.

9. The master asserts an acknowledge on SDA.

10. The master receives a second data byte.

11. The master asserts an acknowledge on SDA.

12. The master receives a data byte.

13. The master asserts an acknowledge on SDA.

14. The master receives a second data byte.

15. The master asserts a not acknowledge on SDA to notify the

slave that the data transfer is complete.

16. The master asserts a stop condition on SDA to end the

transaction.

08711-060

S A

...

1 A

AAA

SLAVE ADDRESS

DATA[7:0]

DATA[7:0] DATA[7:0]

DATA[15:8]

DATA[15:8] DATA[15:8]

FROM MASTER TO SLAVE

FROM SLAVE TO MASTER

S = START CONDITI ON

SR = REPEATED START

P = STO P CONDITION

A = ACKNOWL EDGE

A = NO T ACKNO WLE DGE

Figure 27. Reading Three Lots of Two Bytes of Data from the Conversion Result Register

AD7291 Data Sheet

Rev. B | Page 24 of 28

MODES OF OPERATION

When supplies are first applied to the AD7291, the ADC

powers up in partial power-down mode and normally remains

in this partial power-down state while not converting. Once

the master addresses the AD7291, it exits partial power-down.

There are two methods of initiating a conversion on the

AD7291: command mode and autocycle mode.

COMMAND MODE

In command mode, the AD7291 converts on demand on either

a single channel or a sequence of channels. Writing in the

command register puts the part into command mode. This is

the default mode of operation and allows a conversion to be

automatically selected any time a write operation occurs to the

command register. To enter this mode, the required combina-

tion of channels is written into the command register (Register

0x00). Following the write operation, the AD7291 must be

addressed again to indicate that a read operation is required.

The read then takes place from the voltage or temperature

conversion result register. For the first conversion to occur,

the address pointer written to the AD7291 must point to the

voltage conversion result register or TSENSE conversion result

channel address bits are read. The next conversion in the

sequence takes place once the next read from the result

acquisition and conversion times combined take approximately

4.45 µs (1.25 µs acquisition time plus 3.2 µs conversion time).

When in command mode, the part cycles through the selected

channels from the lowest selected channel in the sequence to

the next lowest until all the channels in the sequence are

converted.

To exit the command mode, the master should not acknowledge

the final byte of data. This stops the AD7291 transmitting,

allowing the master to assert a stop condition on the bus. On

the receipt of a stop condition, the AD7291 stops converting

and enters partial power-down mode, but the content of the

command register is preserved. Once the part is readdressed

and a read is initiated from the voltage conversion register, the

AD7291 begins converting on the previously selected sequence

of channels. The conversion sequence starts converting the

first selected channel in the sequence; that is, if Channel 1,

Channel 2, and Channel 3 are selected and a stop condition

occurs after the Channel 1 result is read, on resumption of

conversions, Channel 1 is reconverted and the conversion

sequence continues.

Data Sheet AD7291

Rev. B | Page 25 of 28

The example in Figure 28 shows the command mode convert-

ing on a sequence of channels including VIN0, VIN1, and VIN2.

1. The master device asserts a start condition on SDA.

2. The master sends the 7-bit slave address followed by the

write bit (low).

3. The addressed slave device (AD7291) asserts an

acknowledge on SDA.

4. The master sends the command register address (0x00).

5. The slave asserts an acknowledge on SDA.

6. The master sends the first data byte (0xE0) to the command

7. The slave asserts an acknowledge on SDA.

8. The master sends the second data byte (0x20) to the com-

mand register.

9. The slave asserts an acknowledge on SDA.

10. The master sends the result register address (0x01).

11. The slave asserts an acknowledge on SDA.

12. The master sends the 7-bit slave address followed by the

write bit (high).

13. The slave (AD7291) asserts an acknowledge on SDA.

14. The master receives a data byte, which contains the

channel address bits and the four MSBs of the converted

result for Channel VIN0.

15. The master then asserts an acknowledge on SDA.

16. The master receives the second data byte, which contains

the eight LSBs of the converted result for Channel VIN0. The

master then asserts on acknowledge on SDA.

17. Step 11 and Step 12 repeat for Channel VIN1 and

Channel VIN2.

18. Once the master has received the results from all the

selected channels, the slave again converts and outputs

the result for the first channel in the selected sequence.

Step 12 to Step 14 are repeated.

19. The master asserts a not acknowledge on SDA and a stop

condition on SDA to end the conversion and exit

command mode.

To change the conversion sequence, rewrite a new sequence to

the command mode. If a new write to the command register is

performed while an existing conversion sequence is underway,

the existing conversion sequence is terminated and the next

conversion performed is the first selected channel from the new

sequence. The maximum throughput that can be achieved using

this mode with a 400 kHz I2C clock is (400 kHz/18) = 22.2 kSPS.

08711-016

SSA

...

0SA SA SACOMMAND = 0xE0 COMMAND = 0x20

IN0

[11:8]

POINT TO RESULT REG (0x01) SR 1SASA CH AD (0000)

...

IN2

[11:8]

A A

...

IN0

[7:0]

... ........

= POSITION OF SAMPLING START

SLAVE ADDRESS

POINT TO COMMAND REG (0x00)

IN0

[7:0] ACH AD (0001) A

...

IN1

[7:0]V

IN1

[11:8]

IN0

[11:8]

SLAVE ADDRESS

IN2

[7:0]

IN2

[7:0]

CH AD (0010) CH ID (0000)

FROM MASTER TO SLAVE

FROM SLAVE TO MASTER

S = START CONDITION

SR = REPEATED START

P = STOP CONDITION

SA = SLAVE ACKNOWLEDGE

A = NOT ACKNOWLEDGE

Figure 28. Command Mode Operation

AD7291 Data Sheet

Rev. B | Page 26 of 28

AUTOCYCLE MODE

The AD7291 can be configured to convert continuously on a

programmable sequence of channels, making it the ideal mode

of operation for system monitoring. This mode is useful for

monitoring signals, such as battery voltage and temperature,

alerting only when the limits are violated.

Conversions take place in the background approximately every

50 µs, and are transparent to the master. The acquisition and

conversion times combined for any channel take approximately

3.6 µs. Typically, this mode is used to automatically monitor a

selection of channels with either the limit registers programmed

to signal an out-of-range condition via the alert function or the

minimum/maximum recorders tracking the variation over time

of a particular channel. Reads and writes can be performed at

any time (the ADC voltage conversion result register, Register

0x01, contains the most recent conversion result).

During power-up, this mode is disabled. To enable this mode,

write to Bit D0 in the command register (Register 0x00) and

select the desired channels for conversion by writing to the

corresponding channel bits (Bit D15 to Bit D8). If more than

one channel bit is set in the configuration register, the ADC

automatically cycles through the channel sequence starting with

the lowest channel and working its way up through the sequence.

Once the sequence is complete, the ADC starts converting on

the lowest channel again, continuing to loop through the

sequence until this mode is exited. Once a conversion is

completed, the conversion result is compared with the content

of the limit registers, and alert status registers are automatically

updated. If a violation of the limit registers is found, the ALERT

pin is asserted with the polarity determined by Bit D3 in the

command register.

If a command mode conversion is required while the autocycle

mode is active, it is necessary to disable the autocycle mode

before proceeding to the command mode. This is achieved

by setting Bit D0 of the command register to 1. When the

command mode conversion is complete, the user can reenable

autocycle mode by setting Bit D0 to 1 in the command register.

In autocycle mode, the AD7291 does not enter partial power-

down on receipt of a stop condition; therefore, conversions and

alert monitoring continue to function.

Data Sheet AD7291

Rev. B | Page 27 of 28

OUTLINE DIMENSIONS

0.50

BSC

0.50

0.40

0.30

0.25

0.18

COMPLIANT

JEDEC STANDARDS MO-220- WG GD.

020509-B

BOTTO M VIEWTO P VI EW

EXPOSED

PAD

PIN 1

INDICATOR

4.10

4.00 S Q

3.90

SEATING

PLANE

0.80

0.75

0.70 0.05 MAX

0.02 NOM

0.20 REF

0.25 M IN

COPLANARITY

0.08

PIN 1

INDI

ATOR

2.75

2.60 SQ

2.35

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE P IN CONFIGURATION AND

FUNCT ION DE S CRIPT IONS

SECT ION OF T HIS DAT A SHEET.

1516

Figure 29. 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

4 mm × 4 mm Body, Very Very Thin Quad

(CP-20-8)

Dimensions shown in millimeters

ORDERING GUIDE

Model1 Temperature Range Package Description Package Option

AD7291BCPZ −40°C to +125°C 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-20-8

AD7291BCPZ-RL7 −40°C to +125°C 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-20-8

EVAL-AD7291SDZ Evaluation Board

1 Z = RoHS Compliant Part.

AD7291 Data Sheet

Rev. B | Page 28 of 28

NOTES

I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

registered trademarks are the property of their respective owners.

D08711-0-10/11(B)