S6BT112A01/S6BT112A02 ASSP CXPI Transceiver IC for Automotive Network The S6BT112A01 and S66BT112A02 are integrated transceiver ICs for automotive communication network with Clock Extension Peripheral Interface (CXPI). It has a flexible bit rate ranging from 2.4 Kbps to 20 Kbps and is JASO CXPI compliant. This CXPI transceiver IC connects the CXPI data link controller and the CXPI Bus line, and enables direct connection to the vehicle battery with a high surge protection. Additionally, these devices have an optional Spread Spectrum Clock Generator (SSCG) function. During Sleep mode, S6BT112A01 and S6BT112A02 reduce power consumption. The Cypress CXPI transceiver IC supports master node and slave node as selected SELMS pins. Features Compliant with the JASO CXPI (JASO D 015-3-15) standard Overtemperature protection Compliant with the SAE CXPI ( J3076_201510) standard Low-voltage detection. Supports 2.4 Kbps to 20 Kbps bitrate Supports Sleep and Wakeup modes Waveshaping for low Electromagnetic Interference (EMI) Sleep mode current: 6 A (typical at Slave) Operating voltage range: 5.3 V to 18 V Halogen-free 8-pin SOIC package Direct battery operation with protection against load dump, ESD protection HBM (1.5 k, 100 pF) 8 kV (BUS pin, BAT BUS short to VBAT overcurrent protection. Voltage tolerance 40 V (BUS pin) Loss of ground protection; BUS pin leakage is lower than S6BT112A01: With SSCG. jump start, and transients 1 mA. pin) S6BT112A02: Without SSCG. Easy selection of master node or slave node. S6BT112A Block Diagram Cypress Semiconductor Corporation Document Number: 002-10203 Rev.*E * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised December 4, 2018 S6BT112A01/S6BT112A02 Table of Contents 1. Applications ............................................................................................................................................................. 3 2. Pin Assignment ............................................................................................................................................................. 4 3. Pin Descriptions ............................................................................................................................................................. 5 4. Block Diagram ............................................................................................................................................................. 6 5. Function Description .......................................................................................................................................................... 7 5.1 Operation Modes ........................................................................................................................................................... 7 5.2 Master Node .................................................................................................................................................................. 8 5.3 Slave Node .................................................................................................................................................................. 11 5.4 Common Functions ..................................................................................................................................................... 15 6. Absolute Maximum Ratings ............................................................................................................................................. 21 7. Recommended Operating Conditions ............................................................................................................................ 22 8. Electrical Characteristics ................................................................................................................................................. 23 9. Ordering Information ........................................................................................................................................................ 34 10. Package Dimensions ...................................................................................................................................................... 34 Document History ........................................................................................................................................................... 35 Sales, Solutions, and Legal Information ............................................................................................................................. 36 Document Number: 002-10203 Rev.*E Page 2 of 36 S6BT112A01/S6BT112A02 1. Applications The following figures illustrate the typical applications of S6BT112A01 or S6BT112A02. S6BT112A AS MASTER 12V Battery CXPI BUS LINE BAT S6BT112A: CXPI Transceiver IC Regulator RC OSC 5V VCC SELMS MCU LDO Regulator Thermal Shutdown Low Voltage Detection Over Current Protection CLK TXD RXD NSLP UART CXPI Control Logic VSS CXPI PHY BUS GND S6BT112A AS SLAVE 12V Battery CXPI BUS LINE BAT S6BT112A: CXPI Transceiver IC Regulator RC OSC 5V VCC SELMS MCU CLK TXD RXD NSLP UART LDO Regulator Thermal Shutdown Low Voltage Detection Over Current Protection CXPI Control Logic VSS CXPI PHY BUS GND Document Number: 002-10203 Rev.*E Page 3 of 36 S6BT112A01/S6BT112A02 2. Pin Assignment Figure 2-1 Pin Assignment (TOP VIEW) RXD 1 7 BAT 3 6 BUS TXD 4 5 GND NSLP 2 CLK Document Number: 002-10203 Rev.*E 8 SELMS Page 4 of 36 S6BT112A01/S6BT112A02 3. Pin Descriptions Table 3-1 Pin Descriptions Pin Symbol Number 1 RXD Direction Output Description Receive data output (open-drain). Requires external pull-up resistor. (refer to Table 7-1 ) Sleep control input. 2 NSLP Input Low: Sleep mode or Standby mode High: Normal mode. Refer to section 5.2.2 or section 5.3.2 When the SELMS pin is Low, the CLK pin is the Baud rate clock input. Input clock signal with baud rate frequency. (When the input clock frequency is 20 kHz, the bit rate is 20 Kbps) 3 CLK I/O When the SELMS pin is High, the CLK pin is Baud rate clock output. Outputs clock signal with baud rate frequency. (When the output clock frequency is 20 kHz , the bit rate is 20 Kbps) Open drain output. Requires external pull-up resistor. (refer to Table 7-1) 4 TXD Input 5 GND - 6 BUS I/O 7 BAT - Transmit data input Ground CXPI BUS line Input/Output Battery (voltage source) supply. Master / slave node select input. 8 SELMS Input Low: Master High: Slave Document Number: 002-10203 Rev.*E Page 5 of 36 S6BT112A01/S6BT112A02 4. Block Diagram Figure 4-1 Block Diagram RXD SELMS Filter BAT Power On Rest Low Voltage RPU_TXD BUS NSLP Control logic CLK TXD Waveform Shaping RPD_NSLP Thermal Shutdown Document Number: 002-10203 Rev.*E GND Page 6 of 36 S6BT112A01/S6BT112A02 5. Function Description 5.1 Operation Modes Figure 5-1 State Transition Diagram Notes [1] : "Hi-z" means high-impedance. [2] : Switching of the master / slave during operation is prohibited. Refer to section 5.4.5. [3] : The operation mode, after the transceiver powers on, has to start from sleep mode. [4] : If TXD is Low when releasing the thermal shutdown, TXD has to toggle "High" before valid. TXD is a Low signal input. For details, refer to section 5.4.7. Document Number: 002-10203 Rev.*E Page 7 of 36 S6BT112A01/S6BT112A02 5.2 Master Node There is only one node in a system, which functions as a schedule manager and a primary clock master. The transceiver works in Master mode when low-level is applied on SELMS. The baud rate clock is applied on the CLK pin in the Master state. The transceiver is usually used as the "Master" or "Slave", except for the "Secondary Clock master function". The SELMS input should not be changed in normal mode. The SELMS input should not be changed during wakeup pulse transmission in Sleep mode. The CLK pin inputs for the baud rate clock in Master state. Table 5-1 SELMS Pin State for Master Pin Input Signal Master/Slave SELMS Low Master Figure 5-2 CLK Input -> BUS signal (Master) 5.2.1 Normal Mode The Normal mode denotes the state to which communication is possible. The master node transmits the clock to the CXPI BUS, which means that the clock is master. During the Normal mode, the transmitted signal is encoded and the received signal is decoded. When the transmitting node transmits data to the CXPI BUS, it transmits to the TXD pin after converting the data to UART format by 1 byte. The data is transmitted to the CXPI BUS as LSB first. When the receiving node receives data from the CXPI BUS, it receives from the RXD pin in the UART format by 1 byte. The UART format is listed in Table 5-2. Refer to the JASO CXPI (JASO D 015-3:2015) standard for details of the operation. Table 5-2 UART Format Start bit bit 0 (LSB) bit 1 bit 2 Document Number: 002-10203 Rev.*E bit 3 bit 4 bit 5 bit 6 bit 7(MSB) Stop bit Page 8 of 36 S6BT112A01/S6BT112A02 5.2.2 Sleep Mode The Sleep mode denotes a power-saving state during which each node stops transmitting and receiving data. All nodes transition to Sleep mode immediately after power-on. The nodes also transition to Sleep mode after the Sleep processing is executed from the Normal mode and transition from Standby mode or Normal mode due to CXPI BUS error. When each node receives the Wakeup factor during the Sleep mode, it transitions to the Standby mode.The Wakeup factor (for example, detecting that the ignition has been turned on) of each node is different from each application (for example, detecting that the ignition has been turned on) and the external factor that receives the Wakeup pulse from the CXPI BUS. During the Sleep mode, the reception signal is received without decoding. The MCU can detect a wakeup pulse width monitor using the RXD signal. The sleep mode is initiated by a falling edge on the NSLP pin while TXD is already set High. The CXPI BUS transmit path is immediately disabled when the NSLP pin goes Low. All wake-up events must be maintained for a specific period (refer to the TMODE_CHG parameter in Table 8-7). Table 5-3 Transition from Normal to Sleep mode Pin Pin State Description TXD High No data transmitting CLK High No clock receiving NSLP High to Low - RXD High impedance High level with external pull-up resistor. BUS High impedance High level with external pull-up resistor. SELMS Low - Note: The "Pin State" indicates before the falling edge in the NSLP pin Table 5-4 Transition from Sleep to Normal mode Pin Pin State Description TXD High No data transmitting CLK High No clock receiving NSLP Low to High - RXD High impedance High level with external pull-up resistor. BUS High impedance High level with external pull-up resistor. SELMS Low - Note: The "Pin State" indicates the state before the rising edge in the NSLP pin Figure 5-3 Transition Sequence Between Sleep and Normal Mode Note: [1] "Hi-Z" means high-impedance. Document Number: 002-10203 Rev.*E Page 9 of 36 S6BT112A01/S6BT112A02 Table 5-5 Bitrate of 20 Kbps (50 s/Bit) UART Receive Data FCH Number of Bits of L Level 3-bit Wakeup Pulse Width 150 s F8H 4-bit 200 s 5.2.3 F0H 5-bit 250 s E0H 6-bit 300 s C0H 7-bit 350 s 80H 8-bit 400 s 00H 9-bit 450 s Standby Mode The Standby mode denotes the prepared state to the Normal mode after releasing the Sleep mode. During the CLK state (in slave node), the RXD pin and the BUS pin are in a high-impedance state. After TMODE_CHG, the state changes to the Normal mode. 5.2.4 Power-on Sequence The power-on sequence occurs at power-up while setting up Sleep mode. When VBAT is above 5.3 V, the NSLP pin should be in a High state. After transition to the normal mode, activate the BUS pin after a clock input of 33 periods. Figure 5-4 Power-on Sequence of Master Node Document Number: 002-10203 Rev.*E Page 10 of 36 S6BT112A01/S6BT112A02 5.3 Slave Node All the nodes, except the master node, are connected with the system. The transceiver works as Slave when High level is applied on SELMS. The CLK pin outputs the baud rate clock during the Slave state. The transceiver is usually used as the "Master" or "Slave", except for the "Secondary Clock master function". Table 5-6 SELMS Pin State for Slave Pin SELMS Input Signal High Master/Slave Slave The SELMS input should not be changed during the Normal mode or during wakeup pulse transmission in the Sleep mode. The CLK pin outputs the baud rate clock in Slave node. Figure 5-5 CLK Pin Clock Output (Slave) 5.3.1 Normal Mode The Normal mode can perform data transmit and receive. During the Normal mode, the signal that is transmitted is encoded and the signal that is received is decoded. When the transmitting node transmits data to the CXPI BUS, it transmits to the TXD pin after converting the data to UART format by 1 byte. The data is transmitted to the CXPI BUS by LSB first. When the receiving node receives data from the CXPI BUS , it revises from the RXD pin in the UART format by 1 byte. The UART format is shown in Table 5-7. Refer to the JASO CXPI (JASO D 015-3:2015) standard for details of the operation. Table 5-7 UART Format Start bit bit 0 (LSB) bit 1 bit 2 Document Number: 002-10203 Rev.*E bit 3 bit 4 bit 5 bit 6 bit 7(MSB) Stop bit Page 11 of 36 S6BT112A01/S6BT112A02 5.3.2 Sleep Mode The Sleep mode denotes a state of power saving during which each node stops transmit and receive of data. All nodes transition to the Sleep mode immediately after power-on. They also transition to the Sleep mode after the sleep processing is executed from the Normal mode and transition from the Standby mode or the Normal mode due to CXPI BUS error. During the Sleep mode, when each node receives the Wakeup factor, it transitions to the Standby mode. The Wakeup factor is different from each application and is composed of the internal factor (for example, detecting that the ignition has been turned on) and the external factor that receives the Wakeup pulse from the CXPI BUS. During the Sleep mode, the reception signal is received without decoding. The sleep mode is initiated by a falling edge on the NSLP pin while the TXD pin is already set High. The CXPI BUS transmit path is immediately disabled when the NSLP pin goes Low. All wake-up events must be maintained for a specific period (refer to TMODE_CHG in Table 8-7). Figure 5-6 Transition Sequence Between Sleep and Normal Mode Table 5-8 Transition from Normal to Sleep Mode Pin TXD Pin State High Description No data transmitting CLK High impedance High level with external pull-up resistor. NSLP High to Low - RXD High impedance High level with external pull-up resistor. BUS High impedance High level with external pull-up resistor. SELMS High - Note: The "Pin State" indicates the state before the falling edge of the NSLP pin. Table 5-9 Transition from Sleep to Normal Mode Pin TXD Pin State High Description No data transmitting CLK High impedance High level with external pull-up resistor. NSLP Low to High - RXD High impedance High level with external pull-up resistor. BUS High impedance High level with external pull-up resistor. SELMS High - Note: The "Pin State" indicates the state before the rising edge of the NSLP pin. Document Number: 002-10203 Rev.*E Page 12 of 36 S6BT112A01/S6BT112A02 Receiver Function in Sleep Mode During the Sleep mode, the received signal will be output from the CLK pin without decoding a received signal. The RXD pin outputs at High level. When the Master node transmits the encoded PWM clock signal to the CXPI BUS during a wake-up sequence, Slave MCUs receive shorter low-level width signals than the UART communication period and possibly get errors. This is because the Slave node is received without decoding. To avoid these errors, S6BT112A01 or S6BT112A02 CXPI transceiver IC outputs receive signals on the CLK pin in the Sleep mode. MCU can detect a wake-up pulse width to monitor the CLK signal. (Figure 5-7) Figure 5-7 CLK Output of Receive SignalRXD Stays High (for Slave Node) Wakeup Function The WakeupPulseOutput state transmits out the wakeup pulse in the Slave node. When the slave device returns from the Sleep mode, it must transmit a wake-up pulse. As the NSLP pin is in a Low state, the TXD pin transmits a Low state. The TXD signal is transmitted to the BUS pin without encode. The TXD pin outputs the signal width, which is a value obtained by subtracting the TTXD_BT: Signal width = TXD signal ("L") - TTXD_BT("L") Figure 5-8 Wake-Up Pulse Transmission Document Number: 002-10203 Rev.*E Page 13 of 36 S6BT112A01/S6BT112A02 5.3.3 Standby Mode This is the standby state during the Normal mode after releasing the Sleep mode. During this state, CLK (in slave node), the RXD pin, and the BUS pin enter the high-impedance state. After "TMODE_CHG," this state changes to the Normal mode. 5.3.4 Power-on Sequence This sequence occurs at power-up, while setting up the Sleep mode. When VBAT is above 5.3 V, the NSLP pin should be in a High state. Figure 5-9 Power-on Sequence of Slave Node Document Number: 002-10203 Rev.*E Page 14 of 36 S6BT112A01/S6BT112A02 5.4 5.4.1 Common Functions Overtemperature Protection The overtemperature protection (OTP) monitors the die temperature. If the junction temperature exceeds the shutdown junction temperature, TSD_H, the thermal protection circuit disables the output driver. The driver is enabled again when the junction temperature falls below TSD_L and theTXD pin is toggled. (see Table 5-10) 5.4.2 WP_ThermalShutdown The WP_ThermalShutdown state detects the "shutdown temperature" during the WakeupPulseOutput mode. The overtemperature protection is inactive during the Sleep mode. Table 5-10 Input Signal Change after Recovery from Thermal Shutdown Master/Slave Pin Toggle of Input Signal Master TXD Required Slave TXD Required Table 5-11 State Under Thermal Shutdown Master/Slave Pin TXD NSLP Master High: Normal mode / Low: Sleep mode (Thermal protection inactive) CLK(input) Normal function RXD Normal function BUS High impedance TXD Normal function NSLP Slave Description Normal function High: Normal mode / Low: Sleep mode (Thermal protection inactive) CLK Normal function RXD Normal function BUS High impedance Figure 5-10 Sequence of Thermal Shutdown Document Number: 002-10203 Rev.*E Page 15 of 36 S6BT112A01/S6BT112A02 5.4.3 Low-voltage Reset The low-voltage reset state detects the low voltage of the BAT pin. This device has an integrated power-on reset and low-voltage detection at the supply BAT. If the supply voltage, VBAT, is dropping below the power-on reset level (that is, VBAT<VPOR_L), then change the LowPowerReset mode. In the LowPowerReset mode, the output stage is disabled and communication to the CXPI BUS is not possible. If the power supply reaches a higher level than the low-voltage reset level, VBAT> VPOR_H, then change the Standby mode (the NSLP pin is High) or Sleep mode (the NSLP pin is Low). After releasing LowPowerRest mode, enable the Power-up sequence. Table 5-12 Input Signal Change after Recovery from Low Voltage Reset Toggle of Input Master/Slave Pin Signal Required Master TXD Slave TXD Required Table 5-13 State Under Low Voltage Reset Master/Slave Master Slave Pin Description SELMS Reset TXD Reset NSLP Reset CLK Reset(High impedance) RXD High impedance BUS High impedance SELMS Reset TXD Reset NSLP Reset CLK Reset(High impedance) RXD High impedance BUS High impedance Figure 5-11 Low-Voltage Detection After releasing the low-voltage reset mode, the logical value high is output to the BUS pin after a clock input of 33 periods. The TXD data is valid from the falling edge on the TXD pin. Document Number: 002-10203 Rev.*E Page 16 of 36 S6BT112A01/S6BT112A02 Overcurrent Protection 5.4.4 The current in the transmitter output stage is limited to protect the transmitter against short-circuit to BAT or GND pins. Table 5-14 Overcurrent Protection Master/Slave Pin TXD Master Slave 5.4.5 Description Normal function NSLP Normal function CLK Normal function RXD Normal function BUS Output current limited by IBUS_LIM TXD Normal function NSLP Normal function CLK Normal function RXD Normal function BUS Output current limited by IBUS_LIM Secondary Clock Master The node that detects the wakeup event transmits the wakeup pulse on to the CXPI BUS. If the primary clock master cannot transmit the clock to the CXPI BUS due to failure, the wakeup pulse is retransmitted. If the clock is not transmitted to the CXPI BUS, each node detects the CXPI BUS error. The secondary clock master may transmit the clock to the CXPI BUS instead of the primary clock master if it detects that the clock does not exist, and confirms that the clock does not exist on the CXPI BUS for the period during which it transitions from the Sleep mode Operation sequence from master to slave The TXD input pin is set High and the CLK pin is high-impedance. A Low setting on the NSLP pin initiates a transition to the Sleep mode. After the RXD pin is confirmed to High state, the SELMS pin goes to High state. Table 5-15 shows the pin states just before the SELMS pin input signal change. Table 5-15 Pin State Table (from Master to Slave) Pin Pin State Description TXD High No data transmitting CLK High impedance High level with external pull-up resistor. NSLP Low Sleep mode SELMS Low to High - RXD High No data receiving BUS High No wakeup signal receiving preferred Document Number: 002-10203 Rev.*E Page 17 of 36 S6BT112A01/S6BT112A02 Figure 5-12 Application Example Secondary Clock Master S6BT112A AS SLAVE (SECONDARY CLOCK MASTER ) 12V Battery CXPI BUS LINE BAT S6BT112A: CXPI Transceiver IC Regulator RC OSC 5V VCC SELMS MCU CLK TXD RXD NSLP UART LDO Regulator Thermal Shutdown Low Voltage Detection Over Current Protection CXPI Control Logic VSS CXPI PHY BUS GND Figure 5-13 Transition Sequence from Master to Slave Operation sequence from slave to master The TXD pin inputs high and the slave node transitions to the Sleep mode after the CLK pin was confirmed to High, and the SELMS pin goes to Low. Document Number: 002-10203 Rev.*E Page 18 of 36 S6BT112A01/S6BT112A02 Table 5-16 Pin State Table (from Slave to Master) Pin TXD Pin State High Description No data transmitting CLK High impedance No wakeup signal receiving NSLP Low Sleep mode SELMS High to Low - RXD High - BUS High No wakeup signal receiving preferred Note: The pin states just before the SELMS input signal change. Figure 5-14 Transition Sequence from Slave to Master 5.4.6 Arbitration Transceivers arbitrate bit-by-bit. Arbitration in bytes is done in the MCU. In the Normal mode, each node always compares the received bit from the CXPI BUS with the transmitted bit to the CXPI BUS. When the value of the bit is corresponding, the node may continuously transmit to the CXPI BUS. When the value of the bit is not corresponding, the loss of arbitration is detected, and the transmission of the bit after that shall discontinue. If the transmitting node detects the arbitration loss, it behaves as the receiving node. The data of each bit transmitted on the CXPI BUS performs arbitration from the start by the bit. Moreover, arbitration is targeted at the entire field of the frame. When two or more nodes begin transmitting at the same time, by arbitration only the node that transmits the highest priority frame can complete the transmission. The MCU compares between the transmitted data (TXD) and received data (RXD). If the data difference is detected, MCU has to stop data transmission until finding IFS. 5.4.7 TXD Toggle If the TXD pin is short to ground or open, the BUS pin output is not fixed Low (logic value). Therefore, it does not interfere with the communication of the other device. An initial TXD dominant check prevents the bus line being driven to a permanent dominant state (blocking all network communications) if the TXD pin is forced permanently Low by a hardware and/or software application failure. The TXD input level is checked after a transition to the Normal mode. If the TXD pin is Low, the transmit path remains disabled and is only enabled when the TXD pin goes High. A TXD toggle is required in the following cases. Data Data First First transmission after recovery from low-voltage reset. transmission after recovery from thermal shutdown. TXD data transmission in the Normal mode. wake-up pulse transmission in sleep mode. Document Number: 002-10203 Rev.*E Page 19 of 36 S6BT112A01/S6BT112A02 Short-circuit from the TXD pin to ground.(failure detect) In the event of a short-circuit to ground or an open-wire on the TXD pin, the BUS pin output remains High (logical value `1') by this toggle function. In this case, by comparing the sent data to the TXD pin and received data from the RXD pin of the transceiver IC, the MCU can detect the permanent Low on the TXD pin by the data difference. In this case too, the receiver is active. Figure 5-15 Normal Transmission Sequence of Master Figure 5-16 TXD Toggle of Master after Transition to Normal mode Figure 5-17 Slave TXD Toggle after Recovery from Low voltage State Document Number: 002-10203 Rev.*E Page 20 of 36 S6BT112A01/S6BT112A02 6. Absolute Maximum Ratings Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings. Parameters Power supply voltage Symbol Conditions Min Max Unit VBAT BAT pin -0.3 40 V VNSLP NSLP pin -0.3 6.9 V VSELMS SELMS pin -0.3 18 V VCLK CLK pin -0.3 6.9 V VTXD TXD pin -0.3 6.9 V VRXD RXD pin -0.3 6.9 V VCLK CLK pin -0.3 6.9 V VBUS BUS pin -40 40 V VESDBUS BUS pin -8 8 kV VESDBAT BAT pin -8 8 kV -2 2 kV Input voltage Output voltage BUS pin voltage Rating BUS pin ESD (1.5 k, 100 pF) BAT pin ESD (1.5 k, 100 pF) NSLP pin SELMS pin ESD VESD CLK pin (1.5 k, 100 pF) TXD pin RXD pin Storage temperature TSTG - -55 150 C TJMAX - -40 150 C Maximum junction temperature Document Number: 002-10203 Rev.*E Page 21 of 36 S6BT112A01/S6BT112A02 7. Recommended Operating Conditions Table 7-1 Recommended Condition Parameters Power supply voltage Operating ambient temperature Min Value Typ Max 5.3 - 18 V 40 +25 +125 C BUS pin (Master nodeSELMS=0V) 900 1000 1100 Symbol VBAT Conditions BAT pin [1] TA - Unit BUS pin pull-up resistance RMASTER RXD pin pull-up resistance RRXD RXD pin 2.4 10 - k CLK pin pull-up resistance RCLK CLK pin (SELMS=5V) 2.4 10 - k Note: [1]: (18 V < VBAT 27 V) less than 2 minutes. WARNING: 1. The recommended operating conditions are requiredir to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated under these conditions. 2. Any use of semiconductor devices will be under their recommended operating condition. 3. Operation under any conditions other than these conditions may adversely affect reliability of device and could result in device failure. 4. No warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. If you are considering application under any conditions other than listed herein, please contact sales representatives beforehand. Document Number: 002-10203 Rev.*E Page 22 of 36 S6BT112A01/S6BT112A02 8. Electrical Characteristics Table 8-1 DC Characteristics VBAT = 5.3 V~27 V[1], TA = -40~125 C; All voltages are referenced to Pin 8 (GND); Positive currents flow into the IC; unless otherwise specified. Parameters Symbol Pin Name Conditions Min Typ Max Unit - 1.4 2.9 mA - 2.0 4.0 mA - 6 - A - 16 - A - - 50 A - - 60 A Normal mode TXD=5 V CLK=20 kHz, Duty 50% Normal mode TXD=0 V CLK=20 kHz, Duty 50% Sleep mode VBAT =12 V TXD=5 V SELMS=5 V BUS= VBAT TA=25 C Sleep mode Power supply current IBAT BAT VBAT =12 V TXD=5 V SELMS=0 V BUS= VBAT TA=25 C Sleep mode VBAT =12 V TXD=5 V SELMS=5 V BUS= VBAT Sleep mode VBAT =12 V TXD=5 V SELMS=0 V BUS= VBAT BUS pin pull-up resistance RBUSpu BUS - 20 30 47 k BUS short circuit current IBUS_LIM BUS VBUS=18 V 40 - 200 mA Document Number: 002-10203 Rev.*E Page 23 of 36 S6BT112A01/S6BT112A02 Parameters Symbol Pin Name Conditions Min Typ Max Unit - - 20 A -1 - - mA BUS=18 V BUS input leak current (HIGH) IBUS_PAS_rec BUS VBAT =5.3 V TXD=5 V TA=25 C BUS input leak current (LOW) BUS=0 V IBUS_PAS_dom BUS VBAT =12 V TXD=5 V loss of ground BUS leak current IBUS_NO_GND BUS VBAT =GND=18 V BUS=0 V -1 - 1 mA loss of battery BUS leak current IBUS_NO_BAT BUS VBAT =0 V BUS=18 V TA=25 C - - 30 A VBUSDR BUS VBAT =13.5 V IBUSsource=-100 A 2.4 - 5.7 V BUS TXD=0 V VBAT =7 V BUS pull-up resistance= 500 - - 1.4 V VO_dom BUS TXD=0 V VBAT =18 V BUS pull-up resistance= 500 - - 2 V Receiver low level threshold voltage VBUSdom BUS VBAT =12V, TA=25 C - - 0.423 VBAT V Receiver high level threshold voltage VBUSrec BUS VBAT =12V, TA=25 C 0.556 VBAT - - V Receiver hysteresis voltage VHYS BUS VBAT =12V, TA=25C - - 0.133 VBAT V Low level power-on reset threshold voltage VPOR_L BAT - 3.1 3.8 4.7 V High level power-on reset threshold voltage VPOR_H BAT - 3.3 4.1 4.9 V VPOR_HYS BAT - 0.2 0.3 0.5 V Temperature shutdown threshold TSD_H - [2] 156 165 174 C Temperature shutdown release threshold TSD_L - [2] 151 159 168 C BUS drop voltage VO_dom BUS low level output voltage power-on reset hysteresis voltage Notes: [1]: (18 V < VBAT 27 V) less than 2 minutes. [2]: Guaranteed by design Document Number: 002-10203 Rev.*E Page 24 of 36 S6BT112A01/S6BT112A02 Table 8-2 DC Characteristics CLK Pin (If SELMS = 5 V, this pin operates as Open Drain Output Pin. If SELMS = 0 V, this pin operates as an input pin) VBAT = 5.3 V~27 V[1], TA = -40~125 C; all voltages are referenced to Pin 8 (GND). Positive current flow into the IC; unless otherwise specified. Parameters Symbol Pin Name Min Typ Ma x Unit High level input voltage VIH_CLK CLK SELMS = 0 V 2 - 6 V Low level input voltage VIL_CLK CLK SELMS = 0 V -0.3 - 0.8 V Hysteresis range of input voltage VHYS_CLK CLK SELMS = 0 V 0.03 - 0.5 V Low level output voltage VOL_CLK CLK - - 0.6 V Conditions ICLK = 2.2 mA SELMS = 5 V Low level current IOL_CLK CLK SELMS = 5 V 1.3 3 - mA High level leak current IILH_CLK CLK SELMS = 5 V -3 - 3 A Low level leak current IILL_CLK CLK SELMS = 5 V -3 - 3 A Note: [1]: (18 V < VBAT 27 V) less than 2 minutes. Table 8-3 DC Characteristics NSLP Pin VBAT = 5.3 V~27 V[1], TA = -40~125 C; all voltages are referenced to Pin 8 (GND). Positive current flow into the IC; unless otherwise specified. Parameters Symbol Pin Name High level input voltage VIH_NSLP NSLP Low level input voltage VIL_NSLP Hysteresis range of input voltage VHYS_NSLP Internal pull-down resistance RPD_NSLP Low level leak current IILL_NSLP NSLP NSLP NSLP NSLP Conditions Min Typ Max Unit - 2 - 6 V - -0.3 - 0.8 V - 0.03 - 0.5 V NSLP = 5 V 100 250 650 k NSLP = 0 V -3 - 3 A Note: [1]: (18 V < VBAT 27 V) less than 2 minutes Document Number: 002-10203 Rev.*E Page 25 of 36 S6BT112A01/S6BT112A02 Table 8-4 TXD Pin VBAT = 5.3 V~27 V[1], TA = -40~125 C; all voltages are referenced to Pin 8 (GND). Positive current flow into the IC; unless otherwise specified. Parameters Symbol Pin Name Conditions Min Typ Max Unit High level input voltage VIH_TXD TXD - 2 - 6 V Low level input voltage VIL_TXD TXD - -0.3 - 0.8 V Hysteresis range of input voltage VHYS_TXD TXD - 0.03 - 0.5 V Internal pull-up resistance RPU_TXD TXD TXD = 0 V 50 125 325 k High level leak current IILH_TXD TXD TXD = 5 V -3 - 3 A Note: [1]: (18V < VBAT 27V) less than 2 minutes Table 8-5 SELMS Pin VBAT = 5.3 V~27 V[1], TA = -40~125 C; all voltages are referenced to Pin 8 (GND). Positive current flow into the IC; unless otherwise specified. Parameters Symbol Pin Name High level input voltage VIH_SELMS SELMS Low level input voltage VIL_SELMS Hysteresis range of input voltage VHYS_SELMS Internal pull-up resistance RPU_SELMS High level leak current IILH_SELMS SELMS SELMS SELMS Conditions Min Typ Max Unit - 2 - 6 V - -0.3 - 0.8 V - 0.03 - 0.5 V SELMS = 0 200 500 1300 k -3 - 3 A V SELMS SELMS = 5 V Note: [1]: (18 V < VBAT 27 V) less than 2 minutes. Document Number: 002-10203 Rev.*E Page 26 of 36 S6BT112A01/S6BT112A02 Table 8-6 RXD Pin (Open Drain Output) VBAT = 5.3 V~27 V[1], TA = -40~125 C; all voltages are referenced to Pin 8 (GND). Positive current flow into the IC; unless otherwise specified. Parameters Symbol Pin Name Conditions Min Typ Max Unit Low level output voltage VOL_RXD RXD IRXD = 2.2 mA - - 0.6 V Low level current IOL_RXD RXD RXD = 0.4 V 1.3 3 - mA High level leak current IOLH_RXD RXD RXD = 5 V -3 - 3 A Low level leak current IOLL_RXD RXD RXD = 0 V -3 - 3 A Note: [1]: (18 V < VBAT 27 V) less than 2 minutes. Table 8-7 AC Characteristics VBAT = 5.3 V~27 V[1], TA = -40~125 C BUS Load 1 k /1 nF; unless otherwise specified. Parameters Bitrate Symbol Pin Name TBUAD BUS VTH(bus) [3] = 0.5VBAT TMODE_CHG NSLP VTH(5v)[4] = 50% Conditions Min Typ Max Unit 2.4 - 20 kbps - - 1 ms 100 - - s 1 - - ms - - 195 s - - 0.9 Tbit[5] - - 0.39Tbit +6 - Mode transition time (Sleep to Normal or Normal to Sleep.) NSLP wait time TSLP_WT Minimum sleep time TSLP_MN CLK NSLP VTH(5 V) [4] = 50% NSLP NLSP = 0 V Driver boot time under sleep mode. [2] TTXD_BT TXD SELMS = 5 V VTH(5v)[4]=50% VTH(bus)[3]=0.3VBAT NLSP = 5 V SELMS = 0 V CLK transmission delay time TCLK_PD CLK CLK=input clock TXD=5 V VTH(5v)[4]=50% VTH(bus)[3]=0.3VBAT NLSP = 5 V Time of Low level of logic value '1' SELMS = 0 V Ttx_1_lo_rec BUS CLK=input clock TXD=5 V VTH(bus)[3] = 0.7VBAT Document Number: 002-10203 Rev.*E Page 27 of 36 S6BT112A01/S6BT112A02 Parameters Symbol Pin Name Conditions Min Typ Max Unit 0.11 - - Tbit - - - - - - 0.06 - - Tbit - - 2.4 Tbit - - 3.3 Tbit 30 - 70 % 14 - 50 % 30 - 150 s 0.5 - 5 s - - 0.16 Tbit 0.93 - - V_rec_1 NLSP = 5 V Time of Low level of logic value '1' SELMS = 0 V Ttx_1_lo_dom BUS CLK=input clock TXD=5 V VTH(bus)[3] = 0.3 VBAT Time of Low level of logic value '0' Ttx_0_lo_rec BUS NLSP = 5 V Ttx_1_lo_rec TXD = 0 V +0.06Tbit VTH(bus) [3] = Time of Low level of logic value '0' Ttx_0_lo_dom BUS 0.7 VBAT NLSP = 5 V Ttx_1_lo_dom TXD=0 V +0.06Tbit VTH(bus) [3] = 0.3 VBAT High level time at receiving node. NLSP = 5 V Ttx_0_hi BUS TXD = 0 V VTH(bus)[3] = 0.556 VBAT TRXD_PD RXD NSLP = 5 V Delay time of transmission if logic value '0'. TTXD_PD TXD NSLP = 5 V Input clock duty TICLK_DY CLK SELMS = 0 V TOCLK_DY CLK SELMS = 5 V Trx_wakeup_master BUS Receiver delay time Output clock duty[6] Wakeup pulse filter constant(Master) VTH(bus)[3] = VBUSdom VTH(bus) [3]=0.3 VBAT VTH(5 V)[4] = 50% VTH(5 V)[4] = 50% NSLP = 0 V SELMS = 0 V VTH(bus) [3]=42.3% Wakeup pulse filter constant(Slave) NSLP = 0 V Trx_wakeup_slave BUS SELMS = 5 V VTH(bus) [3] = 42.3% NSLP = 5 V Time of bus slope from minimum Ttx_1_dom_m BUS SELMS = 0 V VBAT = 7V VTH(bus) [3] = 0.3 VBAT Recessive level of logical value `0'. V_rec_0 Document Number: 002-10203 Rev.*E BUS NSLP = 5 V Page 28 of 36 S6BT112A01/S6BT112A02 Notes: [1]: (18 V < VBAT 27 V) less than 2 minutes RXD pin load: 20 pF [2]: CXPI BUS load (Figure 8-11) : 10 nF/500 [3]: VTH(bus)threshold of BUS pin [4]: VTH(5v)threshold of NSLP,CLK,TXD,SELMS,RXD pins. [5]: Tbit stands for 1bit time.(Figure 8-1) [6]: logic '0/1' threshold clock Figure 8-1 Definition of Tbit Figure 8-2 Mode Transition Time Figure 8-3 NSLP Wait Time Figure 8-4 Minimum Sleep Time Document Number: 002-10203 Rev.*E Page 29 of 36 S6BT112A01/S6BT112A02 Figure 8-5 Driver Boot Time Under Sleep Mode Figure 8-6 CLK Transmission Delay Time Document Number: 002-10203 Rev.*E Page 30 of 36 S6BT112A01/S6BT112A02 Figure 8-7 Logic Low and High CXPI BUS Waveform Figure 8-8 Receiver Delay Time Document Number: 002-10203 Rev.*E Page 31 of 36 S6BT112A01/S6BT112A02 Figure 8-9 Logic Low Transmission Delay Time Figure 8-10 Wakeup Pulse Waveform Document Number: 002-10203 Rev.*E Page 32 of 36 S6BT112A01/S6BT112A02 Figure 8-11 CXPI BUS Load Connection Document Number: 002-10203 Rev.*E Page 33 of 36 S6BT112A01/S6BT112A02 9. Ordering Information Part Number S6BT112A01SSBB002 Package 8-pin 150-mil SOIC Tape and Reel (SOA008) S6BT112A02SSBB002 8-pin 150-mil SOIC Tape and Reel (SOA008) 10. Package Dimensions Package Type Package Code SOP 8 SOA 008 NOTES: DIMENSIONS SYMBOL MIN. NOM. MAX. 0.89 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M - 1994. 3. DIMENSION D DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 mm PER END. DIMENSION E1 DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 mm PER SIDE. D AND E1 DIMENSIONS ARE DETERMINED AT DATUM H. 4. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM. DIMENSIONS D AND E1 ARE DETERMINED AT THE OUTMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUSIVE OF ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 5. DATUMS A AND B TO BE DETERMINED AT DATUM H. 6. "N" IS THE MAXIMUM NUMBER OF TERMINAL POSITIONS FOR THE SPECIFIED PACKAGE LENGTH. 7. THE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 TO 0.25 mm FROM THE LEAD TIP. 8. DIMENSION "b" DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.10 mm TOTAL IN EXCESS OF THE "b" DIMENSION AT 0.50 MAXIMUM MATERIAL CONDITION. THE DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OF THE LEAD FOOT. 9. THIS CHAMFER FEATURE IS OPTIONAL. IF IT IS NOT PRESENT, THEN A PIN 1 IDENTIFIER MUST BE LOCATED WITHIN THE INDEX AREA INDICATED. 10. LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED FROM THE SEATING PLANE. A - - 1.75 A1 0.10 - 0.25 A2 1.32 - - b 0.31 - 0.51 b1 0.28 - 0.48 c 0.17 - 0.25 c1 0.17 - 0.23 D 4.90 BSC E 6.00 BSC E1 3.90 BSC e L 1.27 BSC - 0.40 L1 1.04 REF L2 0.25 BSC 8 N h 0.25 - 0 0 - 8 01 5 - 15 02 1. ALL DIMENSIONS ARE IN MILLIMETERS. 002-18754 ** 0 REF Document Number: 002-10203 Rev.*E Page 34 of 36 S6BT112A01/S6BT112A02 Document History Document Title: S6BT112A01/S6BT112A02 ASSP CXPI Transceiver IC for Automotive Network Document Number: 002-10203 Revision ECN ** 5046456 Orig. of Submission Change Date AKFU 12/11/2015 Description of Change Initial release New Spec. Revised the sentence style of the cover page Changed all section 5 for easy to understand. *A 5208207 AKFU 04/06/2016 Changed figure of application. Changed Figure 4-1 and Figure 5-1. Removed "Driver recovery time when over-temperature detection is released." Changed figure of application. Changed Figure 4-1 Block Diagram Changed Figure 5-12 Application example Secondary clock master *B 5528948 AKFU 11/24/2016 Added the conditions of VBUSdom/VBUSrec/ VHYS/Ttx_1_dom_m. Removed the prameter of Receiver center level voltage (VBUS_CNT). Changed Figure 8-11 CXPI BUS Load Connection Changed Ordering Information. Changed Package Dimensions. Updated Introduction. Updated Note [3] (Page 8). *C 5547736 AKFU 12/09/2016 Updated 5.2 Master Node. Updated 5.2.2 Sleep Mode. Changed figure of 1. Applications *D 5757034 AKFU 06/20/2017 Changed Figure 5-12 Application example Secondary Clock Master *E 6397891 SHNO Document Number: 002-10203 Rev.*E 12/04/2018 Changed SOA 008 figure in Package Demensions Page 35 of 36 S6BT112A01/S6BT112A02 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. 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