2004 Microchip Technology Inc. Advance Information DS39632A
PIC18F2455/2550/4455/4550
Data Sheet
28/40/44-Pin High-Performance,
Enhanced Flash USB Microcontrollers
with nanoWatt Technology
DS39632A-page ii Advance Information 2004 Microchip Technology Inc.
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• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in t he
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrit y of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
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Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
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2004 Microchip Technology Inc. Advance Information DS39632A-page 1
PIC18F2455/2550/4455/4550
Universal Seri al Bus Features:
• USB V2.0 Compliant
• Low Speed (1.5 Mb/s) and Full Speed (12 Mb/s)
• Supports Control, Interrupt, Isochronous and Bulk
Transfers
• Supports up to 32 endpoints (16 bidirectional)
• 1-Kbyte dual access RAM for USB
• On -board USB transceiver w ith on-c hip voltage
regulator
• Interface for off-chip USB transceiver
• Streaming Parallel Port (SPP) for USB streaming
transfers (40/44-pin devices only)
Power Managed Modes:
• Run: CPU on, periphera ls on
• Idle: CP U off, peripherals on
• Sleep: CPU off, peripherals off
• Idle mode currents down to 5.8 µA typical
• Sleep mode currents down to 0.1 µA typical
• Timer1 oscillator: 1.1 µA typical, 32 kHz, 2V
• Watchdog Timer: 2.1 µA typical
• Two-Speed Osci ll ator Start-up
Flexible Oscil lator Structure:
• Four Cry stal mo des, incl uding High Prec ision PLL
for USB
• Two External Clock modes, up to 48 MHz
• Internal oscillator block:
- 8 user selectable frequencies, from 31 kHz to 8 MHz
- User-tunable to compensate for frequency drift
• Secondary oscillator using Timer1 @ 32 kHz
• Dual oscillator options allow microcontroller and
USB module to run at different clock speeds
• Fail-Safe Clock Monitor
- Allows for safe shutdown if any clock stops
Peripheral Highl ights:
• High current sink/source 25 mA/25 mA
• Three extern al inte rrup t s
• Four Timer modules (Timer0 to Timer3)
• Up to 2 Capture/Compare/PWM (CCP) modules:
- Capture is 16-bit, max resolution 6.25 ns (TCY/16)
- Compare is 16-bit, max resolution 100 ns (TCY)
- PWM output: PWM resolution is 1 to 10-bit
• Enhanced Capture/Compare/PWM (ECCP) module:
- Multiple output modes
- Selectable polarity
- Programmable dead time
- Auto-Shutdown and Auto-Restart
• Enhanced USART module:
- LIN bus support
• Master Synchronous Serial Port (MSSP) module
supporting 3-wire SPI™ (all 4 modes) and I2C™
Master and Slav e Mod es
• 10-bit, up to 13-channels Analog-to-Digital Converter
module (A/D) with programmable acquisition time
• Dual analog comparators with input multiplexing
Special Microcontroller Features:
• C compiler optimized architecture with optional
extended instruction set
• 100,000 eras e/w ri te cy cl e Enhanced Flash
program memory typical
• 1,000,000 erase/write cycle Data EEPROM
memory typical
• Flash/Data EEPROM Retention: > 40 years
• Self-programmable under software control
• Priority levels for interrupts
• 8 x 8 Single-Cycle Hardware Multiplier
• Extended Watchdog Ti mer (WDT):
- Programmable period from 41 ms to 131s
- 2% stability over VDD and temperature
• Programmable Code Protection
• Single-supply 5V In-Circuit Serial
Programming™ (ICSP™) via two pins
• In-Circuit Debug (ICD) via two pins
• Optional dedicated ICD/ICSP port (44-pin devices only)
• Wide operating voltage range (2.0V to 5.5V)
Device
Program Memory Data Memory
I/O 10-bit
A/D (ch) CCP/ECCP
(PWM) SPP
MSSP
EAUSART
Comparators
Timers
8/16-bit
FLASH
(bytes) # Single-Word
Instructions SRAM
(bytes) EEPROM
(bytes) SPI Master
I2C
PIC18F2455 24 K 12288 2048 256 24 10 2/0 No Y Y 1 2 1/3
PIC18F2550 32 K 16384 2048 256 24 10 2/0 No Y Y 1 2 1/3
PIC18F4455 24 K 12288 2048 256 35 13 1/1 Yes Y Y 1 2 1/3
PIC18F4550 32 K 16384 2048 256 35 13 1/1 Yes Y Y 1 2 1/3
28/40/44-Pin High-Performance, Enhanced Flash USB
Microcontrollers with nanoWatt Technology
PIC18F2455/2550/4455/4550
DS39632A-page 2 Advance Information 2004 Microchip Technology Inc.
Pin Diagrams
40-Pi n PDIP
PIC18F2455
28-Pin PDIP, SOIC
PIC18F2550
10
11
2
3
4
5
6
1
8
7
9
12
13
14 15
16
17
18
19
20
23
24
25
26
27
28
22
21
MCLR/VPP/RE3
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT/RCV
RA5/AN4/SS/HLVDIN/C2OUT
VSS
OSC1/CLKI
OSC2/CLKO/RA6
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2(1)/UOE
RC2/CCP1
VUSB
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/AN11/KBI0
RB3/AN9/CCP2(1)/VPO
RB2/AN8/INT2/VMO
RB1/AN10/INT1/SCK/SCL
RB0/AN12/INT0/FLT0/SDI/SDA
VDD
VSS
RC7/RX/DT/SDO
RC6/TX/CK
RC5/D+/VP
RC4/D-/VM
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/AN11/KBI0/CSSPP
RB3/AN9/CCP2(1)/VPO
RB2/AN8/INT2/VMO
RB1/AN10/INT1/SCK/SCL
RB0/AN12/INT0/FLT0/SDI/SDA
VDD
VSS
RD7/SPP7/P1D
RD6/SPP6/P1C
RD5/SPP5/P1B
RD4/SPP4
RC7/RX/DT/SDO
RC6/TX/CK
RC5/D+/VP
RC4/D-/VM
RD3/SPP3
RD2/SPP2
MCLR/VPP/RE3
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT/RCV
RA5/AN4/SS/HLVDIN/C2OUT
RE0/AN5/CK1SPP
RE1/AN6/CK2SPP
RE2/AN7/OESPP
VDD
VSS
OSC1/CLKI
OSC2/CLKO/RA6
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2(1)/UOE
RC2/CCP1/P1A
VUSB
RD0/SPP0
RD1/SPP1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
PIC18F4455
PIC18F4550
Note 1: RB3 is the alternate pin for CCP2 multiplexing.
2004 Microchip Technology Inc. Advance Information DS39632A-page 3
PIC18F2455/2550/4455/4550
Pin Diagrams (Continued)
PIC18F4455
44-Pin TQFP
44-Pin QFN
PIC18F4455
PIC18F4550
PIC18F4550
10
11
2
3
6
1
18
19
20
21
22
12
13
14
15
38
8
7
44
43
42
41
40
39
16
17
29
30
31
32
33
23
24
25
26
27
28
36
34
35
9
37
RA3/AN3/VREF+
RA2/AN2/VREF-/CVREF
RA1/AN1
RA0/AN0
MCLR/VPP/RE3
NC/ICCK(2)/ICPGC(2)
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/AN11/KBI0/CSSPP
NC/ICDT(2)/ICPGD(2) RC6/TX/CK
RC5/D+/VP
RC4/D-/VM
RD3/SPP3
RD2/SPP2
RD1/SPP1
RD0/SPP0
VUSB
RC2/CCP1/P1A
RC1/T1OSI/CCP2(1)/UOE
NC/ICPORTS(2)
NC/ICRST(2)/ICVPP(2)
RC0/T1OSO/T13CKI
OSC2/CLKO/RA6
OSC1/CLKI
VSS
VDD
RE2/AN7/OESPP
RE1/AN6/CK2SPP
RE0/AN5/CK1SPP
RA5/AN4/SS/HLVDIN/C2OUT
RA4/T0CKI/C1OUT/RCV
RC7/RX/DT/SDO
RD4/SPP4
RD5/SPP5/P1B
RD6/SPP6/P1C
VSS
VDD
RB0/AN12/INT0/FLT0/SDI/SDA
RB1/AN10/INT1/SCK/SCL
RB2/AN8/INT2/VMO
RB3/AN9/CCP2(1)/VPO
RD7/SPP7/P1D 5
4
10
11
2
3
6
1
18
19
20
21
22
12
13
14
15
38
8
7
44
43
42
41
40
39
16
17
29
30
31
32
33
23
24
25
26
27
28
36
34
35
9
37
RA3/AN3/VREF+
RA2/AN2/VREF-/CVREF
RA1/AN1
RA0/AN0
MCLR/VPP/RE3
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/AN11/KBI0/CSSPP
NC RC6/TX/CK
RC5/D+/VP
RC4/D-/VM
RD3/SPP3
RD2/SPP2
RD1/SPP1
RD0/SPP0
VUSB
RC2/CCP1/P1A
RC1/T1OSI/CCP2(1)/UOE
RC0/T1OSO/T13CKI
OSC2/CLKO/RA6
OSC1/CLKI
VSS
AVDD
RE2/AN7/OESPP
RE1/AN6/CK2SPP
RE0/AN5/CK1SPP
RA5/AN4/SS/HLVDIN/C2OUT
RA4/T0CKI/C1OUT/RCV
RC7/RX/DT/SDO
RD4/SPP4
RD5/SPP5/P1B
RD6/SPP6/P1C
VSS
VDD
RB0/AN12/INT0/FLT0/SDI/SDA
RB1/AN10/INT1/SCK/SCL
RB2/AN8/INT2/VMO
RB3/AN9/CCP2(1)/VPO
RD7/SPP7/P1D 5
4AVSS
VDD
AVDD
Note 1: RB3 is the alternate pin for CCP2 multiplexing.
2: Special ICPORTS features available in select circumstances. See Section 25.9 for more information.
PIC18F2455/2550/4455/4550
DS39632A-page 4 Advance Information 2004 Microchip Technology Inc.
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 7
2.0 Oscillator Configurations............................................................................................................................................................ 23
3.0 Power Managed Modes ...... .. .. .... .. ..... .. .. .. .... .. .. .. ..... .... .. .. .. .. .. .. ....... .. .. .. .. .... .. ..... .. .. .. .... .. .. .. ......................................................... 35
4.0 Reset.......................................................................................................................................................................................... 43
5.0 Memory O rganization................................................................................................................................................................. 57
6.0 Flash Pro g ram Memory........... ...... ....... ................. ...... ................. ...... ...... ................. ...... ........................................................... 79
7.0 Data EEPR OM Mem o ry...... ...... ................. ...... ................. ...... ....... ................. ...... ...... ............................................................... 89
8.0 8 x 8 Hardware Multip lier............... ....... ...... ...... ....... ...... ...... ....... ...... ...... ...... ....... ...... ...... ........................................................... 95
9.0 Interrupts.................................................................................................................................................................................... 97
10.0 I/O Ports ............... ................. ...... ................. ...... ................. ................. ...... ............. ................................................................. 111
11.0 Timer0 Module ......................................................................................................................................................................... 125
12.0 Timer1 Module ......................................................................................................................................................................... 129
13.0 Timer2 Module ......................................................................................................................................................................... 135
14.0 Timer3 Module ......................................................................................................................................................................... 137
15.0 Capture/Compare/PWM (CCP) Modules .................................................................. .... ............. ...... ........................................ 141
16.0 Enhanc ed Capture/Com pare/PW M (ECCP) Module................................................................................................................ 149
17.0 Universal Serial Bus (USB)...................................................................................................................................................... 163
18.0 Streaming Parallel Port ............................................................................................................................................................ 187
19.0 Mas ter Sy nchronous Serial Port (M SSP ) Module .................................................................................................................... 193
20.0 Enhanc ed Universal Sync hronous Receiv er Transmitter (EUSART )....................................................................................... 233
21.0 10-Bit Analog-to-Digital Converter (A/D) Module ..................................... .... ........... .... .... ........... .............................................. 253
22.0 Comparator Module................................ .. .... .... .. ......... .. .... .... .. ......... .... .. .... .. ......... .... .. .... ......................................................... 263
23.0 Comparator Voltage Reference Module....... .... .. ....... .... .. .... .. ....... .... .. .... .. .... ....... .. .... .. .... .. ....... .... ............................................ 269
24.0 High/Low-Voltage Detect (HLVD)..................... ......... .... .... .... ........... .... .... .... ......... .... .... .... ....................................................... 273
25.0 Specia l Features of the CPU......... ....... ...... ...... ................. ...... ....... ...... ................. ...... ...... ....................................................... 279
26.0 Instruction Set Summary.......................................................................................................................................................... 301
27.0 Developm ent Suppor t............................................................................................................................................................... 351
28.0 Electrical Characteristics.......................................................................................................................................................... 357
29.0 DC and AC Characteristics Graphs and Tables............ .... .... ......... .. .... .... .... ....... .... .... .... ......... .. .... .......................................... 395
30.0 Packagin g In fo rmation................. ....... ...... ................. ...... ...... ....... ................ ....... ...... ...... ......................................................... 397
Appendix A: Revision History............................................................................................................................................................. 405
Appendix B: Device Differences......................................................................................................................................................... 405
Appendix C: Conversion Considerations ................................ .... .. .... ....... .. .... .. .... .. ....... .... .. .... .. .. ....................................................... 406
Appendix D: Migration from Baseline to Enhanced Devices.............................................................................................................. 406
Appendix E: Migration from Mid-Range to Enhanced Devices.......................... .... ......... .... .... .... ........... .... .... .................................... 407
Appendix F: Migration from High-End to Enhanced Devices..................... .... .. .... ....... .... .. .... .... .. ....... .... .. .... ...................................... 407
Index .................................................................................................................................................................................................. 409
On-Line Support...................................... ......... .... .. .... ......... .. .... .. .... ......... .. .... .... .. ......... .. ................................................................... 421
Systems Information and Upgrade Hot Line. ..................................................................................................................................... 421
Reader Response.............................................................................................................................................................................. 422
PIC18F2455/2550/4455/4550 Product Identification System ............................................................................................................ 423
2004 Microchip Technology Inc. Advance Information DS39632A-page 5
PIC18F2455/2550/4455/4550
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
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We welcome your feedback.
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The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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PIC18F2455/2550/4455/4550
DS39632A-page 6 Advance Information 2004 Microchip Technology Inc.
NOTES:
2004 Microchip Technology Inc. Advance Information DS39632A-page 7
PIC18F2455/2550/4455/4550
1.0 DEVICE OVERVIEW
This do cu me n t conta i ns dev ic e spec if i c in f orm at i on fo r
the following devices:
This family of dev ices offers the a dvantages of all PIC18
microcontrollers – namely, high computational perfor-
mance at an ec onomical price – w ith the addition of high
endurance, Enhanced Flash program memory. In addi-
tion to these features, the PIC18F2455/2550/4455/4550
family introduces design enhancements that make
these microcontrollers a logical choice for many
high-performance, power sensitive applications.
1.1 New Core Features
1.1.1 nanoWatt TECHNOLOGY
All of the devices in the PIC18F2455/2550/4455/4550
family incorporate a range of features that can signifi-
cantly reduce power consumption during operation.
Key items include:
•Alternate Run Modes: By clocking the controller
from the Timer1 source or the internal oscillator
block, power consumption during code execution
can be reduced by as much as 90%.
•Multiple Idle Modes: The controller can also run
with its CPU core disabled but the peripherals still
active . In these st ates, powe r consumptio n can be
reduced even further, to as little as 4% of normal
operation requirements.
•On-the-fly Mode Switching: The power
manage d mode s a re invo ked b y user code d urin g
operation, allowing the user to incorporate
power-saving ideas into their application’s
software design.
•Lower Consumption in Key Modules: The
power requirements for both Timer1 and the
Watch dog Timer have been reduced by up to
80%, with typical values of 1 .1 µA and 2.1 µA,
respectively.
1.1.2 UNIVERSAL SERIAL BUS (USB)
Devices in the PIC18F2455/2550/4455/4550 family
incor porate a fully -feature d Univ ersal Se rial Bu s com-
munications module that is compliant with the USB
Specification Revision 2.0. The module supports both
low-speed and full-speed communication for all sup-
ported data transfer types. It also incorporates its own
on-chip transceiver and 3.3V regulator and supports
the use of extern al transc eivers and volt age reg ulators.
1.1.3 MULTIPLE OSCILLATOR OPTIONS
AND FEATURES
All of the devices in the PIC18F2455/2550/4455/4550
family offer twelve different oscillator options, allowing
users a wide range o f choices i n developin g applica tion
hardware. These include:
• Four Crystal modes, using crystals or ceramic
resonators
• Four External Clock modes, offering the option of
using two pins (oscillator input and a divide-by-4
clock output) or one pin (oscillator input, with the
second pin reassigned as general I/O)
• An internal oscillator block which provides an
8 MHz clock (±2% accuracy) and an INTRC
source (app rox im ate ly 31 kHz, stable ove r
temperature and VDD), as well as a range of
6 user selectable clock frequencies, between
125 kHz to 4 MHz, for a total of 8 clock
frequenci es. This op tion frees an oscillat or pin for
use as additi ona l general purpos e I/O.
• A Phase Lock Loop (PLL) frequency multiplier,
available to both t he high-speed c rystal and
external oscillator modes, which allows a wide
range of clock speeds from 4 MHz to 48 MHz.
• Asynchronous dual clock operation, allowing the
USB module to run from a high-frequency
oscillator while the rest of the microcontroller is
clocked from an internal low-power oscillator.
Besides its availability as a clock source, the internal
oscill ato r blo ck pro vid es a s t ab le re ference so urc e th at
gives the family additional features for robust
operation:
•Fail-Safe Clock Monitor: This option constantly
monitors the main clock source against a
reference signal provided by the internal oscilla-
tor. If a clock failure occurs, the controller is
switched to the internal oscillator block, allowing
for continued low-speed operation or a safe
application shutdown.
•Two-Speed Start-up: This option allows the
internal oscillator to serve as the clock source
from Power-on Reset , or wake-up from Sleep
mode, until the primary clock source is available.
• PIC18F2455 • PIC18LF2455
• PIC18F2550 • PIC18LF2550
• PIC18F4455 • PIC18LF4455
• PIC18F4550 • PIC18LF4550
PIC18F2455/2550/4455/4550
DS39632A-page 8 Advance Information 2004 Microchip Technology Inc.
1.2 Other Special Features
•Memory Endurance: The Enhanced Flash cells
for both program memory and data EEPROM are
rated to last for many thousands of erase/write
cycles – up to 100,000 for program memory and
1,000,000 for EEPROM. Data retention without
refresh is conservatively estimated to be greater
than 40 year s.
•Self-Programmability: These devices can write
to their own program memory spaces under
internal software control. By using a bootloader
routine, l oc ate d in the p rote cte d Bo ot Blo ck at th e
top of program memory, it becomes possible to
create an application that can update itself in the
field.
•Extended Instruction Set: The
PIC18F2455/2550/4455/4550 family introduces
an option al extensi on to the PIC18 instr uction set,
which adds 8 new instructions and an Indexed
Literal Offset Addressing mode. This extension,
enabled as a device configuration option, has
been specifically designed to optimize re-entrant
applic ation code original ly develo ped in high-l evel
languages, such as C.
•Enhanced CCP Module: In PWM mode, this
module provides 1, 2 or 4 modulated outputs for
controlling half-bridge and full-bridge drivers.
Other featu res inc lu de auto - sh ut d ow n, for
disabl ing PWM output s on interrup t or other selec t
conditions and auto-restart, to reactivate outputs
once the condition has cleared.
•Enhanced Addressable USART: This serial
communication module is capable of standard
RS-232 operation an d provides support for th e LIN
bus protocol. Other enhancements include
Automati c Baud Rate Detectio n an d a 16-bit Baud
Rate Genera tor for improved res olution. Whe n the
microcontroller is using the internal oscillator
block, the EUSART provides stable operation for
applications that talk to the outside world without
using an external crystal (or its accompanying
power requirement).
•10-bit A/D Converter: This module incorporates
programmable acquisition time, allowing for a
channel to be selected and a conversion to be
initiated without waiting for a samp lin g p erio d and
thus, reducing code overhead.
• Dedicated ICD/ICSP Port: Thes e dev ic es
introduce the use of debugger and programming
pins that are not multiplexed with other micro-
controller features. Offered as an option in select
pac kages, thi s feature allo ws users to d evelop I/O
intensive applications while retaining the ability to
program and debug in the circuit.
1.3 Details on Individual Family
Members
Devices in the PIC18F 2455/2550/44 55/4550 famil y are
available in 28-pin and 40/44-pin packages. Block
diagrams for the two groups are shown in Figure 1-1
and Figure 1-2.
The devices are differentiated from each other in six
ways:
1. Flash program memory (24 Kbytes for
PIC18FX455 devices, 32 Kbytes for
PIC18FX550).
2. A/D channels (10 for 28-pin devices, 13 for
40/44-pin devices).
3. I/O ports (3 bidirectional ports and 1 input only
port on 28-pin devices, 5 bidirectional ports on
40/44-pin devices).
4. CCP and Enhanced CCP implementation
(28-pin devices have 2 standard CCP modules,
40/44-pin devices have one standard CCP
module and one ECCP module).
5. Streaming Parallel Port (present only on
40/44-pin devices).
All other feature s for devi ces in th is family are ide ntical.
These are summarized in Table 1-1.
The pinouts for all devices are listed in Table 1-2 and
Table 1-3.
Like all Microchip PIC18 devices, members of the
PIC18F2455/2550/4455/4550 family are available as
both standard and low-voltage devices. Standard
device s with En hanced Fl ash memory, desig nated with
an “F” in the part number (such as PIC18F2550),
accom modate an ope rati ng VDD ra nge of 4 . 2V t o 5. 5V.
Low-voltage parts, designated by “LF” (such as
PIC18LF2550), function over an extended VDD range
of 2.0V to 5.5V.
2004 Microchip Technology Inc. Advance Information DS39632A-page 9
PIC18F2455/2550/4455/4550
TABLE 1-1: DEVICE FEATURES
Features PIC18F2455 PIC18F2550 PIC18F4455 PIC18F4550
Operating Frequency DC – 48 MHz DC – 48 MHz DC – 48 MHz DC – 48 MHz
Program Memo ry (Bytes ) 24576 32768 24576 32768
Program Memo ry (Instruction s) 12288 16384 12288 16384
Data Me mo ry (Byte s) 2048 2048 2048 2048
Data EEPROM Memory (Bytes) 256 256 256 256
Interrupt Sources 19 19 20 20
I/O Ports Ports A, B, C, (E) Ports A, B, C, (E) Ports A, B, C, D, E Ports A, B, C, D, E
Timers 4 4 4 4
Capture/Compare/PWM Modules 1 1 1 1
Enhanced Capture/
Compare/PWM Modules 0011
Serial Communications MSSP,
Enhanced USART MSSP,
Enhanced USART MSSP,
Enhanced USART MSSP,
Enhanced USART
Universal Serial Bus (USB)
Module 1111
Streaming Parallel Port (SPP) No No Yes Yes
10-bit Analog-to-Digital Module 10 Input Channels 10 Input Channels 13 Input Channels 13 Input Channels
Comparators 2 2 2 2
Resets (and Delays) POR, BOR,
RESET Ins truction,
Stack Full,
Stack Underflow
(PWRT, OST),
MCLR (optional),
WDT
POR, BOR,
RESET Instruction,
Stack Full,
Stack Underflow
(PWRT, OST),
MCLR (optional),
WDT
POR, BOR,
RESET Instruction,
Stack Full,
Stack Unde rflo w
(PWRT, OST),
MCLR (optional),
WDT
POR, BOR,
RESET Instruction,
Stack Full,
Stack Unde rflo w
(PWRT, OST),
MCLR (optional),
WDT
Programmable Low -Volta ge
Detect Yes Yes Yes Yes
Programmab le Brown-o ut Rese t Yes Yes Yes Yes
Instruction Set 75 Instructions;
83 with Extended
Instruction Set
enabled
75 Instructions;
83 with Extended
Instruction Set
enabled
75 Instructio ns ;
83 with Extended
Instruction Set
enabled
75 Instructio ns ;
83 with Extended
Instruction Set
enabled
Packages 28-pin PDIP
28-pin SOIC 28-pin PDIP
28-pin SOIC 40-pin PDIP
44-pin QFN
44-pin TQFP
40-pin PDIP
44-pin QFN
44-pin TQFP
PIC18F2455/2550/4455/4550
DS39632A-page 10 Advance Information 2004 Microchip Technology Inc.
FIGURE 1-1: PIC18F 2445/ 2550 ( 28-PIN) BLOCK DI AGR AM
Data Latch
Dat a Memor y
(2Kbytes)
Address Latch
Dat a Addr ess<12 >
12
Access
BSR
44
PCH PCL
PCLATH
8
31 Level Stack
Program Counter
PRODLPRODH
8 x 8 Multiply
8
8
8
ALU<8>
Address Latc h
Program Memory
(24/32 Kbytes)
Data Latch
20
8
8
Table Pointer<21>
inc/dec logic
21
8
Data Bus<8>
Table Latch
8
IR
12
3
ROM Latch
PCLATU
PCU
PORTE
MCLR/VPP/RE3(1)
Note 1: RE3 is multiplexed with MCLR and is only available when the MCLR Resets are disabled.
2: OSC1/CLKI and OSC2/CLKO ar e only available in select o scillator mode s and when the se pins are not being used as dig ital I/O. Refer
to Section 2.0 “Oscillator Configurations” for additional information.
3: RB3 is the alternate pin for CCP2 multiplexing.
W
Instruction Bus <16>
STKPTR Bank
8
8
8
BITOP
FSR0
FSR1
FSR2
inc/dec
Address
12
Decode
logic
EUSART
Comparator MSSP 10-bit
ADC
Timer2Timer1 Timer3Timer0
HLVD
CCP1
BOR Data
EEPROM
USB
Instruction
Decode &
Control
State machine
control signals
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
OSC1(2)
OSC2(2)
VDD,
Brown-out
Reset
Internal
Oscillator
Fail-Safe
Clock Monitor
Reference
Band Gap
VSS
MCLR(1)
Block
INTRC
Oscillator
8 MHz
Oscillator
Single-Supply
Programming
In-Circuit
Debugger
T1OSI
T1OSO
USB Volt age
Regulator
VUSB
PORTB
PORTC
RB0/AN12/INT0/FLT0/SDI/SDA
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2(3)/UOE
RC2/CCP1
RC4/D-/VM
RC5/D+/VP
RC6/TX/CK
RC7/RX/DT/SDO
RB1/AN10/INT1/SCK/SCL
RB2/AN8/INT2/VMO
RB3/AN9/CCP2(3)/VPO
RB4/AN11/KBI0
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
PORTA
RA4/T0CKI/C1OUT/RCV
RA5/AN4/SS/HLVDIN/C2OUT
RA3/AN3/VREF+
RA2/AN2/VREF-/CVREF
RA1/AN1
RA0/AN0
OSC2/CLKO/RA6
2004 Microchip Technology Inc. Advance Information DS39632A-page 11
PIC18F2455/2550/4455/4550
FIGURE 1-2: PIC18F4455/4550 (40/44-PIN) BLOCK DIAGRAM
Instruction
Decode &
Control
Data Latch
Dat a Memory
(2Kbytes)
Address Latch
Data Ad dre ss <12>
12
Access
BSR
44
PCH PCL
PCLATH
8
31 Level Stack
Program Counter
PRODLPRODH
8 x 8 Multiply
8
BITOP 8
8
ALU<8>
Address Latch
Program Memory
(24/32 Kbytes)
Data Latch
20
8
8
Table Pointer<21>
inc/dec logic
21
8
Data Bus<8>
Table Latch
8
IR
12
3
ROM Latch
PORTD
RD0/SPP0
PCLATU
PCU
PORTE
MCLR/VPP/RE3(1)
RE2/AN7/OESPP
RE0/AN5/CK1SPP
RE1/AN6/CK2SPP
Note 1: RE3 is multiplexed with MCLR and is only available when the MCLR Resets are disabled.
2: OSC1/CLKI an d OSC2/CLK O are only availab le in select oscillat or m odes and when these pins ar e not bein g used as digital I/O. Refer
to Sectio n 2.0 “Osc illa tor Config u ratio ns” for additional information.
3: These pins are only available on 44-pin TQFP under certain conditions. Refer to Sec tion 25.9 “Sp ecial I CPORT S Featur es (Desi gnate d
Packages Only)” for additional information.
4: RB3 is the alternate pin for CCP2 multiplexing.
:RD4/SPP4
EUSART
Comparator MSSP 10-bit
ADC
Timer2Timer1 Timer3Timer0
CCP2
HLVD
ECCP1
BOR Data
EEPROM
W
Instruction Bus <16>
STKPTR Bank
8
State machine
control signals
8
8
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
OSC1(2)
OSC2(2)
VDD,
Brown-out
Reset
Internal
Oscillator
Fail-Safe
Clock Monitor Reference
Band Gap
VSS
MCLR(1)
Block
INTRC
Oscillator
8 MHz
Oscillator
Single-Supply
Programming
In-Circuit
Debugger
T1OSI
T1OSO
RD5/SPP5/P1B
RD6/SPP6/P1C
RD7/SPP7/P1D
PORTA
PORTB
PORTC
RA4/T0CKI/C1OUT/RCV
RA5/AN4/SS/HLVDIN/C2OUT
RB0/AN12/INT0/FLT0/SDI/SDA
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2(4)/UOE
RC2/CCP1/P1A
RC4/D-/VM
RC5/D+/VP
RC6/TX/CK
RC7/RX/DT/SDO
RA3/AN3/VREF+
RA2/AN2/VREF-/CVREF
RA1/AN1
RA0/AN0
RB1/AN10/INT1/SCK/SCL
RB2/AN8/INT2/VMO
RB3/AN9/CCP2(4)/VPO
OSC2/CLKO/RA6
RB4/AN11/KBI0/CSSPP
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
USB
FSR0
FSR1
FSR2
inc/dec
Address
12
Decode
logic
USB Volt age
Regulator
VUSB
ICRST(3)
ICPGC(3)
ICPGD(3)
ICPORTS(3)
PIC18F2455/2550/4455/4550
DS39632A-page 12 Advance Information 2004 Microchip Technology Inc.
TABLE 1-2: PIC18F2455/2550 PINOUT I/O DESCRIPTIONS
Pin Name
Pin
Number Pin
Type Buffer
Type Description
PDIP,
SOIC
MCLR/VPP/RE3
MCLR
VPP
RE3
1I
P
I
ST
ST
Master Clear (input) or programming voltage (input).
Master Clear (Reset) input. This pin is an active-low
Reset to the device.
Programmi ng vol t ag e inpu t.
Digital input.
OSC1/CLKI
OSC1
CLKI
9I
IAnalog
Analog
Oscillator crystal or external clock input.
Oscillator crystal input or external clock source input.
External clock source input. Always associated with pin
function OSC1. (See OSC2/CLKO pins.)
OSC2/CLKO/RA6
OSC2
CLKO
RA6
10 O
O
I/O
—
—
TTL
Oscillator crystal or clock output.
Oscillator crystal output. Connects to crystal or resonator in
Crystal Oscillator mode.
In select modes , OS C2 pin outpu t s C L KO w hi ch has 1/4 the
frequency of OSC1 and denotes the instruction cycle rate.
General purpose I/O pin.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Alternate assignment for CCP2 when CCP2MX configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX configuration bit is set.
2004 Microchip Technology Inc. Advance Information DS39632A-page 13
PIC18F2455/2550/4455/4550
PORTA is a bidirectional I/O port.
RA0/AN0
RA0
AN0
2I/O
ITTL
Analog Digital I/O.
Analog input 0.
RA1/AN1
RA1
AN1
3I/O
ITTL
Analog Digital I/O.
Analog input 1.
RA2/AN2/VREF-/CVREF
RA2
AN2
VREF-
CVREF
4I/O
I
I
O
TTL
Analog
Analog
—
Digital I/O.
Analog input 2.
A/D reference voltage (low) input.
Analog comparator reference output.
RA3/AN3/VREF+
RA3
AN3
VREF+
5I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog input 3.
A/D refe rence voltage (high ) input.
RA4/T0CKI/C1OUT/RCV
RA4
T0CKI
C1OUT
RCV
6I/O
I
O
I
TTL
ST
—
TTL
Digital I/O.
Timer0 external clock input.
Comparator 1 output.
External USB transceiver RCV input.
RA5/AN4/SS/
HLVDIN/C2OUT
RA5
AN4
SS
HLVDIN
C2OUT
7
I/O
I
I
I
O
TTL
Analog
TTL
Analog
—
Digital I/O.
Analog input 4.
SPI slave select input.
High/Low-Voltage Detect input.
Comparator 2 output.
RA6 — — — See t he OSC2/CL KO/RA6 pin.
TABLE 1-2: PIC18F2455/2550 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin
Number Pin
Type Buffer
Type Description
PDIP,
SOIC
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Alternate assignment for CCP2 when CCP2MX configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX configuration bit is set.
PIC18F2455/2550/4455/4550
DS39632A-page 14 Advance Information 2004 Microchip Technology Inc.
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
RB0/AN12/INT0/FLT0/
SDI/SDA
RB0
AN12
INT0
FLT0
SDI
SDA
21
I/O
I
I
I
I
I/O
TTL
Analog
ST
ST
ST
ST
Digital I/O.
Analog input 12.
External interrupt 0.
PWM Fault input (CCP1 module).
SPI data in.
I2C data I/O.
RB1/AN10/INT1/SCK/
SCL
RB1
AN10
INT1
SCK
SCL
22
I/O
I
I
I/O
I/O
TTL
Analog
ST
ST
ST
Digital I/O.
Analog input 10.
External interrupt 1.
Synchronous serial clock input/output for SPI™ mode.
Synchronous serial clock input/ou tput for I2C™ mode.
RB2/AN8/INT2/VMO
RB2
AN8
INT2
VMO
23 I/O
I
I
O
TTL
Analog
ST
—
Digital I/O.
Analog input 8.
External interrupt 2.
External USB transceiver VMO output.
RB3/AN9/CCP2/VPO
RB3
AN9
CCP2(1)
VPO
24 I/O
I
I/O
O
TTL
TTL
ST
—
Digital I/O.
Analog input 9.
Capture 2 input/Compare 2 output/PWM 2 output.
External USB transceiver VPO output.
RB4/AN11/KBI0
RB4
AN11
KBI0
25 I/O
I
I
TTL
Analog
TTL
Digital I/O.
Analog input 11.
Interrupt-on-change pin.
RB5/KBI1/PGM
RB5
KBI1
PGM
26 I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
Low-Vo ltage ICSP™ Programming enable pin.
RB6/KBI2/PGC
RB6
KBI2
PGC
27 I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming clock pin.
RB7/KBI3/PGD
RB7
KBI3
PGD
28 I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.
TABLE 1-2: PIC18F2455/2550 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin
Number Pin
Type Buffer
Type Description
PDIP,
SOIC
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Alternate assignment for CCP2 when CCP2MX configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX configuration bit is set.
2004 Microchip Technology Inc. Advance Information DS39632A-page 15
PIC18F2455/2550/4455/4550
PORTC is a bidirectional I/O port.
RC0/T1OSO/T13CKI
RC0
T1OSO
T13CKI
11 I/O
O
I
ST
—
ST
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
RC1/T1OSI/CCP2/UOE
RC1
T1OSI
CCP2(2)
UOE
12 I/O
I
I/O
—
ST
CMOS
ST
—
Digital I/O.
Timer1 oscillator input.
Capture 2 input/Compare 2 output/PWM 2 output.
External USB transceiver OE output.
RC2/CCP1
RC2
CCP1
13 I/O
I/O ST
ST Digital I/O.
Capture 1 input/Compare 1 output/PWM 1 output.
RC4/D-/VM
RC4
D-
VM
15 I/O
I/O
I
TTL
—
TTL
Digital input.
USB differential minus line (input/output).
External USB transceiver VM input.
RC5/D+/VP
RC5
D+
VP
16 I/O
I/O
O
TTL
—
TTL
Digital input.
USB differential plus line (input/output).
External USB transceiver VP input.
RC6/TX/CK
RC6
TX
CK
17 I/O
O
I/O
ST
—
ST
Digital I/O.
EUSART asy nc hronous transmit.
EUSART sy nc hron ous clock (se e RX/DT).
RC7/RX/DT/SDO
RC7
RX
DT
SDO
18 I/O
I
I/O
O
ST
ST
ST
—
Digital I/O.
EUSART asy nc hro nou s rece iv e.
EUSART sy nc hron ous dat a (se e TX/CK) .
SPI™ data out.
RE3 — — — See MCLR/VPP/RE3 pin.
VUSB 14 O — Internal USB 3.3V voltage regulator.
VSS 8, 19 P — Ground reference for logic and I/O pins.
VDD 20 P — Positive supply for logic and I/O pins.
TABLE 1-2: PIC18F2455/2550 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin
Number Pin
Type Buffer
Type Description
PDIP,
SOIC
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Alternate assignment for CCP2 when CCP2MX configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX configuration bit is set.
PIC18F2455/2550/4455/4550
DS39632A-page 16 Advance Information 2004 Microchip Technology Inc.
TABLE 1-3: PIC18F4455/4550 PINOUT I/O DESCRIPTIONS
Pin Name Pin Number Pin
Type Buffer
Type Description
PDIP QFN TQFP
MCLR/VPP/RE3
MCLR
VPP
RE3
11818 I
P
I
ST
ST
Master Clear (input) or programming voltage (input).
Master Clear (Reset) input. This pin is an
active-low Reset to the device.
Programming voltage input.
Digital input.
OSC1/CLKI
OSC1
CLKI
13 32 30 I
IAnalog
Analog
Oscillator crystal or external clock input.
Oscillator crystal input or external clock source input.
External clock source input. Always associated with
pin function OSC1. (See OSC2/CLKO pins.)
OSC2/CLKO/RA6
OSC2
CLKO
RA6
14 33 31 O
O
I/O
—
—
TTL
Oscill ator cry stal or clock out put.
Oscill ator cry stal output. Connect s to crys tal or
resonator in Crystal Oscillator mode.
In RC mode, OSC2 pin outputs CLKO which has 1/4
the frequency of OSC1 and denotes the instruction
cycle rate.
General purpose I/O pin.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Alternate assignment for CCP2 when CCP2MX configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX configuration bit is set.
3: These pins are No Connect unless the ICPRT configuration bit is set. For NC/ICPORTS, the pin is No
Connect unless ICPRT is set and the DEBUG configuration bit is cleared.
2004 Microchip Technology Inc. Advance Information DS39632A-page 17
PIC18F2455/2550/4455/4550
PORTA is a bidirectional I/O port.
RA0/AN0
RA0
AN0
21919
I/O
ITTL
Analog Digital I/O.
Analog input 0.
RA1/AN1
RA1
AN1
32020
I/O
ITTL
Analog Digital I/O.
Analog input 1.
RA2/AN2/VREF-/
CVREF
RA2
AN2
VREF-
CVREF
42121
I/O
I
I
O
TTL
Analog
Analog
—
Digital I/O.
Analog input 2.
A/D refere nce v o ltage (low) input .
Analog comparator reference output.
RA3/AN3/VREF+
RA3
AN3
VREF+
52222
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog input 3.
A/D reference voltage (high) input.
RA4/T0CKI/C1OUT/
RCV
RA4
T0CKI
C1OUT
RCV
62323
I/O
I
O
I
TTL
ST
—
TTL
Digital I/O.
Timer0 external clock input.
Comparator 1 output.
External USB transceiver RCV input.
RA5/AN4/SS/
HLVDIN/C2OUT
RA5
AN4
SS
HLVDIN
C2OUT
72424
I/O
I
I
I
O
TTL
Analog
TTL
Analog
—
Digital I/O.
Analog input 4.
SPI slave select input.
High/Low-Voltage Detect input.
Comparator 2 output.
RA6 — — — — — See the OSC2/CLKO/RA6 pin .
TABLE 1-3: PIC18F4455/4550 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name Pin Number Pin
Type Buffer
Type Description
PDIP QFN TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Alternate assignment for CCP2 when CCP2MX configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX configuration bit is set.
3: These pins are No Connect unless the ICPRT configuration bit is set. For NC/ICPORTS, the pin is No
Connect unless ICPRT is set and the DEBUG configuration bit is cleared.
PIC18F2455/2550/4455/4550
DS39632A-page 18 Advance Information 2004 Microchip Technology Inc.
PORTB is a bidirectional I/O port. PORTB can be
software programmed for internal weak pull-ups on all
inputs.
RB0/AN12/INT0/
FLT0/SDI/SDA
RB0
AN12
INT0
FLT0
SDI
SDA
33 9 8
I/O
I
I
I
I
I/O
TTL
Analog
ST
ST
ST
ST
Digital I/O.
Analog input 12.
External interrupt 0.
Enhanced PWM Fau lt inpu t (ECCP1 mo dul e).
SPI™ data in.
I2C™ data I/O.
RB1/AN10/INT1/SCK/S
CL RB1
AN10
INT1
SCK
SCL
34 10 9
I/O
I
I
I/O
I/O
TTL
Analog
ST
ST
ST
Digital I/O.
Analog input 10.
External interrupt 1.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C mode.
RB2/AN8/INT2/VMO
RB2
AN8
INT2
VMO
35 11 10 I/O
I
I
O
TTL
Analog
ST
—
Digital I/O.
Analog input 8.
External interrupt 2.
External USB transceiver VMO output.
RB3/AN9/CCP2/VPO
RB3
AN9
CCP2(1)
VPO
36 12 11 I/O
I
I/O
O
TTL
TTL
ST
—
Digital I/O.
Analog input 9.
Capture 2 input/Compare 2 output/PWM 2 output.
External USB transceiver VPO output.
RB4/AN11/KBI0/CSSPP
RB4
AN11
KBI0
CSSPP
37 14 14 I/O
I
I
O
TTL
Analog
TTL
—
Digital I/O.
Analog input 11.
Interrupt-on-change pin.
SPP chip select control output.
RB5/KBI1/PGM
RB5
KBI1
PGM
38 15 15 I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
Low-Voltage ICSP™ Programming enable pin.
RB6/KBI2/PGC
RB6
KBI2
PGC
39 16 16 I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming clock pin.
RB7/KBI3/PGD
RB7
KBI3
PGD
40 17 17 I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.
TABLE 1-3: PIC18F4455/4550 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name Pin Number Pin
Type Buffer
Type Description
PDIP QFN TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Alternate assignment for CCP2 when CCP2MX configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX configuration bit is set.
3: These pins are No Connect unless the ICPRT configuration bit is set. For NC/ICPORTS, the pin is No
Connect unless ICPRT is set and the DEBUG configuration bit is cleared.
2004 Microchip Technology Inc. Advance Information DS39632A-page 19
PIC18F2455/2550/4455/4550
PORTC is a bidirectional I/O port.
RC0/T1OSO/T13CKI
RC0
T1OSO
T13CKI
15 34 32 I/O
O
I
ST
—
ST
Digital I/O.
Timer1 oscil lat or outpu t.
Timer1/Timer3 external clock input.
RC1/T1OSI/CCP2/
UOE
RC1
T1OSI
CCP2(2)
UOE
16 35 35
I/O
I
I/O
O
ST
CMOS
ST
—
Digital I/O.
Timer1 oscil lat or inpu t.
Capture 2 input/Compare 2 output/PWM 2 output.
External USB transceiver OE output.
RC2/CCP1/P1A
RC2
CCP1
P1A
17 36 36 I/O
I/O
O
ST
ST
TTL
Digital I/O.
Capture 1 input/Compare 1 output/PWM 1 output.
Enhanced CCP1 PWM output, channel A.
RC4/D-/VM
RC4
D-
VM
23 42 42 I/O
I/O
I
TTL
—
TTL
Digital input.
USB differential minus line (input/output).
External USB transceiver VM input.
RC5/D+/VP
RC5
D+
VP
24 43 43 I/O
I/O
I
TTL
—
TTL
Digital input.
USB differential plus line (input/output).
External USB transceiver VP input.
RC6/TX/CK
RC6
TX
CK
25 44 44 I/O
O
I/O
ST
—
ST
Digital I/O.
EUSART asyn chronous transmit.
EUSART synchronous clock (see RX/DT).
RC7/RX/DT/SDO
RC7
RX
DT
SDO
26 1 1 I/O
I
I/O
O
ST
ST
ST
—
Digital I/O.
EUSART asyn chro nous receive.
EUSART synchronous data (see TX/CK).
SPI data out.
TABLE 1-3: PIC18F4455/4550 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name Pin Number Pin
Type Buffer
Type Description
PDIP QFN TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Alternate assignment for CCP2 when CCP2MX configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX configuration bit is set.
3: These pins are No Connect unless the ICPRT configuration bit is set. For NC/ICPORTS, the pin is No
Connect unless ICPRT is set and the DEBUG configuration bit is cleared.
PIC18F2455/2550/4455/4550
DS39632A-page 20 Advance Information 2004 Microchip Technology Inc.
PORTD is a bidirectional I/O port or a Streaming
Parallel Port (SPP). These pins have TTL input buffers
when the SPP module is enabled.
RD0/SPP0
RD0
SPP0
19 38 38 I/O
I/O ST
TTL Digital I/O.
Streaming Parallel Port data.
RD1/SPP1
RD1
SPP1
20 39 39 I/O
I/O ST
TTL Digital I/O.
Streaming Parallel Port data.
RD2/SPP2
RD2
SPP2
21 40 40 I/O
I/O ST
TTL Digital I/O.
Streaming Parallel Port data.
RD3/SPP3
RD3
SPP3
22 41 41 I/O
I/O ST
TTL Digital I/O.
Streaming Parallel Port data.
RD4/SPP4
RD4
SPP4
27 2 2 I/O
I/O ST
TTL Digital I/O.
Streaming Parallel Port data.
RD5/SPP5/P1B
RD5
SPP5
P1B
28 3 3 I/O
I/O
O
ST
TTL
—
Digital I/O.
Streaming Parallel Port data.
Enhanced CCP1 PWM output, channel B.
RD6/SPP6/P1C
RD6
SPP6
P1C
29 4 4 I/O
I/O
O
ST
TTL
—
Digital I/O.
Streaming Parallel Port data.
Enhanced CCP1 PWM output, channel C.
RD7/SPP7/P1D
RD7
SPP7
P1D
30 5 5 I/O
I/O
O
ST
TTL
—
Digital I/O.
Streaming Parallel Port data.
Enhanced CCP1 PWM output, channel D.
TABLE 1-3: PIC18F4455/4550 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name Pin Number Pin
Type Buffer
Type Description
PDIP QFN TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Alternate assignment for CCP2 when CCP2MX configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX configuration bit is set.
3: These pins are No Connect unless the ICPRT configuration bit is set. For NC/ICPORTS, the pin is No
Connect unless ICPRT is set and the DEBUG configuration bit is cleared.
2004 Microchip Technology Inc. Advance Information DS39632A-page 21
PIC18F2455/2550/4455/4550
PORTE is a bidirectional I/O port.
RE0/AN5/CK1SPP
RE0
AN5
CK1SPP
82525
I/O
I
O
ST
Analog
—
Digital I/O.
Analog input 5.
SPP clock 1 output.
RE1/AN6/CK2SPP
RE1
AN6
CK2SPP
92626
I/O
I
O
ST
Analog
—
Digital I/O.
Analog input 6.
SPP clock 2 output.
RE2/AN7/OESPP
RE2
AN7
OESPP
10 27 27 I/O
I
O
ST
Analog
—
Digital I/O.
Analog input 7.
SPP output enable output.
RE3 — — — — — See MCLR /VPP/RE3 pin.
VSS 12, 31 6, 30,
31 6, 29 P — Ground reference for logic and I/O pins.
VDD 11, 32 7, 8,
28, 29 7, 28 P — Positive supply for logic and I/O pins.
VUSB 18 37 37 O — Internal USB 3.3V voltage regulator output.
NC/ICCK/ICPGC
ICCK
ICPGC
——12I/O
I/O ST
ST
No connect or dedicated ICD/ICSP port clock.(3)
In-Circ uit Debugg er cl ock.
ICSP programming clock.
NC/ICDT/ICPGD
ICDT
ICPGD
——13I/O
I/O ST
ST
No connect or dedicated ICD/ICSP port clock.(3)
In-Circuit Debugger data.
ICSP programming data.
NC/ICRST/ICVPP
ICRST
ICVPP
——33 I
P—
—
No connect or dedicated ICD/ICSP port Reset.(3)
Master Clear (Reset) input.
Programming voltage input.
NC/ICPORTS
ICPORTS — — 34 P — No connect or 28-pin device emulation.(3)
Enable 28-pin device emulation when connected
to VSS.
NC — 13 — — — No connect.
TABLE 1-3: PIC18F4455/4550 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name Pin Number Pin
Type Buffer
Type Description
PDIP QFN TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Alternate assignment for CCP2 when CCP2MX configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX configuration bit is set.
3: These pins are No Connect unless the ICPRT configuration bit is set. For NC/ICPORTS, the pin is No
Connect unless ICPRT is set and the DEBUG configuration bit is cleared.
PIC18F2455/2550/4455/4550
DS39632A-page 22 Advance Information 2004 Microchip Technology Inc.
NOTES:
2004 Microchip Technology Inc. Advance Information DS39632A-page 23
PIC18F2455/2550/4455/4550
2.0 OSCILLATOR
CONFIGURATIONS
2.1 Overview
Devices in the PIC18F2455/2550/4455/4550 family
incorporate a different oscillator and microcontroller
clock sy st em than previous PIC 1 8F d evices. The add i-
tion of the USB module, with its unique requirements
for a stable clock source, make it necessary to provide
a separate clock source that is compliant with both
USB low-speed and full speed specifications.
To accommodate these requirements,
PIC18F2455/2550/4455/4550 devices include a new
clock branch to provide a 48 MHz clock for full speed
USB operat ion. Since it is driv en from the primar y clock
source, an additional system of prescalers and
postscalers has been added to accommodate a wide
range of oscillator frequencies. An overview of the
oscillator structure is shown in Figure 2-1.
Other oscillator features used in PIC18 enhanced
microcontrollers, such as the internal oscillator block
and clock switching, remain the same. They are
discussed later in this chapter.
2.1.1 OSCILLATOR CONTROL
The operation of the oscillator in
PIC18F2455/2550/4455/4550 devices is controlled
through two conf iguration reg isters and two control re g-
isters. Configuration Registers 1L and 1H select the
oscillator mode and USB prescaler/postscaler options.
As configuration bits, these are set when the device is
programmed and left in that configuration until the
dev ice is reprogrammed.
The OSCCON register (Register 2-2) selects the Active
Clock mode; it is primarily used in controlling clock
switching in power managed modes. Its use is
discussed in Section 2.4.1 “Oscillator Control
Register”.
The OSCTUNE register (Register 2-1) is used to trim
the INTRC frequency source, as well as select the
low-frequency clock source that drives several special
features. Its use is described in Section 2.2.5.2
“OSCTUNE Register”.
2.2 Oscillator Types
PIC18F2455/2550/ 4455/4550 devices can be operated
in twel ve dis tin ct oscil lat or m ode s. In contra st wi th p re-
vious PIC18 enhanced microcontrollers, four of these
modes involve the use of two oscillator types at once.
Users can program the FOSC3:FOSC0 configuration
bits to select one of these modes:
1. XT Crystal/Resonator
2. XTPLL Crystal/Resonator with PLL enabled
3. HS High-Speed Crystal/Resonator
4. HSPLL High-Speed Crystal/Resonator
with PLL enabled
5. EC External Clock with FOSC/4 output
6. ECIO External Clock with I/O on RA6
7. ECPLL External Cl oc k with PLL ena ble d
and FOSC/4 output on RA6
8. ECPIO Ex tern al Cl ock wi th PLL ena ble d,
I/O on RA6
9. INTHS Internal Oscillator used as
microcontroller clock source, HS
Oscillator used as USB clock source
10. INTXT Internal Oscillator used as
microcontroller clock source, XT
Oscillator used as USB clock source
11. INTIO Internal Oscillator used as
microcontroller clock source, EC
Oscillator used as USB clock source,
digi tal I/O on RA6
12. INTCKO Internal Oscillator used as
microcontroller clock source, EC
Oscillator used as USB clock source,
FOSC/4 outp ut on RA6
2.2.1 OSCILLATOR MODES AND
USB OPERATION
Because of the unique requirement s of the USB module,
a different approach to clock operation is necessary. In
previous PICmicro® devices, all core and peripheral
clocks were driven by a single oscillator source; the
usual sources were primary, secondary or the internal
oscillator. With PIC18F2455/2550/4455/4550 devices,
the primary oscillator becomes part of the USB module
and cannot be associated to any other clock source.
Thus, the USB module must be clocked from the primary
clock source; however, the microcontroller core and
other peripherals can be separately clocked from the
secondary or internal oscillators as before.
Because of the timing requirements imposed by USB,
an int erna l c lock of either 6 MHz or 48 MHz is require d
while the USB module is enabled. Fortunately, the
microcontroller and other peripherals are not required
to run at this clock speed when using the primary
oscillator. There are numerous options to achieve the
USB module clock requi rement and sti ll provide fl exibil-
ity f or cloc king the r est of the devi ce from the pri mary
oscillator source. These are detailed in Section 2.3
“Oscillator Settings for USB”.
PIC18F2455/2550/4455/4550
DS39632A-page 24 Advance Information 2004 Microchip Technology Inc.
FIGURE 2-1: PIC18F2455/2550/4455/4550 CLOCK DIAGRAM
PIC18F4550
FOSC3:FOSC0
Secondary Oscillator
T1OSCEN
Enable
Oscillator
T1OSO
T1OSI
Clock Source Option
for other Modules
OSC1
OSC2
Sleep
Primary Oscillator
XT, HS, EC, ECIO
T1OSC
CPU
Peripherals
IDLEN
INTOSC Po stscaler
MUX
MUX
8 MHz
4 MHz
2 MHz
1 MHz
500 kHz
125 kHz
250 kHz
OSCCON<6:4>
111
110
101
100
011
010
001
000
31 kHz
INTRC
Source
Internal
Oscillator
Block
WDT, PWRT, FSCM
8 MHz
Internal Oscillator
(INTOSC)
OSCCON<6:4>
Clock
Control
OSCCON<1:0>
Source
8 MHz
31 kHz (INTRC) 0
1
OSCTUNE<7>
and Two-Speed Start-up
96 MHz
PLL
PLLDIV
CPUDIV
0
1
0
1
÷ 2
PLL Prescaler
MUX
111
110
101
100
011
010
001
000
÷ 1
÷ 2
÷ 3
÷ 4
÷ 5
÷ 6
÷ 10
÷ 12
11
10
01
00
PLL Postscaler
÷ 2
÷ 3
÷ 4
÷ 6
USB
USBDIV
FOSC3:FOSC0
HSPLL, ECPLL,
11
10
01
00
Oscillator Post scaler
÷ 1
÷ 2
÷ 3
÷ 4
CPUDIV
1
0
Peripheral
FSEN
÷ 4
USB Clock Source
XTPLL, ECPIO
Primary
Clock
2004 Microchip Technology Inc. Advance Information DS39632A-page 25
PIC18F2455/2550/4455/4550
2.2.2 CRYSTAL OSCILLATOR/CERAMIC
RESONATORS
In HS, HSPLL, XT and XTPLL Oscillator modes, a
crystal or ceramic resonator is connected to the OSC1
and OSC2 pins to establish oscillation. Figure 2-2
shows the pin connections.
The oscillator design requires the use of a parallel cut
crystal.
FIGURE 2-2: CRYSTAL/CERAMIC
RESONATOR OPERATION
(XT, HS OR HSPLL
CONFIGURATION)
TABLE 2-1: CAPACITOR SELECTION FOR
CERAMIC RESONATORS
T ABLE 2-2: CAPACITOR SELECTION FOR
CRYST AL OSCILLATOR
An internal postscaler allows users to select a clock
frequency other than that of the crystal or resonator.
Frequency division is determined by the CPUDIV
configuration bits. Users may select a clock frequency
of the oscillator frequency, or 1/2, 1/3 or 1/4 of the
frequency.
An external clock may also be used when the micro-
controller is in HS Oscillator mode. In this case, the
OSC2/CLKO pin is left open (Figure 2-3).
Note: Use of a series cut crystal may give a fre-
quency out of the crystal manufacturer’s
specifications.
Typical Capacitor Values Used:
Mode Freq OSC1 OSC2
XT 4.0 MHz 33 pF 33 pF
HS 8.0 MHz
16.0 MHz 27 pF
22 pF 27 pF
22 pF
Capacitor values are for design guidance only.
These capacitors were tested with the resonators
listed below for basic start-up and operation. These
values are no t optimized.
Dif ferent cap acitor values may be required to produc e
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected
VDD and temperature range for the application.
See the notes on page 25 for additional information.
Resonators Used:
4.0 MHz
8.0 MHz
16.0 MHz
Note 1: See Table 2-1 and Table 2-2 for initial values of
C1 and C2.
2: A series resistor (RS) may be required for AT
strip cut crystals.
3: RF varies with the oscillator mode chosen.
C1(1)
C2(1)
XTAL
OSC2
OSC1
RF(3)
Sleep
To
Logic
PIC18FXXXX
RS(2)
Internal
Osc Type Crystal
Freq
Typical Cap acitor V alues
Tested:
C1 C2
XT 4 MHz 27 pF 27 pF
HS 4 MHz 27 pF 27 pF
8 MHz 22 pF 22 pF
20 MHz 15 pF 15 pF
Capacitor values are for design guidance only.
These capacito rs were tested with th e crystals listed
below for basic st a r t-up a nd ope rati on. These values
are not optimized.
Dif ferent capa citor values m ay be required to prod uce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected
VDD and temperature range for the application.
See the notes following this table for additional
information. Crystals Used:
4 MHz
8 MHz
20 MHz
Note 1: Higher capacit ance inc reases the st abilit y
of oscillator but also increases the
start-up time.
2: When operating below 3V VDD, or when
using certain ceramic resonators at any
voltage, it may be necessary to use the
HS mode or switch to a crystal oscillator.
3: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external
components.
4: Rs may be required to avoid overdriving
crystals with low drive level specification.
5: Always veri fy os ci lla tor performance ov er
the VDD and temperature range that is
expected for the application.
PIC18F2455/2550/4455/4550
DS39632A-page 26 Advance Information 2004 Microchip Technology Inc.
FIGURE 2-3: EXTERNAL CLOCK INPUT
OPERATION (HS OSC
CONFIGURATION)
2.2.3 EXTERNAL CLOCK INPUT
The EC, ECIO, ECPLL and ECPIO Oscillator modes
require an external cl ock sourc e to be conne cted to the
OSC1 pin. There is no oscillator start-up time required
after a Power-on Reset or after an exit from Sleep
mode.
In the EC and ECPLL Oscillator modes, the oscillator
frequency divided by 4 is available on the OSC2 pin.
This signal may be used for test purposes or to
synchronize other logic. Figure 2-4 shows the pin
connections for the EC Oscillator mode.
FIGURE 2-4: EXTERNAL CLOCK
INPUT OPERATION
(EC AND ECPLL
CONFIGURATION)
The ECIO and ECPIO Oscillator modes function like
the EC and ECPLL modes, except that the OSC2 pin
becomes an additional general purpose I/O pin. The
I/O pin becomes bit 6 of PORTA (RA6). Figure 2-5
shows the pin connections for the ECIO Oscillator
mode.
FIGURE 2-5: EXTERNAL CLOCK
INPUT OPERATION
(ECIO AND ECPIO
CONFIGURATION)
The internal postscaler for reducing clock frequency in
XT and HS modes is also available in EC and ECIO
modes.
2.2.4 PLL FREQUENCY MULTIPLIER
PIC18F2 455/2550/4 255/4550 dev ices includ e a Phase
Locked Loop (PLL) circuit. This is provided specifically
for USB applications with lower speed oscillators and
can also be used as a microcontroll er clock so urce.
The PLL is enabled in HSPLL, XTPLL, ECPLL and
ECPIO Oscillator modes. It is designed to produce a
fixed 96 MHz reference clock from a fixed 4 MHz input;
the output can then be divided and used for both the
USB and the microcontroller core clock. Because the
PLL has a fixed frequency input and output, there are
eight prescaling options to match the oscillator input
frequency to the PLL.
Ther e i s al so a s epara te pos tscal er op tio n for de rivi ng
the microcontroller clock from the PLL. This allows the
USB peripheral and microcontroller to use the same
oscillator input and still operate at different clock
speeds . In contrast to the post scaler for XT, HS and EC
modes, the available options are 1/2, 1/3, 1/4 and 1/6
of the PLL output.
The HSPLL, ECPLL and ECPIO modes make use of
the HS mode oscillator for frequencies up to 48 MHz.
The pr es ca ler div id es the os ci ll ator inp ut by up to 12 to
produ ce the 4 MHz drive for the PLL. The XTPLL mod e
can only use an inp ut frequency of 4 MHz, which drive s
the PLL directly.
FIGURE 2-6: PLL BLOCK DIAGRAM
(HS MODE)
OSC1
OSC2
Open
Clock from
Ext. System PIC18FXXXX
(HS Mode)
OSC1/CLKI
OSC2/CLKO
FOSC/4
Clock from
Ext. System PIC18FXXXX
OSC1/CLKI
I/O (OSC2)
RA6
Clock from
Ext. System PIC18FXXXX
MUX
VCO
Loop
Filter
and
Prescaler
OSC2
OSC1
PLL Enable
FIN
FOUT
SYSCLK
Phase
Comparator
HS/EC/ECIO/XT Oscillator Enable
÷24
(from Configuration Register 1H)
Oscillator
2004 Microchip Technology Inc. Advance Information DS39632A-page 27
PIC18F2455/2550/4455/4550
2.2.5 INTERNAL OSCILLATOR BLOCK
The PIC18F2455/2550/4455/4550 devices include an
internal oscillator block which generates two different
clock signals; either can be used as the microcontrol-
ler’s cloc k source. If the USB periphe ral is not u sed, the
internal oscillator may eliminate the need for external
oscillator cir cuits on the OSC1 and/or OSC2 pins.
The main output (INTOSC) is an 8 MHz clock source,
which can be used to directly drive the device clock. It
also drives the INTOSC postscaler, which can provide
a range of clock frequencies from 31 kHz to 4 MHz.
The IN TOSC o utput is enabled w hen a cloc k freque ncy
from 125 kHz to 8 MHz is selected.
The other clock source is the internal RC oscillator
(INTRC), which provides a nominal 31 kHz output.
INTRC is enabled if it is selected as the device clock
sour ce; it is also ena bled automatic ally when an y of the
following are enabled:
• Power-up Timer
• Fail-Safe Clock Monitor
• Watchdog Timer
• Two-Speed Start-up
These features are discussed in greater detail in
Section 25.0 “Special Features of the CPU”.
The clock source frequency (INTOSC direct, INTRC
direct or INTOSC postscaler) is selected by configuring
the IRCF bits of the OSCCON register (page 32).
2.2.5.1 Internal Oscillator Modes
When the internal oscillator is used as the microcontrol-
ler clock source, one of the other oscillator modes
(external clock or external crystal/resonator) must be
used as the USB clock source. The choice of USB
clock source is determined by the particular internal
oscillator mode.
There are four distinct modes available:
1. INTHS mode: The USB clock is provided by the
oscillator in HS mode.
2. INTXT mode: The USB clock is provided by the
osci llat or in XT mode.
3. INTCKO mode: The USB clock is provided by an
external clock input on OSC1/CLKI; the
OSC2/CLKO pin outputs FOSC/4.
4. INTIO mode: The USB clock is provided by an
external clock input on OSC1/CLKI; the
OSC2/CLKO pin functions as a digit al I/O (RA6).
Of these four modes, only INTIO mode frees up an
additional pin (OSC2/CLKO/RA6) for port I/O use.
2.2.5.2 OSCTUNE Register
The internal oscillator’s output has been calibrated at
the factory but can be adjusted in the user’s applica-
tion. This is done by writing to the OSCTUNE register
(Register 2-1). The tuning sensitivity is constant
throughout the tuning range.
When the O SC TUN E reg is ter is mo di fied , the IN T O SC
and INTRC frequencies will begin shifting to the new
frequency. The INTRC clock will reach the new
frequency within 8 clock cycles (approximately
8*32µs = 256 µs). The INTOSC clock will stabilize
within 1 ms. Code ex ecution continu es during this s hift.
There is no indication that the shift has occurred.
The OSCTUNE register also contains the INTSRC bit.
The INTSRC bit allows users to select which internal
oscillator provides the clock source when the 31 kHz
frequenc y opt ion is se lected . This is cove red in greater
detail in Section 2.4.1 “Oscillat or Control Register”.
2.2.5.3 Internal Oscillator Output Frequency
and Drift
The internal oscillator block is calibrated at the factory
to produce an INTOSC output frequency of 8.0 MHz.
However, this frequency may drift as VDD or tempera-
ture changes, which can affect the controller operation
in a variety of ways.
The low -fre qu enc y IN TRC o sc il lat or o pe rates i ndepen-
dently of the INT OSC so urce. Any ch anges in INTO SC
across voltage and temperature are not necessarily
reflected by changes in INTRC and vice versa.
PIC18F2455/2550/4455/4550
DS39632A-page 28 Advance Information 2004 Microchip Technology Inc.
REGISTER 2-1: OSCTUNE: OSCILLATOR TUNING REGISTER
2.2.5.4 Compensating for INTOSC Drift
It is possible to adjust the INTOSC frequency by
modifying the value in the OSCTUNE register. This has
no effect on the INTRC clock source frequency.
Tuning the INTOSC source requires knowing when to
make the adjustment, in which direction it should be
made and in some cases, how large a change is
needed. When using the EUSART, for example, an
adjustm ent may be requir ed when it begins to generate
framing errors or receives data with errors while in
Asynchronous mode. Framing errors indicate that the
device clock frequency is too high; to adjust for this,
decrement the value in OSCTUNE to reduce the clock
frequency. On the other hand, errors in data may sug-
gest that the clock speed is too low; to compensate,
increm ent OSC T UNE to incr eas e the clo ck freque nc y.
It is also possible to verify device clock speed against
a reference clock. Two timers may be used; one timer
is clocked by the peripheral clock, while the other is
clocked by a fixed reference source, such as the
T i mer1 o scillato r. Both time rs are cleare d, but t he timer
clocked by the reference generates interrupts. When
an interrupt occurs, the internally clocked timer is read
and both timers are cleared. If the internally clocked
timer value is greater than expected, then the internal
oscillator block is running too fast. To adjust for this,
decr em ent the OSCT U NE register.
Finally, a CCP mod ule ca n us e fre e run nin g Timer1 (or
Timer 3), cl oc ked by the int erna l os cil la t or bl ock and an
external event with a known period (i.e., AC power fre-
quency). The time of the first event is captured in the
CCPRxH:CCPRxL registers and is recorded for use
later. When the second event causes a capture, the
time of the firs t eve nt i s su btra cte d fro m the tim e of th e
second event. Since the period of the external event is
known, the time difference between events can be
calculated.
If the measured time is much greater than the calcu-
lated time, the internal oscillator block is running too
fast; to compensate, decrement the OSCTUNE register .
If the measured time is much less than the calculated
time, the int er nal osci llator block is r unning to o slow ; t o
compensate, increment the OSCTUNE register .
R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
INTSRC —— TUN4 TUN3 TUN2 TUN1 TUN0
bit 7 bit 0
bit 7 INTSRC: Internal Oscillator Low-Frequency Source Select bit
1 = 31.25 kHz device clock derived from 8 MHz INTOSC source (divide-by-256 enabled)
0 = 31 kHz device clock derived directly from INTRC internal oscillator
bit 6-5 Unimplemented: Read as ‘0’
bit 4-0 TUN4:TUN0: Frequency Tuning bits
01111 = Maximum frequency
• •
• •
00001
00000 = Center frequency. Oscillator module is running at the calibrated frequency.
11111
• •
• •
10000 = Minimum frequency
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
2004 Microchip Technology Inc. Advance Information DS39632A-page 29
PIC18F2455/2550/4455/4550
2.3 Oscillator Settings for USB
When the PIC18F4550 is used for USB connectivity, it
must have either a 6 MHz or 48 MHz clock for USB
operation, depending on whether Low-Speed or Full
Speed mode is being used. This may require some
forethought in selecting an oscillator frequency and
programming the device.
The full range of possible oscillator configurations
compatible with USB operation is shown in Table 2-3.
2.3.1 LOW-SPEED OPERATION
The USB clock for Low-Speed mode is derived from
the primary oscillator chain and not directly from the
PLL; it is divided by 4 to produce the actual 6 MHz
clock. Because of this, the microcontroller can only use
a clock frequency of 24 MHz when the USB module is
active and the controller clock source is one of the
primary oscillator modes (XT, HS or EC, with or without
the PLL).
This restriction does not apply if the microcontroller
clock source is the secondary oscillator or internal
oscillator block.
2.3.2 RUNNING DIFFERENT USB AND
MICROCONTROLLER CLOCKS
The USB module, in either mode, can run asynchro-
nously with respect to the microcontroller core and
other peripherals. This means that applications can use
the pr imary oscilla tor for the USB cloc k while the m icro-
controller runs from a separate clock source at a lower
speed. If it is necessary to run the entire application
from only one clock source, full speed operation
provides a greater selection of microcontroller clock
frequencies.
TABLE 2-3: OSCILLATOR CONFIGURATION OPTIONS FOR USB OPERATION
Input Oscillator
Frequency PLL Division
(PLLDIV2:PLLDIV0) Clock Mode
(FOSC3:FOSC0) MCU Clock Division
(CPUDIV1:CPUDIV0) Microcontroller
Clock Frequency
48 MHz N/A(1) EC, ECIO None (00)48MHz
÷2 (01)24 MHz
÷3 (10)16MHz
÷4 (11)12MHz
48 MHz ÷12 (111) EC, ECIO None (00)48MHz
÷2 (01)24 MHz
÷3 (10)16MHz
÷4 (11)12MHz
ECPL L, ECPI O ÷2 (00)48MHz
÷3 (01)32MHz
÷4 (10)24 MHz
÷6 (11)16MHz
40 MHz ÷10 (110) EC, ECIO None (00)40MHz
÷2 (01)20MHz
÷3 (10) 13.33 MHz
÷4 (11)10MHz
ECPL L, ECPI O ÷2 (00)48MHz
÷3 (01)32MHz
÷4 (10)24 MHz
÷6 (11)16MHz
24 MHz ÷6 (101) HS, EC, ECIO None (00)24 MHz
÷2 (01)12MHz
÷3 (10)8MHz
÷4 (11)6MHz
HSPLL, ECPLL, ECPIO ÷2 (00)48MHz
÷3 (01)32MHz
÷4 (10)24 MHz
÷6 (11)16MHz
Legend: All clock frequencies, except 24 MHz, are exclusively associated with full speed USB operation (USB clock of 48 MHz).
Bold is used to highlight clock selections that are compatible with low-speed USB operation (system clock of 24 MHz,
USB clock of 6 M Hz).
Note 1: Only valid when the USBDIV configuration bit is cleared.
PIC18F2455/2550/4455/4550
DS39632A-page 30 Advance Information 2004 Microchip Technology Inc.
20 MHz ÷5 (100) HS, EC, ECIO None (00)20MHz
÷2 (01)10MHz
÷3 (10)6.67MHz
÷4 (11)5MHz
HSPLL, ECPLL, ECPIO ÷2 (00)48MHz
÷3 (01)32MHz
÷4 (10)24 MHz
÷6 (11)16MHz
16 MHz ÷4 (011) HS, EC, ECIO None (00)16MHz
÷2 (01)8MHz
÷3 (10)5.33MHz
÷4 (11)4MHz
HSPLL, ECPLL, ECPIO ÷2 (00)48MHz
÷3 (01)32MHz
÷4 (10)24 MHz
÷6 (11)16MHz
12 MHz ÷3 (010) HS, EC, ECIO None (00)12MHz
÷2 (01)6MHz
÷3 (10)4MHz
÷4 (11)3MHz
HSPLL, ECPLL, ECPIO ÷2 (00)48MHz
÷3 (01)32MHz
÷4 (10)24 MHz
÷6 (11)16MHz
8MHz ÷2 (001) HS, EC, ECIO None (00)8MHz
÷2 (01)4MHz
÷3 (10)2.67MHz
÷4 (11)2MHz
HSPLL, ECPLL, ECPIO ÷2 (00)48MHz
÷3 (01)32MHz
÷4 (10)24 MHz
÷6 (11)16MHz
4MHz ÷1 (000) XT, HS, EC, ECIO No n e (00)4MHz
÷2 (01)2MHz
÷3 (10)1.33MHz
÷4 (11)1MHz
HSPLL, ECPLL, XTPLL ÷2 (00)48MHz
÷3 (01)32MHz
÷4 (10)24 MHz
÷6 (11)16MHz
TABLE 2-3: OSCILLATOR CONFIGURATION OPTIONS FOR USB OPERATION (CONTINUED)
Input Oscillator
Frequency PLL Division
(PLLDIV2:PLLDIV0) Clock Mode
(FOSC3:FOSC0) MCU Clock Division
(CPUDIV1:CPUDIV0) Microcontroller
Clock Frequency
Legend: All clock frequencies, except 24 MHz, are exclusively associated with full speed USB operation (USB clock of 48 MHz).
Bold is used to highlight clock selections that are compatible with low-speed USB operation (system clock of 24 MHz,
USB clock of 6 M Hz).
Note 1: Only valid when the USBDIV configuration bit is cleared.
2004 Microchip Technology Inc. Advance Information DS39632A-page 31
PIC18F2455/2550/4455/4550
2.4 Clock Sources and Oscillator
Switching
Like previous PIC18 enhanced devices, the
PIC18F2 455/2550/ 4455/4550 family in cludes a fe ature
that allo ws the dev ice clock so urce to be sw itched fro m
the main oscillator to an alternate low-frequency clock
source. PIC18F2455/2550/4455/4550 devices offer
two alternate clock sources. When an alternate clock
source is enabled, the various power managed
operat in g mode s are ava il abl e.
Essentially, there are three clock sources for these
devices:
• Primary oscillators
• Second ary oscill ators
• Internal oscillator block
The primary oscillators include the External Crystal
and Resonator modes, the External Clock modes and
the internal oscillator block. The particular mode is
defined by the FOSC3:FOSC0 configuration bits. The
details of these modes are covered earlier in this
chapter.
The secondary oscillators are those external sources
not connected to the OSC1 or OSC2 pins. These
sources may continue to operate even after the
controller is placed in a power managed mode.
PIC18F2 455 /25 50/ 445 5/45 50 devices o f fer the Timer1
oscill ator as a seconda ry oscillator. This oscillato r , in all
power managed modes, is often the time base for
functions such as a real-time clock. Most often, a
32.768 kHz watch crystal is connected between the
RC0/T1OSO/T13CKI and RC1/T1OSI pins. Like the
XT and HS mode oscillator circuits, loading capacitors
are also connected from each pin to ground. The
Timer1 oscillator is discussed in greater detail in
Section 12.3 “Timer1 Oscillator”.
In addi tion to be ing a prim ary clock s ource, the internal
oscillator block is available as a power managed
mode cl oc k s ourc e. The INT RC source is a lso us ed a s
the clock source for several special features, such as
the WDT and Fail-Safe Clock Monitor.
2.4.1 OSCILLATOR CONTROL REGISTER
The OSCCON register (Register 2-2) controls several
aspects of the device clock’s operation, both in full
power operation and in power managed modes.
The System Clock Select bits, SCS1:SCS0, select the
clock source. The available clock sources are the
primary clock (defined by the FOSC3:FOSC0 configu-
ration bits), the secondary clock (Timer1 oscillator) and
the internal oscillator block. The clock source changes
immediately after one or more of the bits is written to,
following a brief clock transition interval. The SCS bits
are cleared on all forms of Reset.
The Internal Oscillator Frequency Select bits,
IRCF2:IRCF0, select the frequency output of the internal
oscillator block to drive the de vice clock. The choices are
the INTRC source, the INTOSC source (8 MHz) or one
of the frequencies derived from the INTOSC postscaler
(31 kHz to 4 MHz). If the internal oscillator block is sup-
plying the device c lock, changing the st ates of these bit s
will have an immediate change on the internal oscilla-
tor’s output. On device Resets, the default output
frequency of the internal oscillator block is set at 1 MHz.
When an output frequency of 31 kHz is selected
(IRCF2:IRCF0 = 000), users may choose which inter-
nal oscillator acts as the source. This is done with the
INTSRC bit in th e OSCTUNE register (OSCTUNE<7>).
Setting this bit selects INTOSC as a 31.25 kHz clock
source by enabling the divide-by-256 output of the
INTOSC postscaler. Clearing INTSRC selects INTRC
(nominally 31 kHz) as the cloc k source.
This op tion allo ws use rs to sele ct the tun able and more
precise INTOSC as a clock source, while maintaining
power sa vings with a very lo w clock speed. Rega rdless
of the setting of INTSRC, INTRC always remains the
clock source for features such as the Watchdog Timer
and the Fail-Safe Clock Monitor.
The OSTS, IOFS and T1RUN bits indicate which clock
source is currently providing the device clock. The OSTS
bit indicates that the Oscillator Start-up Timer has timed
out and the primary clock is providing the device clock in
primary clock modes. The IOFS bit indicates when the
internal oscillator block has stabilized and is providing
the device clock in RC Clock modes. The T1RUN bit
(T1CON<6>) indicates when the Timer1 oscillator is pro-
viding the device clock in secondary clock modes. In
power managed modes, only one of these three bit s will
be set at any time. If none of these bits are set, the
INTRC is providing the clock or the internal oscillator
block has just st arted and is not yet stable.
The IDL EN bi t dete rmines i f th e device goes into Sleep
mode or one of the Idle modes when the SLEEP
instruction is executed.
The use of the flag and control bits in the OSCCON
register is discussed in more detail in Section 3.0
“Power Managed Modes”.
Note 1: The Timer1 oscillator must be enabled to
select the secondary clock source. The
Timer1 oscillator is enabled by setting the
T1OSCEN bit in the Timer1 Control regis-
ter (T1CON<3>). If the T imer1 osc illator is
not enabled, then any attempt to select a
secondary clock s ource w ill be igno red .
2: It is recommended that the Timer1
oscillator be operating and stable prior to
switching to it as the clock source; other-
wise, a very long delay may occur while
the Timer1 oscillator starts.
PIC18F2455/2550/4455/4550
DS39632A-page 32 Advance Information 2004 Microchip Technology Inc.
2.4.2 OSCILLA TOR TRANSITIONS
PIC18F2455/2550/4455/4550 devices contain circuitry
to prevent clock “glitches” when switching between
clock sources . A short p ause in the devic e clock occurs
during the clock switch. The length of this pause is the
sum of two cycles of the old clock source and three to
four cycles of the new clock source. This formula
assumes that the new clock source is stable.
Clock transitions are discussed in greater detail in
Section 3.1.2 “Entering Power Managed Modes”.
REGISTER 2-2: OSCCON REGISTER
R/W-0 R/W-1 R/W-0 R/W-0 R(1) R-0 R/W-0 R/W-0
IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0
bit 7 bit 0
bit 7 IDLEN: Idle Enable bit
1 = Device enters Idle mode on SLEEP instruction
0 = Device enters Sleep mode on SLEEP instr uction
bit 6-4 IRCF2:IRCF0: Internal Oscillator Frequency Select bits
111 = 8 MHz (INTOSC drives clock directly)
110 = 4 MHz
101 = 2 MHz
100 = 1 MHz(3)
011 = 500 kHz
010 = 250 kHz
001 = 125 kHz
000 = 31 kHz (from either INTOSC/256 or INTRC directly)(2)
bit 3 OSTS: Oscillator Start-up Time-out Status bit(1)
1 = Oscillator Start-up Timer time-out has expired; primary oscillator is running
0 = Oscillator Start-up Timer time-out is running; primary oscillator is not ready
bit 2 IOFS: INTOSC Frequency Stable bit
1 = INTOSC frequency is stable
0 = INTOSC frequency is not stable
bit 1-0 SCS1:SCS0: Sy stem Cl ock Se lect bits
1x = Internal oscillator block
01 = Timer 1 oscillator
00 = Primary oscillator
Note 1: Depends on state of the IESO configuration bit.
2: Source selected by the INTSRC bit (OSCTUNE<7>), see text.
3: Default output frequency of INTOSC on Reset.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
2004 Microchip Technology Inc. Advance Information DS39632A-page 33
PIC18F2455/2550/4455/4550
2.5 Effects of Power Managed Modes
on the Various Clock Sources
When PRI_IDLE mode is selected, the designated pri-
mary oscillator continues to run without interruption.
For all other power managed modes, the oscillator
using the OSC1 pin is disabled. Unless the USB
module is enabled, the OSC1 pin (and OSC2 pin, if
used by the oscillator) will stop oscillating.
In secondary clock modes (SEC_RUN and
SEC_IDLE), the Timer1 oscillator is operating and
providing the device clock. The Timer1 oscillator may
also run in all power managed modes if required to
clock Timer1 or Timer3.
In internal oscillator modes (RC_RUN and RC_IDLE),
the internal oscillator block provides the device clock
source. The 31 kHz INTR C output can be used d irectl y
to provide the clock and may be enabled to support
various special features, regardless of the power man-
aged mode (see Section 25.2 “Watchdog Timer
(WDT)”, Section 25.3 “Two-Speed Start-up” and
Section 25.4 “Fail-Safe Clock Monitor” for more
information on WDT, Fail-Safe Clock Monitor and
Two-Speed Start-up). The INTOSC output at 8 MHz
may be used directly to clock the device or may be
divided down by the postscaler. The INTOSC output is
disabled if the clock is provided directl y from the INTRC
output.
Regardless of the Run or Idle mode selected, the USB
clock source will continue to operate. If the device is
operating from a crystal or resonator-based oscillator,
that oscillator will continue to clock the USB module;
the core and all other modules will switch to the new
clock source.
If the Sleep mode is selected, all clock sources are
stopped. Since all the transistor switching currents
have been stopped, Sleep mode achieves the lowest
current consumption of the device (only leakage
currents).
Sleep mode should never be invoked while the USB
module is operating and connected. The only exception
is when the device has been issued a “Suspend” com-
mand over the USB. Once the module has suspended
operation and shifted to a low-power state, the
microcontroller may be safely put into Sleep mode.
Enabling any on-chip feature that will operate during
Sleep w ill increase the current co nsumed during Sl eep.
The INTRC is required to support WDT operation. The
Timer1 oscillator may be operating to support a
real-time clock. Other features may be operating that
do not require a device clock source (i.e., SSP slave,
PSP, INTn pins and others). Peripherals that may add
significant current consumption are listed in
Section 28.2 “DC Characteristics: Power-Down a nd
Supply Current”.
2.6 Power-up Delays
Power-up delays are controlled by two timers, so that
no exte rna l Reset circ ui try is re qui red for most a ppl ic a-
tions. The delays ensure that the device is kept in
Reset until the device powe r supply i s stable under nor-
mal circumstances and the primary clock is operating
and stable. For additional information on power-up
delays, see Section 4.5 “Device Reset Timers”.
The first timer is the Power-up Timer (PWRT), which
provides a fixed delay on power-up (parameter 33,
Table 28-12). It is enabled by clearing (= 0) the
PWRTEN configuration bit.
The second timer is the Oscillator Start-up Timer
(OST), intended to keep the chip in Reset until the
crystal oscillator is stable (XT and HS modes). The
OST does this by counting 1024 oscillator cycles
before allowing the oscillator to clock the device.
When the HSPLL Oscillator mode is selected, the
device is k ept in Res et for an add itiona l 2 ms, f ollowin g
the HS mode OST delay, so the PLL can lock to the
inco mi ng cl ock frequ enc y.
There is a delay of interval, TCSD (parameter 38,
Table 28-12), following POR, while the controller
become s ready to ex ecute instruc tions. This del ay runs
concurrently with any other delays. This may be the
only delay that occurs when any of the EC or internal
oscill ato r mo des are us ed a s th e pri ma ry c lock sourc e.
TABLE 2-4: OSC1 AND OSC2 PIN STATES IN SLEEP MODE
Oscillator Mode OSC1 Pin OSC2 Pin
INTCKO Floating, pulled by external clock At logic low (clock/4 output)
INTI O Floating, pulled by exter nal clock Configured as PORTA, bit 6
ECIO, ECPIO Floating, pulled by external clock Configured as PORTA, bit 6
EC Floating, pulled by external clock At logic low (clock/4 output)
XT and HS Feedback inverter disabled at quiescent
voltage level Feedback inverter disabled at quiescent
voltage level
Note: See Table 4-2 in Section 4.0 “Reset” for time-outs due to Sleep and MCLR Reset.
PIC18F2455/2550/4455/4550
DS39632A-page 34 Advance Information 2004 Microchip Technology Inc.
NOTES:
2004 Microchip Technology Inc. Advance Information DS39632A-page 35
PIC18F2455/2550/4455/4550
3.0 POWER MANAGED MODES
PIC18F2455/2550/4455/4550 devices offer a total of
seven operating modes for more efficient power man-
agemen t. These m odes prov ide a variety of options for
selective power conservation in applications where
resources may be limited (i.e., battery-powered
devices).
There are three categories of power managed modes:
• Run modes
• Idle mo des
• Sleep mode
These categories define which portions of the device
are clo cked and some times , what sp eed. The Ru n and
Idle modes may use any of the three available clock
sources (primary, secondary or internal oscillator
block); the Sleep mode does not use a clock source.
The power managed modes include several
power-saving features offered on previous PICmicro®
devic es. One is the clock swi tching featur e, offere d in
other PIC18 devices, allowing the controller to use the
Time r1 os cil la tor in pl ac e of the prim ary osc il lato r. Also
included is the Sleep mode, offered by all PICmicro
devices, where all device clocks are stopped.
3.1 Selecting Power Managed Modes
Selecting a power managed mode requires two
decisions: if the CPU is to be clocked or not and the
selection of a clock source. The IDLEN bit
(OSCCON<7>) controls CPU clocking, while the
SCS1:SCS0 bits (OSCCON<1:0>) select the clock
source. The individual modes, bit settings, clock sources
and af fected mod ules are sum mariz ed in Table 3-1.
3.1.1 CLOCK SOURCES
The SCS1: SCS0 bits allow the sele ction of one o f three
clock sources for power managed modes. They are:
• the primary clock, as defined by the
FOSC3:FOSC0 configuration bits
• the secondary clock (the Timer1 oscillator)
• the internal oscillator block (for RC modes)
3.1.2 ENTERING POWER MANAGED
MODES
Switching from one power managed mode to another
begins by loading the OSCCON register. The
SCS1:SCS0 bi ts select the clock sourc e and determine
which Run or Idle mode is to be used. Changing these
bits causes an immediate switch to the new clock
source, assuming that it is running. The switch may
also be subject to clock transition delays. These are
discussed in Section 3.1.3 “Clock Transitions and
Status Indicators” and subsequent sections.
Entry to the Power Managed Idle or Sleep modes is
triggered by the execution of a SLEEP instruction. The
actual mode that results depends on the status of the
IDLEN bit.
Depending on the current mode and the mode being
switched to, a ch ange t o a po wer man aged m ode d oes
not always require setting all of these bits. Many
transitions may be done by changing the oscillator
select bit s, or chang ing th e IDLEN b it, prior t o i ssuing a
SLEEP instruction. If the IDLEN bit is already
configured correctly, it may only be necessary to
perform a SLEEP instruction to switch to the desired
mode.
TABLE 3-1: POWER MANAGED MODES
Mode OSCCON Bit s Module Clockin g Available Clock and Oscillator Source
IDLEN<7>(1) SCS1:SCS0<1:0> CPU Peripherals
Sleep 0N/A Off Off None – All clocks are disabled
PRI_RUN N/A 00 Clocked Clocked Primary – all oscillator modes.
This is the normal full power execution mode.
SEC_RUN N/A 01 Clocked Clocked Secondary – Timer1 Oscillator
RC_RUN N/A 1x Clocked Clocked Internal Oscillator Bloc k (2)
PRI_IDLE 100Off Clocked Primary – all oscillator modes
SEC_IDLE 101Off Clocked Secondary – Timer1 Oscillator
RC_IDLE 11xOff Clocked Int ernal Oscillator Block(2)
Note 1: IDLEN reflects its value when the SLEEP instruction is executed.
2: Includes INTOSC and INTOSC postscaler, as well as the INTRC source.
PIC18F2455/2550/4455/4550
DS39632A-page 36 Advance Information 2004 Microchip Technology Inc.
3.1.3 CLOCK TRANSITIONS AND
STATUS INDICATORS
The length of the transition between clock sources is
the sum of two cyc les of the o ld clo ck so urce and thre e
to four cycles of the new clock source. This formula
assumes that the new clock source is stable.
Three bits indicate the current clock source and its
status. They are:
• OSTS (OSCCON<3>)
• IOFS (OSCCON<2>)
• T1RUN (T1CON<6>)
In general, only one of these bits will be set while in a
given power managed mode. When the OSTS bit is
set, the primary clock is providing the device clock.
When the IOFS bit is set, the INTOSC output is
_provid ing a stab le 8 MHz clock sou rce to a divid er that
actually drives the de vice clock. When the T1RUN bit i s
set, the Timer1 oscillator is providing the clock. If none
of these bits are set, then either the INTRC clock
source is cl oc ki ng t he dev ic e, o r th e INTOSC source i s
not yet stable.
If the internal oscillator block is configured as the
primary cl oc k s ou r ce by th e FO SC3: FO SC 0 configura-
tion bit s, then both the OSTS and IOFS bit s may be set
when in PRI_RUN or PRI_IDLE modes. This indicates
that the pri ma ry c loc k (IN TOSC outp ut) i s ge nera ting a
stable 8 MHz output. Entering another RC power
manage d m ode at th e s am e fre que nc y w ou ld cle ar th e
OSTS bit.
3.1.4 MULTIPLE SLEEP COMMANDS
The power managed mode that is invoked with the
SLEEP instruction is determined by the setting of the
IDLEN bit at the time the instruction is executed. If
another SLEEP instruction is executed, the device will
enter the powe r manag ed mode specified by IDLEN at
that time. If IDLEN has changed, the device will enter
the new power managed mode specified by the new
setting.
3.2 Run Modes
In the Run modes, clocks to both the core and
peripherals are active. The difference between these
modes is the clock sou r ce .
3.2.1 PRI_RUN MODE
The PRI_RUN mode is the normal, full power execution
mode of the microcontroller. This is also the default
mode upon a device Reset, unless T wo-Speed S tart-up
is enabled (see Section 25.3 “Two-Speed Start-up”
for det ails). In thi s mode, the O STS bit is se t. The IOFS
bit may be set if the internal oscillator block is the pri-
mary clock source (see Section 2.4.1 “Oscillator
Control Register”).
3.2.2 SEC_RUN MODE
The SEC_RUN mode is the compatible mode to the
“clock switching” feature offered in other PIC18
devices. In this mode, the CPU and peripherals are
clock ed from the T ime r1 oscill ator . This gives us ers the
option of lower power consumption while still using a
high accuracy clock source.
SEC_RUN mode is en tered by setting the SC S1:SCS0
bits to ‘01’. The device clock source is switched to the
Timer1 oscillator (see Figure 3-1), the primary
oscillator is shut down, the T1RUN bit (T1CON<6>) is
set and the OSTS bit is cleared.
On transitions from SEC_RUN mode to PRI_RUN, the
peripherals and CPU continue to be clocked from the
Timer1 oscillator while the primary clock is started.
When t he prima ry clo ck becom es r eady, a clock sw itch
back to the primary clock occurs (see Figure 3-2).
When the clock switch is complete, the T1RUN bit is
cleared, the OSTS bit is set and the primary clock is
providing the clock. The IDLEN and SCS bits are not
affected by the wake-up; the Timer1 oscillator
continues to run.
Note 1: Caution should be used when modifying a
single IR CF bit. I f VDD is le ss than 3V, it is
possible to select a higher clock speed
than is supported by the low VDD.
Improper device operation may result if
the VDD/FOSC specifications are violated.
2: Executing a SLEEP instruction does not
necessarily place the device into Sleep
mode. It acts as the trigger to place the
controller into either the Sleep mode or
one of the Idle modes, depending on the
setting of the IDLEN bit.
Note: The Timer1 oscillator should already be
running pri or to entering SEC_RUN mod e.
If the T1OSCEN bit is not set when the
SCS1:SCS0 bits are set to ‘01’, entry to
SEC_RUN mode will not occur. If the
Timer1 oscillator is enabled but not yet
running, dev ice cloc ks wi ll be delayed until
the oscillator has started; in such situa-
tions, initial oscillator operation is far from
stable and unpredictable operation may
result.
2004 Microchip Technology Inc. Advance Information DS39632A-page 37
PIC18F2455/2550/4455/4550
FIGURE 3-1: TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE
FIGURE 3-2: TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL)
3.2.3 RC_RUN MODE
In RC_RUN mode, the CPU and peripherals are
clocked from the internal oscillator block using the
INTOSC multiplexer; the primary clock is shut down.
When usin g the INTRC sourc e, this mode pro vides the
best power conservation of all the Run modes, while
still executing code. It works well for user applications
which are not highly timing sensitive or do not require
high-speed clocks at all times.
If the primary clock source is the internal oscillator
block (either INTRC or INTOSC), there are no distin-
guishable differences between PRI_RUN and
RC_RUN modes during execution. However, a clock
switch delay will occur during entry to and exit from
RC_RUN mode. Therefore, if the primary clock source
is the internal oscillator block, the use of RC_RUN
mode is not recommended.
This mode is entered by setting SCS1 to ‘1’. Although
it is ignored, it is recommended that SCS0 also be
cleared; this is to maintain software compatibility with
future devices. When the clock source is switched to
the INTOSC multiplexer (see Figure 3-3), the primary
oscillator is shut down and the OSTS bit is cleared. The
IRCF bits may be modified at any time to immediately
change the clock speed.
Q4Q3Q2
OSC1
Peripheral
Program
Q1
T1OSI
Q1
Counter
Clock
CPU
Clock
PC + 2PC
123
n-1
n
Clock Transition
Q4Q3Q2 Q1 Q3Q2
PC + 4
Q1 Q3 Q4
OSC1
Peripheral
Program PC
T1OSI
PLL Clock
Q1
PC + 4
Q2
Output
Q3 Q4 Q1
CPU Clock
PC + 2
Clock
Counter
Q2 Q2 Q3
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
SCS1:SCS0 bits Changed
TPLL(1)
12 n-1n
Clock
OSTS bit Set
Transition
TOST(1)
Note: Cau tio n s hou ld be u se d w he n m odi fy ing a
single IRCF bit. If VDD is less than 3V, it is
possible to select a higher clock speed
than is supported by the low VDD.
Improper device operation may result if
the VDD/FOSC specifications are violated.
PIC18F2455/2550/4455/4550
DS39632A-page 38 Advance Information 2004 Microchip Technology Inc.
If the IRCF bits and the INTSRC bit are all clear, the
INTOSC output is not enabled and the IOFS bit will
remain clear; there will be no indication of the current
clock source. The INTRC source is providing the
device clocks.
If the IRCF bits are changed from all clear (thus,
enabling the INTOSC output) or if INTSRC is set, the
IOFS bit becomes set after the INTOSC output
becomes stable. Clocks to the device continue while
the INTOSC source stabilizes after an interval of
TIOBST.
If th e I RC F b its w ere pr e vi o us ly at a no n - zer o v al u e o r
if INTSRC was set before setting SCS1 and the
INTOSC source was already stable, the IOFS bit will
remain set.
On transitions from RC_RUN mode to PRI_RUN mode,
the device continues to be clocked from the INTOSC
multipl exer whil e the primary clo ck is st arted . When th e
prim ary cl oc k b ec ome s ready, a cloc k s w itc h t o th e pri-
mary clock occurs (see Figure 3-4). When the clock
switch is complete, the IOFS bit is cleared, the OSTS
bit is set and the primary clock is providing the device
clock. T he IDLEN an d SC S bit s are not af fe cte d by the
switch. The INTRC source will continue to run if either
the WDT or the Fail-Safe Clock Monitor is enabled.
FIGURE 3-3: TRANSITION TIMING TO RC_RUN MODE
FIGURE 3-4: TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE
Q4Q3Q2
OSC1
Peripheral
Program
Q1
INTRC
Q1
Counter
Clock
CPU
Clock
PC + 2PC
123 n-1n
Clock Transition
Q4Q3Q2 Q1 Q3Q2
PC + 4
Q1 Q3 Q4
OSC1
Peripheral
Program PC
INTOSC
PLL Clock
Q1
PC + 4
Q2
Output
Q3 Q4 Q1
CPU Clock
PC + 2
Clock
Counter
Q2 Q2 Q3
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
SCS1:SCS0 bits Changed
TPLL(1)
12 n-1n
Clock
OSTS bit Set
Transition
Multiplexer
TOST(1)
2004 Microchip Technology Inc. Advance Information DS39632A-page 39
PIC18F2455/2550/4455/4550
3.3 Sleep Mode
The Power Managed Sleep mode in the
PIC18F2455/2550/4455/4550 devices is identical to
the legacy Sleep mode offered in all other PICmicro
devices. It is entered by clearing the IDLEN bit (the
default state on device Reset) and executing the
SLEEP instruction. This shuts down the selected
oscillator (Figure 3-5). All clock source status bits are
cleared.
Entering t he Sleep mode from any othe r mode does not
require a clock switch. This is because no clocks are
needed once the controller has entered Sleep. If the
WDT is selected, the INTRC source will continue to
operate. If the Timer1 oscillator is enabled, it will also
continue to run.
When a wake even t occurs i n Sleep mo de (by int errupt,
Reset or WDT time-o ut), the devi ce wil l not be clocke d
until the clock source selected by the SCS1:SCS0 bits
becomes ready (see Figure 3-6), or it will be clocked
from the internal oscillator block if either the
Two-Speed Start-up or the Fail-Safe Clock Monitor are
enabled (see Section 25.0 “Special Features of the
CPU”). In either case, the OSTS bit is set when the
primary clock is providing the device clocks. The
IDLEN and SCS bits are not affected by the wake-up.
3.4 Idle Modes
The Idle modes allow the controller’s CPU to be
selectively shut down while the peripherals continue to
operate. Selecting a particular Idle mode allows users
to further manage power consumption.
If the IDLEN bit i s set to a ‘1’ when a SLEEP inst ruction is
exec uted, the periph erals will be cl ocked fr om the cl ock
source selected using the SCS1:SCS0 bits; however , the
CPU will not be clocked. The clock source status bits are
not affected. Setting IDLEN and executing a SLEEP
instr uction pro vides a qu ick method of switchi ng f rom a
given R u n m o de to its corresp on di ng Idle m od e.
If the WDT is selected, the INTRC source will continue
to operate . If the T imer1 oscillato r is enabled, it will also
continue to run.
Since the CPU is not executing instructions, the only
exits from any of the Idle modes are by interrupt, WDT
tim e-out or a Reset. When a wa ke even t occur s, CPU
execution is delayed by an interval of TCSD
(parameter 38, Table 28-12) while it becomes ready to
execute code. When the CPU begins executing code,
it resumes with the same clock source for the current
Idle mode. For example, when waking from RC_IDLE
mode, the internal oscillator block will clock the CPU
and peripherals (in other words, RC_ RUN mo de). The
IDLEN and SCS bits are not affected by the wake-up.
While in any Idle mode or the Sleep mode, a WDT
time-out will re sul t i n a WD T wake-up to t he Ru n m od e
currently specified by the SCS1:SCS0 bits.
FIGURE 3-5: TRANSITION TIMING FOR ENTRY TO SLEEP MODE
FIGURE 3-6: TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL)
Q4Q3Q2
OSC1
Peripheral
Sleep
Program
Q1Q1
Counter
Clock
CPU
Clock
PC + 2PC
Q3 Q4 Q1 Q2
OSC1
Peripheral
Program PC
PLL Clock
Q3 Q4
Output
CPU Clock
Q1 Q2 Q3 Q4 Q1 Q2
Clock
Counter PC + 6
PC + 4
Q1 Q2 Q3 Q4
Wake Event
Note1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
TOST(1) TPLL(1)
OSTS bit Set
PC + 2
PIC18F2455/2550/4455/4550
DS39632A-page 40 Advance Information 2004 Microchip Technology Inc.
3.4.1 PRI_IDLE MODE
This mode is unique among the three Low-Power Idle
modes, in that it does not disable the primary device
clock. For timing sensitive applications, this allows for
the faste st resump tion of device op eration with its more
accur ate prima ry clock sour ce, since t he clock sou rce
does not have to “warm up” or transition from another
oscillator.
PRI_IDLE mode is entered from PRI_RUN mode by
setting the IDLEN bit and executing a SLEEP instruc-
tion. If the device is in another Run mode, set IDLEN
first, then clear the SCS bits and execute SLEEP.
Although the C PU is disab led, th e periphe rals c ontinu e
to be clocked from the primary clock source specified
by the FO SC3:FOSC0 config uration bit s. The OSTS bit
remains set (see Figure 3-7).
When a wake event occurs, the CPU is clocked from the
primary clock source. A delay of interval TCSD is
required between the wake event and when code
execution starts. This is required to allow the CPU to
become ready to execute instructions. After the
wake-up, the OSTS bit remains set. The IDLEN and
SCS bits are not affected by the wake-up (see
Figure 3-8).
3.4.2 SEC_IDLE MODE
In SEC_IDLE mode, the CPU is disabled but the
peripherals continue to be clocked from the Timer1
oscillator . This mode is entered from SEC_RUN by set-
ting the IDLEN bit and exec uting a SLEEP instruction. If
the devi ce is in another Ru n mode, set IDLEN first, then
set SCS1:SCS0 to ‘01’ and ex ec ut e SLEEP. When the
clock source is switched to the Timer1 oscillator, the
primary oscillator is shut down, the OSTS bit is cleared
and the T1RUN bit is set.
When a w ake event o ccurs, the pe ripherals contin ue to
be clocked from the Timer1 oscillator. After an interval
of TCSD fol lowing t he wa ke eve nt, the CPU b egins exe-
cuting c ode being c locked by the Timer1 osc illator. The
IDLEN and SCS bits are not affected by the wake-up;
the Timer1 oscillator continues to run (see Figure 3-8).
FIGURE 3-7: TRANSITION TIMING FOR ENTRY TO IDLE MODE
FIGURE 3-8: TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE
Note: The Timer1 oscillator should already be
running prior to entering SEC_IDL E mode.
If the T1OSCEN bit is not set when the
SLEEP instruction is executed, the SLEEP
instruction will be ignored and entry to
SEC_IDLE mode will not occur. If the
Timer1 oscillator is enabled but not yet
running, peripheral clocks will be delayed
until the oscillator has started. In such sit-
uations, initial oscillator operation is far
from stable and unpredictable operation
may re sult.
Q1
Peripheral
Program PC PC + 2
OSC1
Q3 Q4 Q1
CPU Clock
Clock
Counter
Q2
OSC1
Peripheral
Program PC
CPU Clock
Q1 Q3 Q4
Clock
Counter
Q2
Wake Event
TCSD
2004 Microchip Technology Inc. Advance Information DS39632A-page 41
PIC18F2455/2550/4455/4550
3.4.3 RC_IDLE MODE
In RC_I DL E m od e, t he C PU is d is abl ed but th e p erip h-
erals co nti nue to b e c loc ke d fro m the inter nal os cil lator
block using the INTOSC multiplexer. This mode allows
for cont rollable power c onservation during Idle periods .
From RC_RUN, this mode is entered by setting the
IDLEN bit and executing a SLEEP instruction. If the
device is in a nother Run m ode, first set IDLEN, th en set
the SCS1 bit and execute SLEEP. Although its value is
ignored, it is re comm ended that SC S0 also be cle ared;
this is to maintain software compatibility with future
devices. The INTOSC multiplexer may be used to
select a higher clo ck f requ enc y, by modi fyi ng th e IR CF
bits, before executing the SLEEP instruction . Wh en th e
clock source is switch ed to the INTOSC mult iplexer , the
primary oscillator is shut down and the OSTS bit is
cleared.
If the IRCF bits are set to any non-zero value or the
INTSRC bit is set, the INTOSC output is enabled. The
IOFS bit becomes set, after the INTOSC output
becomes stable, after an interval of TIOBST
(parameter 39, Table 28-12). Clocks to the peripherals
continue while the INTOSC source stabilizes. If the
IRCF bits were previously at a non-zero value, or
INTSRC was set before the SLEEP instr uction was exe-
cuted and the INTOSC source was already stable, the
IOFS bit will remain set. If the IRCF bits and INTSRC
are all clear , the INTOSC out put will not be enabled, the
IOFS bit will remain c lear and there will be no ind ication
of the curr ent cl ock source.
When a w ake event o ccurs, the pe ripherals continue to
be clocked from the INTOSC multiplexer. After a delay
of TCSD following the w ake event, the CP U begins exe-
cuting code being clocked by the INTOSC multiplexer.
The IDLEN and SCS bits are not affected by the
wake-up. The INTRC source will continue to run if
either the WDT or the Fail-Safe Clock Monitor is
enabled.
3.5 Exiting Idle and Sleep Modes
An exit from Sleep mode or any of the Idle modes is
triggered by an interrupt, a Reset or a WDT time-out.
This section discusses the triggers that cause exits
from power managed modes. The clocking subsystem
actions are discussed in each of the power managed
modes (see Section 3.2 “Run Modes”, Section 3.3
“Sleep Mode” and Section 3.4 “Idle Modes”).
3.5. 1 EXIT BY INTERRUPT
Any of the available interrupt sources can cause the
device to exit from an Idle mode or the Sleep mode to
a Run mode. To enable this functionality, an interrupt
source m us t be en ab led by s etti ng i t s enable bi t in on e
of the INTCON or PIE registers. The exit sequence is
initiate d when the c orresponding interrupt flag bit is set.
On all ex its from Idl e or Sleep mod es by interrupt, code
execution branches to the interrupt vector if the
GIE/GIEH bit (INTCON<7>) is set. Otherwise, code
execution continues or resumes without branching
(see Section 9.0 “Interrupts”).
A fixed delay of interval TCSD fol low i ng th e wak e ev en t
is required when leaving Sleep and Idle modes. This
del ay is requi red for the CPU to prepar e for exec ution.
Instruction execution resumes on the first clock cycle
following this delay.
3.5.2 EXIT BY WDT TIME-OUT
A WDT time-out will cause different actions depending
on which power managed mode the device is in when
the time-out occurs.
If th e dev ice is not ex ecut ing code ( all Idle mo des a nd
Sleep mod e), th e time-o ut w ill res ul t in a n ex it fro m the
power mana ged mode (see Section 3.2 “Run Modes”
and Section 3.3 “Sleep Mode”). If the device is exe-
cuting code (all Run modes), the time-out will result in
a WDT Reset (see Section 25.2 “Watchdog Timer
(WDT)”).
The WDT timer and postscaler are cleared by execut-
ing a SLEEP or CLRWDT instruction, the loss of a
currently selected clock source (if the Fail-Safe Clock
Monitor is enabled) and modifying the IRCF bits in the
OSCCON register if the internal oscillator block is the
device clock source.
3.5. 3 EXIT BY RESET
Normally, the device is held in Reset by the Oscillator
Start-up Timer (OST) until the primary clock becomes
ready. At that time, the OSTS bit is set and the device
begins e xe cu ting code . If th e in tern al o sc il lat or block i s
the new clock source, the IOFS bit is set instead.
The exit delay time from Reset to the start of code
execution depends on both the clock sources before
and after the wake-up and the type of oscillator if the
new clock source is the primary clock. Exit delays are
summarized in Table 3-2.
Code execution can begin before the primary clock
becomes ready. If either the Two-Speed Start-up (see
Section 25.3 “Two-Speed Start-up”) or Fail-Safe
Clock Monitor (see Section 25.4 “Fail-Safe Clock
Monitor”) is enabled, the device may begin execution
as soon as the Re set sourc e ha s cle ared. Execut ion is
clocked by the INTOSC multiplexer driven by the
internal oscillator block. Execution is clocked by the
internal oscillator block until either the primary clock
becomes ready or a power managed mode is entered
before the primary clock becomes ready; the primary
clock is then shut down.
PIC18F2455/2550/4455/4550
DS39632A-page 42 Advance Information 2004 Microchip Technology Inc.
3.5.4 EXIT WITHOUT AN OSCILLATOR
START-UP DELAY
Certain exits from power managed modes do not
invoke the OST at all. There are two cases:
• PRI_IDLE mode where the primary clock source
is not stopped; and
• the primary clock source is not any of the XT or
HS modes.
In these instances, the primary clock source either
does not require an oscillator start-up delay since it is
already running (PRI_IDLE), or normally does not
require an oscillator s tart-up dela y (EC and any internal
oscillator modes). However, a fixed delay of interval
TCSD following the wake event is still required when
leaving Sleep and Idle modes to allow the CPU to
prepare for execution. Instruction execution resumes
on the first clock cycle following this delay.
TABLE 3-2: EXIT DELAY ON W AKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE
(BY CLOCK SOURCES)
Microcontroller Clock Source Exit Delay Clock Ready Status
Bit (OSCCON)
Before W ake -up After Wake-up
Primary Device Clock
(PRI_IDLE mode)
XT, HS
None OSTSXTPLL, HSPLL
EC
INTOSC(3) IOFS
T1OSC or INTRC(1)
XT, HS TOST(4)
OSTSXTPLL, HSPLL TOST + trc(4)
EC TCSD(2)
INTOSC(2) TIOBST(5) IOFS
INTOSC(3)
XT, HS TOST(5)
OSTSXTPLL, HSPLL TOST + trc(4)
EC TCSD(2)
INTOSC(2) None IOFS
None
(Sleep mode)
XT, HS TOST(4)
OSTSXTPLL, HSPLL TOST + trc(4)
EC TCSD(2)
INTOSC(2) TIOBST(5) IOFS
Note 1: In this instance, refers specifically to the 31 kHz INTRC clock source.
2: TCSD (par ame ter 38 ) is a requir ed del ay whe n wa king from Sl eep an d all Idle modes an d runs conc urrentl y
with any other required delays (see Section 3.4 “Idle Mode s”).
3: Includes both the INTOSC 8 MHz source and postscaler derived frequencies.
4: TOST is the Oscillator Start-up Timer (parameter 32). trc is the PLL Lock-out Timer (paramet er F12); it is
also designated as TPLL.
5: Execution continues during TIOBST (parameter 39), the INTOSC stabilization period.
2004 Microchip Technology Inc. Advance Information DS39632A-page 43
PIC18F2455/2550/4455/4550
4.0 RESET
The PIC18F2455/2550/4455/4550 devices differentiate
between various kin ds of R eset:
a) Power-on Reset (POR)
b) MCLR Reset during normal operation
c) MCLR Reset during power managed modes
d) Watchdog Timer (WDT) Reset (during
execution)
e) Programmable Brown-out Reset (BOR)
f) RESET Inst ruction
g) Stack Fu ll Reset
h) Stack Underflow Reset
This section discusses Resets generated by MCLR,
POR and BO R and cov ers the ope rati on of the var iou s
start-up timers. Stack Reset events are covered in
Section 5.1.2.4 “Stack Full and Underflow Resets”.
WDT Re se ts ar e co v ere d i n Section 25.2 “Watchdog
Timer (WDT)”.
A simplif ied block diagra m of the On-Chip Rese t Circu it
is sh own i n Figure 4-1.
4.1 RCON Register
Device Reset events are tracked through the RCON
register (Register 4-1). The lower five bits of the regis-
ter indic ate that a spec ific Reset event has oc curred. In
most ca ses, these b its can o nly be clear ed by the e vent
and mus t be s et b y the app lic at ion afte r the e ve nt. Th e
state of these flag bits, taken together, can be read to
indicate the type of Reset that just occurred. This is
described in more detail in Section 4.6 “Reset State
of Registers”.
The RCON register also has control bits for setting
interrupt priority (IPEN) and software control of the
BOR (SBOREN). Interrupt priority is discussed in
Section 9.0 “Interrupts”. BOR is covered in
Section 4.4 “Brown-out Reset (BOR)”.
FIGURE 4-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
S
RQ
External Reset
MCLR
VDD
OSC1
WDT
Time-out
VDD Rise
Detect
OST/PWRT
INTRC
(1)
POR Pulse
OST
10-bit Ripple Counter
PWRT
Chip_Reset
11-bit Ripple Counter
Enable OST(2)
Enable PWRT
Note 1: This is the INTRC source from the internal oscillator block and is separate from the RC oscillator of the CLKI pin.
2: See Table 4-2 for time-out situations.
Brown-out
Reset BOREN
RESET
Instruction
Stack
Pointer Stack Full/Underflow Reset
Sleep
( )_IDLE
1024 Cycles
65.5 ms
32 µs
MCLRE
PIC18F2455/2550/4455/4550
DS39632A-page 44 Advance Information 2004 Microchip Technology Inc.
REGISTER 4-1: RCON REGISTER
R/W-0 R/W-1(1) U-0 R/W-1 R-1 R-1 R/W-0(2) R/W-0
IPEN SBOREN —RITO PD POR BOR
bit 7 bit 0
bit 7 IPEN: Interrupt Priority Enable bit
1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode)
bit 6 SBOREN: BOR Software Enable bit(1)
If BOREN1:BOREN0 = 01:
1 = BOR is enabled
0 = BOR is disabled
If BOREN1:BOREN0 = 00, 10 or 11:
Bit is disabled and read as ‘0’.
bit 5 Unimplemented: Read as ‘0’
bit 4 RI: RESET Instruction Flag bit
1 = The RESET instruction was not executed (set by firmware only)
0 = The RESET instruction was executed causing a device Reset (must be set in software after
a Br own-out Reset occurs )
bit 3 TO: Watchdog Time-out Flag bit
1 = Set by power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
bit 2 PD: Power-down Detection Flag bit
1 = Set by power-up or by the CLRWDT instruction
0 = Set by execution of the SLEEP instruction
bit 1 POR: Power-on Reset Status bit(2)
1 = A Power-on Reset has not occurred (set by firmware only)
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0 BOR: Brown-out Reset Status bit
1 = A Brown-out Reset has not occurred (set by firmware only)
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Note 1: If SBOREN is enabled, its Reset state is ‘1’; otherwise, it is ‘ 0’.
2: The actual R e set val ue o f POR is det erm ine d by the type of device Re set. See the
notes following this table and Section 4.6 “Reset State of Registers” for
additional information.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: It is recommended that the POR bit be set after a Power-on Reset has been
detected so that subsequent Power-on Resets may be detected.
2: Brown-out Reset is said to have occurred when BOR is ‘0’ and POR i s ‘1’ (assuming
that POR was set to ‘1’ by software immediately after POR).
2004 Microchip Technology Inc. Advance Information DS39632A-page 45
PIC18F2455/2550/4455/4550
4.2 Master Clear Reset (MCLR)
The MCLR pin provides a method for triggering an
external Reset of the device. A Reset is generated by
hold ing the pin low . T hese devi ces have a noise fi lter in
the MCLR Reset path which detects and ignores small
pulses.
The MCLR pin i s not dri ven l ow b y any i nter nal Res ets ,
including the WDT.
In PIC18F2455/2550/4455/4550 devices, the MCLR
input can be disabled with the MCLRE configuration bit.
When MCLR is disabled, the pin becomes a digital
input. See Section 10.5 “PORTE, TRISE and LATE
Registers” for more information.
4.3 Power-on Reset (POR)
A Power-on Reset pulse is generated on-chip
whenever VDD rises above a certain threshold. This
allows the device to start in the initialized state when
VDD is adequate for operation.
To take advantage of the POR circuitry, tie the MCLR
pin th rou gh a res is tor ( 1 k Ω to 10 kΩ) to VDD. Thi s wi ll
eliminate external RC components usually needed to
create a Power-on Re set delay. A minim um rise rate for
VDD is specified (parameter D004). For a slow rise
time, see Figure 4-2.
When the device s t arts norm al ope rati on (i.e ., ex its the
Reset condition), device operating parameters (volt-
age, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.
POR events are captured by the POR bit (RCON<1>).
The state of the bit is set to ‘0’ whenever a POR occurs ;
it does not change for any other Reset event. POR is
not reset to ‘1’ by any hardware event. To capture
multiple events, the user manually resets the bit to ‘1’
in software following any POR.
FIGURE 4-2: EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD POWER-UP)
Note 1: External Power-on Reset circuit is required
only if the VDD power-up slope is too slow.
The diode D helps discharge the capacitor
quickly when VDD powers down.
2: R < 40 kΩ is recommended to make sure that
the voltage drop across R does not violate
the device’s electrical specification.
3: R1 ≥ 1 kΩ will limit any current flowing into
MCLR from external capacitor C, i n the event
of MCLR/VPP pin breakdown, due to Electro-
static Discharge (ESD) or Electrical
Overs tress (EOS) .
C
R1
R
D
VDD
MCLR
PIC18FXXXX
VDD
PIC18F2455/2550/4455/4550
DS39632A-page 46 Advance Information 2004 Microchip Technology Inc.
4.4 Brown-out Reset (BOR)
PIC18F2455/2550/4455/4550 devices implement a
BOR circuit that provides the user with a number of
configuration and power-saving options. The BOR
is controlled by the BORV1:BORV0 and
BOREN1:BOR EN0 co nfigura tion b its . There are a tota l
of four BOR configurations which are summarized in
Table 4-1.
The BOR t hreshold is set b y the BOR V1:BOR V0 bi ts. If
BOR is enabled (any values of BOREN1:BOREN0,
except ‘00’), any drop of VDD below VBOR (param eter
D005) for greater than TBOR (parameter 35) will reset
the device. A Reset may or may not occur if VDD fal ls
below VBOR for less than TBOR. The chip will remain in
Brown-out Reset until VDD rises above VBOR.
If the Po wer-up T imer is enabled, i t will be inv oked after
VDD rises above VBOR; it then will keep the chip in
Reset for an additional time delay, TPWRT
(parameter 33). If VDD drops below VBOR while the
Power-up Timer is running, the chip will go back into a
Brown-out Reset and the Power-up Timer will be
initialized. Once VDD rises above VBOR, the Power-up
Timer will execute the additional time delay.
BOR and the Power-on Timer (PWRT) are
independently configured. Enabling BOR Reset does
not automatically enab le the PWRT.
4.4.1 SOFTWARE ENABLED BOR
When BOREN1:BOREN0 = 01, the BOR can be
enabled or disabled by the user in software. This is
done with the control bit, SBOREN (RCON<6>).
Setting SBOREN enables the BOR to function as
previously described. Clearing SBOREN disables the
BOR entirely. The SBOREN bit operates only in this
mode; otherwise it is read as ‘0’.
Placing the BOR under software control gives the user
the additional flexibility of tailoring the application to its
environ me nt w it hou t ha vi ng to reprog ram the de vi ce to
change BOR configuration. It also allows the user to
tailor device power consumption in software by elimi-
nating the incremental current that the BOR consumes.
While the BOR current is typically very small, it may
have some impact in low-power applications.
4.4.2 DETECTING BOR
When BO R is enab led, the BO R bit always resets to ‘0’
on any BOR or POR event. This makes it difficult to
determin e if a BOR eve nt ha s occ urre d jus t by reading
the state of BOR alone. A more reliable method is to
simultaneously check the state of both POR and BOR.
This as sumes that t he POR bit is re set to ‘1’ in softwa re
immediately after any POR event. IF BOR is ‘0’ while
POR is ‘1’, it can be reli ably assumed th at a BOR event
has occurred.
4.4.3 DISABLING BOR IN SLEEP MODE
When BOREN1:BOREN0 = 10, the BOR remains
under hardware control and operates as previously
described. Whenever the device enters Sleep mode,
howev er, the BOR is au tomati cally disabl ed. When the
device returns to any other operating mode, BOR is
automatically re-enabled.
This mode allows for applications to recover from
brown-out situations, while actively executing code,
when the device requires BOR protection the most. At
the same time, it save s additional po wer in Sleep mode
by eliminating the small incremental BOR current.
TABLE 4-1: BOR CONFIGURATIONS
Note: Even when BOR is under softwa re control,
the BOR Reset voltage level is still set by
the BORV1:BORV0 configuration bits. It
cannot be changed in software.
BOR Configuration Status of
SBOREN
(RCON<6>) BOR Operation
BOREN1 BOREN0
00Unavailable BOR disabled; must be enabled by reprogramming the configuration bits.
01Available BOR enabled in software; operation controlled by SBOREN.
10Unavailable BOR enabled in hardware in Run and Idle modes, disabled during Sleep
mode.
11Unavailable BOR enabled in hardware; must be disabled by reprogramming the
configuration bits.
2004 Microchip Technology Inc. Advance Information DS39632A-page 47
PIC18F2455/2550/4455/4550
4.5 Device Reset Timers
PIC18F2455/2550/4455/4550 devices incorporate
three separate on-chip timers that help regulate the
Power-on Reset process. Their main function is to
ensure that the device clock is stable before code is
execut ed. The se tim ers are:
• Power-up Timer (PWRT)
• Oscillator Start-up Timer (OST)
• PLL Lock Time-out
4.5.1 POWER-UP TIMER (PWRT)
The Power-up Timer (PWRT) of PIC18F2455/2550/
4455/4550 devices is an 11-bit counter which uses the
INTRC source as the clock input. This yields an
approximate time interval of 2048 x 32 µs=65.6ms.
While the PWRT is counting, the device is held in
Reset.
The powe r-up tim e de lay depe nd s on the INTRC cl oc k
and will vary from chip to chip due to temperature and
process variation. See DC parameter #33 for details.
The PWRT is enabled by clearing the PWRTEN
configuration bit .
4.5.2 OSCILLATOR START-UP TIME R
(OST)
The Oscillator Start-up Timer (OST) provides a 1024
oscillator cycle (from OSC1 input) delay after the
PWRT del ay is ov er (par a me t er 3 3 ). T h is en su re s t ha t
the crystal oscillator or resonator has started and
stabilized.
The OST time-out is invoked only for XT, LP, HS and
HSPLL modes and only on Power-on Reset or on exit
from most power managed modes.
4.5.3 PLL LOCK TIME-OUT
With the PLL enabled in its PLL mode, the time-out
sequence following a Power-on Reset is slightly differ-
ent from other oscillator modes. A separate timer is
used to p rov ide a fixe d tim e-o ut tha t i s su f f i cient for th e
PLL to lock to the main oscillator frequency. This PLL
lock time-out (TPLL) is typically 2 ms and follows the
oscillator start-up time-out.
4.5.4 TIME-OUT SEQUENCE
On power-up, the time-out sequence is as follows:
1. After the POR pulse has cleared, PWRT
time-out is invoked (if enabled).
2. Then, the OST is activated.
The total time-out will vary based on oscillator configu-
ration and the status of the PWRT. Figure 4-3,
Figure 4-4, Figure 4-5, Figure 4-6 and Figure 4-7 all
depict time-out sequences on power-up, with the
Power-up Timer enabled and the device operating in
HS Oscillator mode. Figures 4-3 through 4-6 also apply
to devic es op erating in XT or L P m odes. F or devi ces i n
RC mode and with the PWRT disabled, on the other
hand, there will be no time-out at all.
Since the time-outs occur from the PO R pulse, if MCLR
is kept low long e nough, all ti me-outs will expire. Bring-
ing MCLR high will begin execution immediately
(Figure 4-5). This is useful for testing purposes or to
synchronize more than one PIC18FXXXX device
operating in parallel.
TABLE 4-2: TIME-OUT IN VARIOUS SITUATIONS
Oscillator
Configuration
Power-up(2) and Brown-out Exit from
Power Managed Mode
PWRTEN = 0PWRTEN = 1
HS, XT 66 ms(1) + 1024 TOSC 1024 TOSC 1024 TOSC
HSPLL, XTPLL 66 ms(1) + 1024 TOSC + 2 ms(2) 1024 TOSC + 2 ms(2) 1024 TOSC + 2 ms(2)
EC, ECIO 66 ms(1) ——
ECPLL, ECPIO 6 6 ms(1) + 2 ms(2) 2 ms(2) 2 ms(2)
INTIO, INTCKO 66 ms(1) ——
INTHS, INTXL 66 ms(1) + 1024 TOSC 1024 TOSC 1024 TOSC
Note 1: 66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay.
2: 2 ms is the nominal time required for the PLL to lock.
PIC18F2455/2550/4455/4550
DS39632A-page 48 Advance Information 2004 Microchip Technology Inc.
FIGURE 4-3: T IME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT)
FIGURE 4-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
FIGURE 4-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
TPWRT
TOST
VDD
MCLR
INTERNAL POR
PWRT TIME-O UT
OST TIME-OUT
INTERNAL RESET
TPWRT
TOST
VDD
MCLR
INTER N AL PO R
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
TPWRT
TOST
2004 Microchip Technology Inc. Advance Information DS39632A-page 49
PIC18F2455/2550/4455/4550
FIGURE 4-6: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT)
FIGURE 4-7: TIME-OUT SEQUENCE ON POR W/ PLL ENABLED (MCLR TIED TO VDD)
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL R ESET
0V 1V 5V
TPWRT
TOST
TPWRT
TOST
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-O UT
INTERNAL RESET
PLL TIME-OUT
TPLL
Note: TOST = 1024 clock cycles.
TPLL ≈ 2 ms max. First three stages of the PWRT timer.
PIC18F2455/2550/4455/4550
DS39632A-page 50 Advance Information 2004 Microchip Technology Inc.
4.6 Reset State of Registers
Most registers are unaffected by a Reset. Their status
is unknown on POR and unchanged by all other
Resets. The other registers are forced to a “Reset
state” depending on the type of Reset that occurred.
Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal oper-
ation. Status bits from the RCON register, RI, TO, PD,
POR and BO R, are set or cle ared dif ferently i n dif ferent
Reset situations, as indicated in Table 4-3. These bits
are used in software to determine the nature of the
Reset.
Table 4-4 describes the Reset states for all of the
Special Function Registers. These are categorized by
Power-on and Brown-out Resets, Master Clear and
WDT Resets and WDT wake-ups.
TABLE 4-3: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR
RCON REGISTER
Condition Program
Counter
RCON Register STKPTR Register
SBOREN RI TO PD POR BOR STKFUL STKUNF
Power-on Reset 0000h 1 11100 0 0
RESET Instruction 0000h u(2) 0uuuu u u
Brown-out 0000h u(2) 111u0 u u
MCLR during Power Managed
Run modes 0000h u(2) u1uuu u u
MCLR during Power Managed
Idle modes and Sleep mode 0000h u(2) u10uu u u
WDT T ime-out during Full Power
or Power Managed Run modes 0000h u(2) u0uuu u u
MCLR during Full Power
Execution 0000h u(2) uuuuu u u
Stack Full Reset (STVREN = 1) 0000h u(2) uuuuu 1 u
Stack Underflow Reset
(STVREN = 1)0000h u(2) uuuuu u 1
Stack Underflow Error (not an
actual Reset, STVREN = 0)0000h u(2) uuuuu u 1
WDT Time-out during Power
Managed Idle or Sleep modes PC + 2 u(2) u00uu u u
Interrupt Exit from Power
Managed modes PC + 2 u(2) uu0uu u u
Legend: u = unchanged
Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the
inter rupt ve cto r (008h or 0018 h).
2: Reset state is ‘1’ for POR and unchanged for all other Resets when software BOR is enabled
(BOREN1:BOREN0 configuration bits = 01 and SBOREN = 1). Otherwise, the Reset state is ‘0’.
2004 Microchip Technology Inc. Advance Information DS39632A-page 51
PIC18F2455/2550/4455/4550
TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS
Register Applicable Devices Power-on Reset,
Brown-out Reset
MCLR Resets,
WDT R eset,
RESET Instruction,
Stack Resets
Wake-up via WDT
or Interrupt
TOSU 2455 2550 4455 4550 ---0 0000 ---0 0000 ---0 uuuu(1)
TOSH 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu(1)
TOSL 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu(1)
STKPTR 2455 2550 4455 4550 00-0 0000 uu-0 0000 uu-u uuuu(1)
PCLATU 2455 2550 4455 4550 ---0 0000 ---0 0000 ---u uuuu
PCLATH 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
PCL 2455 2550 4455 4550 0000 0000 0000 0000 PC + 2(2)
TBLPTRU 2455 2550 4455 4550 --00 0000 --00 0000 --uu uuuu
TBLPTRH 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
TBLPTRL 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
TABLAT 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
PRODH 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu
PRODL 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu
INTCON 2455 2550 4455 4550 0000 000x 0000 000u uuuu uuuu(3)
INTCON2 2455 2550 4455 4550 1111 -1-1 1111 -1-1 uuuu -u-u(3)
INTCON3 2455 2550 4455 4550 11-0 0-00 11-0 0-00 uu-u u-uu(3)
INDF0 2455 2550 4455 4550 N/A N/A N/A
POSTINC0 2455 2550 4455 4550 N/A N/A N/A
POSTDEC0 2455 2550 4455 4550 N/A N/A N/A
PREINC0 2455 2550 4455 4550 N/A N/A N/A
PLUSW0 2455 2550 4455 4550 N/A N/A N/A
FSR0H 2455 2550 4455 4550 ---- 0000 ---- 0000 ---- uuuu
FSR0L 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu
WREG 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu
INDF1 2455 2550 4455 4550 N/A N/A N/A
POSTINC1 2455 2550 4455 4550 N/A N/A N/A
POSTDEC1 2455 2550 4455 4550 N/A N/A N/A
PREINC1 2455 2550 4455 4550 N/A N/A N/A
PLUSW1 2455 2550 4455 4550 N/A N/A N/A
FSR1H 2455 2550 4455 4550 ---- 0000 ---- 0000 ---- uuuu
FSR1L 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu
BSR 2455 2550 4455 4550 ---- 0000 ---- 0000 ---- uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cell s ind ic ate co nditions do not app ly for the desig nat ed dev ic e.
Note 1: When the wak e-up is d ue to an int errup t and the G IEL or GIEH bit is set, the TOSU, T OSH and T O SL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
3: When the wake-up is due to a n interrupt a nd the GIEL or G IEH bit is se t, the PC is lo aded with th e interrupt
vector (0008h or 0018h).
4: See Table 4-3 for Reset value for specific condition.
5: PORTA<6>, LATA<6> and TRISA<6> are enabled, depending on the oscillator mode selected. When not
enabled as PORTA pins, they are disabled and read ‘0’.
PIC18F2455/2550/4455/4550
DS39632A-page 52 Advance Information 2004 Microchip Technology Inc.
INDF2 2455 2550 4455 4550 N/A N/A N/A
POSTINC2 2455 2550 4455 4550 N/A N/A N/A
POSTDEC2 2455 2550 4455 4550 N/A N/A N/A
PREINC2 2455 2550 4455 4550 N/A N/A N/A
PLUSW2 2455 2550 4455 4550 N/A N/A N/A
FSR2H 2455 2550 4455 4550 ---- 0000 ---- 0000 ---- uuuu
FSR2L 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu
STATUS 2455 2550 4455 4550 ---x xxxx ---u uuuu ---u uuuu
TMR0H 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
TMR0L 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu
T0CON 2455 2550 4455 4550 1111 1111 1111 1111 uuuu uuuu
OSCCON 2455 2550 4455 4550 0100 q000 0100 00q0 uuuu uuqu
HLVDCON 2455 2550 4455 4550 0-00 0101 0-00 0101 u-uu uuuu
WDTCON 2455 2550 4455 4550 ---- ---0 ---- ---0 ---- ---u
RCON(4) 2455 2550 4455 4550 0q-1 11q0 0q-q qquu uq-u qquu
TMR1H 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu
TMR1L 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu
T1CON 2455 2550 4455 4550 0000 0000 u0uu uuuu uuuu uuuu
TMR2 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
PR2 2455 2550 4455 4550 1111 1111 1111 1111 1111 1111
T2CON 2455 2550 4455 4550 -000 0000 -000 0000 -uuu uuuu
SSPBUF 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu
SSPADD 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
SSPSTAT 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
SSPCON1 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
SSPCON2 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
ADRESH 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu
ADRESL 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu
ADCON0 2455 2550 4455 4550 --00 0000 --00 0000 --uu uuuu
ADCON1 2455 2550 4455 4550 --00 0qqq --00 0qqq --uu uuuu
ADCON2 2455 2550 4455 4550 0-00 0000 0-00 0000 u-uu uuuu
TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register Applicable Devices Power-on Reset,
Brown-out Reset
MCLR Resets,
WDT R eset,
RESET Instruction,
Stack Resets
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cell s ind ic ate co nditions do not app ly for the desig nat ed dev ic e.
Note 1: When the wak e-up is d ue to an int errup t and the G IEL or GIEH bit is set, th e TOSU, T OSH and T O SL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
3: When the wake-up is due to a n interrupt a nd the GIEL or G IEH bit is se t, the PC is lo aded with th e interrupt
vector (0008h or 0018h).
4: See Table 4-3 for Reset value for specific condition.
5: PORTA<6>, LATA<6> and TRISA<6> are enabled, depending on the oscillator mode selected. When not
enabled as PORTA pins, they are disabled and read ‘0’.
2004 Microchip Technology Inc. Advance Information DS39632A-page 53
PIC18F2455/2550/4455/4550
CCPR1H 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu
CCPR1L 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu
CCP1CON 2455 2550 4455 4550 --00 0000 --00 0000 --uu uuuu
2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
CCPR2H 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu
CCPR2L 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu
CCP2CON 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
BAUDCON 2455 2550 4455 4550 01-0 0-00 01-0 0-00 uu-u u-uu
ECCP1DEL 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
ECCP1AS 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
CVRCON 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
CMCON 2455 2550 4455 4550 0000 0111 0000 0111 uuuu uuuu
TMR3H 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu
TMR3L 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu
T3CON 2455 2550 4455 4550 0000 0000 uuuu uuuu uuuu uuuu
SPBRGH 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
SPBRG 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
RCREG 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
TXREG 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
TXSTA 2455 2550 4455 4550 0000 0010 0000 0010 uuuu uuuu
RCSTA 2455 2550 4455 4550 0000 000x 0000 000x uuuu uuuu
EEADR 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
EEDATA 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
EECON2 2455 2550 4455 4550 0000 0000 0000 0000 0000 0000
EECON1 2455 2550 4455 4550 xx-0 x000 uu-0 u000 uu-0 u000
TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register Applicable Devices Power-on Reset,
Brown-out Reset
MCLR Resets,
WDT R eset,
RESET Instruction,
Stack Resets
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cell s ind ic ate co nditions do not app ly for the desig nat ed dev ic e.
Note 1: When the wak e-up is d ue to an int errup t and the G IEL or GIEH bit is set, the TOSU, T OSH and T O SL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
3: When the wake-up is due to a n interrupt a nd the GIEL or G IEH bit is se t, the PC is lo aded with th e interrupt
vector (0008h or 0018h).
4: See Table 4-3 for Reset value for specific condition.
5: PORTA<6>, LATA<6> and TRISA<6> are enabled, depending on the oscillator mode selected. When not
enabled as PORTA pins, they are disabled and read ‘0’.
PIC18F2455/2550/4455/4550
DS39632A-page 54 Advance Information 2004 Microchip Technology Inc.
IPR2 2455 2550 4455 4550 1111 1111 1111 1111 uuuu uuuu
2455 2550 4455 4550 1111 1111 1111 1111 uuuu uuuu
PIR2 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu(3)
2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu(3)
PIE2 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
IPR1 2455 2550 4455 4550 1111 1111 1111 1111 uuuu uuuu
2455 2550 4455 4550 -111 1111 -111 1111 -uuu uuuu
PIR1 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu(3)
2455 2550 4455 4550 -000 0000 -000 0000 -uuu uuuu
PIE1 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
2455 2550 4455 4550 -000 0000 -000 0000 -uuu uuuu
OSCTUNE 2455 2550 4455 4550 0--0 0000 0--0 0000 u--u uuuu
TRISE 2455 2550 4455 4550 ---- -111 ---- -111 uuuu -uuu
TRISD 2455 2550 4455 4550 1111 1111 1111 1111 uuuu uuuu
TRISC 2455 2550 4455 4550 11-- -111 11-- -111 uu-- -uuu
TRISB 2455 2550 4455 4550 1111 1111 1111 1111 uuuu uuuu
TRISA(5) 2455 2550 4455 4550 -111 1111(5) -111 1111(5) -uuu uuuu(5)
LATE 2455 2550 4455 4550 ---- -xxx ---- -uuu ---- -uuu
LATD 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu
LATC 2455 2550 4455 4550 xx-- -xxx uu-- -uuu uu-- -uuu
LATB 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu
LATA(5) 2455 2550 4455 4550 -xxx xxxx(5) -uuu uuuu(5) -uuu uuuu(5)
PORTE 2455 2550 4455 4550 0--- x000 0--- x000 u--- uuuu
PORTD 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu
PORTC 2455 2550 4455 4550 xxxx -xxx uuuu -uuu uuuu -uuu
PORTB 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu
PORTA(5) 2455 2550 4455 4550 -x0x 0000(5) -u0u 0000(5) -uuu uuuu(5)
TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register Applicable Devices Power-on Reset,
Brown-out Reset
MCLR Resets,
WDT R eset,
RESET Instruction,
Stack Resets
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cell s ind ic ate co nditions do not app ly for the desig nat ed dev ic e.
Note 1: When the wak e-up is d ue to an int errup t and the G IEL or GIEH bit is set, th e TOSU, T OSH and T O SL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
3: When the wake-up is due to a n interrupt a nd the GIEL or G IEH bit is se t, the PC is lo aded with th e interrupt
vector (0008h or 0018h).
4: See Table 4-3 for Reset value for specific condition.
5: PORTA<6>, LATA<6> and TRISA<6> are enabled, depending on the oscillator mode selected. When not
enabled as PORTA pins, they are disabled and read ‘0’.
2004 Microchip Technology Inc. Advance Information DS39632A-page 55
PIC18F2455/2550/4455/4550
UEP15 2455 2550 4455 4550 ---0 0000 ---0 0000 ---u uuuu
UEP14 2455 2550 4455 4550 ---0 0000 ---0 0000 ---u uuuu
UEP13 2455 2550 4455 4550 ---0 0000 ---0 0000 ---u uuuu
UEP12 2455 2550 4455 4550 ---0 0000 ---0 0000 ---u uuuu
UEP11 2455 2550 4455 4550 ---0 0000 ---0 0000 ---u uuuu
UEP10 2455 2550 4455 4550 ---0 0000 ---0 0000 ---u uuuu
UEP9 2455 2550 4455 4550 ---0 0000 ---0 0000 ---u uuuu
UEP8 2455 2550 4455 4550 ---0 0000 ---0 0000 ---u uuuu
UEP7 2455 2550 4455 4550 ---0 0000 ---0 0000 ---u uuuu
UEP6 2455 2550 4455 4550 ---0 0000 ---0 0000 ---u uuuu
UEP5 2455 2550 4455 4550 ---0 0000 ---0 0000 ---u uuuu
UEP4 2455 2550 4455 4550 ---0 0000 ---0 0000 ---u uuuu
UEP3 2455 2550 4455 4550 ---0 0000 ---0 0000 ---u uuuu
UEP2 2455 2550 4455 4550 ---0 0000 ---0 0000 ---u uuuu
UEP1 2455 2550 4455 4550 ---0 0000 ---0 0000 ---u uuuu
UEP0 2455 2550 4455 4550 ---0 0000 ---0 0000 ---u uuuu
UCFG 2455 2550 4455 4550 00-0 0000 00-0 0000 uu-u uuuu
UADDR 2455 2550 4455 4550 -000 0000 -000 0000 -uuu uuuu
UCON 2455 2550 4455 4550 -0x0 000- -0x0 000- -uuu uuu-
USTAT 2455 2550 4455 4550 -xxx xxx- -xxx xxx- -uuu uuu-
UEIE 2455 2550 4455 4550 0--0 0000 0--0 0000 u--u uuuu
UEIR 2455 2550 4455 4550 0--0 0000 0--0 0000 u--u uuuu
UIE 2455 2550 4455 4550 -000 0000 -000 0000 -uuu uuuu
UIR 2455 2550 4455 4550 -000 0000 -000 0000 -uuu uuuu
UFRMH 2455 2550 4455 4550 ---- -xxx ---- -xxx ---- -uuu
UFRML 2455 2550 4455 4550 xxxx xxxx xxxx xxxx uuuu uuuu
SPPCON 2455 2550 4455 4550 ---- --00 ---- --00 ---- --uu
SPPEPS 2455 2550 4455 4550 00-0 0000 00-0 0000 uu-u uuuu
SPPCFG 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
SPPDATA 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register Applicable Devices Power-on Reset,
Brown-out Reset
MCLR Resets,
WDT R eset,
RESET Instruction,
Stack Resets
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cell s ind ic ate co nditions do not app ly for the desig nat ed dev ic e.
Note 1: When the wak e-up is d ue to an int errup t and the G IEL or GIEH bit is set, the TOSU, T OSH and T O SL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
3: When the wake-up is due to a n interrupt a nd the GIEL or G IEH bit is se t, the PC is lo aded with th e interrupt
vector (0008h or 0018h).
4: See Table 4-3 for Reset value for specific condition.
5: PORTA<6>, LATA<6> and TRISA<6> are enabled, depending on the oscillator mode selected. When not
enabled as PORTA pins, they are disabled and read ‘0’.
PIC18F2455/2550/4455/4550
DS39632A-page 56 Advance Information 2004 Microchip Technology Inc.
NOTES:
2004 Microchip Technology Inc. Advance Information DS39632A-page 57
PIC18F2455/2550/4455/4550
5.0 MEMORY ORGANIZATION
There are three types of memory in PIC18 Enhanced
Microcontroller devices:
• Program Memory
• Data RAM
• Data EEPROM
As Harvard arc hitecture devices, the da ta and progra m
memories use separate busses; this allows for concur-
rent access of the two memory spaces. The data
EEPROM, for practical purposes, can be regarded as
a peripheral devi ce, since it is addressed and accessed
through a set of control registers.
Additional detailed information on the operation of the
Flash program memory is provided in Section 6.0
“Flash Program Memory”. Data EEPROM is dis-
cussed separately in Section 7.0 “Data EEPROM
Memory”.
5.1 Program Memory Organization
PIC18 microcontrollers implement a 21-bit program
counter, which is capable of addressing a 2-Mbyte
progra m memory sp ace. Acces sing a lo cation b etween
the upper boundary of the physically implemented
memory and the 2-Mbyte address will return all ‘0’s ( a
NOP instr uction).
The PIC18F2455 and PIC18F4455 each have
24 Kbytes of Flas h memory an d can store up to 12,288
single-word instructions. The PIC18F2550 and
PIC18F4550 each have 32 Kbytes of Flash memory
and can store up to 16,384 single-word instructions.
PIC18 devices have two interrupt vectors. The Reset
vector address is at 0000h and the interrupt vector
addresses are at 0008h and 0018h.
The program memory maps for PIC18FX455 and
PIC18FX550 devices are shown in Figure 5-1.
FIGURE 5-1: PROGRAM MEMORY MAP AND STACK FOR PIC18F2455/2550/4455/4550
DEVICES
PC<20:0>
S tack Level 1
•
Stack Level 31
Reset V ector
Lo w Pr i o r i ty Inter rupt Vector
•
•
CALL,RCALL,RETURN
RETFIE,RETLW
21
0000h
0018h
On-Chip
Program Memory
High Priority Interrupt Vect or 0008h
User Memory Space
1FFFFFh
6000h
5FFFh
Read ‘0’
200000h
PC<20:0>
Stack Level 1
•
Stack Level 31
Reset V ector
Low Prio r i ty Interr upt Vec to r
•
•
CALL,RCALL,RETURN
RETFIE,RETLW
21
0000h
0018h
8000h
7FFFh
On-Chip
Program Memory
High Priority Interrupt Vect or 0008h
User Memory Space
Read ‘0’
1FFFFFh
200000h
PIC18FX455 PIC18FX550
PIC18F2455/2550/4455/4550
DS39632A-page 58 Advance Information 2004 Microchip Technology Inc.
5.1.1 PROGRAM COUNTER
The Progra m Counter (PC) s pecifies the address of the
instruction to fetch for execution. The PC is 21 bits wide
and is contained in three separate 8-bit registers. The
low byte, known as the PCL register, is both readable
and wr itable. Th e high byt e, or PCH regi ster, contai ns
the PC<1 5:8> bits; it is not directly re adable or writ able.
Update s to the PCH register are performe d through the
PCLATH register. The upper byte is called PCU. This
register contains the PC<20:16> bits; it is also not
directly readable or writable. Updates to the PCU
register are performed through the PCLATU register.
The contents of PCLATH and PCLATU are transferred
to the program counter by any operation that writes
PCL. Similarly, the upper two bytes of the program
counter are tran sferred to PCL ATH and PCLATU by an
operation that reads PCL. This is useful for computed
offsets to the PC (see Section 5.1.4.1 “Computed
GOTO”).
The PC addresses bytes in the program memory. To
prevent the PC from becoming misaligned with word
instructions, the Least Significant bit of PCL is fixed to
a value of ‘0’. The PC increments by 2 to address
sequential instructions in the program memory.
The CALL, RCALL and GOTO program branch
instructions write to the program counter directly. For
these instructions, the contents of PCLATH and
PCLATU are not transferred to the program counter.
5.1.2 RETURN ADDRESS STACK
The return addre ss s tack al lows a ny co mb ination of u p
to 31 program calls and interrupts to occur. The PC is
pus hed o nt o th e stac k when a CALL or RCALL instruc-
tion is executed or an interrupt is Acknowledged. The
PC value is pulled off the stack on a RETURN, RETLW
or a RETFIE instruction. PC LATU and PCLATH are n ot
affected by any of the RETURN or CALL instruct ions.
The stack operates as a 31-word by 21-bit RAM and a
5-bit Stack Pointer, STKPTR. The stack space is not
part of either program or data sp ace. The Stack Pointer
is readable and writable and the address on the top of
the stack is readable and writable through the
top-of-stack Special File Registers. Data can also be
pushed to, or popped from the stack, using these
registers.
A CALL type inst ruct ion cause s a pus h onto t he stac k;
the Stack Pointer is first incremented and the location
pointed to by the Stack Pointer is written with the
contents of the PC (already pointing to the instruction
following the CALL). A RETURN type ins truc ti on c au se s
a pop from the stack; the contents of the location
pointed to by the STKPTR are transferred to the PC
and then the stack pointer is decremented.
The Stack Pointer is initialized to ‘00000’ after all
Resets. There is no RAM associated with the location
corresponding to a Stack Pointer value of ‘00000’; this
is only a Res et v alu e. Status bit s in dic ate if th e s tack i s
full or has overflowed or has underflowed.
5.1.2.1 Top-of-Stack Access
Only the top of the return address stack (TOS) is
readable and writable. A set of three registers,
TOSU:T OSH:T OSL, hold the content s of the st ack loca-
tion pointed to by the STKP TR register (Figure 5-2). This
allows users to implement a s oftware stack if nec essary.
After a CALL, RCALL or interrupt, the software can read
the pushed value by reading the TOSU:TOSH:TOSL
registers. These values can be placed on a use r defined
software stack. At return time, the software can return
these values to T OSU:T O SH:T O SL and do a return.
The user must disable the global interrupt enable bits
while accessing the stack to prevent inadvertent stack
corruption.
FIGURE 5-2: RETURN ADDRESS STACK AND ASSOCIATED REGISTERS
00011
001A34h
11111
11110
11101
00010
00001
00000
00010
Return Address Stack <20:0>
Top-of-Stack 000D58h
TOSLTOSHTOSU 34h1Ah00h STKPTR<4:0>
Top-of-St a ck R egis ters S tack Pointer
2004 Microchip Technology Inc. Advance Information DS39632A-page 59
PIC18F2455/2550/4455/4550
5.1.2.2 Return Stack Pointer (STKPTR)
The STKP TR register (Regis ter 5-1) cont ains the S tac k
Pointer value, the STKFUL (Stack Full) status bit and
the STKUNF (Stack Underflow) status bits. The value
of the Stack Pointer can be 0 through 31. The Stack
Pointer increments before values are pushed onto the
stack and decrements after values are popped off the
stack. On Reset, the Stack Pointer value will be zero.
The user may read and write the Stack Pointer value.
This feature can be used by a Real-Time Operating
System for return stack maintenance.
After t he PC is pus hed o nto the stac k 31 times (witho ut
popping any values off the stack), the STKFUL bit is
set. The STKFUL bit is cleared by software or by a
POR.
The action that takes place when the stack becomes
full depends on the state of the STVREN (Stack Over-
flow Reset Enable) configuration bit. (Refer to
Section 25.1 “Configura tion Bits” for a de scription of
the device configuration bits.) If STVREN is set
(default), the 31st push will push the (PC + 2) value
onto the stack, set the STKFUL bit and reset the
device. The STKFUL bit will remain set and the Stack
Pointer will be set to zero.
If STVREN is clea red, the STKFUL bi t will be se t on the
31st push and the Stack Pointer will increment to 31.
Any additional pushes will not overwrite the 31st push
and the STKPTR will remain at 31.
When the stack has been popped enough times to
unload th e stack, the ne xt pop will return a value of zero
to the PC and sets the STKUNF bit, while the Stack
Pointer remains at zero. The STKUNF bit will remain
set until cleared by software or until a POR occurs.
5.1.2.3 PUSH and POP Instructions
Since the Top-of-Stack is readable and writable, the
ability to pus h values on to the st ac k an d pul l values off
the stack without disturbing normal program execution
is a desirable feature. The PIC18 instruction set
includes two instructions, PUSH and POP, that permit
the TOS to be manipulated under software control.
T OSU, T OSH and T OS L can be m odifie d to plac e dat a
or a return address on the stack.
The PUSH instruction places the current PC value onto
the stack. This increments the Stack Pointer and loads
the current PC value onto the stack.
The POP instruction discards the current TOS by decre-
menting the Stack Pointer. The previous value pushed
onto the stack then becomes the TOS value.
REGISTER 5-1: STKPTR REGISTER
Note: Returning a value of zero to the PC on an
underflow has the effect of vectoring the
program to the Reset vector, where the
stack conditions can be verified and
appropriate actions can be taken. This is
not the same as a Reset, as the contents
of the SFRs are not affected.
R/C-0 R/C-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
STKFUL(1) STKUNF(1) — SP4 SP3 SP2 SP1 SP0
bit 7 bit 0
bit 7 STKFUL: Stack Full Flag bit(1)
1 = Stack became full or overflowed
0 = Stack has not become full or overflowed
bit 6 STKUNF: Stack Underflow Flag bit(1)
1 = Stack underflow occurred
0 = Stack underflow did not occur
bit 5 Unimplemented: Read as ‘0’
bit 4-0 SP4:SP0: Stack Pointer Locati on bits
Note 1: Bit 7 and bit 6 are c leared by user software or by a POR.
Legend:
R = Readable bit W = Writable bit U = Unimplemented C = Clearable only bit
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC18F2455/2550/4455/4550
DS39632A-page 60 Advance Information 2004 Microchip Technology Inc.
5.1.2.4 Stack Full and Underflow Resets
Device Resets on stack overflow and stack underflow
conditions are enabled by setting the STVREN bit in
Config ura tion Regi ster 4L. Whe n STVREN i s s et, a ful l
or underflow will set the appropriate STKFUL or
STKUNF bit and then cause a device Reset. When
STVREN is cleared, a full or underflow condition will set
the appropriate STKFUL or STKUNF bit but not cause
a device Reset. The STKFUL or STKUNF bits are
cleared by the user software or a Power-on Reset.
5.1.3 FAST REGISTER STACK
A fast register stack is provided for the Status, WREG
and BSR registers to provide a “fast return” option for
interrupts. Each stack is only one level deep and is
neither readable nor writable. It is loaded with the
current value of the corresponding register when the
processor vectors for an interrupt. All interrupt sources
will push v alue s in to th e stac k regi ste rs. T he v alues in
the regi st ers ar e then load ed ba ck i nto th eir a ssociate d
registers if the RETFIE, FAST instruction is used to
return from the interrupt.
If both low and high priority interrupts are enabled, the
stack registers cannot be used reliably to return from
low priority interrupts. If a high priority interrupt occurs
while servicing a low priority interrupt, the stack register
values stored by the low priority interrupt will be
overwritten. In these cases, users must save the key
registers in software during a low priority interrupt.
If interrupt pri ority is not used, all interrupts may use the
fast register stack for returns from interrupt. If no
inter rupts are used, the fast regis te r st ac k c an be used
to restore the Status, WREG and BSR registers at the
end of a subroutine call. To use the fast register stack
for a su broutin e cal l, a CALL label, FAST instruction
must be executed to save the Status, WREG and BSR
registers to the fast register stack. A RETURN, FAST
instruction is then executed to restore these registers
from the fast register stack.
Example 5-1 shows a source code example that uses
the fast register stack during a subroutine call and
return.
EXAMPLE 5-1: FAST REGISTER STACK
CODE EXAMPLE
5.1.4 LOOK-UP TABLES IN PROGRAM
MEMORY
There may be programming situations that require the
creation of data structures, or look-up tables, in
program memory. For PIC18 devices, look-up tables
can be implemented in two way s :
• Computed GOTO
• Table Reads
5.1.4.1 Computed GOTO
A comput ed GOTO i s a cc om pli sh ed b y a ddi ng a n offset
to the program counter. An example is shown in
Example 5-2.
A look-up table can be formed with an ADDWF PCL
instruction and a group of RETLW nn instructions. The
W register is loa ded with an offset into the table befo re
executi ng a c al l to tha t t a ble . Th e fi rst ins tru cti on o f th e
called routine is the ADDWF PCL instruction. The next
instruction executed will be one of the RETLW nn
instructions, that returns the value ‘nn’ to the calling
function.
The offset value (in WREG) specifies the number of
bytes that the program counter should advance and
should be mu ltiples of 2 (LSb = 0).
In this method, only one data byte may be stored in
each instruction location and room on the return
address stack is required.
EXAMPLE 5-2: COMPUTED GOTO USING
AN OFFSET VALUE
5.1.4.2 Table Reads and Table Writes
A better method of storing data in program memory
allow s two bytes of dat a to be stored in each instruc tion
location.
Look-up table data may be stored two bytes per
program word by using table reads and writes. The
Table Pointer (TBLPTR) register specifies the byte
address and the Table Latch (TABLAT) register
cont ains the da ta that is read from o r written to pro gram
memory. Data is transferred to or from program
memory one byte at a time.
Table read and table write operations are discussed
further in Section 6.1 “Table Reads and Table
Writes”.
CALL SUB1, FAST ;STATUS, WREG, BSR
;SAVED IN FAST REGISTER
;STACK
•
•
SUB1 •
•
RETURN, FAST ;RESTORE VALUES SAVED
;IN FAST REGISTER STACK
MOVF OFFSET, W
CALL TABLE
ORG nn00h
TABLE ADDWF PCL
RETLW nnh
RETLW nnh
RETLW nnh
.
.
.
2004 Microchip Technology Inc. Advance Information DS39632A-page 61
PIC18F2455/2550/4455/4550
5.2 PIC18 Instruction Cycle
5.2.1 CLOCKING SCHEME
The m icroc on t rol l er c l oc k i n pu t, w het h er fro m an i n te r-
nal or external source, is internally divided by four to
generate four non-overlapping quadrature clocks (Q1,
Q2, Q3 and Q4). Internally, the program counter is
incremented on every Q1; the instruction is fetched
from the program memory and latched into the instruc-
tion regis ter during Q4. The ins truc tion is decoded and
executed during the following Q1 through Q4. The
clocks and instruction execution flow are shown in
Figure 5-3.
5.2.2 INSTRUCTION FLOW/PIPELINING
An “Instruction Cycle” consists of four Q cycles: Q1
through Q4. The instruction fetch and execute are pipe-
lined in such a manner that a fetch takes one instruction
cycle, while the decode and execute takes another
instr ucti on cycl e. H oweve r, due to t he pipel ini ng, each
instruction effectively executes in one cycle. If an
instruc tion causes the program count er to change (e.g.,
GOTO), then two cycles are required to complete the
instruction (Example 5-3).
A fetch cycle begins with the Program Counter (PC)
incrementing in Q1.
In the ex ecution cycle , the fetched instruction i s latched
into the Instruction Register (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q 3 and Q4 c ycles. Data mem ory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 5-3: CLOCK/INSTRUCTION CYCLE
EXAMPLE 5-3: INSTRUCTION PIPELINE FLOW
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Q1
Q2
Q3
Q4
PC
OSC2/CLKO
(RC mode)
PC PC + 2 PC + 4
Fetch INST (PC)
Execute INST (PC – 2)
Fetch INST (PC + 2)
Execute INST (PC)
Fetch INST (PC + 4)
Execute I NST (P C + 2)
Internal
Phase
Clock
Note: All instructions are single cycle, except for any program branches. These take two cycles since the
fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then
executed.
TCY0TCY1TCY2TCY3TCY4TCY5
1. MOVLW 55h Fetch 1 Execute 1
2. MOVWF PORTB Fetch 2 Execute 2
3. BRA SUB_1 Fetch 3 Execu te 3
4. BSF PORTA, BIT3 (Forced NOP) Fetch 4 Flush (NOP)
5. Instruction @ address SUB_1 Fetch SUB_1 Execute SUB_1
PIC18F2455/2550/4455/4550
DS39632A-page 62 Advance Information 2004 Microchip Technology Inc.
5.2.3 INSTRUCTIONS IN PROGRAM
MEMORY
The program memory is addressed in bytes. Instruc-
tions are stored as two bytes or four bytes in program
memory. The Least Significant Byte of an instruction
word is always stored in a program memory location
with an even add ress (LSb = 0). To maintain alignment
with i nstruction bo undaries , the PC i ncrement s in s teps
of 2 a nd the LSb wi ll always read ‘0’ (see Section 5.1.1
“Program Counter”).
Figure 5-4 s hows an ex am ple of h ow in st ruc tion w ord s
are stored in the program memory.
The CALL and GOTO instructions have the absolute pro-
gram memory address embedded into the instruction.
Since instructions are always stored on word bound-
aries, the data contained in the instruction is a word
address. The word address is written to PC<20:1>,
which accesses the desired byte address in program
memory. Instruction #2 in Figure 5-4 shows how the
instruction, GOTO 0006h, is encoded in the program
memory. Program branch instructions, which encode a
relative address offset, operate in the same manner . The
of fset value stored in a branch instruction represent s the
number of single-word instructions that the PC will be
offset by. Section 26.0 “Instruction Set Summary”
provides further details of the instruction s et.
FIGURE 5-4: INSTRUCTIONS IN PROGRAM MEMORY
5.2.4 TWO-WORD INSTRUCTIONS
The standard PIC18 instruction set has four two-word
instructions: CALL, MOVFF, GOTO and LSFR. In all
cases, the se cond wor d of th e inst ruct ions al ways has
‘1111’ as its four M ost Si gnifican t bit s; the ot her 12 bit s
are literal data, usually a data memory address.
The use of ‘1111’ in the 4 MSbs of an instruction
specif ies a s peci al form of NOP. If the in str uction is exe-
cuted in proper sequence – immediately after the first
word – the data in the second word is accessed and
used by the instruction sequence. If the first word is
skipped for some reason and the second word is
executed by itself, a NOP is executed instead. This is
necessary for cases when the two-word instruction is
prec ed ed b y a co nd i ti ona l in st ru ct i on t h at c han ge s t he
PC. Example 5-4 shows how this works.
EXAMPLE 5-4: TWO-WORD INSTRUCTIONS
Word Address
LSB = 1LSB = 0↓
Program Memory
Byte Locations → 000000h
000002h
000004h
000006h
Instruction 1: MOVLW 055h 0Fh 55h 000008h
Instruction 2: GOTO 0006h EFh 03h 00000Ah
F0h 00h 00000Ch
Instruction 3: MOVFF 123h, 456h C1h 23h 00000Eh
F4h 56h 000010h
000012h
000014h
Note: See Section 5.5 “Program Memory and
the Extended Instruction Set” for
information on two-word instruction in the
extended instruction set.
CASE 1:
Object Code Source Code
0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0?
1100 0001 0010 0011 MOVFF REG1, REG2 ; No, skip this word
1111 0100 0101 0110 ; Execute this word as a NOP
0010 0100 0000 0000 ADDWF REG3 ; continue code
CASE 2:
Object Code Source Code
0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0?
1100 0001 0010 0011 MOVFF REG1, REG2 ; Yes, execute this word
1111 0100 0101 0110 ; 2nd word of instruction
0010 0100 0000 0000 ADDWF REG3 ; continue code
2004 Microchip Technology Inc. Advance Information DS39632A-page 63
PIC18F2455/2550/4455/4550
5.3 Data Memory Organization
The da ta me mo ry i n P IC 1 8 d ev ic es is imp lem en t ed as
static RAM. Each register in the data memory has a
12-bit address, allowing up to 4096 bytes of data
memory. The memory spac e is divided i nto as man y as
16 banks that contain 256 bytes each.
PIC18F2455/2550/4455/4550 devices implement 8
complete banks, for a total of 2048 bytes. Figure 5-5
shows the data memory organization for the devices.
The data memory contains Special Function Registers
(SFRs) and General Purpose Registers (GPRs). The
SFRs are used for control and status of the controller
and per ipheral functio ns, while GP Rs are used for dat a
storage and scratch pad operations in the user’s
applic ation. Any read of an unim plemente d locat ion will
read as ‘0’s.
The instruction set and architecture allow operations
across all banks. The entire data memory may be
accessed by Direct, Indirect or Indexed Addressing
modes. Addressing modes are discussed later in this
subsection.
To ensure that commonly used registers (SFRs and
select GP Rs) c an b e ac cess ed i n a singl e c ycle, PIC1 8
devices im pl em ent an Ac ce ss Ba nk . Th is i s a 256-by te
memor y space that provid es fa st acc ess to SFRs and
the lower portion of GPR Bank 0 without using the
BSR. Section 5.3.3 “Access Bank” provides a
detailed descr iption of the Access RAM.
5.3.1 USB RAM
Banks 4 through 7 of the data memory are actually
mapped to special dual port RAM. When the USB
module is disabled, the GPRs in these banks are used
like any other GPR in the data memory space.
When the USB module is enabled, the memory in these
banks is allocated as buffer RAM for USB operation.
This area is shared between the microcontroller core
and the USB Serial Interface Engine (SIE) and is used
to transfer data directly between the two.
It is theore tically possib le to use the areas of USB RAM
that are not allocated as USB buffers for normal
scrat chpad mem ory or ot her va riab le s tora ge. In pr ac-
tice, the dyn am ic natu re of b uffer allocation makes thi s
risky at best. Additionally , Bank 4 is used for USB buffer
management when the module is enabled and should
not be used for any other purposes during that time.
Additional information on USB RAM and buffer
operation is provided in Section 17.0 “Universal
Serial Bus (USB)”.
5.3.2 BANK SELECT REGISTER (BSR)
Large areas of data memory require an efficient
addressing scheme to make rapid access to any
address possible. Ideally, this means that an entire
address doe s no t ne ed to be provi ded for e ach read or
write operation. For PIC18 devices, this is accom-
plished with a RAM banking scheme. This divides the
memory space into 16 contiguous banks of 256 bytes.
Depending on the instruction, each location can be
addressed directly by its full 12-bit address, or an 8-bit
low-order address and a 4-bit bank pointer.
Most in struct ions in th e PIC18 instruct ion se t make us e
of th e bank poin ter, known as the Bank Select Reg ister
(BSR). This SFR holds the 4 Most Significant bits of a
location’s address; the instruction itself includes the
8 Least Significant bits. Only the four lower bits of the
BSR are implemented (BSR3:BSR0). The upper four
bit s are unused; the y will always read ‘0’ an d cannot be
written to. T he BSR can be load ed directly by using the
MOVLB instruction.
The value of the BSR indicates the bank in data mem-
ory; th e 8 bit s in the instru ction s how the lo cation in the
bank an d can be th ought of as an of fset from the bank’ s
lower boundary. The relationship between the BSR’s
value a nd the bank div ision i n data memo ry is sho wn in
Figure 5-6.
Since up to 16 regis ters may share the s ame low -order
address, the user must always be careful to ensure that
the proper bank is selected before performing a data
read or w ri te. For example , wri ting what s ho uld b e p r o-
gram data to an 8-bit address of F9h while the BSR is
0Fh will end up resetting the program counter.
While any bank can be s el ec ted, only th os e ba nk s th at
are actually implemented can be read or written to.
Writes to unimplemented banks are ignored, while
reads from unimplemented banks will return ‘0’s. Even
so, the Status register will still be affected as if the
operation was successful. The data memory map in
Figure 5-5 indicates which banks are implemented.
In the core PIC18 instruction set, only the MOVFF
instruction fully specifies the 12-bit address of the
source a nd target reg isters. This i nstruction ig nores the
BSR comple tely when it ex ecutes. All othe r instruction s
include only the low-order address as an operand and
must use either the BSR or the Access Bank to locate
their targ et regis te rs.
Note: The operation of some aspects of data
memory are changed when the PIC18
extended instruction set is enabled. See
Section 5.6 “Data Memory and the
Extended Instruction Set” for more
information.
PIC18F2455/2550/4455/4550
DS39632A-page 64 Advance Information 2004 Microchip Technology Inc.
FIGURE 5-5: DATA MEMORY MAP FOR PIC18F2455/2550/4455/4550 DEVICES
Bank 0
Bank 1
Bank 14
Bank 15
Data Memory Map
BSR<3:0>
= 0000
= 0001
= 1111
060h
05Fh
F60h
FFFh
00h
5Fh
60h
FFh
Access Bank
When a = 0:
The BSR is ignored and the
Access Bank is used.
The first 96 bytes are
general purpose RAM
(from Bank 0).
The remain ing 160 byt es are
Special Function Registers
(from Bank 15).
When a = 1:
The BSR spe cifies th e Bank
used by the instruction.
F5Fh
F00h
EFFh
1FFh
100h
0FFh
000h
Access RAM
FFh
00h
FFh
00h
FFh
00h
GPR
GPR
SFR
Access RAM High
Access RA M Low
Bank 2
= 0110
= 0010
(SFRs)
2FFh
200h
3FFh
300h
4FFh
400h
5FFh
500h
6FFh
600h
7FFh
700h
800h
Bank 3
Bank 4
Bank 5
Bank 6
Bank 7
Bank 8
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
00h
GPR
GPR(1)
GPR
GPR(1)
GPR(1)
GPR(1)
FFh
= 0011
= 0100
= 0101
= 0111
= 1000
Unused
Read as 00h
to
= 1110
Note 1: These banks al so serve as RAM buffe r for USB operation. Se e Section 5.3.1 “USB RAM” f or more
information.
Unused
2004 Microchip Technology Inc. Advance Information DS39632A-page 65
PIC18F2455/2550/4455/4550
FIGURE 5-6: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING)
5.3.3 ACCESS BANK
While the use of the BSR with an embedded 8-bit
address allows users to address the entire range of
data mem ory, it also mean s that the user mu st a lways
ensure that the correct bank is selected. Otherwise,
data may be read from or written to the wrong location.
This can be disastrous if a GPR is the intended target
of an operation, but an SFR is written to instead.
Verifying and/or changing the BSR for each read or
write to data memory can become very inefficient.
To stre amline access for the most com monly used dat a
memory locations, the data memory is configured with
an Access Bank, which allows users to access a
mapped block of memory without specifying a BSR.
The Access Bank consists of the first 96 bytes of
memory (00h-5Fh) in Bank 0 and the last 160 bytes of
memory (60 h-FFh) in Block 15 . The lower half is known
as the “Access RAM” and is composed of GPRs. This
upper half is also where the device’s SFRs are
mapped. These two areas are mapped contiguously in
the Access Bank and can be addressed in a linear
fashion by an 8-bit address (Figure 5-5).
The Access Bank is used by core PIC18 instructions
that include the Access RAM bit (the ‘a’ parameter in
the instruction). When ‘a’ is equal to ‘1’, the in st ru ct ion
uses the BSR and the 8-bit address included in the
opcode for the data memory address. When ‘a’ is ‘0’,
however, the instruction is forced to use the Access
Bank address map; the current value of the BSR is
ignored enti r el y.
Using this “forced” addressing allows the instruction to
operate on a data address in a single cycle, without
updating the BSR first. For 8-bit addresses of 60h and
above, t his mean s that use rs can ev aluate an d opera te
on SFRs more efficiently. The Access RAM below 60h
is a goo d place for da ta values th at the user might need
to access rapidly, such as immediate computational
results or common program variables. Access RAM
also allows for faster and more code efficient context
saving and switching of va riables.
The mapping of the Access Bank is slightly different
when the extended instruction set is enabled (XINST
configuration bit = 1). This is discussed in more detail
in Section 5.6.3 “Mapping The Access Bank in
Indexed Literal Offset Mode”.
5.3.4 GE NERAL PURPOSE
REGISTER FILE
PIC18 devices may have banked memory in the GPR
area. T his is dat a RAM, w hich is avai lable f or use by all
instructions. GPRs start at the bottom of Bank 0
(address 000h) and grow upwards towards the bottom
of the SFR area. GPRs are not initialized by a
Power-on Reset and are unchanged on all other
Resets.
Note 1: The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to
the registers of the Access Bank.
2: The MOVFF instruction embeds the entire 12-bit address in the instruction.
Data Memory
Bank Select(2)
70
From Opcode(2)
0000
000h
100h
200h
300h
F00h
E00h
FFFh
Bank 0
Bank 1
Bank 2
Bank 14
Bank 15
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
Bank 3
through
Bank 13
0011 11111111
70
BSR(1)
PIC18F2455/2550/4455/4550
DS39632A-page 66 Advance Information 2004 Microchip Technology Inc.
5.3.5 SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers
used by the CPU a nd peripheral mo dules for controlling
the desired operation of the device. These reg isters are
implem ented as st atic RAM in th e dat a me mory sp ac e.
SFRs st art at th e top of dat a memory an d extend do wn-
ward to occupy the top segment of Bank 15, from F60h
to FFFh. A list of these registers is given in Table 5-1
and Table 5-2.
The SFRs can be classified into two sets: those
associated with the “core” device functionality (ALU,
Resets and interrupts) and those related to the
peripheral functions. The reset and interrupt registers
are described in their respective chapters, while the
ALU’s Status register is described later in this section.
Registers related to the operation of a peripheral
features are described in the chapter for that
peripheral.
The SFRs are typically distributed among the
periphera ls w ho se fun cti ons th ey c ontr ol. U nus ed SFR
locations are unimplemented and read as ‘0’s.
TABLE 5-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F2455/2550/4455/4550 DEVICES
Address Name Address Name Address Name Address Name Address Name
FFFh TOSU FDFh INDF2(1) FBFh CCPR1H F9Fh IPR1 F7Fh UEP15
FFEh TOSH FDEh POSTINC2(1) FBEh CCPR1L F9Eh PIR1 F7Eh UEP14
FFDh TOSL FDDh POSTDEC2(1) FBDh CCP1CON F9Dh PIE1 F7Dh UEP13
FFCh STKPTR FDCh PREINC2(1) FBCh CCPR2H F9Ch —(2) F7Ch UEP12
FFBh PCLATU FDBh PLUSW2(1) FBBh CCPR2L F9Bh OSCTUNE F7Bh UEP11
FFAh PCLATH FDAh FSR2H FBAh
CCP2CON
F9Ah —(2) F7Ah UEP10
FF9h PCL FD9h FSR2L FB9h —(2) F99h —(2) F79h UEP9
FF8h TBLPTRU FD8h STATUS FB8h BAUDCON F98h —(2) F78h UEP8
FF7h TBLPTRH FD7h TMR0H FB7h ECCP1DEL F97h —(2) F77h UEP7
FF6h TBLPTRL FD6h TMR0L FB6h ECCP1AS(3) F96h TRISE(3) F76h UEP6
FF5h TABLAT FD5h T0CON FB5h CVRCON F95h TRISD(3) F75h UEP5
FF4h PRODH FD4h —(2) FB4h CMCON F94h TRISC F74h UEP4
FF3h PRODL FD3h OSCCON FB3h TMR3H F93h TRISB F73h UEP3
FF2h INTCON FD2h LVDCON FB2h TMR3L F92h TRISA F72h UEP2
FF1h INTCON2 FD1h WDTCON FB1h T3CON F91h —(2) F71h UEP1
FF0h INTCON3 FD0h RCON FB0h SPBRGH F90h —(2) F70h UEP0
FEFh INDF0(1) FCFh TMR1H FAFh SPBRG F8Fh —(2) F6Fh UCFG
FEEh POSTINC0(1) FCEh TMR1L FAEh RCREG F8Eh —(2) F6Eh UADDR
FEDh POSTDEC0(1) FCDh T1CON FADh TXREG F8Dh LATE(3) F6Dh UCON
FECh PREINC0(1) FCCh TMR2 FACh TXSTA F8Ch LATD(3) F6Ch USTAT
FEBh PLUSW0(1) FCBh PR2 FABh RCSTA F8Bh LATC F6Bh UEIE
FEAh FSR0H FCAh T2CON FAAh EEADRH F8Ah LATB F6Ah UEIR
FE9h FSR0L FC9h SSPBUF FA9h EEADR F89h LATA F69h UIE
FE8h WREG FC8h SSPADD FA8h EEDATA F88h —(2) F68h UIR
FE7h INDF1(1) FC7h SSPSTAT FA7h EECON2(1) F87h —(2) F67h UFRMH
FE6h POSTINC1(1) FC6h SSPCON1 FA6h EECON1 F86h —(2) F66h UFRML
FE5h POSTDEC1(1) FC5h SSPCON2 FA5h —(2) F85h —(2) F65h SPPCON(3)
FE4h PREINC1(1) FC4h ADRESH FA4h —(2) F84h PORTE F64h SPPEPS(3)
FE3h PLUSW1(1) FC3h ADRESL FA3h —(2) F83h PORTD(3) F63h SPPCFG(3)
FE2h FSR1H FC2h ADCON0 FA2h IPR2 F82h PORTC F62h SPPDATA(3)
FE1h FSR1L FC1h ADCON1 FA1h PIR2 F81h PORTB F61h —(2)
FE0h BSR FC0h ADCON2 FA0h PIE2 F80h PORTA F60h —(2)
Note 1: Not a physical register.
2: Unimplemented registers are read as ‘0’.
3: Registers are implemented only on 40/44-pin devices.
2004 Microchip Technology Inc. Advance Information DS39632A-page 67
PIC18F2455/2550/4455/4550
TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2455/2550/4455/4550)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR Details
on page
TOSU — — — Top-of-S tack Upper Byte (TOS<20:16>) ---0 0000 51, 58
TOSH Top-of-Stack High Byte (TOS<15:8>) 0000 0000 51, 58
TOSL Top-of-Stack Low Byte (TOS<7:0>) 0000 0000 51, 58
STKPTR STKOVF STKUNF — Return Stack Pointer 00-0 0000 51, 59
PCLATU ——bit 21
(1) Holding Register for PC<20:16> ---0 0000 51, 58
PCLATH Holding Register for PC<15:8> 0000 0000 51, 58
PCL PC Low Byte (PC<7:0>) 0000 0000 51, 58
TBLPTRU —— bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000 51, 82
TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 51, 82
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 0000 0000 51, 82
TABLAT Program Memory Table Latch 0000 0000 51, 82
PRODH Product Register High Byte xxxx xxxx 51, 95
PRODL Product Register Low Byte xxxx xxxx 51, 95
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 51, 99
INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 —TMR0IP—RBIP1111 -1-1 51, 100
INTCON3 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF 11-0 0-00 51, 101
INDF0 Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register) N/A 51, 73
POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register) N/A 51, 74
POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register) N/A 51, 74
PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) N/A 51, 74
PLUSW0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) –
value of FSR0 offset by W N/A 51, 74
FSR0H — — — — Indirect Data Memory Address Pointer 0 High ---- 0000 51, 73
FSR0L Indirect Data Memory Address Pointer 0 Low Byte xxxx xxxx 51, 73
WREG Working Register xxxx xxxx 51
INDF1 Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register) N/A 51, 73
POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register) N/A 51, 74
POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register) N/A 51, 74
PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) N/A 51, 74
PLUSW1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) –
value of FSR1 offset by W N/A 51, 74
FSR1H — — — — Indirect Data Memory Address Pointer 1 High ---- 0000 51, 73
FSR1L Indirect Data Memory Address Pointer 1 Low Byte xxxx xxxx 51, 73
BSR — — — — Bank Select Register ---- 0000 52, 63
INDF2 Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register) N/A 52, 73
POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register) N/A 52, 74
POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register) N/A 52, 74
PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) N/A 52, 74
PLUSW2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) –
value of FSR2 offset by W N/A 52, 74
FSR2H — — — — Indirect Data Memory Address Pointer 2 High ---- 0000 52, 73
FSR2L Indirect Data Memory Address Pointer 2 Low Byte xxxx xxxx 52, 73
STATUS — — —NOVZDCC---x xxxx 52, 71
TMR0H Timer0 Register H igh By te 0000 0000 52, 127
TMR0L Timer0 Register Low Byte xxxx xxxx 52, 127
T0CON TMR0ON T08BIT T0CS T0SE T0PS3 T0PS2 T0PS1 T0PS0 1111 1111 52, 125
Legend: x = unknown , u = unchanged, — = unimplemented, q = value depe nds on cond iti on
Note 1: Bit 21 of the PC is only available in Serial Programming mode.
2: The SBOREN bit is only available when BOREN<1:0> = 01; otherwise, the bit reads as ‘0’.
3: These registers and/or bits are not implemented on 28-pin dev ices and are read as ‘ 0’. Reset values are shown for 40/44-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
4: RA6 is configured as a port pin based on various primary oscillator modes. When the port pin is disabled, all of the associated bits read ‘0’.
5: RE3 is only available as a port pin when the MCLRE configuration bit is clear; otherwise, the bit reads as ‘0’.
6: RC5 and RC4 are only available as port pins when the USB module is disabled (UCON<3> = 0).
PIC18F2455/2550/4455/4550
DS39632A-page 68 Advance Information 2004 Microchip Technology Inc.
OSCCON IDLEN IRCF2 IRCF1 IRCF0 OSTS FLTS SCS1 SCS0 0100 q000 52, 32
HLVDCON VDIRMAG — IRVST LVDEN LVDL3 LVDL2 LVDL1 LVDL0 0-00 0101 52, 273
WDTCON — — — — — — —SWDTEN--- ---0 52, 292
RCON IPEN SBOREN(2) —RITO PD POR BOR 0q-1 11q0 52, 44
TMR1H Timer1 Register H igh By te xxxx xxxx 52, 133
TMR1L Timer1 Regi st er Low By tes xxxx xxxx 52, 133
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 5 2, 129
TMR2 Timer2 Regist er 0000 0000 52, 136
PR2 Timer2 Period Register 1111 1111 52, 136
T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 5 2, 135
SSPBUF SSP Receive Buffer/Transmit Register xxxx xxxx 52, 194,
202
SSPADD SSP Address Register in I2C™ Slave Mode. SSP Baud Rate Reload Register in I2C Master Mode. 0000 0000 5 2, 202
SSPSTAT SMP CKE D/A PSR/WUA BF 0000 0000 52, 194,
203
SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 52, 195,
204
SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 52, 205
ADRESH A/D Result Register High Byte xxxx xxxx 52, 262
ADRESL A/D Result Register Low Byte xxxx xxxx 52, 262
ADCON0 —— CHS3 CHS2 CHS1 CHS0 GO/DONE ADON --00 0000 52, 253
ADCON1 —— VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0qqq 5 2, 254
ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0-00 0000 5 2, 255
CCPR1H Capture/Co mpare/PWM Regi ster 1 High Byte xxxx xxxx 53, 142
CCPR1 L Ca ptu re /C om pare/ PWM Registe r1 Low Byt e xxxx xxxx 53, 142
CCP1CON P1M1(3) P1M0(3) DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 53, 141,
149
CCPR2H Capture/Co mpare/PWM Regi ster 2 High Byte xxxx xxxx 53, 142
CCPR2 L Ca ptu re /C om pare/ PWM Registe r2 Low Byt e xxxx xxxx 53, 142
CCP2CON —— DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 0000 0000 5 3, 141
BAUDCON ABDOVF RCMT — SCKP BRG16 — WUE ABDEN 01-0 0-00 5 3, 236
ECCP1DEL PRSEN PDC6(3) PDC5(3) PDC4(3) PDC3(3) PDC2(3) PDC1(3) PDC0(3) 0000 0000 53, 158
ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1(3) PSSBD0(3) 0000 0000 5 3, 159
CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000 0000 53, 269
CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0111 5 3, 263
TMR3H Timer3 Register H igh By te xxxx xxxx 53, 139
TMR3L Timer3 Register Low Byte xxxx xxxx 53, 139
T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 5 3, 137
SPBRGH USART Baud Rate Generator High Byte 0000 0000 53, 237
SPBRG USART Baud Rate Generator 0000 0000 53, 237
RCREG USART Receive Register 0000 0000 53, 244
TXREG USART Transmit Register 0000 0000 53, 242
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 53, 234
RCSTA SPEN RX9 SREN CREN ADEN FERR OERR RX9D 0000 000x 5 3, 235
TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2455/2550/4455/4550) (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR Details
on page
Legend: x = unknown , u = unchanged, — = unimplemented, q = value depe nds on cond iti on
Note 1: Bit 21 of the PC is only available in Serial Programming mode.
2: The SBOREN bit is only available when BOREN<1:0> = 01; otherwise, the bit reads as ‘0’.
3: These registers and/or bits are not implemented on 28-pin dev ices and are read as ‘ 0’. Reset values are shown for 40/44-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
4: RA6 is configured as a port pin based on various primary oscillator modes. When the port pin is disabled, all of the associated bits read ‘0’.
5: RE3 is only available as a port pin when the MCLRE configuration bit is clear; otherwise, the bit reads as ‘0’.
6: RC5 and RC4 are only available as port pins when the USB module is disabled (UCON<3> = 0).
2004 Microchip Technology Inc. Advance Information DS39632A-page 69
PIC18F2455/2550/4455/4550
EEADR EEPROM Address Register 0000 0000 53, 89
EEDATA EEPROM Data Register 0000 0000 53, 89
EECON2 EEPROM Control Register 2 (not a physical register ) 0000 0000 53, 80
EECON1 EEPGD CFGS — FREE WRERR WREN WR RD xx-0 x000 53, 81
IPR2 OSCFIP CMIP USBIP EEIP BCLIP LVDIP TMR3IP CCP2IP 1111 1111 54, 107
PIR2 OSCFIF CMIF USBIF EEIF BCLIF LVDIF TMR3IF CCP2IF 0000 0000 54, 103
PIE2 OSCFIE CMIE USBIE EEIE BCLIE LVDIE TMR3IE CCP2IE 0000 0000 54, 105
IPR1 SPPIP(3) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 5 4, 106
PIR1 SPPIF(3) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 5 4, 102
PIE1 SPPIE(3) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 54, 104
OSCTUNE INTSRC —— TUN4 TUN3 TUN2 TUN1 TUN0 0--0 0000 54, 28
TRISE(3) — — — — — TRISE2 TRISE1 TRISE0 0000 -111 5 4, 124
TRISD(3) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 1111 1111 5 4, 122
TRISC TRISC7 TRISC6 — — — TRISC2 TRISC1 TRISC0 11-- -111 54, 119
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 54, 116
TRISA — TRISA6(4) TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 -111 1111 54, 113
LATE(3) — — — — — LATE2 LATE1 LATE0 ---- -xxx 5 4, 124
LATD(3) LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 xxxx xxxx 54, 122
LATC LATC7 LATC6 — — — LATC2 LATC1 LATC0 xx-- -xxx 54, 119
LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx xxxx 54, 116
LATA —LATA6
(4) LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 xxxx xxxx 54, 113
PORTE RDPU(3) — — —RE3
(5) RE2(3) RE1(3) RE0(3) 0--- xxxx 54, 123
PORTD(3) RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx 5 4, 122
PORTC RC7 RC6 RC5(6) RC4(6) — RC2 RC1 RC0 xxxx -xxx 54, 119
PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 54, 116
PORTA —RA6
(4) RA5 RA4 RA3 RA2 RA1 RA0 -x0x 0000 54, 113
UEP15 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 5 5, 169
UEP14 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 5 5, 169
UEP13 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 5 5, 169
UEP12 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 5 5, 169
UEP11 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 55, 169
UEP10 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 5 5, 169
UEP9 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 55, 169
UEP8 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 55, 169
UEP7 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 55, 169
UEP6 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 55, 169
UEP5 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 55, 169
UEP4 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 55, 169
UEP3 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 55, 169
UEP2 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 55, 169
UEP1 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 55, 169
UEP0 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 55, 169
TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2455/2550/4455/4550) (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR Details
on page
Legend: x = unknown , u = unchanged, — = unimplemented, q = value depe nds on cond iti on
Note 1: Bit 21 of the PC is only available in Serial Programming mode.
2: The SBOREN bit is only available when BOREN<1:0> = 01; otherwise, the bit reads as ‘0’.
3: These registers and/or bits are not implemented on 28-pin dev ices and are read as ‘ 0’. Reset values are shown for 40/44-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
4: RA6 is configured as a port pin based on various primary oscillator modes. When the port pin is disabled, all of the associated bits read ‘0’.
5: RE3 is only available as a port pin when the MCLRE configuration bit is clear; otherwise, the bit reads as ‘0’.
6: RC5 and RC4 are only available as port pins when the USB module is disabled (UCON<3> = 0).
PIC18F2455/2550/4455/4550
DS39632A-page 70 Advance Information 2004 Microchip Technology Inc.
UCFG UTEYE UOEMON — UPUEN UTRDIS FSEN UPP1 UPP0 00-0 0000 5 5, 166
UADDR — ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 -000 0000 55, 170
UCON — PPBRST SE0 PKTDIS USBEN RESUME SUSPND —-0x0 000- 5 5, 164
USTAT — ENDP3 ENDP2 ENDP1 ENDP0 DIR PPBI —-xxx xxx- 55, 168
UEIE BTSEE —— BTOEE DFN8EE CRC16EE CRC5EE PIDEE 0--0 0000 55, 181
UEIR BTSEF —— BTOEF DFN8EF CRC16EF CRC5EF PIDEF 0--0 0000 55, 180
UIE — SOFIE STALLIE IDLEIE TRNIE ACTIVIE UERRIE URSTIE -000 0000 55, 179
UIR — SOFIF STALLIF IDLEIF TRNIF ACTIVIF UERRIF URSTIF -000 0000 55, 178
UFRMH — — — — — FRM10 FRM9 FRM8 ---- -xxx 5 5, 170
UFRML FRM7 FRM6 FRM5 FRM4 FRM3 FRM2 FRM1 FRM0 xxxx xxxx 55, 170
SPPCON(3) — — — — — — SPPOWN SPPEN ---- --00 55, 187
SPPEPS(3) RDSPP WRSPP — BUSY ADDR3 ADDR2 ADDR1 ADDR0 00-0 0000 55, 191
SPPCFG(3) CLKCFG1 CLKCFG0 CSEN CLK1EN WS3 WS2 WS1 WS0 0000 0000 55, 188
SPPDATA(3) DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 0000 0000 55, 192
TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2455/2550/4455/4550) (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR Details
on page
Legend: x = unknown , u = unchanged, — = unimplemented, q = value depe nds on cond iti on
Note 1: Bit 21 of the PC is only available in Serial Programming mode.
2: The SBOREN bit is only available when BOREN<1:0> = 01; otherwise, the bit reads as ‘0’.
3: These registers and/or bits are not implemented on 28-pin dev ices and are read as ‘ 0’. Reset values are shown for 40/44-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
4: RA6 is configured as a port pin based on various primary oscillator modes. When the port pin is disabled, all of the associated bits read ‘0’.
5: RE3 is only available as a port pin when the MCLRE configuration bit is clear; otherwise, the bit reads as ‘0’.
6: RC5 and RC4 are only available as port pins when the USB module is disabled (UCON<3> = 0).
2004 Microchip Technology Inc. Advance Information DS39632A-page 71
PIC18F2455/2550/4455/4550
5.3.6 STATUS REGISTER
The S tatus register , shown in Register 5-2, contains the
arithmetic status of the ALU. As with any other SFR, it
can be the operand for any inst ruc tio n.
If the Status reg ister is the d estinatio n for an instruct ion
that af fect s the Z, DC, C, OV or N bit s, the result s of the
instruction are not written; instead, the status is
updated accord ing to t he inst ruct ion pe rformed. The re-
fore, the res ul t of an ins tru cti on w i th the Status reg ister
as its destinatio n may be dif ferent than intended . As an
example, CLRF STATUS will se t the Z bit and lea ve the
remaining Status bits unchanged (‘000u u1uu’).
It is recommended that only BCF, BSF, SWAPF, MOVFF
and MOVWF instructions are used to alter the Status
register, because t hese instru ctions do n ot af fec t t he Z,
C, DC, OV or N bits in the Status register.
For other i ns truc tio ns that do n ot a f fect Status bi t s , se e
the instruction set summaries in Table 26-2 and
Table 26-3.
REGISTER 5-2: STATUS REGISTER
Note: The C and DC bits operate as the borrow
and digit borrow bits, respectively, in
subtraction.
U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x
— — —NOVZDCC
bit 7 bit 0
bit 7-5 Unimplemented: Read as ‘0’
bit 4 N: Negative bit
This bit is used for signed arithmetic (2’s complement). It indicates whether the result was
negative (ALU MSB = 1).
1 = Result was negative
0 = Result was positive
bit 3 OV: Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the 7-bit
magnitude which causes the sign bit (bit 7) to change state.
1 = Overfl ow occurred for signed arithm etic (in this ar ithmeti c oper ation)
0 = No overflow occurred
bit 2 Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1 DC: Digi t carry/bor row bit
For ADDWF, ADDLW, SUBLW and SUBWF instructions:
1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result
Note: For borrow, the polarity is reversed. A subtraction is executed by adding the two’s
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either bit 4 or bit 3 of the source register.
bit 0 C: Carry/borrow bit
For ADDWF, ADDLW, SUBLW and SUBWF instructions:
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note: For borrow, the polarity is reversed. A subtraction is executed by adding the two’s
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the high or low-order bit of the source register.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC18F2455/2550/4455/4550
DS39632A-page 72 Advance Information 2004 Microchip Technology Inc.
5.4 Data Addressing Modes
While the program memory can be addressed in only
one way – through the program counter – information
in the da ta m emory sp ace can be addr essed in several
ways. For most instructions, the addressing mode is
fixed. Other instructions may use up to three modes,
dependi ng on whic h operands are us ed and whe ther or
not the extended instruction set is enabled.
The addressing modes are:
• Inherent
• Literal
•Direct
•Indirect
An additional addressing mode, Indexed Literal Offset,
is available when the extended instruction set is
enabled (XINST configuration bit = 1). Its operation is
discussed in greater detail in Section 5.6.1 “Indexed
Addressing with Literal Offset”.
5.4.1 INHERENT AND LITERAL
ADDRESSING
Many PIC18 control instructions do not need any
argument at all; they either perform an operation that
globally affects the device or they operate implicitly on
one register. This addressing mode is known as
Inher ent Add res sin g. Exa mp les includ e SLEEP, RESET
and DAW.
Other instructions work in a similar way but require an
additional explicit argument in the opcode. This is
known as Literal Addressing mode because they
require some literal value as an argument. Examples
include ADDLW and MOVLW, which respectively, add or
move a literal value to the W register. Other examples
include CALL and GOTO, which include a 20-bit
program memory address.
5.4.2 DIRECT ADDRESSING
Direct addressing specifies all or part of the source
and/or destination address of the operation within the
opcode itself. The options are specified by the
arguments accompanying the instruction.
In the core PIC18 instruction set, bit-oriented and
byte-oriented instructions use some version of direct
addressing by default. All of these instructions include
some 8-bit literal address as their Least Significant
Byte. This address specifies either a re gister address in
one of the banks of d ata RAM ( Section 5.3.4 “Gener al
Purpose Register File”) or a location in the Access
Bank (Section 5.3.3 “Access Bank”) as the data
source for the instruction.
The Acc es s RAM b it ‘a’ de term in es ho w the a ddre ss i s
interpreted. When ‘a’ is ‘1’, the contents of the BSR
(Section 5.3.2 “Bank Select Register (BSR)”) are
used with the addres s to determ ine the com plete 12-b it
addr ess of t he regis ter. When ‘ a’ is ‘0’, the address is
interpreted as being a register in the Access Bank.
Addressing that uses the Access RAM is sometimes
also known as Direct Forced Addressing mode.
A few instructions, such as MOVFF, include the entire
12-bit address (either source or destination) in their
opcodes. In these cases, the BSR is ignored entirely.
The destin ation of the ope ration’ s result s is determine d
by the destinatio n bit ‘d ’. Wh en ‘d’ is ‘1’, the results are
stor ed ba ck in t he s o ur c e re g is ter, over wr iti n g i ts or i gi -
nal contents. When ‘d’ is ‘0’, the results are stored in
the W register. Instructions without the ‘d’ argument
have a dest ination that is implicit in the inst ruction; their
destination is either the target register being operated
on or the W register.
5.4.3 INDIRECT ADDRESSING
Indirect addressing a llows the use r to access a location
in data memory without giving a fixed address in the
instruction. This is done by using File Select Registers
(FSRs) as poi nters to the location s to be read or written
to. Since the FSRs are themselves located in RAM as
Special File Reg isters, they can a lso b e dire ctly mani p-
ulated under program control. This makes FSRs very
use ful i n i mpl emen ti ng data stru ctu res, suc h a s ta bles
and arrays in data memory.
The registers for indirect addressing are also
implemented with Indirect File Operands (INDFs) that
permit au tomati c mani pulati on of the poi nter val ue wi th
auto-incrementing, auto-decrementing or offsetting
with a not her value . Th is al lo ws f or e ffici ent co de, usin g
loops, such as the example of clearing an entire RAM
bank in Example 5-5.
EXAMPLE 5-5: HOW TO CLEAR RAM
(BANK 1) USING
INDIRECT ADDRESSING
Note: The ex ecutio n of some i nstruct ions in t he
core PIC18 instruction set are changed
when the PIC18 extended instruction
set is enabled. See Section 5.6 “Data
Memory and the Extended Instruction
Set” for more information.
LFSR FSR0, 100h ;
NEXT CLRF POSTINC0 ; Clear INDF
; register then
; inc pointer
BTFSS FSR0H, 1 ; All done with
; Bank1?
BRA NEXT ; NO, clear next
CONTINUE ; YES, continue
2004 Microchip Technology Inc. Advance Information DS39632A-page 73
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5.4.3.1 FSR Regist er s and the
INDF Operand
At the core of indirect addressing are three sets of
registers: FSR0, FSR1 and FSR2. Each represents a
pair of 8-bit registers, FSRnH and FSRnL. The four
upper bit s of the FSRnH register are not used, s o each
FSR pair hol ds a 12 -bit valu e. Thi s re prese nts a va lue
that can address the entire range of the data memory
in a linear fashion. The FSR register pairs, then, serve
as pointers to data memory locations.
Indirect addressing is accomplished with a set of
Indirect File Operands, INDF0 through INDF2. These
can be thought of as “virtual” registers: they are
mapped in the SFR sp ace bu t are not ph ysic ally impl e-
mented. Reading or writing to a parti cular INDF register
actually accesses its corresponding FSR register pair.
A read from INDF1, for example, reads the data at the
address indicated by FSR1H:FSR1L. Instructions that
use the INDF registers as operands actually use the
contents of their corr espon ding FSR as a poin ter to th e
instruction’s target. The INDF operand is just a
convenient way of using the pointer.
Because indir ect addres sing us es a full 1 2-bit a ddress ,
data RAM banking is not necessary. Thus, the current
contents of the BSR and the Access RAM bit have no
effect on determining the target address.
FIGURE 5-7: INDIRECT ADDRESSING
FSR1H:FSR1L
0
7
Data Memory
000h
100h
200h
300h
F00h
E00h
FFFh
Bank 0
Bank 1
Bank 2
Bank 14
Bank 15
Bank 3
through
Bank 13
ADDWF, INDF1, 1
07
Using an instruction with one of the
indirect addressing registers as the
operand....
...uses the 12-bit address stored in
the FSR pair associated with that
register....
...to determine the data memory
location to be used in that operation.
In this case, the FSR1 pair contains
ECCh. This means the contents of
location ECCh will be added to that
of the W register and stored back in
ECCh.
xxxx1110 11001100
Bank 14
PIC18F2455/2550/4455/4550
DS39632A-page 74 Advance Information 2004 Microchip Technology Inc.
5.4.3.2 FSR Regist er s and POST IN C,
POSTDEC, PREINC and PL USW
In additi on to the INDF o perand, each F SR register p air
also has four additional indirect operands. Like INDF,
these are “virtual” registers that cannot be indirectly
read or written to. Accessing these registers actually
accesses the associated FSR register pair, but also
performs a specific action on it stored value. They are:
• POSTDEC: acc es se s the FSR value, then
automatically decrements it by ‘1’ afterwards
• POSTINC: accesses the FSR value, then
automatically increments it by ‘1’ afterwards
• PREINC: inc r ements the FSR valu e by ‘1’, then
uses it in the operation
• PLUSW: adds the signed value of the W register
(range of -127 to 12 8) to that of the FSR and uses
the new value in the operation.
In this context, accessing an INDF register uses the
value in the FSR regi sters without chan ging them. Sim-
ilarly, accessing a PLUSW register gives the FSR value
of fset by t hat in th e W registe r; n either v alu e is ac tu all y
changed in the operation. Accessing the other virtual
registers changes the value of the FSR registers.
Operations on the FSRs with POSTDEC, POSTINC
and PREINC affect the entire register pair; that is, roll-
overs of the FSRn L regi ster fro m FFh to 0 0h ca rry ov er
to the FSRnH register. On the other hand, results of
these operations do not change the value of any flags
in the Status register (e.g., Z, N, OV, etc.).
The PLUSW register can be used to implement a form
of indexed addressing in the data memory space. By
manipulating the value in the W register, users can
reach addresses that are fixed offsets from pointer
addresses. In some applications, this can be used to
implement some powerful program control structure,
such as sof tware stacks, inside of data memo ry.
5.4.3.3 Operations by FSRs on FSRs
Indirect addressing operations that target other FSRs
or virtual registers represent special cases. For exam-
ple, usin g an FSR to point to one of the virtual registers
will not result in successful operations. As a specific
case, assume that FSR0H:FSR0L contains FE7h, the
address of INDF1. Attempts to read the value of the
INDF1, using INDF0 as an operand, will return 00h.
Attempts to write to INDF1, using INDF0 as the
operand, will result in a NOP.
On the other ha nd, using the v irtual regist ers to write to
an FS R pa ir may not occu r as plan ned. I n t hese cases,
the val ue will be written to the FSR p air bu t without any
incrementing or decrementing. Thus, writing to INDF2
or POSTDEC2 will write the same value to the
FSR2H:FSR2L.
Since the FSRs are physical registers mapped in the
SFR space, they can be manipulated through all direct
operations. Users should proceed cautiously when
working on these registers, particularly if their code
uses indirect addressing.
Similarly, operations by indirect addressing are gener-
ally pe rmitted on all other SFRs . Users should exerc ise
the appropriate caution that they do not inadvertently
change settings that might affect the operation of the
device.
2004 Microchip Technology Inc. Advance Information DS39632A-page 75
PIC18F2455/2550/4455/4550
5.5 Program Memory and the
Extended Instruct ion Set
The operation of pro gra m m emory is un affected by the
use of the extended instruction set.
Enabling the extended instruction set adds eight
additional two-word commands to the existing
PIC18 instruction set: ADDFSR, ADDULNK, CALLW,
MOVSF, MOVSS, PUSHL, SUBFSR and SUBULNK. Thes e
instructions are executed as described in
Section 5.2.4 “Two-Word Instructions”.
5.6 Data Memory and the Extended
Instructi on Set
Enabling the PIC18 extended instruction set (XINST
configuration bit = 1) significantly changes certain
aspects of data memory and its addressing.
Specific ally , t he use of the Acce ss Bank for ma ny of the
core PIC18 instructions is different; this is due to the
introduction of a new addressing mode for the data
memory space. This mode also alters the behavior of
indirect addressing using FSR2 and its associated
operands.
What doe s not chan ge is ju st as im po rtant. The size of
the data memory space is unchanged, as well as its
linear addressing. The SFR map remains the same.
Core PIC18 instructions can still operate in both Direct
and Indirect Addressing mode; inherent and literal
instructions do not change at all. Indirect addressing
with FSR0 and FSR1 also remain unchanged.
5.6.1 INDEXED ADDRESSING WITH
LITERAL OFFSET
Enabling the PIC18 extended instruction set changes
the behavior of indirect addressing using the FSR2 reg-
ister pair and its associated file operands. Under the
proper conditions, instructions that use the Access
Bank – that is, most bit-oriented and byte-oriented –
instructions – can invoke a form of indexed addressing
using an offse t spe ci fied in the i nst ruc t io n. Thi s s pec ia l
address ing mod e is k nown as I ndexed A ddressing with
Literal Offset or Indexed Literal Offset mode.
When using the extended instruction set, this
addressing mode requires the following:
• The use of the Access Bank is forced (‘a’ = 0);
and
• The f ile ad dres s argument is le ss th an o r equal to
5Fh.
Under these conditions, the file address of the instruc-
tion is not interpreted as the lower byte of an address
(used with th e BSR in direct ad dress ing), or as an 8-b it
address in the Access Bank. Instead, the value is
interpreted as an offset value to an address pointer,
specified by FSR2. The offset and the contents of
FSR2 are added to obtain the target address of the
operation.
5.6.2 INSTRUCTIONS AFFECTED BY
INDEXED LITERAL OFFSET MODE
Any of the core PIC18 instructions that can use direct
addressing are potentially affected by the Indexed
Literal Offset Addressing mode. This includes all
byte-oriented and bit-oriented instructions, or almost
one-half of the standard PIC18 instruction set. Instruc-
tions that only use Inherent or Literal Addressing
modes are una ffecte d.
Additionally, byte-oriented and bit-oriented instructions
are not affected if they use the Access Bank (Access
RAM bit is ‘1’), or in clude a file add ress of 60h or ab ove.
Instructions meeting these criteria will continue to
execute as befo re. A comp aris on of the dif ferent po ssi-
ble addressing modes when the extended instruction
set is enabled in shown in Figure 5-8.
Those who desire to use byte-oriented or bit-oriented
instructions in the Indexed Literal Offset mode should
note the changes to assembler syntax for this mode.
This is described in more detail in Section 26.2.1
“Extended Instruction Syntax”.
PIC18F2455/2550/4455/4550
DS39632A-page 76 Advance Information 2004 Microchip Technology Inc.
FIGURE 5-8: COMP ARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND
BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED)
EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff)
When a = 0 and f ≥ 60h:
The instruction executes in
Direct Forced mode. ‘f’ is inter-
preted as a location in the
Access RAM between 060h
and 0FFh. This is the s ame as
the SFRs, or l ocations F60 h to
0FFh (Bank 15) of data
memory.
Locations below 60h are not
available in this addressing
mode.
When a = 0 and f ≤ 5Fh:
The instruction executes in
Indexed Literal Offset mode. ‘f’
is interpre ted as an offset to the
address value in FSR2. The
two are added together to
obtain the address of the target
register for the instruction. The
address can be anywhere in
the data memory space.
Note that in this mode, the
correct syntax is now:
ADDWF [k], d
where ‘k’ is the same as ‘f’.
When a = 1 (all val ues of f):
The instruction executes in
Direct mode (also known as
Direct Long mode). ‘f’ is inter-
preted as a location in one of
the 16 banks of the data
memory space. The bank is
design ated by the Bank Sel ect
Register (BSR). The address
can be in any implemented
bank in the data memory
space.
000h
060h
100h
F00h
F60h
FFFh
Valid range
00h
60h
FFh
Data Memory
Access RAM
Bank 0
Bank 1
through
Bank 14
Bank 15
SFRs
000h
080h
100h
F00h
F60h
FFFh Data Memory
Bank 0
Bank 1
through
Bank 14
Bank 15
SFRs
FSR2H FSR2L
ffffffff001001da
ffffffff001001da
000h
080h
100h
F00h
F60h
FFFh Data Memory
Bank 0
Bank 1
through
Bank 14
Bank 15
SFRs
for ‘f’
BSR
00000000
080h
2004 Microchip Technology Inc. Advance Information DS39632A-page 77
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5.6.3 MAPPING THE ACCESS BANK IN
INDEXED LITERAL OFFSET MODE
The use of Indexed Literal Offset Addressing mode
effectively changes how the lower portion of Access
RAM (00h to 5Fh) is mapped. Rather than containing
just the contents of the bottom half of Bank 0, this mode
maps the contents from Bank 0 and a user defined
“window” that can be located anywhere in the data
memory space. The value of FSR2 establishes the
lower boundary of the addresses mapped into the
window, while the upper boundary is defined by FSR2
plus 95 (5Fh). Addresses in the Access RAM above
5Fh are mapped as previously described (see
Section 5.3.3 “Access Bank”). An example of Access
Bank remapping in this addressing mode is shown in
Figure 5-9.
Remapping of the Access Bank applies only to opera-
tions u sing the I ndexed Lite ral Offs et mode. Ope rations
that use the BSR (Access RAM bit is ‘1’) will continue
to use direct addressing as before. Any indirect or
indexed operation that expli citly uses any of the ind irect
file operands (including FSR2) will continue to operate
as standard indirect addressing. Any instruction that
uses the Access Bank but includes a register address
of greater than 05Fh will us e di rect addressi ng a nd the
normal Access Bank map.
5.6.4 BSR IN INDEXED LITERAL OFFSET
MODE
Although the Access Bank is remapped when the
extended instruction set is enabled, the operation of the
BSR remains unchanged. Direct addressing using the
BSR to select the data memory bank operates in the
same manner as previously described.
FIGURE 5-9: REMAPPING THE ACCESS BANK WITH INDEXED LITERAL
OFFSET ADDRESSING
Data Memory
000h
100h
200h
F60h
F00h
FFFh
Bank 1
Bank 15
Bank 2
through
Bank 14
SFRs
ADDWF f, d, a
FSR2H:FSR2L = 120h
Locations in the region
from the FSR2 pointer
(120h) to the pointer plus
05Fh (17Fh) are mapped
to the bottom of the
Access RAM (000h-05Fh).
Special File Registers at
F60h through FFFh are
mapped to 60h through
FFh, as usual.
Bank 0 addresses below
5Fh are not available in
this mode. They can still
be addressed by using the
BSR.
Access Bank
00h
60h
FFh
Bank 0
SFRs
Bank 1 “Window”
Window
Example Situation:
120h
17Fh
5Fh
PIC18F2455/2550/4455/4550
DS39632A-page 78 Advance Information 2004 Microchip Technology Inc.
NOTES:
2004 Microchip Technology Inc. Advance Information DS39632A-page 79
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6.0 FLASH PROGRAM MEMORY
The Flash program memory is readable, writable and
erasable, during normal operation over the entire VDD
range.
A read from program memory is executed on one byte
at a time. A write to program memory is executed on
blocks of 64 bytes at a time. Program memory is
erased in blocks of 64 bytes at a time. A Bulk Erase
operation may not be issued from user code.
Writing or erasing program memory will cease
instruction fetches until the operation is complete. The
program memory cannot be accessed during the write
or erase, therefore, code cannot execute. An internal
programming timer terminates program memory writes
and erases.
A value wri tten to program memory does not need to be
a valid instruction. Executing a program memory
location that forms an invalid instruction results in a
NOP.
6.1 Table Reads and Table Writes
In order to read and write program memory, there are
two operations that allow the processor to move bytes
between the program memory s pace and the d ata RAM:
• Table Read (TBLRD)
• Table Write (TBLWT)
The program memory space is 16 bits wide, while the
data RAM space is 8 bits wide. Table reads and table
writes move data between these two memory spaces
through an 8-bit register (TABLAT).
Table read operations retrieve data from program
memory and places it into the data RAM space.
Figure 6-1 shows the operation of a table read with
program memory and data RAM.
Table w rite oper atio ns sto re d ata fro m the data me mor y
space into holding registers in program memory. The
procedure to write the contents of the holding registers
into program memory is detailed in Section 6.5 “Writin g
to Flash Program Memory”. Figure 6-2 shows the
operation of a table write with program memory and data
RAM.
Table operations work with byte entities. A table block
containing data, rather than program instructions, is not
required to be word aligned. Therefore, a table block can
start and end at any byte address. If a table write is being
used to write executable code into program memory,
program instructions will need to be word aligned.
FIGURE 6-1: TABLE READ OPERATION
Table Pointer(1) Table Latch (8-bit)
Program Memory
TBLPTRH TBLPTRL TABLAT
TBLPTRU
Instruction: TBLRD*
Note 1: Table Pointer register points to a byte in program memory.
Program Memory
(TBLPTR)
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FIGURE 6-2: TABLE WRITE OPERATION
6.2 Control Registers
Several control registers are used in conjunction with
the TBLRD and TBLWT instructions. These include the:
• EECON1 register
• EECON2 register
• TABLAT register
• TBLPTR registers
6.2.1 EECON1 AND EECON2 REGISTERS
The EECON1 register (Register 6-1) is the control
register for memory acce sses. The EECON2 register is
not a physical register; it is used exclusively in the
memory write and erase sequences. Reading
EECON2 will read all ‘0’s.
The EEPGD control bit determi nes if th e access will be
a program or data EEPROM memory access. When
clear, any subsequent operations will operate on the
data EEPROM memory. When set, any subsequent
operations will operate on the program memory.
The CFGS control bit determines if the access will be
to the configuration/calibration registers or to program
memory/data EEPROM memory. When set,
subsequent operations will operate on configuration
registers regardless of EEPGD (see Section 25.0
“Special Features of the CPU”). When clear , memory
selection access is determined by EEPGD.
The FREE bit, when set, will allow a program memory
erase operation. When FREE is set, the erase opera-
tion is initi ated on the n ext WR comm and. Wh en FR EE
is clear, only writes are enabled.
The WREN bit, when set, will allow a write operation.
On powe r-up, the WR EN bit is clear. The WRERR bit i s
set in hardware when the WREN bit is set and cleared
when the internal programming timer expires and the
write operation is complete.
The WR control bit initiates write operations. The bit
cannot be cleared, only set, in software; it is cleared in
hardware at the completion of the write operation.
Table Pointer(1) Table Latch (8-bit)
TBLPTRH TBLPTRL TABLAT
Program Memory
(TBLPTR)
TBLPTRU
Instruction: TBLWT*
Note 1: Table Pointer actually points to one of 64 holding registers, the address of which is determined by
TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in
Section 6.5 “Writing to Flash Program Memory”.
Holding Registers
Program Memory
Note: During normal operation, the WRERR is
read as ‘1’. This can indicate that a write
operation was prematurely terminated by
a Reset, or a write operation was
attempted improperly.
Note: The EEIF interrupt flag bit (PIR2<4>) is set
when the write is complete. It must be
cleared in software.
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REGISTER 6-1: EECON1 REGISTER
R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0
EEPGD CFGS — FREE WRERR WREN WR RD
bit 7 bit 0
bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit
1 = Access Flash program memory
0 = Access data EEPROM memory
bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit
1 = Access configuration registers
0 = Access Flash program or data EEPROM memory
bit 5 Unimplemented: Read as ‘0’
bit 4 FREE: Flash Row Erase Enable bit
1 = Erase the program memory row addressed by TBLPTR on the next WR command (cleared
by completion of erase operation)
0 = Perform write only
bit 3 WRERR: Flash Program/Data EEPROM Error Flag bit
1 = A write operation is prematurely terminated (any Reset during self-timed programming in
normal operation or an improper write attempt)
0 = The write operation completed
Note: When a WRERR occurs, the EEPGD and CFGS bits are not cleared.
This allows tracing of the error condition.
bit 2 WREN: Flash Program/Data EEPROM Write Enable bit
1 = Allows write cycles to Flash program/data EEPROM
0 = Inhibits write cycles to Flash program/data EEPROM
bit 1 WR: Write Control bit
1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle
(The operation is self-timed and the bit is cleared by hardware once write is complete.
The WR bit can only be set (not cleared) in software.)
0 = Write cycle to the EEPROM is complete
bit 0 RD: Read Control bit
1 = Initiates an EEPROM read (Read t akes one cycle. RD is cleared in hardware. The RD bit can
only be set (not cleared) in software. RD bit cannot be set w hen EEPGD = 1 or CFGS = 1.)
0 = Does not initiate an EEPROM read
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
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6.2.2 TABLE LATCH REGISTER (TABLAT)
The Table Latch (TABLAT) is an 8-bit register mapped
into the SFR sp ace. The Table Latch registe r is used to
hold 8-bit data during data transfers between program
memory and data RAM.
6.2.3 TABLE POINTER REGISTER
(TBLPTR)
The Table Pointer (TBLPTR) regis ter ad dre sses a by te
within the program memory . The TBLPTR is comprised
of three SFR regis ters: Ta ble Pointer Upper Byte, Table
Pointer High Byte and Table Pointer Low Byte
(TBLPTRU:TBLPTRH:TBLPTRL). These three regis-
ters join to form a 22-bit wide pointer. The low-order
21 bits allow the device to address up to 2 Mbytes of
progra m memory sp ace. Th e 22nd b it allows acce ss to
the device ID, the user ID and the configuration bits.
The table pointer, TBLPTR, is used by the TBLRD and
TBLWT instructions. These instructions can update the
TBLPTR in one of four ways based on the table opera-
tion. These operations are shown in Table 6-1. These
operations on the TBLPTR only affect the low-order
21 bits.
6.2.4 TABLE POINTER BOUNDARIES
TBLPTR is used in reads, writes and erases of the
Flash program memory.
When a TBLRD is executed, all 22 bits of the TBLPTR
determine which byte is read from program memory
into TABLAT.
When a TBLWT is executed, the six LSbs of the Table
Pointer register (TBLP TR<5:0>) determi ne which of the
64 program memory holding registers is written to.
When the timed write to program memory begins (via
the WR bit), the 16 MSbs of the TBLPTR
(TBLPTR<21:6>) determine which program memory
block of 64 bytes is written to. For more detail, see
Section 6.5 “Writing to Flash Program Memory”.
When an erase of program memory is executed, the
16 MSbs of the Table Pointer register (TBLPTR<21:6>)
point to the 64-byte block that wi ll be erased. The Leas t
Significant bits (TBLPTR<5:0>) are ignored.
Figure 6-3 describes the relevant boundaries of the
TBLPTR based on Flash program memory operations.
TABLE 6-1: TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS
FIGURE 6-3: TABLE POINTER BOUNDARIES BASED ON OPERATION
Example Operation on Table Pointer
TBLRD*
TBLWT* TBLPTR is not modif ied
TBLRD*+
TBLWT*+ TBLPTR is incremented after the read/write
TBLRD*-
TBLWT*- TBLPTR is decremented after the read/write
TBLRD+*
TBLWT+* TBLPTR is increm en ted before the read /write
21 16 15 87 0
TABLE ERASE/WRITE TABLE WRITE
TABLE READ – TBLPTR<21:0>
TBLPTRLTBLPTRH
TBLPTRU
TBLPTR<5:0>TBLPTR<21:6>
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6.3 Reading the Flash Program
Memory
The TBLRD instruction is used to retrieve data from
program memory and places it into data RAM. Table
reads fro m program memory are pe rformed one byte at
a time.
TBLPTR points to a byte address in program space.
Executing TBLRD places the byte pointed to into
TABLAT. In addition, TBLPTR can be modified
automatically for the next table read operation.
The interna l program memory is typically org anized by
words. The Least Significan t bit of th e address selects
between the high and low bytes of the word. Figure 6-4
shows the interface between the internal program
memory and the TABLAT.
FIGURE 6-4: READS FROM FLASH PROGRAM MEMORY
EXAMPLE 6-1: READING A FLASH PROGRAM MEMORY WORD
(Even Byte Address)
Program Memory
(Odd Byte Address)
TBLRD TABLAT
TBLPTR = xxxxx1
FETCH
Instruction Register
(IR) Read Register
TBLPTR = xxxxx0
MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base
MOVWF TBLPTRU ; address of the word
MOVLW CODE_ADDR_HIGH
MOVWF TBLPTRH
MOVLW CODE_ADDR_LOW
MOVWF TBLPTRL
READ_WORD
TBLRD*+ ; read into TABLAT and increment
MOVF TABLAT, W ; get data
MOVWF WORD_EVEN
TBLRD*+ ; read into TABLAT and increment
MOVFW TABLAT, W ; get data
MOVF WORD_ODD
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6.4 Erasing Flash Program Memory
The mi nimum eras e block is 32 words or 64 byte s. Only
through the use of an external programmer, or through
ICSP control, can larger blocks of program memory be
Bulk Erased. Word erase in the Flash array is not
supported.
When initiating an erase sequence from the micro-
controll er itsel f, a block of 64 by tes of program me mory
is erased. The Most Significant 16 bits of the
TBLPTR<21:6> point to the block being erased.
TBLPTR<5:0> are ignored.
The EECON1 regis te r com ma nds the era se operation.
The EEPGD bit must be set to point to the Flash pro-
gram memory. The WREN bit must be set to enable
write op erations. The FREE bit i s set to selec t an erase
operation.
For protec tio n, t he w ri te i ni tiat e s equ enc e f or EEC ON 2
must be used.
A long w rite i s nec essary for erasing th e inte rnal Fl ash.
Instruction execution is halted while in a long write
cycle. The long write will be terminated by the internal
programming timer.
6.4.1 FLASH PROGRAM MEMORY
ERASE SEQUENCE
The sequence of events for erasing a block of internal
program memory location is:
1. Load Table Pointer register with address of row
being erased.
2. Set the EECON1 register for the erase operation:
• set EEPGD bit to point to program memory;
• clear the CFGS bit to access program memory;
• set WREN bit to enable writes;
• set FREE bit to enable the erase.
3. Disable int errup ts.
4. Write 55h to EECON2.
5. Write 0AAh to EECON2.
6. Set the WR bit. This will begin the Row Erase
cycle.
7. The CPU will stall for duration of the erase
(about 2 ms using internal timer).
8. Re-enable interrupts.
EXAMPLE 6-2: ERASING A FLASH PROGRAM MEMORY ROW
MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base
MOVWF TBLPTRU ; address of the memory block
MOVLW CODE_ADDR_HIGH
MOVWF TBLPTRH
MOVLW CODE_ADDR_LOW
MOVWF TBLPTRL
ERASE_ROW
BSF EECON1, EEPGD ; point to Flash program memory
BCF EECON1, CFGS ; access Flash program memory
BSF EECON1, WREN ; enable write to memory
BSF EECON1, FREE ; enable Row Erase operation
BCF INTCON, GIE ; disable interrupts
Required MOVLW 55h
Sequence MOVWF EECON2 ; write 55h
MOVLW 0AAh
MOVWF EECON2 ; write 0AAh
BSF EECON1, WR ; start erase (CPU stall)
BSF INTCON, GIE ; re-enable interrupts
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6.5 Writing to Flash Program Memory
The minimum programming block is 32 words or
64 bytes. Word or byte programming is not supported.
Table writes are used internally to load the holding
registers needed to program the Flash memory. There
are 64 holding registers used by the table writes for
programming.
Since the Table Latch (TABLAT) is only a single byte,
the TBLWT instruction may need to be executed 64
times for each programming operation. All of the table
write operations will essentially be sh ort writes because
only the holding registers are written. At the end of
updating the 64 holding registers, the EECON1 register
must be written to in order to start the programming
operation with a long write.
The long write is necessary for programming the
internal Flash. Ins tructio n execu tion is halted whil e in a
long write cycle. The long write will be terminated by
the internal programming timer.
The EEPROM on-chip timer controls the write time.
The write/erase voltages are generated by an on-chip
charge pump, rated to operate over the voltage range
of the device.
FIGURE 6-5: TABLE WRITES TO FLASH PROGRAM MEMORY
6.5.1 FLASH PROGRAM MEMORY WRITE
SEQUENCE
The sequence of events for programming an internal
program memory location sh ould be:
1. Read 64 bytes into RAM.
2. Update data values in RAM as necessary.
3. Load Table Pointer register with address being
erased.
4. Execute the Row Erase procedure.
5. Load Table Pointer register with address of first
byte being written.
6. Write the 64 by tes in to the hold ing reg isters with
auto-increment.
7. Set the EECON 1 register for the wri te operation:
• set EEPGD bit to point to program memory;
• clear the CFGS bit to access program memory;
• set WREN to enable byte writes.
8. Disable int errup ts.
9. Write 55h to EECON2.
10. Write 0AAh to EECON2.
11. Set the WR bit. This will begin the w rite cy cl e.
12. The CPU wil l st all for d uration o f the w rite (abo ut
2 ms using internal timer).
13. Re-enable interrupts.
14. Verify the memory (table read).
This procedure will require about 18 ms to update one
row of 64 bytes of memory . An example of the required
code is given in Example 6-3.
Note: The default value of the holding registers on
device Resets and after write operations is
FFh. A write of FFh to a holding register
does not modi fy th at byt e. T his mea ns th at
individual bytes of program memory may be
modified, provided that the change does not
attemp t to cha nge an y bit f rom a ‘0’ to a ‘1’.
When modifying individual bytes, it is not
necessary to load all 64 holding registers
before ex ec u t in g a write o pe r at io n.
TBLPTR = xxxx3FTBLPTR = xxxxx1TBLPTR = xxxxx0 TBLP T R = xxxxx2
Program Memory
Holding Register H olding Register Holding Register Holding Register
88 8 8
TABLAT
Write Register
Note: Before setting the WR bit, the Table
Pointer address needs to be within the
intended address range of the 64 bytes in
the holding register.
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EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY
MOVLW D'64 ; number of bytes in erase block
MOVWF COUNTER
MOVLW BUFFER_ADDR_HIGH ; point to buffer
MOVWF FSR0H
MOVLW BUFFER_ADDR_LOW
MOVWF FSR0L
MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base
MOVWF TBLPTRU ; address of the memory block
MOVLW CODE_ADDR_HIGH
MOVWF TBLPTRH
MOVLW CODE_ADDR_LOW
MOVWF TBLPTRL
READ_BLOCK
TBLRD*+ ; read into TABLAT, and inc
MOVF TABLAT, W ; get data
MOVWF POSTINC0 ; store data
DECFSZ COUNTER ; done?
BRA READ_BLOCK ; repeat
MODIFY_WORD
MOVLW DATA_ADDR_HIGH ; point to buffer
MOVWF FSR0H
MOVLW DATA_ADDR_LOW
MOVWF FSR0L
MOVLW NEW_DATA_LOW ; update buffer word
MOVWF POSTINC0
MOVLW NEW_DATA_HIGH
MOVWF INDF0
ERASE_BLOCK
MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base
MOVWF TBLPTRU ; address of the memory block
MOVLW CODE_ADDR_HIGH
MOVWF TBLPTRH
MOVLW CODE_ADDR_LOW
MOVWF TBLPTRL
BSF EECON1, EEPGD ; point to Flash program memory
BCF EECON1, CFGS ; access Flash program memory
BSF EECON1, WREN ; enable write to memory
BSF EECON1, FREE ; enable Row Erase operation
BCF INTCON, GIE ; disable interrupts
MOVLW 55h
Required MOVWF EECON2 ; write 55h
Sequence MOVLW 0AAh
MOVWF EECON2 ; write 0AAh
BSF EECON1, WR ; start erase (CPU stall)
BSF INTCON, GIE ; re-enable interrupts
TBLRD*- ; dummy read decrement
MOVLW BUFFER_ADDR_HIGH ; point to buffer
MOVWF FSR0H
MOVLW BUFFER_ADDR_LOW
MOVWF FSR0L
WRITE_BUFFER_BACK
MOVLW D’64 ; number of bytes in holding register
MOVWF COUNTER
WRITE_BYTE_TO_HREGS
MOVFW POSTINC0, W ; get low byte of buffer data
MOVWF TABLAT ; present data to table latch
TBLWT+* ; write data, perform a short write
; to internal TBLWT holding register.
DECFSZ COUNTER ; loop until buffers are full
BRA WRITE_WORD_TO_HREGS
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EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED)
6.5.2 WRITE VERIFY
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
6.5.3 UNEXPECTED TERMINATION OF
WRITE OPER ATION
If a wri te is term in ate d by an unpl anned ev en t, s uch a s
loss of power or an unexpected Reset, the memory
locatio n jus t progra mmed shou ld be verifi ed and repr o-
gramme d if needed. If t he write operatio n is interrupte d
by a MCLR Reset or a WDT Time-out Reset during
normal operation, the user can check the WRERR bit
and rewrite the location(s) as needed.
6.5.4 PROTECTION AGAINST SPURIOUS
WRITES
To protect against spurious writes to Flash program
memory, the write initiate sequence must also be
followed. See Sect io n 2 5. 0 “Sp eci al F eatu res of the
CPU” for more detail.
6.6 Flash Program Operation Duri ng
Code Protection
See Section 25.5 “Program Verification and Code
Protection” for details on code protection of Flash
program memory.
TABLE 6-2: REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
PROGRAM_MEMORY
BSF EECON1, EEPGD ; point to Flash program memory
BCF EECON1, CFGS ; access Flash program memory
BSF EECON1, WREN ; enable write to memory
BCF INTCON, GIE ; disable interrupts
MOVLW 55h
Required MOVWF EECON2 ; write 55h
Sequence MOVLW 0AAh
MOVWF EECON2 ; write 0AAh
BSF EECON1, WR ; start program (CPU stall)
BSF INTCON, GIE ; re-enable interrupts
BCF EECON1, WREN ; disable write to memory
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset
Values
on page
TBLPTRU —— bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) 51
TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 51
TBLPTRL Program Memory Table Pointer High Byte (TBLPTR<7:0>) 51
TABLAT Program Memory Table Latch 51
INTCON GIE/GIEH PEIE/GIEL TMR0IE INTE RBIE TMR0IF INTF RBIF 51
EECON2 EEPROM Control Register 2 (not a physical register) 53
EECON1 EEPGD CFGS — FREE WRERR WREN WR RD 53
IPR2 OSCFIP CMIP USBIP EEIP BCLIP LVDIP TMR3IP CCP2IP 54
PIR2 OSCFIF CMIF USBIF EEIF BCLIF LVDIF TMR3IF CCP2IF 54
PIE2 OSCFIE CMIE USBIE EEIE BCLIE LVDIE TMR3IE CCP2IE 54
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.
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NOTES:
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7.0 DATA EEPROM MEMORY
The data EEPROM is a nonvolatile memory array,
separate from the data RAM and p rogram memory , that
is used for long-term storage of program data. It is not
directly mapped in either the register file or program
memory space, but is indirectly addressed through the
Special Function Registers (SFRs). The EEPROM is
readable and writ able durin g normal ope ration over the
entire VDD range.
Four SFRs are used to read and write to the data
EEPROM as well as the program memory. They are:
• EECON1
• EECON2
• EEDATA
• EEADR
The data EEPROM allows byte read and write. When
interfacing to the data memory block, EEDATA holds
the 8-bit data for read/write and the EEADR register
holds the address of the EEPROM location being
accessed.
The EEPROM data memory is rated for high erase/write
cycle endurance. A byte write automatically erases the
location and writes the new data (erase-before-write).
The write time is controlled by an on-chip timer; it will
vary with voltage and temperature as well as from chip
to chip. Please refer to parameter D122 (Table 28-1 in
Section 28.0 “Electrical Characteristics”) for exact
limits.
7.1 EECON1 and EECON2 Registers
Access to the data EEPROM is controlled by two
register s: EECON1 an d EECON2. Thes e are the same
registers which control access to the program memory
and are used in a similar manner for the data
EEPROM.
The EECON1 register (Register 7-1) is the control
register for data and program memory access. Control
bit, EEPGD, determines if the access will be to program
or data EEPROM memory. When clear, operations will
access the data EEPROM memory . When set, program
memor y is accessed.
Control bit, CFGS, determines if the access will be to
the configuration registers or to program memory/data
EEPROM memory. When set, subsequent operations
access configuration registers. When CFGS is clear,
the EEPGD bit selects either program Flash or data
EEPROM memory.
The WREN bit, when set, will allow a write operation.
On powe r-up, the WR EN bit is clear. The WR ERR bit is
set in hardware when the WREN bit is set and cleared
when the internal programming timer expires and the
write operation is complete.
The WR control bit initiates write operations. The bit
cannot be cleared, only set, in software; it is cleared in
hardware at the completion of the write operation.
Control bits, RD and WR, start read and erase/write
operat ions, respec tively . These bi ts are set by fi rmware
and cleared by hardware at the completion of the
operation.
The RD bit cannot be set when accessing program
memory (EEPGD = 1). Program memory is read using
table read instructions. See Section 6.1 “Table Reads
and Table Writes” regarding table reads.
The EECON2 register is not a physical register. It is
used exclusively in the memory write and erase
sequences. Reading EECON2 will read all ‘0’s.
Note: During normal operation, the WRERR is
read as ‘1’. This can indicate that a write
operation was prematurely terminated by
a Reset, or a write operation was
attempted improperly.
Note: The EEIF interrupt flag bit (PIR2<4>) is set
when the write is complete. It must be
cleared in software.
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REGISTER 7-1: EECON1 REGISTER
R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0
EEPGD CFGS — FREE WRERR WREN WR RD
bit 7 bit 0
bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit
1 = Access Flash program memory
0 = Access data EEPROM memory
bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit
1 = Access configuration registers
0 = Access Flash program or data EEPROM memory
bit 5 Unimplemented: Read as ‘0’
bit 4 FREE: Flash Row Erase Enable bit
1 = Erase the program memory row addressed by TBLPTR on the next WR command (cleared
by completion of erase operation)
0 = Perform write only
bit 3 WRERR: Flash Program/Data EEPROM Error Flag bit
1 = A write operation is prematurely terminated (any Reset during self-timed programming in
normal operation, or an improper write attempt)
0 = The write operation completed
Note: When a WRERR occurs, the EEPGD and CFGS bits are not cleared.
This allows tracing of the error condition.
bit 2 WREN: Flash Program/Data EEPROM Write Enable bit
1 = Allows write cycles to Flash program/data EEPROM
0 = Inhibits write cycles to Flash program/data EEPROM
bit 1 WR: Write Control bit
1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle
(The operation is self-timed and the bit is cleared by hardware once write is complete.
The WR bit can only be set (not cleared) in software.)
0 = Write cycle to the EEPROM is complete
bit 0 RD: Read Control bit
1 = Initiates an EEPROM read
(Read t akes one cycle. RD is cleared in hardw are. The RD bit can only be set (not cleared)
in software. RD bit cannot be set when EEPGD = 1 or CFGS = 1.)
0 = Does not initiate an EEPROM read
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
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7.2 Reading the Data EEPROM
Memory
To read a data memory loca tion, the user must write the
address to the EEADR register, clear the EEPGD
control bit (EECON1<7>) and then set control bit, RD
(EECON1<0>). The data is available on the very next
instruction cycle; therefore, the EEDATA register can
be read by the next instruction. EEDATA will hold this
value u ntil another re ad operation, or until it is w ritten to
by the user (during a write operation).
The basic process is shown in Example 7-1.
7.3 Writing to the Data EEPROM
Memory
To write an EEPROM data location, the address must
first be writ ten to the EEAD R r egiste r and the da ta writ-
ten to the EEDATA register. The sequence in
Example 7-2 must be followed to initiate the write cycle.
The write will not begin if this sequence is not exactly
followed (write 55h to EECON2, write 0AAh to
EECON2, then set WR bit) for each byte. It is strongly
recommended that interrupts be disabled during this
code segment.
Additionally, the WREN bit in EECON1 must be set to
enable writes. This mechanism prevents accidental
writes to data EEPROM due to unexpected code exe-
cution (i.e., runaway programs). The WREN bit should
be kept clear at all times, except when updating the
EEPROM. The WREN bit is not cleared by hardware.
After a write sequence has been initiated, EECON1,
EEADR and EEDATA cannot be modified. The WR bit
will be inhibited from being set unless the WREN bit is
set. The WREN bit must be set on a previous instruc-
tion. Both WR a nd WREN c an not be se t with th e s am e
instruction.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EEPROM Interrupt Flag bit
(EEIF) is s et. The user may e ither e nable this interrup t,
or poll this bit. EEIF must be cleared by software.
7.4 Write Ve rify
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
EXAMPLE 7-1: DATA EEPROM READ
EXAMPLE 7-2: DATA EEPROM WRITE
MOVLW DATA_EE_ADDR ;
MOVWF EEADR ; Lower bits of Data Memory Address to read
BCF EECON1, EEPGD ; Point to DATA memory
BCF EECON1, CFGS ; Access EEPROM
BSF EECON1, RD ; EEPROM Read
MOVF EEDATA, W ; W = EEDATA
MOVLW DATA_EE_ADDR ;
MOVWF EEADR ; Lower bits of Data Memory Address to write
MOVLW DATA_EE_DATA ;
MOVWF EEDATA ; Data Memory Value to write
BCF EECON1, EPGD ; Point to DATA memory
BCF EECON1, CFGS ; Access EEPROM
BSF EECON1, WREN ; Enable writes
BCF INTCON, GIE ; Disable Interrupts
MOVLW 55h ;
Required MOVWF EECON2 ; Write 55h
Sequence MOVLW 0AAh ;
MOVWF EECON2 ; Write 0AAh
BSF EECON1, WR ; Set WR bit to begin write
BSF INTCON, GIE ; Enable Interrupts
; User code execution
BCF EECON1, WREN ; Disable writes on write complete (EEIF set)
PIC18F2455/2550/4455/4550
DS39632A-page 92 Advance Information 2004 Microchip Technology Inc.
7.5 Operation During Code-Protect
Data EEPROM memory has it s own code-protect bits in
configuration words. External read and write
operations are disabled if code protection is enabled.
The mic rocontroll er its elf can bo th read and write to the
internal data EEPROM, regardless of the state of the
code-protect configuration bit. Refer to Section 25.0
“Special Features of the CPU” for additional
information.
7.6 Protection Against Spurious Write
There are conditions when the device may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been implemented. On power-up, the WREN bit is
cleared. In addition, writes to the EEPROM are bloc ked
during the Power-up Timer period (TPWRT,
parameter 33).
The wri te in iti ate sequence and the WREN bi t tog eth er
help prevent an accidental write during brown-out,
power glitch or software malfunction.
7.7 Using the Data EEPROM
The dat a EEPROM is a hi gh en dura nc e, byt e a ddr ess-
able array that has been optimized for the storage of
frequently changing information (e.g., program
variables or other data that are updated often).
Frequently changing values will typically be updated
more often than specification D124 or D124A. If this is
not t he ca se, an arra y re fres h mus t be perf orm ed. For
this reason, variables that change infrequently (such as
constants, IDs, calibration, etc.) should be stored in
Flash program memory.
A simple data EEPROM refresh routine is shown in
Example 7-3.
EXAMPLE 7-3: DATA E EPROM REFRESH ROUTINE
Note: If data EEPROM is only used to store
const a nts an d/or data that change s rarel y,
an array refresh is likely not required. See
spec ificati on D124 or D124A.
CLRF EEADR ; Start at address 0
BCF EECON1, CFGS ; Set for memory
BCF EECON1, EEPGD ; Set for Data EEPROM
BCF INTCON, GIE ; Disable interrupts
BSF EECON1, WREN ; Enable writes
Loop ; Loop to refresh array
BSF EECON1, RD ; Read current address
MOVLW 55h ;
Required MOVWF EECON2 ; Write 55h
Sequence MOVLW 0AAh ;
MOVWF EECON2 ; Write 0AAh
BSF EECON1, WR ; Set WR bit to begin write
BTFSC EECON1, WR ; Wait for write to complete
BRA $-2
INCFSZ EEADR, F ; Increment address
BRA LOOP ; Not zero, do it again
BCF EECON1, WREN ; Disable writes
BSF INTCON, GIE ; Enable interrupts
2004 Microchip Technology Inc. Advance Information DS39632A-page 93
PIC18F2455/2550/4455/4550
TABLE 7-1: REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INTE RBIE TMR0IF INTF RBIF 51
EEADR EEPROM Address Register 53
EEDATA EEPROM Data Register 53
EECON2 EEPROM Control Register 2 (not a physical register) 53
EECON1 EEPGD CFGS — FREE WRERR WREN WR RD 53
IPR2 OSCFIP CMIP USBIP EEIP BCLIP LVDIP TMR3IP CCP2IP 54
PIR2 OSCFIF CMIF USBIF EEIF BCLIF LVDIF TMR3IF CCP2IF 54
PIE2 OSCFIE CMIE USBIE EEIE BCLIE LVDIE TMR3IE CCP2IE 54
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.
PIC18F2455/2550/4455/4550
DS39632A-page 94 Advance Information 2004 Microchip Technology Inc.
NOTES:
2004 Microchip Technology Inc. Advance Information DS39632A-page 95
PIC18F2455/2550/4455/4550
8.0 8 x 8 HARD WARE MULTIPLIER
8.1 Introduction
All PIC18 devices include an 8 x 8 hardware multiplier
as part of the ALU. The multiplier performs an unsigned
operation and yields a 16-bit result that is stored in the
product register pair, PRODH:PRODL. The multiplier’s
operation does not affect any flags in the Status
register.
Making multiplication a hardware operation allows it to
be com pl eted i n a sing le ins tru cti on cy cl e. This has the
advantages of higher computational throughput and
reduced code size for multiplication algorithms and
allows the PIC18 devices to be used in many applica-
tions previously reserved for digital signal processors.
A comparison of various hardware and software
multiply operations, along with the savings in memory
and execution time, is shown in Table 8-1.
8.2 Operation
Example 8-1 shows the instruction sequence for an
8 x 8 unsigned multiplication. Only one instruction is
required when one of the arguments is already loaded
in the WREG register.
Exampl e 8-2 shows the sequence t o do an 8 x 8 signed
multiplication. To account for the sign bits of the
argumen ts, e ach argu ment’ s Most Si gnificant bit (MSb)
is tested and the appropriate subtractions are done.
EXAMPLE 8- 1: 8 x 8 UNSIGNED
MULTIP L Y ROU TI NE
EXAMPLE 8-2: 8 x 8 SIGNED MULTIPLY
ROUTINE
TABLE 8-1: PERFORMANCE COMPARISON FOR VARIOUS MULTIPLY OPERATIONS
MOVF ARG1, W ;
MULWF ARG2 ; ARG1 * ARG2 ->
; PRODH:PRODL
MOVF ARG1, W
MULWF ARG2 ; ARG1 * ARG2 ->
; PRODH:PRODL
BTFSC ARG2, SB ; Test Sign Bit
SUBWF PRODH, F ; PRODH = PRODH
; - ARG1
MOVF ARG2, W
BTFSC ARG1, SB ; Test Sign Bit
SUBWF PRODH, F ; PRODH = PRODH
; - ARG2
Routine Multiply Method Program
Memory
(Words)
Cycles
(Max)
Time
@ 40 MHz @ 10 MHz @ 4 MHz
8 x 8 unsigned Without hardware multiply 13 69 6.9 µs27.6 µs69 µs
Hardware multiply 1 1 100 ns 400 ns 1 µs
8 x 8 signed Without hardware multiply 33 91 9.1 µs36.4 µs91 µs
Hardware multiply 6 6 600 ns 2.4 µs6 µs
16 x 16 unsigned Without hardware multiply 21 242 24.2 µs96.8 µs 242 µs
Hardware multiply 28 28 2.8 µs 11.2 µs28 µs
16 x 16 signed Without hardware multiply 52 254 25.4 µs 102.6 µs 254 µs
Hardware multiply 35 40 4.0 µs16.0 µs40 µs
PIC18F2455/2550/4455/4550
DS39632A-page 96 Advance Information 2004 Microchip Technology Inc.
Example 8-3 shows the sequence to do a 16 x 16
unsigned multiplication. Equation 8-1 shows the
algorith m that is us ed. The 32-b it result is st ored in fo ur
registers (RES3:RES0).
EQUATION 8-1: 16 x 16 UNSIGNED
MULTIPLICATION
ALGORITHM
EXAMPLE 8- 3: 16 x 16 UNSIGNED
MULTIPLY ROUTINE
Example 8-4 shows the sequence to do a 16 x 16
signed multiply. Equation 8-2 shows the algorithm
used. The 32-bit result is stored in four registers
(RES3:RES0). To account for the sign bits of the
arguments, the MSb for each argument pair is tested
and the appropriate subtractions are done.
EQUATION 8-2: 16 x 16 SIGNED
MULTIPLICATION
ALGORITHM
EXAMPLE 8-4: 16 x 16 SIGNED
MU LTIPLY ROUTINE
RES3:RES0 = ARG1H:ARG1L • ARG2H:ARG2L
= (ARG1H • ARG2H • 216) +
(ARG1H • ARG2L • 28) +
(ARG1L • ARG2H • 28) +
(ARG1L • ARG2L)
MOVF ARG1L, W
MULWF ARG2L ; ARG1L * ARG2L->
; PRODH:PRODL
MOVFF PRODH, RES1 ;
MOVFF PRODL, RES0 ;
;
MOVF ARG1H, W
MULWF ARG2H ; ARG1H * ARG2H->
; PRODH:PRODL
MOVFF PRODH, RES3 ;
MOVFF PRODL, RES2 ;
;
MOVF ARG1L, W
MULWF ARG2H ; ARG1L * ARG2H->
; PRODH:PRODL
MOVF PRODL, W ;
ADDWF RES1, F ; Add cross
MOVF PRODH, W ; products
ADDWFC RES2, F ;
CLRF WREG ;
ADDWFC RES3, F ;
;
MOVF ARG1H, W ;
MULWF ARG2L ; ARG1H * ARG2L->
; PRODH:PRODL
MOVF PRODL, W ;
ADDWF RES1, F ; Add cross
MOVF PRODH, W ; products
ADDWFC RES2, F ;
CLRF WREG ;
ADDWFC RES3, F ;
RES3:RES0 = ARG1H:ARG1L • ARG2H:ARG2L
= (ARG 1H • ARG 2H • 216) +
(ARG1H • ARG2L • 28) +
(ARG1L • ARG2H • 28) +
(ARG1L • ARG2L) +
(-1 • ARG2H<7> • ARG1H:ARG1L • 216) +
(-1 • ARG1H<7> • ARG2H:ARG2L • 216)
MOVF ARG1L, W
MULWF ARG2L ; ARG1L * ARG2L ->
; PRODH:PRODL
MOVFF PRODH, RES1 ;
MOVFF PRODL, RES0 ;
;
MOVF ARG1H, W
MULWF ARG2H ; ARG1H * ARG2H ->
; PRODH:PRODL
MOVFF PRODH, RES3 ;
MOVFF PRODL, RES2 ;
;
MOVF ARG1L,W
MULWF ARG2H ; ARG1L * ARG2H ->
; PRODH:PRODL
MOVF PRODL, W ;
ADDWF RES1, F ; Add cross
MOVF PRODH, W ; products
ADDWFC RES2, F ;
CLRF WREG ;
ADDWFC RES3, F ;
;
MOVF ARG1H, W ;
MULWF ARG2L ; ARG1H * ARG2L ->
; PRODH:PRODL
MOVF PRODL, W ;
ADDWF RES1, F ; Add cross
MOVF PRODH, W ; products
ADDWFC RES2, F ;
CLRF WREG ;
ADDWFC RES3, F ;
;
BTFSS ARG2H, 7 ; ARG2H:ARG2L neg?
BRA SIGN_ARG1 ; no, check ARG1
MOVF ARG1L, W ;
SUBWF RES2 ;
MOVF ARG1H, W ;
SUBWFB RES3
;
SIGN_ARG1
BTFSS ARG1H, 7 ; ARG1H:ARG1L neg?
BRA CONT_CODE ; no, done
MOVF ARG2L, W ;
SUBWF RES2 ;
MOVF ARG2H, W ;
SUBWFB RES3
;
CONT_CODE
:
2004 Microchip Technology Inc. Advance Information DS39632A-page 97
PIC18F2455/2550/4455/4550
9.0 INTERRUPTS
The PIC18F2455/2550/4455/4550 devices have multi-
ple interrupt sources and an interrupt priority feature
that all ow s ea ch in terru pt source to be a ssig ned a hig h
priority level or a low priority level. The high priority
interrupt vector is at 000008h and the low priority
interrupt vector is at 000018h. High priority interrupt
events will interrupt any low priority interrupts that may
be in progress .
There are ten registers which are used to control
interrupt operation. These registers are:
• RCON
•INTCON
• INTCON2
• INTCON3
• PIR1, PIR2
• PIE1, PIE2
• IPR1, IPR2
It is recommended that the Microchip header files
suppli ed with MP LAB® IDE be used fo r the symb olic bit
names in these registers. This allows the assembler/
compil er to automa tical ly ta ke care of the pla ceme nt of
these bits within the specified register.
Each interrupt source has three bits to control its
operation. The functions of these bits are:
• Flag bit to indicate that an interrupt event
occurred
• Enable bit that allows program execution to
branch to the interrupt vector address when the
flag bit is set
• Priority bit to select high priority or low priority
The interrupt priority feature is enabled by setting the
IPEN bit (RCON<7>). When interrupt priority is
enabled, there are two bits which enable interrupts
globall y. Setting the G IEH bit (INTCON<7>) ena bles all
interrupts that have the priority bit set (high priority).
Setting the GIEL bit (INTCON<6>) enables all
inter rupts that have the pr iority bit cleared ( low prio rity).
When the interrupt flag, enable bit and appropriate
global interrupt enable bit are set, the interrupt will
vector immediately to address 000008h or 000018h,
depending on the priority bit setting. Individual inter-
rupts can be disabled through their corresponding
enable bits.
When the IPEN bit is cleared (default state), the
interrupt priority feature is disabled and interrupts are
compatible with PICmicro® mid-range devices. In
Compatibility mode, the interrupt priority bits for each
source have no effect. INTCON<6> is the PEIE bit,
which enables/dis ables all pe ripheral interru pt sources.
INTCON<7> is the GIE bit, which enables/disables all
interrupt sources. All interrupts branch to address
000008h in Compatibility mode.
When an interrupt is responded to, the global interrupt
enable bit is cleared to disable further interrupts. If the
IPEN bit is clear ed, this is the GIE bit. If interrupt priority
levels are used, this will be either the GIEH or GIEL bit.
High priority interrupt sources can interrupt a low
priority interrupt. Low priority interrupts are not
processed while high priority interrupts are in progress.
The return address is pushed onto the stack and the
PC is loaded with the interrupt vector address
(000008h or 000018h). Once in the Interrupt Service
Routine, the source(s) of the interrupt can be deter-
mined by polling the interrupt flag bits. The interrupt
flag bit s must be cleared in software be fore re-enab ling
interrupts to avoid recursive interrupts.
The “return from interrupt” instruction, RETFIE, exits
the interrup t routine and set s the GIE bit (GIEH or GI EL
if priority levels are used), which re-enables interrupts.
For external interrupt events, such as the INT pins or
the POR TB input chang e interrupt, the i nterrupt latenc y
will be three to four instruction cycles. The exact
latency is the same for one or two-cycle instructions.
Individual interrupt flag bits are set, regardless of the
status of their corresponding enable bit or the GIE bit.
9.1 USB Interrupts
Unlike o ther p eripher als , the USB modu le is cap abl e of
generati ng a wid e range of interrupt s for m any types of
event s. The se in cl ude se veral t ypes of norm al com mu-
nication and status events and several module level
error events.
To handle these events, the USB module is equipped
with its own interrupt logic. The logic functions in a
manner similar to the m icrocontroller level interrupt fun-
nel, with each interrupt source havin g separate fla g and
enable bits. All events are funneled to a single device
level interrupt, USBIF (PIR2<5>). Unlike the device
level i nterrupt logic , the in divid ual USB i nterrupt events
cannot be individually assigned their own priority. This
is determined at the device level interrupt funnel for all
USB events by the USBIP bit.
For additional details on USB interrupt logic, refer to
Section 17.5 “USB Interrupts ”.
Note: Do not use the MOVFF instruction to modify
any of the interrupt control registers while
any interrupt is enabled. Doing so may
cause erratic microcontroller behavior.
PIC18F2455/2550/4455/4550
DS39632A-page 98 Advance Information 2004 Microchip Technology Inc.
FIGURE 9-1: INTERRUPT LOGIC
TMR0IE
GIEH/GIE
GIEL/PEIE
Wake-up if in Sleep Mode
Interrupt to CPU
Vector to Location
0008h
INT2IF
INT2IE
INT2IP
INT1IF
INT1IE
INT1IP
TMR0IF
TMR0IE
TMR0IP
RBIF
RBIE
RBIP
IPEN
TMR0IF
TMR0IP
INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
RBIF
RBIE
RBIP
INT0IF
INT0IE
GIEL/PEIE
Interrupt to CPU
Vector to Location
IPEN
IPE
0018h
Peripheral Interrupt Flag bit
Peripheral Interrupt Enable bit
Peripheral Inter rupt Priority bit
Peripheral Interrupt Flag bit
Peripheral Interrupt Enable bit
Peripheral Interrupt Priority bit
TMR1IF
TMR1IE
TMR1IP
USBIF
USBIE
USBIP
Additiona l Peripheral Interrup t s
TMR1IF
TMR1IE
TMR1IP
High Priority Interrupt Generation
Low Priority Interrupt Generation
USBIF
USBIE
USBIP
Additional Peripheral Interrupts
GIE/GEIH
From USB
Interrupt Logic
From USB
Interrupt Logic
2004 Microchip Technology Inc. Advance Information DS39632A-page 99
PIC18F2455/2550/4455/4550
9.2 INTCON Registers
The INTCON registers are readable and writable
registers, which contain various enable, priority and
flag bits.
REGISTER 9-1: INTCON REGISTER
Note: Interru pt flag bit s ar e set when an inter rupt
conditi on occurs, regardle ss of the st ate of
its corresponding enable bit or the global
interrupt enable bit. User software should
ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt.
This feature allows for software polling.
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
bit 7 bit 0
bit 7 GIE/GIEH: Globa l Interrupt Enable bit
When IPEN = 0:
1 = Enables all unma sk ed interrupt s
0 = Disables all interrupts
When IPEN = 1:
1 = Enables all high prio rity interru pt s
0 = Disables all high priority interrupts
bit 6 PEIE/GIEL: Peripheral Interrupt Enable bit
When IPEN = 0:
1 = Enables all unma sk ed peri pheral interru pt s
0 = Disables all peripheral interrupts
When IPEN = 1:
1 = Enables all low priority peripheral interrupts
0 = Disables all low priority peripheral interrupts
bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 overflow interrupt
0 = Disables the TMR0 overflow interrupt
bit 4 INT0IE: INT0 External Interrupt Enable bit
1 = Enables the INT0 externa l inte rrupt
0 = Disables the INT0 external interrupt
bit 3 RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overf lowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1 INT0IF: INT0 External Interrupt Flag bit
1 = The INT0 external interrupt occurred (must be cleared in software)
0 = The INT0 external interrupt did not occur
bit 0 RBIF: RB Port Change Interrupt Flag bit
1 = At least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state
Note: A mismatch condition will continue to set this bit. Reading PORTB will end the
mismatch condition and allow the bit to be cleared.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC18F2455/2550/4455/4550
DS39632A-page 100 Advance Information 2004 Microchip Technology Inc.
REGISTER 9-2: INTCON2 REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 U-0 R/W-1 U-0 R/W-1
RBPU INTEDG0 INTEDG1 INTEDG2 —TMR0IP—RBIP
bit 7 bit 0
bit 7 RBPU: PORTB Pull-up Enable bit
1 = All PORTB p ull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6 INTEDG0: External Interrupt 0 Edge Sele ct bit
1 = Interrupt on rising edge
0 = Interrupt on fall in g edge
bit 5 INTEDG1: External Interrupt 1 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on fall in g edge
bit 4 INTEDG2: External Interrupt 2 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on fall in g edge
bit 3 Unimplemented: Read as ‘0’
bit 2 TMR0IP: TMR0 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1 Unimplemented: Read as ‘0’
bit 0 RBIP: RB Port Change Interrupt Priority bit
1 = High priority
0 = Low priority
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note: Interrupt flag bit s are s et whe n an i nterrupt conditi on oc c urs, rega rdless of the st a t e
of its corresponding enable bit or the global interrupt enable bit. User software
should ensure the appropriate interrupt flag bits are clear prior to enabling an
interrupt. This feature allows for software polling.
2004 Microchip Technology Inc. Advance Information DS39632A-page 101
PIC18F2455/2550/4455/4550
REGISTER 9-3: INTCON3 REGISTER
R/W-1 R/W-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0
INT2IP INT1IP —INT2IEINT1IE— INT2IF INT1IF
bit 7 bit 0
bit 7 INT2IP: INT2 External Interrupt Priority bit
1 = High priority
0 = Low priority
bit 6 INT1IP: INT1 External Interrupt Priority bit
1 = High priority
0 = Low priority
bit 5 Unimplemented: Read as ‘0’
bit 4 INT2IE: INT2 External Interrupt Enable bit
1 = Enables the INT2 external interrupt
0 = Disables the INT2 external interrupt
bit 3 INT1IE: INT1 External Interrupt Enable bit
1 = Enables the INT1 external interrupt
0 = Disables the INT1 external interrupt
bit 2 Unimplemented: Read as ‘0’
bit 1 INT2IF: INT2 External Interrupt Flag bit
1 = The INT2 external interrupt occurred (must be cleared in software)
0 = The INT2 external interrupt did not occur
bit 0 INT1IF: INT1 External Interrupt Flag bit
1 = The INT1 external interrupt occurred (must be cleared in software)
0 = The INT1 external interrupt did not occur
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note: Interrupt flag bit s are s et whe n an in terrupt cond iti on oc c urs, rega rdle ss of the st a te
of its corresponding enable bit or the global interrupt enable bit. User software
should ensure the appropriate interrupt flag bits are clear prior to enabling an
interrupt. This feature allows for software polling.
PIC18F2455/2550/4455/4550
DS39632A-page 102 Advance Information 2004 Microchip Technology Inc.
9.3 PIR Registers
The PIR regi sters c onta in the ind ividual fl ag bit s for the
peripheral interrupts. Due to the number of peripheral
interrupt sources, there are two Peripheral Interrupt
Request (Flag) registers (PIR1 and PIR2).
REGISTER 9-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1
Note 1: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Interrupt Enable bit, GIE (INTCON<7>).
2: User software should ensure the approp ri-
ate interrupt flag bits are cleared prior to
enabling an interrupt and after servicing
that interrupt.
R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0
SPPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF
bit 7 bit 0
bit 7 SPPIF: Streaming Parallel Port Read/Write Interrupt Flag bit(1)
1 = A read or a write operation has taken place (must be cleared in software)
0 = No read or write has occurred
Note 1: This bit is reserved on 28-pin devices; always maintain this bit clear.
bit 6 ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed (must be cleared in software)
0 = The A/D conversion is not complete
bit 5 RCIF: EUSART Receive Interrupt Flag bit
1 = The EUSART receive buffer, RCREG, is full (cleared when RCREG is read)
0 = The EUSART receive buffer is empty
bit 4 TXIF: EUSART Transmit Interrupt Flag bit
1 = The EUSART transmit buffer, TXREG, is empty (cleared when TXREG is written)
0 = The EUSART transmit buffer is full
bit 3 SSPIF: Master Synchronous Serial Port Interrupt Flag bit
1 = The transmission/reception is complete (must be cleared in software)
0 = Waiting to transmit/receive
bit 2 CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode .
bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 mat ch occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = MR1 register did not overflow
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
2004 Microchip Technology Inc. Advance Information DS39632A-page 103
PIC18F2455/2550/4455/4550
REGISTER 9-5: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
OSCFIF CMIF USBIF EEIF BCLIF LVDIF TMR3IF CCP2IF
bit 7 bit 0
bit 7 OSCFIF: Oscillator Fail Interrupt Flag bit
1 = System oscil lator f ailed, cl ock i nput ha s cha nged t o INT OSC (must be cle ared i n softwa re)
0 = System clock operating
bit 6 CMIF: Comparator Interrupt Flag bit
1 = Comparator input has changed (must be cleared in software)
0 = Comparator input has not changed
bit 5 USBIF: USB Interrupt Flag bit
1 = USB has requested an interrupt (must be cleared in software)
0 = No USB interrupt request
bit 4 EEIF: Data EEPROM/Flash Write Operation Interrupt Flag bit
1 = The write operation is complete (must be cleared in software)
0 = The write operation is not complete, or has not been started
bit 3 BCLIF: Bus Collision Interrupt Flag bit
1 = A bus collision has occurred (must be cleared in software)
0 = No bus collision occurred
bit 2 LVDIF: High/Low-Voltage Detect Interrupt Flag bit
1 = A high/low-voltage co ndition oc curr ed (must be cleared in software)
0 = No high/low-voltage event has occurred
bit 1 TMR3IF: TMR3 Overflow Interrupt Flag bit
1 = TMR3 register overflowed (must be cleared in software)
0 = TMR3 register did not overflow
bit 0 ECCP1IF: CCPx Interrupt Flag bit(1)
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode.
Note 1: This bit is available in 40/44-pin devices only.
Legend: Legend
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
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9.4 PIE Registers
The PIE registers contain the individual enable bits for
the peripheral interrupts. Due to the number of periph-
eral interrupt sources, there are two Peripheral Interrupt
Enable registers (PIE1 and PIE2). When IPEN = 0, the
PEIE bit must be set to enable any of these peripheral
interrupts.
REGISTER 9-6: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SPPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE
bit 7 bit 0
bit 7 SPPIE: Streaming Parallel Port Read/Write Interrupt Enable bit(1)
1 = Enables the SPP read/write interrupt
0 = Disables the SPP read/write interrupt
Note 1: This bit is reserved on 28-pin devices; always maintain this bit clear.
bit 6 ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D interrupt
0 = Disables the A/D interru pt
bit 5 RCIE: EUSART Receiv e Interru pt Enab le bit
1 = Enables the EUSART receive interrupt
0 = Disables the EUSA RT receive interrupt
bit 4 TXIE: EUSART Transmit Interrupt Enable bit
1 = Enables the EUSART transmit interrupt
0 = Disables the EUSART transmit interrupt
bit 3 SSPIE: Master Synchronous Serial Port Interrupt Enable bit
1 = Enables the MSSP interrupt
0 = Disables the MSSP interrupt
bit 2 CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
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REGISTER 9-7: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
OSCFIE CMIE USBIE EEIE BCLIE LVDIE TMR3IE CCP2IE
bit 7 bit 0
bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit
1 = Enabled
0 =Disabled
bit 6 CMIE: Comparator Interrupt Enable bit(1)
1 = Enabled
0 =Disabled
bit 5 USBIE: USB Interrupt Enable bit
1 = Enabled
0 =Disabled
bit 4 EEIE: Data EEPROM/Flash Write Operation Interrupt Enable bit
1 = Enabled
0 =Disabled
bit 3 BCLIE: Bus Collision Interrupt Enable bit
1 = Enabled
0 =Disabled
bit 2 LVDIE: High/Low-Voltage Detect Interrupt Enable bit
1 = Enabled
0 =Disabled
bit 1 TMR3IE: TMR3 Overflow Interrupt Enable bit
1 = Enabled
0 =Disabled
bit 0 CCP2IE: CCP2 Interrupt Enable bit
1 = Enabled
0 =Disabled
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
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9.5 IPR Registers
The IPR registers contain the individual priority bits for
the peripheral interrupts. Due to the number of
peripheral interrupt sources, there are two Peripheral
Interrupt Priority registers (IPR1 and IPR2). Using the
priority bits requires that the Interrupt Priority Enable
(IPEN) bit be set.
REGISTER 9-8: IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
SPPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP
bit 7 bit 0
bit 7 SPPIP: Streaming Parallel Port Read/Write Interrupt Priority bit(1)
1 =High priority
0 = Low priority
Note 1: This bit is reserved on 28-pin devices; always maintain this bit set.
bit 6 ADIP: A/D Converter Interrupt Priority bit
1 =High priority
0 = Low priority
bit 5 RCIP: EUSART Receive Interrupt Priority bit
1 =High priority
0 = Low priority
bit 4 TXIP: EUSART Transmit Interrupt Priority bit
1 =High priority
0 = Low priority
bit 3 SSPIP: Master Synchronous Serial Port Interrupt Priority bit
1 =High priority
0 = Low priority
bit 2 CCP1IP: CCP1 Interrupt Priority bit
1 =High priority
0 = Low priority
bit 1 TMR2IP: TMR2 to PR2 Match Interrupt Priority bit
1 =High priority
0 = Low priority
bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit
1 =High priority
0 = Low priority
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
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REGISTER 9-9: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2
R/W-1 R/W-1 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
OSCFIP CMIP USBIP EEIP BCLIP LVDIP TMR3IP CCP2IP
bit 7 bit 0
bit 7 OSCFIP: Oscillator Fail Interrupt Priority bit
1 =High priority
0 = Low priority
bit 6 CMIP: Comparator Interrupt Priority bit
1 =High priority
0 = Low priority
bit 5 USBIP: USB Interrupt Priority bit
1 =High priority
0 = Low priority
bit 4 EEIP: Data EEPROM/Flash Write Operation Interrupt Priority bit
1 =High priority
0 = Low priority
bit 3 BCLIP: Bus Collision Interrupt Priority bit
1 =High priority
0 = Low priority
bit 2 LVDIP: High/Low-Voltage Detect Interrupt Priority bit
1 =High priority
0 = Low priority
bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit
1 =High priority
0 = Low priority
bit 0 CCP2IP: CCP2 Interrupt Priority bit
1 =High priority
0 = Low priority
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
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DS39632A-page 108 Advance Information 2004 Microchip Technology Inc.
9.6 RCON Register
The RCO N regist er conta ins flag b its whic h are used to
deter mine the caus e of the last R eset or wa ke -up from
Idle or Slee p mo des . R CO N als o co ntains the IPE N b it
which enables interrupt priorities.
REGISTER 9-10: RCON REGISTER
R/W-0 R/W-1 U-0 R/W-1 R-1 R-1 R/W-0 R/W-0
IPEN SBOREN —RITO PD POR BOR
bit 7 bit 0
bit 7 IPEN: Interrupt Priority Enable bit
1 = Enable prio rity leve ls on inte rrup ts
0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode)
bit 6 SBOREN: Software BOR Enable bit
For details of bit operation, see Register 4-1.
bit 5 Unimplemented: Read as ‘0’
bit 4 RI: RESET Instruction Flag bit
For details of bit operation, see Register 4-1.
bit 3 TO: Watchdog Time-out Flag bit
For details of bit operation, see Register 4-1.
bit 2 PD: Power-Down Detection Flag bit
For details of bit operation, see Register 4-1.
bit 1 POR: Power-on Reset Status bit
For details of bit operation, see Register 4-1.
bit 0 BOR: Brown-out Reset Status bit
For details of bit operation, see Register 4-1.
Note 1: Actual Reset values are determined by device configuration and the nature of the
device Reset. See Register 4-1 for additional information.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
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9.7 INTn Pin Interrupts
External interrupts on the RB0/INT0, RB1/INT1 and
RB2/INT2 p ins are edge -triggered. If the corresponding
INTEDGx bit in the INTCON2 register is set (= 1), the
interrupt is triggered by a rising edge; if the bit is clear,
the trigger is on the falling edge. When a valid edge
appears on the RBx/INTx pin, the corresponding flag
bit, INTxF, is set. This interrupt can be disabled by
clearing the corresponding enable bit, INTxE. Flag bit,
INTxF, must be cleared in software in the Interrupt
Service Routine before re-enabling the interrupt.
All external interrupts (INT0, INT1 and INT2) can wake-
up the processor from the power managed modes if bit,
INTxE, was set prior to going into the power managed
modes. If the Globa l Interrupt Enable bit, GIE, is set, the
processor will branch to the interrupt vector following
wake-up.
Interrupt priority for INT1 and INT2 is determined by the
value contained in the interrupt priority bits, INT1IP
(INTCON3<6>) and INT2IP (INTCON3<7>). There is
no priority bit associated with INT0. It is always a high
priority interrupt source.
9.8 TMR0 Interrupt
In 8-b it mod e (whic h is the de faul t), a n overfl ow in t he
TMR0 register (FFh →00h) will set flag bit TMR0IF. In
16-bit mode, an overflow in the TMR0H:TMR0L regis-
ter pair (FFFFh → 0000h) wi ll set TMR0IF. The interrupt
can be enabled/disabled by setting/clearing enable bit,
TMR0IE (INTCON<5>). Interrupt priority for Timer0 is
determined by the value contained in the interrupt pri-
ority bit, TMR0IP (INTCON2<2>). See Section 13.0
“Timer2 Module” for further details on the Timer0
module.
9.9 PORTB Interrupt-on-Change
An input change on PORTB<7:4> sets flag bit, RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit, RBIE (INTCON<3>).
Interrupt priority for PORTB interrupt-on-change is
determined by the value contained in the interrupt
priority bit, RBIP (INTCON2<0>).
9.10 Context Saving During Interrupts
During interrupts, the return PC address is saved on
the st ack. Additiona lly , th e WREG, S t atus and BSR re g-
isters are sa ved on the fast return st ack . If a fast return
from interrupt is not used (see Section 5.3 “Data
Memory Organization”), the user may need to save
the WREG, Status and BSR registers on entry to the
Interrupt Service Routine. Depending on the user’s
applic ation, o the r regist ers ma y also need t o be save d.
Example 9-1 saves and restores the WREG, Status
and BSR regi sters d uring an In terrupt Servic e Rou tine.
EXAMPLE 9-1: SAVING STATUS, WREG AND BSR REGISTERS IN RAM
MOVWF W_TEMP ; W_TEMP is in virtual bank
MOVFF STATUS, STATUS_TEMP ; STATUS_TEMP located anywhere
MOVFF BSR, BSR_TEMP ; BSR_TMEP located anywhere
;
; USER ISR CODE
;
MOVFF BSR_TEMP, BSR ; Restore BSR
MOVF W_TEMP, W ; Restore WREG
MOVFF STATUS_TEMP, STATUS ; Restore STATUS
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NOTES:
2004 Microchip Technology Inc. Advance Information DS39632A-page 111
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10.0 I/O PORTS
Depending on the device selected and features
enabled, there are up to five ports available. Some pins
of the I/O ports are multiplexed with an alternate
function from the peripheral features on the device. In
general, when a perip heral is ena bled, that pi n may not
be used as a general purpose I/O pin.
Each port has three registers for its operation. These
registers are:
• TRIS register (data direction register)
• Port register (reads the levels on the pins of the
device)
• LAT register (output latch)
The Data Latch register (LATA) is useful for read-
modify-write operations on the value that the I/O pins
are driving.
A simplified model of a generic I/O port, without the
interf aces to other peripherals, is sho wn in Figure 10-1.
FIGURE 10-1: GENERIC I/O PORT
OPERATION
10.1 PORTA, TRISA and LATA Registers
PORTA is a 8-bit wide, bidirectional port. The corre-
sponding data direction register is TRISA. Setting a
TRISA bit (= 1) will make the corresponding PORT A pin
an input (i.e., put the corresponding output driver in a
high-impedance mode). Clearing a TRISA bit (= 0) wi ll
make the correspon ding POR TA pin an out put (i.e., put
the contents of the output latch on the selected pin).
Reading the PORTA register reads the status of the
pins; writing to it will write to the port latch.
The Data Latch register (LATA) is also memory
mapped. Read-modify-write operations on the LATA
register read and write the latched output value for
PORTA.
The RA4 pin is multiplexed with the Timer0 module
clock input to become the RA4/T0CKI pin. Pins RA6
and RA7 are multiplexed with the main oscillator pins;
they are enabled as oscillator or I/O pins by the selec-
tion of t he main os ci l la t or i n Con f i gu rat i o n Re g is t er 1 H
(see Section 25.1 “Configuration Bits” for details).
When th ey are not used as port pins, RA6 and RA7 and
their associated TRIS and LAT bits are read as ‘0’.
RA4 is also multi plexe d wi th the USB m odule; it se rves
as a receiver input from an external USB transceiver.
For details on configuration of the USB module, see
Section 17.2 “USB Status and Control”.
Several PORT A pins are multiplexed with analog inputs,
the analog VREF+ and VREF- inputs and the comparator
voltage reference output. The operation of pins
RA3:RA0 and RA5 a s A/D conve rter inp uts is sel ected
by clearing/setting the control bits in the ADCON1
register (A/D Control Register 1).
All other PORTA pins have TTL input levels and full
CMOS out put driv ers .
The TRISA register controls the direction of the RA
pins, ev en w he n th ey a re being use d as ana log inp uts.
The user mu st ensure the bit s in the TRISA registe r are
maintained set when using them as analog inputs.
EXAMPLE 10-1: INITIALIZING PORTA
Data
Bus
WR LAT
WR TRIS
RD Port
Data Latch
TRIS Latch
RD TRIS
Input
Buffer
I/O pin(1)
QD
CK
QD
CK
EN
QD
EN
RD LAT
or Port
Note 1: I/O pins have diode protection to VDD and VSS.
Note: On a Power-on Reset, RA5 and RA3:RA0
are configured as analog inputs and read
as ‘0’. RA4 is configured as a digital input.
CLRF PORTA ; Initialize PORTA by
; clearing output
; data latches
CLRF LATA ; Alternate method
; to clear output
; data latches
MOVLW 0Fh ; Configure A/D
MOVWF ADCON1 ; for digital inputs
MOVLW 07h ; Configure comparators
MOVWF CMCON ; for digital input
MOVLW 0CFh ; Value used to
; initialize data
; direction
MOVWF TRISA ; Set RA<3:0> as inputs
; RA<5:4> as outputs
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DS39632A-page 112 Advance Information 2004 Microchip Technology Inc.
TABLE 10-1: PORTA I/O SUMMARY
Pin Function TRIS
Setting I/O I/O Type Description
RA0/AN0 RA0 0OUT DIG LATA<0> data output; not affected by analog input.
1IN TTL PORTA<0> data input; disabled when analog input enabled.
AN0 1IN ANA A/D input channel 0 and Comparator C1- input. Default configuration
on POR; does not affect digital output.
RA1/AN1 RA1 0OUT DIG LATA<1> data output; not affected by analog input.
1IN TTL PORTA<1> data input. Reads ‘0’ on POR.
AN1 1IN ANA A/D input channel 1 and Comparator C2- input. Default configuration
on POR; does not affect digital output.
RA2/AN2/
VREF-/CVREF RA2 0OUT DIG LATA<2> data output; not affected by analog input. Disabled when
CVREF output enabled.
1IN TTL PORTA<2> data input. Disabled when analog functions enabled;
disabled when CVREF out put enabled.
AN2 1IN ANA A/D input channel 2 and Comparator C2+ input. Default configuration
on POR; not affected by analog output.
VREF- 1IN ANA A/D and comparator voltage reference low input.
CVREF OUT ANA Comparator voltage reference output. Enabling this feature disables
digital I/O.
RA3/AN3/
VREF+RA3 0OUT DIG LATA<3> data output; not affected by analog input.
1IN TTL PORTA<3> data input; disabled when analog input enabled.
AN3 1IN ANA A/D input channel 3 and Comparator C1+ input. Default configuration
on POR.
VREF+1IN ANA A/D and comparator voltage reference high input.
RA4/T0CKI/
C1OUT/RCV RA4 0OUT DIG LATA<4> data output; not affected by analog input.
1IN ST PORTA<4> data input; disabled when analog input enabled.
T0CKI 1IN ST Timer0 clock input.
C1OUT 0OUT DIG Comparator 1 output; takes priority over port data.
RCV IN TTL External USB transceiver RCV input.
RA5/AN4/SS/
HLVDIN/C2OUT RA5 0OUT DIG LATA<5> data output; not affected by analog input.
1IN TTL PORTA<5> data input; disabled when analog input enabled.
AN4 1IN ANA A/D input channel 4. Default configuration on POR.
SS 1IN TTL Slave select input for SSP (MSSP module).
HLVDIN 1IN A NA High/Low-Voltage Detect external trip point input.
C2OUT 0OUT DIG Comparator 2 output; takes priority over port data.
OSC2/CLKO/
RA6 RA6 0OUT DIG LATA<6> data output. Available only in ECIO, ECPIO and INTIO
modes; otherwise reads as ‘0’.
1IN TTL PORTA<6> data input. Available only in ECIO, ECPIO and INTIO
modes; otherwise reads as ‘0’.
OSC2 xOUT A NA M ain oscillator feedback output connection (all XT and HS modes).
CLKO xOUT DIG System cy cle clock output (FOSC/4); available in EC, ECPLL and
INTCKO modes.
Legend: O UT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, OD = Open-Drain Output,
ST = Schmitt Buffer Input, TTL = TTL Buffer Input
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TABLE 10-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset
Values
on page
PORTA —RA6
(1) RA5 RA4 RA3 RA2 RA1 RA0 54
LATA —LATA6
(1) LATA Data O utput Register 54
TRISA —TRISA6
(1) PORTA Data Direction Register 54
ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 52
CMCON(2) C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 53
CVRCON(2) CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 53
UCON —PPBRST SE0 PKTDIS USBEN RESUME SUSPND —55
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by P ORTA.
Note 1: RA6 and its associated latch and data direction bits are enabled as I/O pins based on oscillator
configuration; otherwise, they are read as ‘0’.
2: These registers are unimplemented on 28-pin devices.
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10.2 PORTB, TRISB and LATB
Registers
PORTB is an 8-bit wide, bidirectional port. The corre-
sponding data direction register is TRISB. Setting a
TRISB bit (= 1) will make the corresponding PORTB
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISB bit (= 0)
will make th e corresp onding POR TB pi n an out put (i.e .,
put the contents of the ou tput latch on the selected pin).
The Data Latch register (LATB) is also memory
mapped. Read-modify-write operations on the LATB
register read and write the latched output value for
PORTB.
Each of th e POR TB pins has a we ak inte rnal pul l-up. A
single control bit can turn on all the pull-ups. This is
performed by clearing bit RBPU (INTCON2<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on a Power-on Reset.
Four of the PORTB pins (RB7:RB4) have an interrupt-
on-change feature. Only pins configured as inputs can
cause this interrupt to occur; any RB7:RB4 pin
configured as an output is excluded from the interrupt-
on-change comparison. The pins are compared with
the old value latched on the last read of PORTB. The
“mismatch” outputs of RB7:RB4 are ORed together to
generate the RB Port Change Interrupt with Flag bit,
RBIF (INTCON<0>).
The interrupt-on-change can be used to wake the
device from Sleep. The user, in the Interrupt Service
Routine, can clear the interrupt in th e following manner:
a) Any read or write of PORTB (except with the
MOVFF (ANY), PORTB instruction). This will
end the mismatch condition.
b) Clear flag bit, RBIF.
A mismatc h condi tion wi ll contin ue to set flag bi t, RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit, RBIF, to be cleared.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
Pins, RB2 and RB3, are multiplexed with the USB
peripheral and serve as the differential signal outputs
for an external USB transceiver (TRIS configuration).
Refe r to Section 17.2.2.2 “External Transceiver” for
additional information on configuring the USB module
for operation with an external transceiver.
RB4 is multiplexed with CSSPP, the Chip Select
function for the Streaming Parallel Port (SPP) (TRIS
setting). Details of its operation are discussed in
Section 18.0 “Streaming Parallel Port”.
EXAMPLE 10-2: INITIA LIZING PORTB
Note: On a Power-on Reset, RB4:RB0 are
configu red as analog inp uts by defau lt and
read as ‘0’; RB7:RB5 are configured as
digital inputs.
By programming the configuration bit,
PBADEN (CONFIG3H<1>), RB4:RB0 will
alternatively be c onfigured as dig ital input s
on POR.
CLRF PORTB ; Initialize PORTB by
; clearing output
; data latches
CLRF LATB ; Alternate method
; to clear output
; data latches
MOVLW 0Eh ; Set RB<4:0> as
MOVWF ADCON1 ; digital I/O pins
; (required if config bit
; PBADEN is set)
MOVLW 0CFh ; Value used to
; initialize data
; direction
MOVWF TRISB ; Set RB<3:0> as inputs
; RB<5:4> as outputs
; RB<7:6> as inputs
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TABLE 10-3: PORTB I/O SUMMARY
Pin Function TRIS
Setting I /O I/O Type Description
RB0/AN12/
INT0/FLT0/
SDI/SDA
RB0 0OUT DIG LATB<0> data output; not affected by analog input.
1IN TTL PORTB<0> data input; weak pull-up when RBPU bit is cleared.
Disabled when analog input enabled(1).
AN12 1IN ANA A/D input channel 12(1).
INT0 1I N ST Ext ernal Interrupt 0 input.
FLT0 1IN ST Enhanced PWM Fault input (ECCP1 module); enabled in software.
SDI 1IN ST SPI™ data input (MSSP module).
SDA 1OUT DIG I2C™ data output (MSSP module); takes priority over port data.
1IN I2C/SMB I2C data input (MSSP module); input type depends on module setting.
RB1/AN10/
INT1/SCK/
SCL
RB1 0OUT DIG LATB<1> data output; not affected by analog input.
1IN TTL PORTB<1> data input; weak pull-up when RBPU bit is cleared.
Disabled when analog input enabled(1).
AN10 1IN ANA A/D input channel 10(1).
INT1 1I N ST Ext ernal interrupt 1 input.
SCK 0OUT DI G SPI clock output (MSSP module); takes priority over port data.
1IN ST SPI clock input (MSSP module).
SCL 0OUT DIG I2C clock output (MSSP module); takes priority over port data.
1IN I2C/SMB I2C clock input (MSSP module); input type depends on module setting.
RB2/AN8/
INT2/VMO RB2 0OUT DI G LATB<2> data output; not affected by analog input.
1IN TTL PORTB<2> data input; weak pull-up when RBPU bit is cleared.
Disabled when analog input enabled(1).
AN8 1IN ANA A/D input channel 8(1).
INT2 1I N ST Ext ernal Interrupt 2 input.
VMO OUT DIG External USB transceiver D- data output.
RB3/AN9/
CCP2/VPO RB3 0OUT DIG LATB<3> data output; not affected by analog input.
1IN TTL PORTB<3> data input; weak pull-up when RBPU bit is cleared.
Disabled when analog input enabled(1).
AN9 1IN ANA A/D input channel 9(1).
CCP2(2) 0OUT DIG CCP2 Compare and PWM output.
1IN ST CCP2 Capture input.
VPO OUT DIG External USB transceiver D+ data output.
RB4/AN11/
KBI0/CSSPP RB4 0OUT DIG LATB<4> data output; not affected by analog input.
1IN TTL PORTB<4> data input; weak pull-up when RBPU bit is cleared.
Disabled when analog input enabled(1).
AN11 1IN ANA A/D input channel 11(1).
KBI0 1IN TTL Interrupt on pin change.
CSSPP(4) IN DIG SPP chip select control output.
RB5/KBI1/
PGM RB5 0OUT DIG LATB<5> data output.
1IN TTL PORTB<5> data input; weak pull-up when RBPU bit is cleared.
KBI1 1IN TTL Interrupt on pin change.
PGM xIN ST Single-Supply Programming mode entry (ICSP). Enabled by LVP
configuration bit; all other pin functions disabled.
Legend: PWR = Power Supply, OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, OD = Open-Drain Output,
ST = Schmitt Buffer Input, TTL = TTL Buffer Input
Note 1: Configuration on POR is determined by PBADEN configuration bit. Pins are configured as analog inputs when PBADEN
is set and digital inputs when PBADEN is cleared.
2: Alternate pin assignment for CCP2, when CCP2MX = 0. Default assignment is RC3.
3: All other pin functions are disabled when ICSP™ or ICD operation are enabled.
4: 40/44-pin devices only.
PIC18F2455/2550/4455/4550
DS39632A-page 116 Advance Information 2004 Microchip Technology Inc.
TABLE 10-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
RB6/KBI2/
PGC RB6 0OUT DIG LATB<6> data output.
1IN TTL PORTB<6> data input; weak pull-up when RBPU bit is cleared.
KBI2 1IN TTL Interrupt on pin change.
PGC xIN ST Serial execution (ICSP) clock input for ICSP and ICD operation(3).
RB7/KBI3/
PGD RB7 0OUT DIG LATB<7> data output.
1IN TTL PORTB<7> data input; weak pull-up when RBPU bit is cleared.
KBI3 1IN TTL Interrupt on pin change.
PGD xOUT DIG Serial execution data output for ICSP and ICD operation(3).
xIN ST Serial execution data input for ICSP and ICD operation(3).
TABLE 10-3: PORTB I/O SUMMARY (CONTINUED)
Pin Function TRIS
Setting I /O I/O Type Description
Legend: PWR = Power Supply, OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, OD = Open-Drain Output,
ST = Schmitt Buffer Input, TTL = TTL Buffer Input
Note 1: Configuration on POR is determined by PBADEN configuration bit. Pins are configured as analog inputs when PBADEN
is set and digital input s when PBADEN is cleared.
2: Alternate pin assignment for CCP2, when CCP2MX = 0. Default assignment is RC3.
3: All other pin functions are disabled when ICSP™ or ICD operation are enabled.
4: 40/44-pin devices only.
Name Bit 7 Bit 6 B it 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset
Values
on page
PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 54
LATB LATB Data Output Register (Read and Write to Data Latch) 54
TRISB PORTB Data Direction Control Register 54
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51
INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 —TMR0IP —RBIP51
INTCON3 INT2IP INT1IP —INT2IEINT1IE— INT2IF INT1IF 51
ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 52
SPPCON(1) — — — — — — SPPOWN SPPEN 55
SPPCFG(1) CLKCFG1 CLKCFG0 CSEN CLK1EN WS3 WS2 WS1 WS0 55
UCON —PPBRST SE0 PKTDIS USBEN RESUME SUSPND —55
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTB.
Note 1: These registers are uni mp lem en t ed on 28-pin dev ic es .
2004 Microchip Technology Inc. Advance Information DS39632A-page 117
PIC18F2455/2550/4455/4550
10.3 PORTC, TRISC and LATC
Registers
PORTC is a 7-bit wide, bidirectional port. The corre-
sponding data direction register is TRISC. Setting a
TRISC bit (= 1) will make the corresponding PORTC
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISC bit (= 0)
will mak e the correspo nding PORT C pin an ou tput (i.e.,
put the contents of the ou tput latch on the selected pin).
In PIC18F2455/2550/4455/4550 devices, the RC3 pin
is no t implemented.
The Data Latch register (LATC) is also memory
mapped. Read-modify-write operations on the LATC
register read and write the latched output value for
PORTC.
POR TC is primarily multiplexe d with serial comm unica-
tions modules, including the USART, MSSP module
and the U SB mod ule (Table 10-5). Except for RC 4 an d
RC5, PORTC uses Schmitt Trigger input buffers.
Pins RC4 and RC5 are multiplexed with the USB
module . Depen ding on the con figuration of the module,
they can serve as the differential data lines for the on-
chip USB transceiver, or the data inputs from an
external USB transceiver. Both RC4 and RC5 have
TTL inp ut b uffers instead of the Sc hmitt Trigger buf fe rs
on the other pins.
Unlike other PORTC pins, RC4 and RC5 do not have
TRISC b its as so cia t ed wit h t he m. A s di gi ta l po rts, they
can only functi on as di git al inpu ts. When con figured for
USB operation, the data direction is determined by the
configuration and status of the USB module at a given
time. If an external transceiver is used, RC4 and RC5
always function as inputs from the transceiver. If the
on-chip transceiver is used, the data direction is deter-
mined by the operation being performe d by the modul e
at that time.
When the external transceiver is enabled, RC2 also
serves as the output enable control to the transceiver.
Additional information on configuring USB options is
provided in Section 17.2.2.2 “External Transceiver”.
When enabling peripheral functions on PORTC pins
other than RC4 and RC5, care should be taken in defin-
ing the TRIS bits. Some peripherals override the TRIS
bit to make a pin an output, while other peripherals
override the TRIS bit to make a pin an input. The user
should re fer to the cor respon ding periph eral section for
the correct TRIS bit settings.
The contents of the TRISC register are affected by
peripheral overrides. Reading TRISC always returns
the current contents, even though a peripheral device
may be overriding one or more of the pins.
EXAMPLE 10-3: INITIALIZING PORTC
Note: On a Power-on Reset, these pins are
configured as digital inputs.
CLRF PORTC ; Initialize PORTC by
; clearing output
; data latches
CLRF LATC ; Alternate method
; to clear output
; data latches
MOVLW 07h ; Value used to
; initialize data
; direction
MOVWF TRISC ; RC<5:0> as outputs
; RC<7:6> as inputs
PIC18F2455/2550/4455/4550
DS39632A-page 118 Advance Information 2004 Microchip Technology Inc.
TABLE 10-5: PORTC I/O SUMMARY
Pin Function TRIS
Setting I/O I/O Type Description
RC0/T1OSO/
T13CKI RC0 0OUT DIG LATC<0> data output.
1IN ST PORTC<0> data input.
T1OSO xOUT ANA Timer1 oscillator output; enabled when Timer1 oscillator enabled.
Disables digital I/O.
T13CKI 1IN S T Ti m er1/ Timer3 counter input.
RC1/T1OSI/
CCP2/UOE RC1 0OUT DIG LATC<1> data output.
1IN ST PORTC<1> data input.
T1OSI xIN A N A Timer1 oscillator input; enabled when Timer1 oscillator enabled.
Disables digital I/O.
CCP2(1) 0OUT DIG CCP2 Compare and PWM output; takes priority over port data.
1IN ST CCP2 Capture input.
UOE OUT DIG External USB transceiver OE outpu t.
RC2/CCP1/
P1A RC2 0OUT DIG LATC<2> data output.
1IN ST PORTC<2> data input.
CCP1 0OUT DIG ECCP1 Compare and PWM output; takes priority over port data.
1IN ST ECCP1 Capture input.
P1A(3) OUT DIG E CCP1 Enhan ced PW M output, channel A; takes priority over port
data. May be configured for tri-state during Enhanced PWM shutdown
events.
RC4/D-/VM RC4 —(2) IN TTL PORTC<4> data input; disabled when USB enabled.
D- —(2) OUT XCVR USB bus differential minus line output (internal transceiver).
—(2) IN XCVR USB bus differential minus line input (internal transceiver).
VM —(2) IN TTL External USB transceiver VM input.
RC5/D+/VP RC5 —(2) IN TTL PORTC<5> data input; disabled when USB enabled.
D+ —(2) OUT XCVR USB bus differential plus line output (internal transceiver).
—(2) IN XCVR USB bus differential plus line input (internal transceiver).
VP —(2) IN TTL External USB transceiver VP input.
RC6/TX/CK RC6 0OUT DIG LATC <6> data output.
1IN ST PORTC<6> data input.
TX 1OUT DIG Asynchronous serial transmit data output (USART module); takes
priority over port data. User must configure as output.
CK 1OUT DIG Synchronous serial clock output (USART module); takes priority over
port data.
1IN ST Synchronous serial clock input (USART module).
RC7/RX/DT/
SDO RC7 0OUT DIG LATC<7> data output.
1IN ST PORTC<7> data input.
RX 1IN ST Asynchronous serial receive data input (USART module).
DT 1OUT DIG Synchronous serial data output (USART module); takes priority over
port data.
1IN ST Synchronous serial data input (USART module). User must configure
as an input.
SDO 0OUT DIG SPI data output (MSSP module).
Legend: PWR = Power Supply, OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, OD = Open-Drain Output,
ST = Schmitt Buffer Input, TTL = TTL Buffer Input, XCVR = USB transceiver.
Note 1: Default pin assignment. Alternate pin assignment is RB2 (when CCP2MX = 0).
2: RC4 and RC5 do not have corresponding TRISC bits. In port mode, these pins are input only. USB data direction is
determined by the USB configuration.
3: 40/44-pin devices only.
2004 Microchip Technology Inc. Advance Information DS39632A-page 119
PIC18F2455/2550/4455/4550
TABLE 10-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset
Values
on page
PORTC RC7 RC6 RC5 RC4 — RC2 RC1 RC0 54
LATC LATC7 LATC6 ——— LATC2 LATC1 LATC0 54
TRISC TRISC7 TRISC6 ——— TRISC2 TRISC1 TRISC0 54
UCON —PPBRST SE0 PKTDIS USBEN RESUME SUSPND —55
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by P ORTC.
PIC18F2455/2550/4455/4550
DS39632A-page 120 Advance Information 2004 Microchip Technology Inc.
10.4 PORTD, TRISD and LATD
Registers
PORTD is an 8-bit wide, bidirectional port. The corre-
sponding Data Direction register is TRISD. Setting a
TRISD bit (= 1) will make the corresponding PORTD
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISD bit (= 0)
will mak e the correspo nding PORT D pin an ou tput (i.e.,
put the contents of the ou tput latch on the selected pin).
The Data Latch register (LATD) is also memory
mapped. Read-modify-write operations on the LATD
register read and write the latched output value for
PORTD.
All pins on PORTD are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output.
Each of the PORTD pins has a weak internal pull-up. A
single control bit, RDPU (PORTE<7>), can turn on all
the pull-ups. This is performed by setting RDPU. The
weak pull-up is automatically turned off when the port
pin is configured as a digital output or as one of the
other multiplexed peripherals. The pull-ups are
disabled on a Power-on Reset. The PORTE register is
shown in Section 10.5 “PORTE, TRISE and LATE
Registers”.
Three of the PO RT D pins are mult iplexed w ith outp uts ,
P1B, P1C and P1D, of the Enhanced CCP module. The
operation of these additional PWM output pins is
covered in greater detail in Section 16.0 “Enhanced
Capture/Compare/PWM (ECCP) Module”.
PORTD can also be configured as an 8-bit wide
Streaming Parallel Port (SPP). In this mode, the input
buffers are TTL. For additional information on configu-
ration and uses of the SPP, see See Section 18.0
“Streaming Parallel Port”.
EXAMPLE 10-4: INITIALIZING PORTD
Note: PORTD is only available on 40/44-pin
devices.
Note: On a Power-on Reset, these pins are
configured as digital inputs.
Note: When the Enhanced PWM mode is used
with either dual or quad outputs, the SSP
functions of PORTD are automatically
disabled.
CLRF PORTD ; Initialize PORTD by
; clearing output
; data latches
CLRF LATD ; Alternate method
; to clear output
; data latches
MOVLW 0CFh ; Value used to
; initialize data
; direction
MOVWF TRISD ; Set RD<3:0> as inputs
; RD<5:4> as outputs
; RD<7:6> as inputs
2004 Microchip Technology Inc. Advance Information DS39632A-page 121
PIC18F2455/2550/4455/4550
TABLE 10-7: PORTD I/O SUMMARY
Pin Function TRIS
Setting I/O I/O Type Description
RD0/SPP0 RD0 0OUT DIG LATD<0> data output.
1IN ST PORTD<0> data input.
SPP0 OUT DIG SPP<0> output data; takes priority over port data.
IN TTL SP P<0> input data.
RD1/SPP1 RD1 0OUT DIG LATD<1> data output.
1IN ST PORTD<1> data input.
SPP1 OUT DIG SPP<1> output data; takes priority over port data.
IN TTL SP P<1> input data.
RD2/SPP2 RD2 0OUT DIG LATD<2> data output.
1IN ST PORTD<2> data input.
SPP2 OUT DIG SPP<2> output data; takes priority over port data.
IN TTL SP P<2> input data.
RD3/SPP3 RD3 0OUT DIG LATD<3> data output.
1IN ST PORTD<3> data input.
SPP3 OUT DIG SPP<3> output data; takes priority over port data.
IN TTL SP P<3> input data.
RD4/SPP4 RD4 0OUT DIG LATD<4> data output.
1IN ST PORTD<4> data input.
SPP4 OUT DIG SPP<4> output data; takes priority over port data.
IN TTL SP P<4> input data.
RD5/SPP5/P1B RD5 0OUT DIG LATD<5> data output
1IN ST PORTD<5> data input
SPP5 OUT DIG SPP<5> output data; takes priority over port data.
IN TTL SP P<5> input data.
P1B 0OUT DIG EC CP1 Enhanced PWM output, channel B; takes priority over
port and SPP data(1).
RD6/SPP6/P1C RD6 0OUT DIG LATD<6> data output.
1IN ST PORTD<6> data input.
SPP6 OUT DIG SPP<6> output data; takes priority over port data.
IN TTL SP P<6> input data.
P1C 0OUT DIG EC CP1 Enhanc ed PW M output, channel C; takes priority over
port and SPP data(1).
RD7/SPP7/P1D RD7 0OUT DIG LATD<7> data output.
1IN ST PORTD<7> data input.
SPP7 OUT DIG SPP<7> output data; takes priority over port data.
IN TTL SP P<7> input data.
P1D 0OUT DIG EC CP1 Enhanc ed PW M output, channel D; takes priority over
port and SPP data(1).
Legend: PWR = Power Supply, OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, OD = Open-Drain Output,
ST = Schmitt Buffer Input, TTL = TTL Buffer Input
Note 1: May be configured for tri-state during Enhanced PWM shutdown events.
PIC18F2455/2550/4455/4550
DS39632A-page 122 Advance Information 2004 Microchip Technology Inc.
TABLE 10-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset
Values
on page
PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 54
LATD LATD Data Output Register 54
TRISD PORTD Data Direction Register 54
PORTE RDPU — — — RE3(1,2) RE2(2) RE1(2) RE0(2) 54
CCP1CON EPWM1M1 EPWM1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 53
SPPCON — — — — — — SPPOWN SPPEN 55
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTD.
Note 1: Implemented only when Master Clear functionality is disabled (MCLRE configuration bit = 0).
2: RE3 is the only PORTE bit implemented on both 28-pin and 40/44-pin devices. All other bits are
implemented only when PORTE is implemented (i.e., 40/44-pin devices).
3: These bits are available on 40/44-pin devices only.
2004 Microchip Technology Inc. Advance Information DS39632A-page 123
PIC18F2455/2550/4455/4550
10.5 PORTE, TRISE and LATE
Registers
Depending on the particular PIC18F2455/2550/4455/
4550 device selected, PORTE is implemented in two
different ways.
For 40/44-pin devices, PORTE is a 4-bit wide port.
Three pins (RE0/AN5/CK1SPP, RE1/AN6/CK2SPP
and RE2/AN7/O ESPP ) are ind ivi du all y configura ble a s
inputs or outputs. These pins have Schmitt Trigger
input buffers. When sel ect ed a s an analog inp ut, t hes e
pins will read as ‘0’s.
The corresponding data direction register is TRISE.
Setting a TRISE bit (= 1) will make the corresponding
PORTE pin an input (i.e. , put th e corres po ndi ng outp ut
driver in a high-impedance mode). Clearing a TRISE bit
(= 0) will mak e the corre sponding P ORTE pin an output
(i.e., pu t the co ntents o f the output latch on the selecte d
pin).
In addition to port data, the PORTE register
(Register 10-1) also contains the RDPU control bit
(PORTE<7>); this enables or disables the weak
pull-ups on PORTD.
TRISE controls the direction of the RE pins, even when
they are being used as analog inputs. The user must
make sure to keep the pins configured as inputs when
using them as analog inputs.
The Data Latch register (LATE) is also memory
mapped. Read-modify-write operations on the LATE
register, read and write the latched output value for
PORTE.
The fourth pin of PORTE (MCLR/VPP/RE3) is an in put
only pin. Its operation is controlled by the MCLRE
configuration bit. When selected as a port pin
(MCLRE = 0), it functions as a digital in put only pin; as
such, i t does not have TRIS or LAT bit s assoc iated with
its operation. Otherwise, it functions as the device’s
Master Clear input. In either configuration, RE3 also
functions as the programming voltage input during
programming.
EXAMPLE 10-5: INITIALIZING PORTE
10.5.1 PORTE IN 28-PIN DEVICES
For 28-pin devices, PORTE is only available when
Master Clear functionality is disabled (MCLRE = 0). In
these cases, PORTE is a single bit, input only port com-
prised of RE3 only. The pin operates as previously
described.
REGISTER 10-1: PORTE REGISTER
Note: On a Power-on Reset, RE2:RE0 are
configured as analog inputs.
Note: On a Pow er- on Re set, RE3 i s enab led as
a digital input only if Master Clear
functionality is disabled.
CLRF PORTE ; Initialize PORTE by
; clearing output
; data latches
CLRF LATE ; Alternate method
; to clear output
; data latches
MOVLW 0Ah ; Configure A/D
MOVWF ADCON1 ; for digital inputs
MOVLW 03h ; Value used to
; initialize data
; direction
MOVLW 07h ; Turn off
MOVWF CMCON ; comparators
MOVWF TRISC ; Set RE<0> as inputs
; RE<1> as outputs
; RE<2> as inputs
R-0 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1
RDPU ———RE3
(1) RE2(2) RE1(2) RE0(2)
bit 7 bit 0
bit 7 RDPU: PORTD Pull-up Enable bit
1 = PORTD pull-ups are enabled by individual port latch values
0 = All PORTD pull-ups are disabled
bit 6-4 Unimplemented: Read as ‘0’
bit 3-0 RE3:RE0: PORTE Data Input bits(1,2)
Note 1: Implemented only when Master Clear functionality is disabled (MCLRE
configuration bit = 0); otherwise, read as ‘0’.
2: Unimplemented in 28-pin devices; read as ‘0’.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC18F2455/2550/4455/4550
DS39632A-page 124 Advance Information 2004 Microchip Technology Inc.
TABLE 10-9: PORTE I/O SUMMARY
TABLE 10-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Pin Function TRIS
Setting I/O I/O Type Description
RE0/AN5/
CK1SPP RE0 0OUT DIG LATE<0> data output; not affected by analog input.
1IN ST PORTE<0> data input; disabled when analog input enabled.
AN5 1IN ANA A /D input channel 5; default configuration on POR.
CK1SPP OUT DI G SPP clock 1 output (SPP enabled).
RE1/AN6/
CK2SPP RE1 0OUT DIG LATE<1> data output; not affected by analog input.
1IN ST PORTE<1> data input; disabled when analog input enabled.
AN6 1IN ANA A /D input channel 6; default configuration on POR.
CK2SPP OUT DI G SPP clock 2 output (SPP enabled).
RE2/AN7/
OESPP RE2 0OUT DIG LAT E<2> data output; not affected by analog input.
1IN ST PORTE<2> data input; disabled when analog input enabled.
AN7 1IN ANA A /D input channel 7; default configuration on POR.
OESPP OUT DIG SPP output enable output (SPP enabled).
MCLR/VPP/
RE3 RE3 — (1) IN ST PORTE<3> data input; enabled when MCLRE configuration bit is
clear.
MCLR —(1) IN ST External Master Clear input; enabled when MCLRE configuration bit
is set.
VPP — (1) IN ANA High-voltage detection, used for ICSP™ mode entry detection.
Always available, regardless of pin mode.
Legend: O UT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, OD = Open-Drain Output,
ST = Schmitt Buffer Input, TTL = TTL Buffer Input.
Note 1: RE3 does not have a corresponding TRISE<3> bit. This pin is always an input, regardless of mode.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset
Values
on page
PORTE RDPU — — —RE3
(1,2) RE2(2) RE1(2) RE0(2) 54
LATE — — — — — LATE Data Output Register(2) 54
TRISE — — — — — TRISE Data Direction Register(2) 54
ADCON1 —— VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 52
CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 53
SPPCON(3) — — — — — — SPPOWN SPPEN 55
SPPCFG(3) CLKCFG1 CLKCFG0 CSEN CLK1EN WS3 WS2 WS1 WS0 55
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTE.
Note 1: Implemented only when Master Clear functionality is disabled (MCLRE configuration bit = 0).
2: RE3 is the only PORTE bit implemented on both 28-pin and 40/44-pin devices. All other bits are
implemented only when PORTE is implemented (i.e., 40/44-pin devices).
3: These registe r s are uni mp lem en ted on 28-pin dev ic es .
2004 Microchip Technology Inc. Advance Information DS39632A-page 125
PIC18F2455/2550/4455/4550
11.0 TIMER0 MODULE
The T imer0 module incorporates th e following features:
• Software selectable operation as a timer or
counter in both 8-bit or 16-bit modes
• Readable and writable registers
• Dedicated 8-bit, software programmable
prescaler
• Selectable c l ock source (internal or external)
• Edge select for external clock
• Interrupt-on-overflow
The T0CON register (Register 11-1) controls all
aspects of the module’s operation, including the
prescale selection. It is both readable and writable.
A simplified block diagram of the Timer0 module in
8-bit mode is shown in Figure 11-1. Figure 11-2 shows
a simplified bl oc k diagram o f t he timer mo dul e i n 1 6-bit
mode.
REGISTER 11-1: T0CON: TIMER0 CONTROL REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0
bit 7 bit 0
bit 7 TMR0ON: Timer0 On/Off Control bit
1 = Enables Timer0
0 = Stops Timer0
bit 6 T08BIT: Timer0 8-bit/16-bit Control bit
1 = Timer0 is configured as an 8-bit timer/counter
0 = Timer0 is configured as a 16-bit timer/counter
bit 5 T0CS: Timer0 Clock Source Select bit
1 = Transit ion on T0CK I pin
0 = Internal instruction cycle clock (CLKO)
bit 4 T0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3 PSA: Timer0 Prescaler Assignment bit
1 = TImer0 presc aler is NOT assigned. Timer0 cloc k input by passes presc aler.
0 = Timer0 presca ler is assigned. Timer0 clock input comes from prescaler output.
bit 2-0 T0PS2:T0PS0: Timer0 Prescaler Select bits
111 = 1:256 Prescale value
110 = 1:128 Prescale value
101 = 1:64 Prescale value
100 = 1:32 Prescale value
011 = 1:16 Prescale value
010 = 1:8 Prescale value
001 = 1:4 Prescale value
000 = 1:2 Prescale value
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘ 0’ = Bit is cleared x = Bit is unknown
PIC18F2455/2550/4455/4550
DS39632A-page 126 Advance Information 2004 Microchip Technology Inc.
11.1 Timer0 Operation
Timer0 can operate as either a timer or a counter; the
mode is selected by clearing the T0CS bit
(T0CON<5>). In Timer mode, the module increments
on every clock by default unless a different prescaler
value is selected (see Section 11.3 “Prescaler”). If
the TMR0 register is written to, the increment is
inhibited for the following two instruction cycles. The
user can work around this by writing an adjusted value
to the TMR0 register.
The Counter mode is selected by setting the T0CS bit
(= 1). In Counter mode, Timer0 increments either on
every rising or falling edge of pin RA4/T0CKI. The
increm enting edg e is determin ed by the T imer0 Sourc e
Edge Select bit, T0SE (T0CON<4>); clearing this bit
selects the rising edge. Restrictions on the external
clock input are dis cu ssed below.
An external clock source can be used to drive Timer0;
however, it must meet certain requirements to ensure
that the external clock can be synchronized with the
internal phase clock (TOSC). There is a delay between
synchronization and the onset of incrementing the
timer/counter.
11.2 Timer0 Reads and Writes in
16-Bit Mode
TMR0H is not the actual high byte of Timer0 in 16-bit
mode; it is actually a buffered version of the real high
byte of Timer0, which is not directly readable nor writ-
able (refer to Figure 11-2). TMR0H is updated with the
contents of the high byte of Timer0 during a read of
TMR0L. This provides the ability to read all 16 bits of
T imer 0 without havi ng to verify tha t the read of the hig h
and low byte were valid, due to a rollover between
successive reads of the hi gh and low byte.
Similarly, a write to the high byte of Timer0 must also
take place through the TMR0H Buffer registe r. The high
byte is updated with the contents of TMR0H when a
write o ccurs to TMR0L. Th is allows all 16 bits o f T imer0
to be updated at once.
FIGURE 11-1: TIMER0 BLOCK DIAGRAM (8-BIT MODE)
FIGURE 11-2: TIMER0 BLOCK DIAGRAM (16-BIT MODE)
Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
T0CKI pin
T0SE
0
10
1
T0CS
FOSC/4
Programmable
Prescaler
Sync with
Internal
Clocks TMR0L
(2 TCY Delay)
Internal Data Bus
PSA
T0PS2:T0PS0
Set
TMR0IF
on Overflow
38
8
Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
T0CKI pin
T0SE
0
10
1
T0CS
FOSC/4
Programmable
Prescaler
Sync with
Internal
Clocks TMR0L
(2 TCY Delay)
Internal Data Bus
8
PSA
T0PS2:T0PS0
Set
TMR0IF
on Overflow
3
TMR0
TMR0H
High Byte
88
8
Read TMR0L
Write TMR0L
8
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11.3 Prescaler
An 8-bi t counter i s availabl e as a presc aler for the T imer0
module. The prescaler is not directly readable or writable;
its value is set by the PSA and T0PS2:T0PS0 bits
(T0CON<3:0>) which determine the prescaler
assi gn ment an d presca le ra tio .
Clearing the PSA bit assigns the prescaler to the
Timer0 module. When it is assigned, prescale values
from 1:2 through 1:256, in power-of-2 increments, are
selectable.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF TMR0, MOVWF
TMR0, BSF TMR0,etc.) clear the prescaler count.
11.3 .1 SWITCHING PRESC ALER
ASSIGNMENT
The prescaler assignment is fully under software
control and can be changed “on-the-fly” during program
execution.
11.4 Timer0 Int errupt
The TMR0 interrupt is generated when the TMR0
register overflows from FFh to 00h in 8-bit mode, or
from FFFFh to 0000h in 16-bit mode. This overflow sets
the TMR0IF flag bit. The interrupt can be masked by
clearing the TMR0IE bit (INTCON<5>). Before re-
enabling the interrupt, the TMR0IF bit must be cleared
in software by the Interrupt Service Routine.
Since Timer0 is shut down in Sleep mode, the TMR0
interrupt cannot awaken the processor from Sleep.
TABLE 11-1: REGISTERS ASSOCIATED WITH TIMER0
Note: Writing to TMR0 when the prescaler is
assign ed to Timer0 will clear th e presc aler
count but will not change the prescaler
assignment.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset
Values
on pag e
TMR0L Timer0 Module Low Byte Register 52
TMR0H Timer0 Module High Byte Register 52
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51
T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 52
TRISA — P ORTA Data Direction Register 54
Legend: — = unimplemented locations, read as ‘0’. Shaded cells are not used by Timer0.
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NOTES:
2004 Microchip Technology Inc. Advance Information DS39632A-page 129
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12.0 TIMER1 MODULE
The Timer1 timer/counter module incorporates these
features:
• Software selectab le operation as a 16-bit ti mer or
counter
• Readable and writable 8-bit registers (TMR3H
and TMR3L)
• Select able cl ock so urce (inte rnal or ex ternal), w ith
device clock or Timer1 oscillator internal options
• Interrupt-on-overflow
• Module R eset on CCP special event trigger
• Device clock status flag (T1RUN)
A simplified block diagram of the Timer1 module is
shown in Fi gure 12-1. A block di agr am o f the module’s
operatio n in Read /Wr ite mode is show n in Figure 12-2.
The module incorporates its own low-power oscillator
to provide an additional clocking option. The Timer1
oscillator can also be used as a low-power clock source
for the microcontroller in power managed operation.
Timer1 can also be used to provide Real-Time Clock
(RTC) functionality to applications with only a minimal
addition of external components and code overhead.
Timer1 is controlled through the T1CON Control
register (Register 12-1). It also contains the Timer1
Oscillator Enable bit (T1OSCEN). Timer1 can be
enabled or disabled by setting or clearing control bit,
TMR1ON (T1CON<0>).
REGISTER 12-1: T1CON: TIMER1 CONTROL REGISTER
R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
bit 7 bit 0
bit 7 RD16: 16-bit Read/Write Mode Enable bit
1 = Enables register read/write of TImer1 in one 16-bit operation
0 = Enables register read/write of Timer1 in two 8-bit operations
bit 6 T1RUN: Time r1 Syste m Cloc k Status bit
1 = Device clo c k is derived from Timer1 oscillato r
0 = Device clo ck is derived from another source
bit 5-4 T1CKPS1:T1CKPS0: Timer1 Input Clock Prescal e Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
bit 3 T1OSCEN: Timer1 Oscillator En able bit
1 = Timer1 oscillator is enabled
0 = Timer1 oscillator is shut off
The oscillator inverter and feedback resistor are turned off to eliminate power drain.
bit 2 T1SYNC: Timer1 External Clock Input Synchronization Select bit
When TMR1CS = 1:
1 = Do not synchronize external clock input
0 = Synchronize external clock input
When TMR1CS = 0:
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1 TMR1CS: Timer1 Clock Source Select bit
1 = External clock from pin RC0/T1OSO/T13CKI (on the rising edge)
0 = Internal clock (FOSC/4)
bit 0 TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘ 0’ = Bit is cleared x = Bit is unknown
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DS39632A-page 130 Advance Information 2004 Microchip Technology Inc.
12.1 Timer1 Operation
Timer1 can operate in one of these modes:
•Timer
• Synchronous Counter
• Asynchronous Counter
The operating mode is determined by the clock select
bit, TMR3CS (T3CON<1>). When TMR3CS is cleared
(= 0), Timer3 increments on every internal instruction
cycle (Fosc/4). When the bit is set, Timer3 increments
on every rising edge of the Timer1 external clock input
or the Timer1 oscillator, if enabled.
When Timer1 is enabled, the RC1/T1OSI and RC0/
T1OSO/T13CKI pins become inputs. This means the
values of TRISC<1:0> are ignored and the pins are
read as ‘0’.
FIGURE 12-1: TIMER1 BLOCK DIAGRAM
FIGURE 12-2: TIMER1 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)
T1SYNC
TMR1CS
T1CKPS1:T1CKPS0
Sleep Input
T1OSCEN(1)
FOSC/4
Internal
Clock
On/Off
Prescaler
1, 2, 4, 8 Synchronize
Detect
1
02
T1OSO/T13CKI
T1OSI
1
0
TMR1ON
TMR1L Set
TMR1IF
on Overflow
TMR1
High Byte
Clear TMR1
(CCP Special Event Trigger)
Timer1 Oscillator
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
On/Off
Timer1
T1SYNC
TMR1CS
T1CKPS1:T1CKPS0
Sleep Input
T1OSCEN(1)
FOSC/4
Internal
Clock
Prescaler
1, 2, 4, 8 Synchronize
Detect
1
02
T1OSO/T13CKI
T1OSI
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
1
0
TMR1L
Internal Data Bus
8
Set
TMR1IF
on Overflow
TMR1
TMR1H
High Byte
88
8
Read TMR1L
Write TMR1L
8
TMR1ON
Clear TMR1
(CCP Special Event Trigger)
Timer1 Oscillator
On/Off
Timer1
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12.2 Timer1 16-Bit Read/Write Mode
Timer1 can be configured for 16-bit reads and writes
(see Figure 12-2). When the RD16 control bit
(T1CON< 7>) is set, the add ress fo r TMR1H is mappe d
to a buffer r egist er fo r the high b yte o f Timer1. A read
from TMR1L will load the contents of the high byte of
Timer1 into the Timer1 high byte buffer. This provides
the user with the ability to accurately read all 16 bits of
Timer1 without having to determine whether a read of
the high byte, followed by a read of the low byte, has
become invalid due to a rollover between reads.
A write to the high byte of Timer1 must also take place
through the TMR1H Buffer register. The Timer1 high
byte is updated with the contents of TMR1H when a
write occurs to TMR1L. This allows a user to write all
16 bit s to both the high and low bytes of T imer1 at once.
The high byte of Timer1 is not directly readable or
writable in this mode. All reads and writes must take
place through the Timer1 High Byte Buffer register.
Writes to TMR1H do not clear the Timer1 prescaler.
The prescaler is only cleared on writes to TMR1L.
12.3 Timer1 Oscillator
An on-chip crystal oscillator circuit is incorporated
between pins T1OSI (input) and T1OSO (amplifier
output). It is enabled by setting the Timer1 Oscillator
Enable bit, T1OSCEN (T1CON<3>). The oscillator is a
low-power circuit rated for 32 kHz crystals. It will
continue to run during all power managed modes. The
circuit for a typical LP oscillator is shown in Figure 12-3.
Table 12-1 shows the capacitor selection for the Timer1
oscillator.
The user m us t pro vi de a sof tware time delay to en su re
proper start-up of the Timer1 oscillator.
FIGURE 12-3: EXTERNAL
COMPONENTS FOR THE
TI MER1 LP OSCILLATOR
T ABLE 12-1: CAPACITOR SELECTION FOR
THE TIMER OSCILLATOR
12.3.1 USING TIMER1 AS A CLOCK
SOURCE
The T imer1 oscillator is also available as a clock source
in po wer mana ged mod es. By set ting t he cloc k select
bits, SCS1:SCS0 (OSCCON<1:0>), to ‘01’, the device
switches to SEC_RUN mode; both the CPU and
periphera ls are clocked from the T imer1 o scillator . If the
IDLEN bit (OSCCON<7>) is cleared and a SLEEP
instruction is executed, the device enters SEC_IDLE
mode. Additional details are available in Section 3.0
“Power Managed Modes”.
Whenever the Timer1 oscillator is providing the clock
source, the Timer1 system clock status flag, T1RUN
(T1CON< 6>), is set. Th is can be us ed to determine th e
controller ’s current clocking mode. It can also indicate
the clock source being currently used by the Fail-Safe
Clock Monitor. If the Clock Monitor is enabled and the
Timer1 oscillator fails while providing the clock, polling
the T1RUN bit will indicate wheth er the clock is being
provided by the Timer1 oscillator or another source.
12.3.2 LOW-POWER TIMER1 OPTION
The Timer1 oscillator can operate at two distinct levels
of power consumption based on device configuration.
When the LPT 1OSC confi guration bi t is set, t he T imer1
oscillator operates in a low-power mode. When
LPT1OSC is not set, T imer1 operates at a higher power
level. Po we r co ns um ptio n fo r a p art ic ula r mo de is rel a-
tively constant, regardless of the device’s operating
mode. The default Timer1 configuration is the higher
power mode.
As the low-power Timer1 mode tends to be more sen-
sitive to interference, high noise environments may
cause some oscillator instability. The low-power option
is, therefore, best suited for low noise applications
where power conservation is an important design
consideration.
Note: See the Notes with Table 12-1 for additiona
l
information about capacitor selection.
C1
C2
XTAL
PIC18FXXXX
T1OSI
T1OSO
32.768 kHz
33 pF
33 pF
Osc Type Freq C1 C2
LP 32 kHz 27 pF(1) 27 pF(1)
Note 1: Microchip suggests these values as a
starting point in validating the oscillator
circuit.
2: Higher capacit ance inc reases the st abilit y
of the oscillator but also increases the
start-up time.
3: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external
components.
4: Capacitor values are for design guidance
only.
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12.3.3 TIMER1 OSCILLATOR LAYOUT
CONSIDERATIONS
The Timer1 oscillator circuit draws very little power
during operation. Due to the low-power nature of the
oscillator, it may also be sensitive to rapidly changing
signals in close proximity.
The oscillator circuit, shown in Figure 12-3, should be
located as close as possible to the microcontroller.
There should be no circuits passing within the oscillator
circuit boundaries other than VSS or VDD.
If a hig h-s pee d cir cui t m us t b e loc ate d near the o sc ill a-
tor (such as the CCP1 pin in Output Compare or PWM
mode, or the primary oscillator using the OSC2 pin), a
grounded guard ring around the oscillator circuit, as
shown in Figure 12-4, may be helpful when used on a
single-sided PCB, or in addition to a ground plane.
FIGURE 12-4: OSCILLATOR CIRCUIT
WITH GROUNDED GUARD
RING
12.4 Timer1 Interrupt
The TMR1 register pair (TMR1H:TMR1L) increments
from 0000h to FFFFh and rolls over to 0000h. The
Timer1 interrupt, if enabled, is generated on overflow,
which is latched in interrupt flag bit, TMR1IF
(PIR1<0>). This interrupt can be enabled or disabled
by setting or clearing the Timer1 Interrupt Enable bit,
TMR1IE (PIE1<0>).
12.5 Resetting Timer1 Us ing the CCP
Special Event Trigger
If eit her o f th e C CP modu le s is co n fig ur e d in C o mpare
mode to generate a special event trigger
(CCP1M3:CCP1M0 or CCP2M3:CCP2M0 = 1011),
this sig nal wil l reset T i mer1. Th e trigge r from CCP2 wil l
also start an A/D conversion if the A/D module is
enabled (see Section 15.3.4 “ Specia l Event Trigger”
for more information.).
The module must be configured as either a timer or a
synch rono us cou nte r to t ak e a dva nt age of thi s fe atur e.
When used this way, the CCPRH:CCPRL register pair
ef fe cti vely bec om es a period regi ste r for Timer1.
If Timer1 is running in Asynchronous Counter mode,
this Reset operation may not work.
In the event that a write to Timer1 coincides with a
special event trigger, the write operation will take
precedence.
12.6 Using Timer1 as a Real-Time
Clock
Adding an extern al LP os cilla tor to Timer1 (such as th e
one described in Section 12.3 “Timer1 Oscillator”
above), g ives use rs the optio n to includ e RTC fu nction-
ality to their applications. This is accomplished with an
inexpensive watch crystal to provide an accurate time
base and several lines of application code to calculate
the time. When operating in Sleep mode and using a
battery or supercapacitor as a power source, it can
completely eliminate the need for a separate RTC
device and battery backup.
The application code routine, RTCisr, shown in
Example 12-1, demonstrates a simple method to
increment a counter at one-second intervals using an
Interrupt Service R ou tin e. I ncrementi ng the TM R1 re g-
ister pair to overflow triggers the interrupt and calls the
routine, w hich in creme nts the seco nds cou nter by on e;
additional counters for minutes and hours are
inc remented as the prev ious counter overflo w.
Since the register pair is 16 bits wide, counting up to
overflow the register directly from a 32.768 kHz clock
would take 2 seconds. To force the overflow at the
required one-second intervals, it is necessary to pre-
load it; the simplest method is to set the MSb of TMR1H
with a BSF instruction. Note that the TMR1L register is
never preloaded or altered; doing so may introduce
cumulative erro r over many cycles.
For this m ethod to be a ccurate, T imer 1 must oper ate in
Asynchronous mode and the Timer1 overflow interrupt
must be enabled (PIE1<0> = 1) as shown in the
routine, RTCinit. The Timer1 oscillator must also be
enabled and running at all times.
VDD
OSC1
VSS
OSC2
RC0
RC1
RC2
Note: Not drawn to scale.
Note: The special event triggers from the CCP2
module will not set the TMR1IF interrupt
flag bit (PIR1<0>).
2004 Microchip Technology Inc. Advance Information DS39632A-page 133
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EXAMPLE 12-1: IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE
TABLE 12-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
RTCinit
MOVLW 80h ; Preload TMR1 register pair
MOVWF TMR1H ; for 1 second overflow
CLRF TMR1L
MOVLW b’00001111’ ; Configure for external clock,
MOVWF T1OSC ; Asynchronous operation, external oscillator
CLRF secs ; Initialize timekeeping registers
CLRF mins ;
MOVLW d’12’
MOVWF hours
BSF PIE1, TMR1IE ; Enable Timer1 interrupt
RETURN
RTCisr
BSF TMR1H, 7 ; Preload for 1 sec overflow
BCF PIR1, TMR1IF ; Clear interrupt flag
INCF secs, F ; Increment seconds
MOVLW d’59’ ; 60 seconds elapsed?
CPFSGT secs
RETURN ; No, done
CLRF secs ; Clear seconds
INCF mins, F ; Increment minutes
MOVLW d’59’ ; 60 minutes elapsed?
CPFSGT mins
RETURN ; No, done
CLRF mins ; clear minutes
INCF hours, F ; Increment hours
MOVLW d’23’ ; 24 hours elapsed?
CPFSGT hours
RETURN ; No, done
MOVLW d’01’ ; Reset hours to 1
MOVWF hours
RETURN ; Done
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 54
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 54
IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 54
TMR1L Timer1 Register, Low Byte 52
TMR1H TImer1 Register, High Byte 52
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 52
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.
Note 1: These bits are unimplemented on 28-pin devices; always maintain these bits clear.
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NOTES:
2004 Microchip Technology Inc. Advance Information DS39632A-page 135
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13.0 TIMER2 MODULE
The Timer2 module timer incorporates the following
features:
• 8-bit timer and period registers (TMR2 and PR2,
respectively)
• Readable and writable (both registers)
• Software programmable prescaler (1:1, 1:4 and
1:16)
• Software programmable postscaler (1:1 through
1:16)
• Interrupt on TMR2-to-PR2 match
• Optional use as the shift clock for the MSSP
module
The module is controlled through the T2CON register
(Register 13-1), which enables or disables the timer
and configures the prescaler and postscaler. Timer2
can be shut off by clearing control bit, TMR2ON
(T2CON<2>), to mini mize power consumpti on.
A simplified block diagram of the module is shown in
Figure 13-1.
13.1 Timer2 Operation
In normal operation, TMR2 is incremented from 00h on
each clock (FOSC/4). A 2-bit counter/prescaler on the
clock input gives direct input, divide-by-4 and divide-by-
16 prescale options; these are selected by the prescaler
control bits, T2CKPS1:T2CKPS0 (T2CON<1:0>). The
value of TMR 2 is comp ared to that of the period register ,
PR2, on each clock cycle. When the two values match,
the comparator generates a match signal as the timer
output. This signal also reset s the value of TMR2 to 00h
on the next cycle and drives the output counter/
postscaler (see Section 13.2 “Timer2 Interrupt”).
The TMR2 and PR2 registers are both directly readable
and writable. The TMR2 register is cleared on any
device Reset, while the PR2 register initializes at FFh.
Both the p rescaler and post scale r counters ar e cleare d
on the following events:
• a write to the TMR2 register
• a write to the T2CON register
• any device Reset (Power-on Reset, MCLR Reset,
Watchdog Timer Reset or Brown-out Reset)
TMR2 is not cleared when T2CON is written.
REGISTER 13-1: T2CON: TIMER2 CONTROL REGISTER
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0
bit 7 bit 0
bit 7 Unimplemented: Read as ‘0’
bit 6-3 T2OUTPS3:T2OUTPS0: T imer2 Output Postscale Select bits
0000 = 1:1 Postscale
0001 = 1:2 Postscale
•
•
•
1111 = 1:16 Postscale
bit 2 TMR2ON: Tim er2 On bit
1 = Timer2 is on
0 = Timer2 is off
bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Selec t bit s
00 = Prescaler is 1
01 = Prescaler is 4
1x = Prescaler is 16
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘ 0’ = Bit is cleared x = Bit is unknown
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13.2 Timer2 Interrupt
Timer2 also can generate an optional device interrupt.
The Timer2 output signal (TMR2-to-PR2 match) pro-
vides the input for the 4-bit output counter/postscaler.
This coun ter gen erat es th e TMR2 m atc h inter rupt flag
which is latched in TM R 2IF (P IR1<1 > ). Th e in terru pt i s
enabled by setting the TMR2 Match Interrupt Enable
bit, TMR2IE (PIE1<1>).
A range o f 16 po stscale options (fro m 1 : 1 thro ugh 1:1 6
inclusive) can be selected with the postscaler control
bits, T2OUTPS3:T2OUTPS0 (T2CON<7:3>).
13.3 TMR2 Output
The unscaled output of TMR2 is available primarily to
the CCP modules, where it is used as a time base for
operat io ns in PWM mo de.
T i mer2 ca n be op tion ally u sed as the sh ift clo ck so urce
for the MSSP module operating in SPI mode.
Additional information is provided in Section 19.0
“Master Synchronous Serial Port (MSSP) Module”.
FIGURE 13-1: TIMER2 BLOCK DIAGRAM
TABLE 13-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Comparator
TMR2 Output
TMR2
Postscaler
Prescaler PR2
2
FOSC/4
1:1 to 1:16
1:1, 1:4, 1:16
4
T2OUTPS3:T2OUTPS0
T2CKPS1:T2CKPS0
Set TMR2IF
Internal Data Bus 8
Reset TMR2/PR2
8
8
(to PWM or MSSP)
Match
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 54
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 54
IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 54
TMR2 Timer2 Register 52
T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 52
PR2 Timer2 Period Register 52
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.
Note 1: These bits are unimplemented on 28-pin devices; always maintain these bits clear.
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14.0 TIMER3 MODULE
The Timer3 module timer/counter incorporates these
features:
• Software selectab le operation as a 16-bit ti mer or
counter
• Readable and writable 8-bit registers (TMR3H
and TMR3L)
• Selectable clock source (internal or external) with
device clock or Timer1 oscillator internal options
• Interrupt-on-overflow
• Module R eset on CCP special event trigger
A simplified block diagram of the Timer3 module is
shown in Fi gure 14-1. A block di agr am o f the module’s
operatio n in Read /Wr ite mode is show n in Figure 14-2.
The Timer3 module is controlled through the T3CON
register (Register 14-1). It also selects the clock source
options for the CCP modules (see Section 15.1.1
“CCP Modules and Timer Resources” for more
information).
REGISTER 14-1: T3CON: TIMER3 CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
RD16 T3ECCP1(1) T3CKPS1 T3CKPS0 T3CCP1(1) T3SYNC TMR3CS TMR3ON
bit 7 bit 0
bit 7 RD16: 16-bit Read/Write Mode Enable bit
1 = Enables register read/write of Timer3 in one 16-bit operation
0 = Enables register read/write of Ti mer3 in two 8-bit operations
bit 6, 3 T3ECCP1:T3CCP1: Timer3 and Timer1 to CCPx Enable bits(1)
1x = Timer3 is the capture/compare clock source for both CCP and ECCP modules
01 = Timer3 is the ca ptur e/compare c l ock source for ECCP1;
Timer1 is the capture/compare clock source for CCP1
00 = Timer1 is the capture/compare clock source for both CCP and ECCP modules
Note 1: These bits are available on 40/44-pin devices only.
bit 5-4 T3CKPS1:T3CKPS0: Timer3 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
bit 2 T3SYNC: Timer3 External Clock Input Synchronization Control bit
(Not usable if the device clock comes from Timer1/Timer3.)
When TMR3CS = 1:
1 = Do not synchronize external clock input
0 = Synchronize external clock input
When TMR3CS = 0:
This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0.
bit 1 TMR3CS: Timer3 Clock Source S elect bit
1 = External clock input from Timer1 oscillator or T13CKI (on the rising edge after the first
falling edge)
0 = Internal clock (FOSC/4)
bit 0 TMR3ON: Timer3 On bit
1 = Enables Timer3
0 = Stops Timer3
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC18F2455/2550/4455/4550
DS39632A-page 138 Advance Information 2004 Microchip Technology Inc.
14.1 Timer3 Operation
Timer3 can operate in one of three modes:
•Timer
• Synchronous Counter
• Asynchronous Counter
The operating mode is determined by the clock select
bit, TMR3CS (T3CON<1>). When TMR3CS is cleared
(= 0), Timer3 increments on every internal instruction
cycle ( F OSC/4). When the bit is set, Timer3 increments
on every rising edge of the Timer1 external clock input
or the Timer1 oscillator, if enabled.
As with Timer1, the RC1/T1OSI and RC0/T1OSO/
T13CKI pi ns becom e input s when the Timer1 oscillat or
is enabled. This means the values of TRISC<1:0> are
ignored and the pins are read as ‘0’.
FIGURE 14-1: TIMER3 BLOCK DIAGRAM
FIGURE 14-2: TIMER3 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)
T3SYNC
TMR3CS
T3CKPS1:T3CKPS0
Sleep Input
T1OSCEN(1)
FOSC/4
Internal
Clock
Prescaler
1, 2, 4, 8 Synchronize
Detect
1
02
T1OSO/T13CKI
T1OSI
1
0
TMR3ON
TMR3L Set
TMR3IF
on Overflow
TMR3
High Byte
Timer1 Oscillator
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
On/Off
Timer3
CCP1/CCP2 Special Event Trigger
TCCPx Clear TMR3
T3SYNC
TMR3CS
T3CKPS1:T3CKPS0
Sleep Input
T1OSCEN(1)
FOSC/4
Internal
Clock
Prescaler
1, 2, 4, 8 Synchronize
Detect
1
02
T1OSO/T13CKI
T1OSI
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
1
0
TMR3L
Internal Data Bus
8
Set
TMR3IF
on Overflow
TMR3
TMR3H
High Byte
88
8
Read TMR1L
Write TMR1L
8
TMR3ON
CCP1/CCP2 Special Event Trigger
Timer1 Oscillator
On/Off
Timer3
Timer1 Clock Input
TCCPx Clear TMR3
2004 Microchip Technology Inc. Advance Information DS39632A-page 139
PIC18F2455/2550/4455/4550
14.2 Timer3 16-Bit Read/Write Mode
Timer3 can be configured for 16-bit reads and writes
(see Figure 14-2). When the RD16 control bit
(T3CON< 7>) is set, the add ress fo r TMR3H is mappe d
to a buffer r egist er fo r the high b yte o f Timer3. A read
from TMR3L will load the contents of the high byte of
Timer3 into the Timer3 high byte buffer. This provides
the user with the ability to accurately read all 16 bits of
Timer1 without having to determine whether a read of
the high byte, followed by a read of the low byte, has
become invalid due to a rollover between reads.
A write to the high byte of Timer3 must also take place
through the TMR3H Buffer register. The Timer3 high
byte is updated with the contents of TMR3H when a
write occurs to TMR3L. This allows a user to write all
16 bit s to both the high and low bytes of T imer3 at once.
The high byte of Timer3 is not directly readable or
writable in this mode. All reads and writes must take
place through the Ti mer3 High Byte Buffer register.
Writes to TMR3H do not clear the Timer3 prescaler.
The prescaler is only cleared on writes to TMR3L.
14.3 Using the Timer1 Oscillator as the
Timer3 Clock Source
The Timer1 internal oscillator may be used as the clock
source for Timer3. The Timer1 oscillator is enabled by
setting the T1 OSCEN (T1CON <3>) bi t. To use i t as th e
T imer3 clock source, the TMR3CS bit must also be set.
As previously noted, this also configures Timer3 to
increm ent on e very ri sin g edge of the o scillato r so urce.
The Timer1 oscillator is described in Section 12.0
“Timer1 Module”.
14.4 Timer3 Interrupt
The TMR3 register pair (TMR3H:TMR3L) increments
from 0000h to FFFFh and overflows to 0000h. The
Timer3 interrupt, if enabled, is generated on overflow
and is latched in interrupt flag bit, TMR3IF (PIR2<1>).
This interrupt can be enabled or disabled by setting or
clearing the Timer3 Interrupt Enable bit, TMR3IE
(PIE2<1>).
14.5 Resetting Timer3 Using the CCP
Special Event Trigger
If the CCP2 module is configured to generate a
special event trigger in Compare mode
(ECCP1M3:ECCP1M0 = 1011), this signal will reset
Timer3. It will also start an A/D conversion if the A/D
module is enabled (see Section 15.3.4 “Special
Event Trigger” for more information.).
The module must be configured as either a timer or
synch rono us cou nte r to t ak e a dva nt age of thi s fe atur e.
When used th is way , the ECCPR2H:ECCPR2L register
pair effectively becomes a period register for Timer3.
If Timer3 is running in Asynchronous Counter mode,
the Reset operation may not work.
In the event that a write to Timer3 coincides with a
special event trigger from a CCP module, the write will
take precedence.
TABLE 14-1: REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER
Note: The special event triggers from the CCP2
module will not set the TMR3IF interrupt
flag bit (PIR1<0>).
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51
PIR2 OSCFIF CMIF(2) —EEIF BCLIF LVDIF TMR3IF ECCP1IF(2) 54
PIE2 OSCFIE CMIE(2) —EEIE BCLIE LVDIE TMR3IE ECCP1IE(2) 54
IPR2 OSCFIP CMIP(2) —EEIP BCLIP LVDIP TMR3IP ECCP1IP(2) 54
TMR3L Timer3 Registe r Low Byte 53
TMR3H Timer3 Register High Byte 53
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 52
T3CON RD16 T3ECCP1(1) T3CKPS1 T3CKPS0 T3CCP1(1) T3SYNC TMR3CS TMR3ON 53
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module.
Note 1: These bits are available on 40/44-pin devices only.
2: These bits are available on 40/44-pin devices and reserved in 28-pin devices.
PIC18F2455/2550/4455/4550
DS39632A-page 140 Advance Information 2004 Microchip Technology Inc.
NOTES:
2004 Microchip Technology Inc. Advance Information DS39632A-page 141
PIC18F2455/2550/4455/4550
15.0 CAPTURE/COMPARE/PWM
(CCP) MODULES
PIC18F2455/2550/4455/4550 devices all have two
CCP (Capt ure/Comp are/PWM) modules. Each mo dule
cont ains a 16-bit register , whi ch can opera te as a 16-bit
Capture register, a 16-bit Compare register or a PWM
Master/Sl ave Dut y Cycle register.
In 28-pin devices, the two standard CCP modules (CCP1
and CCP2) operate as described in this chapter. In
40/44-pin devices, CCP1 is implemented as an
Enhanced CCP module, with standard Capture and
Compare modes and Enhanced PWM modes. The
ECCP implementation is discussed in Section 16.0
“Enh anced C apture/ Comp are/PWM (ECCP) M odule”.
The Ca pture and Comp are opera tions de scribed in this
chapter apply to all standard and Enhanced CCP
modules.
REGISTER 15-1: CCPxCON REGISTER (CCP2 MODULE, CCP1 MODULE IN 28-PIN DEVICES)
Note: Throughout this section and Section 16.0
“Enhanced Capture/Compare/PWM (ECCP)
Module”, references to the register and bit
names for CCP modules are referr ed to gener-
ically by the use of ‘x’ or ‘y’ in place of the
specific module number. Thus, “CCPxCON”
might refer to the control register for CCP1,
CCP2 or ECCP1. “CCPxCON” is used
throughout these sections to refer to the
module control register, regardless of whether
the CCP module is a standard or Enhanced
implementation.
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0
bit 7 bit 0
bit 7-6 Unimplemented: Re ad as ‘0’
bit 5-4 DCxB1:DCxB0: PWM Duty Cycle bit 1 and bit 0 for CCP Module x
Capture mode:
Unused.
Compare mode:
Unused.
PWM mo de:
These bits are the two LSbs (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight MSbs
(DCx9:DCx2) of the duty cycle are found in CCPRxL.
bit 3-0 CCPxM3:CCPxM0: CCP Module x Mode Select bits
0000 = Capture/Compare/PWM disabled (resets CCP module)
0001 = Reserved
0010 = Compare mode, toggle output on match (CCPIF bit is set)
0011 = Reserved
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, ever y 16th rising edge
1000 = Compare mode: initialize CCP pin low; on compare match, force CCP pin high
(CCPIF bit is set)
1001 = Compare mode: initialize CCP pin high; on compare match, force CCP pin low
(CCPIF bit is set)
1010 = Compare mode: generate software interrupt on compare match (CCPIF bit is set,
CCP pin reflects I/O st ate)
1011 = Compare mode: trigger special event, reset timer, start A/D conversion on
CCP2 match (CCPIF bit is set)
11xx =PWM mode
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC18F2455/2550/4455/4550
DS39632A-page 142 Advance Information 2004 Microchip Technology Inc.
15.1 CCP Module Configuration
Each Capture/Compare/PWM module is associated
with a control register (generically, CCPxCON) and a
data register (CCPRx). The data register, in turn, is
comprised of two 8-bit registers: CCPRxL (low byte)
and CCPRxH (high byte). All registers are both
readable and writable.
15.1.1 CCP MODULES AND TIMER
RESOURCES
The CCP modules utilize Timers 1, 2 or 3, depending
on the mo de selected. T imer1 and T imer3 are available
to modules in Capture or Compare modes, while
Timer2 is available for modules in PWM mode.
TABLE 15-1: CCP MODE – TIMER
RESOURCE
The assignment of a particular timer to a module is
determined by the Timer-to-CCP enable bits in the
T3CON register (Register 14-1). Both modules may be
acti ve at any given t ime an d may shar e the s ame tim er
resource if they are configured to operate in the same
mode (Capture/Compare or PWM) at the same time. The
interactions between the two modules are summarized in
Figure 15-2. In Timer1 in Asynchronous Counter mode,
the capture operation will not work.
15.1.2 CCP2 PIN ASSIGNMENT
The pin as signment fo r CCP2 (Capture inpu t, Compare
and PW M output) c an chang e, based o n device config-
uration. The CCP2MX configuration bit determines
which pin CCP2 is multiplexed to. By default, it is
assign ed to RC1 (CCP2M X = 1). If the conf iguration b it
is cleared, CCP2 is multiplexed with RB3.
Changing the pin assignment of CCP2 does not
automatically change any requirements for configuring
the port p in. Users m ust always veri fy that the app ropri-
ate TRIS register is configured correctly for CCP2
operation, regardless of where it is located.
TABLE 15-2: INTERACTIONS BETWEEN CCP1 AND CCP2 FOR TIMER RESOURCES
CCP/ECCP Mode Timer Resource
Capture
Compare
PWM
Ti mer1 or Timer3
Ti mer1 or Timer3
Timer2
CCP1 Mode CCP2 Mode Interaction
Capture Capture Each module can use TMR1 or TMR3 as the time base. The time base can be different
for each CCP.
Capture Compare C CP2 can be co nfigured for t he special ev ent trigger to reset TMR1 or TM R3 (dependi ng
upon which time base is used). Automatic A/D conversions on trigger event can also be
done. Operation of CCP1 could be affected if it is using the same timer as a time base.
Compare Capture CCP1 be configured for the Special Event Trigger to reset TMR1 or TMR3 (depending
upon which time base is used). Operation of CCP2 could be affected if it is using the
same timer as a time base.
Compare Compare Either module can be configured for the Special Event Trigger to reset the time base.
Automatic A/D conversions on CCP2 trigger event can be done. Conflicts may occur if
both modules are using the same time base.
Capture PWM(1) None
Compare PWM(1) None
PWM(1) Capture None
PWM(1) Compare None
PWM(1) PWM Both PWMs will have the same frequency and update rate (TMR2 interrupt).
Note 1: Includes standard and Enhanced PWM operation.
2004 Microchip Technology Inc. Advance Information DS39632A-page 143
PIC18F2455/2550/4455/4550
15.2 Capture Mode
In Capture mode, the CCPRxH:CCPRxL register pair
captures the 16-bit value of the TMR1 or TMR3
registers when an event occurs on the corresponding
CCPx pin. An event is defined as one of the following:
• every falling edge
• every rising edge
• every 4th rising edge
• every 16th rising edge
The event is selected by the mode select bits,
CCPxM3:CCPxM0 (CCPxCON<3:0>). When a capture
is made, the interrupt request flag bit, CCPxIF, is set; it
must be cleared in software. If another capture occurs
before the value in register CCPRx is read, the old
captured value is overwritten by the new captured value.
15.2.1 CCP PIN CONFIGURATION
In Capture mode, the appropriate CCPx pin should be
configured as an input by setting the corresponding
TRIS direction bit.
15.2.2 TIMER1/T IMER3 MODE SELECTION
The tim ers that are to be used with the capture feature
(Timer1 and/or Timer3) must be running in Timer mode or
Synchr oni zed Count er mode . I n As ynchr ono us Co unt er
mode, the capture operation will not work. The timer to be
used with each CCP module is selected in the T3CON
register (see Se cti on 15.1.1 “C CP M odu le s a nd Timer
Resources”).
15.2.3 SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep the
CCPxIE interrupt enable bit clear to avoid false inter-
rupts. The interrupt flag bit, CCPxIF, should also be
cleared following any such change in operating mode.
15.2.4 CCP PRESCALER
There are four prescaler settings in Capture mode; they
are specifie d as p art of the operati ng mode sel ected by
the mode select bits (CCPxM3:CCPxM0). Whenever
the CCP module is turned off or Capture mode is dis-
abled, the prescaler counter is cleared. This means
that any Reset will clear the prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleare d, therefore , the first cap ture may be from
a non-zero prescaler. Example 15-1 shows the
recommended method for switching between capture
prescalers. This example also clears the prescaler
counter and will not generate the “false” interrupt.
EXAMPLE 15-1: CHANGIN G BETWEEN
CAPTURE PRESCALERS
(CCP2 SHOWN)
FIGURE 15-1: CAPTURE MODE OPERATION BLOCK DIAGRAM
Note: If RB3/CCP2 or RC1/CCP2 is configured
as an output, a write to the port can cause
a capture condition.
CLRF CCP2CON ; Turn CCP module off
MOVLW NEW_CAPT_PS ; Load WREG with the
; new prescaler mode
; value and CCP ON
MOVWF CCP2CON ; Load CCP2CON with
; this value
CCPR1H CCPR1L
TMR1H TMR1L
Set CCP1IF TMR3
Enable
Q1:Q4
CCP1CON<3:0>
CCP1 pin Prescaler
÷ 1, 4, 16 and
Edge Detect TMR1
Enable
T3CCP2
T3CCP2
CCPR2H CCPR2L
TMR1H TMR1L
Set CCP2IF
TMR3
Enable
CCP2CON<3:0>
CCP2 pin Prescaler
÷ 1, 4, 16
TMR3H TMR3L
TMR1
Enable
T3CCP2
T3CCP1
T3CCP2
T3CCP1
TMR3H TMR3L
and
Edge Detect
4
44
PIC18F2455/2550/4455/4550
DS39632A-page 144 Advance Information 2004 Microchip Technology Inc.
15.3 Compare Mode
In Compare mode, the 16-bit CCPRx register value is
constantly compared against either the TMR1 or TMR3
register pair value. When a match occurs, the CCPx pin
can be:
• driven high
• driven low
• toggled (high-to-low or low-to-high)
• remain u nchanged (tha t is, reflect s the state of th e
I/O latch)
The acti on on the pin is b ased on the val ue of the mode
select bits (CCPxM3:CCPxM0). At the same time, the
interrupt flag bit, CCPxIF, is set.
15.3.1 CCP PIN CONFIGURATION
The user must configure the CCPx pin as an output by
clearing the appropriate TRIS bit.
15.3.2 TIMER1/T IMER3 MODE SELECTION
Timer1 and/or Timer3 must be running in Timer mode
or Synchronized Counter mode if the CCP module is
using the compare feature. In Asynchronous Counter
mode, the compare operation may not work.
15.3.3 SOFTWARE INTERRUPT MODE
When the Generate Software Interrupt mode is chosen
(CCPxM3:CCPxM0 = 1010), t h e c o r res po nd i ng C C Px
pin is not affected. Only a CCP interrupt is generated,
if enabled and the CCPxIE bit is set.
15.3.4 SPECIAL EVENT TRIGGER
Both CCP modules are equipped with a special event
trigger. This is an internal hardware signal generated
in Compare mode to trigger actions by other modules.
The special event trigger is enabled by selecting
the Compare Special Event Trigger mode
(CCPxM3:CCPxM0 = 1011).
For either CCP module, the special event trigger resets
the timer register pair for whichever timer resource is
currently assigned as the module’s time base. This
allows the CCPRx registers to serve as a programm able
period register for either timer.
The special event trigger for CCP2 can also start an
A/D conversion. In order to do this, the A/D converter
must already be enabled.
FIGURE 15-2: COMPARE MODE OPERATION BLOCK DIAGRAM
Note: Clearing the CCP2CON register will force
the RB3 or RC1 compare output latch
(dependi ng on devi ce con figuration ) to the
default lo w level. This is not the POR TB or
PORTC I/O data latch.
CCPR1H CCPR1L
TMR1H TMR1L
Comparator Q
S
R
Output
Logic
Special Ev ent Trigger
Set CCP1IF
CCP1 pin
TRIS
CCP1CON<3:0>
Output Enable
TMR3H TMR3L
CCPR2H CCPR2L
Comparator
1
0
T3CCP2
T3CCP1
Set CCP2IF
1
0
Compare
4
(Timer1/Timer3 Reset)
Q
S
R
Output
Logic
Special Event Trigger
CCP2 pin
TRIS
CCP2CON<3:0>
Output Enab le
4
(Timer1/Timer3 Reset, A/D Trigger)
Match
Compare
Match
2004 Microchip Technology Inc. Advance Information DS39632A-page 145
PIC18F2455/2550/4455/4550
TABLE 15-3: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51
RCON IPEN SBOREN —RI TO PD POR BOR 52
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 54
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 54
IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 54
PIR2 OSCFIE CMIE —EEIE BCLIF LVDIF TMR3IF CCP2IF 54
PIE2 OSCFIF CMIF —EEIF BCLIE LVDIE TMR3IE CCP2IE 54
IPR2 OSCFIP CMIP —EEIP BCLIP LVDIP TMR3IP CCP2IP 54
TRISB PORTB Data Direction Control Register 54
TRI SC PORTC Data Direction Control Register 54
TMR1L Timer1 Register Low Byte 52
TMR1H Timer1 Register High Byte 52
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 52
TMR3H Timer3 Register High Byte 53
TMR3L Timer3 Register Low Byte 53
T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 53
CCPR1L Capture/Compare/PWM Register 1 Low Byte 53
CCPR1H Capture/Compare/PWM Register 1 High Byte 53
CCP1CON P1M1(1) P1M0(1) DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 53
CCPR2L Capture/Compare/PWM Register 2 Low Byte 53
CCPR2H Capture/Compare/PWM Register 2 High Byte 53
CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 53
Legend: — = unimplemented, read as ‘0’. Shade d cell s are not use d by Captu r e/Co mpare, Tim er1 or Timer3.
Note 1: These bits are unimplemented on 28-pin devices; always maintain these bits clear.
PIC18F2455/2550/4455/4550
DS39632A-page 146 Advance Information 2004 Microchip Technology Inc.
15.4 PWM Mode
In Pulse-W idth Modulati on (PWM) mode, the CCPx pin
produces up to a 10-bit resolution PWM output. Since
the CCP2 pin is multiplexed with a PORTB or PORTC
data latch, the appropriate TRIS bit must be cleared to
make the CCP2 pin an output.
Figure 15-3 shows a simplified block diagram of the
CCP module in PWM mo de.
For a ste p-by-step proc edure on how t o set up the CC P
module for PWM operation, see Section 15.4.4
“Setup for PWM Operation”.
FIGURE 15-3: SIMPLIFIED PWM BLOCK
DIAGRAM
A PWM output (Figure 15-4) has a time base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period
(1/period).
FIGURE 15-4: PWM OUTPUT
15.4.1 PWM PERIOD
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
following formula:
EQUATION 15-1:
PWM frequency is defined as 1/[PWM period].
When TM R2 is equal to PR2, t he following three event s
occur on the next increment cycle:
•TMR2 is cleared
• The CCP2 pin is set (exception: if PWM duty
cycle = 0%, the CCP2 pin will not be set)
• The PWM duty cycle is latched from CCPR2L into
CCPR2H
15.4.2 PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPR2L register and to the CCPxCON<5:4> bits. Up
to 10-bit resolution is available. The CCPRxL contains
the eight MSbs and the CCPxCON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPRxL:CCPxCON<5:4>. The following equation is
used to calculate the PWM duty cycle in time:
EQUATION 15-2:
CCPRx L an d CC PxC O N<5 :4> c an be w ri tten to a t an y
time, but the duty cycle value is not latched into
CCPR2H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR2H is a read-only re gister.
Note: Clearing the CCP2CON register will force
the RB3 or RC1 output latch (depending
on device configuration) to the default low
level. This is not the PORTB or PORTC
I/O data latch.
CCPRxL
CCPRxH (Slave)
Comparator
TMR2
Comparator
PR2
(Note 1)
RQ
S
Duty Cycle Registers CCPxCON<5:4>
Clear Timer,
CCP1 pin and
latch D.C.
Note 1: The 8-bit timer TMR2 value is concatenated with 2-bit
internal Q clock or 2 bits of the prescaler to create the
10-bit time base.
CCPx
Corresponding
TRIS bit
Output
Period
Duty Cycle
TMR2 = PR2
TMR2 = Duty Cycle
TMR2 = PR2
Note: The T imer2 post scalers (see Section 13.0
“Timer2 Module”) are not used in the
determination of the PWM frequency. The
postscaler could be used to have a servo
update rate at a different frequency than
the PWM output.
PWM Period = [(PR2) + 1] • 4 • TOSC •
(TMR2 Prescale Value)
PWM Duty Cycle = (CCPRXL:CCPXCON<5:4>) •
TOSC • (TMR2 Prescale Value)
2004 Microchip Technology Inc. Advance Information DS39632A-page 147
PIC18F2455/2550/4455/4550
The CCPR2H register and a 2-bit internal latch are
used to double-buffer the PWM duty cycle. This
double-buffering is essential for glitchless PWM
operation.
When the CCPRxH and 2-bit latch match TMR2,
concatenated with an internal 2-bit Q clock or 2 bits of
the TMR2 prescaler, the CCP2 pin is cleared.
The ma ximum P WM res olut ion (b its) fo r a giv en PWM
frequency is given by the equation:
EQUATION 15-3:
TABLE 15-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz
15.4.3 PWM AUTO-SHUTDOWN
(CCP1 ONLY)
The PWM auto-shutdown features of the Enhanced CCP
module are also available to CCP1 in 28-pin devices. The
operation of this feature is discussed in detail in
Section 16.4.7 “E nhanc ed PWM Auto- Shutdown”.
Auto-shutdown features are not available for CCP2.
15.4.4 SETUP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP module for PWM operation:
1. Set the PWM period by writing to the PR2
register.
2. Set the PWM duty cycle by writing to the
CCPR xL register and CCPxCON<5:4> bits.
3. Make the CCPx pin an output by clearing the
appropriate TRIS bit.
4. Set the TMR2 prescale value, then enable
Timer2 by writing to T2CON.
5. Configure the CCPx module f or PWM operatio n.
Note: If the PWM d uty c ycle v alu e i s lon ger tha n
the PWM period, the CCP2 pin will not be
cleared.
FOSC
FPWM
---------------
log
2()log
----------------------------- bits=
PWM Resolution (max)
PWM Frequency 2.44 kHz 9.77 kHz 39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz
Timer Prescaler (1, 4, 16)1641111
PR2 Value FFh FFh FFh 3Fh 1Fh 17h
Maximum Resolution (bits) 10 10 10 8 7 6.58
PIC18F2455/2550/4455/4550
DS39632A-page 148 Advance Information 2004 Microchip Technology Inc.
TABLE 15-5: REGISTERS ASSOCIATED WITH PWM AND TIMER2
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51
RCON IPEN SBOREN —RI TO PD POR BOR 52
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 54
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 54
IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 54
TRISB PORTB Data Direction Control Register 54
TRISC PORTC Data Dir ection Control Register 54
TMR2 Timer2 Register 52
PR2 Timer2 Period Register 52
T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 52
CCPR1L Capture/Compare/PWM Register 1 Low Byte 53
CCPR1H Capture/Compare/PWM Register 1 High Byte 53
CCP1CON P1M1(1) P1M0(1) DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 53
CCPR2L Capture/Compare/PWM Register 2 Low Byte 53
CCPR2H Capture/Compare/PWM Register 2 High Byte 53
CCP2CON —— DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 53
ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1(1) PSSBD0(1) 53
ECCP1DEL PRSEN PDC6(1) PDC5(1) PDC4(1) PDC3(1) PDC2(1) PDC1(1) PDC0(1) 53
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PWM or Timer2.
Note 1: These bits are unimplemented on 28-pin devices; always maintain these bits clear.
2004 Microchip Technology Inc. Advance Information DS39632A-page 149
PIC18F2455/2550/4455/4550
16.0 ENHANCED
CAPTURE/COMPARE/PWM
(ECCP) MODULE
In PIC18F4455/4550 devices, CCP1 is implemented
as a standard CCP module with Enhanced PWM
capabilities. These include the provision for 2 or 4
output channels, user selectable polarity, dead-band
control and automatic shutdown and restart. The
Enhanced features are discussed in detail in
Section 16.4 “Enhanced PWM Mode”. Capture,
Compare and single output PWM functions of the
ECCP module are the same as described for the
standard CCP module.
The control register for the Enhanced CCP module is
shown in Register 16-1. It differs from the CCPCON
registers in PIC18F2255/2550 devices in that the two
Most Significant bits are implemented to control PWM
functionality.
REGISTER 16-1: CCP1CON REGISTER (ECCP1 MODULE, PIC18F4455/4550 DEVICES)
Note: The ECCP mo dule is implemented onl y in
40/44-pin devices.
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0
bit 7 bit 0
bit 7-6 P1M1:P1M0: Enhanced PWM Output Configuration bits
If ECCP1M3:ECCP1M2 = 00, 01, 10:
xx = P1A assigned as Capture/Compare input/output; P1B, P1C, P1D assigned as port pins
If ECCP1M3:ECCP1M2 = 11:
00 = Single output: P1A modulated, P1B, P1C, P1D assigned as port pins
01 = Full-bridge output forward: P1D modulated; P1A active; P1B, P1C inactive
10 = Half-bridge output: P1A, P1B modulated with dead-band control; P1C, P1D assigned
as port pins
11 = Full-bridge output reverse: P1B modulated; P1C active; P1A, P1D inactive
bit 5-4 DC1B1:DC1B0: PWM Duty Cycle bit 1 and bit 0
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bit s are the two LSbs of the 10 -bit PWM duty cy cle. T he eigh t MSbs of the duty cycl e are
found in CCPRxL.
bit 3-0 CCP1M3:CCP1M0: Enhanced CCP Mode Select bits
0000 = Capture/Compare/PWM off (resets ECCP module)
0001 = Reserved
0010 = Compare mode, toggle output on match
0011 = Capture mode
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode, initialize ECCP pin low, set output on compare match (set ECCP1IF)
1001 = Comp are mode, initialize ECCP pin h igh, clear output on c ompare match (set ECCP1IF)
1010 = Compare mode, generate software interrupt only, CCP pin reverts to I/O state
1011 = Compa re mode , trigg er special event (ECC P reset s TMR1 or TM R3, set s ECCP1 IF bit )
1100 = PWM mode; P1A, P1C active-high; P1B, P1D active-high
1101 = PWM mode; P1A, P1C active-high; P1B, P1D active-low
1110 = PWM mode; P1A, P1C active-low; P1B, P1D active-high
1111 = PWM mode; P1A, P1C active-low; P1B, P1D active-low
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC18F2455/2550/4455/4550
DS39632A-page 150 Advance Information 2004 Microchip Technology Inc.
In addition to the expanded range of modes available
through the C CP1CO N regis ter, the ECCP module has
two additional registers associated with Enhanced
PWM opera tion and aut o-shutdown f eatures. They a re:
• ECCP1DEL (Dead-Band Delay)
• ECCP1AS (Auto-Shutdown Configuration)
16.1 ECCP Outputs and Configuration
The E nhance d CCP modul e may h ave up to four PW M
outputs, depending on the selected operating mode.
These outputs, designated P1A through P1D, are
multiplexed with I/O pins on PORTC and PORTD. The
outputs that are active depend on the CCP operating
mode selected. The pin assignments are summarized
in Table 16-1.
To configure the I/O pins as PWM outputs, the proper
PWM mode must be selected by setting the
EPWM1M1:EPWM1M0 and CCP1M3:CCP1M0 bits.
The appropriate TRISC and TRISD direction bits for the
port pins must also be set as outputs.
16.1.1 ECCP MODULES AND TIMER
RESOURCES
Like the standard CCP module s, the ECCP mod ule can
utilize Timers 1, 2 or 3, depending on the mode
select ed. Timer1 an d Timer3 are ava ila ble for m od ule s
in Capture or Compare modes, while Timer2 is
available for modules in PWM mode. Interactions
between the standard an d Enhanced CCP modules are
identic al to those d escribed for s tandard CCP modules.
Additional details on timer resources are provided in
Section 15.1.1 “CCP Modules and Timer
Resources”.
16.2 Capture and Comp are Modes
Except for the operation of the special event trigger
discussed below, the Capture and Compare modes of
the ECCP1 module are identical in operation to that of
CCP1. These are discussed in detail in Section 15.2
“Capture Mode” and Section 15.3 “Compare
Mode”.
16.2.1 SPECIAL EVENT TRIGGER
The special event trigger output of ECCP1 resets the
TMR1 o r TMR3 registe r pa ir , depe nding on w hich timer
resource is currently selected. This allows the ECCP1
register to effectively be a 16-bit programmable period
register for Timer1 or Timer3.
16.3 Standard PWM Mode
When configured in Single Output mode, the ECCP
module functions identically to the standard CCP
module in PWM mode as described in Section 15.4
“PWM Mode”. This is also sometimes referred to as
“Compatible CCP” mode, as in Table 16-1.
TABLE 16-1: PIN ASSIGNMENTS FOR VARIOUS ECCP1 MODES
Note: When setting up single output PWM
operations, users are free to use either of
the processes described in Section 15.4.4
“Setup for PWM Operation” or
Section 16.4.9 “Setup for PWM Opera-
tion”. The latter is more generic but will
work for either single or multi-output PWM.
ECCP Mode CCP1CON
Configuration RC2 RD5 RD6 RD7
All PIC18F4455/4550 devices:
Compatible CCP 00xx 11xx CCP1 RD5/SPP5 RD6/SPP6 RD7/SPP7
Dual PWM 10xx 11xx P1A P1B RD6/SPP6 RD7/SPP7
Quad PWM x1xx 11xx P1A P1B P1C P1D
Legend: x = Don’t care. Shaded cells indicate pin assignments not used by ECCP1 in a given mode.
2004 Microchip Technology Inc. Advance Information DS39632A-page 151
PIC18F2455/2550/4455/4550
16.4 Enhanced PWM Mode
The Enhanced PWM mode provides additional PWM
output options for a broader range of control applica-
tions. The module is a backwa rd com p a t ib le ve rsi on of
the st andard CCP m odule and o ffers up to four output s,
designated P1A through P1D. Users are also able to
select the polarity of the signal (either active-high or
active -low). The module’ s outpu t mode an d polarit y are
configured by setting the P1M1:P1M0 and
CCP1M3:CCP1M0 bits of the CCP1CON register.
Figure 16-1 shows a simplified block diagram of PWM
operatio n. All con trol regi sters are double -buf fe red and
are loaded at the beginning of a new PWM cycle (the
period boundary when Timer2 resets) in order to pre-
vent gli tches on any of the outputs. The exception is the
PWM Delay register, ECCP1DEL, which is loaded at
either the duty cycle boundary or the boundary period
(whichever comes first). Because of the buffering, the
modul e wai ts un t il th e as si gn ed ti m er rese ts in ste ad of
starting immediately. This means that Enhanced PWM
waveforms do not exactly match the standard PWM
wavef orms, but are ins tead of fset by one ful l instruc tion
cycle (4 TOSC).
As before, the user must manually configure the
appropriate TRIS bits for output.
16.4.1 PWM PERIOD
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
following equation:
EQUATION 16-1:
PWM frequency is defined as 1 /[PWM period]. When
TMR2 is e qual to PR 2, the foll owing three event s occur
on the next increment cycle:
•TMR2 is cleared
• The CCP1 pin is set (if PW M duty cycle = 0%, the
ECP1 pin will not be set)
• The PWM du ty cy cl e is copi ed from CCPR1L into
CCPR1H
FIGURE 16-1: SIMPLI FIED BLOCK DIAGRAM OF THE ENHANCED PWM MODULE
Note: The Timer2 postscaler (see Section 13.0
“Timer2 Module”) is not used in the
determination of the PWM frequency. The
postscaler could be used to have a servo
update rate at a different frequency than
the PWM output.
PWM Period = [(PR2) + 1] • 4 • TOSC •
(TMR2 Prescale Value)
CCPR1L
CCPR1H (Slave)
Comparator
TMR2
Comparator
PR2
(Note 1)
RQ
S
Duty Cycle Registers CCP1CON<5:4>
Clear Timer,
set CCP1 pin and
latch D.C.
Note: The 8-bit TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler, to create the 10-bit time
base.
TRISD<4>
CCP1/P1A
TRISD<5>
P1B
TRISD<6>
TRISD<7>
P1D
Output
Controller
P1M1:P1M0 2CCP1M3:CCP1M0
4
ECCP1DEL
CCP1/P1A
P1B
P1C
P1D
P1C
PIC18F2455/2550/4455/4550
DS39632A-page 152 Advance Information 2004 Microchip Technology Inc.
16.4.2 PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPR1L register and to the ECP1CON<5:4> bits. Up
to 10-bit resolution is available. The CCPR1L contains
the eight MSbs and the CCP1CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The PWM duty cycle is
calculated by the following equation.
EQUATION 16-2:
CCPR1L and CC P1CON <5:4> c an be wr itten to at an y
time, but the duty cycle value is not copied into
CCPR1H until a m atch between PR2 and TM R2 occurs
(i.e., the period is complete). In PWM mode, CCPR1H
is a read-only r egister.
The CCPR1H register and a 2-bit internal latch are
used to double-buffer the PWM duty cycle. This
double-b uf feri ng is esse ntial for g litchl ess PWM ope ra-
tion. When the CCPR1H and 2-bit latch match TMR2,
concatenated with an internal 2-bit Q clock or two bits
of the TMR2 prescaler, the CCP1 pin is cleared. The
maximum PWM resolution (bits) for a given PWM
frequency is given by the following equation.
EQUATION 16-3:
16.4.3 PWM OUTPUT CONFIGURATIONS
The EPWM1M1:EPWM1M0 bits in the ECCP1CON
register allow one of four configurations:
• Single Output
• Half-Bridge Output
• Full-Br idge Output, Forward mo de
• Full-Bridge Output, Reverse mode
The Single Output mode is the standard PWM mode
discussed in Section 16.4 “Enhanced PWM Mode”.
The Half-Bridge and Full-Bridge Output modes are
covered in detail in the sections that follow.
The general relationship of the outputs in all
configurations is summarized in Figure 16-2 and
Figure 16-3.
TABLE 16-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz
PWM Duty Cycle = (ECCPR1L:ECCP1CON<5:4> •
TOSC • (TMR2 P r escale Value)
Note: If the PWM d uty c ycle v alu e i s lon ger tha n
the PWM period, the CCP1 pin will not be
cleared.
()
PWM Resolution (max) =
FOSC
FPWM
log
log(2) bits
PWM Frequency 2.44 kHz 9.77 kHz 39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz
Timer Prescaler (1, 4, 16)1641111
PR2 Value FFh FFh FFh 3Fh 1Fh 17h
Maximum Resolution (bits) 10 10 10 8 7 6.58
2004 Microchip Technology Inc. Advance Information DS39632A-page 153
PIC18F2455/2550/4455/4550
FIGURE 16-2: PWM OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE)
FIGURE 16-3: PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE)
0
Period
00
10
01
11
SIGNAL PR2+1
CCP1CON
<7:6>
P1A Modulated
P1A Modulated
P1B Modulated
P1A Ac ti ve
P1B Inactive
P1C Inactive
P1D Modulated
P1A Inactive
P1B Modulated
P1C Active
P1D Inactive
Duty
Cycle
(Single Output)
(Half-Bridge)
(Full-Bridge,
Forward)
(Full-Bridge,
Reverse)
Delay(1) Delay(1)
0
Period
00
10
01
11
SIGNAL PR2+1
CCP1CON
<7:6>
P1A Modulated
P1A Modulated
P1B Modulated
P1A Ac ti ve
P1B Inactive
P1C Inactive
P1D Modulated
P1A Inactive
P1B Modulated
P1C Active
P1D Inactive
Duty
Cycle
(Single Output)
(Half-Bridge)
(Full-Bridge,
Forward)
(Full-Bridge,
Reverse)
Delay(1) Delay(1)
Relationships:
• Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value)
• Duty Cycle = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value)
• Delay = 4 * TOSC * (ECCP1DEL<6:0>)
Note 1: Dead-band delay is programmed using the ECCP1DEL register (Section 16.4.6 “Programmable Dead-Band Delay”).
PIC18F2455/2550/4455/4550
DS39632A-page 154 Advance Information 2004 Microchip Technology Inc.
16.4.4 HALF-BRIDGE MODE
In the Half-Bridge Output mode, two pins are used as
outputs to drive push-pull loads. The PWM output sig-
nal is outp ut on the P1 A pin , whi le th e comp lem entary
PWM output signal is output on the P1B pin
(Figure 16-4). This mode can be used for half-bridge
applic ati ons , as sh own in Figu re 16-5, or for full-b ridge
applications where four power switches are being
modulated with two PWM signals.
In Half-Bridge Output mode, the programmable
dead-ban d delay can be used t o preven t shoot-throug h
current in half-bridge power devices. The value of bits
PDC6:PDC0 sets the number of instruction cycles
befor e the output is driven acti ve. If the v alue is g reater
than the duty cycle, the corresponding output remains
inactive during the entire cycle. See Section 16.4.6
“Programmable Dead-Band Delay” for more details
of the dead-band delay operations.
Since the P1A and P1B outputs are multiplexed with
the PORTC<2> and PORTD<5> data latches, the
TRISC<2> and TRISD<5> bits must be cleared to
configure P1A and P1B as outputs.
FIGURE 16-4: HALF-BRIDGE PWM
OUTPUT
FIGURE 16-5: EXAMPLES OF HALF-BRIDGE OUTPUT MODE APPLICATIONS
Period
Duty Cycle
td
td
(1)
P1A(2)
P1B(2)
td = Dead-Band Delay
Period
(1) (1)
Note 1: At this time, the TMR2 register is equal to the
PR2 register.
2: Output signals are shown as active-high.
PIC18FX455/X550
P1A
P1B
FET
Driver
FET
Driver
V+
V-
Load
+
V
-
+
V
-
FET
Driver
FET
Driver
V+
V-
Load
FET
Driver
FET
Driver
PIC18FX455/X550
P1A
P1B
Stan d ard Half-Bridge Circuit (“Pu sh -Pull”)
Half-Bridge Output Driving a Full-Bridge Circuit
2004 Microchip Technology Inc. Advance Information DS39632A-page 155
PIC18F2455/2550/4455/4550
16.4.5 FULL-BRIDGE MODE
In Full-Bridge Output mode, four pins are used as
outputs; however , only two outputs are active at a time.
In the Forward mode, pin P1A is continuously active
and pin P1D is modulated. In the Reverse mode, pin
P1C is continuously active and pin P1B is modulated.
These are illustrated in Figure 16-6.
P1A, P1B, P1C and P1D outputs are multiplexed with
the PORTC<2>, PORTD<5>, PORTD<6> and
PORTD<7> data latches. The TRISC<2>, TRISD<5>,
TRISD<6> and TRISD<7> bits must be cleared to
make the P1A, P1B, P1C and P1D pins outputs.
FIGURE 16-6: FULL-BRIDGE PWM OUTPUT
Period
Duty Cycle
P1A(2)
P1B(2)
P1C(2)
P1D(2)
Forwar d Mo de
(1)
Period
Duty Cycle
P1A(2)
P1C(2)
P1D(2)
P1B(2)
Reverse Mode
(1)
(1)
(1)
Note 1: At this time, the TMR2 register is equal to the PR2 register.
Note 2: Output signal is shown as active-high.
PIC18F2455/2550/4455/4550
DS39632A-page 156 Advance Information 2004 Microchip Technology Inc.
FIGURE 16-7: EXAMP LE OF FULL-BRIDGE APPLICATION
16.4.5.1 Directio n Change in Full-Br idge M ode
In the Full-Bridge Output mode, the EPWM1M1 bit in
the CCP1CON register allows the user to control the
forward/reverse direction. When the application firm-
ware changes this direction control bit, the module will
assume the new direction on the next PWM cycle.
Just before the end of the current PWM period, the
modulated outputs (P1B and P1D) are placed in their
inactiv e state, whil e the unmodula ted outputs (P1A and
P1C) are switched to drive in the opposite direction.
This occurs in a time interval of (4 TOSC * (Timer2
Prescale Value) before the next PWM period begins.
The Timer2 prescaler will be either 1, 4 or 16, depend-
ing on the value of the T2CKPS bit (T2CON<1:0>).
During the interval from the switch of the unmodulated
outputs to the beginning of the next period, the
modulated outputs (P1B and P1D) remain inactive.
This relationship is shown in Figure 16-8.
Note that in the Full-Bridge Output mode, the CCP1
module do es not prov ide an y dead-band de lay. In ge n-
eral, since only one output is modulated at all times,
dead-band delay is not required. However, there is a
situation where a dead-band delay might be required.
This situation occurs when both of the following
conditions are true:
1. The direction of the PWM output changes when
the duty cycle of the output is at or near 100%.
2. The tu rn-off ti me of the po wer swi tch, incl uding
the power device and driver circuit, is greater
than the turn-on tim e.
Figure 16-9 shows an example where the PWM direc-
tion changes from forward to reverse at a near 100%
duty cycle. At time t1, the outputs, P1A and P1D,
become inactive, while output P1C becomes active. In
this example, since the turn-off time of the power
device s is longer th an the turn-on time, a shoot-through
current may flow through power devices, QC and QD,
(see Figure 16-7) for the duration of ‘t’. The same
phenomenon will occur to power devices, QA and QB,
for PWM direction change from reverse to forward.
If changing PWM direction at high duty cycle is required
for an application, one of the following requirements
must b e met:
1. Reduce PWM for a PWM period before
changing directions.
2. Use switch drivers th at can drive the switches of f
faster than they can drive them on.
Other options to prevent shoot-through current may
exist.
P1A
P1C
FET
Driver
FET
Driver
V+
V-
Load
FET
Driver
FET
Driver
P1B
P1D
QA
QB QD
QC
PIC18FX455/X550
2004 Microchip Technology Inc. Advance Information DS39632A-page 157
PIC18F2455/2550/4455/4550
FIGURE 16-8: PWM DIRE CTION CHANGE
FIGURE 16-9: PWM DIRE CTION CHANGE AT NEAR 100% DUTY CYCLE
DC
Period(1)
SIGNAL
Note 1: The direction bit in the CCP1 Control register (CCP1CON<7>) is written any time during the PWM cycle.
2: When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle at intervals
of 4 TOSC, 16 TOSC or 64 TOSC, depending on the Timer2 prescaler value. The modulated P1B and P1D signals
are inactive at this time.
Period
(Note 2)
P1A (Active-High)
P1B (Active-High)
P1C (Active-High)
P1D (Active-High)
DC
Forward Period Reverse Pe rio d
P1A
tON
tOFF
t = tOFF – tON
P1B
P1C
P1D
External Switch D
Potential
Shoot-Through
Current
Note 1: All signals are shown as active-high.
2: tON is the turn-on delay of power switch QC and its driver.
3: tOFF is the turn-off delay of power switch QD and its driver.
External Switch C
t1
DC
DC
PIC18F2455/2550/4455/4550
DS39632A-page 158 Advance Information 2004 Microchip Technology Inc.
16.4.6
PROGRAMMABLE DEAD-BAND
DELAY
In half-bridge applications where all power switches are
modulated at the PWM freque ncy at all times, the po wer
switches normally require more time to turn off than to
turn on. If both the upper and lower power switches are
switched at the same time (one turned on and the other
turned of f), both switches may be on for a short period of
time until one switch completely turns off. During this
brief interval, a very high current (shoot-through cu rrent)
may flow through both power switches, shorting the
bridge supply. To avoid this potentially destructive
shoot-through current from flowing during switching,
turning on either of the power switches is normally
delayed to allow the other switc h to comple tely turn off.
In the Half-Bridge Output mode, a digitally program-
mable dead-band delay is available to avoid
shoot-through current from destroying the bridge
powe r switc hes. T he del ay occu rs at t he sign al tran si-
tion from the non-active state to the active state. See
Figure 16-4 for illustration. Bits PDC6:PDC0 of the
ECCP1DEL register (Register 16-2) set the delay
period in terms of microcontroller instruction cycles
(TCY or 4 TOSC). These bits are not available on 28-pin
devi ces, as t he stand ard CCP m odule does not supp ort
half- brid ge ope rati on.
16.4.7
ENHANCED PWM AUTO-SHUTDOWN
When CCP1 is programmed for any of the Enhanced
PWM modes, the active output pins may be configured
for auto-shutdown. Auto-shutdown immediately places
the Enhanced PWM output pins into a defined shutdown
state when a shut dow n even t occurs.
A shutdown event can be caused by either of the
comparator modules, a low level on the
RB0AN12/INT 0/FLT0/SDI/SDA pin, or any combination
of these three sources. The comparators may be used to
monitor a voltage input proportional to a current being
monitored in the bridge circuit. If the voltage exceeds a
threshold, the comparator switches state and triggers a
shutdown. Alternatively, a digital signal on the INT0 pin
can also trigger a shut down. The auto-shut down feature
can be disabled by not selecting any auto-shutdown
sources. The auto-shutdown sources to be used are
selected using the ECCPAS2:ECCPAS0 bits (bits<6:4>
of the ECCP1AS register).
When a shutdown occurs, the output pins are
asynchronously placed in their shutdown states,
specified by the PSSAC1:PSSAC0 and
PSS1BD1:PSS1BD0 bits (ECCPAS3:ECC PA S0). Each
pin pair (P1A/P1C and P1B/P1D) may be set to drive
high, drive low or be tri-stated (not driving). The
ECCPASE bit (ECCP1AS<7>) is also set to hold the
Enhanced PWM outputs in their shut dow n st ates .
The ECCPASE bit is set by har dware when a shu tdown
event o cc urs. If autom ati c restarts are no t e nab led , th e
ECCPASE bit is cleared by firmware when the cause of
the shutdown clears. If automatic restarts are enabled,
the ECCPASE bit is automatically cleared when the
cause of the auto-shutdown has cleared.
If the ECCPASE bit is set when a PWM period begins,
the PWM o utputs remain in their shutdown stat e for that
entire PW M peri od. Wh en the ECCPASE bit is c leared,
the PWM outputs will return to normal operation at the
beginning of the next PWM period.
REGISTER 16-2: ECCP1DEL: PWM CONFIGURATION REGISTER
Note: Programmable dead-band delay is not
implemented in 28-pin devices with
standard CCP modules.
Note: Writing to the ECCPASE bit is disabled
while a shutdown condition is active.
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PRSEN PDC6(1) PDC5(1) PDC4(1) PDC3(1) PDC2(1) PDC1(1) PDC0(1)
bit 7 bit 0
bit 7 PRSEN: PWM Restart Enable bit
1 = Upon auto-shutdown, the ECCPASE bit clears automatically once the shutdown event
goes away; the PWM restarts automatically
0 = Upon auto-shutdown, ECCPASE must be cleared in software to restart the PWM
bit 6-0 PDC6:PDC0: PWM De la y Co unt bits(1)
Delay time, in number of FOSC/4 (4 * TOSC) cycles, between the scheduled and actual time for
a PWM signal to transition to active.
Note 1: Reserved on 28-pin de vic es; maintain th ese bits clear.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
2004 Microchip Technology Inc. Advance Information DS39632A-page 159
PIC18F2455/2550/4455/4550
REGISTER 16-3: ECCP1AS: ENHANCED CAPTURE/COMPARE/PWM AUTO-SHUTDOWN
CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1(1) PSSBD0(1)
bit 7 bit 0
bit 7 ECCPASE: ECCP Auto-Shutdown Event Status bit
1 = A shutdown event has occurred; ECCP outputs are in shutdown state
0 = ECCP outputs are operating
bit 6-4 ECCPAS2:ECCPAS0: ECCP Auto-Shutdown Source Select bits
111 = RB0 or Comparator 1 or Comparator 2
110 = RB0 or Comparat or 2
101 = RB0 or Comparat or 1
100 = RB0
011 = Either Comparator 1 or 2
010 = Comparator 2 output
001 = Comparator 1 output
000 = Auto-shutdown is disabled
bit 3-2 PSSAC1:PSSAC0: Pins A and C Shutdown State Control bits
1x = Pins A and C tr i-state (40 /44-pin devices)
01 = Drive Pins A and C to ‘1’
00 = Drive Pins A and C to ‘0’
bit 1-0 PSSBD1:PSSBD0: Pins B and D Shutdown State Control bits(1)
1x = Pins B and D tri-state
01 = Drive Pins B and D to ‘1’
00 = Drive Pins B and D to ‘0’
Note 1: Reserved on 28-pin devices; maintain these bits clear.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC18F2455/2550/4455/4550
DS39632A-page 160 Advance Information 2004 Microchip Technology Inc.
16.4.7.1 Auto-Shutdown and Auto-Restart
The auto-shutdown feature can be configured to allow
automatic restarts of the module following a shutdown
event. This is enabled by setting the PRSEN bit of the
ECCP1DEL register (ECCP1DEL<7>).
In Shut down mode with PRSEN = 1 (Figure 16-10), the
ECCPASE bit will remain set for as long as the cause
of the shutdown continues. When the shutdown condi-
tion clears, the ECCP1ASE bit is cleared. If PRSEN = 0
(Fig ure 16 -11) , o nce a s hutdow n c ondit io n oc cur s, t he
ECCPASE bit will remain set until it is cleared by
firmware. Once ECCPASE is cleared, the Enhanced
PWM will resume at the beginning of the next PWM
period.
Independent of the PRSEN bit setting, if the
auto-shutdown source is one of the comparators, the
shutdown condition is a level. The ECCPASE bit
cannot be cleared as long as the cause of the shutdown
persists.
The Auto-Shu tdown mode can be forced by writing a ‘1’
to the ECCPASE bit.
16.4.8 START-UP CONSIDERATIONS
When the ECCP mo dule is used in t he PWM mode, t he
application hardware must use the proper external pull-up
and/or pull-down resistors on the PWM output pins. When
the microcontroller is released from Reset, all of the I/O
pins are in the high-impedance state. The external circuits
must keep the pow er switch device s in the off state until
the microcontroller drives the I/O pins with the proper
signal levels, or activates the PWM output(s).
The CCP1M1:CCP1M0 bits (CCP1CON<1:0>) allow
the user to choose whether the PWM output sig nals are
active-high or active-low for each pair of PWM output
pins (P1A/P1C and P1B/P1D). The PWM output
polarities must be selected before the PWM pins are
configu red as output s. Changin g the p olarity conf igura-
tion while the PWM pins are configured as outputs is
not recom mended, sinc e it may result i n damage to th e
application circuits.
The P1A, P1B, P1C and P1D output latches may not be
in the proper states when the PWM module is initialized.
Enabling the P WM pins for outp ut at the sa me time as
the ECCP module may cause damage to the applica-
tion circuit . The ECCP module must be enabl ed in the
proper output mode and complete a full PWM cycle
before configuring the PWM pins as outputs. The com-
pletion o f a f ull PWM c ycle is indicate d by the TMR2I F
bit being set as the second PWM period begins.
FIGURE 16-10: PWM AUTO-SHUTDOWN (PRSEN = 1, AUTO-RESTART ENABLED)
FIGURE 16-11: PWM AUTO-SHUTDOWN (PRSEN = 0, AUTO-RESTART DISABLED)
Note: Writing to the ECCPASE bit is disabled
while a shutdown condition is active.
Shutdown
PWM
ECCPASE bit
Activity
Event
Shutdown
Event Occurs Shutdown
Event Clears PWM
Resumes
Normal PWM
Start of
PWM Period
PWM Period
Shutdown
PWM
ECCPASE bit
Activity
Event
Shutdown
Event Occurs Shutdown
Event Clears PWM
Resumes
Normal PWM
Start of
PWM Period
ECCPASE
Cleared by
Firmware
PWM Period
2004 Microchip Technology Inc. Advance Information DS39632A-page 161
PIC18F2455/2550/4455/4550
16.4.9 SETUP FOR PWM OPERA TIO N
The following steps should be taken when configuring
the ECCP module for PWM operation:
1. Configure the PWM pins, P1A and P1B (and
P1C and P1D, if used), as inputs by setting the
corresponding TRIS bits.
2. Set the PWM period by loading the PR2 register .
3. Configure the CCP1 module for the desired
PWM mode and configuration by loading the
CCP1CON register with the appropriate values:
• Select one of the available output
configurations and direction with the
P1M1:P1M0 bits.
• Select the polarities of the PWM output
signals with the CCP1M3:CCP1M0 bits.
4. Set the PWM du ty cycle by loading the CCPR1L
register and CCP1CON<5:4> bits.
5. For Half-Bridge Output mode, set the
dead-band delay by loading ECCP1DEL<6:0>
with the appropriate value.
6. If auto-shutdown operation is required, load the
ECCP1AS register:
• Select the auto -shutdown sources using the
ECCPAS2:ECCPAS0 bits.
• Select the shutdown states of the PWM
output pins using PSSAC1:PSSAC0 and
PSSBD1:PSSBD0 bits.
• Set the ECCPASE bit (ECCP1AS<7>).
• Config ure the c ompar ators us ing the CMCON
register.
• Configure the comparator inputs as analog
inputs.
7. If auto-restart operation is required, set the
PRSEN bit (ECCP1DEL<7>).
8. Configure and start TMR2:
• Clear the TMR2 interrupt flag bit by clearing
the TMR2IF bit (PIR1<1>).
• Set the TMR2 prescale value by loading the
T2CKPS bits (T2CON<1:0>).
• Enable Timer2 by setting the TMR2ON bit
(T2CON<2>).
9. Enable PWM outputs after a new PWM cycle
has started:
• W a it until TM Rn overflo ws (TM RnIF bit is se t).
• Enable the CCP1/P1A, P1B, P1C an d/or P1D
pin outputs by clearing the respective TRIS
bits.
• Clear the ECCPASE bit (ECCP1AS<7>).
16.4.10 EFFECTS OF A RESET
Both Power-on Reset and subsequen t Resets will force
all ports to Input mode and the CCP registers to their
Reset states.
This forces the Enhanced CCP module to reset to a
state compatible with the standard CCP module.
PIC18F2455/2550/4455/4550
DS39632A-page 162 Advance Information 2004 Microchip Technology Inc.
TABLE 16-3: REGISTERS ASSOCIATED WITH ECCP1 MODULE AND TIMER1 TO TIMER3
Name Bit 7 Bit 6 B it 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF page 51
RCON IPEN ——RI TO PD POR BOR page 52
IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP page 54
PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF page 54
PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE page 54
IPR2 OSCFIP CMIP —EEIP BCLIP LVDIP TMR3IP CCP2IP page 54
PIR2 OSCFIF CMIF —EEIF BCLIF LVDIF TMR3IF CCP2IF page 54
PIE2 OSCFIE CMIE —EEIE BCLIE LVDIE TMR3IE CCP2IE page 54
TRISB PORTB Data Direction Register page 54
TRISC PORTC Data Direction Register page 54
TRISD(1) PORTD Data Direction Register 54
TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register page 52
TMR 1H Holding Register for th e M ost Significa nt Byt e of the 16-bit TMR1 R egister page 52
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON page 52
TMR 2 Timer2 M odule Regis te r page 52
T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 page 52
PR2 Timer2 Period Register page 52
TMR3L Holding Register for the Least Significant Byte of the 16-bit TMR3 Register page 53
TMR 3H Holding Register for th e M ost Significa nt Byt e of the 16-bit TMR3 R egister page 53
T3CON RD16 T3ECCP1(1) T3CKPS1 T3CKPS0 T3CCP1(1) T3SYNC TMR3CS TMR3ON page 53
CCPR1L(2) Capture/Com par e/ PW M R egi s te r 1 (LSB) page 53
CCPR1H(2) Ca pt ur e/ Com par e/ PWM Regis te r 1 (M SB) page 53
CCP1CON P1M1(1) P1M0(1) DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 page 53
ECCP1AS(2) ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1(2) PSSBD0(2) page 53
ECCP1DEL PRSEN PDC6(2) PDC5(2) PDC4(2) PDC3(2) PDC2(2) PDC1(2) PDC0(2) page 53
Legend: — = unim pl emented , r ead as ‘0’. Sh aded cell s ar e not used durin g E CC P operation.
Note 1: These bits are avai labl e on 40/44-p in devices only.
2: Thes e bits or regist er s are unimp le m ented in 28-pi n devices; al wa y s m ai ntain t hese bit clear.
3: These bi ts are available on 40/44-p in and reserve d on 28-pin dev ic es .
2004 Microchip Technology Inc. Advance Information DS39632A-page 163
PIC18F2455/2550/4455/4550
17.0 UNIVERSAL SERIAL BUS
(USB)
This section describes the details of the USB
peripheral. Because of the very specific nature of the
module, knowledge of USB is expected. Some
high-level USB information is provided in
Section 17.10 “Overview of USB” only for appl ication
design reference . Designe rs are encouraged to refer to
the official specification published by the USB Imple-
menters Forum (USB-IF) for the latest information.
USB Specification Revision 2.0 is the most current
specification at th e time of publication of this document.
17.1 Overview of the USB Peripheral
The PIC18FX455/X550 device family contains a full
speed and low-speed compatible USB Serial Interface
Engine (SI E ) th at a llo ws fas t c om munic ati ons b etwee n
any USB host and the PIC® microcontroller. The SIE
can be interfaced directly to the USB, utilizing the
internal transceiver, or it can be connected through an
external transceiver. An internal 3.3V regulator is also
available to power the internal transceiver in 5V
applications.
Some sp ecial hardw are features ha ve been inc luded to
improve performance. Dual port memory in the
device’s data memory space (USB RAM) has been
supplied to share direct memory access between the
microc ontroller core and th e SIE. Buffe r descriptors a re
also provided, allowing users to freely program end-
point memory usage within the USB RAM space. A
Streaming Parallel Port has been provided to support
the uninterrupted transfer of large volumes of data,
such as isochronous data, to external memory buffers.
Figure 17-1 presents a general overview of the USB
peripheral and its features.
FIGURE 17-1: USB PERIPHERAL AND OPTIONS
OE(1)
1Kbyte
USB RAM
USB
SIE
USB Control VM(1)
VP(1)
RCV(1)
VMO(1)
VPO(1)
Transceiver
External
Transceiver
P
P
EN
3.3V Regulator
D+
D-
Internal Pull-ups
OE
VUSB External 3.3V
Supply(3)
FSEN
UPUEN
UTRDIS
USB Clock from the
Oscillator Module
and
VREGEN Optional
External
Pull-ups(2)
(Low
(Full
PIC18FX455/X550 Family
SPP7:SPP0
USB Bus
USB Bus
FS
Speed) Speed)
Note 1: This signal is only available if the internal transceiver is disabled (UTRDIS = 1).
2: The internal pull-up resistors should be disabled (UPUEN = 0) if external pull-up resistors are used.
3: Do not enable the internal regulator when using an external 3.3V supply.
Configuration
CK1SPP
CK2SPP
CSSPP
OESPP
PIC18F2455/2550/4455/4550
DS39632A-page 164 Advance Information 2004 Microchip Technology Inc.
17.2 USB Status and Control
The operation of the USB module is configured and
manage d throu gh three co ntro l regi sters. In addi tio n, a
tot al of 19 r egisters are used to m anage the a ctual USB
transactions. The registers are:
• USB Control register (UCON)
• USB Configuration register (UCFG)
• USB Transfer Status register (USTAT)
• USB Device Address register (UADDR)
• Frame Number registers (UFRMH :UFR ML)
• Endpoint Enable registers 0 through 15 (UEPn)
17.2.1 USB CONTROL REGISTER (UCON)
The USB Control register (Register 17-1) contains bits
needed to control the module behavior during
transfers. The register contains configuration bits that
control the follow i ng:
• Main USB Peripheral Enable
• Ping-Pong Buffer Pointer Reset
• Control of the Suspend mode
• Packet Transfer Disable
In addition, the USB Control register contains a status
bit, which is used to indicate the occurrence of a
single-ended zero on the bus.
The overall operation of the USB module is controlled
by the USBEN b it (UCON<3>). Setting this bit activates
the module and resets all of the PPBI bits in the Buffer
Descriptor Table to ‘0’. This bit also activates the
on-chip voltage regulator and connects internal pull-up
resisto rs, if they are e nabled. Thus, this bit can be used
as a soft attach/detach to the USB. Although all status
and confi guratio n bits are ignored when thi s bit is clea r ,
the module needs to be fully preconfigured prior to
setting thi s bit.
REGISTER 17-1: UCON: USB CONTROL REGISTER
U-0 R/W-0 R-x R/C-0 R/W-0 R/W-0 R/W-0 U-0
— PPBRST SE0 PKTDIS USBEN RESUME SUSPND —
bit 7 bit 0
bit 7 Unimplemented: Read as ‘0’
bit 6 PPBRST: Ping-Pong Buffers Reset bit
1 = Reset all ping-pong buffer pointers to the Even BD banks
0 = Ping-pong buffer pointers not being res et
bit 5 SE0: Live Single-Ended Zero Flag bit
1 = Single-ended zero active on the USB bus
0 = No single-ended zero detected
bit 4 PKTDIS: Packet Transfer Disable bit
1 = SIE token and packet processing disabled, automatically set when a SETUP token is
received
0 = SIE token and packet processing enabled
bit 3 USBEN: USB Module Enable bit
1 = USB module and supporting circuitry enabled (device attached)
0 = USB module and supporting circuitry disabled (device detached)
bit 2 RESUME: Resume Signaling Enable bit
1 = Resume signaling activated
0 = Resume signaling disabled
bit 1 SUSPND: Suspend USB bit
1 = USB module and supporting circuitry in Power Conserve mode, SIE clock inactive
0 = USB module and supporting circuitry in normal operation, SIE clock clocked at the
configured rate
bit 0 Unimplemented: Read as ‘0’
Legend: R = Readable bit W = Writable bit
C = Clearable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
2004 Microchip Technology Inc. Advance Information DS39632A-page 165
PIC18F2455/2550/4455/4550
The PPBRST bi t (UCON<6>) con trols the Re set st atus
when Double-Buffering mode (ping-pong buffering) is
used. Whe n the PPBRST bit is set, all pin g-pong buf fer
pointers are se t to the Even buf fers. PPB RST has to be
cleared by firmware. This bit is ignored in buffering
modes not using ping-pong buffering.
The PKTD IS bit (UCON<4> ) is a fla g indicat ing that th e
SIE has disabled packet transmission and reception.
This bit is set by the SIE when a SETUP token is
received to allow setup processing. This bit cannot be
set by the microcontroller, only cleared; clearing it
allows the SIE to continue transmission and/or
reception. Any pending events within the Buffer
Descriptor Table will still be available, indicated within
the USTAT register ’s FIFO buffer.
The RESUME bit (UCON<2>) allows the peripheral to
perform a remote wake-up by executing Resume sig-
naling. To generate a valid remote wake-up, firmware
must s et RESUME for 1 0 ms and then clear the bit. For
more information on Resume signaling, see
Sections 7.1.7.5, 11.9 and 11.4.4 in the USB 2.0
specification.
The SUSPND (UCON<1>) bit places the module and
supporting circuitry (i.e., voltage regulator) in a
low-po wer mode . The in put clock to the SIE is also dis-
abled. This bit should be set by the software in
response to an IDLEIF interrupt. It should be reset by
the microcontroller firmware after an ACTVIF interrupt
is obs erved. Whe n acti ve, the devi ce r emain s att ache d
to the bus but the transceiver outputs remain Idle.
The voltage on the VUSB pin may vary depending on
the value of this bit. Setting this bit before a IDLEIF
request will result in unpredictable bus behavior.
17.2.2 USB CONTROL REGISTER (UCON)
Prior to communicating over USB, the module’s
associated internal and/or external hardware must be
configured. Most of the configuration is performed with
the UCFG register (Register 17-2). The separate USB
voltage regulator (see Section 17.2.2.8 “Internal
Regulator”) is controlled through the configuration
registers.
The UFCG register contains most of the bits that
control the system level behavior of the USB module.
These include:
• Bus speed (full speed vs. low speed)
• On-chip pull-up resistor enable
• On-chip transceiver enable
• Ping-pong buffer usage
The UCFG register also contains two bits which aid in
module testing, debugging and USB certifications.
These bits control output enable state monitoring and
eye pattern generation.
17.2.2.1 Internal Transceiver
The USB peripheral has a built-in USB 2.0 full speed
and low-speed compliant transceiver internally con-
nected to the SIE. This feature is useful for low-cost
single chip applications. The UTRDIS bit (UCFG<3>)
controls the transceiver; it is enabled by default
(UTRDIS = 0). The FSEN bit (UCFG<2>) controls the
transceiver speed; setting the bit enables full speed
operation.
The on-chi p USB pull-up resistors are controlle d by the
UPUEN bit (UCFG<4>). They can only be selected
when the on-chip transceiver is enabled.
The USB specification requires 3.3V operation for
commun ica tio ns; ho wev er, the rest of t he ch ip may be
running at a higher voltage. Thus, the transceiver is
supplied power from a separate source, VUSB.
17.2.2. 2 External Transceive r
This module provides support for use with an off-chip
transceiver. The off-chip transceiver is intended for
applic ations w here phys ical co nditions dicta te the loc a-
tion of the transceiver to be away from the SIE. For
example, applications that require isolation from the
USB could use an external transceiver through some
isolation to the microcontroller’s SIE (Figure 17-2).
External transcei ver opera tion is enabled by setting the
UTRDIS bit.
FIGURE 17-2: TYPICAL EXTERNAL
TRANSCEIVER WITH
ISOLATION
Note: While in Suspend mode, a typical bus
powered USB device is limited to 500 µA
of current. This is the complete current
drawn by the PICmicro® device and its
supporting circuitry. Care should be ta ken
to assure minimum current draw when
device enters Suspend mode.
Note: The USB speed, transceiver and pull-up
should only be c onf igured during the mo d-
ule setup phase. It is not recomme nded to
switch these settings while the module is
enabled.
PIC®
Microcontroller
Transceiver
VPO
OE
Note: The above setting shows a simplified schematic
for a full speed configuration using an external
transceiver with isolation.
VP
RCV
VMO
VM
D+
D-
Isolation 1.5 kΩ
3.3V Derived
from USB
VUSB
VDD
VDD Isolated
from USB
PIC18F2455/2550/4455/4550
DS39632A-page 166 Advance Information 2004 Microchip Technology Inc.
REGISTER 17-2: UCFG: USB CONFIGURATION REGISTER
There are 6 signals from the module to communicate
with and control an external transceiver:
• VM: Input from the single-ended D- line
• VP: Input from the single-ended D+ line
• RCV: Input from the differential receiver
• VMO: Output to the differential line driver
• VPO: Output to the differential line driver
•OE
: Output enable
The VPO and VMO signa ls are outp uts from the SIE to
the external transceiver. The RCV signal is the output
from the external transceiver to the SIE; it represents
the differential signals from the serial bus translated
into a single pulse train. The VM and VP signals are
used to report conditions on the serial bus to the SIE
that can’t be captured with the RCV signal. The
combinations of states of these signals and their
interpretation are listed in Ta ble 17-1 and Table 17-2.
R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
UTEYE UOEMON(1) — UPUEN(2,3) UTRDIS(2) FSEN(2) PPB1 PPB0
bit 7 bit 0
bit 7 UTEYE: USB Eye Pattern Test Enable bit
1 = Eye pattern test enabled
0 = Eye pattern test disabled
bit 6 UOEMON: USB OE Monitor Enable bit(1)
1 =OE signal active; it indicates intervals during which the D+/D- lines are driving
0 =OE
signal inactive
bit 5 Unimplemented: Read as ‘0’
bit 4 UPUEN: USB On-Chip Pull-up Enable bit(2,3)
1 = On-chip pull-up enabled (pull-up on D+ with FSEN = 1 or D- with FSEN = 0)
0 = On-chip pull-up disabled
bit 3 UTRDIS: On-Chip Transceiver Disable bit(2)
1 = On-chip transceiver disabled; digital transceiver interface enabled
0 = On-ch ip transceiver active
bit 2 FSEN: Full Speed Enable bit(2)
1 = Full speed device: controls transceiver edge rates; requires input clock at 48 MHz
0 = Low-speed device: controls transceiver edge rates; requires input clock at 6 MHz
bit 1-0 PPB1:PPB0: Ping-Pong Buffers Configuration bits
11 = Reserved
10 = Even/Odd ping-pong buffers enabled for all endpoints
01 = Even/Odd ping-pong buffer enabled for OUT Endpoint 0
00 = Even/Odd ping-pong buffers disabled
Note 1: If UTRDIS is set, the OE signal will be active independent of the UOEMON bit
setting.
2: The FSEN, UPUEN and UTRDIS bits should never be changed while the USB
module is enabled. These values must be preconfigured prior to enabling the
module.
3: This bit is only valid when the on-chip transceiver is activ e (UTRDIS = 0); otherwise,
it is ignored.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
2004 Microchip Technology Inc. Advance Information DS39632A-page 167
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TABLE 17-1: DIFFERENTIAL OUTPUTS TO
TRANSCEIVER
TABLE 17-2: SINGLE-ENDED INPUTS
FROM TRANSCEIVER
The OE signal toggles the state of the external trans -
ceiver. This line is pulled low by the device to enable
the transmission of data from the SIE to an external
device.
17.2.2.3 Internal Pull-up Resistors
The PIC18FX455/X550 devices have built-in pull-up
resistors designed to meet the requirements for
low-speed and full speed USB. The UPUEN bit
(UCFG<4>) enables the internal pull-ups. Figure 17-1
shows the pull-ups and their control.
17.2.2.4 External Pull-up Resistors
External pull-up may also be used. The V USB pin may be
used to pull up D+ or D-. The pull-up resistor must be
1.5 kΩ (±5%), as required by the USB specifications.
Figure 17-3 shows an exa mple.
FIGURE 17-3: EXTER NAL CIRCUITRY
17.2.2.5 Ping-Pong Buffer Configuration
The usage of pin g-pong buff ers is configu red using the
PPB1:PPB0 bit s. Refe r to Section 17.4.4 “Ping-Pong
Buffering” for a complete explanation of the ping -pong
buffers.
17.2.2.6 USB Output Enable Monitor
The USB OE moni tor prov ides i ndica tion as to wheth er
the SIE is listening to the bus or actively driving the bus.
This is enabled by default when using an external
transceiver, or when UCFG<6> = 1.
The OE monitoring is useful for initial system
debugging, as well as scope triggering during eye
pattern generation tests.
17.2.2.7 Eye Pattern Test Enable
An automatic eye pattern test can be generated by the
module when the UCFG<6> bit is set. The eye pattern
output will be observable based on module settings,
meaning that the u ser is first responsible for config uring
the SIE cloc k se ttings, pul l-up resi st or and T ransce iv er
mode. In addition, the module has to be enabled.
Once UTEYE is set, the module emulates a switch from
a receive to transmit state and will start transmitting a
J-K-J-K bit sequence (K-J-K-J for full speed). The
sequence will be repeated indefinitely while the Eye
Pattern Te st mo de is ena ble d.
Note that this bit should never be set while the module
is connected to an actual USB system. This test mode
is intended for board verification to aid with USB certi-
ficatio n tests. It is intende d to show a syste m developer
the noise integrity of the USB signals which can be
affected by board traces, impedance mismatches and
proximity to other system components. It does not
properly test the transition from a receive to a transmit
state. Although the eye pattern is not meant to replace
the more complex USB certification test, it should aid
during first order system debugging.
17.2.2.8 Internal Regulator
The PIC18FX455/X550 devices have a built-in 3.3V reg-
ulator to provide power to the internal transceiver and
provide a source for the internal/external pull-ups. An
external 220 nF (±20%) capacitor is required for stability .
The regul ator is enabled b y default and can be disabled
through th e VREGEN confi guratio n bit. Wh en enab led,
the voltage is visible on pin VUSB. When the regulator
is disabled, a 3.3V source must be provided through
the VUSB pin for the internal transceiver. If the internal
transceiver is disabled, VUSB is not used.
VPO VMO Bus State
00 Single-Ended Zero
01 Dif fere nti al ‘0’
10 Dif fere nti al ‘1’
11 Illegal Condition
VP VM Bus State
00 Single-Ended Zero
01 Low Speed
10 High Speed
11 Error
PIC®
Microcontroller Host
Controller/HUB
VUSB
D+
D-
Note: The above setting shows a typical connection
for a full speed configuration using an on-chip
regulator and an external pull-up resistor.
1.5 kΩ
Note: The drive from VUSB is sufficient to only
drive an external pull-up in addition to the
internal transceiver.
Note 1: Do no t ena ble th e int ernal regul ator if an
external regulator is connected to VUSB.
2: VDD must be greater than VUSB at all
times, even with the regulator disabled.
PIC18F2455/2550/4455/4550
DS39632A-page 168 Advance Information 2004 Microchip Technology Inc.
17.2.3 USB STATUS REGISTER (USTAT)
The USB Status register reports the transaction status
within the SIE. When the SIE issues a USB transfer
comple te interrupt, USTAT should be rea d to determin e
the status of the transfer. USTAT contains the transfer
endpoint number, direction and ping-pong buffer
pointer value (if used).
The USTAT register is actually a read window into a
four-byte status FIFO maintained by the SIE; it allows
the microcontroller to process one transfer while the
SIE processes additional endpoints (Figure 17-4).
When the SIE completes using a buffer for reading or
writing data, it updates the USTAT register. If another
USB transfer is performed before a transaction
complete interrupt is serviced, the SIE will store the
status of the next transfer into the status FIFO.
Clearing the transfer complete flag bit, TRNIF, causes
the SIE to advance the FIFO. If the next data in the
FIFO holding register is valid, the SIE will immediately
reassert the interrupt. If no additional data is present,
TRNIF will remain clear; USTAT data will no longer be
reliable.
FIGURE 17-4: USTAT FIFO
REGISTER 17-3: USTAT: USB ST ATUS REGISTER
Note: The data in the USB S tatus register is valid
only when the TRNIF interrupt flag is
asserted.
Note: If an endpoint re quest is received while the
USTAT FIFO is full, the SIE will
automatically issue a NACK back to the
host.
Data Bus
USTAT fro m SIE
4-byte FIFO
for USTAT Clearing TRNIF
Advances FIFO
U-0 R-x R-x R-x R-x R-x R-x U-0
— ENDP3 ENDP2 ENDP1 ENDP0 DIR PPBI(1) —
bit 7 bit 0
bit 7 Unimplemented: Read as ‘0’
bit 6-3 ENDP4:ENDP0: Encoded nu mb er of last end point activ ity (repr esent s the nu mber of the BDT
updated by the last USB transfer)
1111 = Endpoint 15
1110 = Endpoint 14
....
0001 = Endpoint 1
0000 = Endpoint 0
bit 2 DIR: Last BD Direction Indicator bit
1 = The last transaction was an IN token
0 = The last transaction was an OUT or SETUP token
bit 1 PPBI: Ping-Po ng BD Pointer Indi ca tor bit(1)
1 = The last transaction was to the Odd B D bank
0 = The last transaction was to the Even BD bank
Note 1: This bit is only valid for endpoints with available Even and Odd BD registers.
bit 0 Unimplemented: Read as ‘0’
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
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17.2.4 USB ENDPOINT CONTROL
Each of the 16 possible bidirectional endpoints has its
own ind ependent control registe r , UEPn (wh ere ‘n’ rep-
resents the endpoint number). Each register has an
identical complement of control bits. The prototype is
shown in Register 17-4.
The EPHSHK bit (UEPn<4>) controls handshaking for
the end point; setting this bit enables USB handshaking.
Typically, this bit is always set except when using
isochro no us endpoint s .
The EPCONDIS bit (UEPn<3>) is used to enable or
disable USB control operations (SETUP) through the
endpoint. Clearing this bit enables SETUP transac-
tions; note that the corresponding EPINEN and
EPOUTEN bit must be set to enable IN and OUT
tran sa cti o ns . Fo r E n dp oi nt 0, t his bi t sh o ul d al w a ys be
cleared since the USB specifications identify
Endpoint 0 as the default control endpoint.
The EPOUTEN bit (U EPn<2>) is used to enable or dis -
able USB OUT transactions from the host. Setting this
bit enable s OUT transactions. Similarly, the EPINEN bit
(UEPn<1>) enables or disables USB IN transactions
from the host.
The EPSTALL bit (UEPn<0>) is used to indicate a
STAL L co nd iti o n f o r t h e e n dp oin t . If a STALL i s i s su ed
on a particular endpoint, the EPSTALL bit for that end-
point pair will be set by the SIE. This bit remains set
until it is cleared through firmware, or until the SIE is
reset.
REGISTER 17-4: UEPn: USB ENDPOINT n CONTROL REGISTER (UEP0 THROUGH UEP15)
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL(1)
bit 7 bit 0
bit 7-5 Unimplemented: Read as ‘0’
bit 4 EPHSHK: End poi nt Hands ha ke Enab le bit
1 = Endpoint handshake enabled
0 = Endpoint handshake disabled (typically used for isochronous endpoints)
bit 3 EPCONDIS: Bidirectional Endpoint Control bit
If EPOUTEN = 1 and EPINEN = 1:
1 = Disable Endpoint n from control transfers; only IN and OUT transfers allowed
0 = Enable Endpoint n for control (SETUP) transfers; IN and OUT transfers also allowed
bit 2 EPOUTEN: Endpoint Output Enable bit
1 = Endpoint n output enabled
0 = Endpoint n output disabled
bit 1 EPINEN: Endpoint Input Enable bit
1 = Endpoint n input enabled
0 = Endpoint n input disabled
bit 0 EPSTALL: Endpoint Stall Enable bit(1)
1 = Endpoint n is stalled
0 = Endpoint n is not stalled
Note 1: Valid only if Endpoint n is enabled; otherwise, the bit is ignored.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
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DS39632A-page 170 Advance Information 2004 Microchip Technology Inc.
17.2.5 USB ADDRESS REGISTER
(UADDR)
The Addres s register con tains the unique USB addres s
that the peripheral will decode when active. UADDR is
reset to 00h when a USB Reset is received, indicated
by URSTIF, or when a Reset is received from the
microcontroller. The USB address must be written by
the microcontroller during the USB setup phase
(enumeration) as part of the Chapter 9 firmware
support.
17.2.6 USB FRAME NUMBER REGISTERS
(UFRMH:UFRML)
The Frame Number registers contain the 11-bit frame
number. The low-order byte is contained in UFRML,
while the three high-order bits are contained in
UFRMH. The register pair is updated with the current
frame number whenever a SOF token is received. For
the microcontroller, these registers are read-only. The
Frame Number register is primarily used for
isochronous transfers.
17.3 USB RAM
USB dat a mo ves b etwe en the m icroc ontrol ler co re and
the SIE through a memory space known as the USB
RAM. This is a special dual port memory that is
mapped into the no rmal data memory sp ace in Ban ks 4
through 7 (400h to 7FFh), for a total of 1 Kbyte
(Figure 17-5).
Bank 4 (400h through 4FFh) is used specifically for
endpoint buffer control, while Banks 5 through 7 are
available for USB data. Depending on the type of
buffering being used, all but 8 bytes of Bank 4 may also
be available for use as USB buffer space.
Although USB RAM is available to the microcontroller
as data memory, the sections that are being accessed
by the SIE should not be accessed by the
microcontroller. A semaphore mechanism is used to
determine the access to a particular buffer at any given
time. This is discussed in Section 17.4.1.1 “Buffer
Ownership”.
FIGURE 17-5: IMPLEMENTATION OF
USB RAM IN DATA
MEMORY SPACE
400h
4FFh
7FFh
500h
USB Data or
Buffer Descriptors,
USB Data or User Data
User Data
User Data
Unused
SFRs
3FFh
000h
F60h
FFFh
Banks 0
Banks 4
Bank15
(USB RAM)
F00h
Banks 8
800h
to 14
to 3
to 7
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17.4 Buffer Descriptors and the Buffer
Descriptor Table
The registers in Bank 4 are used specifically for end-
point buffer control in a structure known as the Buffer
Descriptor Table (BDT). This provides a flexible method
for users to construct and control endpoint buffers of
various lengths and configuration.
The BDT i s composed of Buf fer Descript ors (BD) which
are used to define and control the actual buffers in the
USB RAM space. Each BD, in turn, consists of four reg-
isters, where n represents one of the 64 possible BDs
(range of 0 to 63):
• BDnSTAT: BD Status register
• BDnCNT: BD Byte Count register
• BDnADRL: BD Address Low register
• BDnADRH: BD Address High register
BDs alwa ys occu r as a four-byt e block in
the sequence,
BDnST AT:BDnCNT:BDnADRL:BDnADRH.
The address
of BDnSTAT is always an offset of (4n – 1) (in hexa-
decimal) from 400h, with n being the buffer descriptor
number.
Depending on the buffering configuration used
(Section 17.4.4 “Pin g-Pong Buffering”), there are up
to 32, 33 o r 64 sets of buffer d escriptors. At a mi nimum,
the BDT mu st b e a t least 8 byt es lon g. This i s b ec aus e
the USB specification mandates that every device must
have Endpoint 0 with both input and output for initial
setup. Depending on the endpoint and buffering
configuration, the BDT can be as long as 256 bytes.
Although they can be thought of as special function
control registers, the Buffer Descriptor Status and
Address registers are not hardware mapped, as con-
ventional microcontroller SFRs in Bank 15 are. If the
endpoint corresponding to a particular BD is not
enabled, its registers are not used. Instead of appear-
ing as unimplemented addresses, however, they
appear as available RAM. Only when an endpoint is
enabled by setting the UEPn<1> bit does the memory
at thos e addre sses beco me fun ction al as BD regis ters.
As with a ny ad dress in the dat a mem ory sp ace , the BD
registers have an indeterminate value on any device
Reset.
An example of a BD for a 40-byte buffer, starting at
500h, is shown in Figure 17-6. A particular set of BD
register s is o nly vali d if the cor respon ding endp oint has
been e nabled usi ng the UEPn re gister. All BD regis ters
are available in USB RAM. The BD for each endpoint
should be set up prior to enabling the endpoint.
17.4.1 BD STATUS AND CONFIGURATION
Buffer descriptors not only define the size of an end-
point buffer, but also determine its configuration and
control. Most of the configuration is done with the BD
Status register, BDnSTAT (or more generically,
BDSTAT). Each BD has its own unique and
correspondingly numbered BDSTAT register.
FIGURE 17-6: EXAMPLE OF A BUFFER
DESCRIPTOR
Unlike other control registers, the bit configuration for
the BDSTA T re gister is c ontext sensiti ve. There are two
distinct configurations, depending on whether the
microc ontroll er or the USB module is modif ying the BD
and buf f er at a p artic ular time . Only three b it defi nitions
are shared between the two.
17.4.1.1 Buffer Ownership
Because the buf fers and the ir BDs are shar ed between
the CPU and the USB module, a simple semaphore
mechanism is used to distinguish which is allowed to
update the BD and associated buffers in memory.
This is done by using the UOWN bit (BDSTAT<7>) as
a semaphore to distinguish which is allowed to update
the BD and associated bu ffers in memory. UOWN is the
only bit that is shared between the two configurations
of BDSTAT.
When UOWN is clear, the BD entry is “owned” by the
microcontroller core. When the UOWN bit is set, the BD
entry and the buffer memory are “owned” by the USB
peripheral; the core should not modify the BD or its
corresponding data buffer during this time. Note that
the microcontroller core can still read BDSTAT while
the SIE owns the buffer and vice versa.
The buffer descriptors have a different meaning based
on the source of the register update. Prior to placing
ownership with the USB peripheral, the user can con-
figure the bas ic oper ation of the perip hera l thro ugh the
BDSTAT bits. During this time, the byte count and
buffer location registers can also be set.
When U OW N is s et, the us er c an no lo nge r de pend on
the valu es that were writ ten to the BDs. Fr om this point,
the SIE updates the BDs as n ece ss ary, overwriti ng th e
original BD v alues. Th e BDSTAT register is upd ated b y
the SIE with the token PID and the transfer count,
BDnCNT, is updated.
400h
USB Data
Buffer
Buffer
BD0STAT
BD0CNT
BD0ADRL
BD0ADRH
401h
402h
403h
500h
53Fh
Descriptor
Note: Memory regions not to scale.
40h
00h
05h Starting
Size of Block
(xxh)
RegistersAddress Contents
Address
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The BDnSTAT byte of the BDT should always be the
last byte updated when preparing to arm an endpoint.
The SIE will clear the UOWN bit when a transaction
has co mplet ed. The on ly excep tion to th is is w hen KEN
is enabled and/or BSTALL is enabled.
No ha rdware mecha nism e xists t o bloc k acce ss when
the UOWN bit is set. Thus, unexpected behavior can
occur if the microcontroller attempts to modify memory
when the SIE owns it. Similarly, reading such memory
may produce inaccurate data until the USB peripheral
returns ownership to the microcontroller.
17.4.1.2 BDSTAT Register (CPU Mode)
When UOWN = 0, the microcontroller core owns the
BD. At this point, the other seven bits of the register
take on control functions.
The K eep Enable bit, KEN (BDSTA T<5>), det ermines if
a BD st ays enabl ed. If the bit is set, onc e the UOWN b it
is set, it will remain owned by the SIE independent of
the endpoint activity. This prevents the USTAT FIFO
from being updated, as well as the transaction com-
plete in terrupt from being set f or the endp oint. This fea-
ture should only be enabled when the Streaming
Parallel Port is se lected as the data I/O channel instead
of USB RAM.
The Address Increment Disable bit, INCDIS
(BDSTAT<4>), controls the SIE’s automatic address
increment function. Setting INCDIS disables the
auto-increment of the buffer address by the SIE for
each byte transmitted or received. This feature should
only be enabled when using the Streaming Parallel
Port, where each data byte is processed to or from the
same memory locati on.
The Data Toggle Sync Enable bit, DTSEN
(BDSTAT<3>), controls data toggle parity checking.
Setting D TSEN enables dat a toggle sy nchronization b y
the SIE; whe n enabled, it che cks the dat a pack et’s p ar-
ity a ga i ns t the v a lu e of D TS ( BDS TAT < 6> ). I f a pa cke t
arri ves with an in correc t synchr onizati on, th e data wi ll
essentially be ignored; it will not be written to the USB
RAM and the USB transfer complete interrupt flag will
not be set. The SIE will send an ACK token b ack to the
host to Acknowledge receipt, however. The effects of
the DTSEN bit on the SIE are summarized in
Table 17-3.
The Buffer Stall bit, BSTALL (BDSTAT<2>), provides
support for control transfers, usually one-time stalls on
Endpoint 0. It also provides support for the
SET_FEATURE/CLEAR_FEATURE commands speci-
fied in Chapter 9 of the USB specification, typically
continuous STALLs to any endpoint other than the
default control endpoint.
The BSTALL bit enables buffer stalls. Setting BSTALL
causes the SIE to re turn a STALL token to the hos t if a
received token would use the BD in that location. The
EPSTALL bit in the corresponding UEPn control regis-
ter is set and a STALL interrupt is generated when a
ST ALL is issued to the host. The UOWN bit remains set
and the BDs are n ot ch anged unle ss a SETUP token is
received. In this case, the STALL condition is cleared
and the ownership of the BD is returned to the
microcontroller core.
The BD9:BD8 bits (BDSTAT<1:0>) store the two most
significant digit s of the SIE byte count; the lower 8 digit s
are stored in the corresponding BDCNT register. See
Section 17.4.2 “BD Byte Count” for more
information.
TABLE 17-3: EFFECT OF DTSEN BIT ON ODD/EVEN (DATA0/DATA1) PACKET RECEPTION
OUT Packet
from Host
BDnSTAT Settings Device Response after Receiving Packet
DTSEN DTS Handshake UOWN TRNIF BDSTAT and USTAT Status
DATA0 10ACK 01 Updated
DATA1 10ACK 10 Not Updated
DATA0 11ACK 01 Updated
DATA1 11ACK 10 Not Updated
Either 0xACK 01 Updated
Either, with error xxNACK 10 Not Updated
Legend: x = don’t care
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REGISTER 17-5: BDnSTAT: BUFFER DESCRIPTOR n STATUS REGISTER (BD0STAT THROUGH
BD63STAT), CPU MODE (DATA IS WRITTEN TO THE SIDE)
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
UOWN(1) DTS(2) KEN INCDIS DTSEN BSTALL BC9 BC8
bit 7 bit 0
bit 7 UOWN: USB Own bit(1)
0 = The microcontroller core owns the BD and its corresponding buffer
bit 6 DTS: Data Toggle Synchronization bit(2)
1 = Data 1 packet
0 = Data 0 packet
bit 5 KEN: BD Keep Enable bit
1 = USB will keep the BD indefinitely once UOWN is set (required for SPP endpoint
configuration)
0 = USB will hand back the BD once a token has been processed
bit 4 INCDIS: Address Increment Disable bit
1 = Address increment disabled (required for SPP endpoint configuration)
0 = Address increment enabled
bit 3 DTSEN: Data Toggle Synchronization Enable bit
1 = Data toggle synchronization is enabled; data packets with incorrect Sync value will be
ignored
0 = No data toggle synchronization is performed
bit 2 BSTALL: Buffer Stall Enable bit
1 = Buf fer st all enabled ; ST AL L handshak e issued if a token is receiv ed that woul d use the BD
in the given location (UOWN bit remains set, BD value is unchanged)
0 = Buffer stall disabled
bit 1-0 BC9:BC8: Byte Count bits 9 and 8
The byte count bits represent the number of bytes that will be transmitted for an IN token or
received during an OUT token. Together with BC<7:0>, the valid byte counts are 0-1023.
Note 1: This bit must be initialized by the user to the desired value prior to enabling the USB
module.
2: This bit is ig nore d unless DTSEN = 1.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
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DS39632A-page 174 Advance Information 2004 Microchip Technology Inc.
17.4.1.3 BDSTAT Register (SIE Mode)
When th e BD a nd it s buf fer ar e owned b y the SI E, most
of the bits in BDS TAT take on a diffe re nt mean ing .T he
configuration is shown in Register 17-6. Once UOWN
is set, any data or control settings previously written
there by the user will be overwritten with data from the
SIE.
The BDSTAT register is updated by the SIE with the
token Packet Identifier (PID), which is stored in
BDSTA T<5:3>. The transfer c ount in the corresponding
BDCNT register is updated; values that overflow the
8-bit register carry over to the two most significant
digit s of the cou nt, sto red in BDS TAT<1:0>.
17.4.2 BD BYTE COUNT
The byte count represents the total number of bytes
that will be tran smitted during an IN transfer . After an IN
transfer, the SIE will return the n umb er of byt es s en t to
the host.
For an OUT transfer, the byte count represents the
maximum number of bytes that can be received and
stored in USB RAM. After an OUT tran sfer, the SIE will
return the actual number of bytes received. If the num-
ber of bytes received exceeds the corresponding byte
count, the data packet will be rejected and a NACK
handshake will be generated. When this happens, the
byte count will not be updated.
The 10 -bit by te coun t is di stribu ted ov er two re giste rs.
The lower 8 bits of the count reside in the BDCNT reg-
ister. The upper two bits reside in BDSTAT<1:0>. This
represents a valid byte range of 0 to 1023.
17.4.3 BD ADDRESS VALIDATION
The BD Address regis ter p a ir co nt a in the st a rtin g RAM
address location fo r the corre spond ing end point bu ffe r.
For an endpoint starting location to be valid, it must fall
in the rang e of the U SB RAM, 40 0h to 7FFh . No mec h-
anism is available in hardware to validate the BD
address.
If the value of the BD address does not point to an
address in the USB RAM, or if it points to an address
within ano ther endpoi nt’s buffer, data is li kely to be los t
or overwritten. Similarly, overlapping a receive buffer
(OUT endpoint) with a BD location in use can yield
unexpected results. When developing USB applica-
tions, the user may want to consider the inclusion of
software -based address validation in their code.
REGISTER 17-6: BDnSTAT: BUFFER DESCRIPTOR n STATUS REGISTER (BD0STAT THROUGH
BD63STAT), SIE MODE (DATA RETURNED BY THE SIDE TO THE
MICROCONTROLLER)
R/W-x U-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
UOWN — PID3 PID2 PID1 PID0 BC9 BC8
bit 7 bit 0
bit 7 UOWN: USB Own bit
1 = The SIE owns the BD and its corresponding buffer
bit 6 Reserved: Not written by the SIE
bit 5-2 PID3:PID0: Packet Identifier bits
The received token PID value of the last transfer (IN, OUT or SETUP transactions only).
bit 1-0 BC9:BC8: Byte Count bits 9 and 8
These bits are updated by the SIE to reflect the actual number of bytes received on an OUT
transfer and the actual number of bytes transmitted on an IN transfer.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
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17.4.4 PING-PONG BUFFERIN G
An endpoi nt is defined to have a ping-po ng buffer w hen
it has tw o sets of BD entries: one s et for an Even tran s-
fer and one set for an Odd transfer. This allows the
CPU to pr ocess one BD while the SIE is processi ng the
other BD. Double-buffering BDs in this way allows for
maximum thr oughput to/fr om the USB.
The USB module supports three modes of operation:
• No ping-p ong suppo rt
• Ping-pong buffer support for OUT Endpoint 0 only
• Ping-pong buffer support for all endpoints
The ping-pong buffer settings are configured using the
PPB1:PPB0 bits in the UCFG register.
The USB module keeps track of the ping-pong pointer
individually for each endpoint. All pointers are initially
reset to the Even BD when the module is enabled. After
the completion of a transaction (UOWN cleared by the
SIE), the pointer is toggled to the Odd BD. After the
completion of the next transaction, the pointer is
toggled back to the Even BD and so on.
The Even /Odd s ta tus of the las t trans actio n is st ored i n
the PPBI bit of the USTAT register. The user can reset
all ping-pong pointers to Even using the PPBRST bit.
Figure 17-7 shows the three different modes of
operation and how USB RAM is filled with the BDs.
BDs have a fixed relationship to a particular endpoint,
dependi ng on the bufferi ng configuration . The mappin g
of BDs to end point s is det ailed in Table 17-4. This rela-
tionship also means that gaps may occur in the BDT if
endpoints are not enabled contiguously. This theoreti-
cally means that the BDs for disabled endpoints could
be used as buffer space. In practice, users should
avoid using such spaces in the BDT unless a method
of validating BD addresses is implemented.
FIGURE 17-7: BUFFER DESCRIPTOR TABLE MAPPING FOR BUFFERING MODES
EP1 IN Even
EP1 OUT Even
EP1 OUT Odd
EP1 IN Odd
Descriptor
Descriptor
Descriptor
Descriptor
EP1 IN Descriptor
EP15 IN
EP1 OUT
EP0 OUT
PPB1:PPB0 = 00
EP0 IN
EP1 IN
No Ping-Pong Buffers
EP15 IN Descriptor
EP0 IN Descriptor
EP0 OUT Even
PPB1:PPB0 = 01
EP0 OUT Odd
EP1 OUT Descriptor
Ping-Pong Buffer on EP0 OUT
EP15 IN Odd
EP0 IN Even
EP0 OUT Even
PPB1:PPB0 = 10
EP0 OUT Odd
EP0 IN Odd
Ping-Pong Buffers on all EPs
Descriptor
Descriptor
Descriptor
Descriptor
Descriptor
Descriptor
Descriptor
Descriptor
Descriptor
Descriptor
Descriptor
Descriptor
400h
4FFh 4FFh 4FFh
400h 400h
47Fh
483h
Available
as
Data RAM Available
as
Data RAM
Maximum Memory Used: 128 bytes
Maximum BDs: 32 (BD0 to BD31) Maximum Memory Used: 132 bytes
Maximum BDs : 33 (BD0 to BD32) Maximum Memory Used: 256 bytes
Maximum BDs : 64 (BD0 to BD63)
Note: Memory area not shown to scale.
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TABLE 17-4: ASSIGNMENT OF BUFFER DESCRIPTORS FOR THE DIFFERENT
BUFFERING MODES
TABLE 17-5: SUMMARY OF USB BUFFER DESCRIPTOR TABLE REGISTERS
Endpoint
BDs Assigned to Endpoint
Mode 0
(No Ping-Pong) Mode 1
(Ping-Pong on EP0 OUT) Mode 2
(Ping-Pong on all EPs)
Out In Out In Out In
0 0 1 0 (E), 1 (O) 2 0 (E), 1 (O) 2 (E), 3 (O)
1 2 3 3 4 4 (E), 5 (O) 6 (E), 7 (O)
2 4 5 5 6 8 (E), 9 (O) 10 (E), 11 (O)
3 6 7 7 8 12 (E), 13 (O) 14 (E), 15 (O)
4 8 9 9 10 16 (E), 17 (O) 18 (E), 19 (O)
5 10 11 11 1 2 20 (E), 21 (O) 22 (E), 23 (O)
6 12 13 13 14 24 (E), 25 (O) 26 (E), 27 (O)
7 14 15 15 16 28 (E), 29 (O) 30 (E), 31 (O)
8 16 17 17 18 32 (E), 33 (O) 34 (E), 35 (O)
9 18 19 19 20 36 (E), 37 (O) 38 (E), 39 (O)
10 20 21 21 22 40 (E), 41 (O) 42 (E), 43 (O)
11 22 23 23 24 44 (E), 45 (O) 46 (E), 47 (O)
12 24 25 25 26 48 (E), 49 (O) 50 (E), 51 (O)
13 26 27 27 28 52 (E), 53 (O) 54 (E), 55 (O)
14 28 29 29 30 56 (E), 57 (O) 58 (E), 59 (O)
15 30 31 31 32 60 (E), 61 (O) 62 (E), 63 (O)
Legend: (E) = Even transaction buffer, (O) = Odd transaction buffer
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
BDnSTAT(1) UOWN DTS PID3(2)
KEN(3) PID2(2)
INCDIS(3) PID1(2)
DTSEN(3) PID0(2)
BSTALL(3) BC9 BC8
BDnCNT(1) Byte Count
BDnADRL(1) Buffer Address Low
BDnADRH(1) Buffer Address High
Note 1: For buffer descriptor registers, n may have a value of 0 to 63. For the sake of brevity, all 64 registers are
shown as one generic prototype. All registers have indeterminate Reset values (xxxx xxxx).
2: Bits 5 throug h 2 of t he BD nSTAT register ar e used by the SIE to re turn PID3:PI D0 v alues onc e the registe r
is turned over to the SIE (UOWN bit is set). Once the registers have been under SIE control, the values
written for KEN, INCDIS, DTSEN and BSTALL are no longer valid.
3: Prior to turning the buffer descriptor over to the SIE (UOWN bit is cleared), bits 5 through 2 of the
BDnSTAT register are used to configure the KEN, INCDIS, DTSEN and BSTALL settings.
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17.5 USB Interrupts
The USB module can generate multiple interrupt con-
ditions . To acc ommodat e all of these inter rupt s ources ,
the module is provided with its own interrupt logic
structure, similar to that of the microcontroller. USB
interrupts are enabled with one set of control registers
and trapped with a separate set of flag registers. All
sources are funneled into a single USB interrupt
request, USBIF (PIR2<5>), in the microcontroller’s
inter rupt log ic .
Figure 17-8 shows the interrupt logic for the USB
module. There are two layers of interrupt registers in
the USB mo dul e. Th e top lev el c ons is t s of ov era ll US B
status interrupts; these are enabled and flagged in the
UIE and UIR registers, respectively. The second level
consists of USB error conditions, which are enabled
and flagged in the UEIR and UEIE registers. An
interrupt condition in any of these triggers a USB Error
Interrupt Flag (UERRIF) in the top level.
Interrupts may be us ed to trap routine ev ents in a USB
transaction. Figure 17-9 shows some common events
within a USB frame and their corresponding interrupts.
FIGURE 17-8: USB INTERRUPT LOGIC FUNNEL
FIGURE 17-9: EXAMPLE OF A USB TRANSACTION AND INTERRUPT EVENTS
BTSEF
BTSEE
BTOEF
BTOEE
DFN8EF
DFN8EE
CRC16EF
CRC16EE
CRC5EF
CRC5EE
PIDEF
PIDEE
SOFIF
SOFIE
TRNIF
TRNIE
IDLEIF
IDLEIE
STALLIF
STALLIE
ACTVIF
ACTVIE
URSTIF
URSTIE
UERRIF
UERRIE
USBIF
Second Level USB Interrupts
(USB Error Conditions)
UEIR (Flag) and UEIE (Enable) Registers
Top Level USB Interrupts
(USB Status Interrupts)
UIR (Flag) and UIE (Enable) Registers
USB Reset
SOFRESET SETUP DATA STATUS SOF
SETUPToken Data ACK
OUT Token Empty Data ACK
START-OF-FRAME
IN Token Data ACK
SOFIF
URSTIF
1 ms Frame
Differential Data
From Host Fr om Host To Host
From Host To Host From Host
From Host From Host To Host
Transaction
Control Transfer(1)
Transaction
Complete
Note 1: The control transfer shown here is only an example showing events that can occur for every transaction. Typical control transfers
will spread across multiple frames.
Set TRNIF
Set TRNIF
Set TRNIF
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17.5.1 USB INTERRUPT STATUS
REGISTER (UIR)
The USB Interrupt Status register (Register 17-7) con-
tains the flag bits for each of the USB status interrupt
sources. Each of these sources has a corresponding
interrupt enable bit in the UIE register. All of the USB
status flags are ORed together to generate the USBIF
interrupt flag for the microcontroller’s interrupt funnel.
Once an interrupt bit has been set by the SIE, it must
be cleared by software by writing a ‘0’. The flag bits
can al so be se t in sof tware , whic h can ai d in fir mware
debugging.
REGISTER 17-7: UIR: USB INTERRUPT STATUS REGISTER
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R/W-0
— SOFIF STALLIF IDLEIF(1) TRNIF(2) ACTVIF(3) UERRIF(4) URSTIF
bit 7 bit 0
bit 7 Unimplemented: Read as ‘0’
bit 6 SOFIF: START-OF-FRAME Token Interrupt bit
1 = A START-OF-FRAME token received by the SIE
0 = No START-OF-FRAME token received by the SIE
bit 5 STALLIF: A STALL Handshake Interrupt bit
1 = A STALL handshake was sent by the SIE
0 = A STALL handshake has not been sent
bit 4 IDLEIF: Idle Detect Interrupt bit(1)
1 = Idle condition detected (constant Idle state of 3 ms or more)
0 = No Idle condition detected
bit 3 TRNIF: Transaction Complete Interrupt bit(2)
1 = Processing of pending transaction is complete; read USTAT register for endpoint
information
0 = Processing of pending transaction is not complete or no transaction is pending
bit 2 ACTVIF: Bus Activity Detect Interrupt bit(3)
1 = Activity on the D+/D- lines was detected
0 = No activity detected on the D+/D- lines
bit 1 UERRIF: USB Error Condition Interrupt bit(4)
1 = An unmasked error condition has occurred
0 = No unmasked error condition has occurred
bit 0 URSTIF: USB Reset Interrupt bit
1 = Valid USB Reset occurred; 00h is loaded into UADDR register
0 = No USB Reset has occurred
Note 1: Once an Idle state is detected, the user may want to place the USB module in
Suspend mode.
2: Clearing this bit will cause the USTAT FIFO to advan ce (v alid onl y for IN, OUT and
SETUP tokens).
3: This bit is typically unmasked only following the detection of a UIDLE interrupt
event.
4: Only error c ondit ions en abled through the UEIE regi ster will set thi s bit. Th e bit is a
status bit only and cannot be set or cleared by the user.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
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17.5.2 USB INTERRUPT ENABLE
REGISTER (UIE)
The USB Interrupt Enable register (Register 17-8)
contains the enable bits for the USB status interrupt
sources. Setting any of these bits will enable the
respective interrupt source in the UIR register.
The values in this register only affect the propagation
of an interrupt condition to the microcontroller’s inter-
rupt logic. The flag bits are still set by their interrupt
conditions, allowing them to be polled and serviced
without actually generating an interrupt.
REGISTER 17-8: UIE: USB INTERRUPT ENABLE REGISTER
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— SOFIE STALLIE IDLEIE TRNIE ACTVIE UERRIE URSTIE
bit 7 bit 0
bit 7 Unimplemented: Read as ‘0’
bit 6 SOFIE: START-OF-FRAME Token Interrupt Enable bit
1 = START-OF-FRAME token interrupt enabled
0 = START-OF-FRAME token interrupt disabled
bit 5 STALLIE: STALL Handshake Interrupt Enable bit
1 = STALL interrupt enabled
0 = STALL interrupt disabled
bit 4 IDLEIE: Idle Detect Interrupt Enable bit
1 = Idle detect interrupt enabled
0 = Idle detect interrupt disabled
bit 3 TRNIE: Transaction Complete Interrupt Enable bit
1 = Transaction interrupt enabled
0 = Transaction interrupt disabled
bit 2 ACTVIE: Bus Activity Detect Interrupt Enable bit
1 = Bus activity detect interrupt enabled
0 = Bus activity detect interrupt disabled
bit 1 UERRIE: USB Error Interrupt Enable bit
1 = USB error interrupt enabled
0 = USB error interrupt disabled
bit 0 URSTIE: USB Reset Interrupt Enable bit
1 = USB Reset interrupt enabled
0 = USB Reset interrupt disabled
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
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17.5.3 USB ERROR INTERRUPT STATUS
REGISTER (UEIR)
The USB Error I nterrupt Stat us registe r (Regi ster 17-9)
contains the flag bits for each of the error sources
within the USB peripheral. Each of these sources is
controlled by a corresponding interrupt enable bit in
the UEIE register. All of the USB error flags are ORed
together to generate the USB Error Interrupt Flag
(UERRIF ) at the top level of the interrup t logic .
Each error bit is set as soon as the error condition is
detected. Thus, the interrupt will typically not
correspond with the end of a token being processed.
Once an interrupt bit has been set by the SIE, it must
be cleared by software by writing a ‘0’.
REGISTER 17-9: UEIR: USB ERROR INTERRUPT STATUS REGISTER
R/C-0 U-0 U-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0
BTSEF —— BTOEF DFN8EF CRC16EF CRCEF5 PIDEF
bit 7 bit 0
bit 7 BTSEF: Bit Stuff Error Flag bit
1 = A bit stuff error has been detected
0 = No bit stuff error
bit 6-5 Unimplemented: Read as ‘0’
bit 4 BTOEF: Bus Turnaround Time-out Error Flag bit
1 = Bus turnaround time-out has occurred (more than 16 bit times of Idle from previous EOP
elapsed)
0 = No bus turnaround time-out
bit 3 DFN8EF: Data Fi eld Size Erro r Flag bit
1 = The data field was not an integral number of bytes
0 = The data field was an integral number of bytes
bit 2 CRC16EF: CRC16 Fail ure Fla g bit
1 = The CRC16 failed
0 = The CRC16 passed
bit 1 CRC5EF: CRC5 Host Error Flag bit
1 = The token packet was rejected due to a CRC5 error
0 = The token packet was accepted
bit 0 PIDEF: PID Check Fa ilure Flag bit
1 = PID check failed
0 = PID check passed
Legend:
R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
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17.5.4 USB ERROR INTERRUPT ENABLE
REGISTER (UEIE)
The USB Error Interrupt Enable register
(Register 17-10) contains the enable bits for each of
the USB error interrupt sources. Setting any of these
bits will enable the respective error interrupt source in
the UEIR register to propagate into the UERR bit at
the top level of the interrupt logic.
As with the UIE register, the enable bits only affect the
propagation of an interrupt condition to the microcon-
troller’s interrupt logi c. The fl ag b its are st il l s et by their
interrupt conditions, allowing them to be polled and
serviced with actually generating an interrupt.
REGISTER 17-10: UEIE: USB ERROR INTERRUPT ENABLE REGISTER
R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
BTSEE —— BTOEE DFN8EE CRC16EE CRC5EE PIDEE
bit 7 bit 0
bit 7 BTSEE: Bit Stuff Error Interrupt Enable bit
1 = Bit stuff error interrupt enabled
0 = Bit stuff error interrupt disabled
bit 6-5 Unimplemented: Read as ‘0’
bit 4 BTOEE: Bus Turnaround Time-out Error Interrupt Enable bit
1 = Bus turnaround time-out error interrupt enabled
0 = Bus turnaround time-out error interrupt disabled
bit 3 DFN8EE: Data Field Size Error Interrupt Enable bit
1 = Data field size error interrupt enabled
0 = Data field size error interrupt disabled
bit 2 CRC16EE: CRC16 Failure Interrupt Enable bit
1 = CRC16 failure interrupt enabled
0 = CRC16 failure interrupt disabled
bit 1 CRC5EE: CRC5 Host Error Interrupt Enable bit
1 = CRC5 host error interrupt enabled
0 = CRC5 host error interrupt disabled
bit 0 PIDEE: PID Check Failure Interrupt Enable bit
1 = PID check failure interrupt enabled
0 = PID check failure interrupt disabled
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
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17.6 USB Power Modes
Many USB applicat ions wi ll likely have sev eral dif ferent
sets of power requirements and configuration. The
most common power modes encountered are Bus
Power Only, Self-Power Only and Dual Power with
Self-Power Dominance. The most common cases are
presented here.
17.6.1 BUS POWER ONLY
In Bus Power Only mode, all power for the application
is drawn from the USB (Figure 17-10). This is
effectively the simplest power method for the device.
FIGURE 17-10: BUS POWER ONLY
17.6.2 SELF-POWER ONLY
In Self-Power Only mode, the USB application provides
its own power, with very little power being pulled from
the USB. Fi gure 17-11 shows an exa mple. Note that a n
attach indication is added to indicate when the USB
has been connected .
FIGURE 17-11: SELF-POWER ONLY
17.6.3 DUAL POWER WITH SELF-POWER
DOMINANCE
Some applications may require a dual power option.
This allows the application to use internal power prima-
rily, but switch to power from the USB when no int ernal
power is available. Figure 17-12 shows a simple Dual
Power with Self-Power Dominance example, which
automatically switches between Self-Power Only and
USB Bus Power Only modes.
FIGURE 17-12: DUAL POWER EXAMPLE
17.7 Streaming Paral lel Port
The S t reaming Paralle l Port (SPP) is an alternate rou te
option for data besides USB RAM. Using the SPP, an
endpoint can be configured to send data to or receive
data dire ctl y from extern al hardware.
This methodology presents design possibilities where
the microcontroller acts as a data manager, allowing
the SPP to p ass la rge block s of dat a with out the mic ro-
controller actually processing it. An application
example might include a data acquisition system,
where da t a i s st rea med from an e xte rna l FIFO th roug h
USB to the host computer. In this case, endpoint
control i s manage d by the mi crocontrol ler and raw data
movement is processed externally.
The SPP is enabled as a USB endpoint port through
the associated endp oint buffer descriptor . The endpoint
must be enabled as follows:
1. Set BDnADRL:BDnADRH to point to FFFFh.
2. Set the KEN bit (BDnSTAT<5>) to let SIE keep
control of the buffer.
3. Set the INCDIS bit (BDnSTAT<4>) to disable
automat ic add res s inc rem ent .
Refer to Section 18.0 “Streaming Parallel Port” for
more information about the SPP.
VDD
VUSB
VSS
VBUS
~5V
VDD
VUSB
VSS
VSELF
~5V
I/O pin
Attach Sense
100 kΩ
VBUS
~5V 100 kΩ
Note: Users should keep in mind the limits for
devices drawing power from the USB.
According to USB Specification 2.0, this
cannot exceed 100 mA per low-power
device , or 500 mA per high-pow er device .
Note: If an endpoint is configured to use the
SPP, the SPP modu le must also be config-
ured to use the USB module. Otherwise,
unexpected operation may occur.
VDD
VUSB
I/O pin
VSS
Attac h Se n se
VBUS
VSELF
100 kΩ
~5V
~5V
100 kΩ
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17.8 Oscillator
The USB module has specific clock requirements. For
full spe ed ope ration, the clock sourc e must b e 48 MHz.
Even so, the mic rocontroller core and oth er peripherals
are not required to run at that clock speed, or even from
the same clock source. Available clocking options are
described in detail in Section 2.3 “Osci llator Settings
fo r USB”.
17.9 USB Firmware and Drivers
Microchip provides a number of application specific
resour ces, such a s USB Chapte r 9 firm ware a nd driv er
support. Refer to www.microchip.com for the latest
firmware and driver support.
TABLE 17-6: REGISTERS ASSOCIATED WITH USB MODULE OPERATION(1)
Name Bit 7 B it 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Details on
page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51
IPR2 OSCFIP CMIP USBIP EEIP BCLIP LVDIP TMR3IP CCP2IP 54
PIR2 OSCFIF CMIF USBIF EEIF BCLIF LVDIF TMR3IF CCP2IF 54
PIE2 OSCFIE CMIE USBIE EEIE BCLIE LVDIE TMR3IE CCP2IE 54
UCON — PPBRST SE0 PKTDIS USBEN RESUME SUSPND —55
UCFG UTEYE UOEMON — UPUEN UTRDIS FSEN PPB1 PPB0 55
USTAT — ENDP3 ENDP2 ENDP1 ENDP0 DIR PPBI —55
UADDR — ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 55
UFRML FRM7 FRM6 FRM5 FRM4 FRM3 FRM2 FRM1 FRM0 55
UFRMH ————— FRM10 FRM9 FRM8 55
UIR — SOFIF STALLIF IDLEIF TRNIF ACTVIF UERRIF URSTIF 55
UIE — SOFIE STALLIE IDLEIE TRNIE ACTVIE UERRIE URSTIE 55
UEIR BTSEF —— BTOEF DFN8EF CRC16EF CRC5EF PIDEF 55
UEIE BTSEE —— BTOEE DFN8EE CRC16EE CRC5EE PIDEE 55
UEP0 ——— EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 55
UEP1 ——— EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 55
UEP2 ——— EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 55
UEP3 ——— EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 55
UEP4 ——— EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 55
UEP5 ——— EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 55
UEP6 ——— EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 55
UEP7 ——— EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 55
UEP8 ——— EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 55
UEP9 ——— EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 55
UEP10 ——— EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 55
UEP11 ——— EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 55
UEP12 ——— EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 55
UEP13 ——— EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 55
UEP14 ——— EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 55
UEP15 ——— EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 55
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the USB module.
Note 1: T his table includes only those hardware mapped SFRs located in Bank 15 of the data memory space. The Buffer
Descriptor registe rs, which are mapped into Bank 4 and are not true SFRs, are listed separately in Table 17-5.
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17.10 Overview of USB
This s ect ion prese nt s s om e o f th e basic USB concepts
and useful information necessary to design a USB
device. Although much information is provided in this
section, there is a plethora of information provided
within the USB specifications and class specifications.
Thus, the reader is encouraged to refer to the USB
specifications for more information (www.usb.org). If
you are very familiar with the details of USB, then this
sectio n will be a good , albei t ba sic, h igh-le vel refresh er
of USB.
17.10.1 LAYERED FRAMEWORK
A USB device functionality is structured into a layered
framework graphically shown in Figure 17-13. Each
level is associated with a functional level within the
device. The highest layer, other than the device, is the
configuration. A device may have multiple configura-
tions; for example, a particular device may have
multiple power requirements based on Self-Power Only
or Bus Power Only modes.
For each configuration, there may be multiple
interfaces. Each interface could support a particular
mode of that configuration.
Below the interface is the endpoint(s). Data is directly
moved at this level. There can be as many as 16 bidi-
rectional endpoints. Endpoint 0 is always a control
endpoin t and by def ault, whe n the devic e is on the bus,
Endpoint 0 must be available to configure the device.
17.10.2 FRAMES
Information communicated on the bus is grouped into
1 ms time slots referred to as frames. Each frame can
contain ma ny tran sac ti ons to v ari ous de vices an d en d-
poin ts. Figur e 17-9 shows an exampl e of a transaction
within a frame.
17.10.3 TRANSFERS
There are four transfer types defined in the USB
specification.
•Isochronous: This type provides a transfer
method for large amounts of data (up to 1023
bytes) with timely delivery ensured; however, the
data integrity is not ensured. This is good for
streaming applications where small data loss is
not critical, such as audio.
•Bulk: This type of transf er method all ows for large
amounts of data to be transferred with ensured
data integrity; however, the delivery timeliness is
not ensured.
•Interrupt: This type of transfer provides for
ens ured timely delivery for smal l blocks of data.
Plus data integrity is ensured.
•Control: This type provides for device setup
control.
While full speed devices support all transfer types,
low-speed devices are limited to interrupt and control
tran sfers only.
17.10.4 POWER
Power is available from the Universal Serial Bus. The
USB specification defines the bus power requirements.
Devices may either be self-powered or bus powered.
Self-powered devices draw power from an external
source, while bus p owered dev ices use powe r supplied
from the bus.
FIGURE 17-13 : USB LAYERS
Device
Configuration
Interface
Endpoint
Interface
Endpoint Endpoint Endpoint Endpoint
To other Configurations (if any)
To other Interfaces (if any)
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The USB specification limits the power taken from the
bus. Each device is ensured 100 mA at approximately
5V (one uni t lo ad ). Add itio na l po wer m ay b e re que ste d
up to a maximum of 500 mA. Note that power above
one unit load is a request and the host or hub is not
obligated to provide the extra current. Thus, a device
cap able of cons uming more than one unit lo ad must be
able to maintain a low-power configuration of one unit
load or less, if necessary.
The USB specification also defines a Suspend mode.
In this situation, current must be limited to 500 µA,
averaged over 1 second. A device must enter a
Suspend state after 3 ms of inactivity (i.e., no SOF
tokens for 3 ms). A device entering Suspend mode
must d rop cu rrent consum ption withi n 10 ms afte r Sus-
pend. Likewise, when signaling a wake-up, the device
must signal a wake-up within 10 ms of drawing current
above the Suspend limit.
17.10.5 ENUMERATION
When the device is initiall y attached to the bus, the host
enters an enumeration process in an attempt to identify
the device. Essentially, the host interrogates the device,
gathering information su ch as power consum ption, dat a
rates and sizes, protocol and other descriptive informa-
tion; descriptors contain this information. A typical
enumeration process would be as follows:
1. USB Reset: Reset the device. Thus, the device
is not conf igured and doe s not have an add res s
(address 0).
2. Get Device Descriptor: The host requests a
small port ion of the devic e descri pto r.
3. USB Reset: Reset the device ag ain.
4. Set Address: The host assigns an address to the
device.
5. Get Device Descriptor: The host retrieves the
device descriptor, gathering info such as manu-
facturer , type of device, maximum control packet
size.
6. Get Configu rati on Desc rip tors .
7. Get any other Descrip t ors.
8. Set a Configuration.
The exact enumeration process depends on the host.
17.10.6 DESCRIPTORS
There are eight different standard descriptor types of
which five are most important for this device.
17.10.6.1 Device Descriptor
The device desc riptor provides general information such
as manufacturer, product number, serial number, the
class of the device and the number of configurations.
There is only one device de scriptor.
17.10.6.2 Configuration Descriptor
The configuration descriptor provides information on
the power requirements of the device and how many
different interfaces are supported when in this configu-
ration. The re may be more than o ne conf igur ation fo r a
device (i.e., low -power and h igh-power c onfigur ations).
17.10.6.3 Interface Descriptor
The interface descriptor details the number of end-
points used in this interface, as well as the class of the
interface. There may be more than one interface for a
configuration.
17.10.6.4 Endpoint Descriptor
The endpoint descriptor identifies the transfer type
(Section 17.10.3 “Transfers”) and direction, as well
as som e other sp ecifics fo r the endpo int. Th ere may b e
many endpoints in a device and endpoints may be
shared in different configurations.
17.10.6.5 String Descri ptor
Many of the previous descriptors reference one or
more string descriptors. String descriptors provide
human readable information about the layer
(Section 17.10.1 “Layered Framework”) they
describe. Often these strings show up in the host to
help the user identify the device. String descriptors are
generall y optional to s ave mem ory and are enco ded in
a unicode form at.
17.10.7 BUS SPEED
Each USB device must indicate its bus presence and
speed to the host. This is accomplished through a
1.5 kΩ resistor, which is connected to the bus at the
time of the attachme nt eve nt.
Depending on the speed of the device, the resistor
either pulls up the D+ or D- line to 3.3V. For a
low-s peed device, the pull-up resistor is connected to
the D- line. For a full speed device, the pull-up resistor
is connected to the D+ line.
17.10.8 CLASS SPECIFICATIONS AND
DRIVERS
USB specifications include class specifications, which
operating system vendors optionally support.
Examples of classes include Audio, Mass Storage,
Communications and Human Interface (HID). In most
cases , a driver is re quired at the h ost side to ‘ talk’ to th e
USB devi ce. In custo m appl icatio ns, a dr iver may need
to be developed. Fortunately, drivers are available for
most common host systems for the most common
class es of de vi ces . Thu s, the se drive r s ca n be reu se d.
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DS39632A-page 186 Advance Information 2004 Microchip Technology Inc.
NOTES:
2004 Microchip Technology Inc. Advance Information DS39632A-page 187
PIC18F2455/2550/4455/4550
18.0 STREAMING PARALLEL PORT
PIC18F4455/4550 USB devices provide a Streaming
Parallel Port as a hi gh-s pe ed i nte rfac e for movin g da t a
to and fro m an e xterna l system . This pa rallel port op er-
ates as a master port, complete with chip select and
clock outputs to control the movement of data to slave
devices. Data can be channelled either directly to the
USB SIE, or to the microprocessor core. Figure 18-1
shows a block view of the SPP data path.
FIGURE 18-1: SPP DATA PATH
In addition, the SPP can provide time multiplexed
address ing information a long with th e data by u sing the
second strobe ou tput. Thu s, the USB end point nu mber
can be written in conjunction with the data for that
endpoint.
18.1 SPP Configuration
The opera tion of th e SPP is co ntrolled by t wo registers :
SPPCON and SPPCFG. The SPPCON register
(Register 18-1) controls the overall operation of the
paral lel port and determi nes if it operat es under USB or
microcontroller control. The SPPCFG register
(Register 18-2) controls timing configuration and pin
outputs.
18.1.1 ENABLING THE SPP
To enable the SPP, set the SPPEN bit (SPPCON<0>).
In addition, the TRIS bits for the corresponding SPP
pins must be properly configured. At a minimum:
• Bits TRISD<7:0> must be set (= 1)
• Bits TRISE<2:1> must be clear ed (= 0)
If CK1SPP is to be used:
• Bit TRISE<0> must be cleared (= 0)
If CSPP is to be used:
• Bit TRISB<4> must be cleared (= 0)
REGISTER 18-1: SSPCON: SPP CONTROL REGISTER
Note: The Streaming Parallel Port is only
available on 40/44-pin devices.
SPP
Logic
CK2SPP
OESPP
CSSPP
SPP<7:0>
CK1SPP
USB
CPU
PIC18F4455/4550
SIE
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
— — — — — — SPPOWN SPPEN
bit 7 bit 0
bit 7-2 Unimplemented: Read as ‘0’
bit 1 SPPOWN: SPP Ownership bit
1 = USB peripheral controls the SPP
0 = Microcontroller directly controls the SPP
bit 0 SPPEN: SPP Enable bit
1 = SPP is enabled
0 = SPP is disabled
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
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DS39632A-page 188 Advance Information 2004 Microchip Technology Inc.
REGISTER 18-2: SPPCFG: SPP CONFIGURATION REGISTER
18.1.2 CLOCKING DATA
The SPP has four control outputs:
• Two separate clock outputs (CK1SPP and
CK2SPP)
• Output enable (OESPP)
• Chip select (CSSPP)
Toge ther, they allo w for severa l dif fe rent con figurat ions
for controlling the flow of data to slave devices. When
all contro l output s are used, the three ma in options are:
• CLK1 clocks endpoint address information while
CLK2 clocks data
• CLK1 clocks write operations while CLK2 clocks
reads
• CLK1 cl ocks odd add ress d ata w hile CLK2 c locks
even address data
Additional control options are derived by disabling the
CK1SPP and CSSPP outputs. These are enabled or
disabled with the CLK1EN and CSEN bits, respectively ,
located in Register 18-2.
18.1.3 WAIT STATES
The SPP is designed with the capability of adding wait
state s to read and wr ite ope rations . This allo ws acc ess
to parallel devices that require extra time for access.
Wait state clocking is based on the data source clock.
If the SPP is co nfi gure d to oper ate a s a USB endp oin t ,
then w ait st ates are ba sed on the U SB clo ck. Like wis e,
if the SPP is configured to operate from the microcon-
troller , then wait states are based on the instruct ion rate
(FOSC/4).
The WS 3:WS0 bits set the wait s tates us ed by the SPP,
with a range of no wait states to 30 wait states, in mul-
tiples of two. The wait states are added symmetrically
to all transactions, with one-half added following each
of the two clock cycles normally required for the trans-
action. Figure 18-3 and Figure 18-4 show signalling
exampl es with 4 wait st a tes add ed to eac h transac tion.
18.1.4 SPP PULL-UPS
The SPP data lines (SPP<7:0>) are equipped with
internal pull-ups for applic ations that m ay leave the port
in a high-impedance condition. The pull-ups are
enabled using the control bit, RDPU (PORTE<7>).
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CLKCFG1 CLKCFG0 CSEN CLK1EN WS3 WS2 WS1 WS0
bit 7 bit 0
bit 7-6 CLKCFG1:CLKCFG0: SPP Clock Configuration bits
1x = CLK1 toggles on read or write of an odd endpoint address;
CLK2 toggles on read or write of an even endpoint address.
01 = CLK1 toggles on write, CLK2 toggles on read
00 = CLK1 toggles only on endpoint address write, CLK2 toggles on data read or write
bit 5 CSEN: SPP Chip Select Pin Enab le bit
1 = RB4 pin is controlled by the SPP module and functions as SPP CS output
0 = RB4 functions as a digital I/O port
bit 4 CLK1EN: SPP CLK1 Pin Enable bit
1 = RE0 pin is controlled by the SPP module and functions as SPP CLK1 output
0 = RE0 functions as a digital I/O port
bit 3-0 WS3:WS0: SPP Wait States bits
1111 = 30 additional wait states
1110 = 28 additional wait states
• •
• •
0001 = 2 additional wait states
0000 = 0 additional wait states
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
2004 Microchip Technology Inc. Advance Information DS39632A-page 189
PIC18F2455/2550/4455/4550
FIGURE 18-2: TIMING FOR MICROCONTROLLER WRITE ADDRESS, WRITE DATA AND READ
DATA (NO WAIT STATES)
FIGURE 18-3: TIMING FOR USB WRITE ADDRESS AND DATA (4 WAIT STATES)
FIGURE 18-4: TIMING FOR USB WRITE ADDRESS AND READ DATA (4 WAIT STATES)
FOSC/4
ADDR
OESPP
CK1SPP
CK2SPP
CSSPP
SPP<7:0> DATA DATA
MOVWF SPPEPS MOVWF SPPDATA
Write Address Write Data MOVF SPPDATA, W
Read Data
USB Clock
OESPP
CK1SPP
CK2SPP
CSSPP
SPP<7:0>
2 Wait States 2 Wait States 2 Wait States 2 Wait S tates
Write Address Write Data
USB Clock
OESPP
CK1SPP
CK2SPP
CSSPP
SPP<7:0> Write Address Read Data
2 Wait States 2 Wait States 2 Wait States 2 Wait States
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DS39632A-page 190 Advance Information 2004 Microchip Technology Inc.
18.2 Setup for USB Control
When the SPP is configured for USB operation, data
can be c loc ke d d ire ctl y to a nd fro m the USB p erip heral
without intervention of the microcontroller; thus, no
process time is required. Data is clocked into or out
from the SPP with endpoint (address) information first,
followed by one or more bytes of data, as shown in
Figure 18-5. This is ideal for applications that require
isochronous , larg e volume data movement.
The following steps are required to setup the SPP for
USB control:
1. Configure the SPP as desired, including wait
states and cloc ks .
2. Set the SPPOWN bit for USB ownership.
3. Set the buffer descriptor starting address
(BDnADRL:BDnADRH) to FFFFh.
4. Set the KEN bit (BDnSTAT<5>) so the buffer
descriptor is kept indefinitely by the SIE.
5. Set the INCDIS bit (BDnSTAT<4>) to disable
automatic buffer address increment.
6. Set the SPPEN bit to enable the module.
18.3 Setup for Microcontroller Cont rol
The SPP can also act as a parallel port for the micro-
controller. In this mode, the SPPEPS register
(Register 18-3) provides status and address write
control. Data is written to and read from the SPPDATA
register. When the SPP is owned by the microcontrol-
ler, the SPP clock is driven by the instruction clock
(FOSC/4).
The following steps are required to setup the SPP for
microcontroller operation:
1. Configure the SPP as desired, including wait
states and cloc ks .
2. Clear the SPPOWN bit.
3. Set SPPEN to enable the module.
18.3.1 SPP INTERRUPTS
When owned by the microcontroller core, control can
generate an interrupt to notify the application when
each read and write operation is completed. The inter-
rupt flag bit is SPPIF (PIR<7>) and is enabled by the
SSPIE bit (PIE1 <7>). Like all other microcontroller level
interrupts, it can be set to a low or high priority. This is
done with the SSPIP bit (IPR<7>).
18.3.2 WRITING TO THE SPP
Once configured, writing to the SPP is performed by
writing to the SPPEPS and SPPDATA registers. If the
SPP is configured to clock out endpoint address infor-
mation with the data, writing to the SPPEPS register
initiate s the a ddress write cycl e. Oth erwise, t he wri te is
started by writing the data to the SPPDATA register.
The SPPBUSY bit indicates the status of the address
and the data write cycles.
The following is an example write sequence:
1. Write the 4-bit address to the SPPEPS register.
The SPP automatically starts writing the
address. If address write is not used, then skip
to step 3.
2. Monitor the BUSY bit to determine when the
address has been sent. The duration depends
on the wait states.
3. Write the data to the SPPDATA register. The
SPP automaticall y st a rt s writing the data.
4. Monitor the BUSY bit to determine when the
data has been sent. The duration depends on
the wait states.
5. Go back to steps 1 or 3 to write a new address
or data.
FIGURE 18-5: TRANSFER OF DATA BETWEEN USB SIE AND SPP
Note: The SSPBUSY bit should be polled to
make certain that successive writes to the
SPPEPS or SPPDATA registers do not
overrun the wait time due to the wait state
setting.
Byte 0 Byte 1 Byte 2 Byte 3 Byte n
Endpoint
Address
Write USB endpoint number to SPP
Write outbound USB data to SPP, or
Read inbound USB data from SPP
2004 Microchip Technology Inc. Advance Information DS39632A-page 191
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18.3.3 READING FROM THE SPP
Reading from the SPP involves reading the SPPDATA
register. Reading the register the first time initiates the
read op eration. W hen th e read i s fin is hed , i nd ica ted b y
the BUSY bit, the SPPDATA will be loaded with the
current data.
The following is an example read sequence:
1. Write the 4-bit address to the SPPEPS register.
The SPP automatically starts writing the
address . If addres s write is not u sed then skip to
step 3.
2. Monitor the BUSY bit to determine when the
address has been sent. The duration depends
on the wait states.
3. Read the data from the SPPDATA register; the
data from the previous read operation is
returned. The SPP automatically starts the read
cycle for the next read.
4. Monitor the BUSY bit to determine when the
data has been read. The duration depends on
the wait states.
5. Go back to step 3 to read the current byte from
the SPP and start the next read cycle.
REGISTER 18-3: SPPEPS: SPP ENDPOINT ADDRESS AND STATUS REGISTER
R-0 R-0 U-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0
RDSPP WRSPP — SPPBUSY ADDR3 ADDR2 ADDR1 ADDR0
bit 7 bit 0
bit 7 RDSPP: SPP Read Status bit
1 = The last transaction was a read from the SPP
0 = The last transact ion w as not a read from the SPP
bit 6 WRSPP: SPP Write Status bit
1 = The last transaction w as a write t o the SPP
0 = The last transaction w as not a write to the SP P
bit 5 Unimplemented: Read as ‘0’
bit 4 SPPBUSY: SPP Handshaking Override bit
1 = The SPP is busy
0 = The SPP is ready to accept another read or write request
bit 3-0 ADDR3:ADDR0: SPP Endpoint Address bits
1111 = Endpoint Address 15
• •
• •
0001
0000 = Endpoint Address 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
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DS39632A-page 192 Advance Information 2004 Microchip Technology Inc.
TABLE 18-1: REGISTERS ASSOCIATED WITH THE STREAMING PARALLEL PORT
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset
Values
on pag e
SPPCON — — — — — — SPPOWN SPPEN 55
SPPCFG CLKCFG1 CLKCFG0 CSEN CLK1EN WS3 WS2 WS1 WS0 55
SPPEPS RDSPP WRSPP — SPPBUSY ADDR3 ADDR2 ADDR1 ADDR0 55
SPPDATA SPP Data Register 55
PIR1 SPPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 54
PIE1 SPPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 54
IPR1 SPPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 54
PORTE RDPU — — — RE3(1) RE2 RE1 RE0 54
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for the Streaming Parallel Port.
Note 1: RE3 is available when the MCLRE configuration bit is clear; otherwise, it reads as ‘0’.
2004 Microchip Technology Inc. Advance Information DS39632A-page 193
PIC18F2455/2550/4455/4550
19.0 MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
19.1 Master SSP (MSSP) Module
Overview
The Master Synchronous Serial Port (MSSP) module is
a serial interface, useful for communicating with other
periphera l or m icroc ontroll er devic es. Th ese p eriphera l
devices may be serial EEPROMs, shift registers,
display d rivers, A/D converte rs, etc. The MSSP modul e
can operate in one of two modes:
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I2C)
- Full Master mode
- Slave mode (with general address call)
The I2C interface supports the following modes in
hardware:
•Master mode
• Multi-Master mode
• Slave mode
19.2 Control Registers
The MSSP module has three associated registers.
These include a status register (SSPSTAT) and two
control registers (SSPCON1 and SSPCON2). The use
of the se registers a nd t heir individual con fig urat ion bits
differ significantly depending on whether the MSSP
module is operated in SPI or I2C mode.
Additional details are provided under the individual
sections.
19.3 SPI Mode
The S PI mode allo ws 8 bits of dat a to be sy nchronousl y
transmitted and received simultaneously. All four SPI
modes are supported. To accomplish communication,
typically three pins are used:
• Serial Data Out (SDO) – RC7/RX/DT/SDO
• Serial Data In (SDI) –
RB0/AN12/INT0/FLT0/SDI/SDA
• Serial Clock (SCK) – RB1/AN10/INT1/SCK/SCL
Additionally, a fourth pin may be used when in a Slave
mode of operation:
• Slave Select (SS) – RA5/AN4/SS/HLVDIN/C2OUT
Figure 19-1 shows the block diagram of the MSSP
module when operating in SPI mode.
FIGURE 19-1: MSSP BLOCK DIAGRAM
(SPI MODE)
( )
Read Write
Internal
Data Bus
SSPSR reg
SSPM3:SSPM0
bit0 Shift
Clock
SS Control
Enable
Edge
Select
Clock Select
TMR2 Output
TOSC
Prescaler
4, 16, 64
2
Edge
Select
2
4
Data to TX /RX in SSPSR
TRIS bit
2
SMP:CKE
RC7/SDO
SSPBUF reg
RB0/SDI/SDA
RA5/SS
RB1/SCK/SCL
Note: Only those pin functions relevant to SPI™
operation are shown here.
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DS39632A-page 194 Advance Information 2004 Microchip Technology Inc.
19.3.1 REGISTERS
The MSSP module has four registers for SPI mode
operation. These are:
• MSSP Control Register 1 (SSPCON1)
• MSSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer Register
(SSPBUF)
• MSSP Shift Register (SSPSR) – Not directly
accessible
SSPCON1 and SSPSTAT are the control and status
registers in SPI mode operation. The SSPCON1
register is readable and writable. The lower 6 bits of
the SSPSTAT are read-only. The upper two bits of the
SSPSTAT are read/write.
SSPSR is the shift register used for shifting data in or
out. SSPBUF is the buffer register to which data bytes
are written to or read from.
In receive operations, SSPSR and SSPBUF together
create a double-buffered receiver. When SSPSR
receives a complete byte, it is transferred to SSPBUF
and the SSPIF interrupt is set.
During transmission, the SSPBUF is not double-
buff ered. A write to SSPBUF will write to bo th SSPBUF
and SSPSR.
REGISTER 19-1: SSPSTAT: MSSP STATUS REGISTER (SPI MODE)
R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0
SMP CKE D/A PSR/WUA BF
bit 7 bit 0
bit 7 SMP: Sample bit
SPI Master mode:
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI operation is used in Slave mode.
bit 6 CKE: SPI Clock Select bit
1 = Transmit occurs on transition from active to Idle clock state
0 = Transmit occurs on transition from Idle to active clock state
Polarity of clock state is set by the CKP bit (SSPCON1<4>).
bit 5 D/A: Data/Address bit
Used in I2C mode only.
bit 4 P: Stop bit
Used in I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is
cleared.
bit 3 S: Start bit
Used in I2C mode only.
bit 2 R/W: Read/W ri te bit Info rma tio n
Used in I2C mode only.
bit 1 UA: Update Address bit
Used in I2C mode only.
bit 0 BF: Buffer Full Status bit (Receive mode only)
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
2004 Microchip Technology Inc. Advance Information DS39632A-page 195
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REGISTER 19-2: SSPCON1: MSSP CONTROL REGISTER 1 (SPI MODE)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
bit 7 bit 0
bit 7 WCOL: Write Collision Detect bit (Transmit mode only)
1 = The SSPBUF register is written while it is still transmitting the previous word
(must be cleared in software)
0 = No collision
bit 6 SSPOV: Receive Overflow Indicator bit
SPI Slave mode:
1 = A new byte is rec eived while the SSPBUF register is still holdin g the previo us data. In c ase
of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user
must read the SSPBUF, even if only transmitting data, to avoid setting overflow (must be
cleared in sof tware).
0 = No overflow
Note: In Master mode, the overflow bit is not set since each new reception (and
transmission) is initiated by writing to the SSPBUF register.
bit 5 SSPEN: Synchronous Serial Port Enable bit
1 = Enables serial port and configures SCK, SDO, SDI and SS as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
Note: When enabled, these pins must be properly configured as input or output.
bit 4 CKP: Clock Polarity Select bit
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
bit 3-0 SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
0101 = SPI Slave mode, clock = SCK pin , SS pin co ntro l dis abl ed , SS can be used as I/O pin
0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled
0011 = SPI Master mode, clock = TMR2 output/2
0010 = SPI Master mode, clock = FOSC/64
0001 = SPI Master mode, clock = FOSC/16
0000 = SPI Master mode, clock = FOSC/4
Note: Bit combinations not specifically listed here are either reserved or implemented in
I2C mode only.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC18F2455/2550/4455/4550
DS39632A-page 196 Advance Information 2004 Microchip Technology Inc.
19.3.2 OPERATION
When i nitializing SPI operatio n, several options nee d to
be specified. This is done by programming the
appropriate control bits (SSPCON1<5:0> and
SSPSTAT<7:6>). These c ont rol bits allow the foll owin g
to be specified:
• Master mode (SCK is the clock output)
• Slave mode (SCK is the clock input)
• Clock Polarity (Idle state of SCK)
• Data Input Sample Phase (middle or end of data
output time)
• Clock Edge (output data on rising/falling edge of
SCK)
• Clock Rate (Master mode only)
• Slave Select mode (Slave mode only)
The MSSP consists of a Transmit/Receive Shift regis-
ter (SSPSR) and a Buffer register (SSPBUF). The
SSPSR shifts the data in and out of the device, MSb
first. The SSPBUF holds the data that was written to the
SSPSR until the received da ta is ready. Once the 8 bit s
of data have been received, that byte is moved to the
SSPBUF register. Then, the Buffer Full detect bit, BF
(SSPSTAT<0>) and the interrupt flag bit, SSPIF, are
set. This double-buffering of the received data
(SSPBUF) allows the next byte to start reception before
reading t he data that was just re ceived. Any write to the
SSPBUF register during transmission /reception of dat a
will be ignored a nd the W rite Colli sion detec t bit, WCOL
(SSPCON1<7>), will be set. User software must clear
the WCOL bit so that it can be determin ed if the foll ow-
ing write(s) to the SSPBUF register completed
successfully.
When the application software is expecting to receive
valid da ta, the SSPBUF shoul d be read before th e next
byte of data to transfer is written to the SSPBUF. The
Buffer Full bit, BF (SSPSTAT<0>), indicates when
SSPBUF has been loaded with the received data
(transmiss ion is complete ). When the SSPBUF is read,
the BF bit is cleared. This data may be irrelevant if the
SPI is only a transmit ter . Generall y, the MSSP interrupt
is used to determine when the transmission/reception
has completed. The SSPBUF must be read and/or
written. If the interrupt method is not going to be used,
then sof tware polli ng can be do ne to ensure t hat a write
collision does not occur. Example 19-1 shows the
loading of the SSPBUF (SSPSR) for data transmission.
The SSPSR is n ot directly reada ble or wri table and can
only be accessed by addressing the SSPBUF register.
Additionally, the MSSP Status register (SSPSTAT)
indicates the various status conditions.
EXAMPLE 19-1: LOADING THE SSPBUF (SSPSR) R EGISTER
LOOP BTFSS SSPSTAT, BF ;Has data been received (transmit complete)?
BRA LOOP ;No
MOVF SSPBUF, W ;WREG reg = contents of SSPBUF
MOVWF RXDATA ;Save in user RAM, if data is meaningful
MOVF TXDATA, W ;W reg = contents of TXDATA
MOVWF SSPBUF ;New data to xmit
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19.3.3 ENABLING SPI I/O
To enable the serial port, SSP Enable bit, SSPEN
(SSPCON1<5>), must be set. To reset or reconfigure
SPI mode, clear the SSPEN bit, reinitialize the
SSPCON registers and then set the SSPEN bit. This
configures the SDI, SDO, SCK and SS pins as serial
port pin s. For the pins t o behave as the serial p ort fun c-
tion, some must have their data direction bits (in the
TRIS register) appropriately programmed as follows:
• SDI is a uto matically c ontrolled by the SP I mo dule
• SDO must have TRISC<7> bit cleared
• SCK (Master mode) must have TRISB<1> bit
cleared
• SCK (Slave mode) must have TRISB<1> bit set
•SS
must have TRISA<5> bit set
Any serial port function that is not desired may be
overridden by programming the corresponding data
direction (TRIS) register to the opposite value.
19.3.4 TYPIC AL CONNEC TI ON
Figure 19-2 shows a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCK signal.
Data is shifted out of both shift registers on their pro-
grammed clock e dge and l atched on the oppos ite edge
of the cloc k. Both processors should be prog rammed to
the same Clock Polarity (CKP), then both controllers
would send and receive data at the same time.
Whether the data is meaningful (or dummy data)
depends on the application software. This leads to
three scenarios for data transmission:
• Master sends data – Slave send s dummy data
• Master sends data – Slave sends data
• Master sends d ummy data – Slave sends data
FIGURE 19-2: SPI MASTER/SLAVE CONNECTION
Serial Input Buffer
(SSPBUF)
Shift Register
(SSPSR)
MSb LSb
SDO
SDI
PROC ESSOR 1
SCK
SPI Master SSPM3:SSPM0 = 00xxb
Serial Input Buffer
(SSPBUF)
Shift Register
(SSPSR)
LSb
MSb
SDI
SDO
PROCESSOR 2
SCK
SPI Slave SSPM 3:SSPM0 = 010xb
Serial Clock
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19.3.5 MASTER MODE
The master can initiate the data transfer at any time
because it controls the SCK. The master determines
when the slave (Processor 2, Figure 19-2) is to
broadcast data by the software protocol.
In Master mode, the data is transmitted/received as
soon as the SSPBUF register is written to. If the SPI
module is only going to receive, the SDO output could
be disabled (programmed as an input). The SSPSR
register will conti nue to shift i n the signal present on the
SDI pin at the programmed clock rate. As each byte is
received, it will be loaded into the SSPBUF register as
if a normal received byte (interrupts and status bits
appropriately set). This could be useful in receiver
applications as a “Line Activity Monitor” mode.
The clock polarity is selected by appropriately
programming the CKP bit (SSPCON1<4>). This then,
would give waveforms for SPI communication as
shown in Figure 19-3, Figure 19-5 and Figure 19-6,
where t he MSB is tran smitted fi rst. In Ma ster mode , the
SPI clock ra te (bit rate) is user programmable t o be one
of the following:
•F
OSC/4 (or TCY)
•FOSC/16 (or 4 • TCY)
•F
OSC/64 (or 16 • TCY)
• Timer2 output/2
This allows a maximum data rate (at 40 MHz) of
10.00 Mbps.
Figure 19-3 shows the waveforms for Master mode.
When the CKE bit is set, the SDO data is valid before
there is a clock edge on SCK. The change of the input
sample is shown based on the state of the SMP bit. The
time when the SSPBUF is loaded with the received
dat a is shown.
FIGURE 19-3: SPI™ MODE WAVEFORM (MASTER MODE)
SCK
(CKP = 0
SCK
(CKP = 1
SCK
(CKP = 0
SCK
(CKP = 1
4 Clock
Modes
Input
Sample
Input
Sample
SDI bit 7 bi t 0
SDO bit 7 bit 6 bit 5 bi t 4 bit 3 bit 2 bit 1 bit 0
bit 7
SDI
SSPIF
(SMP = 1)
(SMP = 0)
(SMP = 1)
CKE = 1)
CKE = 0)
CKE = 1)
CKE = 0)
(SMP = 0)
Write to
SSPBUF
SSPSR to
SSPBUF
SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
(CKE = 0)
(CKE = 1)
Next Q4 Cycl e
after Q2↓
bit 0
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19.3.6 SLAVE MODE
In Slave m ode , the dat a is transmi tted and receiv ed a s
the external clock pulses appear on SCK. When the
last bit is latched, the SSPIF interrupt flag bit is set.
Before enabling the module in SPI Slave mode, the
clock line must match the proper Idle state. The clock
line can be observed by reading the SCK pin. The Idle
state is determined by the CKP bit (SSPCON1<4>).
While in Slave mode, the external clock is supplied by
the external clock source on the SCK pin. This external
clock must meet the minimum high and low times as
specified in the electrical specifications.
While in Sleep mode, the slave can transmit/receive
data. When a byte is received, the device will wake-up
from Sleep.
19.3.7 SLAVE SELECT
SYNCHRONIZATION
The SS pin allows a Synchronous Slave mode. The
SPI must be in Slave mode wit h SS pin control ena bled
(SSPCON1<3:0> = 04h). The pin must not be driven
low for the SS pin to function as an input. The dat a latch
must be high. When the SS pin is low , transmission and
receptio n are enab led and the SDO pin is driv en. When
the SS pin goes hi gh , th e SD O pin is no lo n ge r dr iv en ,
even if in the middle of a tran smitted byte an d becomes
a floating output. External pull-up/pull-down resistors
may be desirable, depending on the application.
When the SPI module resets, the bit counter is forced
to ‘0’. This can be done by either forcing the SS pin to
a high level or clearing the SSPEN bit.
To emulate two-wire communication, the SDO pin can
be connected to the SDI pin. When the SPI module
needs to operate as a receiver, the SDO pin can be
configured as an input. This disables transmissions
from the SDO. The SDI can always be left as an input
(SDI function) since it cannot create a bus conflict.
FIGURE 19-4: SLAVE SYNCHRONIZATION WAVEFORM
Note 1: When the SPI module is in Slave mode
with SS pin control enabled
(SSPCON<3:0> = 0100), the SPI module
will reset if the SS pin is set to VDD.
2: If the SPI is us ed in Slave mo de with CK E
set, then the SS pin control must be
enabled.
SCK
(CKP = 1
SCK
(CKP = 0
Input
Sample
SDI
bit 7
SDO bit 7 b i t 6 bit 7
SSPIF
Interrupt
(SMP = 0)
CKE = 0)
CKE = 0)
(SMP = 0)
Write to
SSPBUF
SSPSR to
SSPBUF
SS
Flag
bit 0
bit 7 bit 0
Next Q4 Cycle
after Q2↓
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FIGURE 19-5: SPI™ MODE WAVEFORM (SLAVE MODE WITH CKE = 0)
FIGURE 19-6: SPI™ MODE WAVEFORM (SLAVE MODE WITH CKE = 1)
SCK
(CKP = 1
SCK
(CKP = 0
Input
Sample
SDI bit 7
SDO bi t 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
SSPIF
Interrupt
(SMP = 0)
CKE = 0)
CKE = 0)
(SMP = 0)
Write to
SSPBUF
SSPS R to
SSPBUF
SS
Flag
Optional
Next Q4 Cycl e
after Q2↓
bit 0
SCK
(CKP = 1
SCK
(CKP = 0
Input
Sample
SDI bit 7 bit 0
SDO bi t 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
SSPIF
Interrupt
(SMP = 0)
CKE = 1)
CKE = 1)
(SMP = 0)
Write to
SSPBUF
SSPSR to
SSPBUF
SS
Flag
Not Optional
Next Q4 Cycle
after Q2↓
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19.3.8 OPERATION IN POWER MANAGED
MODES
In SPI Master mo de, modu le clo cks may be op erati ng
at a different speed than when in full power mode; in
the case of the Sleep mode, all clocks are halted.
In most power managed modes, a clock is provided to
the peripherals. That clock should be from the primary
clock so u r ce, t he seco nd a ry cl oc k ( Timer1 os ci llat o r at
32.768 kHz) or the INTOSC source. See Section 2.4
“Clock Sources and Oscillator Switching” for
additional information.
In most cases, the speed that the master clocks SPI
data is not important; however, this should be
evaluated for each system.
If MSSP inte rrupts are en abled, they can wake the con-
troller from Sle ep m od e or on e of th e Id le m ode s whe n
the master completes sending data. If an exit from
Sleep or Idle mode is not desired, MSSP interrupts
should be disabled.
If the Sleep mode is selected, all module clocks are
halted and the transmission/reception will remain in
that state until the devices wakes. After the device
returns to Run mode, the module will resume
transmitting and receiving data.
In SPI Slave mode, the SPI Transmit/Receive Shift
register operates asynchronously to the device. This
allows the device to be placed in any power managed
mode and data to be shifted into the SPI Transmit/
Receive Shift register. When all 8 bits have been
received, the MSSP interrupt flag bit will be set and if
enabled, will wake the device.
19.3.9 EFFECTS OF A RESET
A Reset disables the MSSP module and terminat es the
current transfer.
19.3.10 BUS MODE COMPATIBILITY
Table 19-1 shows the compatibility between the
standard SPI modes and the states of the CKP and
CKE control bits.
TABLE 19-1: SPI BUS MODES
There is also a SMP bit w hich co ntrols whe n the dat a is
sampled.
TABLE 19-2: REGISTERS ASSOCIATED WITH SPI™ OPERATION
Standard SPI Mode
Terminology
Control Bits State
CKP CKE
0, 0 0 1
0, 1 0 0
1, 0 1 1
1, 1 1 0
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 54
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 54
IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 54
TRISA PORTA Data Direction Register 54
TRISB PORTB Data Direction Register 54
TRISC PORTC Data Direction Register 54
SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register 52
SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 52
SSPSTAT SMP CKE D/A P S R/W UA BF 52
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode.
Note 1: These bits are unimplemented in 28-pin devices; always maintain these bits clear.
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19.4 I2C Mode
The MSSP module in I2C mode fully implements all
master and slave functions (including general call
support) and provides interrupts on Start and Stop bits
in hardw are to determine a free bus (m ulti-master fun c-
tion). The MSSP module implements the standard
mode specifications as well as 7-bit and 10-bit
addressing.
Two pins are used for data transfer:
• Serial clock (SCL) – RB1/AN10/INT1/SCK/SCL
• Serial data (SDA) –
RB0/AN12/INT0/FLT0/SDI/SDA
The user must configure these pins as inputs or out puts
through the TRISB<1:0> bits.
FIGURE 19-7: MSSP BLOCK DIAGRAM
(I2C™ MODE)
19.4.1 REGISTERS
The MSSP module has six registers for I2C operation.
These are:
• MSSP Control Register 1 (SSPCON1)
• MSSP Control Register 2 (SSPCON2)
• MSSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer Register
(SSPBUF)
• MSSP Shift Register (SSPSR) – Not directly
accessible
• MSSP Address Register (SSPADD)
SSPCON1, SSPCON2 and SSPSTAT are the control
and status registers in I2C mode operation. The
SSPCON1 and SSPCON2 registers are readable and
writable. The lower 6 bit s of the SSPSTA T are read-only.
The upper two bits of the SSPSTAT are read/write.
SSPSR is the shift register used for shifting data in or
out. SSPBUF is the buffer register to which data bytes
are written to or read from.
SSPADD register hold s the slave device addres s when
the SSP is configured in I2C Slave mode. When the
SSP is configu red in Master mod e, the lower seven bits
of SSPADD act as the Baud Rate Generator reload
value.
In receive operations, SSPSR and SSPBUF together
create a double-buffered receiver. When SSPSR
receives a complete byte, it is transferred to SSPBUF
and the SSPIF interrupt is set.
During transmission, the SSPBUF is not double-
buff ered. A write to SSPBUF will write to bo th SSPBUF
and SSPSR.
Read Write
SSPSR reg
Match Detect
SSPADD reg
Start and
Stop bit Detect
SSPBUF reg
Internal
Data Bus
Addr Match
Set, Reset
S, P bits
(SSPSTAT reg)
RB1/SCK/SCL
RB0/SDI/SDA
Shift
Clock
MSb LSb
Note: Only those pin functions relevant to I2C
operation are shown here.
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REGISTER 19-3: SSPSTAT: MSSP STATUS REGISTER (I2C MODE)
R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0
SMP CKE D/A PSR/WUA BF
bit 7 bit 0
bit 7 SMP: Slew Rate Control bit
In Master or Slave mode:
1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz)
0 = Slew rate control enabled for High-Speed mode (400 kHz)
bit 6 CKE: SMBus Select bit
In Master or Slave mode:
1 = Enable SMBus specific inputs
0 = Disable SMBus specific inputs
bit 5 D/A: Data/Address bit
In Master mode:
Reserved.
In Slave mode:
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
bit 4 P: Stop bit
1 = Indicates that a Stop bit has been detected last
0 = Stop bit was not detected last
Note: This bit is cleared on Reset and when SSPEN is cleared.
bit 3 S: Start bit
1 = Indicates that a Start bit has been detected last
0 = Start bit was not detected last
Note: This bit is cleared on Reset and when SSPEN is cleared.
bit 2 R/W: Read/W ri te bit Info rma tio n (I2C mode only)
In Slave mode:
1 = Read
0 = Write
Note: This bit holds the R/W bit information following the last address match. Thi s bit is only
valid from the address match to the next Start bit, Stop bit or not ACK bit.
In Master mode:
1 = Transmit is in progress
0 = Transmit is not in progress
Note: ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is
in Idle mode.
bit 1 UA: Update Address bit (10-bit Slave mode only)
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
bit 0 BF: Buffer Full Status bit
In Transmit mode:
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
In Receive mode:
1 = Data tr ansmit in progress (d oes not include the A CK and Stop bits), SSPBUF is full
0 = Data transmit complete (does not include the ACK and Stop bits), SSPBUF is empty
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘ 0’ = Bit is cleared x = Bit is unknown
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REGISTER 19-4: SSPCON1: MSSP CONTROL REGISTER 1 (I2C MODE)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
bit 7 bit 0
bit 7 WCOL: Write Collision Detect bit
In Master Transmit mode:
1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for
a transmission to be started (must be cleared in software)
0 = No collision
In Slave Transmit mode:
1 = The SSPBUF register is written while it is still transmitting the previous word (must be
cleared in software)
0 = No collision
In Receive mode (Master or Slave modes):
This is a “don’t care” bit.
bit 6 SSPOV: Receive Overflow Indicator bit
In Receive mode:
1 = A byte is received while the SSPBUF register is still holding the previous byte (must be
cleared in software)
0 = No overflow
In Transmit mode:
This is a “don’t care” bit in Transm it mode.
bit 5 SSPEN: Synchronous Serial Port Enable bit
1 = Enables the serial port and configures the SDA and SCL pins as the serial port pins
0 = Disables serial port and configures these pins as I/O port pins
Note: When enabled, the SDA and SCL pins must be properly configured as input or
output.
bit 4 CKP: SCK Release Control bit
In Slave mode:
1 = Release clock
0 = Holds clock low (clock stretch), used to ensure data setup time
In Master mode:
Unused in this mode.
bit 3-0 SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
1011 = I2C Firmware Controlled Master mode (Slave Idle)
1000 = I2C Master mode, clock = FOSC/(4 * (SSPADD + 1))
0111 = I2C Slave mode, 10-bit address
0110 = I2C Slave mode, 7-bit address
Note: Bit combinations not specifically listed here are either reserved or implemented in
SPI mode only.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘ 0’ = Bit is cleared x = Bit is unknown
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REGISTER 19-5: SSPCON2: MSSP CONTROL REGISTER 2 (I2C MODE)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
GCEN ACKSTAT ACKDT ACKEN(1) RCEN(1) PEN(1) RSEN(1) SEN(1)
bit 7 bit 0
bit 7 GCEN: Gener al Call Enable bit (Slave mode only)
1 = Enable interrupt when a general call address (0000h) is received in the SSPSR
0 = General call address disabled
bit 6 ACKSTAT: Acknowledge Status bit (Master Transmit mode only)
1 = Acknowledge was not received from slave
0 = Acknowledge was received from slave
bit 5 ACKDT: Acknowledge Data bit (Master Receive mode only)
1 = Not Acknowledge
0 = Acknowledge
Note: Value that will be transmitted when the user initiates an Acknowledge sequence at
the end of a receive.
bit 4 ACKEN: Acknowledge Sequence Enable bit (Master Receive mode only)(1)
1 = Initiate Acknowledge sequence on SDA and SCL pins and transmit ACKDT data bit.
Automatically cleared by hardware.
0 = Acknowledge sequence Idle
bit 3 RCEN: Receive Enable bit (Master mode only)(1)
1 = Enables Receive mode for I2C
0 = Receive Idle
bit 2 PEN: Stop Condition Enable bit (Master mode only)(1)
1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Stop condition Idle
bit 1 RSEN: Repeated Start Condition Enabled bit (Master mode only)(1)
1 = Initiate Repeated S t art condition on SDA and SCL pins. Autom atically cleared by hardware.
0 = Repeated Start condition Idle
bit 0 SEN: Start Condition Enabled/Stretch Enabled bit(1)
In Master mode:
1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Start condition Idle
In Slave mode:
1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0 = Clock stretching is disabled
Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode,
these bits may not be set (no spooling) and the SSPBUF may not be written (or
writes to the SSPBUF are disabled).
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
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19.4.2 OPERATION
The MSSP module functions are enabled by setting
MSSP enable bit, SSPEN (SSPCON<5>).
The SSPCON1 register allows control of the I2C
operation. Four mode selection bits (SSPCON<3:0>)
allow one of the following I2C modes to be selected:
•I
2C Master mode, cl ock = (FOSC/4) x (SSPADD + 1)
•I
2C Slave mode (7-bit address)
•I
2C Slave mode (10-bit address)
•I
2C Slave mode (7-bit address) with Start and
Stop bit interrupts enabled
•I
2C Slave mode (10-bit address) with Start and
Stop bit interrupts enabled
•I
2C Firmware Controlled Master mode, slave is
Idle
Selection of any I2C mode with the SSPEN bit set,
forces the SCL and SDA pins to be open-drain,
provided these pins are programmed to inputs by
setting the appropriate TRISB bits. To ensure proper
operation of the module, pull-up resistors must be
provided externally to the SCL and SDA pins.
19.4.3 SLAVE MODE
In Slave mod e, the SCL and SDA pins mu st be co nfi g-
ured as inputs (TRISB<1:0> set). The MSSP module
will override the input state with the output data when
required (slave-transmitter).
The I2C Slav e mod e hardware w i ll alwa ys generate a n
interrupt on an address match. Through the mode
select bits, the user can also choose to interrupt on
Start and Stop bits
When an address is matched or the data transfer after
an add res s mat ch i s rece ived , th e ha rdw are au tom ati-
cally will generate the Acknowledge (ACK) pulse and
load the SSPBUF register with the received value
currently in the SSPSR register.
Any combination of the following conditions will cause
the MSSP module not to give this ACK pulse:
• The Buffer Full bit, BF (SSPSTAT<0>), was set
before the transfer was received.
• The overflow bi t, SSPOV (SSPCON<6>), was set
before the transfer was received.
In this case, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF (PIR1<3>) is set. The
BF bit is cleared by reading the SSPBUF register , while
bit SSPOV is cleared through software.
The SCL clock input must have a minimum high and
low fo r pro per op erati on. The h igh an d l ow times o f th e
I2C specification, as well as the requirement of the
MSSP module, are shown in timing parameter #100
and parameter #101.
19.4.3.1 Addressing
Once the MSSP module has been enabled, it waits for
a S t art conditio n to occur. Followin g the S t art conditio n,
the 8-bits are shifted into the SSPSR register. All
incoming bits are sampled with the rising edge of the
clock (SCL) line. The value of register SSPSR<7:1> is
compared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match and the BF
and SSPOV bits are clear, the following events occur:
1. The SSPSR register value is loaded into the
SSPBUF register.
2. The Buffer Full bit, BF, is set.
3. An ACK pulse is generated.
4. MSSP Interrupt Flag bit, SSPIF (PIR1<3>), is
set (interrupt is generated, if enabled) on the
falling edge of the ninth SCL pulse.
In 10-bit Address mode, two address bytes need to be
received by the slave. The five Most Significant bits
(MSbs) of the first address byte specify if this is a 10-bit
address. Bit R/W (SSPST A T<2>) must specify a write so
the slave device will receive the second address byte.
For a 10-bit address, the first byte would equal ‘11110
A9 A8 0’, where ‘A9’ and ‘A8’ are the two MSbs of the
address. The sequence of events for 10-bit address is as
follows, with step s 7 through 9 for the slav e-transmitter:
1. Receive first (high) byte of address (bits SSPIF,
BF and bit UA (SSPSTAT<1>) are set).
2. Update the SSPADD register with second (low)
byte of address (clears bit UA and releases the
SCL line).
3. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
4. Receive second (low) byte of address (bits
SSPIF, BF and UA are set).
5. Update t he SSPADD registe r wi th the first (high)
byte of a ddre ss . If m at ch rel ea ses SCL lin e, thi s
will clear bit UA.
6. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
7. Receive Repeated Start condition.
8. Receive first (high) byte of address (bits SSPIF
and BF are set).
9. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
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19.4.3.2 Reception
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleare d. The re ceived ad dress is loa ded in to
the SSPBUF register and the SDA line is held low
(ACK).
When the address byte overflow condition exists, then
the no Ack no w led ge (ACK ) pul se is g iv en. An ov erfl ow
conditi on is define d as eith er bit, BF (SSPSTAT<0>), is
set, or bit, SSPOV (SSPCON1<6>), is set.
An MSSP interrupt is generated for each data transfer
byte. Flag bit, SSPIF (PIR1<3>), must be cleared in
software. The SSPSTAT register is used to determine
the status of the byte.
If SEN is enabled (SSPCON2<0> = 1), RB1/AN10/
INT1/SCK/SCL will be h eld low (clock stretch) following
each data transfer. The clock must be released by
setting bit, CKP (SSPCON<4>). See Section 19.4.4
“Clock Stretching” for more detail.
19.4.3.3 Transmission
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit and pin RB1/AN10/INT1/SCK/
SCL is held low regardles s of SEN (see Section 19.4.4
“Clock Stretching” for more detail). By stretching the
clock , the mast er will be unable to asse rt anothe r cloc k
pulse until the slave is done preparing the transmit
data. The transmit data must be loaded into the
SSPBUF register, which also loads the SSPSR regis-
ter. Then pin RB1/AN10/INT1/SCK/SCL should be
enabled by setti ng bi t, CKP (SSPCON1 <4>). Th e eight
data bits are shifted out on the falling edge of the SCL
input. This ensures that the SDA signal is valid during
the SCL high time (Figure 19-9).
The ACK pulse from the master-receiver is latched on
the rising edge of the nin th SCL input pu lse. If the SDA
line is high (not ACK), then the data transfer is
comple te. In thi s case , when the ACK i s la tc hed by the
slave, the slave logic is reset (resets SSPSTAT regis-
ter) and the slave monitors for another occurrence of
the Start bit. If the SDA line was low (ACK), the next
transmit data must be loaded into the SSPBUF register .
Again, p in R B1/AN1 0/INT1/SCK/SCL mus t b e ena ble d
by setting bit CKP.
An MSSP interrupt is generated for each data transfer
byte. The SSPIF bit must be cleared in software and
the SSPSTAT register is used to determine the status
of the byte. The SSPIF bit is set on the falling edge of
the ninth clock pulse.
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DS39632A-page 208 Advance Information 2004 Microchip Technology Inc.
FIGURE 19-8: I2C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS)
SDA
SCL
SSPIF
BF (SSPSTAT<0>)
SSPOV (SSPCON<6>)
S1234567891 2345 67891 2345 789 P
A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D1 D0
ACK
Receiving Data
ACK
Receiving Data
R/W = 0
ACK
Receiving Address
Cleared in software
SSPBUF is read
Bus master
terminates
transfer
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
D2
6
(PIR1<3>)
CKP (CKP does not reset to ‘0’ wh e n SE N = 0)
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FIGURE 19-9: I2C™ SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS)
SDA
SCL
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
A6 A5 A4 A3 A2 A1 D6 D5 D4 D3 D2 D1 D0
1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 9
SSPBUF is w ritten in software
Cleared in software From SSPIF ISR
Data in
sampled
S
ACK
Transmitting Data
R/W =
1
ACK
Receiving Address
A7 D7
9 1
D6 D5 D4 D3 D2 D1 D0
2 3 4 5 6 7 8 9
SSP BUF is writ te n in s o ft w a r e
Cleared in software From SSPIF ISR
Transmitting Data
D7
1
CKP
P
ACK
CK P is s e t in so f tw a re CKP is s e t in so f tw a r e
SCL held low
while CPU
responds to SSPIF
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DS39632A-page 210 Advance Information 2004 Microchip Technology Inc.
FIGURE 19-10 : I2C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS)
SDA
SCL
SSPIF
BF (SSPSTAT<0>)
S123456789 123456789 12345 789 P
1 1 1 1 0 A9A8 A7 A6A5A4A3 A2A1A0 D7 D6D5D4D3 D1D0
Receive Data Byte
ACK
R/W = 0
ACK
Receive First Byte of Address
Clear ed in software
D2
6
(PIR1<3>) Cleared in software
Receive Second Byte of Address
Cleared by hardware
when SSPADD is updated
with low byte of address
UA (SSPSTAT<1>)
Clock is held low until
update of SSPADD has
taken place
UA is set indicating that
the SSPADD needs to be
updated
UA is set indicating that
SSPADD needs to be
updated
Cleared by hardware when
SSPADD is updated with high
byte of address
SSPBUF is written with
contents of SSPSR Dummy read of SSPBUF
to clear BF flag
ACK
CKP
12345 789
D7 D6 D5 D4 D3 D1 D0
Receive Data Byte
Bus master
terminates
transfer
D2
6
ACK
Cleared in software Cleared in software
SSPOV (SSPCON<6>)
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
(CKP does not reset to ‘0’ when SEN = 0)
Clock is held low until
update of SSPADD has
taken place
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FIGURE 19-11: I2C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS)
SDA
SCL
SSPIF
BF (SSPSTAT<0>)
S123456789 123456789 12345 789 P
1 1 1 1 0 A9A8 A7 A6A5A4A3A2A1A0 1 1 1 1 0A8
R/W = 1
ACK
ACK
R/W = 0
ACK
Receive First Byte of Address
Cleared in software
Bus master
terminates
transfer
A9
6
(PIR1<3>)
Receive Second Byte of Address
Cleared by hardware when
SSPADD is updated with low
byte of address
UA (SSPSTAT<1>)
Clock is held low until
update of SSPA DD has
taken place
UA is set indicating that
the SSPADD needs to be
updated
UA is set indicating that
SSPADD needs to be
updated
Cleared by hardware when
SSPADD is updated with high
byte of address.
SSPBUF is written with
contents of SSPSR Dummy read of SSPBUF
to clear BF flag
Receive First Byte of Address
12345 789
D7 D6 D5 D4 D3 D1
ACK
D2
6
Tran smitting Data Byte
D0
Dummy read of SSPBUF
to clear BF flag
Sr
Cleared in software
Write of SSPBUF
initiates transmit
Clear ed in software
Completion of
clears BF flag
CKP (SSPCON<4>)
CKP is set in software
CKP is automatically cleared in hardware, holding SCL low
Clock is held low until
update of SSPADD has
taken place
data transmission
Clock is held low until
CKP is set to ‘1’
third address sequence
BF flag is clear
at the end of the
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DS39632A-page 212 Advance Information 2004 Microchip Technology Inc.
19.4.4 CLOCK STRETCHING
Both 7 and 10-bit Slave modes implement automatic
clock stretching during a transmit sequence.
The SEN bit (SSPCON2<0>) al lows clock stretch ing to
be enabled during receives. Setting SEN will cause
the SCL pin to be held low at the end of each data
receive sequence.
19.4.4.1 Clock Stretching for 7-bit Slave
Receive Mode (SEN = 1)
In 7-bit Slave Receive mode, on the falling edge of the
ninth clock at the end of the ACK sequence if the BF
bit is set, the CKP bit in the SSPCON1 register is
automatically cleared, forcing the SCL output to be
held low. The CKP being cleared to ‘0’ will assert the
SCL line low. The CKP bit must be set in the user’s
ISR befo re recep tion i s allo wed to co ntinue . By hol ding
the SCL line low, the user has time to service the ISR
and read the contents of the SSPBUF before the
master device can initiate another receive sequence.
This will prevent buffer overruns from occurring (see
Figure 19-13).
19.4.4.2 Clock Stretching for 10-bit Slave
Receive Mode (SEN = 1)
In 10-bit Slave Receive mode during the address
sequence, clock stretching automatically takes place
but CKP is not c lea red . Duri ng t his time, if th e UA b it i s
set after the ninth clock, clock stretching is initiated.
The UA bit is set after receiving the upper byte of the
10-bit address and following the receive of the second
byte of the 10-bit address with the R/W bit cleared to
‘0’. The release of the clock line occurs upon updating
SSPADD. Clock stretching will occur on each data
receive sequence as described in 7-bit mode.
19.4.4.3 Clock Stretching for 7-bit Slave
Transmit Mode
7-bit Sl ave Transmit mo de imp lemen ts c lock stretc hing
by clearing the CKP bit after the falling edge of the
ninth clock if the BF bit is clear. This occurs regardless
of the state of the SEN bit.
The user’s ISR must set the CKP bit before transmis-
sion is allowed to continue. By holding the SCL line
low, the user has time to service the ISR and load the
contents of the SSPBUF before the master device can
initiate another transmit sequence (see Figure 19-9).
19.4.4.4 Clock Stretching for 10-bit Slave
Transmit Mode
In 10-bit Slave Transmit mode, clock stretching is con-
trolled during the first two address sequences by the
state of the UA bit, just as it is in 10-bit Slave Receive
mode. The first two addresses are followed by a third
address sequence which contains the high-order bits
of the 10-bit address and the R/W bit set to ‘1’. After
the third address sequence is performed, the UA bit is
not set, the module is now configured in Transmit
mode and clock stretching is controlled by the BF flag
as in 7-bit Slave Transmit mode (see Figure 19-11).
Note 1: If the user reads the contents of the
SSPBUF before the falling edge of the
ninth clock, thus clearing the BF bit, the
CKP bit will not be cleared and clock
stretching will not occur.
2: The CKP bit can be set in software
regardless of the state of the BF bit. The
user should be careful to clear the BF bit
in the ISR before the next receive
sequence in order to prevent an overflow
condition.
Note: If the user polls the UA bit and clears it by
updating the SSPADD register before the
falling edge of the ni nth c lock oc curs and i f
the user hasn’t cleared the BF bit by read-
ing the SSPBUF register before that time,
then the CKP bit will still NOT be asserted
low. Clock stretching on the basis of the
state of the BF bit only occurs during a
data sequence, not an address sequence.
Note 1: If the u ser lo ads the contents of SSPBUF,
setting the BF bit before the f alling edge of
the ninth clock, the CKP bit will not be
cleared and clock stretching will not occur .
2: The CKP bit can be set in software
regardless of the state of the BF bit.
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19.4.4.5 Clock Synchronization and
the CKP bit
When the CKP bit is cleared, the SCL output is forced
to ‘0’. However, setting the CKP bit will not assert the
SCL output low until the SCL output is already sam-
pled low. Therefore, the CKP bit will not assert the
SCL line until an external I2C master device has
already asserted the SCL line. The SCL output will
remain low until the CKP bit is set and all other
devices on the I2C bus have deasserted SCL. This
ensures that a write to the CKP bit will not violate the
minimum high time requirement for SCL (see
Figure 19-12).
FIGURE 19-12: CLOCK SYNCHRONIZATION TIMING
SDA
SCL
DX-1DX
WR
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SSPCON
CKP
Master device
deasserts clock
Master device
asserts clock
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DS39632A-page 214 Advance Information 2004 Microchip Technology Inc.
FIGURE 19-13 : I2C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS)
SDA
SCL
SSPIF
BF (SSPSTAT<0>)
SSPOV (SSPCON<6>)
S123456789 1 2345 6789 12345 789 P
A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D1 D0
ACK
Receiving Data
ACK
Receiving Data
R/W = 0
ACK
Receiving Address
Cleared in software
SSPBUF is read
Bus master
terminates
transfer
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
D2
6
(PIR1<3>)
CKP
CKP
written
to ‘1’ in
If BF is cleared
prior to the falling
edge of the 9th clock,
CKP will not be reset
to ‘0’ and no clock
stretching will occur
software
Clock is held low until
CKP is set to ‘1’
Clock is not held low
because buffer full bit is
clear prior to falling edge
of 9th clock Clock is not held low
because ACK = 1
BF is set after falling
edge of the 9th clock,
CKP is reset to ‘0’ and
clock stretching occurs
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FIGURE 19-14 : I2C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 10-BIT ADDRESS)
SDA
SCL
SSPIF
BF (SSPSTAT<0>)
S123456789 123456789 12345 789 P
1 1 1 1 0 A9A8 A7 A6A5A4A3A2A1A0 D7D6D5D4D3 D1D0
Receive Data Byte
ACK
R/W = 0
ACK
Receive First Byte of Address
Clear ed in software
D2
6
(PIR1<3>) Cleared in software
Receive Second Byte of Address
Cleared by hardware when
SSPADD is updated with low
byte of address after falling edge
UA (SSPSTAT<1>)
Clock is held low until
update of SSPA DD has
taken place
UA is set indicating that
the SSPADD needs to be
updated
UA is set indicating that
SSPADD needs to be
updated
Cleared by hardware when
SSPADD is updated with high
byte of address after falling edge
SSPBUF is writ ten with
contents of SSPSR Dummy read of SSPBUF
to clear BF flag
ACK
CKP
12345 789
D7 D6 D5 D4 D3 D1 D0
Receive Data Byte
Bus master
terminates
transfer
D2
6
ACK
Cleared in software Cleared in s oftware
SSPOV (SSPCON<6>)
CKP written to ‘1’
Note: An update of th e SS PADD register b efore
the falling edge of the ninth clock will have
no effect on UA and UA will remain set.
Note: An update of the SSPADD
register before the falling
edge of the ninth clock will
have no effect on UA and
UA will remain set. in software
Clock is held low until
update of SSPADD has
taken place
of ninth clock
of ninth clock
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
Dummy read of SSPBUF
to clear BF flag
Clock is held low until
CKP is set to ‘1’Clock is not held low
because ACK = 1
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19.4.5 GENERAL CALL ADDRESS
SUPPORT
The addressing procedure for the I2C bus is such that
the first byte after the Start condition usually
determines which device will be the slave addressed by
the master. The exception is the general call address
which can address all devices. When this address is
used, all devices should, in theory, respond with an
Acknowledge.
The general call address is one of eight addresses
reserved for specific purposes by the I2C protocol. It
consists of all ‘0’s with R/W = 0.
The general call address is recognized when the Gen-
eral Call Ena ble bit (GCEN) is enabled (SSPCON2< 7>
set). Following a Start bit detect, 8 bits are shifted into
the SSPSR and the address is compared against the
SSPADD. It is also compared to the general call
address and fixed in hardware.
If the general call address matches, the SSPSR is
transferre d to the S SPBUF, the BF f lag bit is set (eighth
bit) and on the falling edg e of the ninth bit (ACK b it), the
SSPIF interrupt flag bit is set.
When the i nterrupt is s ervic ed, t he sou r ce f or the int er-
rupt can be checked by reading the contents of the
SSPBUF. The value can be used to determine if the
address was device specific or a general call address.
In 10-bit mode, the SSPADD is required to be updated
for the seco nd half of the address to match an d the UA
bit is set (SSPSTAT<1>). If the general call address is
sampled when the GCEN bit is set, while the slave is
configured in 10-bit Address mode, then the second
half of the address is not necessary, the UA bit will not
be set and the slave will begin receiving data after the
Acknowledge (Figure 19-15).
FIGURE 19-15: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE
(7 OR 10-BIT ADDRESS MODE)
SDA
SCL S
SSPIF
BF (SSPSTAT<0>)
SSPOV (SSPCON1<6>)
Cleared in software
SSPBUF is read
R/W = 0
ACK
General Call Address
Address is compared to General Call Address
GCEN (SSPCON2<7>)
Receiving Data ACK
123456789123456789
D7 D6 D5 D4 D3 D2 D1 D0
after ACK, set inter rupt
‘0’
‘1’
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19.4.6 MASTER MODE
Master mode is enabled by setting and clearing the
appropria te SSPM bit s in SSPCON1 and by set ting the
SSPEN bit. In Master mode, the SCL and SDA lines
are manipulated by the MSSP hardware.
Master mode of operation is supported by interrupt
generation on the detection of the Start and Stop
conditions. The Stop (P) and Start (S) bits are cleared
from a Reset or when the MSSP module is disabled.
Control of the I 2C bus may be taken when the P bit is
set or the bus is Idle, with both the S and P bits clear.
In Firmware Controlled Master mode, user code
conducts all I2C bus operations based on Start and
Stop bit conditions.
Once Master mode is enabled, the user has six
options:
1. Assert a Start condition on SDA and SCL.
2. Assert a Repeated Start condition on SDA and
SCL.
3. Write to the SSPBUF register initiating
transmission of data/address.
4. Configure th e I2C port to receive data.
5. Generate an Acknowledge condition at the end
of a received byte of data.
6. Generate a Stop condition on SDA and SC L.
The following events will cause SSP Interrupt Flag bit,
SSPIF, to be set (SSP interrupt, if enabled):
• Start condition
• Stop condition
• Data transfer byte transmitted/received
• Acknowledge transmit
• Repeat ed Star t
FIGURE 19-16: MSSP BLOCK DIAGRAM (I2C™ MASTER MODE)
Note: The MSSP module, when configured in
I2C Mast er mode, does n ot allow que ueing
of events. For instance, the user is not
allowed to initiate a Start condition and
immediately write the SSPBUF register to
initiate transmission before the Start
condition is complete. In this case, the
SSPBUF will not be written to and the
WCOL bit wi ll be set, indicating that a write
to the SSPBUF did not occur.
Read Write
SSPSR
S tart bit, Stop bit,
Sta r t b i t De te c t
SSPBUF
Internal
Data Bus
Set/Reset , S, P, WCOL (SSPSTAT)
Shift
Clock
MSb LSb
SDA
Acknowledge
Generate
Stop bit Detect
Write Collision Detect
Clock Arbitration
S tate Counter for
end of XMIT/RCV
SCL
SCL In
Bus Collision
SDA In
Receive Enable
Clock Cntl
Clock Arbitrate/WCOL Detect
(hold off clock source)
SSPADD<6:0>
Baud
Set SSPIF, BCLIF
Reset ACKSTAT, PEN (SSPCON2)
Rate
Generator
SSPM3:SSPM0
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19.4.6.1 I2C Master Mode Operation
The master device generates all of the serial clock
pulses and the S t a rt and Stop condit ions. A tra nsfer i s
ended with a Stop condition or with a Repeated Start
condition. Since the Repeated Start condition is also
the beginning of the next serial transfer , the I2C bus will
not be rel eased.
In Master Transmitter mode, serial data is output
through SDA, while SCL outputs the serial clock. The
first byte transmitted contains the slave address of the
recei vin g dev ice ( 7 bits) and the Rea d/Writ e (R/ W) bit.
In this case, the R/W bit will be logi c ‘0’. S eri al d ata is
transmi tted 8 b it s at a ti me . Afte r each byte is trans mit-
ted, an Acknowledge bit is received. Start and Stop
conditions are output to indicate the beginning and the
end of a serial tran sfer.
In Master Rec eive mode, t he first byte transm itted con-
tains the slave address of the transmitting device
(7 bits) and the R /W bit. In this case, the R/W bit wil l be
logic ‘1’ Thus, the first byte transmitted is a 7-bit slave
addr ess f oll owed by a ‘1’ to indicate receive bit. Serial
data is rece ived via S DA, while SCL o utp uts the se ri al
clock. Seria l data is receive d 8 bits at a time. After eac h
byte is received, an Acknowledge bit is transmitted.
Start and Stop conditions indicate the beginning and
end of transmission.
The Baud R ate Generator us ed for the SPI mod e oper-
ation is used to set the SCL clock frequency for either
100 kHz, 400 kHz or 1 MHz I2C operation. See
Section 19.4. 7 “Bau d Rate” for more detail.
A typical transmit sequence would go as follows:
1. The user generates a Start condition by setting
the Start Enable bit, SEN (SSPCON2<0>).
2. SSPIF is set. The MSSP module will wait the
required start time before any other operation
takes place.
3. The user loads the SSPBUF with the slave
address to transmit.
4. Address is shi fted out the SDA pin unt il all 8 bit s
are transmitted.
5. The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
SSPCON2 register (SSPCON2<6>).
6. The MSSP mo dule g enerate s an interrup t at th e
end of th e ninth c lock cyc le by settin g the SSPIF
bit.
7. The user loads the SSPBUF with eight bits of
data.
8. Data is sh ifted ou t the SDA pin until all 8 bit s are
transmitted.
9. The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
SSPCON2 register (SSPCON2<6>).
10. The MSSP modul e gene rates an int errupt a t the
end of th e ninth c lock cyc le by settin g the SSPIF
bit.
11. The user generates a Stop condition by setting
the Stop Enable bit, PEN (SSPCON2<2>).
12. Interrupt is ge nerated once the S to p cond ition i s
complete.
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19.4.7 BAUD RATE
In I2C Master mode, the Baud Rate Generator (BRG)
reload value is placed in the lower 7 bits of the
SSPADD register (Figure 19-17). When a write occurs
to SSPBUF, the Baud Rate Generator will automatically
begin c oun tin g. Th e BR G c oun ts down to ‘0’ an d s tops
until an other re load h as t aken pl ace. Th e BRG c ount i s
decremented twice per instruction cycle (TCY) on the
Q2 and Q4 clocks. In I2C Master mode, the BRG is
reloaded automatically.
Once the given operation is complete (i.e., transmis-
sion of th e last dat a bit is followed by ACK), the int ernal
clock will automatically stop counting and the SCL pin
will rema in in it s last state.
Table 19-3 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPADD.
FIGURE 19-17: BAUD RATE GENERATOR BLOCK DIAGRAM
TABLE 19-3: I2C CLOCK RATE W/BRG
SSPM3:SSPM0
BRG Down Counter
CLKO FOSC/4
SSPADD<6:0>
SSPM3:SSPM0
SCL
Reload
Control Reload
FCY FCY*2 BRG Value FSCL
(2 Rollovers of BRG)
10 MHz 20 MHz 19h 400 kHz(1)
10 MHz 20 MHz 20h 312.5 kHz
10 MHz 20 MHz 3Fh 100 kHz
4 MHz 8 MHz 0Ah 400 kHz(1)
4 MHz 8 MHz 0Dh 308 kHz
4 MHz 8 MHz 28h 100 kHz
1 MHz 2 MHz 03h 333 kHz(1)
1 MHz 2 MHz 0Ah 100 kHz
1 MHz 2 MHz 00h 1 MHz(1)
Note 1: The I2C interface does not conform to the 400 kHz I2C specification (which applies to rates greater than
100 kHz) in all details, but may be used with care where higher rates are required by the application.
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19.4.7.1 Clock Arbitration
Clock arbitration occurs when the master, during any
receive, transmit or Repeated Start/Stop condition,
deasserts the SCL pin (SCL allowed to float high).
When the SCL pin is allowed to float high, the Baud
Rate Generator (BRG) is suspended from counting
until the SCL pin is actually sampled high. When the
SCL pin is sampled high, the Baud Rate Generator is
reloaded with the contents of SSPADD<6:0> and
begins counting. This ensures that the SCL high time
will always be at least one BRG rollover count in the
event that the clock is held low by an external device
(Figure 19-18).
FIGURE 19-18: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
SDA
SCL
SCL deasserted but slave holds
DX-1DX
BRG
SCL is sampled high, reload takes
place and BRG starts its count
03h 02h 01h 00h (hold off) 03h 02h
Reload
BRG
Value
SCL low (clock arbitration) SCL allowed to transition high
BRG decrements on
Q2 and Q4 cycles
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19.4.8 I2C MASTER MODE START
CONDITION TIMING
To initiate a Start condition, the user sets the Start
Enable bit, SEN (SSPCON2<0>). If the SDA and SCL
pins are sampled high, the Baud Rate Generator is
reloaded with the cont ent s of SSPADD<6:0> and st arts
its count. If SCL and SD A ar e bo th s am pl ed hig h w he n
the Baud Rate Generator times out (TBRG), the SDA
pin is driven low. The action of the SDA being driven
low whil e SC L is hig h is the Sta rt con di tion and cau ses
the S bit (SSPSTAT<3>) to be set. Following this, the
Baud Rate Generator is reloaded with the contents of
SSPADD<6:0> and resum es it s cou nt. Wh en the Bau d
Rate Generator times out (TBRG), the SEN bit
(SSPCON2<0>) will be automatically cleared by
hardware, the Baud Rate Generator is suspended,
leavin g th e SD A l in e h eld lo w and th e Start co ndi tio n i s
complete.
19.4.8.1 WCOL Status Flag
If the user writes the SSPBUF when a Start sequence
is in progress, the W C OL is s et an d the co nte nt s of the
buffer are unchanged (the write doesn’t occur).
FIGURE 19-19: FIRST START BIT TIMING
Note: If at the beginning of the Start condition,
the SDA and SCL pins are already sam-
pled low , or if during the S tart condition, the
SCL line is sampled low before the SDA
line is driven low, a bus collision occurs,
the Bus Collision Interrupt Flag, BCLIF, is
set, the Start condition is aborted and the
I2C module is reset into its Idle state.
Note: Because queueing of events is not
allowed, writing to the lower 5 bits of
SSPCON2 is disabled until the Start
conditi on is complete .
SDA
SCL
S
TBRG
1st bit 2nd bit
TBRG
SDA = 1, At completion of Start bit,
SCL = 1
Write to SSPBUF occurs here
TBRG
hardware clears SEN bit
TBRG
Write to SEN bit occurs here Set S bit (SSPSTAT<3>)
and sets SSPIF bit
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19.4.9 I2C MASTER MODE REPEATED
START CONDITION TIMING
A Repeated Start condition occurs when the RSEN bit
(SSPCON2<1>) is programmed high and the I2C logic
module is in the Idle state. When the RSEN bit is set,
the SCL pin is asserted lo w. When the SCL pin is sam-
pled low, the Baud Rate Generator is loaded with the
contents of SSPADD<5:0> and begins counting. The
SDA pin is released (brought high) for one Baud Rate
Generator coun t (TBRG). When th e Baud Rate Gene ra-
tor times out, if SDA is sampled high, the SCL pin will
be deasserted (brought high). When SCL is sampled
high, the Baud Rate Generator is reloaded with the
contents of SSPADD<6:0> and begins counting. SDA
and SCL must be sampled high for one TBRG. This
action is then followed by assertion of the SDA pin
(SDA = 0) for one TBRG while SCL is high. Following
this, the RSEN bit (SSPCON2<1>) will be automatically
cleared and the Baud Rate Generator will not be
reloaded, leaving the SDA pin held low. As soon as a
Start condition is detected on the SDA and SCL pins,
the S bit (SSPSTAT<3>) will be set. The SSPIF bit will
not be set until the Baud Rate Generator ha s timed out.
Immediately following the SSPIF bit getting set, the user
may write the SSPBUF with the 7-bit address in 7-bit
mode or the default first address in 10-bit mode. After the
first eight bits are transmitted and an ACK is received,
the user may then transmit an additional eight bits of
address (10-bit mode) or eight bit s of dat a (7-bit mode).
19.4.9.1 WCOL Status Flag
If the user writes the SSPBUF when a Repeated Start
sequence is in progress, the WCOL is set and the
contents of the buffe r are un chang ed (the w rite doe sn ’t
occur).
FIGURE 19-20: REPEAT START CONDITION WAVEFORM
Note 1: If RSEN is programmed while any other
event is in progress, it will not take effect.
2: A bus collision during the Repeated Start
conditi on occ urs if:
• SDA is sampled low when SCL go es
from low to high.
• SCL goes low before SDA is
asserted low. This may indicate that
another master is attempting to
transmit a data ‘1’.
Note: Because queueing of events is not
allowed, writing of the lower 5 bits of
SSPCON2 is disabled until the Repeated
Start condition is complete.
SDA
SCL
Sr = Repeated Start
Write to SSPCON2
Writ e to SSPBUF occurs here
Falling edge of ninth clock,
end of Xmit
At completion of Start bit,
hardw are clea rs R SEN bi t
1st bit
Set S (SSPSTAT<3>)
TBRG
TBRG
SDA = 1,
SDA = 1,
SCL (no change). SCL = 1
occurs here.
TBRG TBRG TBRG
and sets SSPIF
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19.4.10 I2C MASTER MODE
TRANSMISSION
Transmission of a data byte, a 7-bit address or the
other half of a 10-bit address is acc omplished by simpl y
writing a value to the SSPBUF register. This action will
set the Buf fer Ful l flag bi t, BF and allo w the Baud Rate
Generator to begin counting and start the next trans-
mission. Each bit of address/data will be shifted out
onto the SDA pin after the falling edge of SCL is
asserted (see data hold time specification parameter
#106). SCL is held low for one Baud Rate Generator
rollove r count (TBRG). Data should be valid before SCL
is released high (see data setup time specification
param eter #107) . When the SC L pin is released hi gh, it
is held that way for TBRG. The data on the SDA pin
must remain stable for that duration and some hold
time after the next falli ng ed ge of SCL. After the eigh th
bit is shifted out (the falling edge of the eighth clock),
the BF flag is cleared and the master releases SDA.
This allows the slave device being addressed to
respond with an ACK bit duri ng th e nint h bit ti me if an
address match occurred, or if data was received
properly. The status of ACK is written into the ACKDT
bit on the falling edge of the ninth clock. If the master
receive s an Ack nowled ge, the Acknow ledg e S tatus bit,
ACKSTA T, is cleared. If not, the bit i s set. After the ninth
clock, the SSPIF bit is set and the master clock (Baud
Rate Generator) is suspended until the next data byte
is loaded into the SSPBUF, leaving SCL low and SDA
unchanged (Figure 19-21).
After the write to the SSPBUF, each bit of address will
be shifted out on th e fal lin g ed ge o f SCL unt il al l s even
address bits and the R/W bit ar e complet ed. On the fall-
ing edge of the eighth clock, the master will deassert
the SDA pin, allowing the slave to respond with an
Acknowledge. On the falling edge of the ninth clock, the
master will sample the SDA pin to see if the address
was rec ognized by a sla ve. The st atus of the ACK bit is
loaded into the ACKSTAT status bit (SSPCON2<6>).
Following the falling edge of the ninth clock transmis-
sion of the address, the SSPIF is set, the BF flag is
cleared and th e Baud Ra te Genera tor is t urned of f until
another write to the SSPBUF takes p lace, holdi ng SCL
low and allowing SDA to float.
19.4.10.1 BF Status Flag
In Transmit mode, the BF bit (SSPSTAT<0>) is set
when the CPU writes to SSPBUF and is cleared when
all 8 bits are shifted out.
19.4.10.2 WCOL Status Flag
If the user writes the SSPBUF when a transmit is
already in progress (i.e., SSPSR is still shifting out a
data byte), the WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
WCOL must be cleared in software.
19.4.10.3 ACKSTAT Status Flag
In T ran smit mod e, the ACKSTAT bit (SSPCON2<6>) is
cleared when the slave has sent an Acknowledge
(ACK =0) and is set when the slav e does not Acknowl-
edge (ACK = 1). A slave sends an Acknowledge when
it has recognized its address (including a general call),
or when the slave has properly received its data.
19.4.11 I2C MASTER MODE RECEPTION
Master mode recepti on is enabl ed by progra mmin g the
Receive Enable bit, RCEN (SSPCON2<3>).
The Baud Rate Generator begins counting and on each
rollove r, the state of the SCL pin chang es (high - to-l ow/
low-to-high) and data is shifted into the SSPSR. After
the falling edge of the eighth clock, the receive enable
flag is automatically cleared, the contents of the
SSPSR are loaded into the SSPBUF, the BF flag bit is
set, the SSPIF flag bi t is set and the Baud Ra te Gener-
ator is s uspen ded from countin g, hold ing SC L low. The
MSSP is now in Idle state awaiting the next command.
When the buffer is read by the CPU, the BF flag bit is
automatically cleared. The user can then send an
Acknowledge bit at the end of reception by setting the
Acknowledge sequence enable bit, ACKEN
(SSPCON2<4>).
19.4.11.1 BF Status Flag
In receiv e op eration, the BF bit is set w he n an add res s
or data byte is loaded into SSPBUF from SSPSR. It is
cleared when the SSPBUF register is read.
19.4.11.2 SSPOV Status Flag
In receive operation, the SSPOV bit is set when 8 bits
are received into the SSPSR and the BF flag bit is
already set from a previo us reception.
19.4.11.3 WCOL Status Flag
If the user writes the SSPBUF when a receive is
already in progress (i.e., SSPSR is still shifting in a dat a
byte), th e WCOL bi t is set an d the conte nts of th e buffer
are unchanged (the write doesn’t occur).
Note: The MSSP module must be in an Idle state
before the RCEN bit is set or the RCEN bit
will be disregarded.
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FIGURE 19-21 : I2C™ MASTER MODE WAVEFORM (T RANSMISSION, 7 OR 10-BIT ADDRESS)
SDA
SCL
SSPIF
BF (SSPSTAT<0>)
SEN
A7 A6 A5 A4 A3 A2 A1 ACK = 0D7 D6 D5 D4 D3 D2 D1 D0
ACK
Transmitting Data or Second Half
R/W = 0Transmit Address to Slave
123456789 123456789 P
Cleared in software service routine
SSPBUF is written in software
from SSP interrup t
After Start condition, SEN cleared by hardware
S
SSPBUF written with 7-bit address and R/W
start transmit
SCL held low
while CPU
responds to SSPIF
SEN = 0
of 10-bit Address
Write SSPCON2<0> SEN = 1
Start condition begins From slave, clear ACKSTAT bit SSPCON2<6>
ACKSTAT in
SSPCON2 = 1
Cleared in softwar e
SSPBUF written
PEN
Cleared in software
R/W
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FIGURE 19-22 : I2C™ MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)
P
9
87
6
5
D0
D1
D2
D3D4
D5
D6D7
S
A7 A6 A5 A4 A3 A2 A1
SDA
SCL 1234567891234567891234
Bus master
terminates
transfer
ACK Receiving Data from Slave
Receiving Data from Slave D0
D1
D2
D3D4
D5
D6D7
ACK
R/W = 1
Transmit Address to Slave
SSPIF
BF
ACK is not sent
Write to SSPCON2<0> (SEN = 1)
Write to SSPBUF occurs here A C K fr om Sla ve
Master configured as a receiver
by programming SSPCON2<3> (RCEN = 1)PEN bit = 1
written here
Data shifted in on falling edge of CLK
Cleared in software
S t art XMIT
SEN = 0
SSPOV
SDA = 0, SCL = 1
while CPU
(SSPSTAT<0>)
ACK
Last bit is shifted into SSPSR and
contents are unloaded into SSPBUF
Cleared in software
Clear ed in software
Set SSPIF interrupt
at end of receive
Set P bit
(SSPSTAT<4>)
and SSPIF
Cleared in
software
ACK from Master
Set SS PIF at end
Set SSPIF interrupt
at end of Acknowledge
sequence
Set SSPIF interrupt
at end of Acknow-
ledge sequence
of receive
Set ACKEN, start Acknowledge sequence
SSPOV is set because
SSPBUF is still full
SDA = ACK DT = 1
RCEN cleared
automatically
RCEN = 1, start
next receive
Write to SSPCON2<4>
to start Acknowledge sequence
SDA = ACKDT (SSPCON2<5>) = 0
RCEN cleared
automatically
responds to SSPIF
ACKEN
Begin Start Condition
Cleared in software
SDA = ACKDT = 0
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19.4.12 ACKNOWLEDGE SEQUENCE
TIMING
An Acknowledge sequence is enabled by setting the
Acknowledge sequence enable bit, ACKEN
(SSPCON2<4>). When this bit is set, the SCL pin is
pulled low and the contents of the Acknowledge data bit
are presented on the SDA pin. If the use r wishes to gen-
erate an Acknowledge, then the ACKDT bit should be
cleared. If not, the user should set the ACKDT bit before
starting an Acknowledge sequence. The Baud Rate
Generator then counts for one rollover period (TBRG)
and the SCL pin is deasserted (pulled high). When the
SCL pin is sampled high (clock arbitration), the Baud
Rate Generator counts for TBRG. The SCL pin is then
pulled low . Following this, the ACKEN bit is a utomatically
cleared, the Baud Rate Generator is turned off and the
MSSP module then goes into Idle mode (Figure 19-23).
19.4.12.1 WCOL Status Flag
If the user writes the SSPBUF when an Acknowledge
sequence is in progress, then WCOL is set and the
contents of the buffe r are un chang ed (the w rite doe sn’t
occur).
19.4.13 STOP CONDITION TIMING
A Stop bit is asserted on the SDA pin at the end of a
receive/transmit by setting the Stop Enable bit, PEN
(SSPCON2<2>). At the end of a receive/transmit, the
SCL line is held low after the falling edge of the ninth
clock. When the PEN bit is set, the master will assert
the SDA line low. When the SDA line is sampled low,
the Baud R ate Gen erat or i s rel oad ed and count s do w n
to ‘0’. When the Baud Rate Generator times out, the
SCL pin will be broug ht high and on e TBRG (Baud R ate
Generator rollover count) later, the SDA pin will be
deasserted. When the SDA pin is sampled high while
SCL is high, the P bit (SSPSTAT<4>) is set. A TBRG
later, the PEN bit is cleared and the SSPIF bit is set
(Figure 19-24).
19.4.13.1 WCOL Status Flag
If the user writes the SSPBUF when a Stop sequence
is in progress, then the WCOL bit is set and the
contents of the buffe r are un chang ed (the w rite doe sn ’t
occur).
FIGURE 19-23: ACKNOWLEDGE SEQUENCE WAVEFORM
FIGURE 19-24: STOP CONDITION RECEIVE OR TRANSMIT MODE
Note: TBRG = one Baud Rate Generator period.
SDA
SCL
Set SS PIF at the
Acknowledge sequence starts here,
write to SSPCON2 ACKEN automatically cleared
Cleared in
TBRG TBRG
end of receive
ACK
8
ACKEN = 1, ACKDT = 0
D0
9
SSPIF
software S et SS PIF at the end
of Acknowledge sequence
Cleared in
software
SCL
SDA
SDA asserted low before rising edge of clock
Write to SSPCON2,
set PEN
Falling edge of
SCL = 1 for TBRG, followed by SDA = 1 for TBRG
9th clock
SCL broug ht hi gh afte r TBRG
Note: TBRG = one Baud Rate Generator period.
TBRG TBRG
after SDA sampled high. P bit (SSPSTAT<4>) is set.
TBRG
to setup Stop condition
ACK
P
TBRG
PEN bit (SSPCON2<2>) is cleared by
hardware and the SSPIF bit is set
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19.4.14 SLEEP OPERATION
While in Sleep mode, the I2C module can receive
addresses or data and when an address match or
complete byte transfer occurs, wake the processor
from Sleep (if the MSSP interrupt is enabled).
19.4.15 EFFECT OF A RESET
A Reset disable s the MSSP module and terminates the
current transfer.
19.4.16 MUL T I-MAS TER MO DE
In Multi-Master mode, the interrupt generation on the
detection of the Start and Stop conditions allows the
deter mination of when the bus i s free. The S top (P) and
Start (S) bits are cleared from a Reset or when the
MSSP module is disabled. Control of the I2C bus may
be taken when the P bit (SSPSTAT<4>) is set, or the
bus is Idle, with both the S and P bits clear. When the
bus is busy, enabling the SSP interrupt will generate
the interrupt when the Stop condition occurs.
In multi-master operation, the SDA line must be
monitored for arbitration to see if the signal level is the
expected output level. This check is performed in
hardware with the result placed in the BCLIF bit.
The states where arbitration can be lost are:
• Address Transfer
• Data Transfer
• A Start Cond ition
• A Repeated Start Condition
• An Acknowledge Condition
19.4.17 MULTI - M A STER C OMMUN ICATION,
BUS COLLI SION AND BU S
ARBITRATION
Multi-Master mode support is achieved by bus arbitra-
tion. When the master outputs address/data bits onto
the SDA pin, arbitration takes place when the master
outputs a ‘1’ on SDA, by letting SDA float high and
another master asserts a ‘0’. When the SCL pin floats
high, data should be stable. If the expected data on
SDA is a ‘1’ and the da t a s am ple d on th e SDA pin = 0,
then a bus collision has taken pl ace. The master wil l set
the Bus Collision Interrupt Flag, BCLIF and reset the
I2C port to its Idle state (Figure 19-25).
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDA and SCL lines are deasserted and the
SSPBUF can b e written to . When the us er servic es th e
bus collision Interrupt Service Routine and if the I2C
bus is free, the user can resume communication by
asserting a Start condition.
If a Start, Repeated Start, Stop or Acknowledge
condition was in progress when the bus collision
occurred, the condition is aborted, the SDA and SCL
lines are deasserted and the respective control bits in
the SSPCON2 register are cleared. When the user ser-
vices the bus collision Interrupt Service Routine and if
the I2C bus is free, the user can resume com munication
by asserting a Start condition.
The master will continue to monitor the SDA and SCL
pins. If a Stop condition occurs, the SSPIF bit will be set.
A write to the SSPBUF will start the transmission of
data at the first data bit regardless of where the
transmitter left off when the bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detectio n of Start and S top con ditions allows the determi-
nation o f when th e bus is free. Control of the I2C bus can
be taken when the P bit is set in the SSPSTAT register,
or the bus is Idl e a nd the S and P bi t s a re c lea red .
FIGURE 19-25: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
SDA
SCL
BCLIF
SDA released
SDA line pulled low
by another source
Sample SDA. While SCL is high,
data doesn’t match what is driven
Bus collision has occurred.
Set bus collision
interrupt (BCLIF)
by the master.
by master
Data changes
while SCL = 0
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19.4.17.1 Bus Collision During a Start
Condition
During a Start condition, a bus collision occurs if:
a) SDA o r SCL are sampled low at the b eginning of
the Start condition (Figure 19-26).
b) SCL is sam pl ed l ow before SDA is as se rted low
(Figure 19-27).
During a Start condition, both the SDA and the SCL
pins are monitored.
If the SDA pin is already low, or the SCL pin is already
low, then all of the following occur:
• the Start c ondition is aborted,
• the BCLIF flag is set and
• the MSSP module is reset to its Idle state
(Figure 19-26).
The Start condition begins with the SDA and SCL pins
deasserted. When the SDA pin is sampled high, the
Baud Rate Generator is loaded from SSPADD<6:0>
and counts down to ‘0’. If the SCL pin is sampled low
while SDA is high, a bus collision occurs because it is
assumed that another master is attempting to drive a
data ‘1’ during the Start condition.
If the SDA pin is sampled low during this count, the
BRG is reset and the SDA line is asserted early
(Figure 19-28). If, however , a ‘1’ is sampled on the SDA
pin, the SDA pin is asserted low at the end of the BRG
count. The Baud Rate Generator is then reloaded and
counts down to ‘0’ and during this tim e, if th e SCL pin s
are sampled as ‘0’, a bus collision does not occur. At
the end of the BRG count, the SCL pin is asserted low.
FIGURE 19-26: BUS COLLISION DURING START CONDITION (SDA ONLY)
Note: The reason that bus collision is not a factor
during a Start condition is that no two bus
masters can assert a Start condition at the
exact same time. Therefore, one master
will always assert SDA before the other.
This condition does not cause a bus
collision because the two masters must be
allowed to arbitrate the first address
following the Start condition. If the address
is the same, arbitration must be allowed to
continue into the data portion, Repeated
Start or S to p condition s.
SDA
SCL
SEN SDA sampled low before
SDA goes low before the SEN bit is set.
S bit and SSPIF set because
SSP module reset into Idle state.
SEN cleared aut omati cally because of bus coll isi on.
S bit and SSPIF set because
Set SEN, enable Start
condition if SDA = 1, SCL = 1
SDA = 0, SCL = 1.
BCLIF
S
SSPIF
SDA = 0, SCL = 1.
SSPIF and BCLIF are
cleared in software
SSPIF and BCLIF are
cleared in software
Set BCLIF,
Start condition. Set BCLIF.
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FIGURE 19-27: BUS COLLISION DURING START CONDITION (SCL = 0)
FIGURE 19-28: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
SDA
SCL
SEN bus collision occurs. Set BCLIF.
SCL = 0 before SDA = 0,
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
TBRG TBRG
SDA = 0, SCL = 1
BCLIF
S
SSPIF
Interrupt cleared
in software
bus collision occurs. Set BCLIF.
SCL = 0 before BRG time-out,
‘0’ ‘0’
‘0’‘0’
SDA
SCL
SEN
Set S
Less th an TBRG TBRG
SDA = 0, SCL = 1
BCLIF
S
SSPIF
S
Interrupts cleared
in software
set SS PIF
SDA = 0, SCL = 1,
SCL pulled low after BRG
time-out
Set SS PIF
‘0’
SDA pulled low by other master .
Reset BRG and assert SDA.
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
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19.4.17.2 Bus Collision During a Repeated
Start Condition
During a Repeated Start condition, a bus collision
occu rs if:
a) A low level is sampled on SDA when SCL goes
from low level to high level.
b) SCL goes low before SDA is asserted low,
indicating that another master is attempting to
transmit a data ‘1’.
When the user dea sserts SDA and the pin is a llowed to
float high, the BRG is loaded with SSPADD<6:0> and
count s down to ‘0’. Th e SCL pin is then deasserted an d
when sampled high, the SDA pin is sampled.
If SDA is low, a bus collision has occurred (i.e., another
master is attempting to transmit a data ‘0’, see
Figure 19-29). If SDA is sampled high, the BRG is
reloaded and begins counting. If SDA goes from high-to-
low before the BRG times out, no bus collision occurs
because no two masters can assert SDA at exactly the
same time.
If SCL goes from high-to-low before the BRG times out
and SDA has not al ready been asserted, a bus collision
occurs. In this case, another master is attempting to
tran smit a data ‘1’ during the Repeated Start condition
(see Figure 19-30).
If, at the end of the BRG time-out, both SCL and SDA
are still high, the SDA pin is driven low and the BRG is
reloaded and begins counting. At the end of the count,
regardless of the status of the SCL pin, the SCL pin is
driven low and the Repeated Start condition is
complete.
FIGURE 19-29: BUS COLLISION DURING A REPEATED ST ART CONDITION (CASE 1)
FIGURE 19-30: BUS COLLISION DURING REPEATED START CONDITION (CASE 2)
SDA
SCL
RSEN
BCLIF
S
SSPIF
Sample SDA when SCL goes high.
If SDA = 0, set BCLIF and release SDA and SCL.
Cleared in software
‘0’
‘0’
SDA
SCL
BCLIF
RSEN
S
SSPIF
Interrupt cleared
in software
SCL goes low before SDA,
set BCLIF. Release SDA and SCL.
TBRG TBRG
‘0’
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19.4.17.3 Bus Collision During a Stop
Condition
Bus collision occurs during a Stop condition if:
a) After the SDA pin has been deasserted and
allowed to float high, SDA is sampled low after
the BRG has timed out.
b) After the SCL pin is deasserted, SCL is sampled
low before SDA goes high.
The Stop condition begins with SDA asserted low.
When SDA is sampled low, the SCL pin is allowed to
floa t. Wh en t he p in i s sa mpled hig h (c loc k arbi tr atio n),
the Baud R ate Generator is load ed with SSP AD D<6:0>
and counts down to ‘0’. After the BRG times out, SDA
is sampled. If SDA is sampled low, a bus collision has
occurred. This is due to another master attempting to
drive a data ‘0’ (Figure 19-31). If the SCL pin is
sample d lo w befo re SD A is allowed to flo at hi gh , a bu s
collis ion occ urs. This is anoth er case of anot her m aster
attempting to drive a data ‘0’ (Figure 19-32).
FIGURE 19-31: BUS COLLISION DURING A STOP CONDITION (CASE 1)
FIGURE 19-32: BUS COLLISION DURING A STOP CONDITION (CASE 2)
SDA
SCL
BCLIF
PEN
P
SSPIF
TBRG TBRG TBRG
SDA asserted low
SDA sampled
low after TBRG,
set BCLIF
‘0’
‘0’
SDA
SCL
BCLIF
PEN
P
SSPIF
TBRG TBRG TBRG
Assert SDA SCL goes low before SDA goes high,
set BCLIF
‘0’
‘0’
PIC18F2455/2550/4455/4550
DS39632A-page 232 Advance Information 2004 Microchip Technology Inc.
NOTES:
2004 Microchip Technology Inc. Advance Information DS39632A-page 233
PIC18F2455/2550/4455/4550
20.0 ENHANCED UNIVE R S A L
SYNCHRONOUS RECEIVER
TRANSMITTER (EUSART)
The Universal Synchronous Asynchronous Receiver
Transmitter (USART) module is one of the two serial
I/O modules. (USART is also known as a Serial
Communications Interface or SCI.) The USART can be
configured as a full-duplex asynchronous system that
can communicate with peripheral devices, such as
CRT terminals and personal computers. It can also be
configured as a half-duplex synchronous system that
can co mmun icate with periph eral de vice s, such as A/D
or D/A integrated circuits, serial EEPROMs and so on.
The EUSART module implements additional features,
including automatic baud rate detection and calibra-
tion, automatic wake-up on Sync Break reception and
12-bit Break character transmit. These make it ideally
suited for use in Local Interconnect Network bus (LIN
bus) systems.
The EUSART can be configured in the following
modes:
• Asynchronous (full-duplex) with:
- Auto-wake-up on character reception
- Auto-baud calibration
- 12-bit Break charac ter tran sm is si on
• Synchronous – Master ( half-duplex) with
selectable clock polarity
• Synchronous – Slave (half-duplex) with select able
clock polarity
The pins of the Enha nced USAR T are mu ltiple xed with
PORTC. In order to configure RC6/TX/CK and
RC7/RX/DT/SDO as a USART:
• bit SPEN (RCSTA<7>) must be set (= 1)
• bit TRISC<7> must be set (= 1)
• bit TRISC<6> must be cleared (= 0) for
Asynchronous and Synchronous Master modes,
or set (= 1) for Synchronous Slave mode
The operation of the Enhanced USART module is
controlled through three registers:
• Transmit Status and Control (TXSTA)
• Receive Status and Control (RCSTA)
• Baud Rate Control (BAUDCON)
These are detailed on the following pages in
Register 20-1, Register 20-2 and Register 20-3,
respectively.
Note: The EUSART control will automatically
reconfigure the pin from input to output as
needed.
PIC18F2455/2550/4455/4550
DS39632A-page 234 Advance Information 2004 Microchip Technology Inc.
REGISTER 20-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-1 R/W-0
CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D
bit 7 bit 0
bit 7 CSRC: Clock Source Select bit
Asynchronous mode:
Don’t care.
Synchronous mode:
1 = Master mode (clock generated internally from BRG)
0 = Slave mode (clock from external source)
bit 6 TX9: 9-bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
bit 5 TXEN: Transmit Enable bit
1 = Transmit enabled
0 = Transmit disabled
Note: SREN/CREN overrides TXEN in Sync mode.
bit 4 SYNC: EUSART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
bit 3 SENDB: Send Break Character bit
Asynchronous mode:
1 = Send Sync Break on next transmission (cleared by hardware upon completion)
0 = Sync Break transmission completed
Synchronous mode:
Don’t care.
bit 2 BRGH: High Baud Rate Select bit
Asynchronous mode:
1 = High speed
0 = Low speed
Synchronous mode:
Unused in this mode .
bit 1 TRMT: Transmit Shift Register Status bit
1 = TSR empty
0 = TSR full
bit 0 TX9D: 9th bit of Transmit Data
Can be address/data bi t or a parity bit.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
2004 Microchip Technology Inc. Advance Information DS39632A-page 235
PIC18F2455/2550/4455/4550
REGISTER 20-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x
SPEN RX9 SREN CREN ADDEN FERR OERR RX9D
bit 7 bit 0
bit 7 SPEN: Serial Port Enable bit
1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins)
0 = Serial port disabled (held in Reset)
bit 6 RX9: 9-bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
bit 5 SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care.
Synchronous mode – Master:
1 = En able s singl e receive
0 = Disables single receive
This bit is cleared after reception is complete.
Synchronous mode – Slave:
Don’t care.
bit 4 CREN: Continuous Receiv e Enab le bit
Asynchronous mode:
1 = Enables receiver
0 = Disables receiver
Synchronous mode:
1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0 = Disables con t in uou s r ece iv e
bit 3 ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1 = Enables address detection, enables interrupt and loads the receive buffer when RSR<8>
is set
0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit
Asynchronous mode 9-bit (RX9 = 0):
Don’t care.
bit 2 FERR: Framing Error bit
1 = Framing error (can be update d by reading RCREG regi ster and receive next valid byte)
0 = No framing error
bit 1 OERR: Overrun Error bit
1 = Overrun error (can be cleared by clearing bit CREN)
0 = No overrun error
bit 0 RX9D: 9th bit of Received Data
This can be address/data bit or a parity bit and must be calculated by user firmware.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC18F2455/2550/4455/4550
DS39632A-page 236 Advance Information 2004 Microchip Technology Inc.
REGISTER 20-3: BAUDCON: BAUD RATE CONTROL REGISTER
R/W-0 R-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0
ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN
bit 7 bit 0
bit 7 ABDOVF: Auto-Baud Acquisition Rollover Status bit
1 = A BRG rollover has occurred during Auto-Baud Rate Detect mode
(must be cleared in software)
0 = No BRG rollover has occurred
bit 6 RCIDL: Receive Operation Idle Status bit
1 = Receive operation is Idle
0 = Receive operation is active
bit 5 Unimplemented: Read as ‘0’
bit 4 SCKP: Synchronous Clock Po larity Select bit
Asynchronous mode:
Unused in this mode.
Synchronous mode:
1 = Idle state for clock (CK) is a high level
0 = Idle state for clock (CK) is a low level
bit 3 BRG16: 16-bit Baud Rate Register Enable bit
1 = 16-bit Baud Rate Generator – SPBRGH and SPBRG
0 = 8-bit Baud Rate Generator – SPBRG only (Compatible mode), SPBRGH value ignored
bit 2 Unimplemented: Read as ‘0’
bit 1 WUE: Wake-up Enable bit
Asynchronous mode:
1 = EUSART will continue to sample the RX pin – interrupt generated on falling edge; bit
cleared in hardware on following rising edge
0 = RX pin not monitored or rising edge detected
Synchronous mode:
Unused in this mode.
bit 0 ABDEN: Auto-Baud Detect Enable bit
Asynchronous mode:
1 = Enable baud rate measurement on the next character. Requires reception of a Sync field
(55h); cleared in hardware upon completion
0 = Baud rate measurement disabled or completed
Synchronous mode:
Unused in this mode.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
2004 Microchip Technology Inc. Advance Information DS39632A-page 237
PIC18F2455/2550/4455/4550
20.1 Baud Rate Genera to r ( BRG)
The BRG is a dedicated 8-bit or 16-bit generator that
supports both the Asynchronous and Synchronous
modes of the EUSART. By default, the BRG operates
in 8-bit mode; setting the BRG16 bit (BAUDCON<3>)
selects 16-bit mode.
The SPBRGH:SPBRG regi ste r p air co ntro ls the perio d
of a free running timer. In Asynchronous mode, bits
BRGH (TXSTA<2>) and BRG16 (BAUDCON<3>) also
control the baud rate. In Synchronous mode, BRGH is
ignored. Table 20-1 shows th e fo rmu la f or c om putation
of the baud rate for different EUSART modes which
only a pply i n Mas te r mode (int ernall y gen erated clock ).
Given the desired baud rate and FOSC, the nearest
integer value for the SPBRGH:SPBRG registers can be
calculated using the formulas in Table 20-1. From this,
the error in baud rate can be determined. An example
calculation is shown in Example 20-1. Typical baud
rates and error values for the various Asynchronous
modes are shown in Table 20-2. It may be advanta-
geous to use the high baud rate (BRGH = 1) or the
16-bit BRG to reduce the baud rate error, or achieve a
slow baud rate for a fast oscillator frequency.
Writing a new value to the SPBRGH:SPBRG registers
causes the BRG timer to be reset (or cleared). This
ensures the BRG does not wait for a timer overflow
before outputting the new baud rate.
20.1.1 OPERATION IN POWER MANAGED
MODES
The device clock is used to generate the desired baud
rate. When one of the power managed modes is
entered, the new clock source may be operating at a
different frequency. This may require an adjustment to
the value in the SPBRG register pair.
20.1.2 SAMPLING
The data on the RX pin is sampled three times by a
majority detect circuit to determine if a high or a low
level is present at the RX pin.
TABLE 20-1: BAUD RATE FORMULAS
EXAMPLE 20-1: CALCULATING BAUD RATE ERROR
TABLE 20-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Configuration Bits BRG/EUSART Mode Ba ud Rate Formula
SYNC BRG16 BRGH
000 8-bit/Asynchronous FOSC/[64 (n + 1)]
001 8-bit/Asynchronous FOSC/[16 (n + 1)]
010 16-bit/Asynchronous
011 16-bit/Asynchronous FOSC/[4 (n + 1)]10x 8-bit/Synchronous
11x 16-bit/Synchronous
Legend: x = Don’t care, n = value of SPBRGH:SPBRG register pair
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset
Values
on page
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 53
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 53
BAUDCON ABDOVF RCIDL —SCKP BRG16 —WUE ABDEN 53
SPBRGH EUSART Baud Rate Generator Register High Byte 53
SPBRG EUSART Baud Rate Generator Register Low Byte 53
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the BRG.
For a device wi th FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG:
Desire d Baud Rate = FOSC/(64 ([SPBRGH:SPBRG] + 1)
Solving for SPBRGH:SPBRG:
X = ((FOSC/Desired Baud Rate)/64) – 1
= ((160 00000 /9600)/ 6 4) – 1
= [25.042] = 25
Calculated Baud Rate = 16000000/(64 (25 + 1))
= 9615
Error = (Calculated Baud Rate – Desired Baud Rate) /Desired Ba ud Rate
= (9615 – 96 00)/9600 = 0.16 %
PIC18F2455/2550/4455/4550
DS39632A-page 238 Advance Information 2004 Microchip Technology Inc.
TABLE 20-3: BAUD RATES FOR ASYNCHRONOUS MODES
BAUD
RATE
(K)
SYNC = 0, BRGH = 0, BRG16 = 0
FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
0.3————————————
1.2 — — — 1.221 1.73 255 1.202 0.16 129 1201 -0.16 103
2.4 2.441 1.73 255 2.404 0.16 129 2.404 0.16 64 2403 -0.16 51
9.6 9.615 0.16 64 9.766 1.73 31 9.766 1.73 15 9615 -0.16 12
19.2 19.531 1.73 31 19.531 1.73 15 19.531 1.73 7 — — —
57.6 56.818 -1.36 10 62.500 8.51 4 52.083 -9.58 2 — — —
115.2 125.000 8.51 4 104.167 -9.58 2 78.125 -32.18 1 — — —
BAUD
RATE
(K)
SYNC = 0, BRGH = 0, BRG16 = 0
FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
0.3 0.300 0.16 207 300 -0.16 103 300 -0.16 51
1.2 1.202 0.16 51 1201 -0.16 25 1201 -0.16 12
2.4 2.404 0.16 25 2403 -0.16 12 — — —
9.6 8.929 -6.99 6 — — — — — —
19.2 20.833 8.51 2 — — — — — —
57.6 62.500 8.51 0 — — — — — —
115.2 62.500 -45.75 0 — — — — — —
BAUD
RATE
(K)
SYNC = 0, BRGH = 1, BRG16 = 0
FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
0.3————————————
1.2————————————
2.4 — — — — — — 2.441 1.73 255 2403 -0.16 207
9.6 9.766 1.73 255 9.615 0.16 129 9.615 0.16 64 9615 -0.16 51
19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19230 -0.16 25
57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55555 3.55 8
115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 — — —
BAUD
RATE
(K)
SYNC = 0, BRGH = 1, BRG16 = 0
FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
0.3 — — — — — — 300 -0.16 207
1.2 1.202 0.16 207 1201 -0.16 103 1201 -0.16 51
2.4 2.404 0.16 103 2403 -0.16 51 2403 -0.16 25
9.6 9.615 0.16 25 9615 -0.16 12 — — —
19.2 19.231 0.16 12 — — — — — —
57.6 62.500 8.51 3 — — — — — —
115.2 125.000 8.51 1 — — — — — —
2004 Microchip Technology Inc. Advance Information DS39632A-page 239
PIC18F2455/2550/4455/4550
BAUD
RATE
(K)
SYNC = 0, BRGH = 0, BRG16 = 1
FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
0.3 0.300 0.00 8332 0.300 0.02 4165 0.300 0.02 2082 300 -0.04 1665
1.2 1.200 0.02 2082 1.200 -0.03 1041 1.200 -0.03 520 1201 -0.16 415
2.4 2.402 0.06 1040 2.399 -0.03 520 2.404 0.16 259 2403 -0.16 207
9.6 9.615 0.16 259 9.615 0.16 129 9.615 0.16 64 9615 -0.16 51
19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19230 -0.16 25
57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55555 3.55 8
115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 — — —
BAUD
RATE
(K)
SYNC = 0, BRGH = 0, BRG16 = 1
FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
0.3 0.300 0.04 832 300 -0.16 415 300 -0.16 207
1.2 1.202 0.16 207 1201 -0.16 103 1201 -0.16 51
2.4 2.404 0.16 103 2403 -0.16 51 2403 -0.16 25
9.6 9.615 0.16 25 9615 -0.16 12 — — —
19.2 19.231 0.16 12 — — — — — —
57.6 62.500 8.51 3 — — — — — —
115.2 125.000 8.51 1 — — — — — —
BAUD
RATE
(K)
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1
FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
0.3 0.300 0.00 33332 0.300 0.00 16665 0.300 0.00 8332 300 -0.01 6665
1.2 1.200 0.00 8332 1.200 0.02 4165 1.200 0.02 2082 1200 -0.04 1665
2.4 2.400 0.02 4165 2.400 0.02 2082 2.402 0.06 1040 2400 -0.04 832
9.6 9.606 0.06 1040 9.596 -0.03 520 9.615 0.16 259 9615 -0.16 207
19.2 19.193 -0.03 520 19.231 0.16 259 19.231 0.16 129 19230 -0.16 103
57.6 57.803 0.35 172 57.471 -0.22 86 58.140 0.94 42 57142 0.79 34
115.2 114.943 -0.22 86 116.279 0.94 42 113.636 -1.36 21 117647 -2.12 16
BAUD
RATE
(K)
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1
FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
0.3 0.300 0.01 3332 300 -0.04 1665 300 -0.04 832
1.2 1.200 0.04 832 1201 -0.16 415 1201 -0.16 207
2.4 2.404 0.16 415 2403 -0.16 207 2403 -0.16 103
9.6 9.615 0.16 103 9615 -0.16 51 9615 -0.16 25
19.2 19.231 0.16 51 19230 -0.16 25 19230 -0.16 12
57.6 58.824 2.12 16 55555 3.55 8 — — —
115.2 111.111 -3.55 8 — — — — — —
TABLE 20-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
PIC18F2455/2550/4455/4550
DS39632A-page 240 Advance Information 2004 Microchip Technology Inc.
20.1.3 AUTO-BAUD RATE DETECT
The Enhan ced USART modu le s up ports the au tomati c
detection and calibration of baud rate. This feature is
active only in Asynchronous mode and while the WUE
bit is clear.
The automatic baud rate measurement sequence
(Figure 20-1) begins whenever a Start bit is received
and the ABDEN bit is set. The calculation is
self-averaging.
In the Auto-Bau d Rate Detect (ABD) mode, the clock to
the BRG is rev ersed. Rather than th e BRG clocking the
incomi ng RX signal, the RX signal is timing the BRG. In
ABD mode, the internal Baud Rate Generator is used
as a coun ter to time the bit p eriod of the inco ming serial
byte stream.
Once th e ABDEN bit is set, th e st ate machine w ill c lear
the BRG and look for a Start bit. The Auto-Baud Rate
Detection must receive a byte with the value 55h
(ASCII “U”, which is also the LIN bus Sync character)
in order to calculate the proper bit rate. The measure-
ment is taken over both a low and a high bit time in
orde r to min imiz e any effec ts caus ed by as ymme try of
the incoming signal. After a Start bit, the SPBRG
begins counting u p, using th e preselec ted clock source
on the first rising ed ge of RX. Aft er eight bi ts on the RX
pin or the fifth rising edge, an accumulated value total-
ling the proper BRG period is left in the
SPBRGH:SPBRG register pair. Once the 5th edge is
seen (this should correspond to the Stop bit), the
ABDEN bit is automatically cleared.
If a rollover of the BRG occurs (an overflow from FFFFh
to 0000h), the event is trapped by the ABDOVF status
bit (BAUDCON<7>). It is set in hardware by BRG roll-
over s and can be set or cleare d by the use r in softwa re.
ABD mode rem ains a ctive after roll over even t s and the
ABDEN bit remains set (Figure 20-2).
While calibrating the baud rate period, the BRG regis-
ters are clocked at 1/8th the preconfigured clock rate.
Note that the BRG clock will be configured by the
BRG16 and BRGH bits. Independent of the BRG16 bit
setting, bo th the SPBRG and SPBRGH will b e u se d as
a 16-bit counter. This allows the user to verify that no
carry occurred for 8-bit modes by checking for 00h in
the SPBRGH register. Refer to Table 20-4 for counter
clock rates to the BRG.
While the ABD sequence takes place, the EUSART
state ma chi ne is held in Idl e. T he RCI F in terr upt i s set
once the fifth rising edge on RX is detected. The value
in the RCREG needs to be read to clear the RCIF
interrupt. The contents of RCREG should be discarded.
TABLE 20-4: BRG COUNTER
CLOCK RATES
20.1.3.1 ABD and EUSART Transmission
Since the BRG clock is reversed during ABD acquisi-
tion, the EUSART transmitter cannot be used during
ABD. This means that whenever the ABDEN bit is set,
TXREG ca nnot be writte n to. Users shou ld also ensu re
that ABDEN does not become set during a transmit
sequenc e. Faili ng to do this m ay resul t in unp redict able
EUSART operation.
Note 1: If the WUE bit is set with the ABDEN bit,
Auto-Baud Rate Detection will occur on
the byte following the Break character.
2: It is up to the user to determine that the
incomi ng character ba ud rate is within th e
range of the selected BRG clock source.
Some combinations of oscillator
frequency and EUSART baud rates are
not poss ible due to b it error r ates. O veral l
system timing and communication baud
rates must be taken into consideration
when using the Auto-Baud Rate
Detection feature.
BRG16 BRGH BRG Counter Clock
00 FOSC/512
01 FOSC/128
10 FOSC/128
11 FOSC/32
Note: During the ABD sequence, SPBRG and
SPBRGH are both used as a 16-bit counter,
independent of BRG16 setting.
2004 Microchip Technology Inc. Advance Information DS39632A-page 241
PIC18F2455/2550/4455/4550
FIGURE 20-1: AUTOMATIC BAUD RATE CALCULATION
FIGURE 20-2: BRG OVERFLOW SEQUENCE
BRG Value
RX pin
ABDEN bit
RCIF bit
Bit 0 Bit 1
(Interrupt)
Read
RCREG
BRG Clock
Start
Auto-Cleared
Set by User
XXXXh 0000h
Edge #1 Bit 2 Bit 3
Edge #2 Bit 4 Bit 5
Edge #3 Bit 6 Bit 7
Edge #4 Stop Bit
Edge #5
001Ch
Note: The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE = 0.
SPBRG XXXXh 1Ch
SPBRGH XXXXh 00h
Start Bit 0
XXXXh 0000h 0000h
FFFFh
BRG Clock
ABDEN bit
RX pin
ABDOVF bit
BRG Value
PIC18F2455/2550/4455/4550
DS39632A-page 242 Advance Information 2004 Microchip Technology Inc.
20.2 EUSART Asynchronous Mode
The Asynchronous mode of operation is selected by
clearing the SYNC bit (TXSTA<4>). In this mode, the
EUSART uses standard Non-Return-to-Zero (NRZ)
format (one St art bit, eight or nine data bits and one S top
bit). The most common data format is 8 bits. An on-chip
dedic at ed 8-bit/1 6-b it Ba ud R at e Ge nerator ca n be u se d
to derive standard baud rate frequencies from the
oscillator.
The EUSART transmits and receives the LSb first. The
EUSART’s transmitter and receiver are functionally
independent but use the same data format and baud
rate. Th e Ba ud Rat e Ge ne ra tor pr odu ces a cl ock , eit h er
x16 or x 64 of the bi t shift r ate depend ing on the BRGH
and BRG16 bit s (TXSTA<2> and BAUDCON<3>). Parity
is not supported by the hardware but can be
impl em en te d i n softwa r e an d st ored as th e 9th d at a bit .
When operating in Asynchronous mode, the EUSART
module consists of the following important elements:
• Baud Rate Generator
• Sampling Circuit
• Asynchronous Transmitter
• Asynchronous Receiver
• Auto-Wake-up on Sync Break Character
• 12-bit Break Character Transmit
• Auto-Ba ud Rate Detec tio n
20.2.1 EUSART ASYNCHRONOUS
TRANSMITTER
The EUSART transmitter block diagram is shown in
Figure 20-3. The heart of the transmitter is the Transmit
(Serial) Shi ft Reg ist er (TSR). T he Shift regi ste r obtains
its data from the Read/Write Transmit Buffer register,
TXREG. The TXREG register is loaded with data in
software. The TSR register is not loaded until the Stop
bit has been transmitted from the previous load. As
soon as the Stop bit is transmitted, the TSR is loaded
with new data from the TXREG register (if available).
Once the TXREG reg iste r tran sfers th e data to the TSR
register (occurs in one TCY), the TXREG register is empty
and the TXIF flag bit (PIR1<4>) is set. This interrupt can
be enab led or di sabled by s etting o r clearing the in terrupt
enable bit, TXIE (PIE1<4>). TXIF will be set regardless of
the state of TXIE; it cannot be cleared in software. TXIF
is also not cleared immediately upon lo ading TXREG, but
becomes valid in the second instruction cycle following
the lo ad i nstru ct ion. Poll ing T XIF imme diate ly f ollo win g a
load o f TXREG w i ll re tu rn in va lid res ul t s .
While TXIF i ndi cates the st atus of the TXRE G r egi ste r,
another bit, TRMT (TXSTA<1>), shows the status of
the TSR register. TRMT is a read-only bit which is set
when the TSR register is empty. No interrupt logic is
tied to this bit so the user has to poll this bit in order to
determine if the TSR register is empty.
To set up an Asynchronous Transmission:
1. Initialize the SPBRGH:SPBRG registers for the
appropriate baud rate. Set or clear the BRGH
and BRG16 bits, as required, to achieve the
desired baud rate.
2. Enable the asy nch ron ous seri al port by clearin g
bit SYNC and setting bit SPEN.
3. If interrupts are desired, set enable bit TXIE.
4. If 9-bit transmission is desired, set transmit bit
TX9. Can be used as address/data bit.
5. Enable the transmission by setting bit TXEN
which will also set bit TXIF.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Load data to the TXREG register (starts
transmission).
8. If using interrup ts, ensu re that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
FIGURE 20-3: EUSART TRANSMIT BLOCK DIAGRAM
Note 1: The TSR register is not mapped in data
memory so it is not available to the user.
2: Flag bit T XIF is set when en able bit TXEN
is set.
TXIF
TXIE
Interrupt
TXEN Baud Rate CLK
SPBRG
Baud Rate Generator
MSb LSb
Data Bus
TXREG Register
TSR Register
(8) 0
TX9
TRMT SPEN
TX pin
Pin Buffer
and Control
8
• • •
SPBRGH
BRG16
TX9D
2004 Microchip Technology Inc. Advance Information DS39632A-page 243
PIC18F2455/2550/4455/4550
FIGURE 20-4: ASYNCHRONOUS TRANSMISSION
FIGURE 20-5: ASYNCHRONOUS TRANSMISSION (BACK TO BACK)
TABLE 20-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Word 1 Stop bit
Word 1
Transmit Shift Reg
Start bit bit 0 bit 1 bit 7/8
Write to TXREG Word 1
BRG Output
(Shift Clock)
TX
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
TRMT bit
(Tran smi t Shi ft
Reg. Empty Flag)
1 TCY
(pin)
Transmit Shift Reg.
Write to TXREG
BRG Output
(Shift Clock)
TX
TXIF bit
(Interrupt Reg. Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Word 1 Word 2
Word 1 Word 2
Stop bit Start bit
Transmit Shift Reg.
Word 1 Word 2
bit 0 bit 1 bit 7/8 bit 0
Note: Thi s timing diagram sh ows two consecutive trans missions.
1 TCY
1 TCY
(pin) Start bit
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 54
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 54
IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 54
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 53
TXREG EUSART Transmit Register 53
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 53
BAUDCON ABDOVF RCIDL —SCKP BRG16 —WUE ABDEN 53
SPBRGH EUSART Baud Rate Generator Register High Byte 53
SPBRG EUSART Baud Rate Generator Register Low Byte 53
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission.
Note 1: Reserved in 28-pin devices; always maintain these bits clear.
PIC18F2455/2550/4455/4550
DS39632A-page 244 Advance Information 2004 Microchip Technology Inc.
20.2.2 EUSART ASYNCHRONOUS
RECEIVER
The receiver block diagram is shown in Figure 20-6.
The data is rece ive d on th e RX pin an d driv es the da t a
recovery block. The data recovery block is actually a
high-sp eed shifter op erating at x16 times the baud rate,
whereas the main receive serial shifter operates at the
bit rate or at FOSC. This mode would typically be used
in RS-232 systems.
To set up an Asynchronous Reception:
1. Initialize the SPBRGH:SPBRG registers for the
appropriate baud rate. Set or clear the BRGH
and BRG16 bits, as required, to achieve the
desired baud rate.
2. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
3. If interrupts are desired, set enable bit RCIE.
4. If 9-bit reception is desired, set bit RX9.
5. Enable the reception by setting bit CREN.
6. Flag bit RCIF will be set when reception is
complete and an interrupt will be generated if
enable bit R CI E was set.
7. Read the RCSTA register to get the 9th bit (if
enabled) and determine if any error occurred
during r eception.
8. Read the 8-bit received data by reading the
RCREG register.
9. If any error occurred, clear the error by clearing
enable bit C RE N.
10. If using interrupt s, ensu re that t he GIE a nd PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
20.2.3 SETTING UP 9-BIT MODE WITH
ADDRESS DETECT
This m ode w o uld ty pi cally b e us ed in R S-48 5 syste ms.
To set up an Asynchronous Reception with Address
Detect Enable:
1. Initialize the SPBRGH:SPBRG registers for the
appropriate baud rate. Set or clear the BRGH
and BRG16 bits, as required, to achieve the
desired baud rate.
2. Enable the asy nch ron ous seri al port by clearin g
the SYNC bit and setting the SPEN bit.
3. If in terrupts a re requ ired, se t the RCE N bit and
select the desired pr iority level with the RCIP bit.
4. Set the RX9 bit to enable 9-bit reception.
5. Set the ADDEN bit to enable address detect.
6. Enable reception by setting the CREN bit.
7. The RCIF bit will be set when reception is
complete. The interrupt will be Acknowledged if
the RCIE and GIE bits are set.
8. Read the RCSTA register to determine if any
error occurred during reception, as well as read
bit 9 of data (if applicable).
9. Read RCREG to determine if the device is being
addressed.
10. If any error occurred, clear the CREN bit.
11. If the device has been addressed, clear the
ADDEN bit to allow all received data into the
receive buffer and interrupt the CPU.
FIGURE 20-6: EUSART RECEIVE BLOCK DIAGRAM
x64 B aud R ate CLK
Baud Rate Generator
RX
Pin Buffer
and Control
SPEN
Data
Recovery
CREN OERR FERR
RSR Register
MSb LSb
RX9D RCREG Regis ter FIFO
Interrupt RCIF
RCIE Data Bus
8
÷ 64
÷ 16
or Stop Start
(8) 7 1 0
RX9
• • •
SPBRGSPBRGH
BRG16
or
÷ 4
2004 Microchip Technology Inc. Advance Information DS39632A-page 245
PIC18F2455/2550/4455/4550
FIGURE 20-7: ASYNCHRONOUS RECEPTION
TABLE 20-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Start
bit bit 7/8
bit 1bi t 0 bit 7/8 bit 0
Stop
bit
Start
bit Start
bit
bit 7/8 Stop
bit
RX (pin)
Rcv Buffer Reg
Rcv Shift Reg
Read Rcv
Buffer Reg
RCREG
RCIF
(Inte rru pt Flag )
OERR bit
CREN
Word 1
RCREG Word 2
RCREG
Stop
bit
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word
causing the OERR (overrun) bit to be set.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 54
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 54
IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 54
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 53
RCREG EUSART Receive Register 53
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 53
BAUDCON ABDOVF RCIDL —SCKP BRG16 — WUE ABDEN 53
SPBRGH EUSART Baud Rate Generator Register High Byte 53
SPBRG EUSART Baud Rate Generator Register Low Byte 53
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
Note 1: Reserved in 28-pin devices; always maintain these bits clear.
PIC18F2455/2550/4455/4550
DS39632A-page 246 Advance Information 2004 Microchip Technology Inc.
20.2.4 AUTO-WAKE-UP ON SYNC BREAK
CHARACTER
During Sleep mode, all clocks to the EUSART are
suspended. Because of this, the Baud Rate Generator
is inactive and a proper byte reception cannot be
performed. The auto-wake-up feature allows the con-
troller to wake-up due to activity on the RX/DT line
while the EUSAR T is operat ing in Asy nchronous m ode.
The auto-wake-up feature is enabled by setting the
WUE bit (BAUDCON<1>). Once set, the typical receive
sequence on RX/DT is disabled and the EUSART
remains in an Idle s tate, monitor ing for a wake-up event
independent of the CPU mode. A wake-up event
consists of a high-to-low transition on the RX/DT line.
(This coincides with the start of a Sync Break or a
Wake -up Sign al cha rac ter for the LIN protocol.)
Following a wake-up event, the module generates an
RCIF interrupt. The interrupt is generated synchro-
nously to the Q clocks in normal operating modes
(Figure 20-8) and asynchronously, if the device is in
Sleep mode (Figure 20-9). The interrupt condition is
cleared by reading the RCREG register.
The WUE bit is automatically cleared once a low -to-high
transition is observed on the RX line following the
wake-up event. At this point, the EUSART module is in
Idle mode and returns to normal operation. This signals
to the user that the Sync Break event is over.
20.2.4.1 Special Considerations Using
Auto-Wake-up
Since auto-wake-up functions by sensing rising edge
transitions on RX/DT, information with any state
changes before the Stop bit may signal a false
end-of-character and cause data or framing errors. To
work properly , therefore, the initial character in the trans-
mission must be all ‘0’s. This can be 00h (8 bytes) for
standard RS-232 devices or 000h (12 bits) for LIN bus.
Oscillator start-up time must also be considered,
especially in applications using oscillators with longer
start-up intervals (i.e., XT or HS mode). The Sync
Break (or Wake-up Signal) character must be of
suf f icient length and be foll ow ed by a suffic ien t inte rva l
to allow enough time for the selected oscillator to start
and provide proper initialization of the EUSART.
20.2.4.2 Special Considerations Using
the WUE Bit
The timing of WUE and RCIF events may cause some
confusion when it comes to determining the validity of
receive d data. As noted , setting the WUE bit places the
EUSART in an Idle mode. The wake-up event causes
a receiv e interrupt by setting th e RCIF bit. The WU E bit
is cleared after this when a rising edge is seen on
RX/DT. The interrupt condition i s t hen cle are d by rea d-
ing the R CREG register. Ordinarily, the dat a in RCREG
will be dummy data and should be discarded.
The fact that the WUE bit has been cleared (or is still
set) and the RCIF flag is set should not be used as an
indicator of the integrity of the data in RCREG. Users
should consider implementing a parallel method in
firmware to verify received data integrity.
To assu re t hat n o act ual data i s los t, che ck th e RCI DL
bit to ve rify th at a receive ope ration is not in proc es s. If
a receive operation is not occurring, the WUE bit may
then be set just prior to entering the Sleep mode.
FIGURE 20-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING NORMAL OPERATION
FIGURE 20-9: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
WUE bit(1)
RX/DT Line
RCIF
Note 1: The EUSART remains in Idle while the WUE bit is set.
Bit set by user Auto-Cleared
Cleared due to user read of RCREG
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
WUE bit(2)
RX/DT Line
RCIF
Sleep Command Executed
Note 1: If the wake-up event requires long oscillator warm-up time, the auto-clear of the WUE bit can occur while the stposc signal is still active.
This sequence should not depend on the presence of Q clocks.
2: The EUSART remains in Idle while the WUE bit is set.
Sleep Ends
Auto-Cleared
Note 1
Cleared due to user read of RCREG
Bit set by user
2004 Microchip Technology Inc. Advance Information DS39632A-page 247
PIC18F2455/2550/4455/4550
20.2.5 BREAK CHARACTER SEQUENCE
The Enhanced EUSART module has the capability of
sending the special Break character sequences that
are required by the LIN bus standard. The Break char-
acter trans mit co nsist s of a Start bit, follo wed by twelv e
‘0’ bits and a Stop bit. The Frame Break character is
sent whene ve r the SEN DB an d TXEN bi t s (TXSTA<3>
and TXSTA<5>) are set while the Transmit Shift
register is loa ded with data. Note that the v alu e o f da ta
written to TXREG will be ignored and all ‘0’s will be
transmitted.
The SENDB bit i s automaticall y reset by ha rdware after
the correspon ding Stop bit is s ent . Th is al lo w s t he us er
to preloa d the trans mit FIFO with the n ext transm it byte
following the Break character (typically, the Sync
character in the LIN specification).
Note that the data value written to the TXREG for the
Break character is ignored. The write simply serves the
purpose of initiating the proper sequence.
The TRMT bit indicates when the transmit operation is
active or Idle, just as it does during normal transmis-
sion. See Figure 20-10 for the timing of the Break
character sequence.
20.2.5.1 Br ea k and Sync Transmi t Seque nc e
The following sequence will send a message frame
header ma de up of a Break, followe d by an Auto-Bau d
Sync byte. This sequence is typical of a LIN bus
master.
1. Configure the EUSART for the desired mode.
2. Set the TXEN and SENDB bits to set up the
Break character.
3. Load the TXREG with a dummy character to
initiate transmission (the value is ignored).
4. Write ‘55h’ to TXREG to load the Sync character
into the transm it FIFO buf fe r.
5. After the Break ha s been s ent, the SENDB bit i s
reset by hardware. The Sync character now
transmi t s in the prec onfigured mode.
When the TXR EG b ec om es em pty, as indi cated by th e
TXIF, the next data byte can be written to TXREG.
20.2.6 RECEIVING A BREAK CHARACTER
The Enhanced USART module can receive a Break
character in two ways.
The first method forces configuration of the baud rate
at a freq uency of 9/ 13 the typi cal spee d. This allow s for
the Stop bit transition to be at the correct sampling
location (13 bits for Break versus Start bit and 8 data
bits for typic al dat a ) .
The second method uses the auto-wake-up feature
describ ed in Section 20.2.4 “Auto-Wake-up on Sync
Break Character”. By enabling this feature, the
EUSART will sample the ne xt two transitions on RX/DT,
cause an RCIF interru pt and receiv e the n ext da ta byte
follow ed by ano the r interru pt.
Note that following a Break character, the user will
typically want to enable the Auto-Baud Rate Detect
feature. Fo r both methods, th e user can set the ABD bit
once the TXIF interrupt is observed.
FIGURE 20-10: SEND BREAK CHARACTER SEQUENCE
Write to TXREG
BRG Output
(Shift Clock)
Start Bit Bit 0 Bit 1 Bit 11 Stop Bit
Break
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
TX (pin)
TRMT bit
(Transmi t Sh ift
Reg. Empty Flag)
SENDB
(Transmi t Sh ift
Reg. Empty Flag)
SENDB sampled here Auto-Cleared
Dummy Write
PIC18F2455/2550/4455/4550
DS39632A-page 248 Advance Information 2004 Microchip Technology Inc.
20.3 EUSART Synchronous
Master Mode
The Synchronous Master mode is entered by setting
the CSRC bit (TXSTA<7>). In this mode, the data is
transmitted in a half-duplex manner (i.e., transmission
and reception do not occur at the same time). When
transmitting data, the reception is inhibited and vice
versa. Synchronous mode is entered by setting bit
SYNC (TXSTA<4>). In addition, enable bit SPEN
(RCSTA<7>) is set in order to con figure the TX and RX
pins to CK (clock) and DT (data) lines, respectively.
The Master mode indicates that the processor trans-
mits the master clock on the CK line. Clock polarity is
selected with the SCKP bit (BAUDCON<4>); setting
SCKP sets the Idle state on CK as high, while clearing
the bit se ts t he Idle st ate as low. This option is provide d
to support Microwire devices with this module.
20.3.1 EUSART SYNCHRONOUS MASTER
TRANSMISSION
The EUSART transmitter block diagram is shown in
Figure 20-3. The heart of the transmitter is the Transmit
(Serial) Shi ft Reg ist er (TSR). T he Shift regi ste r obtains
its data from the Read/Write Transmit Buffer register,
TXREG. The TXREG register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREG (if available).
Once the TXR EG register tr ansfers the dat a to the TSR
register (occurs in one TCYCLE), the TXREG is empty
and the TXIF flag bit (PIR1<4>) is set. The interru pt can
be enabled or disabled by setting or clearing the inter-
rupt enab le bit, T XIE (PIE1<4> ). TXIF is set rega rdles s
of the state of enable bit TXIE; it cannot be cleared in
softwa re. It wi ll res et onl y w hen n ew dat a is load ed into
the TXREG register.
While flag bit TXIF indicates the status of the TXREG
register, another bit, TRMT (TXSTA<1>), shows the
status of the TSR register . TRMT is a read-only bit which
is set when the TSR is empty. No interrupt logic is tied to
this bit so the user has to poll this bit in order to
determine if the TSR register is empty. The TSR is not
mapped in data memory so it is not available to the user .
To set up a Synchronous Master Transmission:
1. Initialize the SPBRGH:SPBRG registers for the
appropriate baud rate. Set or clear the BRG16
bit, as required, to achieve the desired baud
rate.
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
3. If interrupts are desired, set enable bit TXIE.
4. If 9-bit transmission is desired, set bit TX9.
5. Enable the transmission by setting bit TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. S tart transmission b y loading dat a to the TXREG
register.
8. If using interrup ts, ensu re that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
FIGURE 20-11: SYNCHRONOUS TRANSMISSION
bit 0 bit 1 bit 7
Word 1
Q1Q2 Q3Q4 Q1 Q2Q3 Q4Q1Q2 Q3Q4 Q1Q2 Q3 Q4Q1Q2 Q3 Q4 Q3 Q4 Q1 Q2 Q3Q4 Q1Q2 Q3Q4 Q1 Q2Q3Q4 Q1 Q2Q3 Q4Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4
bit 2 bit 0 bit 1 bit 7
RC7/RX1/DT1
RC6/TX1/CK1 pin
Write to
TXREG Reg
TXIF bit
(Interrupt Flag)
TXEN bit ‘1’ ‘1’
Word 2
TRMT bit
Write Word 1 Write Word 2
Note: Sync Master mode, SPBRG = 0, continuous transmission of two 8-bit words.
pin
RC6/TX1/CK1 pin
(SCKP = 0)
(SCKP = 1)
2004 Microchip Technology Inc. Advance Information DS39632A-page 249
PIC18F2455/2550/4455/4550
FIGURE 20-12: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
TABLE 20-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
RC7/RX1/DT1 pin
RC6/TX1/CK1 pin
Write to
TXRE G r e g
TXIF b it
TRMT bit
bit 0 bit 1 bit 2 bit 6 bit 7
TXEN bit
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 54
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 54
IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 54
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 53
TXREG EUSART Transmit Register 53
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 53
BAUDCON ABDOVF RCIDL —SCKPBRG16—WUE ABDEN 53
SPBRGH EUSART Baud Rate Generator Register High Byte 53
SPBRG EUSART Baud Rate Generator Register Low Byte 53
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.
Note 1: Reserved in 28-pin devices; always maintain these bits clear.
PIC18F2455/2550/4455/4550
DS39632A-page 250 Advance Information 2004 Microchip Technology Inc.
20.3.2 EUSART SYNCHRONOUS MASTER
RECEPTION
Once Synchronous mode is selected, reception is
enabled by setting ei ther the Single Receive Enable bit,
SREN (RCSTA<5>), or the Continuous Receive
Enable bit, CREN (RCSTA<4>). Data is sampled on the
RX pin on the falling edge of the clock.
If enable bit SREN is set, only a single word is received.
If enable bit CREN is set, the reception is continuous
until CREN is cleared. If both bits are set, then CREN
takes precedence.
To set up a Synchronous Master Reception:
1. Initialize the SPBRGH:SPBRG registers for the
appropriate baud rate. Set or clear the BRG16
bit, as required, to achieve the desired baud rate.
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
3. Ensure bits CREN and SREN are clear.
4. If interrupts are desired, set enable bit RCIE.
5. If 9-bit reception is desired, set bit RX9.
6. If a single reception is required, set bit SREN.
For continuous reception, set bit CREN.
7. Interrupt fla g bit RCIF will be se t when receptio n
is complete and an interrupt will be generated if
the enable bit RCIE was set.
8. Read the RCSTA register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
9. Read the 8-bit received data by reading the
RCREG register.
10. If any error occurred, clear the error by clearing
bit CREN.
11. If using interrup ts, ensure tha t the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
FIGURE 20-13: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
TABLE 20-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
NameBit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
Reset
V alues on
page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 54
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 54
IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 54
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 53
RCREG EUSART Receive Register 53
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 53
BAUDCON ABDOVF RCIDL — SCKP BRG16 —WUE ABDEN 53
SPBRGH EUSART Baud Rate Generator Register High Byte 53
SPBRG EUSART Baud Rate Generator Register Low Byte 53
Legend: — = unimplemented, read as ‘0’. Shad ed cells are not used for synchronous master reception.
Note 1: Reserved in 28-pin devices; always maintain these bits clear.
CREN bit
RC7/RX1/DT1
RC7/TX1/CK1 pin
Wri te t o
bit SREN
SREN b i t
RCIF bit
(Interrupt)
Read
RXREG
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q2 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1Q2 Q3 Q4 Q1Q2 Q3 Q4Q1 Q2Q3 Q4 Q1 Q2 Q3 Q4
‘
0
’
bit 0 bi t 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7
‘
0
’
Q1 Q2 Q3 Q4
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
RC7/TX1/CK1 pin
pin
(SCKP = 0)
(SCKP = 1)
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20.4 EUSART Synchronous
Slave Mode
Synchronous Slave mode is entered by clearing bit,
CSRC (TXSTA<7>). This mode differs from the
Synchron ous Master mode in that t he shift clock is sup-
plied e xternally at the C K pin (ins tead of be ing supp lied
internally in Master mode). This allows the device to
transfer or receive data while in any low-power mode.
20.4.1 EUSART SYNCHRONOUS
SLAVE TRANSMIT
The operation of the Synchronous Master and Slave
modes are identical, except in the case of the Sleep
mode.
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
a) The first word will immediately transfer to the
TSR register and transmit.
b) The second word will remain in TXREG register.
c) Flag bit TXIF will not be set.
d) When the first word has been shifted out of TSR,
the TXREG register will transfer the second
word to the TSR and flag bit TXIF will now be
set.
e) If enable bit TXIE is set, the interrupt will wake the
chip from Sleep . If the g lobal interrupt i s enabled,
the program will branch to the interrupt vector.
To set up a Synchronous Slave Transmission:
1. Enable the synchronous slave serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
2. Clear bits CREN and SREN.
3. If interrupts are desired, set enable bit TXIE.
4. If 9-bit transmission is desired, set bit TX9.
5. Enable the transmission by setting enable bit
TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Start transmission by loading data to the
TXREGx register.
8. If using interrup ts, ensu re that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
TABLE 20-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 54
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 54
IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 54
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 53
TXREG EUSART Transmit Register 53
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 53
BAUDCON ABDOVF RCIDL — SCKP BRG16 —WUE ABDEN 53
SPBRGH EUSART Baud Rate Generator Register High Byte 53
SPBRG EUSART Baud Rate Ge nera tor Registe r Low Byte 53
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.
Note 1: Reserved in 28-pin devices; always maintain these bits clear.
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DS39632A-page 252 Advance Information 2004 Microchip Technology Inc.
20.4.2 EUSART SYNCHRONOUS SLAVE
RECEPTION
The operation of the Synchronous Master and Slave
modes is identical except in the case of Sleep or any
Idle mode and bit SREN, which is a “don’t care” in
Slave mode.
If receive is enabled by setting the CREN bit prior to
entering Sleep or any Idle mode, then a word may be
received while in this low-power mode. Once the word
is received, the RSR register will transfer the data to th e
RCREG register; if the RCIE enable bi t is set, t he inter-
rupt generated will wake the chip from the low-power
mode. If the global interrupt i s enabled , the program will
branch to the interrupt vector.
To set up a Synchr onous Slave Re ception:
1. Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
2. If interrupts are desired, set enable bit RCIE.
3. If 9-bit reception is desired, set bit RX9.
4. To enable reception, set enable bit CREN.
5. Flag bit RCIF will be set when reception is
complete. An interrupt will be generated if
enable bit RCIE was set.
6. Read the RCSTA register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
7. Read the 8-bit received data by reading the
RCREG register.
8. If any error occurred, clear the error by clearing
bit CREN.
9. If using interrup ts, ensu re that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
TABLE 20-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 54
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 54
IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 54
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 53
RCREG EUSART Receive Register 53
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 53
BAUDCON ABDOVF RCIDL —SCKPBRG16—WUE ABDEN 53
SPBRGH EUSART Baud Rate Generator Registe r High Byte 53
SPBRG EUSART Baud Rate Genera tor Regi ster Low Byte 53
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.
Note 1: Reserved in 28-pin devices; always maintain these bits clear.
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21.0 10-BIT ANA LOG-TO-DIGITAL
CONVERTER (A/D) MODULE
The Analog-to-Digital (A/D) converter module has 10
inputs for the 28-pin devices and 13 for the 40/44-pin
devices. This module allows conversion of an analog
input signal to a corresponding 10-bit digital number.
The module has five registers:
• A/D Result Hi gh Regi ste r (ADRESH)
• A/D Result Low Register (ADRESL)
• A/D Control Regis ter 0 (ADCO N0)
• A/D Control Regis ter 1 (ADCO N1)
• A/D Control Regis ter 2 (ADCO N2)
The ADCON0 register, shown in Register 21-1,
controls the operation of the A/D module. The
ADCON1 register, shown in Register 21-2, configures
the functions of the port pins. The ADCON2, shown in
Register 21-3, configures the A/D clock source,
programmed acquisition time and justification.
REGISTER 21-1: ADCON0 REGISTER
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— CHS3 CHS2 CHS1 CHS0 GO/DONE ADON
bit 7 bit 0
bit 7-6 Unimplemented: Read as ‘0’
bit 5-2 CHS3:CHS0: Analog Channel Select bits
0000 = Channel 0 (AN0)
0001 = Channel 1 (AN1)
0010 = Channel 2 (AN2)
0011 = Channel 3 (AN3)
0100 = Channel 4 (AN4)
0101 = Channel 5 (AN5)(1,2)
0110 = Channel 6 (AN6)(1,2)
0111 = Channel 7 (AN7)(1,2)
1000 = Channel 8 (AN8)
1001 = Channel 9 (AN9)
1010 = Channel 10 (AN10)
1011 = Channel 11 (AN11)
1100 = Channel 12 (AN12
1101 = Unimplemented(2)
1110 = Unimplemented(2)
1111 = Unimplemented(2)
Note 1: These channels are not implemented on 28-pin devices.
2: Performing a conversion on unimplemented channels will return a floating input
measurement.
bit 1 GO/DONE: A/D Conversion Status bit
When ADON = 1:
1 = A/D convers ion in progress
0 = A/D Idle
bit 0 ADON: A/D On bit
1 = A/D converter module is enabled
0 = A/D converter module is disabled
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
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DS39632A-page 254 Advance Information 2004 Microchip Technology Inc.
REGISTER 21-2: ADCON1 REGISTER
U-0 U-0 R/W-0 R/W-0 R/W-0(1) R/W(1) R/W(1) R/W(1)
—— VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0
bit 7 bit 0
bit 7-6 Unimplemented: Read as ‘0’
bit 5 VCFG1: Voltage Reference Configuration bit (VREF- source)
1 =V
REF- (AN2)
0 =AV
SS
bit 4 VCFG0: Voltage Reference Configuration bit (VREF+ sour ce )
1 =VREF+ (AN3)
0 =AV
DD
bit 3-0 PCFG3:PCFG0: A/D Port Configuration Control bits:
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
A = Analog input D = Digital I/O
Note 1: The POR value of the PCFG bits depends on the value of the PBADEN
configuration bit. When PBADEN = 1, PCFG<3:0 > = 0000; when PBADEN = 0,
PCFG<3:0> = 0111.
2: AN5 through AN7 are available only on 40/44-pin devices.
PCFG3:
PCFG0
AN12
AN11
AN10
AN9
AN8
AN7(2
)
AN6(2
)
AN5(2
)
AN4
AN3
AN2
AN1
AN0
0000(1) AAAAAAAAAAAAA
0001 AAAAAAAAAAAAA
0010 AAAAAAAAAAAAA
0011 DAAAAAAAAAAAA
0100 DDAAAAAAAAAAA
0101 DDDAAAAAAAAAA
0110 DDDDAAAAAAAAA
0111(1) DDDDDAAAAAAAA
1000 DDDDDDAAAAAAA
1001 DDDDDDDAAAAAA
1010 DDDDDDDDAAAAA
1011 DDDDDDDDDAAAA
1100 DDDDDDDDDDAAA
1101 DDDDDDDDDDDAA
1110 DDDDDDDDDDDDA
1111 DDDDDDDDDDDDD
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REGISTER 21-3: ADCON2 REGISTER
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0
bit 7 bit 0
bit 7 ADFM: A/D Result Format Select bit
1 = Right justified
0 = Left justified
bit 6 Unimplemented: Read as ‘0’
bit 5-3 ACQT2:ACQT0: A/D Acquisiti on Time Select bits
111 = 20 TAD
110 = 16 TAD
101 = 12 TAD
100 = 8 TAD
011 = 6 TAD
010 = 4 TAD
001 = 2 TAD
000 = 0 TAD(1)
bit 2-0 ADCS2:ADCS0: A/D Conversion Clock Select bits
111 = FRC (clock derived from A/D RC oscillator)(1)
110 = FOSC/64
101 = FOSC/16
100 = FOSC/4
011 = FRC (clock derived from A/D RC oscillator)(1)
010 = FOSC/32
001 = FOSC/8
000 = FOSC/2
Note 1: If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is
added bef ore the A/D c lock st arts. This allows the SLEEP inst ruction to be executed
before starting a conversion.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
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DS39632A-page 256 Advance Information 2004 Microchip Technology Inc.
The analog reference voltage is software selectable to
either the device’s positive and negative supply voltage
(AVDD and AVSS), or the voltage level on the
RA3/AN3/VREF+ and RA2/AN2/VREF-/CVREF pins.
The A/D converter has a unique feature of being able
to operate while the device is in Sleep mode. To oper-
ate in Sleep, th e A/D conv ersion clock must b e derive d
from the A/D’s internal RC oscillator.
The output of the sample and hold is the input into the
converter, which generates the result via successive
approximation.
A device Reset forces all registers to their Reset state.
This forces the A/D module to be turned off and any
conversion in progress is aborted.
Each port pi n associ ated with the A/D converter can be
configured as an analog input, or as a digital I/O. The
ADRESH and ADRESL registers contain the result of
the A/D conversion. When the A/D conversion is com-
plete, the result is loaded into the ADRESH:ADRESL
register pair, the GO/DONE bit (ADCON0 register) is
cleared and A/D Interrupt Flag bit, ADIF, is set. The
block diagram of the A/D module is shown in
Figure 21-1.
FIGURE 21-1: A/D BLOCK DIAGRAM
(Input Voltage)
VAIN
VREF+
Reference
Voltage
AVDD
VCFG1:VCFG0
CHS3:CHS0
AN7(1)
AN6(1)
AN5(1)
AN4
AN3
AN2
AN1
AN0
0111
0110
0101
0100
0011
0010
0001
0000
10-bit
Converter
VREF-
AVSS
A/D
AN12
AN11
AN10
AN9
AN8
1100
1011
1010
1001
1000
Note 1: Channels AN5 through AN7 are not available on 28-pin devices.
2: I/O pins have diode protection to VDD and VSS.
0X
1X
X1
X0
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The value in the ADRESH:ADRESL registers is not
modified for a Power-on Reset. The ADRESH:ADRESL
registers will contain unknown data after a Power-on
Reset.
After the A/D module has been configured as desired,
the sele cted cha nne l m ust be acq uire d b efore the co n-
version is started. The analog input channels must
have their corresponding TRIS bits selected as an
input. To determine acquisition time, see Section 21.1
“A/D Acquisition Requirements”. After this acquisi-
tion time has elapsed, the A/D conversion can be
started. An acquisition time can be programmed to
occur bet ween setting th e GO/DONE bit an d the actual
start of the conversion.
The following steps should be followed to perform an
A/D conversion:
1. Configure the A/D modul e:
• Configure analog pins, voltage reference and
digital I/O (ADCON1)
• Select A/D input channel (ADCON0)
• Select A/D acquisition time (ADCON2)
• Selec t A/D conve rsi on clock (ADCON 2)
• Turn on A/D module (ADCON0)
2. Configu re A/D interr upt (if desired):
• Clear ADIF bit
• Set ADIE bit
• Set GIE bit
3. Wait the required acquisition time (if required).
4. Start conversion:
• Set GO/DONE bit (ADCON0 register)
5. Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared
OR
• Waiting for the A/D interrupt
6. Read A/D Result registers (ADRESH:ADRESL);
clear bit ADIF, if required.
7. For next conversion, go to step 1 or step 2, as
required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 3 TAD is
required before the next acquisition starts.
FIGURE 21-2: A/D TRANSFER FUNCTION
FIGURE 21-3: ANALOG INPUT MODEL
Digital Code Output
3FEh
003h
002h
001h
000h
0.5 LSB
1 LSB
1.5 LSB
2 LSB
2.5 LSB
1022 LSB
1022.5 LSB
3 LSB
Analog Inpu t Voltage
3FFh
1023 LSB
1023.5 LSB
VAIN CPIN
Rs ANx
5 pF
VT = 0.6V
VT = 0.6V ILEAKAGE
RIC ≤ 1k
Sampling
Switch
SS RSS
CHOLD = 25 pF
VSS
VDD
± 100 nA
Legend: CPIN
VT
ILEAKAGE
RIC
SS
CHOLD
= input capacitance
= threshold voltage
= leakage current at the pin due to
= interconnect resistance
= sampling switch
= sample/hold capacitance (from DAC)
various junctions
= sampling switch resistanceRSS
VDD
6V
Sampling Switch
5V
4V
3V
2V
1234
(kΩ)
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DS39632A-page 258 Advance Information 2004 Microchip Technology Inc.
21.1 A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 21-3. The
source impedance (RS) and the internal sampling
switch (RSS) impedance directly affect the time
required to charge the capacitor CHOLD. The sampling
switch (RSS) impedance va rie s over the dev ice vol tag e
(VDD). The sour ce impedanc e af fects th e offse t voltag e
at the analog input (due to pin leakage current). The
maximum recommended impedance for analog
sources is 2.5 kΩ. After the analog input channel is
selected (changed), the channel must be sampled for
at least the minimum acquisition time before starting a
conversion.
To calculate the minimum acquisition time,
Equation 21-1 may be used. This equation assumes
that 1/2 LSb error is used (1024 st eps for the A/D). The
1/2 LSb er ror is the ma ximu m error allow ed for the A/D
to meet its specified resolution.
Example 21-3 shows the calculation of the minimum
required acquisition time TACQ. This calculation is
based on the following application system
assumptions:
CHOLD = 25 pF
Rs = 2.5 kΩ
Conversion Error ≤1/2 LSb
VDD =5V → Rss = 2 kΩ
Temperature = 85°C (system max.)
EQUATION 21-1: ACQUISITION TIME
EQUATION 21-2: A/D MINIMUM CHARGING TIME
EQUATION 21-3: CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME
Note: When the conversion is started, the
holding cap ac itor i s di scon nected from the
input pin.
TACQ = Am plifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient
=T
AMP + TC + TCOFF
VHOLD = (VREF – (VREF/2048)) • (1 – e(-TC/CHOLD(RIC + RSS + RS)))
or
TC = -(CHOLD)(RIC + RSS + RS) ln(1/2048)
TACQ =TAMP + TC + TCOFF
TAMP =0.2 µs
TCOFF = (Temp – 25°C)(0.02 µs/°C)
(50°C – 25°C)(0.02 µs/°C)
1.2 µs
Temperature coefficient is only required for temperatures > 25°C. Below 25°C, TCOFF = 0 ms.
TC = -(CHOLD)(RIC + RSS + RS) ln(1/2047) µs
-(25 pF) (1 kΩ + 2 kΩ + 2.5 kΩ) ln(0.0004883) µs
5.03 µs
TACQ =0.2 µs + 5 µs + 1.2 µs
6.4 µs
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21.2 Selecting and Configuring
Acquisition Time
The ADCON2 register allows the user to select an
acquisition time that occurs each time the GO/DONE
bit is set. It also gives users the option to use an
automatically determined acquisition time.
Acquisition time may be set with the ACQT2:ACQT0
bits (ADCON2<5:3>), which provides a range of 2 to
20 TAD. When the GO/DONE bit is set, th e A/D modul e
continues to sample the input for the selected acquisi-
tion time, then automatically begins a conversion.
Since the acquisition time is programmed, there may
be no need to wait for an acquisition time between
selecting a channel and setting the GO/DONE bit.
Manual acquisition is selected when the
ACQT2:ACQT0 = 000. When the GO/DONE bit is set,
sampling is stopped and a conversion begins. The user
is responsible for ensuring the required acquisition time
has passed between selecting the desired input channel
and setting the GO/DONE bit. This option is also the
default Reset state of the ACQT2:ACQT0 bits and is
compatible with devices that do not offer programmable
acquisition times.
In either case, when the conversion is completed, the
GO/DONE bit is cleared, the ADIF flag is set and the
A/D begins sampling the currently selected channel
again. If an acquisition time is programmed, there is
nothing t o in dic ate if th e ac qu is iti on ti me has en ded , or
if the conversion has begun.
21.3 Selecting the A/D Conversion
Clock
The A/D conversion time per bit is defined as TAD. The
A/D c on vers ion re qui res 11 TAD per 10-bit conversion.
The source of the A/D conversion clock is software
selectable. There are seven possible options for TAD:
•2 T
OSC
•4 TOSC
•8 TOSC
•16 TOSC
•32 TOSC
•64 TOSC
• Intern al RC Os cillator
For correct A/D conversions, the A/D conversion clock
(TAD) must be as sh ort as possible, bu t greater than the
minimum TAD (see parameter 130 for more
information).
Table 21-1 shows the resultant TAD times de ri ve d f ro m
the device operating frequencies and the A/D clock
source selected.
TABLE 21-1: TAD vs. DEVICE OPERATING FREQUENCIES
AD Clock Source (TAD) Maximum Device Frequency
Operation ADCS2:ADCS0 PIC18FXXXX PIC18LFXXXX(4)
2 TOSC 000 2.86 MHz 1.43 kHz
4 TOSC 100 5.71 MHz 2.86 MHz
8 TOSC 001 11.43 MHz 5.72 MHz
16 TOSC 101 22.86 MHz 11.43 MHz
32 TOSC 010 40.0 MHz 22.86 MHz
64 TOSC 110 40.0 MHz 22.86 MHz
RC(3) x11 1.00 MHz(1) 1.00 MHz(2)
Note 1: The RC source has a typical TAD time of 4 ms.
2: The R C source ha s a typical TAD time of 6 ms.
3: For device frequencies above 1 MHz, the device must be in Sleep for the entire conversion or the A/D
accuracy may be out of specific ation .
4: Low-power devices only.
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21.4 Operation in Power Managed
Modes
The se lection of th e automa tic acquis ition ti me a nd A/D
conversion clock is determined in part by the clock
source and frequency while in a power man aged mode.
If the A/D is expected to operate while the device is in
a power managed mode, the ACQT2:ACQT0 and
ADCS2:ADCS0 bits in ADCON2 should be updated in
accordance with the clock source to be used in that
mode. After entering the mode, an A/D acquisition or
conversion may be started. Once started, the device
should continue to be clocked by the same clock
sour ce unt il the con ve r si on has been co mpl eted.
If desired, the device may be placed into the
corr espondi ng Idle m ode dur ing th e conve rsi on. If t he
device c loc k freq ue ncy is less tha n 1 MHz, the A/D RC
clock source should be selected.
Operation in the Sleep mode requires the A/D FRC
clock to be selected. If bits ACQT2:ACQT0 are set to
‘000’ and a con version is started, the conversion will be
delay ed on e ins tr uctio n cycl e to allo w exec uti on of the
SLEEP instruc tion and e ntry to Slee p mode. The IDLEN
bit (OSCCON<7>) must have already been cleared
prior to starting the conversion.
21.5 Configuring Analog Port Pins
The ADCON1, TRISA, TRISB and TRISE registers all
configure the A/D port pins. The port pins needed as
analog inputs must have their corresponding TRIS bits
set (input) . If the TRIS bit is cleare d (output), the digit al
output level (VOH or VOL) will be converted.
The A/D operation is independent of the state of the
CHS3:CHS0 bits and the TRIS bits.
Note 1: When reading the Port register, all pins
configured as analog input channels will
read as c lea red (a lo w l evel). Pins config-
ured as a digital input will convert as an
analog input. Analog levels on a digitally
configured input will be accurately
converted.
2: Analog l evels o n any p in defin ed as a dig-
ital input may cause the digital input buffer
to consume current out of the device’s
specification limits.
3: The PBADEN bit in Configuration
Register 3H configures PORTB pins to
reset as analog or digital pins by control-
ling how the PCFG0 bits in ADCON1 are
reset.
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21.6 A/D Conversions
Figure 21-4 shows the operation of the A/D converter
after the GO bit has been set and the ACQT2:ACQT0
bits are cleared. A conversion is started after the follow-
ing instruction to allow entry into Sl eep mode before the
conversion begins.
Figure 21-5 shows the operation of the A/D converter
after the GO bit has been set, the ACQT2:ACQT0 bits
are set to ‘010’ and selecting a 4 TAD acquisition time
before the conversion starts.
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The A/D Result register
pair will NOT be updated with the partially completed
A/D conversion sample. This means the
ADRESH:ADRESL registers will continue to contain
the value of the last completed conversion (or the last
value written to the ADRESH:ADRESL registers).
After the A/D conversion is completed or aborted, a
2T
AD wait is required before the n ext acquisition can be
started. After this wait, acquisition on the selected
channel is automatically started.
21.7 Discharge
The discharge phase is used to initialize the value of
the capacitor array. The array is discharged before
every sample. This feature helps to optimize the
unity-gain amplifier as the circuit always needs to
charge the capacitor array, rather than
charge/discharge based on previous measure values.
FIGURE 21-4: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0)
FIGURE 21-5: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD)
Note: The GO/DONE bit should NOT be set in
the sam e inst ructio n that tu rns on the A/D.
TAD1TAD2TAD3TAD4 TAD5TAD6 TAD7TAD8 TAD11
Set GO bit
Holding capacitor is disconnected from analog input (typically 100 ns)
TAD9 TAD10
TCY - TAD
ADRESH:ADRESL is loaded, GO bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
Conversion starts
b0
b9 b6 b5 b4 b3 b2 b1
b8 b7
On t he following cycle:
TAD1
Discharge
1234567811
Set GO bit
(Holding capacitor is disconnected)
910
Conversion starts
123 4
(Holding capacitor continues
acquiring input)
TACQ Cycles TAD Cycles
Automatic
Acquisition
Time
b0b9 b6 b5 b4 b3 b2 b1
b8 b7
ADRESH:ADRESL is loaded, GO bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
On the following cycle:
TAD1
Discharge
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21.8 Use of the CCP2 Trigger
An A/ D conversion can be star ted by the special event
trigger of the CCP2 module. This requires that the
CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be pro-
grammed as ‘1011’ and that the A/D module is enabled
(ADON bit is set). When the trigger occurs, the
GO/DONE bit will be set, starting the A/D acquisition
and conv ersio n and the Timer1 (or T i mer3) c ounter wil l
be reset to zero. T imer1 (or T imer3) i s reset to aut omat-
ically repeat the A/D acquisition period with minimal
software overhead (moving ADRESH:ADRESL to the
desired location). The appropriate analog input chan-
nel must be selected and the minimum acquisition
period is either timed by the user, or an appropriate
TACQ time selected be fore the special eve nt trigger sets
the GO/DONE bit (starts a conversion).
If the A/D module is not enabled (A DON is c leared), the
special event trigger will be ignored by the A/D module,
but will still reset the Timer1 (or Timer3) counter.
TABLE 21-2: REGISTERS ASSOCIATED WITH A/D OPERATION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset
Values
on pag e
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 54
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 54
IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 54
PIR2 OSCFIF CMIF —EEIF BCLIF HLVDIF TMR3IF CCP2IF 54
PIE2 OSCFIE CMIE —EEIE BCLIE HLVDIE TMR3IE CCP2IE 54
IPR2 OSCFIP CMIP —EEIP BCLIP HLVDIP TMR3IP CCP2IP 54
ADRESH A/D Result Register High Byte 52
ADRESL A/D Result Register Low Byte 52
ADCON0 —— CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 52
ADCON1 —— VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 52
ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 52
PORTA RA7(1) RA6(1) RA5 RA4 RA3 RA2 RA1 RA0 54
TRISA TRISA7(2) TRISA6(2) PORTA Data Direction Control Register 54
PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 54
TRISB PORTB Data Direction Control Register 54
LATB PORTB Data Latch Register (Read and Write to Data Latch) 54
PORTE(4) — — — —RE3
(3) RE2 RE1 RE0 54
TRISE(4) IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 54
LATE(4) — — — — — PORTE Data Latch Register 54
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1: These bits are unimplemented on 28-pin devices; always maintain these bits clear.
2: PORTA<7:6> and their direction bits are individually configured as port pins based on various primary
oscillator modes. When disabled, these bits read as ‘0’.
3: RE3 port bit is available only as an input pin when the MCLRE configuration bit is ‘0’.
4: These registe r s are not im ple me nte d on 28-pin devi ce s.
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22.0 COMPARATOR MODULE
The analog comparator module contains two compara-
tors that can be configured in a variety of ways. The
inputs can be selected from the analog inputs multiplexed
with p ins RA0 th rough RA 5, as well a s the on- chip volt -
age reference (see Sec tion 21.0 “Comparator Voltage
Reference Module”). The digital outputs (normal or
inverted) are available at the pin level and can also be
read th ro ug h the con trol regi s ter.
The CMCON register (Register 22-1) selects the
comparator input and output configuration. Block
diagrams of the various comparator configurations are
shown in Figure 22-1.
REGISTER 22-1: CMCON REGISTER
R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1
C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0
bit 7 bit 0
bit 7 C2OUT: Comparator 2 Output bit
When C2INV = 0:
1 = C2 VIN+ > C2 VIN-
0 = C2 VIN+ < C2 VIN-
When C2INV = 1:
1 = C2 VIN+ < C2 VIN-
0 = C2 VIN+ > C2 VIN-
bit 6 C1OUT: Comparator 1 Output bit
When C1INV = 0:
1 = C1 VIN+ > C1 VIN-
0 = C1 VIN+ < C1 VIN-
When C1INV = 1:
1 = C1 VIN+ < C1 VIN-
0 = C1 VIN+ > C1 VIN-
bit 5 C2INV: Comparator 2 Output Inversion bit
1 = C2 output inverted
0 = C2 output not inverted
bit 4 C1INV: Comparator 1 Output Inversion bit
1 = C1 output inverted
0 = C1 output not inverted
bit 3 CIS: Comparator I nput Switch bit
When CM2:CM0 = 110:
1 =C1 VIN- connects to RA3/AN3
C2 VIN- connects to RA2/AN2
0 =C1 V
IN- connects to RA0/AN0
C2 VIN- connects to RA1/AN1
bit 2-0 CM2:CM0: Comparator Mo de bits
Figure 22-1 shows the Comparator modes and CM2:CM0 bit settings.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
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22.1 Comparator Configuration
There are eight modes of operation for the compara-
tors, shown in Figure 22-1. Bits CM2:CM0 of the
CMCON register are used to select these modes. The
TRISA register controls the data direction of the
comparator pins for each mode. If the Comparator
mode is cha nged, the c om p ara tor o utput leve l ma y not
be valid for the specified mode change delay shown in
Section 28.0 “Electr ical Cha racteristics”.
FIGURE 22-1: COMPARATOR I/O OPERATING MODES
Note: Compara tor in terr upts sh ould be dis abled
during a Comparator mode change.
Otherwise, a false interrupt may occur.
C1
RA0/AN0 VIN-
VIN+
RA3/AN3/ Off (Read as ‘0’)
Comparators Reset
A
A
CM2:CM0 = 000
C2
RA1/AN1 VIN-
VIN+
RA2/AN2/ Off (Read as ‘0’)
A
A
C1
VIN-
VIN+C1OUT
Two Independent Comparators
A
A
CM2:CM0 = 010
C2
VIN-
VIN+C2OUT
A
A
C1
VIN-
VIN+C1OUT
Two Common Reference Comparators
A
A
CM2:CM0 = 100
C2
VIN-
VIN+C2OUT
A
D
C2
VIN-
VIN+Off (Read as ‘0’)
One Independent Comparator with Output
D
D
CM2:CM0 = 001
C1
VIN-
VIN+C1OUT
A
A
C1
VIN-
VIN+Of f (Read as ‘0’)
Comparators Off (POR Default Val ue)
D
D
CM2:CM0 = 111
C2
VIN-
VIN+Of f (Read as ‘0’)
D
D
C1
VIN-
VIN+C1OUT
Four Inputs Multiplexed to Two Comparators
A
A
CM2:CM0 = 110
C2
VIN-
VIN+C2OUT
A
A
From VREF Module
CIS = 0
CIS = 1
CIS = 0
CIS = 1
C1
VIN-
VIN+C1OUT
Two Common Reference Comparators with Outputs
A
A
CM2:CM0 = 101
C2
VIN-
VIN+C2OUT
A
D
A = Analog Input, port reads zeros always D = Digital Input CIS (CMCON<3>) is the Comparator Input Switch
CVREF
C1
VIN-
VIN+C1OUT
Two Independent Comparators with Outputs
A
A
CM2:CM0 = 011
C2
VIN-
VIN+C2OUT
A
A
RA5/AN4/SS/HLVDIN/C2OUT*
RA4/T0CKI/C1OUT*
VREF+
VREF-/CVREF
RA0/AN0
RA3/AN3/
RA1/AN1
RA2/AN2/
VREF+
VREF-/CVREF
RA0/AN0
RA3/AN3/
RA1/AN1
RA2/AN2/
VREF+
VREF-/CVREF
RA0/AN0
RA3/AN3/
RA1/AN1
RA2/AN2/
VREF+
VREF-/CVREF
RA0/AN0
RA3/AN3/
RA1/AN1
RA2/AN2/
VREF+
VREF-/CVREF
RA0/AN0
RA3/AN3/
RA1/AN1
RA2/AN2/
VREF+
VREF-/CVREF
RA0/AN0
RA3/AN3/
VREF+
RA1/AN1
RA2/AN2/
VREF-/CVREF
RA4/T0CKI/C1OUT*
RA5/AN4/SS/HLVDIN/C2OUT*
RA0/AN0
RA3/AN3/
VREF+
RA1/AN1
RA2/AN2/
VREF-/CVREF
RA4/T0CKI/C1OUT*
* Setting the TRISA<5:4> bits will disable the comparator outputs by configuring the pins as inputs.
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22.2 Comparator Operation
A single comp arator is shown in Figure 22-2, along with
the relationship between the analog input levels and
the digit al ou tput. When the an alog input a t VIN+ is less
than the analog input VIN-, the outp ut of the comp arator
is a digital low level. When the analog input at VIN+ is
greater than the analog input VIN-, the output of the
comparator is a digital high level. The shaded areas of
the output of the comparator in Figure 22-2 represent
the unce rt ainty, due to in put of fse t s and respon se tim e.
22.3 Comparator Reference
Depending on the comparator operating mode, either
an external or internal voltage reference may be used.
The analog signal present at VIN- is compared to the
signal at VIN+ and the digital output of the comparator
is adjusted accordingly (Figure 22 -2).
FIGURE 22-2: SINGLE COMPARATOR
22.3.1 EXTERN AL REFE REN CE SIG NA L
When external voltage references are used, the
comparator module can be configured to have the com-
parators operate from the same or different reference
sour ces. How ever , th resho ld detecto r applica tions ma y
require th e s am e re fere nce. Th e reference s ign al m us t
be between VSS and VDD and can be app lie d to ei ther
pin of the comparator(s).
22.3.2 INTERNAL REFERENCE SIGNAL
The com p a r ato r m odu le also al low s th e sel ec tio n of an
internally generated voltage reference from the
comparator voltage reference module. This module is
describ ed in m ore de tai l in Section 21.0 “Comparator
Voltage Reference Module”.
The internal reference is only available in the mode
where four inputs are multiplexed to two comparators
(CM2:CM0 = 110). In this mode, the internal voltage
reference is applied to the VIN+ pin of both
comparators.
22.4 Comparator Response Time
Response time is the minimum time, after selecting a
new reference voltage or input source, before the
comparator output has a valid level. If the internal ref-
erence is changed, the maximum delay of the internal
voltage reference must be considered when using the
comparator outputs. Otherwise, the maximum delay of
the comparators should be used (see Section 28.0
“Electrical Characteristics” ).
22.5 Comparator Outputs
The comparator outputs are read through the CMCON
register. These bits are read-only. The comparator
output s may al so be dire ctly output to the RA4 a nd RA5
I/O pins . When enab led, multipl exors in th e output p ath
of the RA4 and RA5 pins will switch and the output of
each pin will be the unsynchronized output of the
comparator. The uncertainty of each of the
comparators is related to the input offset voltage and
the response time given in the specifications.
Figure 22-3 shows the comparator output block
diagram.
The TRISA bits will still function as an output enable/
disable for the RA4 and RA5 pins while in this mode.
The polarity of the comparator outputs can be changed
using the C2INV and C1INV bits (CMCON<4:5 >).
–
+
VIN+
VIN-Output
Output
VIN-
VIN+
Note 1: When reading the Port register, all pins
configu red a s anal og inp uts will read as a
‘0’. Pins configured as digital inputs will
convert an analog input according to the
Schmitt Trigger input specification.
2: Analog levels on any pin defined as a
digital inpu t may cau se the input buf fe r to
consume more current than is specified.
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FIGURE 22-3: COMPARATOR OUTPUT BLOCK DIAGRAM
22.6 Comparator Interrupts
The comparator interrupt flag is set whenever there is
a change in the output value of either comparator.
Software will need to maintain information about the
stat us of the out put bits, as rea d from CMCON<7:6> , to
determine the actual change that occurred. The CMIF
bit (PIR2<6>) is the Comparator Interrupt Flag. The
CMIF bit must be reset by clearing it. Since it is also
possible to write a ‘1’ to this register, a simulated
interrupt may be initiated.
Both the CMIE bit (PIE2<6>) and the PEIE bit
(INTCON<6>) must be set to enable the interrupt. In
addition, the GIE bit (INTCON<7>) must also be set. If
any of these bits are clear, the interrupt is not enabled,
though the CMIF bit will still be set if an interrupt
conditi on oc curs.
The use r , in the Interru pt Service Rout ine, can clear th e
inter rupt in the following manner :
a) Any read or write of CMCON will end the
mismatch condition.
b) Clear flag bit CMIF.
A mismatc h co ndi tio n will co nti nue to set fla g bit CMIF.
Reading CMCON will end the mismatch condition and
allow flag bit CMIF to be cleared.
22.7 Comparator Operation
During Sleep
When a comparator is active and the device is placed
in Sleep mode, the comparator remains active and the
interrupt is functiona l if enabled. This interrupt will wake
up the device from Sleep mode, when enabled. Each
operational comparator will consume additional cur-
rent, as shown in the comparator specifications. To
minimi ze power co nsumption wh ile in Sleep mod e, turn
off the comparators (CM2:CM0 = 111) before entering
Sleep. If the dev ice w ak es up fro m Sle ep, the c ontent s
of the CMCON register are not affected.
22.8 Effects of a Reset
A device Reset forces the CMCON register to its Reset
state , ca using the comp arat or modul es to be turn ed of f
(CM2:CM0 = 111). However, the input pins (RA0
through RA3) are configured as analog inputs by
default on device Reset. The I/O configuration for these
pins is determined b y the sett ing of the PCF G3:PCFG0
bits (ADCON1<3:0>). Therefore, device current is
minimized when analog inputs are present at Reset
time.
DQ
EN
To RA4 or
RA5 pin
Bus
Data
Set
MULTIPLEX
CMIF
bit
-+
Port pins
Read CMCON
Reset From
other
Comparator
CxINV
DQ
EN CL
Note: If a change in the CMCON register
(C1OUT or C2OUT) should occur when a
read operation is being executed (start of
the Q2 cycle), then the CMIF (PIR
registers) interrupt flag may not get set.
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22.9 Analog Input Connection
Considerations
A simplified circuit for an analog input is shown in
Figure 22-4. Since the analog pins are connected to a
digital output, they have reverse biased diodes to VDD
and VSS. Th e analog input, th erefore, must be betwee n
VSS and VDD. If the input voltage deviates from this
range by more than 0.6V in either direction, one of the
diodes is forward biased and a latch-up condition may
occur. A maximum source impedance of 10 kΩ is
recommended for the analog sources. Any external
component connected to an analog input pin, such as
a capacitor or a Zener diode, should have very little
leakage current.
FIGURE 22-4: COMP ARATOR ANALOG INPUT MODEL
TABLE 22-1: REGISTERS ASSOCIATED WITH COMPARATOR MODULE
VA
RS < 10k
AIN CPIN
5 pF
VDD
VT = 0.6V
VT = 0.6V
RIC
ILEAKAGE
±500 nA
VSS
Legend: CPIN = Input Capacitance
VT= Threshold Voltage
ILEAKAGE = Leakage Current at the pin due to various junctions
RIC = Interconnect Resistance
RS= Source Impedance
VA = Analog Voltage
Comparator
Input
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset
Values
on page
CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 53
CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 53
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51
PIR2 OSCFIF CMIF —EEIF BCLIF LVDIF TMR3IF CCP2IF 54
PIE2 OCSFIE CMIE —EEIE BCLIE LVDIE TMR3IE CCP2IE 54
IPR2 OSCFIP CMIP —EEIP BCLIP LVDIP TMR3IP CCP2IP 54
PORTA —RA6
(1) RA5 RA4 RA3 RA2 RA1 RA0 54
LATA —LATA6
(1) PORTA Data Latch Register (Read and Write to Data Latch) 54
TRISA — TRISA6(1) PORTA Data Direction Control Register 54
Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the comparator module.
Note 1: POR TA<6> and its directi on and l atch bi ts are indiv iduall y configu red a s port pin s based on various osci lla-
tor modes. Whe n disa ble d, thes e bit s read as ‘0’.
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NOTES:
2004 Microchip Technology Inc. Advance Information DS39632A-page 269
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23.0 COMPARATOR VOLTAGE
REFERENCE MODULE
The comparator voltage reference is a 16-tap resistor
ladder network that provides a selectable reference
voltage. Although its primary purpose is to provide a
reference for the analog comparators, it may also be
used independently of them.
A block diagram of t he module is shown in Figure 23-1.
The resis tor ladder is segment ed to provide two range s
of CVREF values and has a power-down function to
conserve power when the reference is not being used.
The module’s supply reference can be provided from
either device VDD/VSS or an external voltage reference.
23.1 Configuring the Compar ator
Voltage Reference
The vol tag e referen ce m odule i s control led th rough th e
CVRCON register (Register 23-1). The comparator
voltage reference provides two ranges of output
voltage, each with 16 distinct levels. The range to be
used is selected by the CVRR bit (CVRCON<5>). The
primary diffe rence between the rang es is the si ze of th e
steps selected by the CVREF Selection bits
(CVR3:C VR0), w it h on e ra nge offering finer resolu tio n.
The equations used to calculate the output of the
comparator voltage reference are as follows:
If CVRR = 1:
CVREF = ((CVR3:CVR0)/24) x CVRSRC
If CVRR = 0:
CVREF = (CVRSRC x 1/4) + (( (CVR3:CVR0) /32) x
CVRSRC)
The comparator reference supply voltage can come
from either VDD and VSS, or the external VREF+ and
VREF- that are multiplexed with RA2 and RA3. The
voltage source is selected by the CVRSS bit
(CVRCON<4>).
The settling time of the comparator voltage reference
must be considered when changing the CVREF out-
put (see Table 28-3 in Section 28.0 “Electrical
Characteristics”).
REGISTER 23-1: CVRCON REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CVREN CVROE(1) CVRR CVRSS CVR3 CVR2 CVR1 CVR0
bit 7 bit 0
bit 7 CVREN: Comparat or Voltage Refere nce Enable bit
1 =CV
REF circuit powered on
0 =CV
REF circuit powered down
bit 6 CVROE: Comparator VREF Output Enable bit(1)
1 =CVREF voltage level is also output on the RA2/AN2/VREF-/CVREF pin
0 =CV
REF voltage is disconnected from the RA2/AN2/VREF-/CVREF pin
Note 1: CVROE overrides the TRISA<2 > bit setting.
bit 5 CVRR: Comparator VREF Range Selection bit
1 = 0 to 0.667 CVRSRC, with CVRSRC/24 step size (low range)
0 = 0.25 CVRSRC to 0.75 CVRSRC, with CVRSRC/32 step size (high range)
bit 4 CVRSS: Comparator VREF Source Selection bit
1 = Comparator reference source CVRSRC = (VREF+) – (VREF-)
0 = Comparator reference source CVRSRC = VDD – VSS
bit 3-0 CVR3:CVR0: Comparator VREF Value Selection bits (0 ≤ (CVR3:CVR0) ≤ 15)
When CVRR = 1:
CVREF = ((CVR3:CVR0)/24) • (CVRSRC)
When CVRR = 0:
CVREF = (CVRSRC/4) + ((CVR3:CVR0)/32) • (CVRSRC)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
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FIGURE 23-1: VOLTAGE REFERENCE BLOCK DIAGRAM
23.2 Voltage Reference Accuracy/Error
The full range of voltage reference cannot be realized
due to the construction of the module. The transistors
on the top and bottom of the resistor ladder network
(Figure 23-1) keep CVREF from approaching the refer-
ence source rails. The voltage reference is derived
from the reference source; therefore, the CVREF output
changes with fluctuations in that source. The tested
absolute accuracy of the voltage reference can be
found in Section 28.0 “Electrical Characteristics”.
23.3 Operation During Sleep
When the device wakes up from Sleep through an
interr upt o r a Watchdog Timer time- out, the c onte nt s of
the CVRCON register are not affected. To minimize
current consumption in Sleep mode, the voltage
reference should be disabled.
23.4 Effects of a Reset
A device Reset disables the voltage reference by
clearing bit, CVREN (CVRCON<7>). This Reset also
disconnects the reference from the RA2 pin by clearing
bit, CVROE (CVRCON<6>) and selects the high-voltage
range by clearing bit, CVRR (CVRCON<5>). The CVR
value select bits are also cleared.
23.5 Connection Considerations
The voltage reference module operates independently
of the comparator module. The output of the reference
generator may be connected to the RA2 pin if the
TRISA<2> bit and the CVROE bit are both set.
Enabling the voltage reference output onto RA2 when
it is configured as a digital input will increase current
consumption. Connecting RA2 as a digital output with
CVRSS enabled will also increase current
consumption.
The RA2 pin can be used as a simple D/A output with
lim ite d dr i ve c apa bi lit y. Due t o t he l i mi te d c ur re nt dri ve
capability, a buffer must be used on the voltage
reference output for external connections to VREF.
Figure 23-2 shows an example buffering technique.
16-to-1 MUX
CVR3:CVR0
8R
R
CVREN
CVRSS = 0
VDD
VREF+CVRSS = 1
8R
CVRSS = 0
VREF-CVRSS = 1
R
R
R
R
R
R
16 Steps
CVRR
CVREF
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FIGURE 23-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
TABLE 23-1: REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE
CVREF Output
+
–
CVREF
Module
Voltage
Reference
Output
Impedance
R(1)
RA2
Note 1: R is dependent upon the voltage reference configuration bits, CVRCON<3:0> and CVRCON<5>.
PIC18FXXXX
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset
Values
on page
CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 53
CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 53
TRISA TRISA7(1) TRISA6(1) PORTA Data Direction Control Register 54
Legend: Shaded cells are not used with the comparator voltage reference.
Note 1: PORTA pins are enabled based on oscillator configuration.
PIC18F2455/2550/4455/4550
DS39632A-page 272 Advance Information 2004 Microchip Technology Inc.
NOTES:
2004 Microchip Technology Inc. Advance Information DS39632A-page 273
PIC18F2455/2550/4455/4550
24.0 HIGH/LOW-VOLTAGE DETECT
(HLVD)
PIC18F2455/2550/4455/4550 devices have a
High/L ow-V olta ge Detect mod ule (HL VD ). This is a p ro-
gramma ble circui t that allows th e user to specify both a
device voltage trip point and the direction of change
from that point. If the device experiences an excursion
past the trip point in that direction, an interrupt flag is
set. If the interrupt is enabled, the program execution
will branch to the interrupt vector address and the
software can then respond to the interrupt.
The High/Low-Voltage Detect Control register
(Register 24-1) completel y controls the operation of the
HLVD module. This allows the circuitry to be “turned
off” by the user under software control, which
minimizes the current consumption for the device.
The block diagram for the HLVD module is shown in
Figure 24-1.
REGISTER 24-1: HLVDCON: HIGH/LOW-VOLTAGE DETECT CONTROL REGISTER
R/W-0 U-0 R-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1
VDIRMAG — IRVST HLVDEN HLVDL3 HLVDL2 HLVDL1 HLVDL0
bit 7 bit 0
bit 7 VDIRMAG: Voltage Direction Magnitude Select bit
1 = Event occurs when voltage equals or exceeds trip point (HLVDL3:HLDVL0)
0 = Event occurs when voltage equals or falls below trip point (HLVDL3:HLVDL0)
bit 6 Unimplemented: Read as ‘0’
bit 5 IRVST: Internal Refe rence Voltage Stable Flag bit
1 = Indicates that the Voltage Detect logic will generate the interrupt flag at the specified
voltage range
0 = Indicates that the Voltage Detect logic will not generate the interrupt flag at the specified
voltage range and the HLVD interrupt should not be enabled
bit 4 HLVDEN: High/Low-Voltage Detect Power Enable bit
1 = HLVD enabled
0 = HLVD disabled
bit 3-0 HLVDL3:HLVDL0: Voltage Dete cti on Lim it bits
1111 = External analog input is used (input comes from the HLVDIN pin)
1110 = 4.41V-4.87V
1101 = 4.11 V-4.55V
1100 = 3.92V-4.34V
1011 = 3.72V-4.12V
1010 = 3.53V-3.91V
1001 = 3.43V-3.79V
1000 = 3.24V-3.58V
0111 = 2.95V-3.26V
0110 = 2.75V-3.03V
0101 = 2.64V-2.92V
0100 = 2.43V-2.69V
0011 = 2.35V-2.59V
0010 = 2.16V-2.38V
0001 = 1.96V-2.16V
0000 = Reserved
Note: HLVDL3:HLVDL0 m ode s that resul t i n a tri p p oin t b elo w the v ali d o perating voltag e
of the device are not tested.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC18F2455/2550/4455/4550
DS39632A-page 274 Advance Information 2004 Microchip Technology Inc.
The module is enabled by setting the HLVDEN bit.
Each time that the HLVD module is enabled, the cir-
cuitry requires some time to stabilize. The IRVST bit is
a read-only bit and is used to indicate when the circuit
is stable. The module can only generate an interrupt
after the circuit is stable and IRVST is set.
The VDIRMAG bit determines the overall operation of
the module. When VDIRMAG is cleared, the module
monitors for drops in VDD below a predetermined set
point. Wh en the bit is set, the mo dule moni tors for rises
in VDD above the set point.
24.1 Operation
When the HLVD module is enabled , a co mparat or uses
an internally generated reference voltage as the set
point. The set point is compared with the trip point,
where each node in the resistor divider represents a
trip point voltage. The “trip point” voltage is the voltage
level at which the device detects a high or low-voltage
event, depending on the configuration of the module.
When the supply voltage is equal to the trip point, the
voltage tapped off of the resistor array is equal to the
internal reference voltage generated by the voltage
reference module. The comparator then generates an
interrupt signal by setting the HLVDIF bit.
The trip po int v ol tage is sof tw are p rogrammab le to an y
one of sixteen values. The trip point is selected
by programming the HLVDL3:HLVDL0 bits
(HLVDCON<3:0>).
The HLVD modul e has a n additio nal featu re tha t allows
the user to supply the trip voltage to the module from an
external source. This mode is enabled when bits,
HLVDL3:HLVDL0, are set to ‘1111’. In this state, the
comparator input is multiplexed from the external input
pin, HLVDIN. This gives users flexibility because it
allows them to configure the High/Low-Voltage Detect
interrupt to occur at any voltage in the valid operating
range.
FIGURE 24-1: HLVD MODULE BLOCK DIAGRAM (WITH EXTERNAL INPUT)
Set
VDD
16 to 1 MUX
HLVDEN
HLVDCON
HLVDIN
HLVD3:HLVD0 Register
HLVDIN
VDD
Externally Ge nerate d
Trip Point
HLVDIF
HLVDEN
BOREN I n ternal Voltage
Reference
VDIRMAG
2004 Microchip Technology Inc. Advance Information DS39632A-page 275
PIC18F2455/2550/4455/4550
24.2 HLVD Setup
The following steps are needed to set up the HLVD
module:
1. Disa bl e t he modu le by cl ea ri ng t he HLV D EN bit
(HLVDCON<4>).
2. Write the valu e to the HLVDL3:HLVDL0 bits th at
selects the desired HLVD trip point.
3. Set the VDIRMAG bit to detect high voltage
(VDIRMAG = 1) or low voltage (VDIRMAG = 0).
4. Enable the HLVD module by setting the
HLVDEN bit.
5. Clea r the HLVD i nte rrupt flag (PIR 2<2> ), whi ch
may have been set from a previous interrupt.
6. Enable the HLVD interrupt if interrupts are
desired by setting the HLVDIE and GIE bits
(PIE<2> and INTCON<7>). An interrupt will not
be generated until the IRVST bit is set.
24.3 Current Consumption
When the module is enabled, the HLVD comparator
and volt age divider are enabled and will consume static
current. The total current consumption, when enabled,
is specified in electrical specification parameter
#D022B.
Depending on the application, the HLVD module does
not need to be operating constantly. To decrease the
current requirements, the HLVD circuitry may only
need to be en abled for short pe riods w here the volt age
is checked. After doing the check, the HLVD module
may be disabled.
24.4 HLVD Start-up Time
The internal reference voltage of the HLVD module,
specified in electrical specification parameter #D423,
may be used by other internal circuitry, such as the
Programmable Brown-out Reset. If the HLVD or other
circuits using the voltage reference are disabled to
lower the device’s current consumption, the reference
volt age circui t will requ ire time to be come st able befo re
a low or high-voltage condition can be reliably
detected. This start-up time, TIRVST, is an interval that
is independent of device clock speed. It is specified in
electrical specification parameter 36 (Table 28-12).
The HLVD interrupt f lag is no t en abl ed u nti l TIRVST has
expired and a stable reference voltage is reached. For
this reason, brief excursions beyond the set point may
not be detected during this interval. Refer to
Figure 2 4-2 or Figure 24-3.
FIGURE 24-2: LOW-VOLTAGE DETECT OPERATION (VDIRMAG = 0)
VLVD
VDD
HLVDIF
VLVD
VDD
Enable HLVD
TIVRST
HLVDIF may not be set
Enable HLVD
HLVDIF
HLVDIF cleared in software
HLVDIF cleared in software
HLVDIF cleared in software,
CAS E 1:
CAS E 2:
HLVDIF remains set since HLVD condition still exists
TIVRST
Internal Reference is stable
Internal Reference is stable
IRVST
IRVST
PIC18F2455/2550/4455/4550
DS39632A-page 276 Advance Information 2004 Microchip Technology Inc.
FIGURE 24-3: HIGH-VOLTAGE DETECT OPERATION (VDIRMAG = 1)
24.5 Applications
In many applications, the ability to detect a drop below
or rise above a particular threshold is desirable. For
example, the HLVD module could be periodically
enabled to detec t USB a ttach or d et a ch . This assu mes
the device is powered by a lower voltage source than
the Universal Serial Bus when detached. An attach
would indicate a High-Voltage Detect from, for exam-
ple, 3.3V to 5V (the vol tag e on USB) a nd vice ve rsa for
a detach. This feature could save a design a few extra
components and an attach signal (input pin).
For general battery applications, Figure 24-4 shows a
possible voltage curve. Over time, the device voltage
decreases. When the device voltage reaches voltage,
VA, the HLVD logic generates an interrupt at time, TA.
The interrupt could cause the execution of an ISR,
which would allow the application to perform “house-
keeping tasks” and perform a controlled shutdown
before the device voltage exits the valid operating
range at TB. The HLVD, thus, would give the applica-
tion a time window, represented by the difference
between TA and TB, to safely exit.
FIGURE 24-4: TYPICAL LOW-VOLTAGE
DETECT APPLICATION
VLVD
VDD
HLVDIF
VLVD
VDD
Enable HLVD
TIVRST
HLVDIF may not be set
Enable HLVD
HLVDIF
HLVDIF cleared in software
HLVDIF cleared in software
HLVDIF cleared in software,
CASE 1:
CASE 2:
HLVDIF remains set since HLVD condition still exists
TIVRST
IRVST
Internal Reference is stable
Internal Reference is stable
IRVST
Time
Voltage
VA
VB
TATB
VA = HLVD trip point
VB = Minimum valid devic e
operating voltage
Legend:
2004 Microchip Technology Inc. Advance Information DS39632A-page 277
PIC18F2455/2550/4455/4550
24.6 Operation During Sleep
When en abled, the HLVD circuitry contin ues to opera te
during Sleep. If the device voltage crosses the trip
point, the HLVDIF bit will be set and the device will
wake-up from Sleep. Device execution will continue
from the interrupt vector address if interrupts have
been globally enabled.
24.7 Effects of a Reset
A device Reset forces all registers to their Reset state.
This forces the HLVD module to be turned off.
TABLE 24-1: REGISTERS ASSOCIATED WITH HIGH/LOW-VOLTAGE DETECT MODULE
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset
Values
on Page
HLVDCON VDIRMAG — IRVST HLVDEN HLVDL3 HLVDL2 HLVDL1 HLVDL0 52
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51
PIR2 OSCFIF CMIF — EEIF BCLIF HLVDIF TMR3IF CCP2IF 54
PIE2 OCSFIE CMIE —EEIE BCLIE HLVDIE TMR3IE CCP2IE 54
IPR2 OSCFIP CMIP —EEIP BCLIP HLVDIP TMR3IP CCP2IP 54
Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the HLVD module.
PIC18F2455/2550/4455/4550
DS39632A-page 278 Advance Information 2004 Microchip Technology Inc.
NOTES:
2004 Microchip Technology Inc. Advance Information DS39632A-page 279
PIC18F2455/2550/4455/4550
25.0 SPECIAL FEATURES OF THE
CPU
PIC18F2455/2550/4455/4550 devices include several
features intended to maximize reliability and minimize
cost through elimination of external components.
These are:
• Oscillator Selection
• Resets:
- Power-on Reset (PO R)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
• Watchdog Timer (WDT)
• Fail-Safe Clock Monitor
• Two-Speed Start-up
• Code Protection
• ID Locations
• In-Circuit Serial Programming
The oscillator can be configured for the application
dependi ng on frequ ency, power, accuracy and cost . All
of the options are discussed in detail in Section 2.0
“Oscillator Configurations”.
A complete discussion of device Resets and interrupts
is available in previous sections of this data sheet.
In addition to their Power-up and Oscillator S ta rt-up T im-
ers provided for Resets, PIC18F2455/2550/4455/4550
devices have a Watchdog Timer, which is either
permanently enabled via the configuration bits or
software controlled (if con figured as dis abled).
The inclu sio n of an in ternal RC oscillator also provides
the additional benefits of a Fail-Safe Clock Monitor
(FSCM) and Two-Speed Start-up. FSCM provides for
background monitoring of the peripheral clock and
automatic switch over in the event of its failure.
Two-Speed Start-up enables code to be executed
almost immediate ly on st art-up, whi le the primary cl ock
source completes its start-up delays.
All of these features are enabled and configured by
setting the appropriate configuration register bits.
PIC18F2455/2550/4455/4550
DS39632A-page 280 Advance Information 2004 Microchip Technology Inc.
25.1 Configuration Bits
The con figurat ion bit s can be program med (read as ‘0’)
or left unprogrammed (read as ‘1’) to select various
dev ice conf igurati ons. Th ese bits ar e mappe d starting
at program memory location 300000h.
The us er will note that address 300000h is beyond the
user program memory space. In fact, it belongs to the
configuration memor y space (300000h-3FFFFFh), which
can onl y be acce ssed us ing ta ble reads and ta ble writ es.
Programming the configuration registers is done in a
manner s imilar to p rogrammin g the Flas h memo ry. The
EECON1 regist er WR bit sta rts a se lf-tim ed w rite to the
configuration register. In normal operation mode, a
TBLWT instruction with the TBLPTR pointing to the
configu r ati on regi st er s ets u p th e a ddre ss a nd the data
for the configuration register write. Setting the WR bit
starts a long write to the configuration register. The
configuration registers are written a byte at a time. To
write or erase a configuration cell, a TBLWT instructi on
can writ e a ‘1’ or a ‘0’ into the cell. For additional details
on Flash programming, refer to Section 6.5 “Writing
to Flash Program Memory”.
TABLE 25-1: CONFIGURATION BITS AND DEVICE IDs
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default/
Unprogrammed
Value
300000h CONFIG1L —— USBPLL CPUDIV1 CPUDIV0 PLLDIV2 PLLDIV1 PLLDIV0 --00 0000
300001h CONFIG1H IESO FCMEN —— FOSC3 FOSC2 FOSC1 FOSC0 00-- 0101
300002h CONFIG2L —— VREGEN BORV1 BORV0 BOREN1 BOREN0 PWRTEN --01 1111
300003h CONFIG2H — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN ---1 1111
300005h CONFIG3H MCLRE — — — — LPT1OSC PBADEN CCP2MX 1--- -011
300006h CONFIG4L DEBUG XINST ICPRT ——LVP—STVREN100- -1-1
300008h CONFIG5L — — — —CP3
(1) CP2 CP1 CP0 ---- 1111
300009h CONFIG5H CPD CPB — — — — — — 11-- ----
30000Ah CONFIG6L — — — —WRT3
(1) WRT2 WRT1 WRT0 ---- 1111
30000Bh CONFIG6H WRTD WRTB WRTC —————111- ----
30000Ch CONFIG7L — — — —EBTR3
(1) EBTR2 EBTR1 EBTR0 ---- 1111
30000Dh CONFIG7H —EBTRB — — — — — — -1-- ----
3FFFFEh DEVID1 DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 xxxx xxxx(2)
3FFFFFh DEVID2 DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 0000 1011(2)
Legend: x = unknown, u = unchanged, - = unimplemented. Shaded cells are unimplemented, read as ‘0’.
Note 1: Unimplemented in PIC18FX455 devices; maintain this bit set.
2: See Register 25-15 f or DEVID1 values. DEVID re gisters are read-only and cannot be programmed by the user .
2004 Microchip Technology Inc. Advance Information DS39632A-page 281
PIC18F2455/2550/4455/4550
REGISTER 25-1: CONFIG1L: CONFIGURATION REGISTER 1 LOW (BYTE ADDRESS 300000h)
U-0 U-0 R/P-0 R/P-0 R/P-0 R/P-0 R/P-0 R/P-0
—— USBPLL CPUDIV1 CPUDIV0 PLLDIV2 PLLDIV1 PLLDIV0
bit 7 bit 0
bit 7-6 Unimplemented: Read as ‘0’
bit 5 USBPLL: USB Clock Selection bit
1 = USB clock source comes from the 96 MHz PLL divided by 2
0 = USB clock source comes directly from the primary oscillator block with no postscale
bit 4-3 CPUDIV1:CPUDIV0: Syste m Clock P ostscaler Se lecti on bits
For XT, HS, EC and ECIO Oscillator modes:
11 = Primary oscillator divided by 4 to derive system clock
10 = Primary oscillator divided by 3 to derive system clock
01 = Primary oscillator divided by 2 to derive system clock
00 = Primary oscillator used directly for system clock (no postscaler)
For XTPLL, HSPLL, ECPLL and ECPIO Oscillator modes:
11 = Primary oscillator divided by 6 to derive system clock
10 = Primary oscillator divided by 4 to derive system clock
01 = Primary oscillator divided by 3 to derive system clock
00 = Primary oscillator divided by 2 to derive system clock
bit 2-0 PLLDIV2:PLLDIV0: PLL Prescaler Selection bits
111 = Divide by 12 (48 MHz oscillator input)
110 = Divide by 10 (40 MHz oscillator input)
101 = Divide by 6 (24 MHz oscillator input)
100 = Divide by 5 (20 MHz oscillator input)
011 = Divide by 4 (16 MHz oscillator input)
010 = Divide by 3 (12 MHz oscillator input)
001 = Divide by 2 (8 MHz oscillator input)
000 = No prescale (4 MHz oscillator input drives PLL directly)
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC18F2455/2550/4455/4550
DS39632A-page 282 Advance Information 2004 Microchip Technology Inc.
REGISTER 25-2: CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h)
R/P-0 R/P-0 U-0 U-0 R/P-0 R/P-1 R/P-0 R/P-1
IESO FCMEN —— FOSC3 FOSC2 FOSC1 FOSC0
bit 7 bit 0
bit 7 IESO: Internal/External Oscillator Switchover bit
1 = Oscillator Switchover mode enabled
0 = Oscillator Switchover mode disabled
bit 6 FCMEN: Fail-Safe Clock Monitor Enable bit
1 = Fail-Safe Clock Monitor enabled
0 = Fail-Safe Clock Monitor disabled
bit 5-4 Unimplemented: Read as ‘0’
bit 3-0 FOSC3:FOSC0: Oscillator Selection bits(1)
111x = HS oscillator, PLL enabled (HSPLL)
110x = HS oscillator (HS)
1011 = Inte rnal oscillator, HS os cillator used by U SB (IN THS)
1010 = Internal oscillator, XT used by USB (INTXT)
1001 = Inte rnal oscillator, CLKO function on RA 6, E C used by USB (INTCKO)
1000 = Internal oscillator, port function on RA6, EC used by USB (INTIO)
0111 = EC oscillator, PLL enabled, CLKO function on RA6 (ECPLL)
0110 = EC oscillator, PLL ena bled, port function on RA 6 (ECP IO)
0101 = EC oscillator, CLKO function on RA6 (EC)
0100 = EC oscillator, port function on RA6 (ECIO)
001x = XT oscillator, PLL enabled (XTPLL)
000x = XT oscillator (XT), XT used by USB
Note 1: The m icroc ontroll er and USB modu le both us e the sel ected osc illato r as their cl ock
source in XT, HS and EC modes . The USB module uses the i ndicated XT, HS or EC
oscillator as its clock source whenever the microcontroller uses the internal
oscillator block.
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed u = Unchanged from programmed state
2004 Microchip Technology Inc. Advance Information DS39632A-page 283
PIC18F2455/2550/4455/4550
REGISTER 25-3: CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h)
U-0 U-0 R/P-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1
—— VREGEN BORV1 BORV0 BOREN1(1) BOREN0(1) PWRTEN(1)
bit 7 bit 0
bit 7-6 Unimplemented: Read as ‘0’
bit 5 VREGEN: USB Internal Voltage Regulator Enable bit
1 = USB voltage regulator enabled
0 = USB voltage regulator disabled
bit 4-3 BORV1:BORV0: Brown-out Reset Voltage bits
11 = VBOR set to 2.1V
10 = VBOR set to 2.8V
01 = VBOR set to 4.3V
00 = VBOR set to 4.6V
bit 2-1 BOREN1:BOREN0 Brown-out Reset Enable bits(1)
11 = Brown-out Reset enabled in hardware only (SBOREN is disabled)
10 = Brown-out Reset enabled in hardware only and disabled in Sleep mode
(SBOREN is disabled)
01 = Brown-out Reset enabled and controlled by software (SBOREN is enabled)
00 = Brown-out Reset disabled in hardware and software
bit 0 PWRTEN: Power-up Timer Enable bit(1)
1 = PWRT d i sabled
0 = PWRT enabled
Note 1: The Powe r-up T i mer is d ecoup led from Brown-o ut Reset, allowing these fe atures to
be independently controlled.
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed u = Unchanged from programmed state
PIC18F2455/2550/4455/4550
DS39632A-page 284 Advance Information 2004 Microchip Technology Inc.
REGISTER 25-4: CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h)
U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1
— — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN
bit 7 bit 0
bit 7-5 Unimplemented: Read as ‘0’
bit 4-1 WDTPS3:WDTPS0: Watchdog Timer Postscale Select bits
1111 = 1:32,768
1110 = 1:16,384
1101 = 1:8,192
1100 = 1:4,096
1011 = 1:2,048
1010 = 1:1,024
1001 = 1:512
1000 = 1:256
0111 = 1:128
0110 = 1:64
0101 = 1:32
0100 = 1:16
0011 = 1:8
0010 = 1:4
0001 = 1:2
0000 = 1:1
bit 0 WDTEN: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled (control is placed on the SWDTEN bit)
Legend:
R = Readable bit P = Programmab le bit U = Unimpleme nte d bit, read as ‘0’
-n = Value when device is unprogrammed u = Unchanged from programmed state
2004 Microchip Technology Inc. Advance Information DS39632A-page 285
PIC18F2455/2550/4455/4550
REGISTER 25-5: CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h)
R/P-1 U-0 U-0 U-0 U-0 R/P-0 R/P-1 R/P-1
MCLRE ———— LPT1OSC PBADEN CCP2MX
bit 7 bit 0
bit 7 MCLRE: MCLR Pin Enable bit
1 = MCLR pin enabled; RE3 input pin disabled
0 = RE3 input pin enabled; MCLR disabled
bit 6-3 Unimplemented: Read as ‘0’
bit 2 LPT1OSC: Low-Power Ti mer 1 Oscillator Enable bit
1 = Timer1 configured for low-power operation
0 = Timer1 configured for higher power operation
bit 1 PBADEN: PORTB A/D Enable bit
(Affects ADCON1 Reset state. ADCON1 controls PORTB<4:0> pin configuration.)
1 = PORTB<4:0> pins are configured as analog input channels on Reset
0 = PORTB<4:0> pins are configured as digital I/O on Reset
bit 0 CCP2MX: CCP2 Mux bit
1 = CCP2 input/output is multiplexed with RC1
0 = CCP2 input/output is multiplexed with RB3
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed u = Unchanged from programmed state
PIC18F2455/2550/4455/4550
DS39632A-page 286 Advance Information 2004 Microchip Technology Inc.
REGISTER 25-6: CONFIG4L: CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS 300006h)
R/P-1 R/P-0 R/P-0 U-0 U-0 R/P-1 U-0 R/P-1
DEBUG XINST ICPRT(1) ——LVP—STVREN
bit 7 bit 0
bit 7 DEBUG: Background Debugger Enable bit
1 = Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins
0 = Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
bit 6 XINST: Extended Instruction Set Enable bit
1 = Instruction set extension and Indexed Addressing mode enabled
0 = Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
bit 5 ICPRT: Dedicated In-Circuit Debug/Programming Port (ICPORT) Enable bit(1)
1 = ICPORT enabled
0 = ICPORT disabled
Note 1: Available only on PIC18F4455/4550 devices in 44-pin TQFP packages. Always
leave this bit clear in all other devices.
bit 4-3 Unimplemented: Read as ‘0’
bit 2 LVP: Single-Supply ICSP™ Enable bit
1 = Single-Supply ICSP enabled
0 = Single-Supply ICSP disabled
bit 1 Unimplemented: Read as ‘0’
bit 0 STVREN: Stack Full/Underflow Reset Enable bit
1 = Stack full/underflow will cause Reset
0 = Stack full/underflow will not cause Reset
Legend:
R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed u = Unchanged from programmed state
2004 Microchip Technology Inc. Advance Information DS39632A-page 287
PIC18F2455/2550/4455/4550
REGISTER 25-7: CONFIG5L: CONFIGURATION REGISTER 5 LOW (BYTE ADDRESS 300008h)
REGISTER 25-8: CONFIG5H: CONFIGURATION REGISTER 5 HIGH (BYTE ADDRESS 300009h)
U-0 U-0 U-0 U-0 R/C-1 R/C-1 R/C-1 R/C-1
— — — —CP3
(1) CP2 CP1 CP0
bit 7 bit 0
bit 7-4 Unimplemented: Read as ‘0’
bit 3 CP3: Code Protection bit(1)
1 = Block 3 (006000-007FFFh) not code-protected
0 = Block 3 (006000-007FFFh) code-protected
Note 1: Unimplemented in PIC18FX455 devices; maintain this bit set.
bit 2 CP2: Code Protection bit
1 = Block 2 (004000-005FFFh) not code-protected
0 = Block 2 (004000-005FFFh) code-protected
bit 1 CP1: Code Protection bit
1 = Block 1 (002000-003FFFh) not code-protected
0 = Block 1 (002000-003FFFh) code-protected
bit 0 CP0: Code Protection bit
1 = Block 0 (000800-001FFFh) not code-protected
0 = Block 0 (000800-001FFFh) code-protected
Legend:
R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed u = Unchanged from programmed state
R/C-1 R/C-1 U-0 U-0 U-0 U-0 U-0 U-0
CPD CPB — — — — — —
bit 7 bit 0
bit 7 CPD: Data EEPROM Code Protection bit
1 = Data EEPROM not code-protected
0 = Data EEPROM code-protected
bit 6 CPB: Boot Block Code Protection bit
1 = Boot block (000000-0007FFh) not code-protected
0 = Boot block (000000-0007FFh) code-protected
bit 5-0 Unimplemented: Read as ‘0’
Legend:
R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed u = Unchanged from programmed state
PIC18F2455/2550/4455/4550
DS39632A-page 288 Advance Information 2004 Microchip Technology Inc.
REGISTER 25-9: CONFIG6L: CONFIGURATION REGISTER 6 LOW (BYTE ADDRESS 30000Ah)
REGISTER 25-10: CONFIG6H: CONFIGURATION REGISTER 6 HIGH (BYTE ADDRESS 30000Bh)
U-0 U-0 U-0 U-0 R/C-1 R/C-1 R/C-1 R/C-1
— — — —WRT3
(1) WRT2 WRT1 WRT0
bit 7 bit 0
bit 7-4 Unimplemented: Read as ‘ 0’
bit 3 WRT3: Write Protection bit(1)
1 = Block 3 (006000-007FFFh) not write-protected
0 = Block 3 (006000-007FFFh) write-protected
Note 1: Unimplemented in PIC18FX455 devices; maintain this bit set.
bit 2 WRT2: Write Protection bit
1 = Block 2 (004000-005FFFh) not write-protected
0 = Block 2 (004000-005FFFh) write-protected
bit 1 WRT1: Write Protection bit
1 = Block 1 (002000-003FFFh) not write-protected
0 = Block 1 (002000-003FFFh) write-protected
bit 0 WRT0: Write Protection bit
1 = Block 0 (000800-001FFFh) not write-protected
0 = Block 0 (000800-001FFFh) write-protected
Legend:
R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed u = Unchanged from programmed state
R/C-1 R/C-1 R-1 U-0 U-0 U-0 U-0 U-0
WRTD WRTB WRTC(1) — — — — —
bit 7 bit 0
bit 7 WRTD: Data EEPROM Write Protection bit
1 = Data EEPROM not write-protected
0 = Data EEPROM write-protected
bit 6 WRTB: Boot Block Write Protection bit
1 = Boot block (000000-0007FFh) not write-protected
0 = Boot block (000000-0007FFh) write-protected
bit 5 WRTC: Configuration Register Write Protection bit(1)
1 = Configuration registers (300000-3000FFh) not write-protected
0 = Configuration registers (300000-3000FFh) write-protected
Note 1: This bit is read-only in normal execution mode; it can be written only in
Program mode.
bit 4-0 Unimplemented: Read as ‘0’
Legend:
R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed u = Unchanged from programmed state
2004 Microchip Technology Inc. Advance Information DS39632A-page 289
PIC18F2455/2550/4455/4550
REGISTER 25-11: CONFIG7L: CONFIGURATION REGISTER 7 LOW (BYTE ADDRESS 30000Ch)
REGISTER 25-12: CONFIG7H: CONFIGURATION REGISTER 7 HIGH (BYTE ADDRESS 30000Dh)
U-0 U-0 U-0 U-0 R/C-1 R/C-1 R/C-1 R/C-1
———— EBTR3(1) EBTR2 EBTR1 EBTR0
bit 7 bit 0
bit 7-4 Unimplemented: Read as ‘0’
bit 3 EBTR3: Table Read Protection bit(1)
1 = Block 3 (006000-007FFFh) not protected from table reads executed in other blocks
0 = Block 3 (006000-007FFFh) protected from table reads executed in other blocks
Note 1: Unimplemented in PIC18FX455 devices; maintain this bit set.
bit 2 EBTR2: Tab le Read Protec tion bit
1 = Block 2 (004000-005FFFh) not protected from table reads executed in other blocks
0 = Block 2 (004000-005FFFh) protected from table reads executed in other blocks
bit 1 EBTR1: Table Read Protection bit
1 = Block 1 (002000-003FFFh) not protected from table reads executed in other blocks
0 = Block 1 (002000-003FFFh) protected from table reads executed in other blocks
bit 0 EBTR0: Table Read Protection bit
1 = Block 0 (000800-001FFFh) not protected from table reads executed in other blocks
0 = Block 0 (000800-001FFFh) protected from table reads executed in other blocks
Legend:
R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed u = Unchanged from programmed state
U-0 R/C-1 U-0 U-0 U-0 U-0 U-0 U-0
— EBTRB — — — — — —
bit 7 bit 0
bit 7 Unimplemented: Read as ‘0’
bit 6 EBTRB: Boot Block Table Read Protection bit
1 = Boot block (000000-0007FFh) not protected from table reads executed in other blocks
0 = Boot block (000000-0007FFh) protected from table reads executed in other blocks
bit 5-0 Unimplemented: Read as ‘0’
Legend:
R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed u = Unchanged from programmed state
PIC18F2455/2550/4455/4550
DS39632A-page 290 Advance Information 2004 Microchip Technology Inc.
REGISTER 25-13: DEVICE ID REGISTER 1 FOR PIC18F2455/2550/4455/4550 DEVICES
REGISTER 25-14: DEVICE ID REGISTER 2 FOR PIC18F2455/2550/4455/4550 DEVICES
RRRRRRRR
DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0
bit 7 bit 0
bit 7-5 DEV2:DEV0: Device ID bits
101 = PIC18F2455
011 = PIC18F2550
100 = PIC18F4455
010 = PIC18F4550
bit 4-0 REV4:REV0: Revi si on ID bits
These bits are used to indicate the device revision.
Legend:
R = Read-only bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed u = Unchanged from programmed state
RRRRRRRR
DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3
bit 7 bit 0
bit 7-0 DEV10:DEV3: Device ID bits
These bits are used with the DEV2:DEV0 bits in the Device ID Register 1 to identify the
part number.
0000 1011 = PIC18F2455/2550/4455/4550 devices
Note: These values for DEV10:DEV3 may be shared with other devices. The specific
device is always identified by using the entire DEV10:DEV0 bit sequence.
Legend:
R = Read-only bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed u = Unchanged from programmed state
2004 Microchip Technology Inc. Advance Information DS39632A-page 291
PIC18F2455/2550/4455/4550
25.2 Wat chdog Timer (WDT)
For PIC18F 245 5/2 550 /44 55/4 55 0 dev ic es , the WDT is
driven by the INTRC source. When the WDT is
enabled , the c lock sour ce is al so enable d. The nom inal
WDT period is 4 ms and has the same stability as the
INTRC osc il la tor.
The 4 ms period of the WDT is multiplied by a 16-bit
postscaler. Any output of the WDT postscaler is
selected by a multiplexer , controlled by bits in Configu-
ration Register 2H. Available periods range from 4 ms
to 131.072 seconds (2.18 minutes). The WDT and
post scaler are cleare d when any of the following events
occur: a SLEEP or CLRWDT instruction is executed, the
IRCF bits (OSCCON<6:4>) are changed or a clock
failure has occurred.
.
25.2.1 CONTROL REGISTER
Regi ste r 25 -15 sh ow s t he WDT CON re gi s ter. This is a
readable and writ ab le re gis ter wh ic h co nt ains a control
bit that allows software to override the WDT enable
configuration bit, but only if the configuration bit has
disabled the WDT.
FIGURE 25-1: WDT BLOCK DIAGRAM
Note 1: The CLRWDT and SLEEP instructions
clear the WDT and postscaler counts
when executed.
2: Changing the setting of the IRCF bits
(OSCCON<6:4>) clears the WDT and
postscaler counts.
3: When a CLRWDT instruction is executed,
the postscaler count will be cleared.
INTRC Source
WDT
Wake-up
Reset
WDT
WDT Counter
Programmable P ostsca ler
1:1 to 1:32,768
Enable WDT
WDTPS<3:0>
SWDTEN
WDTEN
CLRWDT
4
from Power
Reset
All Device Resets
Sleep
INTRC Control
÷128
Change on IRCF bits Managed Modes
PIC18F2455/2550/4455/4550
DS39632A-page 292 Advance Information 2004 Microchip Technology Inc.
REGISTER 25-15: WDTCON REGISTER
TABLE 25-2: SUMMARY OF WATCHDOG TI MER REGISTERS
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
— — — — — — —SWDTEN
(1)
bit 7 bit 0
bit 7-1 Unimplemented: R ead as ‘0’
bit 0 SWDTEN: Software Controlled Watchdog Timer Enable bit(1)
1 = Watchdog Timer is on
0 = Watchdog Timer is off
Note 1: This bit has no effect if the configuration bit WDTEN is enabled.
Legend:
R = Readable bit W = Writable bit
U = Unimplemented bit, read as ‘0’ -n = Value at POR
Name Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
Reset
Values
on page
RCON IPEN SBOREN —RI TO PD POR BOR 52
WDTCON ———————SWDTEN52
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Watchdog Timer.
2004 Microchip Technology Inc. Advance Information DS39632A-page 293
PIC18F2455/2550/4455/4550
25.3 Two-Speed Start-up
The Two-Speed Start-up feature helps to minimize the
latency period from oscillator start-up to code execution
by allowing the microcontroller to use the INTRC
oscillator as a clock source until the primary clock
source is available. It is enabled by setting the IESO
configuration bit .
Two-Speed Start-up should be enabled only if the
primary oscillator mode is XT, HS, XTPLL or HSPLL
(Crystal-based modes). Other sources do not require
an OST start-up delay; for these, Two-Speed Start-up
should be disabled.
When ena bled, Resets and wake-ups from Sleep mode
cause the device to configur e itself to run from the inter-
nal oscillator block as the clock source, following the
time-out of the Power-up T imer after a Power-on Res et
is enabled. This allows almost immediate code
execution while the primary oscillator starts and the
OST is running. Once the OST times out, the device
automatically switches to PR I_RUN mod e.
Because the OSCCON register is cleared on Reset
event s , the IN T O SC (or pos t s ca ler) clock sourc e is not
initially available after a Reset event; the INTRC clock
is used directly at its base frequency. To use a higher
clock speed on wake-up, the INTOSC or postscaler
clock sour ces can be sele cted to provi de a higher cloc k
speed by set ti ng bi ts, IR CF2: IRCF 0, im medi at ely aft er
Reset. For wake-ups from Sleep, the INTOSC or
postscaler clock sources can be selected by setting,
IRCF2:IRCF0, prior to entering Sleep mode.
In all other power managed modes, T wo-Speed S tart-up
is not used. The device will be clocked by the currently
selected clock source until the primary clock source
becomes available. The setting of the IESO bit is
ignored.
25.3.1 SPECIAL CONSIDERATIONS FOR
USING TWO-SPEED START-UP
While using the INTRC oscillator in T wo-Speed S tart-up,
the device still obeys the normal command sequences
for entering power managed modes, including serial
SLEEP instructions (refer to Section 3.1.4 “Multiple
Sleep Commands”). In practice, this means that user
code can change the SCS1:SCS0 bit settings or issue
SLEEP instructions before the OST times out. This would
allow an application to briefly wake-up, perform routine
“housekeeping” tasks and return to Sleep before the
device starts to operate from the primary o scilla tor.
User code can a lso c heck if t he primar y clo ck s our ce i s
currently providi ng t he d ev ic e c loc ki ng by check in g th e
status of the OSTS bit (OSCCON<3>). If the bit is set,
the pr im ary osc il lat or i s p rovi di ng the clo ck. Ot he rwis e,
the internal oscillator block is providing the clock during
wake-up from Reset or Sleep mode.
FIGURE 25-2: TIMING TRANSITION FOR TWO-SPEED START-UP (INTOSC TO HSPLL)
Q1 Q3 Q4
OSC1
Peripheral
Program PC PC + 2
INTOSC
PLL Clock
Q1
PC + 6
Q2
Output
Q3 Q4 Q1
CPU Clock
PC + 4
Clock
Counter
Q2 Q2 Q3
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
Wake from Interrupt Event
TOST(1) TPLL(1)
12 n-1n
Clock
OSTS bit Set
Transition
Multiplexer
PIC18F2455/2550/4455/4550
DS39632A-page 294 Advance Information 2004 Microchip Technology Inc.
25.4 Fail-Safe Clock Monitor
The Fail-Safe Clock Monitor (FSCM) allows the
microc ont roll er to co ntinue ope rati on i n th e ev en t of a n
external oscill ator failu re by aut omatical ly swi tching th e
device clock to the internal oscillator block. The FSCM
functio n is enabled by setting th e FCMEN confi guration
bit.
When FSCM is enabled, the INTRC oscillator runs at
all times to mo nito r cl oc ks to pe rip herals and prov id e a
backup clock in the event of a clock failure. Clock
monitoring (shown in Figure 25-3) is accomplished by
crea ting a s ample clock signal, which i s the I NTRC o ut-
put divided by 64. This allows ample time between
FSCM sample clocks for a peripheral clock edge to
occur. The peripheral device clock and the sample
clock are present ed as inpu ts to the Clock Monitor latch
(CM). The CM is set on the falling edge of the device
clock source, but cleared on the rising edge of the
sample clock.
FIGURE 25-3: FSCM BLOCK DIAGRAM
Clock failure is tested for on the falling edge of the
sample clock. If a sample clock falling edge occurs
while CM is still set, a clock failure has been detected
(Figure 25-4). This causes the following:
• the FSCM generates an oscillator fail interrupt by
setting bit, OSCFIF (PIR2<7>);
• the dev ice c lo ck s our ce is sw itc hed to th e i nte rnal
oscill ato r blo ck (O SCC ON i s not up dated to s how
the current clock source – this is the fail-safe
condition); and
•the WDT is reset.
During switchover, the postscaler frequency from the
internal oscillator block may n ot be sufficiently stable for
timing sensitive applications. In these cases, it may be
desirable to select another cloc k configuration and enter
an alternate power managed mode. This can be done to
attempt a partial recovery or execute a controlled shut-
down. See Section 3.1.4 “Multiple Sleep Commands”
and Section 25.3.1 “Special Considerations for
Using Two-Speed Start-up” for more details.
To use a higher clock speed on wake-up, the INTOSC
or postscaler clock sources can be selected to provide
a higher clock speed by setting bits, IRCF2:IRCF0,
immediate ly a fter Res et. Fo r wak e-up s fro m Sle ep, th e
INTOSC or postscaler clock sources can be selected
by set ting, IRCF2 :IRCF0, prior to e ntering Sl eep mod e.
The FS CM will dete ct failure s of the p rimary or sec ond-
ary clock sources only. If the internal oscillator block
fails, no failure would be detected, nor would any action
be possible.
25.4.1 FSCM AND THE WATCHDOG T IMER
Both the FSCM and the WDT are clocked by the
INTRC oscillator. Since the WDT operates with a
separate divider and counter, disabling the WDT has
no ef fect on the op eration of the INTRC oscill ator when
the FSCM is enabled.
As already noted, the clock source is switched to the
INTOSC clock when a clock failure is detected.
Depending on the frequency selected by the
IRCF2:IRCF0 bits, this may mean a substantial change
in the speed of code execution. If the WDT is enabled
with a small prescale value, a decrease in clock speed
allows a WDT time-out to occur and a subsequent
device Reset. For this reason, Fail-Safe Clock Monitor
event s also res et the WDT and post scaler , all owing it to
start timing from when execution speed was changed
and dec reasing the li kelihood of an erroneou s time-out.
25.4.2 EXITING FAIL-SAFE OPERATION
The fail-safe condition is terminated by either a device
Reset or by entering a power managed mode. On
Reset, the controller starts the primary clock source
specified in Configuration Register 1H (with any
required start-up delays that are required for the oscil-
lator mode, such as OST or PLL timer). The INTOSC
multiplexer provides the device clock until the primary
clock source becomes ready (similar to a Two-Speed
Start-up). The clock source is then switched to the pri-
mary cl ock (in dic ate d by the OST S bit in th e O SCCO N
register becoming set). The Fail-Safe Clock Monitor
then resumes monitoring the peripheral clock.
The primary clock source may never become ready
during st art-up. In this case, operatio n is clocked by the
INTOSC multiplexer . The OSCCON register will remain
in its Reset state until a power managed mode is
entered.
Peripheral
INTRC ÷ 64
S
C
Q
(32 µs) 488 Hz
(2.048 ms)
Clock Monitor
Latch (CM)
(edge-triggered)
Clock
Failure
Detected
Source
Clock
Q
2004 Microchip Technology Inc. Advance Information DS39632A-page 295
PIC18F2455/2550/4455/4550
FIGURE 25-4: FSCM TIMING DIAGRAM
25.4.3 FSCM INTERRUPTS IN POWER
MANAGED MODES
By entering a power managed mode, the clock
multiplexer selects the clock source selected by the
OSCCON register. Fail-Safe Monitoring of the power
manage d clock s ource resu mes in the power managed
mode.
If an oscillator failure occurs during power managed
operation, the subsequent events depend on whether
or not the oscillator failure interrupt is enabled. If
enabled (OSCFIF = 1), code execution will be clocked
by the INTOSC multiplexer. An automatic transition
back to the failed clock source will not occur.
If the interrupt is disabled, subsequent interrupts while
in Idle mode will cause the CPU to begin executing
instructions while being clocked by the INTOSC
source.
25.4.4 POR OR WAKE-UP FROM SLEEP
The FS CM is d esigned to de tect oscillato r failure at any
point after the device has exited Power-on Reset
(POR) or Low-Power Sleep mode. When the primary
device clock is either EC or INTRC modes, monitoring
can begin immediately following these events.
For oscillator modes involving a crystal or resonator
(HS, HSPLL, LP or XT), the situation is somewhat dif-
ferent. Since the oscillator may require a start-up time
consid erab ly l on ger than the F C SM s am ple c lo ck time,
a false clock failure may be detected. To prevent this,
the internal oscillator block is automatically configured
as the de vice clock and functio ns until the primary clock
is stable (the OST and PLL timers have timed out). This
is identical to Two-Speed Start-up mode. Once the
primary clo ck is stable, the INTRC re turn s to it s rol e a s
the FSCM source.
As noted in Section 25.3.1 “Special Considerations
for Using Two-Speed Start-up”, it is also possible to
select ano ther clock confi guration and en ter an alternate
power managed mode while waiting for the primary clock
to become st able. When the new power m anaged mode
is selec ted, the primary clo ck is disabled .
OSCFIF
CM Output
Device
Clock
Output
Sample Clock
Failure
Detected
Oscillator
Failure
Note: The device clock is normally at a much higher frequency than the sample clock. The relative frequencies in this
example have been chosen for clarity.
(Q)
CM Test CM Tes t CM Test
Note: The sa me logi c tha t prevents false oscilla-
tor failure interrupts on POR or wake from
Sleep wi ll also preven t the detect ion of the
oscillator’s failure to start at all following
these events. This can be avoided by
monitoring the OSTS bit and using a
timing routine to determine if the oscillator
is taking too long to start. Even so, no
oscillator failure interrupt will be flagged.
PIC18F2455/2550/4455/4550
DS39632A-page 296 Advance Information 2004 Microchip Technology Inc.
25.5 Program Verification and
Code Protection
The overall structure of the code protection on the
PIC18 Flash devices differs significantly from other
PICmicro® devices.
The user program memory is divided into five blocks.
One of these is a boot block of 2 Kbytes. T he remainder
of the memory is divided into four blocks on binary
boundaries.
Each of the five blocks has three code protection bits
associated with them. They are:
• Code-Protect bit (CPn)
• Write-Protect bit (WRTn)
• External Block Table Read bit (EBTRn)
Figure 25-5 shows the program memory organization
for 24 and 32-K byte dev ices and th e spe ci fic c ode pro-
tection bit associated with each block. The actual
locations of the bits are summarized in Table 25-3.
FIGURE 25-5: CODE-PROTECTED PROGRAM MEMORY FOR PIC18F2455/2550/4455/4550
TABLE 25-3: SUMMARY OF CODE PROTECTION REGISTERS
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
300008h CONFIG5L ————CP3
(1) CP2 CP1 CP0
300009h CONFIG5H CPD CPB — — — — — —
30000Ah CONFIG6L ————WRT3
(1) WRT2 WRT1 WRT0
30000Bh CONFIG6H WRTD WRTB WRTC — — — — —
30000Ch CONFIG7L ———— EBTR3(1) EBTR2 EBTR1 EBTR0
30000Dh CONFIG7H — EBTRB — — — — — —
Legend: Shaded cell s are uni mp lem en ted .
Note 1: Unimplem ented in PIC18FX455 devices; maintain t his bit set .
MEMORY SIZE/DEVICE Block Code Protection
Controlled By:
24 Kbytes
(PIC18F2455/2555) 32 Kbytes
(PIC18F2550/4550) Address
Range
Boot Block Boot Bloc k 000000h
0007FFh CPB, WRTB, EBTRB
Block 0 Block 0 000800h
001FFFh CP0, WR T0 , EBTR0
Block 1 Block 1 002000h
003FFFh CP1, WR T1 , EBTR1
Block 2 Block 2 004000h
005FFFh CP2, WR T2 , EBTR2
Unimplemented
Read ‘0’s Block 3 006000h
007FFFh CP3, WR T3 , EBTR3
Unimplemented
Read ‘0’s Unimplemented
Read ‘0’s
008000h
1FFFFFh
(Unimplemented Memor y Space )
2004 Microchip Technology Inc. Advance Information DS39632A-page 297
PIC18F2455/2550/4455/4550
25.5.1 PROGRAM MEMORY
CODE PROTECTION
The program memory may be read to or written from
any location using the table read and table write
instructions. The device ID may be read with table
reads. The configuration registers may be read and
written with the table read and table write instructions.
In normal execution mode, the CPn bits have no dire ct
effect. CPn bits inhibit external reads and writes. A
block of user memory may be protected from table
writes if the WRTn configuration bit is ‘0’. The EBTRn
bits control table reads. For a block of user memory
with the EBTRn bit set to ‘0’, a table read instruction
that executes from within that block is allowed to read.
A table read instruction that executes from a location
outside of that block is not allowed to read and will
result in reading ‘0’s. Figures 25-6 through 25-8
illustrate table write and table read protection.
FIGURE 25-6: TABLE WRITE (WRTn) DISALLOWED
Note: Code protection bits may only be written to
a ‘0’ from a ‘1’ state. It is not possible to
write a ‘1’ to a bit in the ‘0’ st ate. Code p ro-
tection b its are only set to ‘1’ b y a full C hip
Erase or Block Erase function. The full
Chip Erase and Blo ck Erase func tions can
only be initiated via ICSP operation or an
external programmer.
000000h
0007FFh
000800h
001FFFh
002000h
003FFFh
004000h
005FFFh
006000h
007FFFh
WRTB, EBTRB = 11
WR T0, EBTR0 = 01
WR T1, EBTR1 = 11
WR T2, EBTR2 = 11
WR T3, EBTR3 = 11
TBLWT*
TBLP T R = 0008 FFh
PC = 001FFEh
TBLWT*
PC = 005FFEh
Register Values Program Memory Configuration Bit Settings
Results: All table writes disabled to Blockn whenever WRTn = 0.
PIC18F2455/2550/4455/4550
DS39632A-page 298 Advance Information 2004 Microchip Technology Inc.
FIGURE 25-7: EXTERNAL BLOCK TABLE READ (EBTRn) DISALLOWED
FIGURE 25-8: EXTERNAL BLOCK TABLE READ (EBTRn) ALLOWED
WRTB, EBTRB = 11
WRT0, EBTR0 = 10
WRT1, EBTR1 = 11
WRT2, EBTR2 = 11
WRT3, EBTR3 = 11
TBLRD*
TBLP T R = 0008 FFh
PC = 003FFEh
Results: All table reads from external blocks to Blockn are disabled whenever EBTRn = 0.
TABLAT register returns a value of ‘0’.
Register Va lues Program Memory Configuration Bit Settings
000000h
0007FFh
000800h
001FFFh
002000h
003FFFh
004000h
005FFFh
006000h
007FFFh
WRTB, EBTRB = 11
WRT0, EBTR0 = 10
WRT1, EBTR1 = 11
WRT2, EBTR2 = 11
WRT3, EBTR3 = 11
TBLRD*
TBLP T R = 0008F Fh
PC = 001FFEh
Register Values Program Memory Configuration Bit Settings
Results: Table reads permitted within Blockn, even when EBTRBn = 0.
TABLAT register returns the value of the data at the location TBLPTR.
000000h
0007FFh
000800h
001FFFh
002000h
003FFFh
004000h
005FFFh
006000h
007FFFh
2004 Microchip Technology Inc. Advance Information DS39632A-page 299
PIC18F2455/2550/4455/4550
25.5.2 DATA EEPROM
CODE PROTECTION
The entire data EEPROM is protected from external
reads and writes by two bits: CPD and WRTD. CPD
inhibits external reads and writes of data EEPROM.
WRTD inhibits internal and external writes to data
EEPROM. The CPU can continue to read and write
data EEPROM regardless of the prote ction bit setti ngs.
25.5.3 CONFIGURATION REGISTER
PROTECTION
The con figurat ion registers can be write-pro tected. Th e
WRTC bit controls protection of the configuration
registers. In normal execution mode, the WRTC bit is
readable only. WRTC can only be written via ICSP
operation or an external programmer.
25.6 ID Locations
Eight memory locations (200000h-200007h) are
designated as ID locations, where the user can store
checksum or other code identification numbers. These
locatio ns are b oth read abl e a nd w ri table d urin g no rma l
execution through the TBLRD and TBLWT instructions
or du r ing p r ogr am / ve rif y. T h e ID loca t io n s c a n be r e ad
when the device is code-prot ecte d.
25.7 In-Circuit Serial Progra mming
PIC18F2455/2550/4455/4550 microcontrollers can be
serially programmed while in the end application circuit.
This is simply done with two lines for clock and data
and three other lines for power, ground and the
programming voltage. This allows customers to manu-
facture boards with unprogrammed devices and then
program the microcontroller just before shipping the
product. This also allows the most recent firmware or a
custom firmware to be programmed.
25.8 In-Circuit Debugger
When the DEBUG con figuration bit is prog rammed to a
‘0’, the In-Circuit Debugger functionality is enabled.
This funct ion al lows s imple debug ging f unctio ns wh en
use d wi t h M PLA B® IDE. When the microcontroller has
this featu r e ena ble d, so me reso urc es are not av ail abl e
for gene ral us e. Table 25-4 shows whi ch res ource s ar e
required by the background debugger.
TABLE 25-4: DEBUGGER RESOURCES
To use the In-Circuit Debugger function of the micro-
controller, the design must implement In-Circuit Serial
Programming connections to MCLR/VPP/RE3, VDD,
VSS, RB7 and RB6. This will interface to the In-Circuit
debugger module available from Microchip or one of
the third party deve lopment tool compani es.
25.9 Special ICPORTS Features
(Designated Packages Only)
Under specific circumstances, the No Connect (NC)
pins of PIC18F4455/4550 devices in 44-pin TQFP
packages can provide additional functionality. These
featur es are contro lled by devi ce co nfigur ation b it s an d
are available only in this package type and pin count.
25.9.1 DEDICATED ICD/ ICSP PORT
The 44-pin TQFP devices can use NC pins to provide
an alternate port for In-Circuit Debugging (ICD) and
In-Circuit Serial Programming (ICSP). These pins are
collectively known as the Dedicated ICSP/ICD port,
since t hey are not sh ared with any o ther fun ction of the
device.
When implemented, the dedicated port activates three
NC pins to pro vide a n alte rnate de vice Reset, data an d
clock ports. None of these ports overlap with standard
I/O pins, making the I/O pins available to the user’s
application.
The dedi cated ICS P/IC D Port i s e nab le d by se tting the
ICPRT configuration bit. The port functions the same
way as the legacy ICSP/ICD port on RB6/RB7.
Tabl e 25-5 iden tifies the fun ctionall y equivalent p ins for
ICSP and ICD purposes.
TABLE 25-5: EQUIVALENT PINS FOR
LEGACY AND DEDICATE
ICD/ICSP™ PORTS
I/O pins: RB 6, RB7
Stack: 2 levels
Program Memory: 512 bytes
Data Memory: 10 bytes
Pin Name Pin
Type Pin Fun ct io n
Legacy
Port Dedicated
Port
MCLR/VPP/
RE3 NC/ICRST/
ICVPP P Device R eset and
Programming
Enable
RB6/KBI2/
PGC NC/ICCK/
ICPGC I Se ria l Clo ck
RB7/KBI3/
PGD NC/ICDT/
ICPGD I/O Se ria l D ata
Legend: I = Input, O = Output, P = Power
PIC18F2455/2550/4455/4550
DS39632A-page 300 Advance Information 2004 Microchip Technology Inc.
Even when the dedicated port is enabled, the ICSP and
ICD functi ons remain availab le through the legac y port.
When V IH is s een o n th e MC LR/VPP/RE3 pin , th e s t a te
of the ICRST/ICVPP pin is ignored.
25.9.2 28-PIN EMULATION
PIC18F4455/4550 devices in 44-pin TQFP packages
also have the ability to change the ir configuration und er
external control for debugging purposes. This allows
the device to behave as if it were a PIC18F2455/2550
28-pin device.
This 28-pi n Configurati on mo de is con trol led throu gh a
single pin, NC/ICPORTS. Connecting this pin to VSS
forces the device to function as a 28-pin device; fea-
tures normally associated with the 40/44-pin devices
are disabled, along with their corresponding control
registers and bits. This includes PORTD and PORTE,
the SPP and the Enhanced PWM functionality of
CCP1. On the other hand, connecting the pin to VDD
forces th e device to function in its default co nfigura tion.
The configuration option is only available when back-
ground debugging and the dedicated ICD/ICSP port
are bot h enable d (DEBUG configuratio n bit is clear an d
ICPRT configuration bit is set). When disabled,
NC/ICPORTS is a no connect pin.
25.10 Single-Supply ICSP Programming
The LVP configuration bit enables Single-Supply ICSP
Programming (formerly known as Low-Voltage ICSP
Programming or LVP). When Single-Supply Program-
ming is enabled, the microcontroller can be
programmed without requiring high voltage being
applied to the MCLR/VPP/RE3 pin, but the
RB5/KBI1/PGM pin is then dedicated to controlling
Program mode entry and is not available as a general
purpose I/O p in.
While programming using Single-Supply Program-
ming, VDD is applied to the MCLR/VPP/RE3 pin as in
normal execution mode. To enter Programming mode,
VDD is applied to the PGM pin.
If Single-Supply ICSP Programming mode will not be
used, the LVP bit can be cl eared. RB5 /KBI1/ PGM the n
become s a vaila ble as the dig ita l I/O p in, RB 5. The LVP
bit may be set or cleared only when using standard
high-voltage programming (VIHH applied to the
MCLR/VPP/RE3 pin). Once LVP has been disabled,
only the standard high-voltage programming is
available and must be used to program the device.
Memory that is not code -protected ca n be erased usin g
either a Bloc k Erase, or erased row by row , the n written
at any s pecified VDD. If co de-protected m emory is to be
erase d, a Block Erase is required. If a Block Eras e is to
be performed when using Low-Voltage Programming,
the device must be supplied with VDD of 4.5V to 5.5V.
Note 1: The I CPORT c onfiguration bit can onl y be
programmed through the default ICSP
port.
2: The ICPORT configuration bit must be
maintained clear f or a ll 28-pin and 40-pin
devices; otherwise unexpected operation
may occur.
Note 1: High-Voltage Programming is always
available, regardless of the state of the
LVP bit, by apply ing VIHH to the MCLR pin.
2: While in Lo w -Volt ag e ICSP Progra mm in g
mode, the RB5 pin c an no longe r be used
as a g eneral pu rpose I /O pin an d should
be held low during normal operation.
3: When using Low-Voltage ICSP Program-
ming (LVP) and the pull-ups on PORTB
are enabled, bit 5 in the TRISB register
must be cleared to disable the pull-up on
RB5 and ensure the proper operation of
the device.
4: If the device Master Clear is disabled,
verify that either of the following is done to
ensure proper entry into ICSP mode:
a) disable Low-Voltage Programming
(CONFIG4l< 2> = 0); or
b) make certain that RB5/KBI1/PGM
is held low during entry into ICSP.
2004 Microchip Technology Inc. Advance Information DS39632A-page 301
PIC18F2455/2550/4455/4550
26.0 INSTRUCTION SET SUMMARY
PIC18F2455/2550/4455/4550 devices incorporate the
standard set of 75 PIC18 core instructions, as well as
an extended set of 8 new instructions for the optimiza-
tion of code that is recursive or that utilizes a software
stack. The extended set is discussed later in this
section.
26.1 Standard Instruction Set
The standard PIC18 instruction set adds many
enhancements to the previous PICmicro instruction
sets, while maintaining an easy migration from these
PICmicro instruction sets. Most instructions are a sin-
gle program memory word (16 bits) but there are four
instructions that require two program memory
locations.
Each single-word instruction is a 16-bit word divided
into an o pcode, whi ch specifies the instructi on type and
one or more operands, which further specify the
operati on of the instructi on.
The instruction set is highly orthogonal and is grouped
into four basic categories:
•Byte-oriented operations
•Bit-oriented operations
•Literal operati ons
•Control operations
The PIC18 instruction set summary in Table 26-2 lists
byte-oriented, bit-oriented, literal and control
operations. Table 26-1 shows the opcode field
descriptions.
Most byte-oriented in str uct ions have three op eran ds :
1. The file register (specified by ‘f’)
2. The destination of the result (specified by ‘d’)
3. The access ed memory (specified by ‘a’)
The file reg ist er desig nator ‘f’ spec ifies which file regi s-
ter is to be used by the instruction. The destination
designator ‘d’ specifies where the result of the opera-
tion is to be placed. If ‘d’ is zero, the result is placed in
the WREG register. If ‘d’ is one, the result is placed in
the file register specified in the instruction.
All bit-oriented instructions have three operands:
1. The file register (specified by ‘f’)
2. The bit in the file register (specified by ‘b’)
3. The access ed memory (specified by ‘a’)
The bit field design ator ‘b’ sele cts the numb er of the bit
affected by the operation, while the file register desig-
nator ‘f’ represents the number of the file in which the
bit is located.
The literal ins truc tions m ay use so me of the follo wing
operands:
• A literal value to be loaded into a file register
(specified by ‘k’)
• The desired FSR register to load the literal value
into (specif ied by ‘f’)
• No operand requir ed
(specified by ‘—’)
The control ins tructions ma y use some of the foll owing
operands:
• A program memory address (specified by ‘n’)
• The mode of th e CALL or RETURN instructions
(specified by ‘s’)
• The mode of the table read and table write
ins tructions (spe cified by ‘m’)
• No operand requir ed
(specified by ‘—’)
All instructions are a single word, except for four
double-word instructions. These instructions were
made double-word to contain the required information
in 32 bits. In the second word, the 4 MSbs are ‘1’s. If
this second word is executed as an instruction (by
it se lf), it will exe cu te as a NOP.
All single-word instructions are executed in a single
inst ruc tion c yc le , un le ss a conditio nal te st is tru e or the
program counter is changed as a result of the instruc-
tion. In th ese cases, the execution takes two i nstruction
cycles with the additional instruction cycle(s) executed
as a NOP.
The doub le-word inst ructions exe cute in two ins truction
cycles.
One in struction cycle consist s of f our oscil lator peri ods.
Thus, for an oscillator frequency of 4 MHz, the normal
inst ruction ex ecution ti me is 1 µs. If a c onditiona l test is
true, or the program counter is changed as a result of
an instruction, the instruction execution time is 2 µs.
Two-word branch instructions (if true) would take 3 µs.
Figur e 26-1 sh ows the gener al forma ts that the instruc-
tions can have. All examples use the convention ‘nnh’
to represent a hexadecimal number.
The Instruction Set Summary, shown in Table 26-2,
lists the standard instructions recognized by the
Microchip Assembler (MPASMTM).
Section 26.1.1 “Standard Instruction Set” provides
a description of each instruction.
PIC18F2455/2550/4455/4550
DS39632A-page 302 Advance Information 2004 Microchip Technology Inc.
TABLE 26-1: OPCODE FIELD DESCRIPTIONS
Field Description
aRAM access bit
a = 0: RAM location in Access RAM (BSR register is ignored)
a = 1: RAM bank is specified by BSR register
bbb Bit address within an 8-bit file register (0 to 7).
BSR Bank Select Register. Used to select the current RAM bank.
C, DC, Z, OV, N ALU status bits: Carry, Digit Carry, Zero, Overflow, Negative.
dDestination select bit
d = 0: store result in WREG
d = 1: store result in file register f
dest Destination: either the WREG register or the specified register file location.
f8-bit register file address (00h to FFh) or 2-bit FSR designator (0h to 3h).
fs12-bit register file address (000h to FFFh). This is the source address.
fd12-bit register file address (000h to FFFh). This is the destination address.
GIE Global Interrupt Enable bit.
kLiteral field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value).
label Label name.
mm The mode of the TBLPTR register for the table read and table write instructions.
Only used with table read and table write instructions:
*No change to register (such as TBLPTR with table reads and writes)
*+ Post-Increment register (suc h as TBLPTR with table reads and writes)
*- Post-Decrement register (such as TBLPTR with table reads and writes)
+* Pre-Increment register (such as TBLPTR with table reads and writes)
nThe relative address (2’s complement number) for relative branch instructions or the direct address for
Call/Branch and Return instructions.
PC Program Counter.
PCL Program Counter Low Byte.
PCH Program Counter High Byte.
PCLATH Program Counter High Byte Latch.
PCLATU Program Counter Upper Byte Latch.
PD Power-down bit.
PRODH Product of Multiply High Byte.
PRODL Product of Multiply Low Byte.
sFast Call/Return mode select bit
s = 0: do not update into/from shadow registers
s = 1: certain registers loaded into/from shadow registers (fast mode)
TBLPTR 21-bit Table Pointer (points to a program memory location).
TABLAT 8-bit Table Latch.
TO Time-out bit.
TOS Top-of-Stack.
uUnused or unchanged.
WDT Watchdog Timer.
WREG Working register (accumulator).
xDon’t care (‘0’ or ‘1’). The assembler will generate code with x = 0. It is the recommended form of use for
compatibility with all Microchip software tools.
zs7-bit offset value for indirect addressing of register files (source).
zd7-bit offset value for indirect addressing of register files (destination).
{ } Optional argument.
[text] Indicates an indexed address.
(text) The contents of text.
[expr]<n> Specifies bit n of the register indicated by the pointer expr.
→Assigned to.
< > Register bit field.
∈In the set of.
italics User defined term (font is Courier).
2004 Microchip Technology Inc. Advance Information DS39632A-page 303
PIC18F2455/2550/4455/4550
FIGURE 26-1: GENERAL FORMAT FOR INSTRUCTIONS
Byte-oriented file register operations
15 10 9 8 7 0
d = 0 for result destination to be WREG register
OPCODE d a f (FILE #)
d = 1 for result destina tion to be file register (f)
a = 0 to force Access Bank
Bit-oriented file register operations
15 12 11 9 8 7 0
OPCODE b (BIT #) a f (FILE #)
b = 3-bit position of bit in file register (f)
Literal operations
15 8 7 0
OPCODE k (literal)
k = 8-bit immediate value
Byte to Byte move operations (2-word)
15 12 11 0
OPCODE f (Source FILE #)
CALL, GOTO and Branch operations
15 8 7 0
OPCODE n<7:0> (literal)
n = 20-bit immediate value
a = 1 for BSR to select bank
f = 8-bit file register address
a = 0 to force Acc ess Bank
a = 1 for BSR to select bank
f = 8-bit file register address
15 12 11 0
1111 n<19:8> (literal)
15 12 11 0
1111 f (Desti n a tion FILE #)
f = 12-bit file register address
Control operations
Example Instruction
ADDWF MYREG, W, B
MOVFF MYREG1, MYREG2
BSF MYREG, bit, B
MOVLW 7Fh
GOTO Label
15 8 7 0
OPCODE n<7:0> (literal)
15 12 11 0
1111 n<19:8> (literal)
CALL MYFUNC
15 11 10 0
OPCOD E n<1 0 :0> ( li t e r a l )
S = Fast bit
BRA MYFUNC
15 8 7 0
OPCODE n<7:0> (literal) BC MYFUNC
S
PIC18F2455/2550/4455/4550
DS39632A-page 304 Advance Information 2004 Microchip Technology Inc.
TABLE 26-2: PIC18FXXXX INSTRUCTION SET
Mnemonic,
Operands Description Cycles 16-Bit I nst ructio n Word Status
Affected Notes
MSb LSb
BYTE-ORIENT ED OPERATIONS
ADDWF
ADDWFC
ANDWF
CLRF
COMF
CPFSEQ
CPFSGT
CPFSLT
DECF
DECFSZ
DCFSNZ
INCF
INCFSZ
INFSNZ
IORWF
MOVF
MOVFF
MOVWF
MULWF
NEGF
RLCF
RLNCF
RRCF
RRNCF
SETF
SUBFWB
SUBWF
SUBWFB
SWAPF
TSTFSZ
XORWF
f, d, a
f, d, a
f, d, a
f, a
f, d, a
f, a
f, a
f, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
fs, fd
f, a
f, a
f, a
f, d, a
f, d, a
f, d, a
f, d, a
f, a
f, d, a
f, d, a
f, d, a
f, d, a
f, a
f, d, a
Add WREG and f
Add WREG and Carry bit to f
AND WREG with f
Clear f
Complement f
Compare f wit h W R EG, skip =
Compare f wit h W R EG, skip >
Compare f wit h W R EG, skip <
Decrem ent f
Decrement f, Skip if 0
Decrement f, Skip if Not 0
Increment f
Increment f, Skip if 0
Increment f, Skip if Not 0
Inclusive O R W R EG wi t h f
Move f
Move fs (source) to 1st word
fd (destination) 2nd word
Move WREG to f
Multiply WREG with f
Negate f
Rotate Left f through Carry
Rotate Left f (No Carry)
Rotate Right f through Carry
Rotate Right f (No Carry)
Set f
Subtract f from WREG with
borrow
Subtract WREG from f
Subtract WREG from f with
borrow
Swap nibbles in f
Test f, skip if 0
Exclusive OR WREG with f
1
1
1
1
1
1 (2 or 3)
1 (2 or 3)
1 (2 or 3)
1
1 (2 or 3)
1 (2 or 3)
1
1 (2 or 3)
1 (2 or 3)
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1 (2 or 3)
1
0010
0010
0001
0110
0001
0110
0110
0110
0000
0010
0100
0010
0011
0100
0001
0101
1100
1111
0110
0000
0110
0011
0100
0011
0100
0110
0101
0101
0101
0011
0110
0001
01da
00da
01da
101a
11da
001a
010a
000a
01da
11da
11da
10da
11da
10da
00da
00da
ffff
ffff
111a
001a
110a
01da
01da
00da
00da
100a
01da
11da
10da
10da
011a
10da
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
C, DC, Z, OV, N
C, DC, Z, OV, N
Z, N
Z
Z, N
None
None
None
C, DC, Z, OV, N
None
None
C, DC, Z, OV, N
None
None
Z, N
Z, N
None
None
None
C, DC, Z, OV, N
C, Z, N
Z, N
C, Z, N
Z, N
None
C, DC, Z, OV, N
C, DC, Z, OV, N
C, DC, Z, OV, N
None
None
Z, N
1, 2
1, 2
1,2
2
1, 2
4
4
1, 2
1, 2, 3, 4
1, 2, 3, 4
1, 2
1, 2, 3, 4
4
1, 2
1, 2
1
1, 2
1, 2
1, 2
1, 2
4
1, 2
Note 1: When a Port register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configure d as i nput and is
driven low by an external device, the data will be written back with a ‘0’.
2: If this in st ru ct ion i s executed on the TMR 0 re gi st er (a nd w here appl ic able, ‘d’ = 1), the prescaler will be cleared if
assigned.
3: If Progr am Counter (PC) is modifie d or a conditional t est is true, the instruction requi r es t wo cycles. Th e second
cycle is executed as a NOP.
4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP
unles s t he f irst w or d of th e i nst r uct ion retrieves the information embedded in t hese 16 bits. This ens ures that all
program memory locations have a valid instruction.
2004 Microchip Technology Inc. Advance Information DS39632A-page 305
PIC18F2455/2550/4455/4550
BIT-ORIENTED OPERATIONS
BCF
BSF
BTFSC
BTFSS
BTG
f, b, a
f, b, a
f, b, a
f, b, a
f, d, a
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, S k i p if Set
Bit Toggle f
1
1
1 (2 or 3)
1 (2 or 3)
1
1001
1000
1011
1010
0111
bbba
bbba
bbba
bbba
bbba
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
None
None
None
None
None
1, 2
1, 2
3, 4
3, 4
1, 2
CONTROL OPERATIONS
BC
BN
BNC
BNN
BNOV
BNZ
BOV
BRA
BZ
CALL
CLRWDT
DAW
GOTO
NOP
NOP
POP
PUSH
RCALL
RESET
RETFIE
RETLW
RETURN
SLEEP
n
n
n
n
n
n
n
n
n
n, s
—
—
n
—
—
—
—
n
s
k
s
—
Branch if Carr y
Branch if Neg at i ve
Branch if Not Carry
Branch if Not Negative
Branch if Not Overflow
Branch if Not Ze ro
Branch if Ove rfl ow
Branch Unconditionally
Branch if Zero
Call subroutine 1st word
2nd word
Clear Watchdog Timer
Decimal Adjust WREG
Go to address 1st word
2nd wo rd
No Operation
No Operation
Pop top of return stack (TOS)
Push top of re tu rn stack (TOS)
Relative Call
Software device Re set
Return from interrupt enable
Return with literal in WREG
Return from Subroutine
Go into Standby mode
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
2
1 (2)
2
1
1
2
1
1
1
1
2
1
2
2
2
1
1110
1110
1110
1110
1110
1110
1110
1101
1110
1110
1111
0000
0000
1110
1111
0000
1111
0000
0000
1101
0000
0000
0000
0000
0000
0010
0110
0011
0111
0101
0001
0100
0nnn
0000
110s
kkkk
0000
0000
1111
kkkk
0000
xxxx
0000
0000
1nnn
0000
0000
1100
0000
0000
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
kkkk
kkkk
0000
0000
kkkk
kkkk
0000
xxxx
0000
0000
nnnn
1111
0001
kkkk
0001
0000
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
kkkk
kkkk
0100
0111
kkkk
kkkk
0000
xxxx
0110
0101
nnnn
1111
000s
kkkk
001s
0011
None
None
None
None
None
None
None
None
None
None
TO, PD
C
None
None
None
None
None
None
All
GIE/GIEH,
PEIE/GIEL
None
None
TO, PD
4
TABLE 26-2: PIC18FXXXX INSTRUCTION SET (CONTINUED)
Mnemonic,
Operands Description Cycles 16-Bit I nst ructio n Word Status
Affected Notes
MSb LSb
Note 1: When a Port register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configure d as i nput and is
driven low by an external device, the data will be written back with a ‘0’.
2: If this in st ru ct ion i s executed on the TMR 0 r egi st er (a nd w here appl ic able, ‘d’ = 1), the prescaler will be cleared if
assigned.
3: If Progr am C ou n ter (PC) is mo dif ie d or a conditional test is true, the instruction requi r es t w o cy cl es. The second
cycle is executed as a NOP.
4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP
unles s t he f irst w or d of th e i nst r uct ion retrieves the information embedded in t hese 16 bits. This ens ures that all
program memory locations have a valid instruction.
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LITERAL OPERATIONS
ADDLW
ANDLW
IORLW
LFSR
MOVLB
MOVLW
MULLW
RETLW
SUBLW
XORLW
k
k
k
f, k
k
k
k
k
k
k
Add l i t eral and WREG
AND literal with WREG
Inclusive OR literal with WREG
Move liter al (1 2-b i t) 2nd wor d
to FSR(f) 1st word
Move literal to BSR<3:0>
Move literal to WREG
Multiply lite ral with WREG
Return with literal in WREG
Subtract WREG from literal
Exclusive OR literal with WREG
1
1
1
2
1
1
1
2
1
1
0000
0000
0000
1110
1111
0000
0000
0000
0000
0000
0000
1111
1011
1001
1110
0000
0001
1110
1101
1100
1000
1010
kkkk
kkkk
kkkk
00ff
kkkk
0000
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
C, DC, Z, OV, N
Z, N
Z, N
None
None
None
None
None
C, DC, Z, OV, N
Z, N
DATA MEMORY ↔ PROGRAM MEMORY OPE RATIONS
TBLRD*
TBLRD*+
TBLRD*-
TBLRD+*
TBLWT*
TBLWT*+
TBLWT*-
TBLWT+*
Table Read
Table Read with post-increment
Table R ead with post-dec rem ent
Table Read with pre-increment
Table Write
Table Write w ith post-incr em ent
Tabl e Write wi t h po st -d ec re me nt
Table Write w ith pr e- i ncr em ent
2
2
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
1000
1001
1010
1011
1100
1101
1110
1111
None
None
None
None
None
None
None
None
TABLE 26-2: PIC18FXXXX INSTRUCTION SET (CONTINUED)
Mnemonic,
Operands Description Cycles 16-Bit I nst ructio n Word Status
Affected Notes
MSb LSb
Note 1: When a Port register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configure d as i nput and is
driven low by an external device, the data will be written back with a ‘0’.
2: If this in st ru ct ion i s executed on the TMR 0 re gi st er (a nd w here appl ic able, ‘d’ = 1), the prescaler will be cleared if
assigned.
3: If Progr am Counter (PC) is modifie d or a conditional t est is true, the instruction requi r es t wo cycles. Th e second
cycle is executed as a NOP.
4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP
unles s t he f irst w or d of th e i nst r uct ion retrieves the information embedded in t hese 16 bits. This ens ures that all
program memory locations have a valid instruction.
2004 Microchip Technology Inc. Advance Information DS39632A-page 307
PIC18F2455/2550/4455/4550
26.1.1 STANDARD INSTRUCTION SET
ADDLW ADD literal to W
Syntax: ADDLW k
Operands: 0 ≤ k ≤ 255
Operation: (W) + k → W
Stat us Af fected: N, OV, C, DC, Z
Encoding: 0000 1111 kkkk kkkk
Description: The contents of W are added to the
8-bit literal ‘k’ and the result is placed in
W.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal ‘k’ Process
Data Wri te to W
Example: ADDLW 15h
Before Instruction
W = 10h
After Instruction
W = 25h
ADDWF ADD W to f
Syntax: ADDWF f {,d {,a}}
Operands: 0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation: (W) + (f) → dest
Stat us Af fected: N, OV, C, DC, Z
Encoding: 0010 01da ffff ffff
Description: Add W to register ‘f’. If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’
(default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select t he
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write to
destination
Example: ADDWF REG, 0, 0
Before Instruction
W = 17h
REG = 0C2h
After Instruction
W = 0D9h
REG = 0C2h
Note: All PIC18 instruc tions may t ake an op tional label arg ument, prec eding the instr uct ion mne monic, for u se in
symbolic addressin g. If a label is used, the instruction format then becomes: {label } instruction argument(s).
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ADDWFC ADD W and Carry bit to f
Syntax: ADDWFC f {,d {,a}}
Operands: 0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation: (W) + (f) + (C) → dest
Stat us Af fected: N, OV, C, DC, Z
Encoding: 0010 00da ffff ffff
Description: Add W, the Carry flag and data memory
location ‘f’. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed in data memory location ‘f’.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in In d e x e d L it e r a l Offset Add r e ssin g
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Wri te to
destination
Example: ADDWFC REG, 0, 1
Before Instruction
Carry bit = 1
REG = 02h
W=4Dh
After Instruction
Carry bit = 0
REG = 02h
W = 50h
ANDLW AND literal with W
Syntax: ANDLW k
Operands: 0 ≤ k ≤ 255
Operation: (W) .AND. k → W
Status Af fected: N, Z
Encoding: 0000 1011 kkkk kkkk
Description: The contents of W are ANDed with the
8-bit literal ‘k’. The result is placed in W.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read literal
‘k’ Process
Data Write to W
Example: ANDLW 05Fh
Before Instruction
W=A3h
After Instruction
W = 03h
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ANDWF AND W with f
Syntax: ANDWF f {,d {,a}}
Operands: 0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation: (W) .AND. (f) → dest
Status Af fected: N, Z
Encoding: 0001 01da ffff ffff
Description: The contents of W are AND’ed with
register ‘f’. If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored back
in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select t he
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in In d e x e d L it e r a l Offset Add r e ssin g
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write to
destination
Example: ANDWF REG, 0, 0
Before Instruction
W = 17h
REG = C2h
After Instruction
W = 02h
REG = C2h
BC Branch if Carry
Syntax: BC n
Operands: -128 ≤ n ≤ 127
Operation: if Carry bit is ‘1’
(PC) + 2 + 2n → PC
Status Af fected: None
Encoding: 1110 0010 nnnn nnnn
Description: If the Carry bit is ‘1’, then the program
will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruct ion.
Words: 1
Cycles: 1(2)
Q Cycle Activity:
If Jump: Q1 Q2 Q3 Q4
Decode Read literal
‘n’ Process
Data Write to PC
No
operation No
operation No
operation No
operation
If No Jump:
Q1 Q2 Q3 Q4
Decode Read literal
‘n’ Process
Data No
operation
Example: HERE BC 5
Before Instruction
PC = address (HERE)
After Instruction
If Carry = 1;
PC = address (HERE + 12)
If Carry = 0;
PC = address (HERE + 2)
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BCF Bit Clear f
Syntax: BCF f, b {,a}
Operands: 0 ≤ f ≤ 255
0 ≤ b ≤ 7
a ∈ [0,1]
Operation: 0 → f<b>
Status Af fected: None
Encoding: 1001 bbba ffff ffff
Description: Bit ‘b’ in register ‘f’ is cleared.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select t he
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in In d e x e d L it e r a l Offset Add r e ssin g
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Proc ess
Data Write
register ‘f’
Example: BCF FLAG_REG, 7, 0
Before Instruction
FLAG_R EG = C7h
After Instruction
FLAG_REG = 47h
BN Branch if Negative
Syntax: BN n
Operands: -128 ≤ n ≤ 127
Operation: if Negative bit is ‘1’
(PC) + 2 + 2n → PC
Status Af fected: None
Encoding: 1110 0110 nnnn nnnn
Description: If the Negative bit is ‘1’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruct ion.
Words: 1
Cycles: 1(2)
Q Cycle Activity:
If Jump: Q1 Q2 Q3 Q4
Decode Read literal
‘n’ Process
Data Write to PC
No
operation No
operation No
operation No
operation
If No Jump:
Q1 Q2 Q3 Q4
Decode Read literal
‘n’ Process
Data No
operation
Example: HERE BN Jump
Before Instruction
PC = address (HERE)
After Instruction
If Negative = 1;
PC = address (Jump)
If Negative = 0;
PC = address (HERE + 2)
2004 Microchip Technology Inc. Advance Information DS39632A-page 311
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BNC Branch if Not Carry
Syntax: BNC n
Operands: -128 ≤ n ≤ 127
Operation: if Carry bit is ‘0’
(PC) + 2 + 2n → PC
Status Af fected: None
Encoding: 1110 0011 nnnn nnnn
Description: If the Carry bit is ‘0’, then the program
will branch.
The 2’s complement number ‘2n’ is
added to the PC. S ince the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruct ion.
Words: 1
Cycles: 1(2)
Q Cycle Activity:
If Jump: Q1 Q2 Q3 Q4
Decode Read literal
‘n’ Process
Data Write to PC
No
operation No
operation No
operation No
operation
If No Jump:
Q1 Q2 Q3 Q4
Decode Read literal
‘n’ Process
Data No
operation
Example: HERE BNC Jump
Before Instruction
PC = address (HERE)
After Instruction
If Carry = 0;
PC = address (Jump)
If Carry = 1;
PC = address (HERE + 2)
BNN Branch if Not Negative
Syntax: BNN n
Operands: -128 ≤ n ≤ 127
Operation: if Negative bit is ‘0’
(PC) + 2 + 2n → PC
Status Af fected: None
Encoding: 1110 0111 nnnn nnnn
Description: If the Negative bit is ‘0’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruct ion.
Words: 1
Cycles: 1(2)
Q Cycle Activity:
If Jump: Q1 Q2 Q3 Q4
Decode Read literal
‘n’ Process
Data Write to PC
No
operation No
operation No
operation No
operation
If No Jump:
Q1 Q2 Q3 Q4
Decode Read literal
‘n’ Process
Data No
operation
Example: HERE BNN Jump
Before Instruction
PC = address (HERE)
After Instruction
If Negative = 0;
PC = address (Jump)
If Negative = 1;
PC = address (HERE + 2)
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BNOV Branch if Not Overflow
Syntax: BNOV n
Operands: -128 ≤ n ≤ 127
Operation: if Overflow bit is ‘0’
(PC) + 2 + 2n → PC
Status Af fected: None
Encoding: 1110 0101 nnnn nnnn
Description: If the Overflow bit is ‘0’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. S ince the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruct ion.
Words: 1
Cycles: 1(2)
Q Cycle Activity:
If Jump: Q1 Q2 Q3 Q4
Decode Read literal
‘n’ Process
Data Write to PC
No
operation No
operation No
operation No
operation
If No Jump:
Q1 Q2 Q3 Q4
Decode Read literal
‘n’ Process
Data No
operation
Example: HERE BNOV Jump
Before Instruction
PC = address (HERE)
After Instruction
If Overflow = 0;
PC = address (Jump)
If Overflow = 1;
PC = address (HERE + 2)
BNZ Branch if Not Zero
Syntax: BNZ n
Operands: -128 ≤ n ≤ 127
Operation: if Zero bit is ‘0’
(PC) + 2 + 2n → PC
Status Af fected: None
Encoding: 1110 0001 nnnn nnnn
Description: If the Zero bit is ‘0’, then the program
will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruct ion.
Words: 1
Cycles: 1(2)
Q Cycle Activity:
If Jump: Q1 Q2 Q3 Q4
Decode Read literal
‘n’ Process
Data Write to PC
No
operation No
operation No
operation No
operation
If No Jump:
Q1 Q2 Q3 Q4
Decode Read literal
‘n’ Process
Data No
operation
Example: HERE BNZ Jump
Before Instruction
PC = address (HERE)
After Instruction
If Zero = 0;
PC = address (Jump)
If Zero = 1;
PC = address (HERE + 2)
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BRA Unconditional Branch
Syntax: BRA n
Operands: -1024 ≤ n ≤ 1023
Operation: (PC) + 2 + 2n → PC
Status Af fected: None
Encoding: 1101 0nnn nnnn nnnn
Description: Add the 2’s complement number ‘2n’ to
the PC. Since the PC will have incre-
mented to fetch the next instruction, the
new address will be PC + 2 + 2n. This
instruction is a two-cycle instruction.
Words: 1
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read literal
‘n’ Process
Data Write to PC
No
operation No
operation No
operation No
operation
Example: HERE BRA Jump
Before Instruction
PC = address (HERE)
After Instruction
PC = address (Jump)
BSF Bit Set f
Syntax: BSF f, b {,a}
Operands: 0 ≤ f ≤ 255
0 ≤ b ≤ 7
a ∈ [0,1]
Operation: 1 → f<b>
Status Af fected: None
Encoding: 1000 bbba ffff ffff
Description: Bit ‘b’ in register ‘f’ is set.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select t he
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write
register ‘f’
Example: BSF FLAG_REG, 7, 1
Before Instruction
FLAG_REG = 0Ah
After Instruction
FLAG_REG = 8Ah
PIC18F2455/2550/4455/4550
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BTFSC Bit Test File, Skip if Clear
Syntax: BTFSC f, b {,a}
Operands: 0 ≤ f ≤ 255
0 ≤ b ≤ 7
a ∈ [0,1]
Operation: skip if (f<b>) = 0
Status Af fected: None
Encoding: 1011 bbba ffff ffff
Description: If bit ‘b’ in register ‘f’ is ‘0’, then the next
instruction is skipped. If bit ‘b’ is ‘0’, then
the next instruction fetched during the
current instruction execution is discarded
and a NOP is executed instead, making
this a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected. If
‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates in
Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh).
See Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data No
operation
If skip: Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
No
operation No
operation No
operation No
operation
Example: HERE
FALSE
TRUE
BTFSC
:
:
FLAG, 1, 0
Before Instruction
PC = address (HERE)
After Instruction
If FLAG<1> = 0;
PC = address (TRUE)
If FLAG<1> = 1;
PC = address (FALSE)
BTFSS Bit Test File, Skip if Set
Syntax: BTFSS f, b {,a}
Operands: 0 ≤ f ≤ 255
0 ≤ b < 7
a ∈ [0,1]
Operation: skip if (f<b>) = 1
Status Af fected: None
Encoding: 1010 bbba ffff ffff
Description: If bit ‘b’ in register ‘f’ is ‘1’, then the next
instruction is skipped. If bit ‘b’ is ‘1’, then
the next instruction fetched during the
current instruction execution is discarded
and a NOP is executed instead, making
this a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected. If
‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh).
See Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data No
operation
If skip: Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
No
operation No
operation No
operation No
operation
Example: HERE
FALSE
TRUE
BTFSS
:
:
FLAG, 1, 0
Before Instruction
PC = address (HERE)
After Instruction
If FLAG<1> = 0;
PC = address (FALSE)
If FLAG<1> = 1;
PC = address (TRUE)
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BTG Bit Toggle f
Syntax: BTG f, b {,a}
Operands: 0 ≤ f ≤ 255
0 ≤ b < 7
a ∈ [0,1]
Operation: (f<b>) → f<b>
Status Af fected: None
Encoding: 0111 bbba ffff ffff
Description: Bit ‘b’ in data mem ory location ‘f’ is
inverted.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26. 2.3 “Byte-Orien ted and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write
register ‘f’
Example: BTG PORTC, 4, 0
Before Instruction:
PORTC = 0111 0101 [75h]
After Instruction:
PORTC = 0110 0101 [65h]
BOV Bra nch if Overf low
Syntax: BOV n
Operands: -128 ≤ n ≤ 127
Operation: if Overflow bit is ‘1’
(PC) + 2 + 2n → PC
Status Af fected: None
Encoding: 1110 0100 nnnn nnnn
Description: If the Overflow bit is ‘1’ , th en th e
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruct ion.
Words: 1
Cycles: 1(2)
Q Cycle Activity:
If Jump: Q1 Q2 Q3 Q4
Decode Read literal
‘n’ Process
Data Write to PC
No
operation No
operation No
operation No
operation
If No Jump:
Q1 Q2 Q3 Q4
Decode Read literal
‘n’ Process
Data No
operation
Example: HERE BOV Jump
Before Instruction
PC = address (HERE)
After Instruction
If Overflow = 1;
PC = address (Jump)
If Overflow = 0;
PC = address (HERE + 2)
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BZ Branch if Zero
Syntax: BZ n
Operands: -128 ≤ n ≤ 127
Operation: if Zero bit is ‘1’
(PC) + 2 + 2n → PC
Status Af fected: None
Encoding: 1110 0000 nnnn nnnn
Description: If the Zero bit is ‘1’, then the program
will branch.
The 2’s complement number ‘2n’ is
added to the PC. S ince the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruct ion.
Words: 1
Cycles: 1(2)
Q Cycle Activity:
If Jump: Q1 Q2 Q3 Q4
Decode Read literal
‘n’ Process
Data Write to PC
No
operation No
operation No
operation No
operation
If No Jump:
Q1 Q2 Q3 Q4
Decode Read literal
‘n’ Process
Data No
operation
Example: HERE BZ Jump
Before Instruction
PC = address (HERE)
After Instruction
If Zero = 1;
PC = address (Jump)
If Zero = 0;
PC = address (HERE + 2)
CALL Subroutine Call
Syntax: CALL k {,s}
Operands: 0 ≤ k ≤ 1048575
s ∈ [0,1]
Operation: (PC) + 4 → TOS,
k → PC<20:1>,
if s = 1
(W) → WS,
(S tatus) → STATUSS,
(BSR) → BSRS
Status Af fected: None
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>) 1110
1111
110s
k19kkk
k7kkk
kkkk
kkkk0
kkkk8
Description: Subroutine call of entire 2-Mbyte
memory range. First, return address
(PC+ 4) is pushed onto the return stack.
If ‘s’ = 1, the W, Status and BSR
registers are also pushed into their
respective shadow registers, WS,
STATUS S and BSRS. If ‘s’ = 0, no
update occurs (default). Then, the
20-bit value ‘k’ is loaded into PC<20:1>.
CALL is a two-cycle instruction.
Words: 2
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read literal
‘k’<7:0>, Push PC to
stack Read literal
‘k’<19:8>,
Write to PC
No
operation No
operation No
operation No
operation
Example: HERE CALL THERE,1
Before Instruction
PC = address (HERE)
After Instruction
PC = address (THERE)
TOS = address (HERE + 4)
WS = W
BSRS = BSR
STATUSS = Status
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CLRF Clear f
Syntax: CLRF f {,a}
Operands: 0 ≤ f ≤ 255
a ∈ [0,1]
Operation: 000h → f
1 → Z
Status Af fected: Z
Encoding: 0110 101a ffff ffff
Description: Clears the contents of the specified
register.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select t he
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in In d e x e d L it e r a l Offset Add r e ssin g
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write
register ‘f’
Example: CLRF FLAG_REG,1
Before Instruction
FLAG_REG = 5Ah
After Instruction
FLAG_REG = 00h
CLRWDT Clear Watchdog Timer
Syntax: CLRWDT
Operands: None
Operation: 000h → WDT,
000h → WDT postscaler,
1 → TO,
1 → PD
Status Af fected: TO, PD
Encoding: 0000 0000 0000 0100
Description: CLRWDT instruction resets the
Watchdog Timer. It also resets the
postscaler of the WDT. Status bits, TO
and PD, are set.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No
operation Process
Data No
operation
Example: CLRWDT
Before Instruction
WDT Counter = ?
After Instruction
WDT Counter = 00h
WDT Postscaler = 0
TO =1
PD =1
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COMF Complement f
Syntax: COMF f {,d {,a}}
Operands: 0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation: → dest
Status Af fected: N, Z
Encoding: 0001 11da ffff ffff
Description: The contents of register ‘f’ are
complemented. If ‘d’ is ‘0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select t he
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in In d e x e d L it e r a l Offset Add r e ssin g
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Proc ess
Data Write to
destination
Example: COMF REG, 0, 0
Before Instruction
REG = 13h
After Instruction
REG = 13h
W=ECh
(f
)
CPFSEQ Compare f with W, skip if f = W
Syntax: CPF SE Q f {,a}
Operands: 0 ≤ f ≤ 255
a ∈ [0,1]
Operation: (f) – (W),
skip if (f) = (W)
(unsigned comparison)
Status Af fected: None
Encoding: 0110 001a ffff ffff
Description: Compares the contents of data memory
location ‘f’ to the contents of W by
performing an unsigned subtraction.
If ‘f’ = W, then the fetched instruction is
discarded and a NOP is executed
instead, making this a two-cycle
instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select t he
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data No
operation
If skip: Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
No
operation No
operation No
operation No
operation
Example: HERE CPFSEQ REG, 0
NEQUAL :
EQUAL :
Before Instruction
PC Address = HERE
W=?
REG = ?
After Instruction
If REG = W;
PC = Address (EQUAL)
If REG ≠ W;
PC = Address (NEQUAL)
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CPFSGT Compare f with W, skip if f > W
Syntax: CPFSGT f {,a}
Operands: 0 ≤ f ≤ 255
a ∈ [0,1]
Operation: (f) – (W),
skip if (f) > (W)
(unsigned comparison)
Status Af fected: None
Encoding: 0110 010a ffff ffff
Description: Compares the contents of data memory
location ‘f’ to the contents of the W by
performing an unsigned subtraction.
If the contents of ‘f’ are greater than the
contents of WREG, then the fetched
instruction is discarded and a NOP is
executed instead, making this a
two-cycle instruct ion.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select t he
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in In d e x e d L it e r a l Offset Add r e ssin g
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data No
operation
If skip: Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
No
operation No
operation No
operation No
operation
Example: HERE CPFSGT REG, 0
NGREATER :
GREATER :
Before Instruction
PC = Address (HERE)
W= ?
After Instruction
If REG > W;
PC = Address (GREATER)
If REG ≤ W;
PC = Address (NGREATER)
CPFSLT Compare f with W, skip if f < W
Syntax: CPFSLT f {,a}
Operands: 0 ≤ f ≤ 255
a ∈ [0,1]
Operation: (f) – (W),
skip if (f) < (W)
(unsigned comparison)
Status Af fected: None
Encoding: 0110 000a ffff ffff
Description: Compares the contents of data memory
location ‘f’ to the contents of W by
performing an unsigned subtraction.
If the contents of ‘f’ are less than the
contents of W, then the fetched
instruction is discarded and a NOP is
executed instead, making this a
two-cycle instruct ion.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select t he
GPR bank (default).
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data No
operation
If skip: Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
No
operation No
operation No
operation No
operation
Example: HERE CPFSLT REG, 1
NLESS :
LESS :
Before Instruction
PC = Address (HERE)
W= ?
After Instruction
If REG < W;
PC = Address (LESS)
If REG ≥ W;
PC = Address (NLESS)
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DAW Decimal Adjust W Register
Syntax: DAW
Operands: None
Operation: If [W<3:0> > 9] or [DC = 1] then
(W<3:0>) + 6 → W<3:0>;
else
(W<3:0>) → W<3:0>;
If [W <7:4> + D C > 9] or [ C = 1] then
(W<7:4>) + 6 + DC → W<7:4>;
else
(W<7:4>) + DC → W<7:4>
Status Af fected: C
Encoding: 0000 0000 0000 0111
Description: DAW adjusts the eight-bit value in W,
resulting from the earlier addition of two
variables (each in packed BCD format)
and produces a correct packed BCD
result.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register W Process
Data Write
W
Example 1:
DAW
Before Instruction
W=A5h
C=0
DC = 0
After Instruction
W = 05h
C=1
DC = 0
Example 2:
Before Instruction
W=CEh
C=0
DC = 0
After Instruction
W = 34h
C=1
DC = 0
DECF Decrement f
Syntax: DECF f {,d {,a}}
Operands: 0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation: (f) – 1 → dest
Stat us Af fected: C, DC, N, OV, Z
Encoding: 0000 01da ffff ffff
Description: Decrem ent register ‘f ’. If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’
(default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select t he
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write to
destination
Example: DECF CNT, 1, 0
Before Instruction
CNT = 01h
Z=0
After Instruction
CNT = 00h
Z=1
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DECFSZ Decrement f, skip if 0
Syntax: DECFSZ f {,d {,a}}
Operands: 0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation: (f) – 1 → dest,
skip if result = 0
Status Af fected: None
Encoding: 0010 11da ffff ffff
Description: The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If the result is ‘0’, the next instruction,
which is already fetched, is discarded
and a NOP is executed instead, making
it a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in In d e x e d L it e r a l Offset Add r e ssin g
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write to
destination
If skip: Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
No
operation No
operation No
operation No
operation
Example: HERE DECFSZ CNT, 1, 1
GOTO LOOP
CONTINUE
Before Instruction
PC = Address (HERE)
After Instruction
CNT = CNT – 1
If CNT = 0;
PC = Address (CONTINUE)
If CNT ≠0;
PC = Address (HERE + 2)
DCFSNZ Decrement f, skip if not 0
Syntax: DCFSNZ f {,d {,a}}
Operands: 0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation: (f) – 1 → dest,
skip if result ≠ 0
Status Af fected: None
Encoding: 0100 11da ffff ffff
Description: The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If the result is not ‘0’, the next
instruction, which is already fetched, is
discarded and a NOP is executed
instead, making it a two-cycle
instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write to
destination
If skip: Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
No
operation No
operation No
operation No
operation
Example: HERE DCFSNZ TEMP, 1, 0
ZERO :
NZERO :
Before Instruction
TEMP = ?
After Instruction
TEMP = T EM P – 1,
If TEMP = 0;
PC = Address (ZERO)
If TEMP ≠0;
PC = Address (NZERO)
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GOTO Unconditional Branch
Syntax: GOTO k
Operands: 0 ≤ k ≤ 1048575
Operation: k → PC<20:1>
Status Af fected: None
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>) 1110
1111
1111
k19kkk
k7kkk
kkkk
kkkk0
kkkk8
Description: GOTO allows an unconditional branch
anywhere within the entire
2-Mbyte memory range. The 20-bit
value ‘k’ is loaded into PC<20:1>.
GOTO is always a two-cycle
instruction.
Words: 2
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read literal
‘k’<7:0>, No
operation Read literal
‘k’<19:8>,
Write to PC
No
operation No
operation No
operation No
operation
Example: GOTO THERE
After Instruction
PC = Address (THERE)
INCF Increm ent f
Syntax: INCF f {,d {,a}}
Operands: 0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation: (f) + 1 → dest
Status Affected: C, DC, N, OV, Z
Encoding: 0010 10da ffff ffff
Description: The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select t he
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write to
destination
Example: INCF CNT, 1, 0
Before Instruction
CNT = FFh
Z=0
C=?
DC = ?
After Instruction
CNT = 00h
Z=1
C=1
DC = 1
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INCFSZ Increment f, skip if 0
Syntax: INCFSZ f {,d {,a}}
Operands: 0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation: (f) + 1 → dest,
skip if result = 0
Status Af fected: None
Encoding: 0011 11da ffff ffff
Description: The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’. (default)
If the result is ‘0’, the next instruction,
which is already fetched, is discarded
and a NOP is executed instead, making
it a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select t he
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in In d e x e d L it e r a l Offset Add r e ssin g
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write to
destination
If skip: Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
No
operation No
operation No
operation No
operation
Example: HERE INCFSZ CNT, 1, 0
NZERO :
ZERO :
Before Instruction
PC = Address (HERE)
After Instruction
CNT = CNT + 1
If CNT = 0;
PC = Address (ZERO)
If CNT ≠0;
PC = Address (NZERO)
INFSNZ Increment f, skip if not 0
Syntax: INFSNZ f {,d {,a}}
Operands: 0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation: (f) + 1 → dest,
skip if result ≠ 0
Status Af fected: None
Encoding: 0100 10da ffff ffff
Description: The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If the result is not ‘0’, the next
instruction, which is already fetched, is
discarded and a NOP is executed
instead, making it a two-cycle
instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select t he
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write to
destination
If skip: Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
No
operation No
operation No
operation No
operation
Example: HERE INFSNZ REG, 1, 0
ZERO
NZERO
Before Instruction
PC = Address (HERE)
After Instruction
REG = REG + 1
If REG ≠0;
PC = Address (NZERO)
If REG = 0;
PC = Address (ZERO)
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IORLW Inclusive OR literal with W
Syntax: IORLW k
Operands: 0 ≤ k ≤ 255
Operation: (W) .OR. k → W
Status Af fected: N, Z
Encoding: 0000 1001 kkkk kkkk
Description: The contents of W are ORed with the
eight-bit literal ‘k’. The result is placed in
W.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal ‘k’ Process
Data Wri te to W
Example: IORLW 35h
Before Instruction
W=9Ah
After Instruction
W=BFh
IORWF Inclusive OR W with f
Syntax: IORWF f {,d {,a}}
Operands: 0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation: (W) .OR. (f) → dest
Status Af fected: N, Z
Encoding: 0001 00da ffff ffff
Description: Inclusive OR W with register ‘f’. If ‘d’ is
‘0’, the result is placed in W. If ‘d’ is ‘1’,
the result is placed back in register ‘f’
(default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select t he
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write to
destination
Example: IORWF RESULT, 0, 1
Before Instruction
RESULT = 13h
W = 91h
After Instruction
RESULT = 13h
W = 93h
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LFSR Load FSR
Syntax: LFSR f, k
Operands: 0 ≤ f ≤ 2
0 ≤ k ≤ 4095
Operation: k → FSRf
Status Af fected: None
Encoding: 1110
1111
1110
0000
00ff
k7kkk
k11kkk
kkkk
Description: The 12-bit literal ‘k’ is loaded into the
File Select Register pointed to by ‘f’.
Words: 2
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read literal
‘k’ MSB Process
Data Write
literal ‘k’
MSB to
FSRfH
Decode Read literal
‘k’ LSB Pr ocess
Data Write literal
‘k’ to FSRfL
Example: LFSR 2, 3ABh
After Instruction
FSR2H = 03h
FSR2L = ABh
MOVF Move f
Syntax: MOVF f {,d {,a}}
Operands: 0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation: f → dest
Status Af fected: N, Z
Encoding: 0101 00da ffff ffff
Description: The contents of register ‘f’ are moved to
a destination dependent upon the
status of ‘d’. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
Location ‘f’ can be anywhere in the
256-byte bank.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select t he
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write W
Example: MOVF REG, 0, 0
Before Instruction
REG = 22h
W=FFh
After Instruction
REG = 22h
W = 22h
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MOVFF Move f to f
Syntax: MOVFF fs,fd
Operands: 0 ≤ fs ≤ 4095
0 ≤ fd ≤ 4095
Operation: (fs) → fd
Status Af fected: None
Encoding:
1st word (source)
2nd word (destin.) 1100
1111
ffff
ffff
ffff
ffff
ffffs
ffffd
Description: The contents of source register ‘fs’ are
moved to destination register ‘fd’.
Location of source ‘f s’ can be anywhere
in the 4096-byte data space (000h to
FFFh) and location of destination ‘fd’
can also be anywhere from 000h to
FFFh.
Either source or destination can be W
(a useful special situation).
MOVFF is particularly useful for
transferring a dat a memory location to a
peripheral register (such as the transmit
buffer or an I/O port).
The MOVFF instruction cannot use the
PCL, TOSU, TOSH or TOSL as the
destination register.
Words: 2
Cycles: 2 (3)
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
(src)
Process
Data No
operation
Decode No
operation
No dummy
read
No
operation Write
register ‘f’
(dest)
Example: MOVFF REG1, REG2
Before Instruction
REG1 = 33h
REG2 = 11h
After Instruction
REG1 = 33h
REG2 = 33h
MOVLB Move litera l to low nibbl e in BSR
Syntax: MOVLW k
Operands: 0 ≤ k ≤ 255
Operation: k → BSR
Status Af fected: None
Encoding: 0000 0001 kkkk kkkk
Description: The eight-bit literal ‘k’ is loaded into the
Bank Select Register (BSR). The value
of BSR<7:4> always remains ‘0’,
regardless of the value of k7:k4.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal ‘k’ Process
Data Write litera l
‘k’ to BSR
Example: MOVLB 5
Before Instruction
BSR Register = 02h
After Instruction
BSR Register = 05h
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MOVLW Move literal to W
Syntax: MOVLW k
Operands: 0 ≤ k ≤ 255
Operation: k → W
Status Af fected: None
Encoding: 0000 1110 kkkk kkkk
Description: T he eight-bit literal ‘k’ is loaded into W.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal ‘k’ Process
Data Write to W
Example: MOVLW 5Ah
After Instruction
W=5Ah
MOVWF M ove W to f
Syntax: MOVWF f {,a}
Operands: 0 ≤ f ≤ 255
a ∈ [0,1 ]
Operation: (W ) → f
Status Af fected: None
Encoding: 0110 111a ffff ffff
Description: Move data from W to register ‘f’.
Location ‘f’ can be anywhere in the
256-byte bank.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, t he BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Index ed
Literal Offset Mode ” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write
register ‘f’
Example: MOVWF REG, 0
Before Instruction
W=4Fh
REG = FFh
After Instruction
W=4Fh
REG = 4Fh
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MULLW Multiply literal with W
Syntax: MULLW k
Operands: 0 ≤ k ≤ 255
Operation: (W ) x k → PR O DH : PR O DL
Status Af fected: None
Encoding: 0000 1101 kkkk kkkk
Description: An unsigned mu ltiplication is carried
out between the contents of W and the
8-bit literal ‘k’. The 16-bit result is
placed in PRODH:PRODL register pair .
PRODH contains the high byte.
W is unchanged.
None of the Status flags are affected.
Note that neither Overflow nor Carry is
possible in this operation. A zero result
is possible but not detected.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal ‘k’ Process
Data Write
registers
PRODH:
PRODL
Example: MULLW 0C4h
Before Instruction
W=E2h
PRODH = ?
PRODL = ?
After Instruction
W=E2h
PRODH = ADh
PRODL = 08h
MULWF Multiply W with f
Syntax: MULWF f {,a}
Operands: 0 ≤ f ≤ 255
a ∈ [0,1]
Operation: (W) x (f) → PRODH:PRODL
Status Af fected: None
Encoding: 0000 001a ffff ffff
Description: An unsigned multiplication is carried
out between the contents of W and the
register file location ‘f’. The 16-bit
result is stored in the PRODH:PRODL
register pair. PRODH contains the
high byte. Both W and ‘f’ are
unchanged.
None of the Status flags are affected.
Note that neither Overflow nor Carry is
possible in this operation. A zero
result is possible but not detected.
If ‘a’ is ‘0’, the Access Ban k is
selected. If ‘a’ is ‘1’, the BSR is used
to select the GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction
operates in Indexed Literal Offset
Addressing mode whenever
f ≤ 95 (5Fh). See Section 26.2.3
“Byte-Oriented and Bit-Oriented
Instructions in Indexed Literal Offset
Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write
registers
PRODH:
PRODL
Example: MULWF REG, 1
Before Instruction
W=C4h
REG = B5h
PRODH = ?
PRODL = ?
After Instruction
W=C4h
REG = B5h
PRODH = 8Ah
PRODL = 94h
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NEGF Negate f
Syntax: NEGF f {,a}
Operands: 0 ≤ f ≤ 255
a ∈ [0,1]
Operation: ( f ) + 1 → f
Stat us Af f ected: N, OV, C, DC, Z
Encoding: 0110 110a ffff ffff
Description: Location ‘f’ is negated using two’ s
complement. The result is placed in the
data memory location ‘f’.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26. 2.3 “Byte-O riented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ P rocess
Data Write
register ‘f’
Example: NEGF REG, 1
Before Instruction
REG = 0011 1010 [3Ah]
After Instruction
REG = 1100 0110 [C6h]
NOP No Operation
Syntax: NOP
Operands: None
Operation: No operation
Status Af fected: None
Encoding: 0000
1111
0000
xxxx
0000
xxxx
0000
xxxx
Description: No operation.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No
operation No
operation No
operation
Example:
None.
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POP Pop Top of Return Stack
Syntax: POP
Operands: None
Operation: (TOS) → bit bucket
Status Af fected: None
Encoding: 0000 0000 0000 0110
Description: The TOS value is pulled off the return
stack and is discarded. The TOS value
then becomes the previous value that
was pushed onto the return stack.
This instruction is provided to enable
the user to properly manage the return
stack to incorporate a software stack.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No
operation Pop TOS
value No
operation
Example: POP
GOTO NEW
Before Instruction
TOS = 0031A2h
Stack (1 level down) = 014332h
After Instruction
TOS = 014332h
PC = NEW
PUSH Push Top of Return Stack
Syntax: PUSH
Operands: None
Operation: (PC + 2) → TOS
Status Af fected: None
Encoding: 0000 0000 0000 0101
Description: The PC + 2 is pushed onto the top of
the return stack. The previous TOS
value is pushed down on the stack.
This instruction allows implementing a
software stack by modifying TOS and
then pushing it onto the return stack.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Push PC + 2
onto return
stack
No
operation No
operation
Example: PUSH
Before Instruction
TOS = 345Ah
PC = 0124h
After Instruction
PC = 0126h
TOS = 0126h
Stack (1 level down) = 345Ah
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RCALL Relative Call
Syntax: RCALL n
Operands: -1024 ≤ n ≤ 1023
Operation: (PC) + 2 → TOS,
(PC) + 2 + 2n → PC
Status Af fected: None
Encoding: 1101 1nnn nnnn nnnn
Description: Subroutine call with a jump up to 1K
from the current location. First, return
address (PC + 2) is pushed onto the
stack. Then, add the 2’s complement
number ‘2n’ to the PC. S ince the PC will
have incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is a
two-cycle instruct ion.
Words: 1
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read literal
‘n’
Push PC to
stack
Process
Data Write to PC
No
operation No
operation No
operation No
operation
Example: HERE RCALL Jump
Before Instruction
PC = Address (HERE)
After Instruction
PC = Address (Jump)
TOS = Address (HERE + 2)
RESET Reset
Syntax: RESET
Operands: None
Operation: Reset all registers and flags that are
affected by a MCLR Reset.
Status Af f ected: All
Encoding: 0000 0000 1111 1111
Description: This instruction provides a way to
execute a MCLR Reset in software.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Start
Reset No
operation No
operation
Example: RESET
After Instruction
Registers = Reset V alue
Flags* = Reset Value
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RETFIE Return from Interrupt
Syntax: RETFIE {s}
Operands: s ∈ [0,1]
Operation: (TOS) → PC,
1 → GIE/GI EH o r PEIE/GIEL,
if s = 1
(WS) → W,
(STATUSS) → St atus,
(BSRS) → BSR,
PCLATU, PCLATH are unchanged.
Status Affected: GIE/GIEH, PEIE/GIEL.
Encoding: 0000 0000 0001 000s
Description: Return from interrupt. Stack is popped
and Top-of-Stack (TOS) is loaded into
the PC. Interrupts are enabled by
setting either the high or low priority
global interrupt enable bit. If ‘s’ = 1, the
contents of the shadow registers WS,
STATUS S and BSRS are loaded into
their corresponding registers, W,
Status and BSR. If ‘s’ = 0, no update of
these registers occurs (default).
Words: 1
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No
operation No
operation Pop PC from
stack
Set GIEH or
GIEL
No
operation No
operation No
operation No
operation
Example: RETFIE 1
After Interrupt
PC = TOS
W=WS
BSR = BSRS
Status = STATUSS
GIE/ GIEH, PEI E/GIEL = 1
RETLW Return literal to W
Syntax: RETLW k
Operands: 0 ≤ k ≤ 255
Operation: k → W,
(TOS) → PC,
PCLATU, PCLATH are unchanged
Status Af fected: None
Encoding: 0000 1100 kkkk kkkk
Description: W is loaded with the eight-bit literal ‘k’.
The program counter is loaded from the
top of the stack (the return address).
The high address latch (PCLATH)
remains unchanged.
Words: 1
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal ‘k’ Process
Data Pop PC from
stack, Write
to W
No
operation No
operation No
operation No
operation
Example:
CALL TABLE ; W contains table
; offset value
; W now has
; table value
:
TABLE
ADDWF PCL ; W = offset
RETLW k0 ; Begin table
RETLW k1 ;
:
:
RETLW kn ; End of table
Before Instruction
W = 07h
After Instruction
W = value of kn
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RETURN Return from Subroutine
Syntax: RETURN {s}
Operands: s ∈ [0,1]
Operation: (TOS) → PC ,
if s = 1
(WS) → W,
(STATUSS) → Stat us,
(BSRS) → BSR ,
PCLATU, PCLATH are unchanged
Status Af fected: None
Encoding: 0000 0000 0001 001s
Description: Return from subroutine. The stack is
popped and the top of the stack (TOS)
is loaded into the program counter. If
‘s’= 1, the contents of the shadow
registers WS, STA TUSS and BSRS are
loaded into their corresponding
registers, W, Status and BSR. If
‘s’ = 0, no update of these registers
occurs (default).
Words: 1
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No
operation Process
Data Pop PC from
stack
No
operation No
operation No
operation No
operation
Example: RETURN
After Instruction:
PC = TOS
RLCF Rotate Left f through Carry
Syntax: RLCF f {,d {,a}}
Operands: 0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation: (f<n>) → dest<n + 1>,
(f<7>) → C,
(C) → dest<0>
Stat us Af f ected: C, N, Z
Encoding: 0011 01da ffff ffff
Description: The contents of register ‘f’ are rotated
one bit to the left through the Carry
flag. If ‘d’ is ‘0’, the result is placed in
W. If ‘d’ is ‘1’, the result is stored back
in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is
selected. If ‘a’ is ‘1’, the BSR is used to
select the GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction
operates in Indexed Literal Offset
Addressing mode whenever
f ≤ 95 (5F h). See Section 26.2.3
“Byte-Oriented and Bit-Oriented
Instructions in Indexed Literal Offset
Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write to
destination
Example: RLCF REG, 0, 0
Before Instruction
REG = 1110 0110
C=0
After Instruction
REG = 1110 0110
W=1100 1100
C=1
Cregister f
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RLNCF Rotate Left f (no carry)
Syntax: RLNCF f {,d {,a}}
Operands: 0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation: (f<n>) → dest<n + 1>,
(f<7>) → dest<0>
Status Af fected: N, Z
Encoding: 0100 01da ffff ffff
Description: The contents of register ‘f’ are rotated
one bit to the left. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, th e re sult is
stored back in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructi ons in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Proc ess
Data Write to
destination
Example: RLNCF REG, 1, 0
Before Instruction
REG = 1010 1011
After Instruction
REG = 0101 0111
register f
RRCF Rot ate Right f through Carry
Syntax: RRCF f {,d {,a}}
Operands: 0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation: (f<n>) → dest<n – 1>,
(f<0>) → C,
(C) → dest<7>
Status Affected: C, N, Z
Encoding: 0011 00da ffff ffff
Description: The contents of register ‘f’ are rotated
one bit to the right through the Carry
flag. If ‘d’ is ‘0’, the result is placed in W.
If ‘d’ is ‘1’, the result is placed back in
register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select t he
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write to
destination
Example: RRCF REG, 0, 0
Before Instruction
REG = 1110 0110
C=0
After Instruction
REG = 1110 0110
W=0111 0011
C=0
Cregister f
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RRNCF Rotate Right f (no carry)
Syntax: RRNCF f {,d {,a}}
Operands: 0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation: (f<n>) → dest<n – 1>,
(f<0>) → dest<7>
Status Af fected: N, Z
Encoding: 0100 00da ffff ffff
Description: The contents of register ‘f’ are rotated
one bit to the right. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank will be
selected, overriding the BSR value. If ‘a’
is ‘1’, then the bank will be selected as
per the BSR value (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in In d e x e d L it e r a l Offset Add r e ssin g
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write to
destination
Example 1: RRNCF REG, 1, 0
Before Instruction
REG = 1101 0111
After Instruction
REG = 1110 1011
Example 2: RRNCF REG, 0, 0
Before Instruction
W=?
REG = 1101 0111
After Instruction
W=1110 1011
REG = 1101 0111
register f
SETF Set f
Syntax: SETF f {,a}
Operands: 0 ≤ f ≤ 255
a ∈ [0,1]
Operation: FFh → f
Status Af fected: None
Encoding: 0110 100a ffff ffff
Description: The contents of the specified register
are set to FFh.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select t he
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write
register ‘f’
Example: SETF REG,1
Before Instruction
REG = 5Ah
After Instruction
REG = FFh
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SLEEP Enter Sleep mode
Syntax: SLEEP
Operands: None
Operation: 00h → WDT,
0 → WDT postscaler,
1 → TO ,
0 → PD
Status Af fected: TO, PD
Encoding: 0000 0000 0000 0011
Description: The Power-Down status bit (PD) is
cleared. The Time-out status bit (TO)
is set. Watchdog T imer and its
postscaler are cleared.
The processor is put into Sleep mode
with the oscillator stopped.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No
operation Process
Data Go to
Sleep
Example: SLEEP
Before Instruction
TO =?
PD =?
After Instruction
TO =1 †
PD =0
† If WDT causes wake-up, this bit is cleared.
SUBFWB Subtract f from W with borrow
Syntax: SUBFWB f {,d {,a}}
Operands: 0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation: (W) – (f) – (C) → dest
Stat us Af f ected: N, OV, C, DC, Z
Encoding: 0101 01da ffff ffff
Description: Subtract register ‘f’ and Carry flag
(borrow) from W (2’s complement
method). If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored in
register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is
selected. If ‘a’ is ‘1’, the BSR is used
to select the GPR bank (default).
If ‘a’ is ‘0’ and t he extended instruction
set is enabled, this instruction
operates in Indexed Literal Offset
Addressing mode whenever
f ≤ 95 (5Fh). See Section 26.2.3
“Byte-Oriented and Bit-Oriented
Instructions in Indexed Literal Offset
Mode” f or details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write to
destination
Example 1: SUBFWB REG, 1, 0
Before Instruction
REG = 3
W=2
C=1
After Instruction
REG = FF
W=2
C=0
Z=0
N = 1 ; result is negative
Example 2: SUBFWB REG, 0, 0
Before Instruction
REG = 2
W=5
C=1
After Instruction
REG = 2
W=3
C=1
Z=0
N = 0 ; result is positive
Example 3: SUBFWB REG, 1, 0
Before Instruction
REG = 1
W=2
C=0
After Instruction
REG = 0
W=2
C=1
Z = 1 ; resul t is zero
N=0
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SUBLW Subtract W from literal
Syntax: SUBLW k
Operands: 0 ≤ k ≤ 255
Operation: k – (W) → W
Stat us Af f ected: N, OV, C, DC, Z
Encoding: 0000 1000 kkkk kkkk
Description W is subtracted from the eight-bit
literal ‘k’. The result is placed in W.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal ‘k’ Process
Data Wri te to W
Example 1: SUBLW 02h
Before Instruction
W = 01h
C=?
After Instruction
W = 01h
C = 1 ; result is positive
Z=0
N=0
Example 2: SUBLW 02h
Before Instruction
W = 02h
C=?
After Instruction
W = 00h
C = 1 ; result is zero
Z=1
N=0
Example 3: SUBLW 02h
Before Instruction
W = 03h
C=?
After Instruction
W = FFh ; (2’ s complement)
C = 0 ; result is negative
Z=0
N=1
SUBWF Subtract W from f
Syntax: SUB W F f {,d {,a}}
Operands: 0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation: (f) – (W) → dest
Stat us Af f ected: N, OV, C, DC, Z
Encoding: 0101 11da ffff ffff
Description: Subtract W f rom register ‘f ’ (2’s
complement method). If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’
(default).
If ‘a’ is ‘0’, the Access Bank is
selected. If ‘a’ is ‘1’, the BSR is used
to select the GPR bank (default).
If ‘a’ is ‘0’ and t he extended instruction
set is enabled, this instruction
operates in Indexed Literal Offset
Addressing mode whenever
f ≤ 95 (5Fh). See Section 26.2.3
“Byte-Oriented and Bit-Oriented
Instructions in Indexed Literal Offset
Mode” f or details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write to
destination
Example 1: SUBWF REG, 1, 0
Before Instruction
REG = 3
W=2
C=?
After Instruction
REG = 1
W=2
C = 1 ; result is positive
Z=0
N=0
Example 2: SUBWF REG, 0, 0
Before Instruction
REG = 2
W=2
C=?
After Instruction
REG = 2
W=0
C = 1 ; result is ze r o
Z=1
N=0
Example 3: SUBWF REG, 1, 0
Before Instruction
REG = 1
W=2
C=?
After Instruction
REG = FFh ;(2’s complement)
W=2
C = 0 ; result is negative
Z=0
N=1
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SUBWFB Subtract W from f with Borrow
Syntax: SUBWFB f {,d {,a}}
Operands: 0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation: (f) – (W) – (C) → dest
Stat us Af fected: N, OV, C, DC, Z
Encoding: 0101 10da ffff ffff
Description: Subtract W and the Carry flag (borrow)
from register ‘f’ (2’s complement
method). If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored back
in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Proc ess
Data Write to
destination
Example 1: SUBWFB REG, 1, 0
Before Instruction
REG = 19h (0001 1001)
W=0Dh(0000 1101)
C=1
After Instruction
REG = 0Ch (0000 1011)
W=0Dh(0000 1101)
C=1
Z=0
N = 0 ; result is positive
Example 2: SUBWFB REG, 0, 0
Before Instruction
REG = 1Bh (0001 1011)
W=1Ah(0001 1010)
C=0
After Instruction
REG = 1Bh (0001 1011)
W = 00h
C=1
Z = 1 ; res u l t is zero
N=0
Example 3: SUBWFB REG, 1, 0
Before Instruction
REG = 03h (0000 0011)
W=0Eh(0000 1101)
C=1
After Instruction
REG = F5h (1111 0100)
; [2’s co mp]
W=0Eh(0000 1101)
C=0
Z=0
N = 1 ; result is negative
SWAPF Swap f
Syntax: SWAPF f {,d {,a}}
Operands: 0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation: (f<3:0>) → dest<7:4>,
(f<7:4>) → dest<3:0>
Status Af fected: None
Encoding: 0011 10da ffff ffff
Description: The upper and lower nibbles of register
‘f’ are exchanged. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result is
placed in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select t he
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write to
destination
Example: SWAPF REG, 1, 0
Before Instruction
REG = 53h
After Instruction
REG = 35h
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TBLRD Table Read
Syntax: TBLRD ( *; *+; *-; +*)
Operands: None
Operation: if TBLRD *,
(Prog Mem (TBLPTR)) → TABLAT;
TBLPTR – No Change;
if TBLRD *+,
(Prog Mem (TBLPTR)) → TABLAT;
(TBLPTR) + 1 → TBLPTR;
if TBLRD *-,
(Prog Mem (TBLPTR)) → TABLAT;
(TBLPTR) – 1 → TBLPTR;
if TBLRD +*,
(TBLPTR) + 1 → TBLPTR;
(Prog Mem (TBLPTR)) → TABLAT;
Status Af fected: None
Encoding: 0000 0000 0000 10nn
nn=0 *
=1 *+
=2 *-
=3 +*
Description: This instruction is used to read the contents
of Program Memory (P.M.). To address the
program memory, a pointer called Table
Pointer (TBLPTR) is used.
The TBLPTR (a 21-bit pointer) points to
each byte in the program memory. TBLPTR
has a 2-Mbyte address range.
TBLP TR[ 0] = 0: Least Significant Byte
of Program Memory
Word
TBLP TR[ 0] = 1: Most Significant Byte
of Program Memory
Word
The TBLRD instruction can modify the value
of TBLPTR as follows:
• no change
• post-increment
• post-decrement
• pre-increment
Words: 1
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No
operation No
operation No
operation
No
operation No oper atio n
(Read Program
Memory)
No
operation No operation
(Write
TABLAT)
TBLRD Table Read (Continued)
Example 1: TBLRD *+ ;
Before Instruction
TABLAT = 55h
TBLPTR = 00A356h
MEMORY (00A356h) = 34h
After Instruction
TABLAT = 34h
TBLPTR = 00A357h
Example 2: TBLRD +* ;
Before Instruction
TABLAT = AAh
TBLPTR = 01A357h
MEMORY (01A357h) = 12h
MEMORY (01A358h) = 34h
After Instruction
TABLAT = 34h
TBLPTR = 01A358h
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TBLWT Table Write
Syntax: TB LWT ( *; *+; *-; +*)
Operands: None
Operation: if TBLWT*,
(TABLAT) → Holding Register;
TBLPTR – No Change;
if TBLWT*+,
(TABLAT) → Holding Register;
(TBLPTR) + 1 → TBL PT R ;
if TBLWT*-,
(TABLAT) → Holding Register;
(TBLPTR) – 1 → TBLPTR;
if TBLWT+*,
(TBLPTR) + 1 → TBL PT R ;
(TABLAT) → Holding Register;
Status Af fected: None
Encoding: 0000 0000 0000 11nn
nn=0 *
=1 *+
=2 *-
=3 +*
Description: This instr uction uses the 3 LSBs of
TBLPTR to determine which of the
8 holding registers the TABLAT is written
to. The holding registers are used to
program the contents of Program
Memory (P.M.). (Refer to Section 6.0
“Flash Program Memory” for additional
details on programming Flash memory.)
The TBLPTR (a 21-bit pointer) points to
each byte in the program memory.
TBLPTR has a 2-Mbyte address range.
The LSb of the TBLPTR selects which
byte of the program memory location to
access.
TBLPTR[0] = 0: Least Significant
Byte of Program
Memory Word
TBLPTR[0] = 1: Most Significant
Byte of Program
Memory Word
The TBLWT instruction can modify the
value of TBLPTR as follows:
• no change
• post-increment
• post-decrement
• pre-increment
Words: 1
Cycles: 2
Q Cycle Activity: Q1 Q2 Q3 Q4
Decode No
operation No
operation No
operation
No
operation No
operation
(Read
TABLAT)
No
operation No
operation
(Write to
Holding
Register )
TBLWT Table Write (Continued)
Example 1: TBLWT *+;
Before Instruction
TABLAT = 55h
TBLPTR = 00A356h
HOLD ING REGIST ER
(00A356h) = FFh
After Instructions (table write completion)
TABLAT = 55h
TBLPTR = 00A357h
HOLD ING REGIST ER
(00A356h) = 55h
Example 2: TBLWT +*;
Before Instruction
TABLAT = 34h
TBLPTR = 01389Ah
HOLD ING REGIST ER
(01389Ah) = FFh
HOLD ING REGIST ER
(01389Bh) = FFh
After Instruction (table write completion)
TABLAT = 34h
TBLPTR = 01389Bh
HOLD ING REGIST ER
(01389Ah) = FFh
HOLD ING REGIST ER
(01389Bh) = 34h
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TSTFSZ Test f, skip if 0
Syntax: TSTFSZ f {,a}
Operands: 0 ≤ f ≤ 255
a ∈ [0,1]
Operation: skip if f = 0
Status Af fected: None
Encoding: 0110 011a ffff ffff
Description: If ‘f’ = 0, the next instruction fetched
during the current instruction execution
is discarded and a NOP is executed,
making this a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in In d e x e d L it e r a l Offset Add r e ssin g
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data No
operation
If skip: Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
No
operation No
operation No
operation No
operation
Example: HERE TSTFSZ CNT, 1
NZERO :
ZERO :
Before Instruction
PC = Address (HERE)
After Instruction
If CNT = 00h,
PC = Address (ZERO)
If CNT ≠00h,
PC = Address (NZERO)
XORLW Exclusive OR literal with W
Syntax: XORLW k
Operands: 0 ≤ k ≤ 255
Operation: (W) .XO R. k → W
Status Af fected: N, Z
Encoding: 0000 1010 kkkk kkkk
Description: The contents of W are XORed with
the 8-bit literal ‘k’. The result is placed
in W.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal ‘k’ Process
Data Write to W
Example: XORLW 0AFh
Before Instruction
W=B5h
After Instruction
W=1Ah
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XORWF Exclusive OR W with f
Syntax: XORWF f {,d {,a}}
Operands: 0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation: (W) .XOR. (f) → dest
Status Af fected: N, Z
Encoding: 0001 10da ffff ffff
Description: Exc lusive OR the contents of W with
register ‘f’. If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored back
in the register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select t he
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in In d e x e d L it e r a l Offset Add r e ssin g
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Proc ess
Data Write to
destination
Example: XORWF REG, 1, 0
Before Instruction
REG = AFh
W=B5h
After Instruction
REG = 1Ah
W=B5h
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26.2 Extended Instruction Set
In additi on to t he s t an dard 75 i nst ruc tions of the PI C18
instruction set, PIC18F2455/2550/4455/4550 devices
also provide an optional extension to the core CPU
functionality. The added features include eight addi-
tional instructions that augment indirect and indexed
addressing operations and the implementation of
Indexed Literal Of fset Addressing mode for many of the
standard PIC18 instructions.
The additional features of the extended instruction set
are d isabled by defa ult. To en able them, u sers must set
the XINST configuration bit.
The instructions in the extended set can all be
class ified as literal operation s, which eith er manip ulate
the File Select Registers, or use them for indexed
addressing. Two of the instructions, ADDFSR and
SUBFSR, each have an additional special instantiation
for using FSR2. These versions (ADDULNK and
SUBULNK) allow for automatic return after execution.
The exte nded instr uctions are s pecifically im plemented
to optimize re-entrant program code (that is, code that
is recursive or that uses a software stack) written in
high-level languages, particularly C. Among other
things, they allow users working in high-level
languages to perform certain operations on data
structures more efficiently. These include:
• dynamic allocation and deallocation of software
stack space when entering and leaving
subroutines
• function pointer invocation
• software stack pointer manipulation
• manipulation of variables located in a software
stack
A summary of the instructions in the extended instruc-
tion set is provide d in Ta ble 26-3. Det aile d descr ipti ons
are pro vided in Section 26.2.2 “Extended Instruction
Set”. The opcode field descriptions in Table 26-1
(page 302) apply to both the standard and extended
PIC18 instruction sets.
26.2.1 EXTENDED INSTRUCTION SYNTAX
Most of the extended instructions use indexed argu-
ment s, using one of the File Sele ct Register s and some
of fset to spe ci fy a sou rce or destination register. When
an argument for an instruction serves as part of
indexed addressing, it is enclosed in square brackets
(“[ ]”). This is done to in dicate that the argument is used
as an index or of f set . MPASM™ Assembl er w ill flag an
error if it de termines that an inde x or offset va lu e is not
bracketed.
When the ex tended ins truction s et is enabled, bra cket s
are also used to indicate index arguments in byte-
oriented and bit-oriented instruction s. This is in addition
to other changes in their syntax. For more details, see
Section 26.2.3.1 “Extended Instruction Syntax with
Standard PIC18 Commands”.
TABLE 26-3: EXTENSIONS TO THE PIC18 INSTRUCTION SET
Note: The instruction set extension and the
Indexed Literal Offset Addressing mode
were designed for optimizing applications
written in C; the user may likely never use
these instructions directly in assembler.
The syntax for these commands is pro-
vided as a reference for u sers who may b e
reviewing code that has been generated
by a compiler.
Note: In the past, square brackets have been
used to denote optional arguments in the
PIC18 and earlier instruction sets. In this
text and going forward, optional
arguments are denoted by braces (“{ }”).
Mnemonic,
Operands Description Cycles 16-Bit Instruction Word Status
Affected
MSb LSb
ADDFSR
ADDULNK
CALLW
MOVSF
MOVSS
PUSHL
SUBFSR
SUBULNK
f, k
k
zs, fd
zs, zd
k
f, k
k
Add literal to FSR
Add literal to FSR2 and return
Call subroutine using WREG
Move zs (source) to 1st word
fd (destination) 2nd word
Move zs (source) to 1st word
zd (destination) 2nd word
Store lite ral at FSR2,
decrement FSR2
Subtract literal from FSR
Subtract literal from FSR2 and
return
1
2
2
2
2
1
1
2
1110
1110
0000
1110
1111
1110
1111
1110
1110
1110
1000
1000
0000
1011
ffff
1011
xxxx
1010
1001
1001
ffkk
11kk
0001
0zzz
ffff
1zzz
xzzz
kkkk
ffkk
11kk
kkkk
kkkk
0100
zzzz
ffff
zzzz
zzzz
kkkk
kkkk
kkkk
None
None
None
None
None
None
None
None
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26.2.2 EXTENDED INSTRUCTION SET
ADDFSR Add Literal to FSR
Syntax: ADDF SR f, k
Operands: 0 ≤ k ≤ 63
f ∈ [ 0, 1, 2 ]
Operation: FSR(f) + k → FSR(f)
Status Af fected: None
Encoding: 1110 1000 ffkk kkkk
Description: T he 6-bit literal ‘k’ is added to the
contents of the FSR specified by ‘f’.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal ‘k’ Process
Data Write to
FSR
Example: ADDFSR 2, 23h
Before Instruction
FSR2 = 03FFh
After Instruction
FSR2 = 0422h
ADDULNK Add L i t era l to FSR2 a n d Ret u r n
Syntax: ADDULNK k
Operands: 0 ≤ k ≤ 63
Operation: FSR2 + k → FSR2,
(TOS) → PC
Status Af fected: None
Encoding: 1110 1000 11kk kkkk
Description: The 6-bit literal ‘k’ is added to the
contents of FSR2. A RETURN is then
executed by loading the PC with the
TOS.
The instruction takes two cycles to
execute; a NOP is performed during
the second cycle.
This may be thought of as a special
case of the ADDFSR instruction,
where f = 3 (binary ‘11’); it operates
only on FSR2.
Words: 1
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal ‘k’ Process
Data Wri te to
FSR
No
Operation No
Operation No
Operation No
Operation
Example: ADDULNK 23h
Before Instruction
FSR2 = 03FFh
PC = 0100h
After Instruction
FSR2 = 0422h
PC = (TOS)
Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in
symbolic addressing. If a label is used, the instruction syntax then becomes: {label} instruction argument(s).
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CALLW Subroutine Call Using WREG
Syntax: CALLW
Operands: None
Operation: (PC + 2) → TOS,
(W) → PCL,
(PCLATH) → PCH,
(PCLATU) → PC U
Status Af fected: None
Encoding: 0000 0000 0001 0100
Description First, the return address (PC + 2) is
pushed onto the return stack. Next, the
contents of W are written to PCL; the
existing value is discarded. Then the
contents of PCLATH and PCLATU are
latched into PCH and PCU,
respectively. The second cycle is
executed as a NOP instruction while the
new next instruction is fetched.
Unlike CALL, there is no option to
update W, Status or BSR.
Words: 1
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
WREG Push PC to
stack No
operation
No
operation No
operation No
operation No
operation
Example: HERE CALLW
Before Instruction
PC = address (HERE)
PCLATH = 10h
PCLATU = 00h
W = 06h
After Instruction
PC = 001006h
TOS = address (HERE + 2)
PCLATH = 10h
PCLATU = 00h
W = 06h
MOVSF Move Indexed to f
Syntax: MOVSF [zs], fd
Operands: 0 ≤ zs ≤ 127
0 ≤ fd ≤ 4095
Operation: ((FSR2) + zs) → fd
Status Af fected: None
Encoding:
1st word (source)
2nd word (destin.) 1110
1111
1011
ffff
0zzz
ffff
zzzzs
ffffd
Description: The contents of the source register are
moved to destination register ‘fd’. The
actual address of the source register is
determined by adding the 7-bit literal
offset ‘zs’ in the first word to the value of
FSR2. The address of the destination
register is specified by the 12-bit literal
‘fd’ in the second word. Both addresses
can be anywhere in the 4096-byte data
space (000h to FFFh).
The MOVSF instruction cannot use the
PCL, TOSU, TOSH or TOSL as the
destination register.
If the resultant source address points to
an indirect addressing register, the
value returned will be 00h.
Words: 2
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Determine
source addr Determine
source addr Read
source reg
Decode No
operation
No dummy
read
No
operation Write
register ‘f’
(dest)
Example: MOVSF [05h], REG2
Before Instruction
FSR2 = 80h
Contents
of 85h = 33h
REG2 = 11h
After Instruction
FSR2 = 80h
Contents
of 85h = 33h
REG2 = 33h
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MOVSS Move Indexed to Indexed
Syntax: MOVSS [zs], [zd]
Operands: 0 ≤ zs ≤ 127
0 ≤ zd ≤ 127
Operation: ((FSR2) + zs) → ((F SR2) + zd)
Status Af fected: None
Encoding:
1st word (source)
2nd word (dest.) 1110
1111
1011
xxxx
1zzz
xzzz
zzzzs
zzzzd
Description The contents of the source register are
moved to the destination register . The
addresses of the source and destination
registers are determined by adding the
7-bit literal offset s ‘zs’ or ‘zd’,
respectively, to the value of FSR2. Both
registers can be located anywhere in
the 4096-byte data memory space
(000h to FFFh).
The MOVSS instruction cannot use the
PCL, TOSU, TOSH or TOSL as the
destination register.
If the resultant source address points to
an indirect addressing register, the
value returned will be 00h. If the
resultant destination address points to
an indirect addressing register, the
instruction will execute as a NOP.
Words: 2
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Determine
source addr Determine
source addr Read
source reg
Decode Determine
dest addr Determine
dest addr Write
to dest reg
Example: MOVSS [05h], [06h]
Before Instruction
FSR2 = 80h
Contents
of 85h = 33h
Contents
of 86h = 11h
After Instruction
FSR2 = 80h
Contents
of 85h = 33h
Contents
of 86h = 33h
PUSHL
Store Literal at FSR2, Decrement FSR2
Syntax: PUSHL k
Operands: 0 ≤ k ≤ 255
Operation: k → (FS R2),
FSR2 – 1→ FSR2
S t at us Af fect ed: None
Encoding: 1111 1010 kkkk kkkk
Description: The 8-bit literal ‘k’ is written to the data
memory address specified by FSR2. FSR2
is decremented by ‘1’ after the operation.
This instruction allows users to push values
onto a software stack.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read ‘k’ Process
data Write to
destination
Example: PUSHL 08h
Before Instruction
FSR2H:FSR2L = 01ECh
Memory (01ECh) = 00h
After Instruction
FSR2H:FSR2L = 01EBh
Memory (01ECh) = 08h
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SUBFSR Subtract Literal from FSR
Syntax: SUBFSR f, k
Operands: 0 ≤ k ≤ 63
f ∈ [ 0, 1, 2 ]
Operation: FSRf – k → FSRf
Status Af fected: None
Encoding: 1110 1001 ffkk kkkk
Description: The 6-bit literal ‘k’ is subtracted from
the contents of the FSR specified by
‘f’.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write to
destination
Example: SUBFSR 2, 23h
Before Instruction
FSR2 = 03FFh
After Instruction
FSR2 = 03DCh
SUBULNK
Subtract Literal from FSR2 and Return
Syntax: SUBULNK k
Operands: 0 ≤ k ≤ 63
Operation: FSR2 – k → FSR2
(TOS) → PC
S t at us Af fect ed: None
Encoding: 1110 1001 11kk kkkk
Description: The 6-bit literal ‘k’ is subtracted from the
contents of the FSR2. A RETURN is then
executed by loading the PC with the TOS.
The instruction takes two cycles to
execute; a NOP is performed during the
second cycle.
This may be thought of as a special case of
the SUBFSR instruction, where f = 3 (binary
‘11’); it operates only on FSR2.
Words: 1
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write to
destination
No
Operation No
Operation No
Operation No
Operation
Example: SUBULNK 23h
Before Instruction
FSR2 = 03FFh
PC = 0100h
After Instruction
FSR2 = 03DCh
PC = (TOS)
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DS39632A-page 348 Advance Information 2004 Microchip Technology Inc.
26.2.3 BYTE-ORIE NTED AND
BIT-ORIENTED INSTRUCTIONS IN
INDEXED LITERAL OFFSET MODE
In additio n to eight new comm ands in the extende d set,
enabling the extended instruction set also enables
Indexed Literal Offset Addre ssing mode (Section 5.6.1
“Indexed Addressing with Literal Offset”). This has
a sign ificant im pact on the way t hat many com mands of
the standard PIC18 instruction set are interpreted.
When the ex ten ded se t is di sabled, a dd ress es em be d-
ded in opco des are treated as literal memory locations:
either as a location in the Access Bank (‘a’ = 0) or in a
GPR bank designated by the BSR (‘a’ = 1). When the
extended instruction set is enabled and ‘a’ = 0,
however, a file register argument of 5Fh or less is
interpreted as an of fse t from the point er val ue in FSR2
and not as a literal address. For practical purposes, thi s
means that all i nstructio ns that us e the Acc ess RAM b it
as an argument – that is, all byte-oriented and bit-
oriented instructions, or almost half of the core PIC18
instructions – may behave differently when the
extended instruction set is enabled.
When the content of FSR2 is 00h, the b oundaries of the
Access RAM are essentially remapped to their original
values. This may be useful in creating backward
compatible code. If this technique is used, it may be
necessary to save the value of FSR2 and restore it
when moving back and forth between C and assembly
routines in order to preserve the Stack Pointer. Users
must also keep in mind the syntax requirements of the
extended instruction set (see Section 26.2.3.1
“Extended Instruction Syntax with Standard PIC18
Commands”).
Although the Indexed Literal Offset Addressing mode
can be very useful for dynamic stack and pointer
manipulation, it can also be very annoying if a simple
arithmetic operation is carried out on the wrong
register. Users who are accustomed to the PIC18 pro-
gramming must keep in mind that, when the extended
instruction set is enabled, register addresses of 5Fh or
less are used for Indexed Literal Offset Addressing.
Representative examples of typical byte-oriented and
bit-oriented instructions in the Indexed Literal Offset
Address ing mode are pro vided on the f ollowing p age to
show how execution is affected. The operand
conditions shown in the examples are applicable to all
instructions of these types.
26.2.3.1 Extended Instruction Syntax with
Standard PIC18 Commands
When the extended instruction set is enabled, the file
register arg ument, ‘f’, in the sta ndard byte-orien ted and
bit-or iented command s is replaced with the li teral of fset
value, ‘k ’. As al rea dy no ted , this occ urs only when ‘f’ is
less t han or eq ual to 5Fh. When an of fset val ue is use d,
it must be indicated by square brackets (“[ ]”). As with
the exte nded ins tructions , the us e of brac kets indicate s
to the com pil er th at the val ue is to be in terp rete d as an
index or an offset. Omitting the brackets, or using a
value greater than 5Fh within brackets, will generate an
error in the MPASM Assembler.
If the ind ex argume nt is pr operly brackete d for Indexe d
Literal Offset Addressing mode, the Access RAM
argument is never specified; it will automatically be
assumed to be ‘0’. This is in contrast to standard
operation (extended instruction set disabled) when ‘a’
is set on the basis of the target address. Declaring the
Access RAM bi t in this m ode will also gen erate an error
in the MPASM Assembler.
The destination argument, ‘d’, functions as before.
In the latest versions of the MPASM assembler,
languag e s upp ort for the extended instruc tion set mus t
be explicitly invoked. This is done with either the
command line option, /y, or the PE directive in the
source lis tin g.
26.2. 4 CONSIDERATIONS WHEN
ENABLING THE EXTENDED
INSTRUCTION SET
It is i mport ant to note that the exten sions to th e ins truc-
tion set may not be beneficial to all users. In particular,
users who are not writing code that uses a software
stack may not benefit from using the extensions to the
instruction set.
Additionally, the Indexed Literal Offset Addressing
mode may create issues with legacy applications
written to the PIC18 assembler. This is because
instruc t ion s i n th e le gac y cod e m ay atte mp t to a dd r es s
registers in the Access Bank below 5Fh. Since these
addresses are interpreted as literal offsets to FSR2
when the instruction set extension is enabled, the
application may read or write to the wrong data
addresses.
When porting an application to the PIC18F2455/2550/
4455/4550, it is very important to consider the type of
code. A l arge, re-entrant application that is written in ‘C’
and wou ld bene fit from effi cient compi lation will do well
when using the instruction set extensions. Legacy
applic ations tha t heavily use the Ac cess Ban k will most
likely not benefit from using the extended instruction
set.
Note: Enabling the PIC18 instruction set
extension may cause legacy applications
to behave erratically or fail entirely.
2004 Microchip Technology Inc. Advance Information DS39632A-page 349
PIC18F2455/2550/4455/4550
ADDWF ADD W to Indexed
(Indexed Literal Offset mode)
Syntax: ADDWF [k] {,d}
Operands: 0 ≤ k ≤ 95
d ∈ [0,1]
Operation: (W) + ((FSR2) + k) → dest
Stat us Af f ected: N, OV, C, DC, Z
Encoding: 0010 01d0 kkkk kkkk
Description: The contents of W are added to the
contents of the register indicated by
FSR2, offset by the value ‘k’.
If ‘d’ is ‘0’, the result is stored in W. If ‘d’
is ‘1’, the result is stored back in
register ‘f’ (default).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read ‘k’ Proces s
Data Write to
destination
Example: ADDWF [OFST] ,0
Before Instruction
W = 17h
OFST = 2Ch
FSR2 = 0A00h
Contents
of 0A2Ch = 20h
After Instruction
W = 37h
Contents
of 0A2Ch = 20h
BSF Bit Set Indexed
(Indexed Literal Offset mode)
Syntax : BS F [k], b
Operands: 0 ≤ f ≤ 95
0 ≤ b ≤ 7
Operation: 1 → ((FSR2) + k)<b>
Status Af fected: None
Encoding: 1000 bbb0 kkkk kkkk
Description: Bit ‘b’ of the register indicated by FSR2,
offset by the value ‘k’, is set.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’ Process
Data Write to
destination
Example: BSF [FLAG_OFST], 7
Before Instruction
FLAG_OFST = 0Ah
FSR2 = 0A00h
Contents
of 0A0Ah = 55h
After Instruction
Contents
of 0A0Ah = D5h
SETF Set Indexed
(Indexed Literal Offset mode)
Syntax: SETF [k]
Operands: 0 ≤ k ≤ 95
Operation: FFh → ((FSR2) + k)
Status Af fected: None
Encoding: 0110 1000 kkkk kkkk
Description: The contents of the register indicated by
FSR2, offset by ‘k’, are set to FFh.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read ‘k’ Process
Data Write
register
Example: SETF [OFST]
Before Instruction
OFST = 2Ch
FSR2 = 0A00h
Contents
of 0A2Ch = 00h
After Instruction
Contents
of 0A2Ch = FFh
PIC18F2455/2550/4455/4550
DS39632A-page 350 Advance Information 2004 Microchip Technology Inc.
26.2.5 SPECIAL CONSIDERATIONS WITH
MICROCHIP MPLAB ® IDE TOOLS
The latest versions of Microchip’s software tools have
been de signe d t o full y sup port th e exte nded i nstruc tion
set of the PIC18F2455/2550/4455/4550 family of
devices. This includes the MPLAB C18 C compiler,
MPASM Assembly language and MPLAB Integrated
Development Environment (IDE).
When selecting a target device for software
development, MPLAB IDE will automatically set default
configu ration bit s for that device. Th e default sett ing for
the XINST configuration bit is ‘0’, disabling the
extended instruction set and Indexed Literal Offset
Address ing mod e. For pr oper e xecution of app licat ions
developed to take advantage of the extended
instruction set, XINST must be set during
programming.
To develop software for the extended instruction set,
the user must enable support for the instructions and
the Index ed Addressing mode in the ir languag e tool(s).
Depending on the environment being used, th is may be
done in several ways:
• A menu option, or dialog box within the
environ me nt, th at allows t he u se r to c onfigure th e
language tool and its settings for the project
• A command line option
• A directive in the source code
These options vary between different compilers,
assemblers and development environments. Users are
encouraged to review the documentation accompany-
ing their development systems for the appropriate
information.
2004 Microchip Technology Inc. Advance Information DS39632A-page 351
PIC18F2455/2550/4455/4550
27.0 DEVELOPMENT SUPPORT
The PICmicro® microcontrollers are supported with a
full ran ge of hardware a nd softwa re develo pment to ols:
• Integrated Development Environment
- MPLAB® IDE Software
• Assemblers/Compilers/Linkers
- MPASMTM Assembler
- MPLAB C17 and MPLAB C18 C Compilers
-MPLINK
TM Object Linker/
MPLIBTM Object Librarian
- MPLAB C30 C Compiler
- MPLAB ASM30 Assembler/Linker/Library
• Simulators
- MPLAB SIM Software Simulator
- MPLAB dsPIC30 Software Simulator
•Emulators
- MPLAB ICE 2000 In-Circuit Emulator
- MPLAB ICE 4000 In-Circuit Emulator
• In-Circuit Debugger
- MPLAB ICD 2
• Device Progra mm ers
-PRO MATE
® II Universa l Devi ce Pr o gr a mm er
- PICSTART® Plus Development Programmer
- MPLAB PM3 Device Programmer
• Low-Cost Demonstration Boards
- PICDEMTM 1 Demonstration Board
- PICDEM.netTM De monstration Board
- PICDEM 2 Plus Demonstration Board
- PICDEM 3 Demonstration Board
- PICDEM 4 Demonstration Board
- PICDEM 17 Demonstration Board
- PICDEM 1 8R Demonstration Board
- PICDEM L IN Demo nstration Board
- PICDEM USB Demonstration Board
• Evaluation Kits
-K
EELOQ®
- P ICDEM MSC
-microID
®
-CAN
- PowerSmart®
-Analog
27.1 MPLAB Integrated Development
Environment Software
The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16-bit micro-
controller market. The MPLAB IDE is a Windows®
based application that contains:
• An interface to debugging tools
- simulator
- programmer (sold separately)
- emulator (sold separately)
- in-circuit debugger (sold separately)
• A full-featured editor with color coded context
• A multiple project manager
• Customizable data windows with direct edit of
contents
• High-level source code debugging
• Mouse over variable inspection
• Exten si ve on-l in e help
The MPLAB IDE allows you to:
• Edit your source fil es (either assembly or C)
• One touch assemble (or compile) and download
to PICmicro emulator and simulator tools
(automatically updates all project information)
• Debug us ing :
- source files (as sembly or C)
- mixed assembly and C
- machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve whe n upgrading to tools with increasin g flexibi lity
and power.
27.2 MPASM Assembler
The MPASM assembler is a full-featured, universal
macro assembler for all PICmicro MCUs.
The MPASM assembler generates relocatable object
files for the MPLINK object linker, Intel® standard HEX
files, M AP files to detail memory u sage and symbol re f-
erence, a bsolute LST files that contain source lines and
generated machine code and COFF files for
debugging.
The MPASM assembler features include:
• Integration into MPLAB IDE projects
• User de fined m acros to strea mline asse mbly c ode
• Condit ion al as sem bl y for mult i-p urpo se sourc e
files
• Directives that allow complete control over the
assembly p rocess
PIC18F2455/2550/4455/4550
DS39632A-page 352 Advance Information 2004 Microchip Technology Inc.
27.3 MPLAB C17 and MPLAB C18
C Compilers
The MPLAB C17 and MPLAB C18 Code Development
Systems are complete ANSI C compilers for
Microchip’s PIC17CXXX and PIC18CXXX family of
microcontrollers. These compilers provide powerful
integration capabilities, superior code optimization and
ease of use not found with other compilers.
For easy source level debugging, the compilers provide
symbol info rmation tha t is optimized to the MPLAB IDE
debugger.
27.4 MPLINK Object Linker/
MPLIB Object Librari an
The MPLINK object linker combines relocatable
objects created by the MPASM assembler and the
MPLAB C17 and MPLAB C18 C compilers. It can link
relocatable objects from precompiled libraries, using
directives from a linker script.
The MPLIB object librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file , only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement , deletion and extr action
27.5 MPLAB C30 C Compiler
The MPLAB C30 C compiler is a full-featured, ANSI
compliant, optimizing compiler that translates standard
ANSI C programs into dsPIC30F assembly language
source. The compiler also supports many command
line options and language extensions to take full
adv antage of the dsPIC 30F dev ice ha rdwar e capab ili-
ties and afford fine control of the compiler code
generator.
MPLAB C30 is distributed with a complete ANSI C
standard library. All library functions have been vali-
dated an d c on form to the ANSI C li brary standard . Th e
library includes functions for string manipulation,
dynamic memory allocation, data conversion, time-
keepin g and math func tions (trigonome tric, expone ntial
and hyperbolic). The compiler provides symbolic
information for high-level source debugging with the
MPLAB IDE.
27.6 MPLAB ASM30 Assembler, Linker
and Librarian
MPLAB ASM30 assembler produces relocatable
machine code from symbolic assembly language for
dsPIC30F devices. MPLAB C30 compiler uses the
assembler to produce it’s object file. The assembler
generates relocatable object files that can then be
archived or linked with other relocatabl e object files and
arch ives to c rea te an e xecu tabl e fil e. N otabl e fe atu res
of the assembler include:
• Support for the entire dsPIC30F instruction set
• Support for fixed-point and floating-point data
• Command line interface
• Rich dire cti ve set
• Flexible macro language
• MPLAB IDE compatibility
27.7 MPLAB SIM Software Simulator
The MPLAB SIM sof tware simulat or allows code deve l-
opment in a PC hosted environment by simulating the
PICmicro series microcontrollers on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a file, or use r de fined key p ress, to any pin. The exec u-
tion can be performed in Single-Step, Execute Until
Break or Trace mode.
The MPLAB SIM simulator fully supports symbolic
debugging using the MPLAB C17 and MPLAB C18
C Compilers, as well as the MPASM assembler. The
software simulator offers the flexibility to develop and
debug code outside of the laboratory environment,
making it an excellent, economical software
development tool .
27.8 MPLAB SIM30 Software Simulator
The MPLAB SIM30 software simulator allows code
develop ment in a PC hosted en vironment by simulating
the dsPIC30F series microcontrollers on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a file, or user defined key press, to any of the pins.
The MPLAB SIM30 simulator fully supports symbolic
debugging using the MPLAB C30 C Compiler and
MPLAB ASM30 assembler . The simulator runs in either
a Command Line mode for automated tasks, or from
MPLAB IDE. This high-speed simulator is designed to
debug, analyze and optimize time intensive DSP
routines.
2004 Microchip Technology Inc. Advance Information DS39632A-page 353
PIC18F2455/2550/4455/4550
27.9 MPLAB ICE 2000
High-Performance Universal
In-Circui t Emu lator
The MPLAB ICE 2000 universal in-circuit emulator is
intended to provide the product development engineer
with a complete microcontroller design tool set for
PICmicro microcontrollers. Software control of the
MPLAB ICE 2000 in-circuit emulator is advanced by
the MPLAB Integrated Development Environment,
which all ows ed iting, b uildin g, do wnlo ading and sourc e
debuggi ng from a singl e envi ronm en t.
The MPLAB ICE 2000 is a full-featured emulator sys-
tem with enhanced trace, trigger and data monitoring
featur es. Interchangea ble processo r modules al low the
system to be easi ly reconfi gured for emula tion of d iffer-
ent processors. The universal architecture of the
MPLAB ICE in-circuit emulator allows expansion to
support new PICmicro microcontrollers.
The MPLAB ICE 2000 in-circuit emulator system has
been designed as a real-time emulation system with
advanced features that are typically found on more
expensive development tools. The PC platform and
Microsoft® Windows 32-bit operating system were
chosen to best make these features available in a
simple, unified application.
27.10 MPLAB ICE 4000
High-Performance Universal
In-Circui t Emu lator
The MPLAB ICE 4000 universal in-circuit emulator is
intended to provide the product development engineer
with a co mplete micro controller de sign tool se t for high-
end PICmicro microcontrollers. Software control of the
MPLAB ICE in-circuit emulator is provided by the
MPLAB Integrated Development Environment, which
allows editing, building, downloading and source
debuggi ng from a singl e envi ronm en t.
The MPLAB ICD 4000 is a premium emulator system,
providing the features of MPLAB ICE 2000, but with
increased emulation memory and high-speed perfor-
mance for dsPIC30F and PIC18XXXX devices. Its
advanc ed emulator fe atures inc lude complex t riggering
and timing, up to 2 Mb of emulation memory and the
ability to view variables in real-time.
The MPLAB ICE 4000 in-circuit emulator system has
been designed as a real-time emulation system with
advanced features that are typically found on more
expensive development tools. The PC platform and
Microsoft Windows 32-bit operating system were
chosen to best make these features available in a
simple, unified application.
27.11 MPLAB ICD 2 In-Circuit Debugger
Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a
powerful, low-cost, run-time development tool,
connecting to the host PC via an RS-232 or high-speed
USB interface. This tool is based on the Flash
PICmicro MCUs and can be used to develop for these
and other PICmicro microcontrollers. The MPLAB
ICD 2 utilizes the in-circuit debugging capability built
into the Flash devices. This feature, along with
Microchip’s In-Circuit Serial ProgrammingTM (ICSPTM)
protocol , offe rs cost ef fective i n-circuit Flash debug ging
from the graphical user interface of the MPLAB
Integrated Development Environment. This enables a
designer to develop and debug source code by setting
breakpoints, single-stepping and watching variables,
CPU status and peripheral registers. Running at full
speed enables testing hardware and applications in
real-tim e. MPLAB ICD 2 also serves as a devel opment
programmer for selected PICmicro devices.
27.12 PRO MATE II Universal Device
Programmer
The PRO MATE II is a universal, CE compliant device
programmer with programmable voltage verification at
VDDMIN and VDDMAX for maxi mum reli abili ty. It features
an LCD display for instructions and error messages
and a modular detachable socket assembly to support
various package types. In Stand-Alone mode, the
PRO MATE II device programmer can read, verify and
program PICmicro devices without a PC connection. It
can also set code protection in this mode.
27.13 MPLAB PM3 Device Programmer
The MPLAB PM3 is a universal, CE compliant device
programmer with programmable voltage verification at
VDDMIN and VDDMAX for maxi mum reli abili ty. It features
a large LCD display (128 x 64) for menus and error
messages and a modular detachable socket assembly
to support various package types. The ICSP™ cable
assembly is included as a standard item. In Stand-
Alone mode , the M PLAB PM3 devi ce pr ogra mmer ca n
read, verify and program PICmicro devices without a
PC connection. It can also set code protection in this
mode. MPLAB PM3 connects to the host PC via an
RS-232 or USB cable. MPLAB PM3 has high-speed
communications and optimized algorithms for quick
programming of large memory devices and incorpo-
rates an SD/M MC ca rd for file st orage an d secu re dat a
applications.
PIC18F2455/2550/4455/4550
DS39632A-page 354 Advance Information 2004 Microchip Technology Inc.
27.14 PICSTART Plus Development
Programmer
The PICSTART Plus development programmer is an
easy-to-use, low-cost, prototype programmer. It con-
nects to the PC via a COM (RS-232) port. MPLAB
Inte grated Dev elopmen t En vironme nt so ftware makes
using the programmer simple and efficient. The
PICSTART Plus development programmer supports
most PICmicro devices up to 40 pins. Larger pin count
devices, such as the PIC16C92X and PIC17C76X,
may be supported with an adapter socket. The
PICSTART Plus development programmer is CE
compliant.
27.15 PICDEM 1 PICmicro
Demonstration Board
The PICDEM 1 demo nstrat ion boa rd demo nstrate s the
capabilities of the PIC16C5X (PIC16C54 to
PIC16C58A), PIC16C61, PIC16C62X, PIC16C71,
PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All
necessary hardware and software is included to run
basic demo programs. The sample microcontrollers
provi d ed wi t h the P IC DE M 1 de mo ns t rat i on b oar d c an
be pro gramme d with a PRO MATE I I devi ce prog ram-
mer or a PICSTART Plus development programmer.
The PICDE M 1 demonstrati on board can be conne cted
to the MPLAB ICE in-circuit emulator for testing. A
proto type area extends the ci rcuitry for a dditio nal appli-
cation components. Features include an RS-232
interface, a potentiometer for simulated analog input,
push button switches and eight LEDs.
27.16 PICDEM.net In ternet/Ethernet
Demonstration Board
The PICDEM.net demonstration board is an Internet/
Ethernet demonstration board using the PIC18F452
microcontroller and TCP/IP firmware. The board
supports any 40-pin DIP device that conforms to the
standard pinout used by the PIC16F877 or
PIC18C452. This kit features a user friendly TCP/IP
stack, web server with HTML, a 24L256 Serial
EEPROM for Xmodem download to web pages into
Serial EEPROM, ICSP/MPLAB ICD 2 interface con-
nector, an Ethernet interface, RS-232 interface and a
16 x 2 LCD display. Also included is the book and
CD-ROM “TCP/IP Lean, Web Servers for Embedded
Systems,” by Jeremy Bentham
27.17 PICDEM 2 Plus
Demonstration Board
The PICDEM 2 Plus demonstration board supports
many 18, 28 and 40-pin microcontrollers, including
PIC16F87X and PIC18FXX2 devices. All the neces-
sary ha rdware and s oftware is included to run the dem-
onstration programs. The sample microcontrollers
provided with the PICDEM 2 demonstration board can
be programmed with a PRO MATE II device program-
mer, PICSTART Plus development programmer, or
MPLAB ICD 2 with a Universal Programmer Adapter.
The MPLAB I CD 2 and MPLAB ICE in-circuit emul ators
may also be used with the PICDEM 2 demonstration
board to test firmware. A prototype area extends the
circuitry for additional application components. Some
of the features include an RS-232 interface, a 2 x 16
LCD display , a piezo speaker , an o n-board temperatu re
sensor, four LEDs and sample PIC18F452 and
PIC16F877 Flash microcontrollers.
27.18 PICDEM 3 PIC16C92X
Demonstration Board
The PICDEM 3 demonstration board supports the
PIC16C923 and PIC16C924 in the PLCC package. All
the necessary hardware and software is included to run
the demonstration programs.
27.19 PICDEM 4 8/14/18-Pin
Demonstration Board
The PICDEM 4 can be used to demonstrate the capa-
bilities of the 8, 14 and 18-pin PIC16XXXX and
PIC18XXXX MCUs, including the PIC16F818/819,
PIC16F87/88, PIC16F62XA and the PIC18F1320
family of microcontrollers. PICDEM 4 is intended to
showcase the many features of these low pin count
parts, including LIN and Motor Control using ECCP.
Special provisions are made for low-power operation
with the supercapacitor circuit and jumpers allow on-
board hardware to be disabled to eliminate current
draw in this mode. Incl uded on the demo board are pro-
visions for Crystal, RC or Canned Oscillator modes, a
five volt regulator for use with a nine volt wall adapter
or battery, DB-9 RS-232 interface, ICD connector for
programming via ICSP and development with MPLAB
ICD 2, 2 x 16 liquid crystal display, PCB footprints for
H-Bridge motor driver, LIN transceiver and EEPROM.
Also included are: header for expansion, eight LEDs,
four potentiometers, three push buttons and a proto-
typing are a. Inc lud ed with the kit is a PIC16F627A and
a PIC18F1 320. Tutorial fir mware is included along w ith
the User’s Guide.
2004 Microchip Technology Inc. Advance Information DS39632A-page 355
PIC18F2455/2550/4455/4550
27.20 PICDEM 17 Demonstration Board
The PICDEM 17 demonstration board is an evaluation
board that demonstrates the capabilities of several
Microchip microcontrollers, including PIC17C752,
PIC17C756A, PIC17C762 and PIC17C766. A pro-
gramme d sample i s included. The PR O MA TE I I device
programmer, or the PICSTART Plus development pro-
gramme r , can be used to reprogram the device for user
tailored application development. The PICDEM 17
demonstration board supports program download and
execution from external on-board Flash memory. A
generous proto typ e area is av ailab le for user hardw are
expansion.
27.21 PICDEM 18R PIC18C601/801
Demonstration Board
The PICDEM 18R demonstration board serves to assist
development of the PIC18C601/801 family of Microchip
microcontrollers. It provides hardware implementation
of both 8-bit Multiplexed/Demultiplexed and 16-bit
Memory modes. The board includes 2 Mb external
Flash memory and 128 Kb SRAM memory, as well as
serial EEPROM, allowing access to the wide range of
memory types supported by the PIC18C601/801.
27.22 PICDEM LIN PIC16C43X
Demonstration Board
The pow erfu l LI N hard w are a nd s of tw are kit includes a
series of boards and three PICmicro microcontrollers.
The small footprint PIC16C432 and PIC16C433 are
used as slaves in the LIN communication and feature
on-board LIN transceivers. A PIC16F874 Flash
microcontroller serves as the master. All three micro-
controllers are programmed with firmware to provide
LIN b us communication.
27.23 PICkitTM 1 Flash Starter Kit
A complete “development system in a box”, the PICkit
Flash Starter Kit includes a convenient multi-section
board for p rogramming, evaluation a nd development of
8/14-pin Flash PIC® microcontrollers. Powered via
USB, the board operates under a simple Windows GUI.
The PICkit 1 Starter Kit includes the User ’s Guide (on
CD ROM), PICkit 1 tutorial software and code for
various applications. Also included are MPLAB® IDE
(Integrated Development Environment) software,
software and hardware “Tips 'n Tricks for 8-pin Flash
PIC® Microcontrollers” Handbook and a USB interface
cable. Supports all current 8/14-pin Flash PIC
microcontrollers, as well as many future planned
devices.
27.24 PICDEM USB PIC16C7X5
Demonstration Board
The PICDEM U SB Demo ns trati on Board sho w s o f f th e
capabilities of the PIC16C745 and PIC16C765 USB
microcontrollers. This board provides the basis for
future USB products.
27.25 Evaluation and
Programming Tools
In additio n to the PICDEM seri es of circuits, Microchip
has a line of evaluation kits and demonstration software
for the se products.
•K
EELOQ evaluation and prog ram mi ng too ls for
Microchip’s HCS Secure Data Products
• CAN developers kit for automotive network
applications
• Analog design boards and filter design software
• PowerS m art battery c harging evaluation/
calibration kits
•IrDA
® development kit
• microID development and rfLabTM development
software
• SEEVAL® designer kit f or mem ory ev al uat ion an d
endurance calculations
• PICDEM MSC demo boards for Switching mode
power supply, high-power IR driver, delta sigma
ADC and flow rate sensor
Check the Microchip web page and the latest Product
Selector Guide for the complete list of demonstration
and evaluation kits.
PIC18F2455/2550/4455/4550
DS39632A-page 356 Advance Information 2004 Microchip Technology Inc.
NOTES:
2004 Microchip Technology Inc. Advance Information DS39632A-page 357
PIC18F2455/2550/4455/4550
28.0 ELECTRIC AL CHARACTERISTICS
Absolute Maximum Ratings(†)
Ambient temperature under bias.............................................................................................................-40°C to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on any pin with respect to VSS (except VDD, MCLR and RA4)..........................................-0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V
Voltage on MC LR with respect to VSS (Note 2)......................................................................................... 0V to +13.25V
Total power dissipation (Note 1) ...............................................................................................................................1.0W
Maximum curr ent out of VSS pin ...........................................................................................................................300 mA
Maximum curr ent into VDD pin..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................... ±20 mA
Output clamp cur rent, IOK (VO < 0 or VO > VDD).............................................................................................................. ±20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin....................................................................................................25 mA
Maximum curr ent sunk by all ports .......................................................................................................................200mA
Maximum current sourced by all ports..................................................................................................................200 mA
Note 1: Power diss ipation is ca lcu la t ed as follows :
Pdis = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOL x IOL)
2: Voltage spikes below VSS at the MCLR/VPP/RE3 pin, inducing currents greater than 80 mA, may cause
latch-up. Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR/VPP/
RE3 pin, rather than pulling this pin directly to VSS.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
PIC18F2455/2550/4455/4550
DS39632A-page 358 Advance Information 2004 Microchip Technology Inc.
FIGURE 28-1: PIC18F2455/2550/4455/4550 V OLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
FIGURE 28-2: PIC18LF2455/2550/4455/4550 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
Frequency
Voltage
6.0V
5.5V
4.5V
4.0V
2.0V
48 MHz
5.0V
3.5V
3.0V
2.5V
PIC18FX455/X550
4.2V
Frequency
Voltage
6.0V
5.5V
4.5V
4.0V
2.0V
48 MHz
5.0V
3.5V
3.0V
2.5V
PIC18LFX455/X550
Note: VDDAPPMIN is the minimum voltage of the PICmicro® device in the applicat ion.
4 MHz
4.2V
25 MHz16 MHz
2004 Microchip Technology Inc. Advance Information DS39632A-page 359
PIC18F2455/2550/4455/4550
28.1 DC Characteri stics: Supply Voltage
PIC18F2455/2550/4455/4550 (Industrial)
PIC18LF2455/2550/4455/4550 (Industrial)
PIC18LF2455/2550/4455/4550
(Industrial) Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
PIC18F2455/2550/4455/4550
(Industrial) Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
Param
No. Symbol Characteristic Min Typ Max Units Conditions
D001 VDD Supply Voltage 2.0 — 5.5 V HS, XT and Internal Oscillator modes
3.0 — 5.5 V HSPLL, XTPLL, ECPIO and ECPLL modes
D002 VDR RAM Data Retention
Voltage(1) 1.5 — — V
D003 VPOR VDD Start Vo ltage
to ensure internal Power-on
Reset signal
— — 0.7 V See Section 4.3 “Power-on Reset (POR)” for
details
D004 SVDD VDD Rise Rate
to ensure internal Power-on
Reset signal
0.05 — — V/ ms See Section 4.3 “Power-on Reset (POR)” for
details
D005 VBOR Brown-out Reset Voltage
BORV1:BORV0 = 11 1.96 2.06 2.16 V
BORV1:BORV0 = 10 2.64 2.78 2.92 V
BORV1:BORV0 = 01 4.11 4.33 4.55 V
BORV1:BORV0 = 00 4.41 4.64 4.87 V
Legend: Shading of rows is to assist in readability of the table.
Note 1: This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM data.
PIC18F2455/2550/4455/4550
DS39632A-page 360 Advance Information 2004 Microchip Technology Inc.
28.2 DC Characteri stics: Power-Down and Supply Current
PIC18F2455/2550/4455/4550 (Industrial)
PIC18LF2455/2550/4455/4550 (Industrial)
PIC18LF2455/2550/4455/4550
(Industrial) Standard Operati ng Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
PIC18F2455/2550/4455/4550
(Industrial) Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
Param
No. Device Typ Max Units Conditions
Power-down Current (IPD)(1)
PIC18LFX455/X550 0.2 TBD µA -40°C VDD = 2.0V,
(Sleep mode)
0.2 TBD µA +25°C
0.4 TBD µA +85°C
PIC18LFX455/X550 0.2 TBD µA -40°C VDD = 3.0V,
(Sleep mode)
0.2 TBD µA +25°C
0.5 TBD µA +85°C
All devices 0.2 TBD µA -40°C VDD = 5.0V,
(Sleep mode)
0.2 TBD µA +25°C
1.0 TBD µA +85°C
Legend: TBD = To Be Determined. Shading of rows is to assist in readability of the table.
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power- down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: S tandard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
2004 Microchip Technology Inc. Advance Information DS39632A-page 361
PIC18F2455/2550/4455/4550
Supply Current (IDD)(2)
PIC18LFX455/X550 11 TBD µA -40°C
FOSC = 31 kHz
(RC_RUN mode,
Internal oscillator source)
13 TBD µA+25°C V
DD = 2.0V
14 TBD µA+85°C
PIC18LFX455/X550 34 TBD µA -40°C
28 TBD µA+25°C V
DD = 3.0V
25 TBD µA+85°C
All devices 77 TBD µA -40°C
62 TBD µA+25°C V
DD = 5.0V
53 TBD µA+85°C
PIC18LFX455/X550 100 TBD µA -40°C
FOSC = 1 MHz
(RC_RUN mode,
Internal oscillator source)
110 TBD µA+25°C V
DD = 2.0V
120 TBD µA+85°C
PIC18LFX455/X550 180 TBD µA -40°C
180 TBD µA+25°C V
DD = 3.0V
170 TBD µA+85°C
All devices 340 T B D µA -40°C
330 TBD µA+25°C V
DD = 5.0V
310 TBD µA+85°C
PIC18LFX455/X550 350 TBD µA -40°C
FOSC = 4 MHz
(RC_RUN mode,
Internal oscillator source)
360 TBD µA+25°C V
DD = 2.0V
370 TBD µA+85°C
PIC18LFX455/X550 0.58 TBD mA -40°C
0.58 TBD mA +25°C VDD = 3.0V
0.58 TBD mA +85°C
All devices 1.1 TBD mA -40°C
1.1 TBD mA +25°C VDD = 5.0V
1.0 TBD mA +85°C
28.2 DC Characteri stics: Power-Down and Supply Current
PIC18F2455/2550/4455/4550 (Industrial)
PIC18LF2455/2550/4455/4550 (Industrial) (Continued)
PIC18LF2455/2550/4455/4550
(Industrial) Standard Operati ng Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
PIC18F2455/2550/4455/4550
(Industrial) Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
Param
No. Device Typ Max Units Conditions
Legend: TBD = To Be Determined. Shading of rows is to assist in readability of the table.
Note 1: The power-down current in Sleep mode does not depend on the os cillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: S tandard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
PIC18F2455/2550/4455/4550
DS39632A-page 362 Advance Information 2004 Microchip Technology Inc.
Supply Current (IDD)(2)
PIC18LFX455/X550 4.7 TBD µA -40°C
FOSC = 31 kHz
(RC_IDLE mode,
Internal oscillator source)
4.6 TBD µA+25°C V
DD = 2.0V
5.1 TBD µA+85°C
PIC18LFX455/X550 6.9 TBD µA -40°C
6.3 TBD µA+25°C V
DD = 3.0V
6.8 TBD µA+85°C
All devices 12 TBD µA -40°C
10 TBD µA+25°C V
DD = 5.0V
10 TBD µA+85°C
PIC18LFX455/X550 49 TBD µA -40°C
FOSC = 1 MHz
(RC_IDLE mode,
Internal oscillator source)
52 TBD µA+25°C V
DD = 2.0V
56 TBD µA+85°C
PIC18LFX455/X550 73 TBD µA -40°C
77 TBD µA+25°C V
DD = 3.0V
77 TBD µA+85°C
All devices 130 T B D µA -40°C
130 TBD µA+25°C V
DD = 5.0V
130 TBD µA+85°C
PIC18LFX455/X550 140 TBD µA -40°C
FOSC = 4 MHz
(RC_IDLE mode,
Internal oscillator source)
140 TBD µA+25°C V
DD = 2.0V
150 TBD µA+85°C
PIC18LFX455/X550 220 TBD µA -40°C
220 TBD µA+25°C V
DD = 3.0V
210 TBD µA+85°C
All devices 0.39 TBD mA -40°C
0.40 TBD mA +25°C VDD = 5.0V
0.38 TBD mA +85°C
28.2 DC Characteri stics: Power-Down and Supply Current
PIC18F2455/2550/4455/4550 (Industrial)
PIC18LF2455/2550/4455/4550 (Industrial) (Continued)
PIC18LF2455/2550/4455/4550
(Industrial) Standard Operati ng Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
PIC18F2455/2550/4455/4550
(Industrial) Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
Param
No. Device Typ Max Units Conditions
Legend: TBD = To Be Determined. Shading of rows is to assist in readability of the table.
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power- down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: S tandard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
2004 Microchip Technology Inc. Advance Information DS39632A-page 363
PIC18F2455/2550/4455/4550
Supply Current (IDD)(2)
PIC18LFX455/X550 150 TBD µA -40°C
FOSC = 1 MHZ
(PRI_RUN,
EC oscillator)
150 TBD µA+25°C V
DD = 2.0V
160 TBD µA+85°C
PIC18LFX455/X550 340 TBD µA -40°C
300 TBD µA+25°C V
DD = 3.0V
280 TBD µA+85°C
All devices 0.72 TBD mA -40°C
0.63 TBD mA +25°C VDD = 5.0V
0.57 TBD mA +85°C
PIC18LFX455/X550 440 TBD µA -40°C
FOSC = 4 MHz
(PRI_RUN,
EC oscillator)
450 TBD µA+25°C V
DD = 2.0V
460 TBD µA+85°C
PIC18LFX455/X550 0.80 TBD mA -40°C
0.78 TBD mA +25°C VDD = 3.0V
0.77 TBD mA +85°C
All devices 1.6 TBD mA -40°C
1.5 TBD mA +25°C VDD = 5.0V
1.5 TBD mA +85°C
All devices 9.5 TBD mA -40°C
FOSC = 40 MHZ
(PRI_RUN,
EC oscillator)
9.7 TBD mA +25°C VDD = 4.2V
9.9 TBD mA +85°C
All devices 11.9 TBD mA -40°C
12.1 TBD mA +25°C VDD = 5.0V
12.3 TBD mA +85°C
28.2 DC Characteri stics: Power-Down and Supply Current
PIC18F2455/2550/4455/4550 (Industrial)
PIC18LF2455/2550/4455/4550 (Industrial) (Continued)
PIC18LF2455/2550/4455/4550
(Industrial) Standard Operati ng Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
PIC18F2455/2550/4455/4550
(Industrial) Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
Param
No. Device Typ Max Units Conditions
Legend: TBD = To Be Determined. Shading of rows is to assist in readability of the table.
Note 1: The power-down current in Sleep mode does not depend on the os cillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: S tandard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
PIC18F2455/2550/4455/4550
DS39632A-page 364 Advance Information 2004 Microchip Technology Inc.
Supply Current (IDD)(2,3)
PIC18LFX455/X550 37 TBD µA -40°C
FOSC = 1 MHz
(PRI_IDLE mode,
EC oscillator)
37 TBD µA+25°C V
DD = 2.0V
38 TBD µA+85°C
PIC18LFX455/X550 58 TBD µA -40°C
59 TBD µA+25°C V
DD = 3.0V
60 TBD µA+85°C
All devices 110 T B D µA -40°C
110 TBD µA+25°C V
DD = 5.0V
110 TBD µA+85°C
PIC18LFX455/X550 140 TBD µA -40°C
FOSC = 4 MHz
(PRI_IDLE mode,
EC oscillator)
140 TBD µA+25°C V
DD = 2.0V
140 TBD µA+85°C
PIC18LFX455/X550 220 TBD µA -40°C
230 TBD µA+25°C V
DD = 3.0V
230 TBD µA+85°C
All devices 410 T B D µA -40°C
420 TBD µA+25°C V
DD = 5.0V
430 TBD µA+85°C
All devices 3.1 TBD mA -40°C
FOSC = 40 MHz
(PRI_IDLE mode,
EC oscillator)
3.2 TBD mA +25°C VDD = 4.2 V
3.3 TBD mA +85°C
All devices 4.4 TBD mA -40°C
4.6 TBD mA +25°C VDD = 5.0V
4.6 TBD mA +85°C
28.2 DC Characteri stics: Power-Down and Supply Current
PIC18F2455/2550/4455/4550 (Industrial)
PIC18LF2455/2550/4455/4550 (Industrial) (Continued)
PIC18LF2455/2550/4455/4550
(Industrial) Standard Operati ng Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
PIC18F2455/2550/4455/4550
(Industrial) Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
Param
No. Device Typ Max Units Conditions
Legend: TBD = To Be Determined. Shading of rows is to assist in readability of the table.
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power- down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: S tandard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
2004 Microchip Technology Inc. Advance Information DS39632A-page 365
PIC18F2455/2550/4455/4550
Supply Current (IDD)(2,3)
PIC18LFX455/X550 13 TBD µA -10°C
FOSC = 32 kHz(3)
(SEC_RUN mode,
Timer1 as clock)
14 TBD µA+25°C V
DD = 2.0V
16 TBD µA+70°C
PIC18LFX455/X550 34 TBD µA -10°C
31 TBD µA+25°C V
DD = 3.0V
28 TBD µA+70°C
All devices 72 TBD µA -10°C
65 TBD µA+25°C V
DD = 5.0V
59 TBD µA+70°C
PIC18LFX455/X550 5.5 TBD µA -10°C
FOSC = 32 kHz(3)
(SEC_IDLE mode,
Timer1 as clock)
5.8 TBD µA+25°C V
DD = 2.0V
6.1 TBD µA+70°C
PIC18LFX455/X550 8.2 TBD µA -10°C
8.6 TBD µA+25°C V
DD = 3.0V
8.8 TBD µA+70°C
All devices 13 TBD µA -10°C
13 TBD µA+25°C V
DD = 5.0V
13 TBD µA+70°C
28.2 DC Characteri stics: Power-Down and Supply Current
PIC18F2455/2550/4455/4550 (Industrial)
PIC18LF2455/2550/4455/4550 (Industrial) (Continued)
PIC18LF2455/2550/4455/4550
(Industrial) Standard Operati ng Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
PIC18F2455/2550/4455/4550
(Industrial) Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
Param
No. Device Typ Max Units Conditions
Legend: TBD = To Be Determined. Shading of rows is to assist in readability of the table.
Note 1: The power-down current in Sleep mode does not depend on the os cillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: S tandard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
PIC18F2455/2550/4455/4550
DS39632A-page 366 Advance Information 2004 Microchip Technology Inc.
Module Differential Currents (∆IWDT, ∆IBOR, ∆ILVD, ∆IOSCB, ∆IAD)
D022
(∆IWDT)Watchdog T imer 1.7 TBD µA -40°C
2.1 TBD µA+25°C V
DD = 2.0V
2.6 TBD µA+85°C
2.2 TBD µA -40°C
2.4 TBD µA+25°C V
DD = 3.0V
2.8 TBD µA+85°C
2.9 TBD µA -40°C
3.1 TBD µA+25°C V
DD = 5.0V
3.3 TBD µA+85°C
D022A
(∆IBOR)Brown-out Reset 17 TBD µA-40°C to +85°CVDD = 3.0V
47 TBD µA-40°C to +85°CVDD = 5.0V
0TBDµA-40°C to +85°CV
DD = 5.0V Sleep mode,
BOREN1:BOREN0 = 10
D022B
(∆ILVD)Low-Voltage Detect 14 TBD µA-40°C to +85°CVDD = 2.0V
18 TBD µA-40°C to +85°CV
DD = 3.0V
21 TBD µA-40°C to +85°CV
DD = 5.0V
D025
(∆IOSCB)Timer1 Oscillator 1.0 TBD µA-10°C
1.1 TBD µA+25°CV
DD = 2.0V 32 kHz on Timer1(4)
1.1 TBD µA+70°C
1.2 TBD µA-10°C
1.3 TBD µA+25°CV
DD = 3.0V 32 kHz on Timer1(4)
1.2 TBD µA+70°C
1.8 TBD µA-10°C
1.9 TBD µA+25°CV
DD = 5.0V 32 kHz on Timer1(4)
1.9 TBD µA+70°C
D026
(∆IAD)A/D Converter 1.0 TBD µAV
DD = 2.0V A/D on, not converting,
1.6 µs ≤ TAD ≤ 6.4 µs
1.0 TBD µAV
DD = 3.0V
1.0 TBD µAV
DD = 5.0V
28.2 DC Characteri stics: Power-Down and Supply Current
PIC18F2455/2550/4455/4550 (Industrial)
PIC18LF2455/2550/4455/4550 (Industrial) (Continued)
PIC18LF2455/2550/4455/4550
(Industrial) Standard Operati ng Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
PIC18F2455/2550/4455/4550
(Industrial) Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
Param
No. Device Typ Max Units Conditions
Legend: TBD = To Be Determined. Shading of rows is to assist in readability of the table.
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power- down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: S tandard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
2004 Microchip Technology Inc. Advance Information DS39632A-page 367
PIC18F2455/2550/4455/4550
USB and Related Module Differential Currents (∆IUSB, ∆IPLL, ∆IUREG, ∆IXCVR)
∆IUSB USB Module +25°CVDD = 3.0V
+25°CV
DD = 5.0V
∆IPLL 96 MHz USB PLL
(Oscillator Module) +25°CVDD = 3.0V
+25°CV
DD = 5.0V
∆IUREG USB Internal Voltage
Regulator +25°CVDD = 3.0V
+25°CV
DD = 5.0V
∆IXCVR USB On-Chip
Transceiver +25°CVDD = 3.0V
+25°CV
DD = 5.0V
28.2 DC Characteri stics: Power-Down and Supply Current
PIC18F2455/2550/4455/4550 (Industrial)
PIC18LF2455/2550/4455/4550 (Industrial) (Continued)
PIC18LF2455/2550/4455/4550
(Industrial) Standard Operati ng Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
PIC18F2455/2550/4455/4550
(Industrial) Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
Param
No. Device Typ Max Units Conditions
Legend: TBD = To Be Determined. Shading of rows is to assist in readability of the table.
Note 1: The power-down current in Sleep mode does not depend on the os cillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: S tandard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
PIC18F2455/2550/4455/4550
DS39632A-page 368 Advance Information 2004 Microchip Technology Inc.
28.3 DC Characteri stics: PIC18F2455/2550/4455/4550 (I ndustrial)
PIC18LF2455/2550/ 4455/4550 (Industrial)
DC CHARACTERISTICS Standa rd O pera ting Condi tions (unless o therwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
Param
No. Symbol Characteristic Min Max Units Conditions
VIL Input Low Voltage
I/O ports (except RC4/RC5 in
USB mode):
D030 with TTL buffer VSS 0.15 VDD VVDD < 4.5V
D030A — 0.8 V 4.5V ≤ VDD ≤ 5.5V
D031 with Schmitt Trigger buffer
RC3 and RC4 VSS
VSS 0.2 VDD
0.3 VDD V
V
D032 MCLR VSS 0.2 VDD V
D032A OSC1 and T1OSI VSS 0.3 VDD V LP, XT, HS,
HSPLL modes (1)
D033 OSC1 VSS 0.2 VDD VEC mode
(1)
VILU D+/D- Input — 0.8 V VDD = 4.35V,
USB suspended(5)
VIH Input High Voltage
I/O ports (except RC4/RC5 in
USB mode):
D040 with TTL buffer 0.2 5 VDD + 0.8V VDD VVDD < 4.5V
D040A 2.0 VDD V4.5V ≤ VDD ≤ 5.5V
D041 with Schmitt Trigger buffer
RC3 and RC4 0.8 VDD
0.7 VDD VDD
VDD V
V
D042 MCLR 0.8 VDD VDD V
D042A OSC1 and T1OSI 0.7 VDD VDD V LP, XT, HS,
HSPLL modes (1)
D043 OSC1 0.8 VDD VDD VEC mode
(1)
VIHU D+/D- Input 2.4 — V VDD = 4.35V,
USB suspended(5)
IIL Input Leakage Current (2,3)
D060 I/O ports — ±1µAVSS ≤ VPIN ≤ VDD,
Pin at high-impe dan ce
D061 MCLR —±5µAVss ≤ VPIN ≤ VDD
D063 OSC1 — ±5µAVss ≤ VPIN ≤ VDD
IPU Weak Pull-up Current
D070 IPURB PORTB weak pull-u p current 50 400 µAVDD = 5V, VPIN = VSS
Note 1: In RC oscillato r configura tion, t he OSC1/CLKI p in is a Sc hmitt T rigg er input. It is not rec ommended t hat the
PICmicro® device be driven with an external clock while in RC mode.
2: The leakage current on the MCL R pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
4: Parameter is characterized but not tested.
5: D+ parameters per USB Specification 2.0.
2004 Microchip Technology Inc. Advance Information DS39632A-page 369
PIC18F2455/2550/4455/4550
VOL Output Low Voltage
D080 I/O ports (except RC4/RC5 in
USB mode) —0.6VIOL = 8.5 mA, VDD = 4.5 V,
-40°C to +85°C
D083 OSC2/CLKO
(EC, ECIO modes) —0.6VI
OL = 1.6 mA, VDD = 4.5V,
-40°C to +85°C
VOLU D+/D- Out — 0.3 VDD = 4.35V,
USB suspended(5)
VOH Output High Voltage(3)
D090 I/O ports (except RC4/RC5 in
USB mode) VDD – 0.7 — V IOH = -3.0 mA, VDD = 4.5V,
-40°C to +85°C
D092 OSC2/CLKO
(EC, ECIO, ECPIO modes) VDD – 0.7 — V IOH = -1.3 mA, VDD = 4.5V,
-40°C to +85°C
VOHU D+/D- Out 2.8 3.6 V VDD = 4. 35V,
USB suspended(5)
Capacitive Loading Specs
on Output Pins
D100(4) COSC2 OSC2 pin — 15 pF In XT, HS and LP modes
when external clock is
used to drive OSC1
D101 CIO All I/O pins and OSC2
(in RC mode) — 50 pF To meet the AC Timing
Specifications
D102 CBSCL, SDA — 400 pF I2C™ Specification
28.3 DC Characteri stics: PIC18F2455/2550/4455/4550 (I ndustrial)
PIC18LF2455/2550/ 4455/4550 (Industrial ) (Continued)
DC CHARACTERISTICS Standa rd O pera ting Condi tions (unless ot herwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
Param
No. Symbol Characteristic Min Max Units Conditions
Note 1: In RC oscillato r configura tion, t he OSC1/CLKI p in is a Sc hmitt T rigg er input. It is not rec ommended t hat the
PICmicro® device be driv en with an external clock while in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
4: Parameter is characterized but not tested.
5: D+ parameters per USB Specification 2.0.
PIC18F2455/2550/4455/4550
DS39632A-page 370 Advance Information 2004 Microchip Technology Inc.
TABLE 28-1: MEMORY PROGRAMMING REQUIREMENTS
DC Character ist ics Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
Param
No. Sym Characteristic Min Typ† Max Units Conditions
Internal Program Memory
Programming Specifications(1)
D110 VPP Voltage on MCLR/VPP/RE3 pin 9 .00 — 13.25 V (Note 3)
D113 IDDP Supply Current during
Programming ——10mA
Data EEPROM Memory
D120 EDByte Endurance 100K 1M — E/W -40°C to +85°C
D121 VDRW VDD for Read/Write VMIN — 5.5 V Using EECON to read/write
VMIN = Minimum operating
voltage
D122 TDEW Erase/Write Cycle Time — 4 — ms
D123 TRETD Characteristic Retention 40 — — Year Provided no other
specifications are violated
D124 TREF Number of Total E rase/Write
Cycles before Refresh(2) 1M 10M — E/W -40°C to +85°C
Program Flash Memory
D130 EPCell Endurance 10K 100K — E/W -40°C to +85°C
D131 VPR VDD for Read VMIN —5.5VVMIN = Minimum operating
voltage
D132 VIE VDD for Block Erase 4.5 — 5.5 V Using ICSP™ port
D132A VIW VDD for Externally Ti med Erase
or Write 4.5 — 5.5 V Using ICSP port
D132B VPEW VDD for Self-timed Write VMIN —5.5VVMIN = Minimum operating
voltage
D133 TIE ICSP Block Erase Cycle Ti me — 4 — ms VDD > 4.5V
D133A TIW ICSP Er ase or Write Cycle Time
(externall y tim ed) 1——msVDD > 4.5V
D133A TIW Self-timed Write Cycle Time — 2 — ms
D134 TRETD Characteristic Retention 40 100 — Year Provided no other
specifications are violated
† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested .
Note 1: These specifications are for programming the on-chip program memory through the use of table write
instructions.
2: Refer to Section 7.7 “Using the Data EEPROM” for a more detailed discussion on data EEPROM
endurance.
3: Required only if sin gle -su ppl y prog ram mi ng is disab led .
2004 Microchip Technology Inc. Advance Information DS39632A-page 371
PIC18F2455/2550/4455/4550
TABLE 28-2: COMPARATOR SPECIFICATIONS
TABLE 28-3: VOLTAGE REFERENCE SPECIFICATIONS
Operating Conditions: 3.0V < VDD < 5.5V, -40°C < TA < +85°C (unless otherwise stated)
Param
No. Sym Characteristics Min Typ Max Units Comments
D300 VIOFF Input Offset Voltage — ± 5.0 ± 10 mV
D301 VICM Input Common Mode Voltage* 0 — VDD – 1.5 V
D302 CMRR Co mm on Mo de Rejection Ratio* 55 — — dB
300 TRESP Response Time(1)* — 150 400 ns PIC18FXXXX
300A — 150 600 ns PIC18LFXXXX,
VDD = 2.0V
301 TMC2OV Comparator Mode Change to
Output Valid* ——10µs
* These parameters are characterized but not tested.
Note 1: Response time measured with one comparator input at (VDD – 1.5)/2, while the other input transitions
from VSS to VDD.
Operating Condit ions : 3.0V < VDD < 5.5V, -40°C < TA < +85°C (unless otherwise stated)
Param
No. Sym Characteristics Min Typ Max Units Comments
D310 VRES Resolution VDD/24 — VDD/32 LSb
D311 VRAA Absolute Accura cy —
—1/4
—1
1/2 LSb
LSb Low Range (CVRR = 1)
High Range (CVRR = 0)
D312 VRUR Unit Resistor Value (R)* — 2k — Ω
310 TSET Settling Time(1)*— — 10 µs
* These parameters are characterized but not tested.
Note 1: Settling time measured while CVRR = 1 and CVR3:CVR0 transitions from ‘0000’ to ‘1111’.
PIC18F2455/2550/4455/4550
DS39632A-page 372 Advance Information 2004 Microchip Technology Inc.
TABLE 28-4: USB MODULE SPECIFICATIONS
TABLE 28-5: USB INTERNAL VOLTAGE REGULATOR SPECIFICATIONS
Operating Conditions: -40°C < TA < +85°C (unless otherwise stated).
Param
No. Sym Characteristic Min Typ Max Units Comments
VUSB USB Voltage 3.0 — 3.6 V Voltage on bus must be in this
range for proper USB
operation
IIL Input Leaka ge on pin — — ±1µAVSS ≤ VPAD ≤ VDD;
Pin at high impedance
VILUSB Input Low Voltage for USB
Buffer ——0.8VFor VUSB range
VIHUSB Input High Voltage for USB
Buffer 2.0 — — V For VUSB range
VCRS Crossover Voltage 1.3 2.0 V Voltage range for pad_dp and
pad_dm crossover to occur
VDIFS Differential Input Sensiti v ity — — 0.2 V The difference bet ween D+
and D- must exce ed this val ue
while VCM is met
VCM Differential Common Mode
Range 0.8 2.5 V
ZOUT Driver Output Impedance 28 — 44 Ω
VOL Voltage Output Low 0.0 — 0.3 V 1.5 kΩ load connected to 3.6V
VOH Voltage Output High 2.8 — 3.6 V 15 kΩ load connected to
ground
Operating Condit ions : -40°C < TA < +85°C (unless otherwise stated).
Param
No. Sym Characteristics Min Typ Max Units Comments
VUSBANA Regulator Output Voltag e* 3.0 — 3.6 V
CUSB External Fil ter Cap acito r
Value* — 220 — nF Must hold sufficient charge
for peak load with minimal
voltage drop
* These parameters are characterized but not tested. Parameter numbers not yet assigned for these
specifications.
2004 Microchip Technology Inc. Advance Information DS39632A-page 373
PIC18F2455/2550/4455/4550
FIGURE 28-3: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS
TABLE 28-6: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS
VHLVD
HLVDIF
VDD
(HLVDIF set by hardware) (HLVDIF can be
cleared in software)
VHLVD
For VDIRMA G = 1:
For VDIRMA G = 0:VDD
Standard O perati ng Co nditio ns (unle ss othe rwis e s tated)
Operating temperature -40°C ≤ TA ≤ +85°C for indust rial
Param
No. Symbol Characteristic Min Typ† Max Units Conditions
D420 HLVD Voltage on VDD
Transition LVV = 0000 N/A N/A N/A V Reserved
LVV = 0001 N/A N/A N/A V Reserved
LVV = 0010 2.16 2.27 2.38 V
LVV = 0011 2.35 2.47 2.59 V
LVV = 0100 2.43 2.56 2.69 V
LVV = 0101 2.64 2.78 2.92 V
LVV = 0110 2.75 2.89 3.03 V
LVV = 0111 2.95 3.10 3.26 V
LVV = 1000 3.24 3.41 3.58 V
LVV = 1001 3.43 3.61 3.79 V
LVV = 1010 3.53 3.72 3.91 V
LVV = 1011 3.72 3.92 4.12 V
LVV = 1100 3.92 4.13 4.34 V
LVV = 1101 4.11 4.33 4.55 V
LVV = 1110 4.41 4.64 4.87 V
† Production tested at TAMB = 25°C. Specifications over temperature limits ensured by characterization.
PIC18F2455/2550/4455/4550
DS39632A-page 374 Advance Information 2004 Microchip Technology Inc.
28.4 AC (Timing) Charact eristics
28.4.1 TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created
using one of the following formats:
1. TppS2ppS 3. TCC:ST (I2C specifications only)
2. TppS 4. Ts (I2C specifications only)
TF Frequency T Time
Lowercase letters (pp) and their meanings:
pp ad SPP address write m c MCLR
cc CCP1 osc OSC1
ck CLKO rd RD
cs CS rw RD or WR
da SPP data write sc SCK
di SDI ss SS
do SDO t0 T0CKI
dt Data in t1 T13CKI
io I/O port wr WR
Uppercase letters and their meanings:
SF Fall P Period
HHigh RRise
I Invalid (High-impedance) V Valid
L Low Z High-impedance
I2C only
AA ou tput access High High
BUF Bus free Low Low
TCC:ST (I2C specifications only)
CC HD Hold SU Setup
ST DAT DATA input hold STO Stop condition
STA Start condition
2004 Microchip Technology Inc. Advance Information DS39632A-page 375
PIC18F2455/2550/4455/4550
28.4.2 TIMING CONDITIONS
The temperature and voltages specified in Table 28-7
apply to all timing specifications unless otherwise
noted. Figure 28-4 specifies the load conditions for the
timing specific ati on s.
TABLE 28-7: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC
FIGURE 28-4: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Note: Because of space limitations, the generic
terms “PIC18FXXXX” and “PIC18LFXXXX”
are used throughout this section to refer to
the PIC18F2455/2550/4455/4550 and
PIC18LF2455/2550/4455/4550 families of
devices specifically and only thos e devices.
AC CHARACTERISTICS
Standard Operating Conditions (unle ss otherw is e stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
Operating voltage VDD range as described in DC spec Section 28.1 and
Section 28.3.
LF parts operate for industrial temperatures only.
VDD/2
CL
RL
Pin
Pin
VSS
VSS
CL
RL=464Ω
CL= 50 pF for al l pins except OSC2/CLKO
and including D and E outputs as ports
Load Cond iti on 1 Load Condition 2
PIC18F2455/2550/4455/4550
DS39632A-page 376 Advance Information 2004 Microchip Technology Inc.
28.4.3 TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 28-5: EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL)
TABLE 28-8: EXTERNAL CLOCK TIMING REQUIREMENTS
OSC1
CLKO
Q4 Q1 Q2 Q3 Q4 Q1
1
23344
Param.
No. Symbol Characteristic Min Max Units Conditions
1A FOSC External CLKI Frequenc y(1)
Oscillator Frequency(1) DC 48 MHz EC, ECIO Osci llator mode
0.1 4 MHz XT, XTPLL Oscillator mode
4 25 MHz HS Oscillator mode
4 48 MHz HSPLL Oscillator mode
1T
OSC External CLKI Period (1)
Oscillator Period(1) 20.8 — ns EC, ECIO Osci ll ator mode
250 10,000 ns XT Oscillator mode
25
20.8 250
250 ns
ns HS Oscillator mode
HSPLL Oscillator mode
2T
CY Instruction Cycle Time(1) 83.3 — ns TCY = 4/FOSC
3 TosL,
TosH External Clock in (OSC1)
High or Low Time 30 — ns XT Oscillator mode
10 — ns HS Oscillator mode
4TosR,
TosF External Clock in (OSC1)
Rise or Fall Time — 20 ns XT Oscillator mode
— 7.5 ns HS Oscillator mode
Note 1: Instruction cycle peri od (TCY) equals four times the input oscillator time base period for all configurations
except PLL . Al l specified values are bas ed on cha rac teri zation dat a for that p arti cu lar os ci ll ator type unde r
standard operating conditions with the device executing code. Exceeding these specified limits may result
in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested
to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock
input is used, the “max.” cycle time limit is “DC” (no clock) for all devices.
2004 Microchip Technology Inc. Advance Information DS39632A-page 377
PIC18F2455/2550/4455/4550
TABLE 28-9: PLL CLOCK TIMING SPECIFICATIONS (VDD = 4.2V TO 5.5V)
TABLE 28-10: AC CHARACTERISTICS: INTERNAL RC ACCURACY
PIC18F2455/2550/4455/4550 (INDUSTRIAL)
PIC18LF2455/2550/4455/4550 (INDUSTRIAL)
Param
No. Sym Characteristic Min Typ† Max Units Conditions
F10 FOSC Oscillator Frequency Range 4 — 48 MHz
F11 FSYS On-Chip VCO System Frequency — 96 — MHz
F12 trc PLL Start- up Time (Lock Time) — — 2 ms
F13 ∆CLK CLKO Stability (Jitter) -0.25 — +0.25 %
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
PIC18LF2455/2550/4455/4550
(Industrial) Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
PIC18F2455/2550/4455/4550
(Industrial) Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
Param
No. Device Min Typ Max Units Conditions
INTOSC Accuracy @ Freq = 8 MHz, 4 MHz, 2 MHz, 1 MHz, 500 kHz, 250 kHz, 125 kHz(1)
PIC18LF2455/2550/4455/4550 -2 +/-1 2 % +25°C VDD = 2.7-3.3V
-5 — 5 % -10°C to +85°C VDD = 2.7-3.3V
-10 +/-1 10 % -40°C to +85°C V DD = 2.7-3.3V
PIC18F2455/2550/4455/4550 -2 +/-1 2 % +25°C VDD = 4.5-5.5V
-5 — 5 % -10°C to +85°C VDD = 4.5-5.5V
-10 +/-1 10 %-40°C to +85°C VDD = 4.5-5.5V
INTRC Accuracy @ Freq = 31 kHz(2)
PIC18LF2455/2550/4455/4550 26.562 — 35.938 k Hz -40°C to +85°C VDD = 2.7-3.3V
PIC18F2455/2550/4455/4550 26.562 —35.938 kHz -40°C to +85°C VDD = 4.5-5.5V
Legend: Shading of rows is to assist in readability of the table.
Note 1: Frequency calibrated at 25°C. OSCTUNE register can be used to compensate for temperature drift.
2: INTRC frequency after calibration.
3: Change of INTRC frequency as VDD changes.
PIC18F2455/2550/4455/4550
DS39632A-page 378 Advance Information 2004 Microchip Technology Inc.
FIGURE 28-6: CLKO AND I/O TIMING
TABLE 28-11: CLKO AND I/O TIMING REQUIREMENTS
Note: Refer to Figure 28-4 for load conditions.
OSC1
CLKO
I/O pin
(Input)
I/O pin
(Output)
Q4 Q1 Q2 Q3
10
13 14
17
20, 21
19 18
15
11
12
16
Old Value New Value
Param
No. Symbol Characteristic Min Typ Max Units Conditions
10 TosH2ckL OSC1 ↑ to CLKO ↓ — 75 200 ns (Note 1)
11 T osH2ckH OSC1 ↑ to CLKO ↑ — 75 200 ns (Note 1)
12 TckR CLKO Rise Time — 35 100 ns (Note 1)
13 TckF CLKO Fall Time — 35 100 ns (Note 1)
14 TckL2ioV CLKO ↓ to Port Out Valid — — 0.5 TCY + 20 ns (Note 1)
15 TioV2ckH Port In Valid before CLKO ↑ 0.25 TCY + 25 — — ns (Note 1)
16 TckH2ioI Port In Hold after CLKO ↑ 0——ns(Note 1)
17 TosH2ioV OSC1 ↑ (Q1 cycle) to Port Out Valid — 50 150 ns
18 TosH2ioI OSC1 ↑ (Q2 cycle) to
Port Input Invalid
(I/O in hold time)
PIC18FXXXX 100 — — ns
18A PIC18LFXXXX 200 — — ns VDD = 2.0V
19 TioV2osH Port Input V alid to OSC1 ↑ (I/O in setup time) 0 — — ns
20 TioR Port Output Rise Time PIC18FXXXX — 10 25 ns
20A PIC18LFXXXX — — 60 ns VDD = 2.0V
21 TioF Port Output Fall Time PIC18FXXXX — 10 25 ns
21A PIC18LFXXXX — — 60 ns VDD = 2.0V
22† TINP INT pin High or Low Time TCY ——ns
23† TRBP RB7:RB4 Change INT High or Low Time TCY ——ns
24† TRCP RC7:RC4 Change INT High or Low Time 20 ns
† These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken in RC mode, where CLKO output is 4 x TOSC.
2004 Microchip Technology Inc. Advance Information DS39632A-page 379
PIC18F2455/2550/4455/4550
FIGURE 28-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND
POWER-UP TIMER TIMING
FIGURE 28-8: BROWN-OUT RESET TIMING
TABLE 28-12: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET REQUIREMENTS
Param.
No. Symbol Characteristic Min Typ Max Units Conditions
30 TmcL MCLR Pulse Width (low) 2 — — µs
31 TWDT Watchdog Timer Ti me-out Period
(no postscaler) —4.00TBDms
32 TOST Oscillati on Start-up Timer Period 1024 TOSC — 1024 TOSC —TOSC = OSC1 period
33 TPWRT Power-up Timer Period — 65.5 TBD ms
34 TIOZ I/O High-Impedance from MCLR
Low or Watchdog Timer Reset —2—µs
35 TBOR Brown-out Reset Pulse Width 200 — — µsVDD ≤ BVDD (see D005)
36 TIVRST Time for Internal Reference
Voltage to become Stable —2050 µs
37 TLVD Low-Voltage Detect Pulse Width 200 — — µsVDD ≤ VLVD
38 TCSD CPU Start-up Time 5 — 10 µs
39 TIOBST Time for INTOSC to Stabilize — 1 — ms
Legend: TBD = To Be Determined
VDD
MCLR
Internal
POR
PWRT
Time-out
OSC
Time-out
Internal
Reset
Watchdog
Timer
Reset
33
32
30
31
34
I/O pins
34
Note: Refer to Figure 28-4 for load conditions.
VDD BVDD 35 VBGAP = 1.2V
VIRVST
Enable Internal
Inte rn a l Referenc e 36
Reference Vo ltage
Voltage Stable
PIC18F2455/2550/4455/4550
DS39632A-page 380 Advance Information 2004 Microchip Technology Inc.
FIGURE 28-9: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
TABLE 28-13: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Note: Refer to Figure 28-4 for load conditions.
46
47
45
48
41
42
40
T0CKI
T1OSO/T13CKI
TMR0 or
TMR1
Param
No. Symbol Characteristic Min Max Units Conditions
40 Tt0H T 0CKI H igh Pulse Width No prescaler 0.5 TCY + 20 — ns
With prescaler 10 — ns
41 Tt0L T0CKI Low P ulse Width No prescaler 0 .5 TCY + 20 — ns
With prescaler 10 — ns
42 Tt0P T0CKI Period No prescaler TCY + 10 — ns
With prescaler Greater of:
20 ns or
(TCY + 40)/N
—nsN = prescale
value
(1, 2, 4,..., 256)
45 Tt1H T13CKI High
Time Synchronous, no prescaler 0.5 TCY + 20 — ns
Synchronous,
with prescaler PIC18FXXXX 10 — ns
PIC18LFXXXX 25 — ns VDD = 2.0V
Asynchronous PIC18FXXXX 30 — ns
PIC18LFXXXX 50 — ns VDD = 2.0V
46 Tt1L T13CKI Low
Time Synchronous, no prescaler 0.5 TCY + 5 — ns
Synchronous,
with prescaler PIC18FXXXX 10 — ns
PIC18LFXXXX 25 — ns VDD = 2.0V
Asynchronous PIC18FXXXX 30 — ns
PIC18LFXXXX 50 — ns VDD = 2.0V
47 Tt1P T13CKI Input
Period Synchronous Greater of:
20 ns or
(TCY + 40)/N
—nsN = prescale
value (1, 2, 4, 8)
Asynchronous 60 — ns
Ft1 T13CKI Oscillator Input Frequency Range DC 50 kHz
48 Tcke 2t mr I Delay from Ext ernal T13CKI Clo ck Edge to T imer
Increment 2 TOSC 7 TOSC —
2004 Microchip Technology Inc. Advance Information DS39632A-page 381
PIC18F2455/2550/4455/4550
FIGURE 28-10: CAPTURE/COMPARE/PWM TIMINGS (ALL CCP MODULES)
TABLE 28-14: CAPTURE/COMPARE/PWM REQUIREMENTS (ALL CCP MODULES)
Note: Refer to Figure 28-4 for load conditions.
CCPx
(Capture Mode)
50 51
52
CCPx
53 54
(Compare or PWM Mode)
Param
No. Symbol Characteristic Min Max Units Conditions
50 T ccL CCPx Input Low
Time No prescaler 0.5 TCY + 20 — ns
With
prescaler PIC18FXXXX 10 — ns
PIC18LFXXXX 20 — ns VDD = 2.0V
51 TccH CCPx In put
High Time No prescaler 0.5 TCY + 20 — ns
With
prescaler PIC18FXXXX 10 — ns
PIC18LFXXXX 20 — ns VDD = 2.0V
52 TccP CCPx I nput Period 3 TCY + 40
N—nsN = prescale
value (1, 4 or 16)
53 TccR CCPx Output Fall Time PIC18FXXXX — 25 ns
PIC18LFXXXX — 45 ns VDD = 2.0V
54 TccF CCPx Output Fall Time PIC18FXXXX — 25 ns
PIC18LFXXXX — 45 ns VDD = 2.0V
PIC18F2455/2550/4455/4550
DS39632A-page 382 Advance Information 2004 Microchip Technology Inc.
FIGURE 28-11: EXAMPLE SPI™ MASTER MODE TIMING (CKE = 0)
TABLE 28-15: EXAMPLE SPI™ MODE REQUIREMENTS (MASTER MODE, CKE = 0)
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
70
71 72
73 74
75, 76
78
79
80
79
78
MSb LSb
bit 6 - - - - - -1
MSb In LSb In
bit 6 - - - -1
Note: Refer to Figure 28-4 for load conditions.
Param
No. Symbol Characteristic Min Max Units Conditions
70 TssL2scH,
TssL2scL SS ↓ to SCK ↓ or SCK ↑ Inpu t TCY —ns
71 TscH SCK Input High Time
(Slave mode) Continuous 1.25 TCY + 30 — ns
71A Sing le Byte 40 — ns (Note 1)
72 TscL SCK Input Low Time
(Slave mode) Continuous 1.25 TCY + 30 — ns
72A Sing le Byte 40 — ns (Note 1)
73 TdiV2scH,
TdiV2scL Setup Time of SDI Data Input to SCK Edge 100 — ns
73A Tb2b Last Clock Edge o f Byte 1 t o the 1s t Clock Edge
of Byte 2 1.5 TCY + 40 — n s (Note 2)
74 TscH2diL,
TscL2diL Hold Time of SDI Data Input to SCK Edge 100 — ns
75 TdoR SDO Data Output Rise Time PIC18FXXXX — 25 ns
PIC18LFXXXX — 45 ns VDD = 2.0V
76 TdoF SDO Data Output Fall Time — 25 ns
78 TscR SCK Output Rise Time
(Master mode) PIC18FXXXX — 25 ns
PIC18LFXXXX — 45 ns VDD = 2.0V
79 TscF SCK Output Fall Time (Master mode) — 25 ns
80 TscH2doV,
TscL2doV SDO Data Output Valid after
SCK Edge PIC18FXXXX — 50 ns
PIC18LFXXXX — 100 ns VDD = 2.0V
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
2004 Microchip Technology Inc. Advance Information DS39632A-page 383
PIC18F2455/2550/4455/4550
FIGURE 28-12 : EXAMP LE SP I™ MASTER MODE TIMING (CKE = 1)
TABLE 28-16: EXAMPLE SPI™ MODE REQUIREMENTS (MASTER MODE, CKE = 1)
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
81
71 72
74
75, 76
78
80
MSb
79
73
MSb In
bit 6 - - - - - -1
LSb In
bit 6 - - - -1
LSb
Note: Refer to Figure 28-4 for load conditions.
Param.
No. Symbol Characteristic Min Max Units Conditions
71 TscH SCK Input High Time
(Slave mode) Continuous 1.25 TCY + 30 — ns
71A Single Byte 40 — ns (Note 1)
72 TscL SCK Input Low Time
(Slave mode) Continuous 1.25 TCY + 30 — ns
72A Single Byte 40 — ns (Note 1)
73 TdiV2scH,
TdiV2scL Setup Time of SDI Data Input to SCK Edge 100 — ns
73A Tb2b Last Clock Edge of Byte 1 to the 1st Clock Edge
of Byte 2 1.5 TCY + 40 — ns (Note 2)
74 TscH2diL,
TscL2diL Hold Time of SDI Data Input to SCK Edge 100 — ns
75 TdoR SDO Data Output Rise Time PIC18FXXXX — 25 ns
PIC18LFXXXX 45 ns VDD = 2.0V
76 TdoF SDO Data Output Fall Time — 25 ns
78 TscR SCK Output Rise Ti me
(Master mode) PIC18FXXXX — 25 ns
PIC18LFXXXX 45 ns VDD = 2.0V
79 TscF SCK Output Fall Time (Master mode) — 25 ns
80 TscH2doV,
TscL2doV SDO Data Output Valid after
SCK Edge PIC18FXXXX — 50 ns
PIC18LFXXXX 100 ns VDD = 2.0V
81 TdoV2scH,
TdoV2scL SDO Data Output Setup to SCK Edge TCY —ns
Note 1: Requ ires the us e of P arameter #73A.
2: Only if Parameter #71A and #72A are used.
PIC18F2455/2550/4455/4550
DS39632A-page 384 Advance Information 2004 Microchip Technology Inc.
FIGURE 28-13: EXAMPLE SPI™ SLAVE MODE TIMING (CKE = 0)
TABLE 28-17: EXAMPLE SPI™ MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0)
Param
No. Symbol Characteristic Min Max Units Conditions
70 TssL2scH,
TssL2scL SS ↓ to SCK ↓ or SCK ↑ Input TCY —ns
71 TscH SCK Input High Time
(Slave mode) Continuous 1.25 TCY + 30 — n s
71A Single Byte 40 — ns (Note 1)
72 TscL SCK Input Low Time
(Slave mode) Continuous 1.25 TCY + 30 — n s
72A Single Byte 40 — ns (Note 1)
73 TdiV2scH,
TdiV2scL Setup Time of SDI Data Input to SCK Edge 100 — ns
73A Tb2b Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 — ns (Note 2)
74 TscH2diL,
TscL2diL Hold Time of SDI Data Input to SCK Edge 100 — ns
75 TdoR SDO Data Output Rise Time PIC18FXXXX — 25 ns
PIC18LFXXXX 45 ns VDD = 2.0V
76 TdoF SDO Data Output Fall Time — 25 ns
77 TssH2doZ SS↑ to SDO Output High-Impedance 10 50 ns
78 TscR SCK Output Rise Time (Master mode) PIC18FXXXX — 25 ns
PIC18LFXXXX 45 ns VDD = 2.0V
79 TscF SCK Output Fall Time (Master mode) — 25 ns
80 TscH2doV,
TscL2doV SDO Data Output Valid after SCK Edge PIC18FXXXX — 50 ns
PIC18LFXXXX 100 ns VDD = 2.0V
83 TscH2ssH,
TscL2ssH SS ↑ after SCK edge 1.5 TCY + 40 — ns
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
70
71 72
73 74
75, 76 77
78
79
80
79
78
SDI
MSb LSb
bit 6 - - - - - -1
MSb In bit 6 - - - -1 LSb In
83
Note: Refer to Figure 28-4 for load conditions.
2004 Microchip Technology Inc. Advance Information DS39632A-page 385
PIC18F2455/2550/4455/4550
FIGURE 28-14: EXAMPLE SPI™ SLAVE MODE TIMING (CKE = 1)
TABLE 28-18: EXAMPLE SPI™ SLAVE MODE REQUIREMENTS (CKE = 1)
Param
No. Symbol Characteristic Min Max Units Conditions
70 TssL2scH,
TssL2scL SS ↓ to SCK ↓ or SCK ↑ Input TCY —ns
71 TscH SCK Input High Time
(Slave mode) Continuous 1.25 TCY + 30 — ns
71A Single Byte 40 — ns (Note 1)
72 TscL SCK Input Low Time
(Slave mode) Continuous 1.25 TCY + 30 — ns
72A Single Byte 40 — ns (Note 1)
73A Tb2b Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 — ns (Note 2)
74 TscH2diL,
TscL2diL Hold Time of SDI Data Input to SCK Edge 100 — ns
75 TdoR SDO Dat a Outpu t Ris e Time PIC18FXXXX — 25 ns
PIC18LFXXXX 45 ns VDD = 2.0V
76 TdoF SDO Da ta Output Fall Time — 25 ns
77 TssH2doZ SS↑ to SDO Output High-Impedance 10 50 ns
78 TscR SCK Output Rise Time
(Master mode) PIC18FXXXX — 25 ns
PIC18LFXXXX — 45 ns VDD = 2.0V
79 TscF SCK Output Fall Time (Master mode) — 25 ns
80 TscH2doV,
TscL2doV SDO Data Output Valid after SCK
Edge PIC18FXXXX — 50 ns
PIC18LFXXXX — 100 ns VDD = 2.0V
82 TssL2doV SDO Dat a Output Valid after SS ↓
Edge PIC18FXXXX — 50 ns
PIC18LFXXXX — 100 ns VDD = 2.0V
83 TscH2ssH,
TscL2ssH SS ↑ after SCK Edge 1.5 TCY + 40 — ns
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
70
71 72
82
SDI
74
75, 76
MSb bit 6 - - - - - -1 LSb
77
MSb In bit 6 - - - -1 LSb In
80
83
Note: Refer to Figure 28- 4 for load conditions.
PIC18F2455/2550/4455/4550
DS39632A-page 386 Advance Information 2004 Microchip Technology Inc.
FIGURE 28-15 : I2C™ BUS START/STOP BITS TIMING
TABLE 28-19: I2C™ BUS START/STOP BITS REQUIREMENTS (SLAVE MODE)
FIGURE 28-16 : I2C™ BUS DATA TIMING
Note: Refer to Figure 28-4 for load conditions.
91
92
93
SCL
SDA
Start
Condition Stop
Condition
90
Param.
No. Symbol Characteristic Min Max Units Conditions
90 TSU:STA Start Condition 100 kHz mode 4700 — ns Only relevant for Repeated
Start condition
Setup Time 400 kHz mode 600 —
91 THD:STA Start Condition 100 kHz mode 400 0 — ns After this per iod, the first
clock pulse is generated
Hold Time 400 kHz mode 600 —
92 TSU:STO Stop Condition 100 kHz mode 4700 — ns
Setup Time 400 kHz mode 600 —
93 THD:STO Stop Condition 100 kHz mode 4000 — ns
Hold Time 400 kHz mode 600 —
Note: Refer to Figure 28- 4 for load conditions.
90
91 92
100
101
103
106 107
109 109 110
102
SCL
SDA
In
SDA
Out
2004 Microchip Technology Inc. Advance Information DS39632A-page 387
PIC18F2455/2550/4455/4550
TABLE 28-20: I2C™ BUS DATA REQUIREMENTS (SLAVE MODE)
Param.
No. Symbol Characteristic Min Max Units Conditions
100 THIGH Clock High Time 100 kHz mode 4.0 — µs PIC18FXXXX must operate
at a minimum of 1.5 MHz
400 kHz mode 0.6 — µs PIC18FXXXX must operate
at a minimum of 10 MHz
SSP Module 1.5 TCY —
101 TLOW Clock Low Time 100 kHz mode 4.7 — µs PIC18FXXXX must operate
at a minimum of 1.5 MHz
400 kHz mode 1.3 — µs PIC18FXXXX must operate
at a minimum of 10 MHz
SSP Module 1.5 TCY —
102 TRSDA and SCL Rise
Time 100 kHz mode — 1000 ns
400 kHz mode 20 + 0.1 CB300 ns CB is specified to be from
10 to 400 pF
103 TFSDA and SCL Fall
Time 100 kHz mode — 300 ns
400 kHz mode 20 + 0.1 CB300 ns CB is specified to be from
10 to 400 pF
90 TSU:STA Start Condition
Setup Time 100 kHz mode 4.7 — µs Only relevant for Repeated
Start condition
400 kHz mode 0.6 — µs
91 THD:STA Start Condition
Hold Time 100 kHz mode 4.0 — µs After this period, the first
clock pulse is generated
400 kHz mode 0.6 — µs
106 THD:DAT Data Input Hold
Time 100 kHz mode 0 — ns
400 kHz mode 0 0.9 µs
107 TSU:DAT Data Input Setup
Time 100 kHz mode 250 — ns (Note 2)
400 kHz mode 1 00 — ns
92 TSU:STO Stop Condition
Setup Time 100 kHz mode 4.7 — µs
400 kHz mode 0.6 — µs
109 TAA Output Valid from
Clock 100 kHz mode — 350 0 ns (Note 1)
400 kHz mode — — ns
110 TBUF Bus Free Time 100 kHz mode 4.7 — µs Time the bus must be free
before a new transmission
can start
400 kHz mode 1.3 — µs
D102 CBBus Capacitive Loading — 400 pF
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
2: A fast mode I2C bus device can be used in a standard mode I2C bus s ystem but the requirement ,
TSU:DAT ≥250 ns, must then be met. This will automatically be the case if the device does not stretch the
LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must
output the next dat a bit to the SDA line, TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the
standard mode I2C bus specification), before the SCL line is released.
PIC18F2455/2550/4455/4550
DS39632A-page 388 Advance Information 2004 Microchip Technology Inc.
FIGURE 28-17: MASTER SSP I2C™ BUS START/STOP BITS TIMING WAVEFORMS
TABLE 28-21: MASTER SSP I2C™ BUS START/STOP BITS REQUIREMENTS
FIGURE 28-18: MASTER SSP I2C™ BUS DATA TIMING
Note: Refer to Figure 28-4 for load conditions.
91 93
SCL
SDA
Start
Condition Stop
Condition
90 92
Param.
No. Symbol Characteristic Min Max Units Conditions
90 TSU:STA Start Conditio n 100 kHz mode 2(TOSC)(BRG + 1) — ns Only relevant for
Repeated Start
condition
Setup Time 400 kHz mode 2(TOSC)(BRG + 1) —
1 MHz mode(1) 2(TOSC)(BRG + 1) —
91 THD:STA Start Co ndition 1 00 kH z mode 2(TOSC)(BRG + 1) — ns After this period, the
first clock pulse is
generated
Hold Time 400 kHz mode 2(TOSC)(BRG + 1) —
1 MHz mode(1) 2(TOSC)(BRG + 1) —
92 TSU:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns
Setup Time 400 kHz mode 2(TOSC)(BRG + 1) —
1 MHz mode(1) 2(TOSC)(BRG + 1) —
93 THD:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns
Hold Time 400 kHz mode 2(TOSC)(BRG + 1) —
1 MHz mode(1) 2(TOSC)(BRG + 1) —
Note 1: Maximum pin capacitance = 10 pF for all I2C pins.
Note: Refer to Figure 28-4 for load conditions.
90 91 92
100 101
103
106 107
109 109 110
102
SCL
SDA
In
SDA
Out
2004 Microchip Technology Inc. Advance Information DS39632A-page 389
PIC18F2455/2550/4455/4550
TABLE 28-22: MASTER SSP I2C™ BUS DATA REQUIREMENTS
Param.
No. Symbol Characteristic Min Max Units Conditions
100 THIGH Clock H igh Time 100 kHz mode 2(TOSC)(BRG + 1) — ms
400 kHz mode 2(TOSC)(BRG + 1) — ms
1 MHz mode(1) 2(TOSC)(BRG + 1) — m s
101 TLOW Clock Low Time 100 kHz mode 2(TOSC)(BRG + 1) — ms
400 kHz mode 2(TOSC)(BRG + 1) — ms
1 MHz mode(1) 2(TOSC)(BRG + 1) — m s
102 TRSDA and SCL
Rise Time 100 kHz mode — 1000 ns CB is specified to be from
10 to 400 pF
400 kHz mode 20 + 0.1 CB300 ns
1 MHz mode(1) — 300 ns
103 TFSDA and SCL
Fall Time 100 kHz mode — 300 ns CB is specified to be from
10 to 400 pF
400 kHz mode 20 + 0.1 CB 300 ns
1 MHz mode(1) — 100 ns
90 TSU:STA Start Condition
Setup Time 100 kHz mode 2(TOSC)(BRG + 1) — ms Only relevant for
Repeated Start
condition
400 kHz mode 2(TOSC)(BRG + 1) — ms
1 MHz mode(1) 2(TOSC)(BRG + 1) — ms
91 THD:STA Start Condition
Hold Time 1 00 kH z mode 2(TOSC)(BRG + 1) — ms After this period, the first
clock pulse is generated
400 kHz mode 2(TOSC)(BRG + 1) — ms
1 MHz mode(1) 2(TOSC)(BRG + 1) — ms
106 THD:DAT Data Input
Hold Time 100 kHz mode 0 — ns
400 kHz mode 0 0.9 ms
107 TSU:DAT Data Input
Setup Time 100 kHz mode 250 — ns (Note 2)
400 kHz mode 100 — ns
92 TSU:STO Stop Condition
Setup Time 100 kHz mode 2(TOSC)(BRG + 1) — ms
400 kHz mode 2(TOSC)(BRG + 1) — ms
1 MHz mode(1) 2(TOSC)(BRG + 1) — ms
109 TAA Output Valid
from Clock 100 kH z mode — 3500 ns
400 kHz mode — 1000 ns
1 MHz mode(1) ——ns
110 TBUF Bus Free Tim e 100 kHz mode 4.7 — ms T ime th e bus mu st b e free
before a new transmission
can start
400 kHz mode 1.3 — ms
D102 CBBus Capac itive Loading — 400 pF
Note 1: Maximum pin capacitance = 10 pF for all I2C pins.
2: A Fast mode I 2C bus de vi ce c an be used i n a s tan dard m ode I 2C bu s sy stem but , p aram eter #107 ≥250 ns,
must then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit
to the SDA line, parameter #102 + parameter #107 = 1000 + 250 = 1250 ns (for 100 kHz mode), before the
SCL line is released.
PIC18F2455/2550/4455/4550
DS39632A-page 390 Advance Information 2004 Microchip Technology Inc.
FIGURE 28-19: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
TABLE 28-23: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
FIGURE 28-20: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
TABLE 28-24: USART SYNCHRONOUS RECEIVE REQUIREMENTS
121 121
120 122
RC6/TX/CK
RC7/RX/DT
pin
pin
Note: Refer to Figure 28-4 for load conditions.
Param
No. Symbol Characteristic Min Max Units Conditions
120 TckH2dtV SYNC XMIT (MASTER & SLAVE)
Clock High to Data Out Valid PIC18FXXXX — 40 ns
PIC18LFXXXX — 100 ns VDD = 2.0V
121 Tckrf Clock Out Rise Time and Fall Time
(Master mode) PIC18FXXXX — 20 ns
PIC18LFXXXX — 50 ns VDD = 2.0V
122 Tdtrf Data Out Rise Time and Fall Time PIC18FXXXX — 20 ns
PIC18LFXXXX — 50 ns VDD = 2.0V
125
126
RC6/TX/CK
RC7/RX/DT
pin
pin
Note: Refer to Figure 28-4 for load conditions.
Param.
No. Symbol Characteristic Min Max Units Conditions
125 TDTV2CKL SYNC RCV (MASTER & SLAVE)
Data Hold before CK ↓ (DT hold time) 10 — ns
126 TCKL2DTL Data Hold after CK ↓ (DT hold time) 15 — ns
2004 Microchip Technology Inc. Advance Information DS39632A-page 391
PIC18F2455/2550/4455/4550
FIGURE 28-21 : USB SIGNA L TIMING
TABLE 28-25: USB LOW-SPEED TIMING REQUIREMENTS
TABLE 28-26: USB FULL SPEED REQUIREMENTS
VCRS
USB Data Differential Lines
90%
10%
TLR,TFR TLF,TFF
Param
No. Symbol Characteristic Min Typ Max Units Conditions
TLR Transition Rise Time 75 — 300 ns CL = 200 to 600 pF
TLF Transition Fall Time 75 — 300 ns CL = 200 to 600 pF
TLRFM Rise/Fall Time Matching 80 — 125 %
Param
No. Symbol Characteristic Min Typ Max Units Conditions
TFR Transition Rise Time 4 — 20 ns CL = 50 pF
TFF Transition Fall Time 4 — 20 ns CL = 50 pF
TFRFM Rise/Fall Time Matching 90 — 111.1 %
PIC18F2455/2550/4455/4550
DS39632A-page 392 Advance Information 2004 Microchip Technology Inc.
FIGURE 28-22: STREAMING PARALLEL PORT TIMING (PIC18F4455/4550)
TABLE 28-27: PARALLEL SLAVE PORT REQUIREMENTS (PIC18F4455/4550)
OESPP
CSSPP
SPP<7:0> Write Data
ToeF2adR
ToeF2adV ToeR2adI
ToeF2daR
ToeF2daV ToeR2adI
Note: Refer to Figure 28 -4 for load conditions.
Write Address
Param.
No. Symbol Characteristic Min Max Units Conditions
ToeF2adR OESPP Falling Edge to CSSPP Rising Edge,
Address Out 05ns
ToeF2adV OESPP Falling Edge to Addres s Out Valid 0 5 ns
ToeR2adI OESPP Rising Edge to Address Out Invalid 0 5 ns
ToeF2daR OESPP Falling Edge to CSSPP Rising Edge,
Data Out 05ns
ToeF2daV OESPP Falling Edge to Addres s Out Valid 0 5 ns
ToeR2daI OESPP Rising Edge to Data Out Invalid 0 5 ns
2004 Microchip Technology Inc. Advance Information DS39632A-page 393
PIC18F2455/2550/4455/4550
TABLE 28-28: A/D CONVERTER CHARACTERISTICS: PIC18F2455/2550/4455/4550 (INDUSTRIAL)
PIC18LF2455/2550/4455/4550 (INDUSTRIAL)
Param
No. Symbol Characteristic Min Typ Max Units Conditions
A01 NRResolution — — 10 bit ∆VREF ≥ 3.0V
A03 EIL Integral Linearity Error — — <±1 LSb ∆VREF ≥ 3.0V
A04 EDL Differential Linearity Error — — <±1 LSb ∆VREF ≥ 3.0V
A06 EOFF Offset Error — — <±1 LSb ∆VREF ≥ 3.0V
A07 EGN Gain Error — — < ±1 LSb ∆VREF ≥ 3.0V
A10 — Monotonicity Guaranteed(1) —
A20 ∆VREF Reference Voltage Range
(VREFH – VREFL)3—AV
DD – AVSS V For 10-bit resolution
A21 VREFH Reference Voltage High AVSS + 3.0V — AVDD + 0.3V V For 10-bit resolution
A22 VREFL Reference Voltage Low AVSS – 0.3V — AVDD – 3.0V V For 10-bit resolutio n
A25 VAIN Anal og Inpu t Volta ge V REFL —VREFH V
A28 AVDD Anal og Supp ly Voltag e VDD – 0.3 — VDD + 0.3 V
A29 AVSS Anal og Supp ly Voltag e VSS – 0.3 — VSS + 0.3 V
A30 ZAIN Recommended Impedance of
Anal og Volt age Source ——2.5kΩ
A40 IAD A/D Conversion
Current (VDD)PIC18FXXXX — 180 — µA Average current
cons umption when
A/D is on (Note 2)
PIC18LFXXXX — 90 — µAV
DD = 2.0V;
Average current
cons umption when
A/D is on (Note 2)
A50 IREF VREF Input Current (Note 3) —
——
—±5
±150 µA
µADuring VAIN acquisition.
During A/D conversion
cycle.
Note 1: The A/D conversion result never decrea ses with an incr ease in the input vo lta ge and has no miss ing code s.
2: When A/D is off, it will not consu me any cu rren t oth er th an m in or le ak age cu rrent. The powe r-dow n cu rrent
spec includes any such leakage from the A/D module.
3: VREFH current is from RA3/AN3/VREF+ pin or AVDD, whichever is selected as the VREFH source.
VREFL current is from RA2/AN2/VREF-/CVREF pin or AVSS, whichever is select ed as t he VREFL sour ce .
PIC18F2455/2550/4455/4550
DS39632A-page 394 Advance Information 2004 Microchip Technology Inc.
FIGURE 28-23: A/D CONVERSION TIMING
TABLE 28-29: A/D CONVERSION REQUIREMENTS
131
130
132
BSF ADCON0, GO
Q4
A/D CLK
A/D DATA
ADRES
ADIF
GO
SAMPLE
OLD_DATA
SAMPLING STOPPED
DONE
NEW_DATA
(Note 2)
987 21 0
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts.
This allows the SLEEP instruction to be executed.
2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
. . . . . .
TCY
Param
No. Symbol Characteristic Min Max Units Conditions
130 TAD A/D Clock Period PIC18 FXXXX 0.7 25.0(1) µsTOSC based, VREF ≥ 3.0V
PIC18LFXXXX TBD TBD µsVDD = 2.0V;
TOSC based, VREF full range
PIC18FXXXX TBD TBD µs A/D RC mode
PIC18LFXXXX TBD TBD µsV
DD = 2.0V;
A/D RC mode
131 TCNV Conversion Time
(not including acquisition time) (Note 2) 11 12 TAD
132 TACQ Acquisition Time (Note 3) 1.4
TBD —
—µs
µs-40°C to +85°C
0°C ≤ to ≤ +85°C
135 TSWC Switching Time from Convert → Sample — (Note 4)
TBD TDIS Discharge Time 0.2 — µs
Note 1: The time of the A/D clock period is dependent on the device frequency and the TAD clock divide r.
2: ADRES register may be read on the following TCY cycle.
3: The time for the holdin g capacitor to acquire the “New” input voltage when th e voltage cha nges full scale
after the conversion (AVDD to AVSS or AVSS to AVDD). The source impedance (RS) on th e i npu t ch annels is
50Ω.
4: On the following cycle of the device clock.
2004 Microchip Technology Inc. Advance Information DS39632A-page 395
PIC18F2455/2550/4455/4550
29.0 DC AND AC
CHARACTERISTICS GRAPHS
AND TABLES
Graphs and tables are not available at this time.
PIC18F2455/2550/4455/4550
DS39632A-page 396 Advance Information 2004 Microchip Technology Inc.
NOTES:
2004 Microchip Technology Inc. Advance Information DS39632A-page 397
PIC18F2455/2550/4455/4550
30.0 PACKAGING INFORMATION
30.1 Package Marking Information
28-Lead PDIP (Skinny DIP)
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
Example
PIC18F2455-I/SP
0410017
28-Lead SO IC
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
YYWWNNN
Example
PIC18F2550-E/SO
0410017
40-Lead PDIP
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
YYWWNNN
Example
PIC18F4455-I/P
0410017
Legend: XX... X Customer sp eci fic inform at ion *
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Note: In the event th e full Mi croch ip p art numbe r canno t be marke d on one li ne, it w ill
be carried o ver to the ne xt line thus lim iting the nu mb er of a vai la ble cha rac ters
for customer specific information.
*Standard PICmicro device marking consists of Microchip part number, year code, week code, and
traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check
with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP
price.
PIC18F2455/2550/4455/4550
DS39632A-page 398 Advance Information 2004 Microchip Technology Inc.
Package Marking Information (Continued)
44-Lead TQFP
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
Example
PIC18F4550
-I/PT0410017
XXXXXXXXXX
44-Lead QFN
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
PIC18F4550
Example
-I/ML
0410017
2004 Microchip Technology Inc. Advance Information DS39632A-page 399
PIC18F2455/2550/4455/4550
30.2 Package Details
The following sections give the technical details of the
packages.
28-Lead Skinny Plasti c Dual In-line (SP) – 300 mil Body (PDIP)
1510515105
β
Mold Draft Angle Bottom 1510515105
α
Mold Draft Angle Top 10.928.898.13.430.350.320eBOverall Row Spacing § 0.560.480.41.022.019.016BLower Lead Width 1.651.331.02.065.053.040B1Upper Lead Width 0.380.290.20.015.012.008
c
Lead Thickness 3.433.303.18.135.130.125LTip to Seating Plane 35.1834.6734.161.3851.3651.345DOverall Length 7.497.246.99.295.285.275E1Molded Package Width 8.267.877.62.325.310.300EShoulder to S houl der Width 0.38.015A1Base to Seating Plane 3.433.303.18.135.130.125
A2
Molded Package Thickness 4.063.813.56.160.150.140ATop to Seating Plane 2.54.100
p
Pitch 2828
n
Number of Pins MAXNOMMINMAXNOMMINDimen sion Li mits MILLIMETERSINCHES*Units
2
1
D
n
E1
c
eB
β
E
α
p
L
A2
B
B1
A
A1
Notes:
JEDEC Equivalent: MO-095
Drawing No. C04-070
* Controlling Parameter
Dimension D and E1 do not include mo ld flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0. 254 mm ) per si de.
§ Significant Characteristic
PIC18F2455/2550/4455/4550
DS39632A-page 400 Advance Information 2004 Microchip Technology Inc.
28-Lead Plasti c Small Outline (SO) – Wide, 300 mil Body (SOIC)
Foot Angle Top φ048048
1512015120
β
Mold Draft Angle Bottom 1512015120
α
Mold Draft Angle Top 0.510.420.36.020.017.014BLead Width 0.330.280.23.013.011.009
c
Lead Thickness
1.270.840.41.050.033.016LFoot Length 0.740.500.25.029.020.010hChamfer Distance 18.0817.8717.65.712.704.695DOverall Length 7.597.497.32.299.295.288E1Molded Package Width 10.6710.3410.01.420.407.394EOverall Width 0.300.200.10.012.008.004A1Standoff § 2.392.312.24.094.091.088A2Molded Package Thickness 2.642.502.36.104.099.093AOverall Height 1.27.050
p
Pitch 2828
n
Number of Pins MAXNOMMINMAXNOMMINDimensi on Lim its MILLIMETERSINCHES*Units
2
1
D
p
n
B
E
E1
L
c
β
45°
h
φ
A2
α
A
A1
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-013
Drawing No. C04-052
§ Significant Characteristic
2004 Microchip Technology Inc. Advance Information DS39632A-page 401
PIC18F2455/2550/4455/4550
40-Lead Plastic Dual In-line (P) – 600 mil Body (PDIP)
1510515105
β
Mold Draft Angle Bottom 1510515105
α
Mold Draft Angle Top 17.2716.5115.75.680.650.620eBOverall Row Spacing § 0.560.460.36.022.018.014BLower Lead Width 1.781.270.76.070.050.030B1Upp er Lea d Width 0.380.290.20.015.012.008
c
Lead Thic kness 3.433.303.05.135.130.120LTip to Seating Plane 52.4552.2651.942.0652.0582.045DOverall Length 14.2213.8413.46.560.545.530E1Molded Package Width 15.8815.2415.11.625.600.595EShoulder to Shoulder Width 0.38.015
A1
Base to Seating Plane 4.063.813.56.160.150.140A2Molded Package Thickness 4.834.454.06.190.175.160ATop to Seating Plane 2.54.100
p
Pitch 4040
n
Number of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units
A2
1
2
D
n
E1
c
β
eB
E
α
p
L
B
B1
A
A1
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-011
Drawing No. C04-016
§ Significant Characteristic
PIC18F2455/2550/4455/4550
DS39632A-page 402 Advance Information 2004 Microchip Technology Inc.
44-Lead Plastic Thin Quad Flatp ack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)
* Controlling Parameter
Notes:
Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-026
Drawing No. C04-076
1.140.890.64.045.035.025CHPin 1 Corner Chamfer
1.00.039
(F)
Footprint (Reference)
(F)
A
A1 A2
α
E
E1
#leads=n1
p
B
D1 D
n
1
2
φ
c
βL
Units INCHES MILLIMETERS*
Dim ension Limi ts MIN NOM MAX MIN NOM MAX
Numb er of Pin s n44 44
Pitch p.031 0.80
Overall Height A .039 .043 .047 1.00 1.10 1.20
Molded Package Thickness A2 .037 .039 .041 0.95 1.00 1.05
Standoff § A1 .002 .004 .006 0.05 0.10 0.15
Foot Length L .018 .024 .030 0.45 0.60 0.75
Foot A ngle φ03.5 7 03.5 7
Overall Width E .463 .472 .482 11.75 12.00 12.25
Overall Length D .463 .472 .482 11.75 12.00 12.25
Molded Package Width E1 .390 .394 .398 9.90 10.00 10.10
Molded Package Length D1 .390 .394 .398 9.90 10.00 10.10
Pins per Side n1 11 11
Lead Thickness c.004 .006 .008 0.09 0.15 0.20
Lead Width B .012 .015 .017 0.30 0.38 0.44
Mold Draft Angle Top α51015 51015
Mold Draft Angle Bottom β51015 51015
CH x 45°
§ Significant Characteristic
2004 Microchip Technology Inc. Advance Information DS39632A-page 403
PIC18F2455/2550/4455/4550
44-Lead Plasti c Quad Flat No Lead Package (ML) 8x8 mm Body (QFN)
PIC18F2455/2550/4455/4550
DS39632A-page 404 Advance Information 2004 Microchip Technology Inc.
NOTES:
2004 Microchip Technology Inc. Advance Information DS39632A-page 405
PIC18F2455/2550/4455/4550
APPENDIX A: REVISION HISTORY
Revision A (May 2004)
Original data sheet for PIC18F2455/2550/4455/4550
devices.
APPENDIX B: DEVICE
DIFFERENCES
The differences between the devices listed in this data
sheet are shown in Table B-1.
TABLE B-1: DEVICE DIFFERENCES
Features PIC18F2455 PIC18F2550 PIC18F4455 PIC18F4550
Program Memo ry (Bytes ) 24576 32768 24576 32768
Program Memo ry (Instruction s) 12288 16384 12288 16384
Interrupt Sources 19 19 20 20
I/O Ports Ports A, B, C, (E) Ports A, B, C, (E) Ports A, B, C, D, E Ports A, B, C, D, E
Capture/Compare/PWM Modules 2 2 1 1
Enhanced Capture/Compare/
PWM Modules 0011
Parallel Communications (SPP) No No Yes Yes
10-bit Analog-to-Digital Module 10 input channels 10 input channels 13 input channels 13 input channels
Packages 28-pin PDIP
28-pin SOIC 28-pin PDIP
28-pin SOIC 40-pin PDIP
44-pin TQFP
44-pin QFN
40-pin PDIP
44-pin TQFP
44-pin QFN
PIC18F2455/2550/4455/4550
DS39632A-page 406 Advance Information 2004 Microchip Technology Inc.
APPENDIX C: CONVERSION
CONSIDERATIONS
This appendix discusses the considerations for
converting from previous versions of a device to the
ones listed in this data sheet. Typically, these changes
are due to the differences in the process technology
used. An example of this type of conversion is from a
PIC16C74A to a PIC16C74B.
Not Applicable
APPENDIX D: MIGRATION FROM
BASELINE TO
ENHANCED DEVICES
This section discusses how to migrate from a Baseline
device (i.e., PIC16C5X) to an Enhanced MCU device
(i.e., PIC18FXXX).
The following are the list of modifications over the
PIC16C5X mic roc on trol ler fam il y:
Not Currently Av ail able
2004 Microchip Technology Inc. Advance Information DS39632A-page 407
PIC18F2455/2550/4455/4550
APPENDIX E: MIGRATION FROM
MID-RANGE TO
ENHANCED DEVICES
A detailed discussion of the differences between the
mid-range MCU devices (i.e., PIC16CXXX) and the
enhanced devices (i.e., PIC18FXXX) is provided in
AN716, “Migrating Designs from PIC16C74A/74B to
PIC18C442.” The changes discussed, while device
specific, are generally applicable to all mid-range to
enhanced device migrations.
This Ap plicatio n Note is availab le as L iterature Nu mber
DS00716.
APPENDIX F: MIGRATION FROM
HIGH-END TO
ENHANCED DEVICES
A detailed discussion of the migration pathway and
differences between the high-end MCU devices (i.e.,
PIC17CXXX) and the enhanced devices (i.e.,
PIC18FXXX) is provided in AN726, “PIC17CXXX to
PIC18CXXX Migration.” This Application Note is
available as Literature Number DS00726.
PIC18F2455/2550/4455/4550
DS39632A-page 408 Advance Information 2004 Microchip Technology Inc.
NOTES:
2004 Microchip Technology Inc. Advance Information DS39632A-page 409
PIC18F2455/2550/4455/4550
INDEX
A
A/D ...................................................................................253
A/D Converter Interrupt, Configuring .......................257
Acquisition Requirements ........................................258
ADCON0 Register ...................................................253
ADCON1 Register ...................................................253
ADCON2 Register ...................................................253
ADRESH Register ...........................................253, 256
ADRESL Register ....................................................253
Analog Port Pins, Configuring .................................260
Associated Registers ...............................................262
Calculating the Minimum Required
Acquisition Time ..............................................258
Configuring the Module ...........................................257
Conversion Clock (TAD) ...........................................259
Conversion Status (GO/DONE Bit) ..........................256
Conversions .............................................................261
Converter Characteristics ........................................393
Discharge ................................................................261
Operation in Power Managed Modes ......................260
Selecting and Configuring
Acquisition Time ..............................................259
Special Event Trigger (CCP2) .................................262
Special Event Trigger (ECCP) .................................150
Absolute Maximum Ratings .............................................357
AC (Timing) Characteristics .............................................374
Load Conditions for Device
Timing Specifications .......................................375
Parameter Symbology .............................................374
Temperature and Voltage Specifications .................375
Timing Conditions ....................................................375
AC Characteristics
Internal RC Accuracy ...............................................377
Access Bank ......................................................................65
Mapping with Indexed Literal
Offset Mode .......................................................77
ACKSTAT ........................................................................223
ACKSTAT Status Flag .....................................................223
ADCON0 Register ...........................................................253
GO/DONE Bit ..........................................................256
ADCON1 Register ...........................................................253
ADCON2 Register ...........................................................253
ADDFSR ..........................................................................344
ADDLW ............................................................................307
ADDULNK ........................................................................344
ADDWF ............................................................................307
ADDWFC .........................................................................308
ADRESH Register ...........................................................253
ADRESL Register ....................................................253, 256
Analog-to-Digital Converter. See A/D.
and BSR ............................................................................77
ANDLW ............................................................................308
ANDWF ............................................................................309
Assembler
MPASM Ass e mbler .................................................351
Auto-Wake-up on Sync Break Character .........................246
B
Bank Select Register (BSR) ..............................................63
Baud Rate Generator .......................................................219
Baud Rate Generator (BRG) ...........................................237
BC ....................................................................................309
BCF ..................................................................................310
BF .................................................................................... 223
BF Status Fla g ................................................................. 223
Block Diagrams
A/D .......................................................................... 256
Analog Input Model ................................................. 257
Baud Rate Generator .............................................. 219
Capture Mode Operation ......................................... 143
Comparator Analog Input Model ............................. 267
Comparator I/O Operating Modes
(Diagram) ........................................................ 264
Comparator Output ................................................. 266
Comparator Voltage Reference .............................. 270
Compare Mode Operation ....................................... 144
Device Clock ............................................................. 24
Enhanced PWM ...................................................... 151
EUSART Receive .................................................... 244
EUSART Transmit ................................................... 242
External Power-on Reset Circuit
(Slow VDD Power-up) ........................................ 45
Fail-Safe Clock Monitor ........................................... 294
Generic I/O Port ...................................................... 111
High/Low-Voltage Detect with
External Input .................................................. 274
MSSP (I2C Master Mode) ....................................... 217
MSSP (I2C Mode) ................................................... 202
MSSP (SPI Mode) ................................................... 193
On-Chip Reset Circuit ............................................... 43
PIC18F2455/2550 ..................................................... 10
PIC18F4455/4550 ..................................................... 11
PLL (HS Mode) ......................................................... 26
PWM Operation (Simplified) .................................... 146
Reads from Flash Program Memory ......................... 83
Single Comparator .................................................. 265
SPP Data Pat h ........................................................ 187
Table Read Operation ............................................... 79
Table Write Operation ............................................... 80
Table Writes to Flash Program Memory ................... 85
Timer0 in 16-Bit Mode ............................................. 126
Timer0 in 8-Bit Mode ............................................... 126
Timer1 ..................................................................... 130
Timer1 (16-Bit Read/Write Mode) ........................... 130
Timer2 ..................................................................... 136
Timer3 ..................................................................... 138
Timer3 (16-Bit Read/Write Mode) ........................... 138
USB Interrupt Logic ................................................. 177
USB Peripheral and Options ................................... 163
Voltage Reference Output
Buffer Example ................................................ 271
Watchdog Timer ...................................................... 291
BN ................................................................................... 310
BNC ................................................................................. 311
BNN ................................................................................. 311
BNOV .............................................................................. 312
BNZ ................................................................................. 312
BOR. See Brown-out Reset.
BOV ................................................................................. 315
BRA ................................................................................. 313
BRG. See Baud Rate Generator.
Brown-out Reset (BOR) .................................................... 46
Disabling in Sleep mode ........................................... 46
BSF ................................................................................. 313
BTFSC ............................................................................. 314
BTFSS ............................................................................. 314
BTG ................................................................................. 315
BZ .................................................................................... 316
PIC18F2455/2550/4455/4550
DS39632A-page 410 Advance Information 2004 Microchip Technology Inc.
C
C Compilers
MPLAB C17 .............................................................352
MPLAB C18 .............................................................352
MPLAB C30 .............................................................352
CALL ................................................................................316
CALLW ............................................................................345
Capture (CCP Module) ....................................................143
Associated Registers ...............................................145
CCP Pin Configuration .............................................143
CCPRxH:CCPRxL Registers ...................................143
Prescaler ..................................................................143
Software Interrupt ....................................................143
Timer1/Timer3 Mode Selection ................................143
Capture (ECCP Module) ..................................................150
Capture/Compare/PWM (CCP) .......................................141
Capture Mode. See Capture.
CCP Mode and Timer Resources ............................142
CCPRxH Register ....................................................142
CCPRxL Register ....................................................142
Compare Mode. See Compare.
Interaction of Two CCP Modules for
Timer Resources .............................................142
Module Configuration ...............................................142
Clock Sources ....................................................................31
Selecting the 31 kHz Source .....................................31
Selection Using OSCCON Register ...........................31
CLRF ...............................................................................317
CLRWDT .........................................................................317
Code Examples
16 x 16 Signed Multiply Routine ................................96
16 x 16 Unsigned Multiply Routine ............................96
8 x 8 Signed Multiply Routine ....................................95
8 x 8 Unsigned Multiply Routine ................................95
Changing Between Capture
Prescalers ........................................................143
Computed GOTO Using an
Offse t Value .......................................................60
Data EEPROM Read .................................................91
Data EEPROM Refresh Routine ................................92
Data EEPROM Write .................................................91
Erasing a Flash Program Memory Row .....................84
Fast Register Stack ...................................................60
How to Clear RAM (Bank 1) Using
Indirect Addressing ............................................72
Implementing a Real-Time Clock Using
a Timer1 Inte rrupt Serv ice ...............................133
Initia li z ing PORTA ....................................................111
Initia li z ing PORTB ....................................................114
Initia li z ing PORTC ...................................................117
Initia li z ing PORTD ...................................................120
Initia li z ing PORTE ....................................................123
Loading the SSPBUF (SSPSR ) Register .................196
Reading a Flash Program Memory Word ..................83
Saving Status, WREG and
BSR Registers in RAM ....................................109
Writing to Flash Program Memory ...................... 86–87
Code Protection ...............................................................279
COMF ..............................................................................318
Comparator ..................................................................... 263
Analog Input Connection
Considerations ................................................ 267
Associated Registers ............................................... 267
Configuration ........................................................... 264
Effect s of a Res et .................................................... 266
Interrupts ................................................................. 266
Operation ................................................................. 265
Operation During Sleep ........................................... 266
Outputs .................................................................... 265
Reference ................................................................ 265
External Signal ................................................ 265
Internal Signal ................................................. 265
Response Time ....................................................... 265
Comparator Specifications .............................................. 371
Comparator Voltage Reference ....................................... 269
Accuracy and Error .................................................. 270
Associated Registers ............................................... 271
Configuring .............................................................. 269
Connection Considerations ..................................... 270
Effect s of a Res et .................................................... 270
Operation During Sleep ........................................... 270
Compare (CCP Module) .................................................. 144
Associated Registers ............................................... 145
CCPRx Register ...................................................... 144
Pin Configuration ..................................................... 144
Softwar e In terrupt .................................................... 144
Special Event Trigger ................... .... .. .. .. . 139, 144, 262
Timer1/Timer3 Mode Selection ............................... 144
Compare (ECCP Module) ............................................... 150
Special Event Trigger .............................................. 150
Configuration Bits ............................................................ 280
Configuration Register Protection ................................... 299
Context Saving During Interrupts .................................... 109
Conversion Considerations ............................................. 406
CPFSEQ .......................................................................... 318
CPFSGT .......................................................................... 319
CPFSLT ........................................................................... 319
Crystal Oscillator/Ceramic Resonator ............................... 25
D
Data Addressing Modes .................................................... 72
Comparing Addressing Modes with the
Extended Instruction Set Enabled ..................... 76
Direct ......................................................................... 72
Indexed Literal Offset ................................................ 75
Indirect ....................................................................... 72
Inherent and Literal ................................................... 72
Data EEPROM Code Protection ..................................... 299
Data EEPROM Memory .................................................... 89
Associated Registers ................................................. 93
EECON1 and EECON2 Registers ............................. 89
Operation During Code-Protect ................................. 92
Protection Against Spurious Write ............................. 92
Reading ..................................................................... 91
Using ......................................................................... 92
Write Verify ................................................................ 91
Writing ....................................................................... 91
2004 Microchip Technology Inc. Advance Information DS39632A-page 411
PIC18F2455/2550/4455/4550
Data Memory .....................................................................63
Access Bank ..............................................................65
and the Extended Instruction Set ..............................75
Bank Select Register (BSR) ......................................63
General Purpose Registers .......................................65
Map for PIC18F2455/2550/4455/4550
Devices ..............................................................64
Special Function Registers ........................................66
USB RAM ..................................................................63
DAW ................................................................................320
DC and AC Characteristics
Graphs and Tables ..................................................395
DC Characteristics ...........................................................368
Power-Down and Supply Current ............................360
Supply Voltage ........................................................359
DCFSNZ ..........................................................................321
DECF ...............................................................................320
DECFSZ ..........................................................................321
Dedicated ICD/ICSP Port ................................................299
Demonstration Boards
PICDEM 1 ................................................................354
PICDEM 17 ..............................................................355
PICDEM 18R ...........................................................355
PICDEM 2 Plus ........................................................354
PICDEM 3 ................................................................354
PICDEM 4 ................................................................354
PICDEM LIN ............................................................355
PICDEM USB ..........................................................355
PICDEM.net Internet/Ethernet .................................354
Development Support ......................................................351
Device Differences ...........................................................405
Device Overview ..................................................................7
Features (table) ...........................................................9
New Core Features .....................................................7
Other Special Features ................................................8
Device Reset Tim e rs .........................................................47
Oscillator Start-up Timer (OST) .................................47
PLL Lock Time-out ....................................................47
Pow e r-up Ti mer (PWR T ) ...........................................47
Direct Addressing ..............................................................73
E
Effect on Standard PIC Instructions ...........................75, 348
Effects of Power Managed Modes on
Various Clock Sources ..............................................33
Electrical Characteristics .................................................357
Enhanced Capture/Compare/PWM (ECCP) ....................149
Associated Registers ...............................................162
Capture and Compare Modes .................................150
Capture Mode. See Capture
(ECCP Module).
Outputs and Configuration .......................................150
Pin Configurations for ECCP1 .................................150
PWM Mode. See PWM (ECCP Module).
Standard PWM Mode ..............................................150
Timer Resources .....................................................150
Enhanced PWM Mode. See PWM (ECCP Module).
Enhanced Universal Synchronous
Receiver Transmitter (USART). See EUSART.
Equations
A/D Acquisition Time ...............................................258
A/D Minimum Charging Time ..................................258
Errata ...................................................................................5
EUSART
Asynchronous Mode ............................................... 242
Associated Registers, Receive ....................... 245
Associated Registers, Transmit ...................... 243
Auto-Wake-up on Sync Break ......................... 246
Break Character Sequence ............................. 247
Receiver .......................................................... 244
Setting up 9-Bit Mode with
Address Detect ....................................... 244
Transmitter ...................................................... 242
Baud Rate Generator (BRG)
Associated Registers ...................................... 237
Auto-Baud Rate Detect ................................... 240
Baud Rate Error, Calculating .......................... 237
Baud Rates, Asynchronous
Modes ..................................................... 238
High Baud Rate Select
(BRGH Bit) .............................................. 237
Operation in Power
Managed Modes ..................................... 237
Sampling ......................................................... 237
Synchronous Master Mode ..................................... 248
Associated Registers,
Receive ................................................... 250
Associated Registers,
Transmit .................................................. 249
Reception ........................................................ 250
Transmission ................................................... 248
Synchronous Slave Mode ....................................... 251
Associated Registers,
Receive ................................................... 252
Associated Registers,
Transmit .................................................. 251
Reception ........................................................ 252
Transmission ................................................... 251
Evaluation and Programming Tools ................................ 355
Extended Instruction Set ................................................. 343
ADDFSR ................................................................. 344
ADDULNK ............................................................... 344
and Using MPLAB IDE Tools .................................. 350
CALLW .................................................................... 345
Considerations for Use ............................................ 348
MOVSF ................................................................... 345
MOVSS ................................................................... 346
PUSHL .................................................................... 346
SUBFSR .................................................................. 347
SUBULNK ............................................................... 347
Syntax ..................................................................... 343
Extern a l C l o ck In put .......................................................... 26
F
Fail-Safe Clock Monitor ........................................... 279, 294
Interrupts in Power
Managed Modes ............................................. 295
POR or Wake-up from Sleep .................................. 295
WDT During Oscillator Failure ................................ 294
Fast Register Stack ........................................................... 60
Firmware Instructions ...................................................... 301
PIC18F2455/2550/4455/4550
DS39632A-page 412 Advance Information 2004 Microchip Technology Inc.
Flash Program Memory .....................................................79
Associated Registers .................................................87
Control Registers .......................................................80
EECON1 and EECON2 .....................................80
TABLAT (Table Latch) Register ........................82
TBLPTR (Table Pointer) Register ......................82
Erase Sequence ........................................................84
Erasing .......................................................................84
Operation During Code-Protect .................................87
Reading .....................................................................83
Table Pointer
Boundaries Based on Operation .......................82
Table Pointer Boundaries ..........................................82
Table Reads and Table Writes ..................................79
Write Sequence .........................................................85
Writing To ..................................................................85
Protection Against Spurious Writes ...................87
Unexpected Termination ...................................87
Write Verify ........................................................87
FSCM. See Fail-Safe Clock Monitor.
G
GOTO ..............................................................................322
H
Hardware Multiplier ............................................................95
Introduction ................................................................95
Operation ...................................................................95
Performance Comparison ..........................................95
High/Low-Voltage Detect .................................................273
Applications .............................................................276
Associated Registers ...............................................277
Characteristics .........................................................373
Current Consumption ...............................................275
Effects of a Reset ....................................................277
Operation .................................................................274
During Sleep ....................................................277
Start-up Time ...................................................275
Setup .......................................................................275
Typical Application ...................................................276
HLVD. See High/Low-Voltage Detect.
I
I/O Por ts ...........................................................................111
I2C Mode (MSSP)
Acknowledge Sequence Timing ..............................226
Baud Rate Generator ...............................................219
Bus Collision
During a Repeated Start Condition ..................230
During a Stop Condition ..................................231
Clock Arbitration ......................................................220
Clock Stretching .......................................................212
10-Bit Slave Receive Mode
(SEN = 1) .................................................212
10-Bit Slave Transmit Mode ............................212
7-Bit Slave Receive Mode
(SEN = 1) ................................................212
7-Bit Slave Transmit Mode ..............................212
Clock Synchronization and the CKP bit
(SEN = 1) .........................................................213
Effect of a Reset ...................................................... 227
General Call Address Support ................................. 216
I2C Clock Rate w/BRG ............................................ 219
Master Mode ........................................................... 217
Operation ........................................................ 218
Reception ........................................................ 223
Repeated Start Condition Timing .................... 222
Start Condition ................................................ 221
Transmission ................................................... 223
Transmit Sequence ......................................... 218
Multi-Master Communication, Bus Collision
and Arbitration ................................................. 227
Multi-Master Mode ................................................... 227
Operation ................................................................. 206
Read/Write Bit Information (R/W Bit) ............... 206, 207
Registers ................................................................. 202
Serial Clock (RB1/AN10/INT1/SCK/SCL) ................ 207
Slave Mode ............................................................. 206
Addressing ...................................................... 206
Reception ........................................................ 207
Transmission ................................................... 207
Sleep Operation ...................................................... 227
Stop Condition Timing ............................................. 226
ID Locations ............................................................ 279, 299
INCF ................................................................................ 322
INCFSZ ........................................................................... 323
In-Circuit Debugger ......................................................... 299
In-Circuit Serial Programming (ICSP) .....................279, 299
Indexed Literal Offset Addressing
and Standard PIC18 Instructions ............................ 348
Indexed Literal Offset Mode ...... ....... ...... ...... ...... . 75, 77, 348
Indirect Addressing ............................................................ 73
INFSNZ ........................................................................... 323
Initialization Conditions for all Registers ......................51–55
Instruction Cycle ................................................................ 61
Clocking Scheme ...................................................... 61
Instruction Flow/Pipelining ................................................. 61
Instruction Format ........................................................... 303
Instruction Set ................................................................. 301
ADDLW ................................................................... 307
ADDWF ................................................................... 307
ADDWF (Indexed Literal Offset mode) .................... 349
ADDWFC ................................................................. 308
ANDLW ................................................................... 308
ANDWF ................................................................... 309
BC ........................................................................... 309
BCF ......................................................................... 310
BN ........................................................................... 310
BNC ......................................................................... 311
BNN ......................................................................... 311
BNOV ...................................................................... 312
BNZ ......................................................................... 312
BOV ......................................................................... 315
BRA ......................................................................... 313
BSF ......................................................................... 313
BSF (Indexed Literal Offset mode) .......................... 349
BTFSC ..................................................................... 314
BTFSS ..................................................................... 314
BTG ......................................................................... 315
BZ ............................................................................ 316
2004 Microchip Technology Inc. Advance Information DS39632A-page 413
PIC18F2455/2550/4455/4550
CALL ........................................................................316
CLRF .......................................................................317
CLRWDT .................................................................317
COMF ......................................................................318
CPFSEQ ..................................................................318
CPFSGT ..................................................................319
CPFSLT ...................................................................319
DAW ........................................................................320
DCFSNZ ..................................................................321
DECF .......................................................................320
DECFSZ ..................................................................321
GOTO ......................................................................322
INCF ........................................................................322
INCFSZ ....................................................................323
INFSNZ ....................................................................323
IORLW .....................................................................324
IORWF .....................................................................324
LFSR .......................................................................325
MOVF ......................................................................325
MOVFF ....................................................................326
MOVLB ....................................................................326
MOVLW ...................................................................327
MOVWF ...................................................................327
MULLW ....................................................................328
MULWF ...................................................................328
NEGF .......................................................................329
NOP .........................................................................329
POP .........................................................................330
PUSH .......................................................................330
RCALL .....................................................................331
RESET .....................................................................331
RETFIE ....................................................................332
RETLW ....................................................................332
RETURN ..................................................................333
RLCF .......................................................................333
RLNCF .....................................................................334
RRCF .......................................................................334
RRNCF ....................................................................335
SETF .......................................................................335
SETF (Indexed Literal Offset mode) ........................349
SLEEP .....................................................................336
SUBFWB .................................................................336
SUBLW ....................................................................337
SUBWF ....................................................................337
SUBWFB .................................................................338
SWAPF ....................................................................338
TBLRD .....................................................................339
TBLWT ....................................................................340
TSTFSZ ...................................................................341
XORLW ...................................................................341
XORWF ...................................................................342
Instructions in Program Memory ........................................62
Two-Word Instruc tions ...............................................62
INTCON Register
RBIF Bit ...................................................................114
INTCON Registers .............................................................99
Inter-Integrated Circuit. See I2C.
Internal Oscillator Block .....................................................27
Adjustment .................................................................27
INTHS, INTXT, INTCKO and INTIO Modes ..............27
OSCTUNE Register ...................................................27
Internal RC Oscillator
Use with WDT ..........................................................291
Interrupt Sources ............................................................. 279
A/D Conversion Complete ....................................... 257
Capture Complete (CCP) ........................................ 143
Compare Complete (CCP) ...................................... 144
Interrupt-on-Change (RB7:RB4) ............................. 114
INTn Pin .................................................................. 109
PORTB, Interrupt-on-Change ................................. 109
TMR0 ...................................................................... 109
TMR0 Overflow ....................................................... 127
TMR2 to PR 2 Match (PWM ) . .......................... 146, 151
TMR3 Overflow ........................................ 129, 137, 139
Interrupts ........................................................................... 97
Logic (diagram) ......................................................... 98
USB ........................................................................... 97
Interrupts, Flag Bits
Interrupt-on-Change (RB7:RB4) Flag
(RBIF Bit) ........................................................ 114
INTOSC Frequency Drift ................................................... 27
INTO SC, INT R C . See Internal Oscillator Block.
IORLW ............................................................................. 324
IORWF ............................................................................ 324
IPR Registers .................................................................. 106
L
LFSR ............................................................................... 325
Look-up Tables .................................................................. 60
Low-Voltage ICSP Programm ing
See Single-Supply ICS P Progra mm ing.
M
Master Clear Reset (MCLR) .............................................. 45
Master Synchronous Serial Port (MSSP). See MSSP.
Memory Organization ........................................................ 57
Data Memory ............................................................. 63
Program Memory ...................................................... 57
Memory Programm ing Re quirements ............................. 370
Migration from Baseline to
Enhanced Devices .................................................. 406
Migration from High-End to
Enhanced Devices .................................................. 407
Migration from Mid-Range to
Enhanced Devices .................................................. 407
MOVF .............................................................................. 325
MOVFF ............................................................................ 326
MOVLB ............................................................................ 326
MOVLW ........................................................................... 327
MOVSF ............................................................................ 345
MOVSS ........................................................................... 346
MOVWF ........................................................................... 327
MPLAB ASM30 Assembler,
Linker, Librarian ...................................................... 352
MPLAB ICD 2 In-Circuit Debugger .................................. 353
MPLAB ICE 2000 High-Perf orm ance
Universal In-Circuit Emulator .................................. 353
MPLAB ICE 4000 High-Perf orm ance
Universal In-Circuit Emulator .................................. 353
MPLAB Integrated Development
Environment Software ............................................. 351
MPLAB PM3 Device Pr ogramm er ................................... 353
MPLINK Object Linker/
MPLIB Object Librarian ........................................... 352
PIC18F2455/2550/4455/4550
DS39632A-page 414 Advance Information 2004 Microchip Technology Inc.
MSSP
ACK Pulse .......................................................206, 207
Control Registers (general) ......................................193
I2C Mode. See I2C Mode.
Module Overview .....................................................193
SPI Master/Slave Connection ..................................197
SPI Mode. See SPI Mode.
SSPBUF ..................................................................198
SSPSR .....................................................................198
MULLW ............................................................................328
MULWF ............................................................................328
N
NEGF ...............................................................................329
NOP .................................................................................329
O
Opcode Field Descriptions ...............................................302
OPTION_REG Register
PSA Bit ....................................................................127
T0CS Bit ..................................................................126
T0PS 2:T0PS0 Bits ...................................................127
T0SE Bit ...................................................................126
Oscillator Configuration .....................................................23
EC ..............................................................................23
ECIO ..........................................................................23
ECPIO ........................................................................23
ECPLL .......................................................................23
HS ..............................................................................23
HSPLL .......................................................................23
INTCKO .....................................................................23
Internal Oscillator Block .............................................27
INTHS ........................................................................23
INTIO .........................................................................23
INTXT ........................................................................23
Oscillator Modes and USB Operation ........................23
XT ..............................................................................23
XTPLL ........................................................................23
Oscillator Selection ..........................................................279
Oscillator Settings for USB ................................................29
Oscillator Start-up Timer (OST) .................................. 33, 47
Oscillator Switching ...........................................................31
Oscillator Transitions .........................................................32
Oscillator, Timer1 .............................................................139
Oscillator, Timer3 .................................................... 129, 137
P
Packaging Information .....................................................397
Details ......................................................................399
Marking ....................................................................397
PICkit 1 Flash Starter Kit .................................................355
PICSTART Plus Developm ent Programm e r ....................354
PIE Registers ...................................................................104
Pin Functions
MCLR/VPP/RE3 ...................................................12, 16
NC/ICCK/ICPGC ........................................................ 21
NC/ICDT/ICPGD ........................................................21
NC/ICPORTS .............................................................21
NC/ICRST/ICVPP .......................................................21
OSC1/CLKI ..........................................................12, 16
OSC2/CLKO/RA6 ................................................12, 16
RA0/AN0 .............................................................. 13, 17
RA1/AN1 .............................................................. 13, 17
RA2/AN2/VREF-/CVREF ........................................ 13, 17
RA3/AN3/VREF+ ...................................................13, 17
RA4/T0CKI/C1OUT/RCV .....................................13, 17
RA5/AN4/SS/HLVDIN/C2OUT ............................. 13, 17
RB0/AN12/INT0/FLT0/SDI/SDA .......................... 14, 18
RB1/AN10/INT1/SCK/SCL ................................... 14, 18
RB2/AN8/INT2/VMO ............................................ 14, 18
RB3/AN9/CCP2/VPO ........................................... 14, 18
RB4/AN11/KBI0 .........................................................14
RB4/AN11/KBI0/CSSPP ............................................ 18
RB5/KBI1/PGM .................................................... 14, 18
RB6/KBI2/PGC .................................................... 14, 18
RB7/KBI3/PGD .................................................... 14, 18
RC0/T1OSO/T13CKI ........................................... 15, 19
RC1/T1OSI/CCP2/UOE ....................................... 15, 19
RC2/CCP1 .................................................................15
RC2/CCP1/P1A ......................................................... 19
RC4/D-/VM ................................................................ 19
RC5/D+/VP .......................................................... 15, 19
RC6/TX/CK .......................................................... 15, 19
RC7/RX/DT/SDO ................................................. 15, 19
RD0/SPP0 ................................................................. 20
RD1/SPP1 ................................................................. 20
RD2/SPP2 ................................................................. 20
RD3/SPP3 ................................................................. 20
RD4/SPP4 ................................................................. 20
RD5/SPP5/P1B ......................................................... 20
RD6/SPP6/P1C ......................................................... 20
RD7/SPP7/P1D ......................................................... 20
RE0/AN5/CK1SPP .................................................... 21
RE1/AN6/CK2SPP .................................................... 21
RE2/AN7/OESPP ...................................................... 21
VDD ...................................................................... 15, 21
VSS ...................................................................... 15, 21
VUSB .................................................................... 15, 21
Pinout I/O Descriptions
PIC18F2455/2550 ..................................................... 12
PIC18F4455/4550 ..................................................... 16
PIR Registers .................................................................. 102
PLL Frequency Multiplier ................................................... 26
HSPLL, XTPLL, ECPLL and ECPI O
Oscillator Modes ............................................... 26
PLL Lock Time-out ............................................................ 47
POP ................................................................................. 330
POR. See Power-on Reset.
PORTA
Associated Registers ............................................... 113
I/O Sum ma ry ........................................................... 112
LATA Register ......................................................... 111
PORTA Register ...................................................... 111
TRISA Register ....................................................... 111
PORTB
Associated Registers ............................................... 116
I/O Sum ma ry ........................................................... 115
LATB Register ......................................................... 114
PORTB Register ...................................................... 114
RB1/AN10/INT1/SCK/SCL Pin ................................ 207
RB7:RB4 Interrupt-on-Change Flag
(RBIF Bit) ........................................................ 114
TRISB Register ....................................................... 114
PORTC
Associated Registers ............................................... 119
I/O Sum ma ry ........................................................... 118
LATC Register ......................................................... 117
PORTC Register ..................................................... 117
TRISC Register ....................................................... 117
2004 Microchip Technology Inc. Advance Information DS39632A-page 415
PIC18F2455/2550/4455/4550
PORTD
Associated Registers ...............................................122
I/O Sum ma ry ...........................................................121
LATD Register .........................................................120
PORTD Register ......................................................120
TRISD Register .......................................................120
PORTE
Associated Registers ...............................................124
I/O Sum ma ry ...........................................................124
LATE Register .........................................................123
PORTE Register ......................................................123
TRISE Register ........................................................123
Postscaler, WDT
Assignment (PSA Bit) ..............................................127
Rate Select (T0PS2:T0PS0 Bits) .............................127
Switching Between Timer0 and WDT ......................127
Power Managed Modes .....................................................35
and A/D Operation ...................................................260
and EUSART Operation ..........................................237
and Multiple Sleep Commands ..................................36
Clock Transitions and Status Indicators ....................36
Effects on Clock Sources ..........................................33
Entering .....................................................................35
Exiting Idle and Sleep Modes ....................................41
by Interrupt ........................................................41
by Reset ............................................................41
by WDT Time-out ..............................................41
Without an Oscillator Start-up Delay .................42
Idle Modes .................................................................39
PRI_IDLE ...........................................................40
RC_IDLE ...........................................................41
SEC_IDLE .........................................................40
Run Modes ................................................................36
PRI_RUN ...........................................................36
RC_RUN ............................................................37
SEC_RUN .........................................................36
Selecting ....................................................................35
Sleep Mode ...............................................................39
Summary (table) ........................................................35
Power-on Reset (POR) ......................................................45
Oscillator Start-up Timer (OST) .................................47
Pow e r-up Ti mer (PWR T ) ...........................................47
Time-out Sequence ...................................................47
Power-up Delays ...............................................................33
Pow e r-up Ti mer (PWR T ) .............................................33, 47
Prescaler
Timer2 .....................................................................152
Prescaler, Timer0 ............................................................127
Assignment (PSA Bit) ..............................................127
Rate Select (T0PS2:T0PS0 Bits) .............................127
Switching Between Timer0 and WDT ......................127
Prescaler, Timer2 ............................................................147
PRI_IDLE Mode .................................................................40
PRI_RUN Mode .................................................................36
PRO MATE II Universal Device Programmer ..................353
Program Counter ...............................................................58
PCL, PCH and PCU Registers ..................................58
PCLATH and PCLATU Registers ..............................58
Program Mem ory
and the Extended Instruction Set ..............................75
Code Protection .......................................................297
Interrupt Vector ..........................................................57
Map and Stack (diagram) ..........................................57
Reset Vector ..............................................................57
Program Verificat ion and Code Protection ...................... 296
Associated Registers .............................................. 296
Programm ing, Device Ins tr uctions .................................. 301
Pulse-Width Modulation. See PWM (CCP Module)
and PWM (ECCP Module).
PUSH .............................................................................. 330
PUSH and POP In stru ctions ............................................. 59
PUSHL ............................................................................ 346
PWM (CCP Module)
Associated Registers .............................................. 148
Auto-Shutdown (CCP1 only) ................................... 147
Duty Cycle ............................................................... 146
Example Frequencies/Resolution s .......................... 147
Period ...................................................................... 146
Setup for PWM Operation ....................................... 147
TMR2 to PR 2 M atch . ....................................... 146, 151
PWM (ECCP Module) ..................................................... 151
CCPR1H:CCPR1L Registers .................................. 151
Direction Change in Full-Bridge
Output Mode ................................................... 156
Duty Cycle ............................................................... 152
Effect s of a Res et .................................................... 161
Enhanced PWM Auto-Shutdown ............................. 158
Example Frequencies/Resolution s .......................... 152
Full-Bridge Application Example ............................. 156
Full-Bridge Mode ..................................................... 155
Half-Bridge Mode .................................................... 154
Half-Bridge Output Mode
Applications Example ...................................... 154
Output Configurations ............................................. 152
Output Relationships (Active-High) ......................... 153
Output Relationships (Active-Low) .......................... 153
Period ...................................................................... 151
Programmable Dead-Band Delay ........................... 158
Setup for Operation ................................................. 161
Start-up Considerations .......................................... 160
Q
Q Clock .................................................................... 147, 152
R
RAM. See Data Memory.
RC_IDLE Mode ................................................................. 41
RC_RUN Mode ................................................................. 37
RC4/D-/VM ........................................................................ 15
RCALL ............................................................................. 331
RCON Register
Bit Status During Initializati on ................................... 50
Register File ...................................................................... 65
Register File Summary ................................................67–70
Registers
ADCON0 (A/D Control 0) ........................................ 253
ADCON1 (A/D Control 1) ........................................ 254
ADCON2 (A/D Control 2) ........................................ 255
BAUDCON (Baud Rate Control) ............................. 236
BDnSTAT (Buffer Desc riptor n Status,
CPU Mode) ..................................................... 173
BDnSTAT (Buffer Desc riptor n Status,
SIE Mode) ....................................................... 174
CCP1CON (Enhanced CCP Control 1) ................... 149
CCPxCON (Standard Capture/Compare/
PWM Control) .................................................. 141
CMCON (Comparator Control) ................................ 263
CONFIG1H (Configuration 1 High) ......................... 282
PIC18F2455/2550/4455/4550
DS39632A-page 416 Advance Information 2004 Microchip Technology Inc.
CONFIG1L (Configuration 1 Low) ...........................281
CONFIG2H (Configuration 2 High) ..........................284
CONFIG2L (Configuration 2 Low) ...........................283
CONFIG3H (Configuration 3 High) ..........................285
CONFIG4L (Configuration 4 Low) ...........................286
CONFIG5H (Configuration 5 High) ..........................287
CONFIG5L (Configuration 5 Low) ...........................287
CONFIG6H (Configuration 6 High) ..........................288
CONFIG6L (Configuration 6 Low) ...........................288
CONFIG7H (Configuration 7 High) ..........................289
CONFIG7L (Configuration 7 Low) ...........................289
CVRCON (Comparator Voltage
Reference Control) ..........................................269
Device ID 1 ..............................................................290
Device ID 2 ..............................................................290
ECCP1AS (ECCP
Auto-Shutdown Control) ..................................159
ECCP1DEL (PWM Configuration) ...........................158
EECON1 (Data EEPROM
Control 1) .....................................................81, 90
HLVDCON (HLVD Control) ......................................273
INTCON (Interrupt Control) ........................................99
INTCON2 (Interrupt Control 2) .................................100
INTCON3 (Interrupt Control 3) .................................101
IPR1 (Peripheral Interrupt Priority 1) .......................106
IPR2 (Peripheral Interrupt Priority 2) .......................107
OSCCON (Oscillator Control) ....................................32
OSCTUNE (Oscillator Tuning) ...................................28
PIE1 (Peripheral Interrupt Enable 1) ........................104
PIE2 (Peripheral Interrupt Enable 2) ........................105
PIR1 (Peripheral Interrupt Request
(Flag) 1) ...........................................................102
PIR2 (Peripheral Interrupt Request
(Flag) 2) ...........................................................103
PORTE ....................................................................123
RCON (Reset Control) .......................................44, 108
RCSTA (Receive Status and Control) .....................235
SPPCFG (SSP Configuration) .................................188
SPPCON (SP P C ontr o l) ..........................................187
SPPEPS (S PP Endpoint Address
and Status) ......................................................191
SSPCON1 (MS SP Control 1, I2C Mode) .................204
SSPCON1 (MS SP Control 1, SPI Mode) .................195
SSPCON2 (MS SP Control 2, I2C Mode) .................205
SSPSTAT (MSSP Status, I2C Mode) ......................203
SSPSTAT (MSSP Status, SPI Mode) ......................194
Status .........................................................................71
STKPTR (Stack Pointer) ............................................59
T0CON (Timer0 Control) .........................................125
T1CON (Timer 1 Control) ........................................129
T2CON (Timer2 Control) .........................................135
T3CON (Timer3 Control) .........................................137
TXSTA (Transmit Status and Control) .....................234
UCFG (USB Configuration) .....................................166
UCON (USB Control) ...............................................164
UEIE (USB Error Interrupt Enable) ..........................181
UEIR (USB Error Interrupt Status) ...........................180
UEPn (USB Endpoint n Control) ..............................169
UIE (USB Interrupt Enable) .....................................179
UIR (USB Interrupt Status) ......................................178
USTAT (USB Status) ...............................................168
WDTCON (Watchdog Tim er Contro l) ......................292
RESET ............................................................................ 331
Reset State of Registers ................................................... 50
Resets ....................................................................... 43, 279
Brown-out Reset (BOR) .......................................... 279
Oscillator Start-up Timer (OST) ............................... 279
Power-on Reset (POR) ........................................... 279
Power-up Timer (PW RT ) ......................................... 279
RETFIE ............................................................................ 332
RETLW ............................................................................ 332
RETURN ......................................................................... 333
Return Address Stack ....................................................... 58
and Associated Registers .......................................... 58
Return Stack Pointer (STKPTR) ........................................ 59
Revision History .............................................................. 405
RLCF ............................................................................... 333
RLNCF ............................................................................ 334
RRCF .............................................................................. 334
RRNCF ............................................................................ 335
S
SCK ................................................................................. 193
SDI .................................................................................. 193
SDO ................................................................................. 193
SEC_IDLE Mode ............................................................... 40
SEC_RUN Mode ............................................................... 36
Serial Clock, SCK ............................................................ 193
Serial D a ta In (SDI) ......................................................... 193
Serial Data Out (SDO) ..................................................... 193
Serial Peripheral Interface. See SPI Mode.
SETF ............................................................................... 335
Slave Select (SS) ............................................................ 193
SLEEP ............................................................................. 336
Sleep
OSC1 and OSC2 Pin States ..................................... 33
Sleep Mode ....................................................................... 39
Software Enabled BOR ..................................................... 46
Software Simulator (MPLAB SIM) ................................... 352
Software Simulator (MPLAB SIM30) ............................... 352
Special Event Trigger. See Compare (ECCP Mode).
Special Event Trigger. See Compare (ECCP Module).
Special Features of the CPU ........................................... 279
Special Function Registers ................................................ 66
Map ........................................................................... 66
Special ICPORT Features ............................................... 299
SPI Mode (MSS P)
Associated Registers ............................................... 201
Bus Mode Compatibility ........................................... 201
Effect s of a Res et .................................................... 201
Enabling SPI I/O ...................................................... 197
Master Mode ........................................................... 198
Master/Slave Connection ........................................ 197
Operation ................................................................. 196
Operation in Power Managed Modes ...................... 201
Serial Clock ............................................................. 193
Serial D a ta In ........................................................... 193
Serial Data Out ........................................................ 193
Slave Mode ............................................................. 199
Slave Select ............................................................ 193
Slave Select Synchronization .................................. 199
SPI Clock ................................................................. 198
Typical Connection .................................................. 197
SPP. See Streaming Parallel Port. .................................. 187
2004 Microchip Technology Inc. Advance Information DS39632A-page 417
PIC18F2455/2550/4455/4550
SS ....................................................................................193
SSPOV ............................................................................223
SSPOV St atus Flag .........................................................223
SSPSTAT Register
R/W Bit ............................................................206, 207
Stack Full/Underflow Resets ..............................................60
Standard Instructions .......................................................301
Status Register ..................................................................71
Streaming Parallel Port ....................................................187
Associated Registers ...............................................192
Clocking Data ..........................................................188
Configuration ...........................................................187
Internal Pull-ups .......................................................188
Interrupts .................................................................190
Reading from (Microcontroller Mode) ......................191
Setup for Microcontroller Control .............................190
Setup for USB Control .............................................190
Transfer of Data Between SIE and SPP ..................190
Wait States ..............................................................188
Writing to (Microcontroller Mode) ............................190
SUBFSR ..........................................................................347
SUBFWB .........................................................................336
SUBLW ............................................................................337
SUBULNK ........................................................................347
SUBWF ............................................................................337
SUBWFB .........................................................................338
SWAPF ............................................................................338
T
Table Pointer Operations (table) ........................................82
Table Reads/Table Writes .................................................60
TBLRD .............................................................................339
TBLWT .............................................................................340
Time-out in Various Situations (table) ................................47
Timer0 ..............................................................................125
16-Bit Mode Timer Reads and Writes .....................126
Associated Registers ...............................................127
Clock Source Edge Select (T0SE Bit) .....................126
Clock Source Select (T0CS Bit) .............................. 126
Operation .................................................................126
Overflow Interru p t ....................................................127
Prescaler. See Pres cale r, Timer0.
Timer1 ..............................................................................129
16-Bit Read/Write Mode ..........................................131
Associated Registers ...............................................133
Interrupt ...................................................................132
Operation .................................................................130
Oscillator ..................................................................131
Layout Considerations .....................................132
Low-Power Option ...........................................131
Using Timer1 as a Clock Source .....................131
Resetting, Using a Special Event
Trigger Output (CCP) ......................................132
Special Event Trigger (ECCP) .................................150
Use as a Real-Time Clock .......................................132
Timer2 ..............................................................................135
Associated Registers ...............................................136
Interrupt ...................................................................136
Operation .................................................................135
Output ......................................................................136
PR2 Register ...................................................146, 151
TMR2 to PR2 Match Interrupt ..........................146, 151
Timer3 ............................................................................. 137
16-Bit Read/Write Mode .......................................... 139
Associated Registers .............................................. 139
Operation ................................................................ 138
Oscillator ........... .. .. .... .. .. ..... .. .. .... .. .. .. .. ..... 129, 137, 139
Overflow Interrupt ............... .. .... .. .. .. .... ..... 129, 137, 139
Special Event Trigger (CCP) . .................................. 139
TMR3H Register .............................................. 129, 137
TMR3L Register .............................................. 129, 137
Timing Diagrams
A/D Conversion ....................................................... 394
Acknowledge Sequence .......................................... 226
Asynchronous Recept ion ........................................ 245
Asynchronous Tra nsmis sion ................................... 243
Asynchronous Tran smis sion
(Back to Back) ................................................. 243
Automatic Baud Rate Calculation ........................... 241
Auto-Wake-up Bit (WUE) During
Normal Operation ............................................ 246
Auto-Wake-up Bit (WUE) During Sleep .................. 246
Baud Rate Generator with Clock Arbitration ........... 220
BRG Overflow Sequence ........................................ 241
BRG Reset Due to SDA Arbitration
During Start Condition ..................................... 229
Brown-out Reset (BOR) .......................................... 379
Bus Collision During a Repeated
Start Condition (Case 1) .................................. 230
Bus Collision During a Repeated
Start Condition (Case 2) .................................. 230
Bus Collision During a Start
Condition (SCL = 0) ........................................ 229
Bus Collision During a Start
Condition (SDA only) ....................................... 228
Bus Collision During a Stop
Condition (Case 1) .......................................... 231
Bus Collision During a Stop
Condition (Case 2) .......................................... 231
Bus Collision for Transmit and
Acknowledge ................................................... 227
Capture/Compare/PWM (CCP) ............................... 381
CLKO and I/O .......................................................... 378
Clock Synchronization ............................................. 213
Clock/Instr u ction Cyc le .............................................. 61
Example SPI Master Mode (CK E = 0) ..................... 382
Example SPI Master Mode (CK E = 1) ..................... 383
Example SPI Slave Mode (CKE = 0) ....................... 384
Example SPI Slave Mode (CKE = 1) ....................... 385
External Clock (All Modes except PLL) ................... 376
Fail-Safe Clock Monitor ........................................... 295
First Start Bi t Timing ................................................ 221
Full-Bridge PWM Output ......................................... 155
Half-Bridge PWM Output ......................................... 154
High/Low-Voltage Detect Characteristics ................ 373
High-Voltage Detect (VDIRMAG = 1) ...................... 276
I2C Bus Data ........................................................... 386
I2C Bus Start/Stop Bits ............................................ 386
I2C Master Mode (7 or 10-Bit
Transmission) .................................................. 224
I2C Master Mode (7-Bit Reception) ......................... 225
I2C Slave Mode (10-Bit Reception,
SEN = 0) ......................................................... 210
I2C Slave Mode (10-Bit Reception,
SEN = 1) ......................................................... 215
PIC18F2455/2550/4455/4550
DS39632A-page 418 Advance Information 2004 Microchip Technology Inc.
I2C Slave Mode (10-Bit Transmission) ....................211
I2C Slave Mode (7-Bit Reception,
SEN = 0) ..........................................................208
I2C Slave Mode (7-Bit Reception,
SEN = 1) ..........................................................214
I2C Slave Mode (7-Bit Transmission) ......................209
I2C Slave Mode General Call Address
Sequence (7 or 10-Bit Address Mode) ............216
Low-Voltage Detect (VDIRMAG = 0) .......................275
Master SSP I2C Bus Data ........................................388
Master SSP I2C Bus Start /S top Bits ........................388
PWM Auto-Shutdown (PRSEN = 0,
Auto-Restart Disabled) ....................................160
PWM Auto-Shutdown (PRSEN = 1,
Auto-Restart Enabled) .....................................160
PWM Direction Change ...........................................157
PWM Direction Change at Near
100% Duty Cycle .............................................157
PWM Output ............................................................146
Repeat Start Condition ............................................222
Reset, Watchdog Timer (WDT),
Oscillator Start-up Timer (OST) and
Pow e r-up Ti mer (PWR T ) .................................379
Send Break Character Sequence ............................247
Slave Synchronization .............................................199
Slow Rise Time (MCLR Tied to VDD,
VDD Rise > TPWRT) ............................................49
SPI Mode (Master Mode) .........................................198
SPI Mode (Slave Mode with CKE = 0) .....................200
SPI Mode (Slave Mode with CKE = 1) .....................200
SPP Write Address and Data
(USB Mode, 4 Wait States) .............................189
SPP Write Address, Read Data
(USB Mode, 4 Wait States) .............................189
SPP Write Address, Write and
Read Data (No Wait States) ............................189
Stop Condition Receive or
Transmit Mode .................................................226
Streaming Parallel Port (PIC18F4455/4550) ...........392
Synchronous Reception
(Master Mode, SREN) .....................................250
Synchronous Transmission .....................................248
Synchronous Transmission
(Through TXEN) ..............................................249
Time-out Sequence on POR w/
PLL Enabled (MCLR Tied to VDD) .....................49
Time-out Sequence on Power-up
(MCLR Not Tied to VDD), Case 1 ......................48
Time-out Sequence on Power-up
(MCLR Not Tied to VDD), Case 2 ......................48
Time-out Sequence on Power-up
(MCLR Tied to VDD, VDD Rise TPWRT) ..............48
Timer0 and Timer1 External Clock ..........................380
Transition for Entry to SEC_RUN Mode ....................37
Transition for Entry to Sleep Mode ............................39
Transition for Two-Speed Start-up
(INTOSC to HSP L L ) ........................................293
Transition for Wake from Sleep (HSPLL) ..................39
Transition from RC_RUN Mode
to PRI_RUN Mode ............................................ 38
Transition from SEC_RUN Mode
to PRI_RUN Mode (HSPLL) .............................. 37
Transition Timing for Entry to Idle Mode ................... 40
Transition Timing for Wake from
Idle to Run Mode .............................................. 40
Transition to RC_RUN Mode ..................................... 38
USART Synchronous Receive
(Master/Slave) ................................................. 390
USART Synchronous Transmission
(Master/Slave) ................................................. 390
Timing Diagrams and Specifications ............................... 376
A/D Conversion Requirements ................................ 394
Capture/Compare/PWM Requirements ................... 381
CLKO and I/O Requirements .................................. 378
Example SPI Mode Requireme nts
(Master Mode, CKE = 0) ................................. 382
Example SPI Mode Requireme nts
(Master Mode, CKE = 1) ................................. 383
Example SPI Mode Requireme nts
(Slave Mode, CKE = 0) ................................... 384
Example SPI Mode Requireme nts
(Slave Mode, CKE = 1) ................................... 385
External Clock Requirements .................................. 376
I2C Bus Data Requirements (Slave Mode) .............. 387
I2C Bus Start/Stop Bits Requirements ..................... 386
Master SSP I 2C Bus Data Requirements ................ 389
Master SSP I 2C Bus Start/S top
Bits Requirements ........................................... 388
Parallel Slave Port Requirements
(PIC18F4455/4550) ......................................... 392
PLL Clock ................................................................ 377
Reset, Watchdog Timer,
Oscillator Start-up Timer,
Power-up Timer and
Brown-out Reset Requirements ...................... 379
Timer0 and Timer1 External
Clock Requirements ........................................ 380
USART Synchronous Receive
Requirements .................................................. 390
USART Synchronous Transmission
Requirements .................................................. 390
USB Full Speed Requirements ............................... 391
USB Low-Speed Requirements .............................. 391
USB Signal Timing .................................................. 391
Top-of-Stack Ac cess ......................................................... 58
TQFP Packages and Special Features ........................... 299
TSTFSZ ........................................................................... 341
Two-Speed Start-up ................................................ 279, 293
Two-Word Instructions
Example Cases ......................................................... 62
TXSTA Register
BRGH Bit ................................................................. 237
2004 Microchip Technology Inc. Advance Information DS39632A-page 419
PIC18F2455/2550/4455/4550
U
Universal Serial Bus
Address Register (UADDR) .....................................170
and Streaming Parallel Port .....................................182
Associated Registers ...............................................183
Buffer Descriptor Table ............................................171
Buffer Descriptors ....................................................171
Address Validation ...........................................174
Assignment in Different
Buffering Modes ......................................176
BDSTAT Register (CPU Mode) .......................172
BDSTAT Register (SIE Mod e) .........................174
Byte Count .......................................................174
Example ...........................................................171
Memory Map ....................................................175
Ownership .......................................................171
Ping-Pong Buffering ........................................175
Register Summary ...........................................176
Status and Configuration .................................171
Bus Power Only Mode .............................................182
Class Specifications and Drivers .............................185
Descriptors ..............................................................185
Dual Power with Self-Power
Dominance Mode ............................................182
Endpoint Control ......................................................169
Enumeration ............................................................185
External Transceiver ................................................165
Eye Pattern Test Enable ..........................................167
Firmware and Drivers ..............................................183
Frame Number Registers ........................................170
Frames ....................................................................184
Internal Transceiver .................................................165
Internal Voltage Regulator .......................................167
Interrupts .................................................................177
and USB Transactions .....................................177
Interrupt Logic ..................................................177
Layered Framework .................................................184
Oscillator Requirements ..........................................183
Output Enable Monitor .............................................167
Overview ..................................................................184
Ping-Pong Buffer Configuration ...............................167
Power ......................................................................184
Power Modes ...........................................................182
Pull-up Resistors .....................................................167
RAM .........................................................................170
Memory Map ....................................................170
Self-Power Only Mode .............................................182
Speed ......................................................................185
Status and Control ...................................................164
Transfer Types ........................................................184
UFRMH:UFRML Registers ......................................170
USB Me mory .............................................................63
USB RAM ..........................................................................63
USB. See Universal Serial Bus.
Universal Serial Bus
Overview ..................................................................163
V
Voltage Reference Specifications ................................... 371
W
Watchdog Timer (WDT) .......................................... 279, 291
Associ a te d Re g i sters ...................... ....... ...... ...... ...... 292
Control Reg i s te r ..... ...... ....... ...... ...... ....... ...... ............ 291
During Oscillator Failure .......................................... 294
Programming Considerations .................................. 291
WCOL ...................................................... 221, 22 2, 223, 226
WCOL Status Flag ................................... 221, 22 2, 223, 226
WWW, On-Line Support ...................................................... 5
X
XORLW ........................................................................... 341
XORWF ........................................................................... 342
PIC18F2455/2550/4455/4550
DS39632A-page 420 Advance Information 2004 Microchip Technology Inc.
NOTES:
2004 Microchip Technology Inc. Advance Information DS39632A-page 421
PIC18F2455/2550/4455/4550
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042003
PIC18F2455/2550/4455/4550
DS39632A-page 422 Advance Information 2004 Microchip Technology Inc.
READER RESPONSE
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DS39632APIC18F2455/2550/4455/4550
1. W hat are the best features of thi s document ?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
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7. How would you improve this document?
2004 Microchip Technology Inc. Advance Information DS39632A-page 423
PIC18F2455/2550/4455/4550
PIC18F2455/2550/4455/4550 PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. X/XX XXX
PatternPackageTemperature
Range
Device
Device PIC18F2455/2550(1), PIC18F4455/4550(1),
PIC18F2455/2550T(2), PIC18F4455/4550T(2);
VDD range 4.2V to 5.5V
PIC18LF2455/2550(1), PIC1 8L F 44 55 / 45 5 0(1),
PIC18LF2455/2550T(2), PIC18LF4455/4550T(2);
VDD range 2.0V to 5.5V
Temper atu re Rang e I = -40°C to +85°C (Industrial)
E= -40°C to +125°C (Extended)
Package PT = TQFP (Thin Quad Flatpack)
SO = SOIC
SP = Skinny Plastic DIP
P=PDIP
M=QFN
Pattern QTP, SQTP, Code or Special Requirements
(blank oth erwi se )
Examples:
a) PIC18LF4550-I/P 301 = Industrial temp., PDIP
package, Extended VDD limits, QTP pattern
#301.
b) PIC18LF2455-I/SO = Industrial temp., SOIC
package, Extended VDD limits.
c) PIC18F4455-I/P = Industrial temp., PDIP
package, normal VDD limits.
Note 1: F = Standard Voltage Range
LF = Wide Voltage Range
2: T = in tape and reel TQFP
packages only.
DS39632A-page 424 Advance Information 2004 Microchip Technology Inc.
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