Dual, 12-/14-/16-Bit nanoDACs® with
5 ppm/°C On-Chip Reference, I2C® Interface
AD5627R/AD5647R/AD5667R, AD5627/AD5667
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved.
FEATURES
Low power, smallest pin-compatible, dual nanoDACs
AD5627R/AD5647R/AD5667R
12-/14-/16-bit
On-chip 1.25 V/2.5 V, 5 ppm/°C reference
AD5627/AD5667
12-/16-bit
External reference only
3 mm x 3 mm LFCSP and 10-lead MSOP
2.7 V to 5.5 V power supply
Guaranteed monotonic by design
Power-on reset to zero scale
Per channel power-down
Hardware LDAC and CLR functions
I2C-compatible serial interface supports standard (100 kHz),
fast (400 kHz), and high speed (3.4 MHz) modes
APPLICATIONS
Process control
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
FUNCTIONAL BLOCK DIAGRAMS
INTERFACE
LOGIC
SDA
SCL
A
DDR
V
DD GND
POWER-ON
RESET
1.25V/2.5V REF
V
REFIN
/
VREFOUT
AD5627R/AD5647R/AD5667R
POWER-DOWN
LOGIC
INPUT
REGISTER
DAC
REGISTER
STRING
DAC A VOUTA
BUFFER
INPUT
REGISTER
DAC
REGISTER
STRING
DAC B VOUTB
LDAC CLR
BUFFER
06342-001
Figure 1. AD5627R/AD5647R/AD5667R
INTERFACE
LOGIC
SDA
SCL
A
DDR
V
DD
GND
POWER-ON
RESET
V
REFIN
AD5627/AD5667
POWER-DOWN
LOGIC
INPUT
REGISTER
DAC
REGISTER
STRING
DAC A V
OUT
A
BUFFER
INPUT
REGISTER
DAC
REGISTER
STRING
DAC B V
OUT
B
LDAC CLR
BUFFER
06342-002
Figure 2. AD5627/AD5667
GENERAL DESCRIPTION
The AD5627R/AD5647R/AD5667R, AD5627/AD5667
members of the nanoDAC family are low power, dual, 12-, 14-,
16-bit buffered voltage-out DACs with/without on-chip
reference. All devices operate from a single 2.7 V to 5.5 V
supply, are guaranteed monotonic by design, and have an I2C-
compatible serial interface.
The AD5627R/AD5647R/AD5667R have an on-chip reference.
The AD56x7RBCPZ have a 1.25 V, 5 ppm/°C reference, giving a
full-scale output range of 2.5 V; the AD56x7RBRMZ have a
2.5 V, 5 ppm/°C reference, giving a full-scale output range of 5
V. The on-chip reference is off at power-up, allowing the use of
an external reference. The internal reference is enabled via a
software write. The AD5667 and AD5627 require an external
reference voltage to set the output range of the DAC.
The AD56x7R/AD56x7 incorporate a power-on reset circuit
that ensures the DAC output powers up to 0 V, and remains
there until a valid write takes place. The part contains a per-
channel power-down feature that reduces the current
consumption of the device to 480 nA at 5 V and provides
software-selectable output loads while in power-down mode.
The low power consumption of this part in normal operation
makes it ideally suited to portable battery-operated equipment.
The on-chip precision output amplifier enables rail-to-rail
output swing.
The AD56x7R/AD56x7 use a 2-wire I2C-compatible serial
interface that operates in standard (100 kHz), fast (400 kHz),
and high speed (3.4 MHz) modes.
Table 1. Related Devices
Part No. Description
AD5663 2.7 V to 5.5 V, dual 16-bit DAC,
external reference, SPI® interface
AD5623R/AD5643R/AD5663R 2.7 V to 5.5 V, dual 12-, 14-, 16-bit
DACs, internal reference,
SPI interface
AD5625R/AD5645R/AD5665R,
AD5625/AD5665
2.7 V to 5.5 V, quad 12-, 14-, 16-bit
DACs, with/without internal
reference, I2C interface
AD5627R/AD5647R/AD5667R, AD5627/AD5667
Rev. 0 | Page 2 of 32
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagrams............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AC Characteristics........................................................................ 5
I2C Timing Specifications............................................................ 6
Absolute Maximum Ratings............................................................ 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions............................. 9
Typical Performance Characteristics ........................................... 10
Terminology .................................................................................... 18
Theory of Operation ...................................................................... 20
D/A Section................................................................................. 20
Resistor String............................................................................. 20
Output Amplifier........................................................................ 20
Internal reference........................................................................ 20
External reference....................................................................... 20
Serial Interface............................................................................ 21
Write Operation.......................................................................... 21
Read Operation........................................................................... 21
High Speed Mode....................................................................... 21
Input Shift Register .................................................................... 23
Multiple Byte Operation............................................................ 23
Broadcast Mode.......................................................................... 23
LDAC Function .......................................................................... 23
Power-Down Modes .................................................................. 25
Power-On Reset and Software Reset ....................................... 26
Clear Pin (CLR).......................................................................... 26
Internal Reference Setup (R Versions) .................................... 26
Application Information................................................................ 27
Using a Reference as a Power Supply for the
AD56x7R/AD56x7..................................................................... 27
Bipolar Operation Using the AD56x7R/AD56x7.................. 27
Power Supply Bypassing and Grounding................................ 27
Outline Dimensions....................................................................... 28
Ordering Guide .......................................................................... 29
REVISION HISTORY
1/07—Revision 0: Initial Version
AD5627R/AD5647R/AD5667R, AD5627/AD5667
Rev. 0 | Page 3 of 32
SPECIFICATIONS
VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; VREFIN = VDD; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter Min Typ Max Unit Conditions/Comments1
STATIC PERFORMANCE2
AD5667R/AD5667
Resolution 16 Bits
Relative Accuracy ±8 ±12 LSB
Differential Nonlinearity ±1 LSB Guaranteed monotonic by design
AD5647R
Resolution 14 Bits
Relative Accuracy ±2 ±4 LSB
Differential Nonlinearity ±0.5 LSB Guaranteed monotonic by design
AD5627R/AD5627
Resolution 12 Bits
Relative Accuracy ±0.5 ±1 LSB
Differential Nonlinearity ±0.25 LSB Guaranteed monotonic by design
Zero-Code Error 2 10 mV All 0s loaded to DAC register
Offset Error ±1 ±10 mV
Full-Scale Error −0.1 ±1 % of FSR All 1s loaded to DAC register
Gain Error ±1.5 % of FSR
Zero-Code Error Drift ±2 µV/°C
Gain Temperature Coefficient ±2.5 ppm Of FSR/°C
DC Power Supply Rejection Ratio −100 dB DAC code = midscale ; VDD = 5 V ± 10%
DC Crosstalk (External Reference) 15 µV Due to full-scale output change,
RL = 2 kΩ to GND or 2 kΩ to VDD
10 µV/mA Due to load current change
8 µV Due to powering down (per channel)
DC Crosstalk (Internal Reference) 25 µV Due to full-scale output change,
RL = 2 kΩ to GND or 2 kΩ to VDD
20 µV/mA Due to load current change
10 µV Due to powering down (per channel)
OUTPUT CHARACTERISTICS3
Output Voltage Range 0 VDD V
Capacitive Load Stability 2 nF RL = ∞
10 nF RL = 2 kΩ
DC Output Impedance 0.5
Short-Circuit Current 30 mA VDD = 5 V
Power-Up Time 4 µs Coming out of power-down mode; VDD = 5 V
REFERENCE INPUTS
Reference Current 110 130 µA VREF = VDD = 5.5 V
Reference Input Range 0.75 VDD V
Reference Input Impedance 50 kΩ
REFERENCE OUTPUT
(LFCSP_WD PACKAGE)
Output Voltage 1.247 1.253 V At ambient
Reference TC3 ±10 ppm/°C
Output Impedance 7.5 kΩ
REFERENCE OUTPUT (MSOP PACKAGE)
Output Voltage 2.495 2.505 V At ambient
Reference TC3 ±5 ±10 ppm/°C
Output Impedance 7.5 kΩ
AD5627R/AD5647R/AD5667R, AD5627/AD5667
Rev. 0 | Page 4 of 32
Parameter Min Typ Max Unit Conditions/Comments1
LOGIC INPUTS (ADDR, CLR, LDAC)3
IIN, Input Current ±1 µA
VINL, Input Low Voltage 0.15 × VDD V
VINH, Input High Voltage 0.85 × VDD V
CIN, Pin Capacitance 2 pF ADDR
20 pF
CLR, LDAC
VHYST, Input Hysteresis 0.1 × VDD V
LOGIC INPUTS (SDA, SCL)
IIN, Input Current ±1 µA
VINL, Input Low Voltage 0.3 × VDD V
VINH, Input High Voltage 0.7 × VDD V
CIN, Pin Capacitance 2 pF
VHYST, Input Hysteresis 0.1 × VDD V
LOGIC OUTPUTS (OPEN-DRAIN)
VOL, Output Low Voltage 0.4 V ISINK = 3 mA
0.6 V ISINK = 6 mA
Floating-State Leakage Current ±1 µA
Floating-State Output Capacitance 2 pF
POWER REQUIREMENTS
VDD 2.7 5.5 V
IDD (Normal Mode)4 V
IH = VDD, VIL = GND
VDD = 4.5 V to 5.5 V 0.4 0.5 mA Internal reference off
VDD = 2.7 V to 3.6 V 0.35 0.45 mA Internal reference off
VDD = 4.5 V to 5.5 V 0.95 1.15 mA Internal reference on
VDD = 2.7 V to 3.6 V 0.8 0.95 mA Internal reference on
IDD (All Power-Down Modes)5 0.48 1 µA VIH = VDD, VIL = GND
1 Temperature range: B grade: −40°C to +105°C.
2 Linearity calculated using a reduced code range: AD5567R/AD5667 (Code 512 to Code 65,024); AD5647R (Code 128 to Code 16,256); AD5627R/AD5627 (Code 32 to
Code 4064). Output unloaded.
3 Guaranteed by design and characterization, not production tested.
4 Interface inactive. All DACs active. DAC outputs unloaded.
5 All DACs powered down.
AD5627R/AD5647R/AD5667R, AD5627/AD5667
Rev. 0 | Page 5 of 32
AC CHARACTERISTICS
VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; VREFIN = VDD; all specifications TMIN to TMAX, unless otherwise noted.1
Table 3.
Parameter2Min Typ Max Unit Conditions/Comments3
Output Voltage Settling Time
AD5627R/AD5627 3 4.5 µs ¼ to ¾ scale settling to ±0.5 LSB
AD5647R 3.5 5 µs ¼ to ¾ scale settling to ±0.5 LSB
AD5667R/AD5667 4 7 µs ¼ to ¾ scale settling to ±2 LSB
Slew Rate 1.8 V/µs
Digital-to-Analog Glitch Impulse 15 nV-s 1 LSB change around major carry transition
Digital Feedthrough 0.1 nV-s
Reference Feedthrough −90 dB VREF = 2 V ± 0.1 V p-p, frequency 10 Hz to 20 MHz
Digital Crosstalk 0.1 nV-s
Analog Crosstalk 1 nV-s External reference
4 nV-s Internal reference
DAC-to-DAC Crosstalk 1 nV-s External reference
4 nV-s Internal reference
Multiplying Bandwidth 340 kHz VREF = 2 V ± 0.1 V p-p
Total Harmonic Distortion −80 dB VREF = 2 V ± 0.1 V p-p, frequency = 10 kHz
Output Noise Spectral Density 120 nV/√Hz DAC code = midscale, 1 kHz
100 nV/√Hz DAC code = midscale, 10 kHz
Output Noise 15 µV p-p 0.1 Hz to 10 Hz
1 Guaranteed by design and characterization, not production tested.
2 See the Terminology section.
3 Temperature range is −40°C to +105°C, typical @ 25°C.
AD5627R/AD5647R/AD5667R, AD5627/AD5667
Rev. 0 | Page 6 of 32
I2C TIMING SPECIFICATIONS
VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, fSCL = 3.4 MHz, unless otherwise noted.1
Table 4.
Parameter Conditions2 Min Max Unit Description
fSCL3 Standard mode 100 kHz Serial clock frequency
Fast mode 400 kHz
High speed mode, CB = 100 pF 3.4 MHz
High speed mode, CB = 400 pF 1.7 MHz
t1 Standard mode 4 s tHIGH, SCL high time
Fast mode 0.6 s
High speed mode, CB = 100 pF 60 ns
High speed mode, CB = 400 pF 120 ns
t2 Standard mode 4.7 s tLOW, SCL low time
Fast mode 1.3 s
High speed mode, CB = 100 pF 160 ns
High speed mode, CB = 400 pF 320 ns
t3 Standard mode 250 ns tSU;DAT, data setup time
Fast mode 100 ns
High speed mode 10 ns
t4 Standard mode 0 3.45 s tHD;DAT, data hold time
Fast mode 0 0.9 s
High speed mode, CB = 100 pF 0 70 ns
High speed mode, CB = 400 pF 0 150 ns
t5 Standard mode 4.7 s tSU;STA, setup time for a repeated start condition
Fast mode 0.6 s
High speed mode 160 ns
t6 Standard mode 4 s tHD;STA, hold time (repeated) start condition
Fast mode 0.6 s
High speed mode 160 ns
t7 Standard mode 4.7 s tBUF, bus free time between a stop and a start condition
Fast mode 1.3 s
t8 Standard mode 4 s tSU;STO, setup time for a stop condition
Fast mode 0.6 s
High speed mode 160 ns
t9 Standard mode 1000 ns tRDA, rise time of SDA signal
Fast mode 300 ns
High speed mode, CB = 100 pF 10 80 ns
High speed mode, CB = 400 pF 20 160 ns
t10 Standard mode 300 ns tFDA, fall time of SDA signal
Fast mode 300 ns
High speed mode, CB = 100 pF 10 80 ns
High speed mode, CB = 400 pF 20 160 ns
t11 Standard mode 1000 ns tRCL, rise time of SCL signal
Fast mode 300 ns
High speed mode, CB = 100 pF 10 40 ns
High speed mode, CB = 400 pF 20 80 ns
t11A Standard mode 1000 ns tRCL1, rise time of SCL signal after a repeated start condition and after
an acknowledge bit
Fast mode 300 ns
High speed mode, CB = 100 pF 10 80 ns
High speed mode, CB = 400 pF 20 160 ns
AD5627R/AD5647R/AD5667R, AD5627/AD5667
Rev. 0 | Page 7 of 32
Parameter Conditions2 Min Max Unit Description
t12 Standard mode 300 ns tFCL, fall time of SCL signal
Fast mode 300 ns
High speed mode, CB = 100 pF 10 40 ns
High speed mode, CB = 400 pF 20 80 ns
t13 Standard mode 10 ns
LDAC pulse width low
Fast mode 10 ns
High speed mode 10 ns
t14 Standard mode 300 ns
Falling edge of 9th SCL clock pulse of last byte of valid write to LDAC
falling edge
Fast mode 300 ns
High speed mode 30 ns
t15 Standard mode 20 ns
CLR pulse width low
Fast mode 20 ns
High speed mode 20 ns
tSP4 Fast mode 0 50 ns Pulse width of spike suppressed
High speed mode 0 10 ns
1 See Figure 3. High speed mode timing specification applies only to the AD5627RBRMZ-2/AD5627BRMZ-2REEL7 and AD5667RBRMZ-2/AD5667BRMZ-2REEL7.
2 CB refers to the capacitance on the bus line.
3 The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on EMC behavior
of the part.
4 Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns for fast mode or 10 ns for high speed mode.
SCL
SDA
PS S P
t
8
t
6
t
5
t
3
t
10
t
9
t
4
t
6
t
1
t
2
t
11
t
12
t
14
CLR
t
13
t
15
LDAC*
t
7
*ASYNCHRONOUS LDAC UPDATE MODE.
06342-003
Figure 3. 2-Wire Serial Interface Timing Diagram
AD5627R/AD5647R/AD5667R, AD5627/AD5667
Rev. 0 | Page 8 of 32
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 5.
Parameter Rating
VDD to GND −0.3 V to +7 V
VOUT to GND −0.3 V to VDD + 0.3 V
VREFIN/VREFOUT to GND −0.3 V to VDD + 0.3 V
Digital Input Voltage to GND −0.3 V to VDD + 0.3 V
Operating Temperature Range, Industrial −40°C to +105°C
Storage Temperature Range −65°C to +150°C
Junction Temperature (TJ maximum) 150°C
Power Dissipation (TJ max − TA)/θJA
θJA Thermal Impedance
LFCSP_WD Package (4-Layer Board) 61°C/W
MSOP Package 150.4°C/W
Reflow Soldering Peak Temperature, Pb-Free 260°C ± 5°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
AD5627R/AD5647R/AD5667R, AD5627/AD5667
Rev. 0 | Page 9 of 32
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
V
OUT
A
10
V
REFIN
2
V
OUT
B
9
V
DD
3
GND
8
SDA
4
LDAC
7
SCL
5
CLR
6
ADDR
AD5627/
AD5667
TOP VIEW
(Not to Scale)
EXPOSED PAD TIED TO GND
ON LFCSP PACKAGE.
06342-101
Figure 4. AD5627/AD5667 Pin Configuration
1
V
OUT
A
10
V
REFIN
/V
REFOUT
2
V
OUT
B
9
V
DD
3
GND
8
SDA
4
LDAC
7
SCL
5
CLR
6
ADDR
AD5627R/
AD5647R/
AD5667R
TOP VIEW
(Not to Scale)
EXPOSED PAD TIED TO GND
ON LFCSP PACKAGE.
06342-102
Figure 5. AD5627R/AD5647R/AD5667R Pin Configuration
Table 6. Pin Function Descriptions
Pin
No. Mnemonic Description
1 VOUTA Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
2 VOUTB Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
3 GND Ground reference point for all circuitry on the part.
4 LDAC Pulsing this pin low allows any or all DAC registers to be updated if the inputs have new data. This allows
simultaneous updates of all DAC outputs. Alternatively, this pin can be tied permanently low.
5 CLR Asynchronous Clear Input. The CLR input is falling-edge sensitive. While CLR is low, all LDAC pulses are ignored.
When CLR is activated, zero scale is loaded to all input and DAC registers. This clears the output to 0 V. The part exits
clear code mode on the falling edge of the 9th clock pulse of the last byte of valid write. If CLR is activated during a
write sequence, the write is aborted. If CLR is activated during high speed mode the part will exit high speed mode.
6 ADDR Three-State Address Input. Sets the two least significant bits (Bit A1, Bit A0) of the 7-bit slave address.
7 SCL Serial Clock Line. This is used in conjunction with the SDA line to clock data into or out of the 24-bit input register.
8 SDA Serial Data Line. This is used in conjunction with the SCL line to clock data into or out of the 24-bit input register. It is
a bidirectional, open-drain data line that should be pulled to the supply with an external pull-up resistor.
9 VDD Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should be decoupled with a
10 F capacitor in parallel with a 0.1 F capacitor to GND.
10 VREFIN/VREFOUT The AD56x7R have a common pin for reference input and reference output. When using the internal reference, this is
the reference output pin. When using an external reference, this is the reference input pin. The default for this pin is
as a reference input. (The internal reference and reference output are only available on R suffix versions.) The AD56x7
has a reference input pin only.
AD5627R/AD5647R/AD5667R, AD5627/AD5667
Rev. 0 | Page 10 of 32
TYPICAL PERFORMANCE CHARACTERISTICS
CODE
INL ERROR (LSB)
10
4
6
8
0
2
–6
–10
–8
–2
–4
0 5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k 65k
V
DD
= V
REF
= 5V
T
A
= 25°C
06342-005
Figure 6. AD5667 INL, External Reference
CODE
INL ERROR (LSB)
4
–4
0 2500 5000 7500 10000 12500 15000
–3
–2
–1
0
1
2
3
V
DD
= V
REF
= 5V
T
A
= 25°C
06342-006
Figure 7. AD5647R INL, External Reference
CODE
INL ERROR (LSB)
1.0
–1.0
0 500 1000 1500 2000 2500 3000 3500 4000
–0.8
–0.6
–0.4
0
0.4
0.2
–0.2
0.6
0.8
V
DD
= V
REF
= 5V
T
A
= 25°C
06342-100
Figure 8. AD5627 INL, External Reference
CODE
DNL ERROR (LSB)
1.0
0.6
0.4
0.2
0.8
0
–0.4
–0.2
–0.6
–1.0
–0.8
0 10k 20k 30k 40k 50k 60k
V
DD
= V
REF
= 5V
T
A
= 25°C
0
6342-007
Figure 9. AD5667 DNL, External Reference
DNL ERROR (LSB)
0.5
0.3
0.2
0.1
0.4
0
–0.2
–0.1
–0.3
–0.5
–0.4
V
DD
= V
REF
= 5V
T
A
= 25°C
CODE
02500 5000 7500 10000 12500 15000
0
6342-008
Figure 10. DNL AD5647R, External Reference
DNL ERROR (LSB)
0.20
0.10
0.05
0.15
0
–0.05
–0.10
–0.20
–0.15
CODE
0500 1000 1500 2000 2500 3000 3500 4000
V
DD
= V
REF
= 5V
T
A
= 25°C
0
6342-009
Figure 11. AD5627 DNL, External Reference
AD5627R/AD5647R/AD5667R, AD5627/AD5667
Rev. 0 | Page 11 of 32
CODE
INL ERROR (LSB)
10
8
0
–10
–6
–8
–4
6
–2
4
2
65000
60000
55000
50000
45000
40000
35000
30000
25000
20000
15000
10000
5000
0
VDD = 5V
VREFOUT = 2.5V
T
A
= 25°C
06342-010
Figure 12. AD5667R INL, 2.5 V Internal Reference
CODE
INL ERROR (LSB)
4
3
–4
–3
–2
2
–1
1
0
16250
15000
13750
12500
11250
10000
8750
7500
6250
5000
3750
2500
1250
0
V
DD
=5V
V
REFOUT
=2.5V
T
A
=25°C
06342-011
Figure 13. AD5647R INL, 2.5 V Internal Reference
CODE
INL ERROR (LSB)
1.0
0.8
0
–1.0
–0.8
–0.6
0.6
–0.4
–0.2
0.4
0.2
0 1000500 20001500 350030002500 4000
VDD =5V
VREFOUT =2.5V
TA= 25°C
06342-012
Figure 14. AD5627R INL, 2.5 V Internal Reference
CODE
DNL ERROR (LSB)
1.0
0.8
0
–1.0
–0.6
–0.8
–0.4
0.6
–0.2
0.4
0.2
65000
60000
55000
50000
45000
40000
35000
30000
25000
20000
15000
10000
5000
0
VDD =5V
VREFOUT =2.5V
T
A
=25°C
06342-013
Figure 15. AD5667R DNL, 2.5 V Internal Reference
CODE
DNL ERROR (LSB)
0.5
0.4
0
–0.5
–0.3
–0.4
–0.2
0.3
–0.1
0.2
0.1
16250
15000
13750
12500
11250
10000
8750
7500
6250
5000
3750
2500
1250
0
V
DD
= 5V
V
REFOUT
= 2.5V
T
A
= 25°C
0
6342-014
Figure 16. AD5647R DNL, 2.5 V Internal Reference
CODE
DNL ERROR (LSB)
0.20
0.15
0
–0.20
–0.15
–0.10
0.10
–0.05
0.05
0 1000500 20001500 350030002500 4000
V
DD
= 5V
V
REFOUT
= 2.5V
T
A
= 25°C
0
6342-015
Figure 17. AD5627R DNL, 2.5 V Internal Reference
AD5627R/AD5647R/AD5667R, AD5627/AD5667
Rev. 0 | Page 12 of 32
CODE
INL ERROR (LSB)
10
8
4
6
2
0
–4
–2
–6
–8
–10
65000
60000
55000
50000
45000
40000
35000
30000
25000
20000
15000
10000
5000
0
V
DD
= 3V
V
REFOUT
= 1.25V
T
A
= 25°C
06342-016
Figure 18. AD5667R INL,1.25 V Internal Reference
CODE
INL ERROR (LSB)
4
–4
16250
15000
13750
12500
11250
10000
8750
7500
6250
5000
3750
2500
1250
0
3
2
1
0
–1
–2
–3
V
DD
= 3V
V
REFOUT
= 1.25V
T
A
= 25°C
06342-017
Figure 19. AD5647R INL, 1.25 V Internal Reference
CODE
INL ERROR (LSB)
1.0
–1.0
0 500 1000 1500 2000 2500 3000 3500 4000
0
0.8
0.6
0.4
0.2
–0.2
–0.4
–0.6
–0.8
V
DD
= 3V
V
REFOUT
= 1.25V
T
A
= 25°C
06342-018
Figure 20. AD5627R INL,1.25 V Internal Reference
CODE
DNL ERROR (LSB)
1.0
0.8
0.4
0.6
0.2
0
–0.4
–0.2
–0.6
–0.8
–1.0
65000
60000
55000
50000
45000
40000
35000
30000
25000
20000
15000
10000
5000
0
V
DD
= 3V
V
REFOUT
= 1.25V
T
A
= 25°C
06342-019
Figure 21. AD5667R DNL,1.25 V Internal Reference
CODE
DNL ERROR (LSB)
0.5
–0.5
16250
15000
13750
12500
11250
10000
8750
7500
6250
5000
3750
2500
1250
0
0
0.4
0.3
0.2
0.1
–0.1
–0.2
–0.3
–0.4
V
DD
= 3V
V
REFOUT
= 1.25V
T
A
= 25°C
06342-020
Figure 22. AD5647R DNL,1.25 V Internal Reference
CODE
DNL ERROR (LSB)
0.20
–0.20
0 500 1000 1500 2000 2500 3000 3500 4000
0
0.15
0.10
0.05
–0.05
–0.10
–0.15
V
DD
= 3V
V
REFOUT
= 1.25V
T
A
= 25°C
06342-021
Figure 23. AD5627R DNL, 1.25 V Internal Reference
AD5627R/AD5647R/AD5667R, AD5627/AD5667
Rev. 0 | Page 13 of 32
TEMPERATURE (°C)
ERROR (LSB)
8
6
4
2
–6
–4
–2
0
–8
–40 –20 4020018060 00
MIN DNL
MAX DNL
MAX INL
MIN INL
V
DD
= V
REF
= 5V
06342-022
Figure 24. INL Error and DNL Error vs. Temperature
VREF (V)
ERROR (LSB)
10
4
6
8
2
0
–8
–6
–4
–2
–10
0.75 1.25 1.75 2.25 4.253.753.252.75 4.75
MIN DNL
MAX DNL
MAX INL
MIN INL
VDD = 5V
TA = 25°C
06342-023
Figure 25. INL and DNL Error vs. VREF
VDD (V)
ERROR (LSB)
8
6
4
2
–6
–4
–2
0
–8
2.7 3.2 3.7 4.74.2 5.2
MIN DNL
MAX DNL
MAX INL
MIN INL
TA = 25°C
06342-024
Figure 26. INL and DNL Error vs. Supply
TEMPERATURE (°C)
ERROR (% FSR)
0
–0.04
–0.02
–0.06
–0.08
–0.10
–0.18
–0.16
–0.14
–0.12
–0.20
–40 –20 40200 1008060
V
DD
= 5V
GAIN ERROR
FULL-SCALE ERROR
06342-025
Figure 27. Gain Error and Full-Scale Error vs. Temperature
TEMPERATURE (°C)
ERROR (mV)
1.5
1.0
0.5
0
–2.0
–1.5
–1.0
–0.5
–2.5
–40 –20 40200860 100
0
OFFSET ERROR
ZERO-SCALE ERROR
06342-026
Figure 28. Zero-Scale Error and Offset Error vs. Temperature
V
DD
(V)
ERROR (% FSR)
1.0
–1.5
–1.0
–0.5
0
0.5
–2.0
2.7 3.2 3.7 4.74.2 5.2
GAIN ERROR
FULL-SCALE ERROR
06342-027
Figure 29. Gain Error and Full-Scale Error vs. Supply
AD5627R/AD5647R/AD5667R, AD5627/AD5667
Rev. 0 | Page 14 of 32
V
DD
(V)
ERROR (mV)
1.0
0.5
0
–2.0
–1.5
–1.0
–0.5
–2.5
2.7 3.2 4.23.7 5.24.7
ZERO-SCALE ERROR
OFFSET ERROR
T
A
= 25°C
06342-028
Figure 30. Zero-Scale Error and Offset Error vs. Supply
I
DD
(mA)
NUMBER OF DEVICES
0
18
16
14
12
10
8
6
4
2
0.440.420.400.380.360.340.320.30
V
DD
= 3.6V
V
DD
= 5.5V
06342-029
Figure 31. IDD Histogram with External Reference
I
DD
(mA)
NUMBER OF DEVICES
0
14
12
10
8
6
4
2
0.74
0.75
0.76
0.77
0.78
0.79
0.80
0.81
0.82
0.83
0.84
0.85
0.86
0.87
0.88
0.89
0.90
0.91
0.92
0.93
0.94
0.95
0.96
0.97
0.98
0.99
1.00
1.01
1.02
1.03
1.04
V
DD
= 3.6V
V
DD
= 5.5V
06342-030
V
REFOUT
= 2.5V
V
REFOUT
= 1.25V
Figure 32. IDD Histogram with Internal Reference
CURRENT (mA)
ERROR VOL
T
AGE (V)
0.5
0.4
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
–10 –8 –6 –4 –2 0 2 4 861
0
V
DD
= 3V
V
REFOUT
= 1.25V
V
DD
= 5V
V
REFOUT
= 2.5V
DAC LOADED WITH
ZERO-SCALE
SINKING CURRENT
DAC LOADED WITH
FULL-SCALE
SOURCING CURRENT
0
6342-031
Figure 33. Headroom at Rails vs. Source and Sink
CURRENT (mA)
V
OUT
(V)
6
5
4
3
2
1
–1
0
–30 –20 –10 0 10 20 30
V
DD
= 5V
V
REFOUT
= 2.5V
T
A
= 25°C
ZERO SCALE
FULL SCALE
MIDSCALE
1/4 SCALE
3/4 SCALE
0
6342-046
Figure 34. AD56x7R with 2.5 V Reference, Source and Sink Capability
CURRENT (mA)
V
OUT
(V)
4
–1
0
1
2
3
–30 –20 –10 0 10 20 30
V
DD
= 3V
V
REFOUT
= 1.25V
T
A
= 25°C
ZERO SCALE
FULL SCALE
MIDSCALE
1/4 SCALE
3/4 SCALE
0
6342-047
Figure 35. AD56x7R with 1.25 V Reference, Source and Sink Capability
AD5627R/AD5647R/AD5667R, AD5627/AD5667
Rev. 0 | Page 15 of 32
CODE
I
DD
(mA)
0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
512 10512 20512 30512 40512 50512 60512
T
A
= 25°C
V
DD
= 5V, V
REFOUT
= 2.5V
V
DD
= V
REF
= 5V
0
6342-060
Figure 36. Supply Current vs. Code
SUPPLY VOLTAGE (V)
IDD (mA)
0
0.05
0.10
0.15
0.25
0.20
0.30
0.40
0.35
3.22.7 3.7 4.2 4.7 5.2
TA = 25°C
06342-061
Figure 37. Supply Current vs. Supply Voltage
TEMPERATURE (°C)
IDD (mA)
0.45
0.05
0.10
0.15
0.20
0.35
0.40
0.25
0.30
0
–40 –20 0 20 40 60 80 100
06342-063
VDD = VREFIN = 5V
VDD = VREFIN = 3V
Figure 38. Supply Current vs. Temperature
TIME BASE = 4µs/DIV
V
DD
= V
REF
= 5V
T
A
= 25°C
FULL-SCALE CODE CHANGE
0x0000 TO 0xFFFF
OUTPUT LOADED WITH 2k
AND 200pF TO GND
V
OUT
= 909mV/DIV
1
06342-048
Figure 39. Full-Scale Settling Time, 5 V
CH1 2.0V CH2 500mV M100µs 125MS/s
A CH1 1.28V
8.0ns/pt
V
DD
= V
REF
= 5V
T
A
= 25°C
V
OUT
V
DD
1
2
MAX(C2)
420.0mV
06342-049
Figure 40. Power-On Reset to 0 V
V
DD
= 5V
SYNC
SLCK
V
OUT
1
3
CH1 5.0V
CH3 5.0V
CH2 500mV M400ns A CH1 1.4V
2
0
6342-050
Figure 41. Exiting Power-Down to Midscale
AD5627R/AD5647R/AD5667R, AD5627/AD5667
Rev. 0 | Page 16 of 32
SAMPLE NUMBER
V
OUT
(V)
2.521
2.522
2.523
2.524
2.525
2.526
2.527
2.528
2.529
2.530
2.531
2.532
2.533
2.534
2.535
2.536
2.537
2.538
0 50 100 150 350 400200 250 300 450 512
V
DD
= V
REF
= 5V
T
A
= 25°C
5ns/SAMPLE NUMBER
GLITCH IMPULSE = 9.494nV
1LSB CHANGE AROUND
MIDSCALE (0x8000 TO 0x7FFF)
0
6342-058
Figure 42. Digital-to-Analog Glitch Impulse (Negative)
SAMPLE NUMBER
V
OUT
(V)
2.491
2.492
2.493
2.494
2.495
2.496
2.497
2.498
0 50 100 150 350 400200 250 300 450 512
V
DD
= V
REF
= 5V
T
A
= 25°C
5ns/SAMPLE NUMBER
ANALOG CROSSTALK = 0.424nV
0
6342-059
Figure 43. Analog Crosstalk, External Reference
SAMPLE NUMBER
V
OUT
(V)
2.456
2.458
2.460
2.462
2.464
2.466
2.468
2.470
2.472
2.474
2.476
2.478
2.480
2.482
2.484
2.486
2.488
2.490
2.492
2.494
2.496
0 50 100 150 350 400200 250 300 450 512
V
DD
= 5V
V
REFOUT
= 2.5V
T
A
= 25°C
5ns/SAMPLE NUMBER
ANALOG CROSSTALK = 4.462nV
0
6342-062
Figure 44. Analog Crosstalk, Internal Reference
1
VDD = VREF = 5V
TA = 25°C
DAC LOADED WITH MIDSCALE
4s/DIV
2µV/DI
V
06342-051
Figure 45. 0.1 Hz to 10 Hz Output Noise Plot, External Reference
5s/DIV
10µV/DI
V
1
V
DD
= 5V
V
REFOUT
= 2.5V
T
A
= 25°C
DAC LOADED WITH MIDSCALE
06342-052
Figure 46. 0.1 Hz to 10 Hz Output Noise Plot, 2.5 V Internal Reference
4s/DIV
5µV/DI
V
1
V
DD
= 3V
V
REFOUT
= 1.25V
T
A
= 25°C
DAC LOADED WITH MIDSCALE
06342-053
Figure 47. 0.1 Hz to 10 Hz Output Noise Plot,1.25 V Internal Reference