Features Fast Read Access Time - 70 ns Automatic Page Write Operation Internal Address and Data Latches for 64 Bytes Internal Control Timer Fast Write Cycle Times Page Write Cycle Time: 3 ms or 10 ms maximum 1 to 64 Byte Page Write Operation Low Power Dissipation 80 mA Active Current 3 mA Standby Current Hardware and Software Data Protection DATA Polling for End of Write Detection High Reliability CMOS Technology Endurance: 104 or 10 Cycles Data Retention: 10 years Single 5 V+ 10% Supply CMOS and TTL Compatible Inputs and Outputs JEDEC Approved Byte-Wide Pinout Full Military, Commercial, and Industrial Temperature Ranges Description The AT28HC256 is a high-performance Electrically Erasable and Programmable Read Only Memory. Its 256K of memory is organized as 32,768 words by 8 bits. Manufactured with Atmels advanced nonvolatile CMOS technology, the AT28HC256 offers access times to 70 ns with power dissipation of just 440 mW. When the AT28HC256 is deselected, the standby current is less than 5 mA. (continued) Pin Configurations TSOP Pin Name Function Top View AO-A14 Addresses eq Zp AIO = ; Att ga 27 p CE CE Chip Enable a a4? 28 og BO? log == a AWG | 5 24 vos WE q 6 Vo4a OE Output Enable ana VOCED 7 22 a HO3 ano WE Write Enable Ad 9 20 B vo2 AT ag] Oa 12? B yoo 1" 1/00 - 1/07 Data Inputs/Outputs AS g 12 aL B at AO 4 1413 15 NC No Connect a8 Ae CERDIP, PDIP, PGA FLATPACK LCC, PLCC Top View Top View Top View 4 3 1 | 27 | 26 1 28 b voc AT AL4VCC AI3 as | A7 | Ai4| WE | A13 2 27 b WE Al2 NG WE s | 2 | 2a | 24 | 25 3 aus 5 A5 | A12| VCC] AQ | AB 5 Ag 6 7/6 22 | 23 at 3 AS | A4 OE | Ail 8 Ato 9 a | 4a 20 | 21 9 ce 0 Al | A2 CE | A10 vO6 12 11 10| 14] 16 | 49 Os oa 151617181920 OO | AO | GND| 04 | /07 yO3 Ws TE NOSE 6 12] 13] 15] 17 | 18 GND vO1 | /02| 1/03! VO5 | vos . Note: PLCC package pins | and 17 are DONT CONNECT. AT28HC256 256 (32K x 8) High Speed CMOS E*PROM 2-183AIMEL Description (Continued) The AT28HC256 is accessed like a Static RAM for the read Atmels 28HC256 has additional features to ensure high quality write cycle without the need for external components. The de and manufacturability. The device utilizes internal error correc- vice contains a 64-byte page register to allow writing of up to 6 lion for extended endurance and improved data retention char- bytes simultaneously. During a write cycle, the address and 1 1 : acteristics. An optional software data protection mechanism is 64 bytes of data are internally latched, freeing the addresses an: i available to guard against inadvertent writes. The device also data bus for other operations. Following the initiation of a writ: includes an extra 64 bytes of E7PROM for device identification cycle, the device will automatically write the latched data usin. or tracking, an internal control timer. The end of a write cycle can be de tected by DATA polling of 07. Once the end of a write cycl has been detected a new access fora read or write can begin. Block Diagram vec DATA INPUTS/OUTPUTS GND -- 400 - VO? _ beep ess OE >| _.. __ _. -] OE, CE AND WE DATA LATCH WE * LOGIC ,|__ INPUT/OUTPUT CE BUFFERS ] YDECODER [*| Y-GATING ADDRESS | * * INPUTS <| CELL MATRIX X DECODER IDENTIFICATION Absolute Maximum Ratings* . oO, on! *NOTICE: Stresses beyond those listed under "Absolute Maxi- Temperature Under Bias................. 55C to +125C | mum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the de- O, O, Storage Temperature... 65C to +150C vice at these or any other conditions beyond those indicated in All Input Voltages the operational sections of this Specification is not implied. 4 (including N.c. Pins) exposure to apsolute tailitn conditions for extende with Respect to Ground 00... -0.6 V to +6.25 V | Periods may allect device relaouty: All Output Voltages with Respect to Ground............ -0.6 V to Vec +0.6 V | Voltage on OE and AQ with Respect to Ground ............... -0.6Vto+13.5V | 2-184 AT28HC256 enumees AT 81256 Device Operation READ: The AT28HC256 is accessed like a Static RAM. When CE and OE are low and WE is high, the data stored at the mem- ory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state when either CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention in their system. BYTE WRITE: A low pulse on the WE or CE input with CE or WE low (respectively) and OE high initiates a write cycle. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Once a byte write has been started it will automatically time itself to completion. Once a programming operation has been initiated and for the duration of twc, a read operation will effectively be a polling operation. PAGE WRITE: The page write operation of the AT28HC256 allows one to sixty-four bytes of data to be written into the de- vice during a single internal programming period. A page write Operation is initiated in the same manner as a byte write; the first byte written can then be followed by one to sixty-three addi- tional bytes. Each successive byte must be written within 150 Js (tpLc) of the previous byte. If the taic limit is exceeded the AT28C256 will cease accepting data and commence the internal programming operation. All bytes during a page write operation must reside on the same page as defined by the state of the A6- Al4 inputs. That is, for each WE high to low transition during the page write operation, A6 - Al4 must be the same. The AO to AS inputs are used to specify which bytes within the page are to be written. The bytes may be loaded in any order and may be altered within the same load period. Only bytes which are specified for writing will be written; unnecessary cycling of other bytes within the page does not occur. DATA POLLING: The AT28HC256 features DATA Polling to indicate the end of a write cycle. During a byte or page write cycle an attempted read of the last byte written will result in the complement of the written data to be presented on I/O7. Once the write cycle has been completed, true data is valid on all out- puts, and the next write cycle may begin. DATA Polling may begin at anytime during the write cycle. TOGGLE BIT: In addition to DATA Polling the AT28HC256 provides another method for determining the end of a write cycle. During the write operation, successive attempts to read data from the device will result in 1/06 toggling between one and zero. Once the write has completed, /06 will stop toggling and valid data will be read. Testing the toggle bit may begin at any time during the write cycle. DATA PROTECTION: If precautions are not taken, inadvertent writes to any five-volt-only nonvolatile memory may occur dur- ing transition of the host system power supply. Atmel has Pin Capacitance (f = 1 MHz, T = 25C) incorporated both hardware and software features that will pro- tect the memory against inadvertent writes. HARDWARE PROTECTION: Hardware features protect against inadvertent writes to the AT28HC256 in the following ways: (a) Vcc sense - if Vcc is below 3.8 V (typical) the write function is inhibited; (b) Vcc power-on delay - once Vcc has reached 3.8 V the device will automatically time out 5 ms typi- cal) before allowing a write: (c) write inhibit - holding any one of OF low, CE high or WE high inhibits write cycles; (d) noise filter - pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a write cycle. SOFTWARE DATA PROTECTION: A software controlled data protection feature has been implemented on_ the AT28HC256. When enabled, the software data protection (SDP), will prevent inadvertent writes. The SDP feature may be enabled or disabled by the user; the AT28HC256 is shipped from Atmel with SDP disabled. SDP is enabled by the host system issuing a series of three write commands; three specific bytes of data are written to three spe- cific addresses (refer to Software Data Protection Algorithm). After writing the three byte command sequence and after twc the entire AT28HC256 will be protected against inadvertent write operations. It should be noted, that once protected the host may still perform a byte or page write to the AT28HC256. This is done by preceding the data to be written by the same three byte command sequence. Once set, SDP will remain active unless the disable command sequence is issued. Power transitions do not disable SDP and SDP will protect the AT28HC256 during power-up and power- down conditions. All command sequences must conform to the page write timing specifications. It should also be noted that the data in the enable and disable command sequences is not written to the device and the memory addresses used in the sequence may be written with data in either a byte or page write operation. After setting SDP, any attempt to write to the device without the three byte command sequence will start the internal write tim- ers. No data will be written to the device; however, for the dura- tion of twc, read operations will effectively be polling opera- tions. DEVICE IDENTIFICATION: An extra 64 bytes of EPROM memory are available to the user for device identification. By raising A9 to 12 V 0.5 V and using address locations 7FCOH to 7FFFH the additional bytes may be written to or read from in the same manner as the regular memory array. OPTIONAL CHIP ERASE MODE: The entire device can be erased using a six byte software code. Please see Software Chip Erase application note for details. | Typ Max Units Conditions Cin 4 6 pF Vin =0V CouT 8 12 pF Vout =0V Note: 1. This parameter is characterized and is not 100% tested. AIMEL 2-185AIMEL D.C. and A.C. Operating Range AT28HC256-7 AT28HC256-90 AT28HC256-12 Com. oC-70C aC - 70C oC - 70C Poepereture (Case) nd. -40C-85C 40C - 85C -40C - 85C Mil. 85C - 125C -55C - 125C Voc Power Supply SV+10% 5V+410% 5V+10% Operating Modes Mode CE OE WE vo Read Vit VIL Viet Dout Write? VIL ____Viq VIL DIN Standby/Write Inhibit Vin x) X High Z Write Inhibit x Xx Vin Write Inhibit x ViL x Output Disable xX __VIH x High Z Chip Erase Vib Vy Vit High Z Notes: 1. X can be Vir or Vin. 3. VH= 12.0 V 405 V. 2. Refer to A.C. Programming Waveforms. D.C. Characteristics Symbol Parameter Condition Min Max Units lu Input Load Current Vin=OVtoVcc+1V 10 LA ILo Output Leakage Current Vio = OV to Voc 10 HA IsBt Voc Standby Current TTL CE=20VtoVec+1y AT2BHO256-90, 12 3 mA AT28HC256-70 60 mA Isp2 Voc Standby CurrentCMOS CE=-3.0VtoVcc+1V AT28HC256-90, -12 300 HA lec Voc Active Current f = 5 MHz; lout = O mA 80 mA VIL Input Low Voltage 0.8 Vv VIH Input High Voltage 2.0 Vv VoL Output Low Voltage lo. = 6.0 mA 45 Vv Vou Output High Voltage loH= -4 mA 2.4 Vv 2-186 AT28HC256 aqueees AT 81256 A.C. Read Characteristics AT28HC256-70 AT28C256-90 AT28HC256-12 Symboi | Parameter Min Max Min Max Min Max Units tacc Address to Output Delay 70 90 120 ns v4 tce? | CE to Output Delay 70 90 120 ns tor | OE to Output Delay 0 35 0 40 0 50 ns tor @4) | CE or OE to Output Float 0 35 | 0 40 0 50 ns Output Hold from OE, CE or 'OH Address, whichever occurred first 0 0 0 ns A.C. Read Waveforms" ?*) ADDRESS x ADDRESS VALID cE | OE [-1ACC {OH OUTPUT HIGH Z OUTPUT VALID Notes: _ 1. CE may be delayed up to tacc - tcg after the address transition 3. tor is specified from OE or CE whichever occurs first without impact on tacc. (CL=5 pF). 2. OE may be delayed up to tce - tog after the falling edge 4. This parameter is characterized and is not 100% tested. of CE without impact on tce or by tacc - tog after an address change without impact on tacc. Input Test Waveforms and Output Test Load Measurement Level 5.0V 3.0V AC AG OUTPUT DRIVING 1.5V MEASUREMENT PIN LEVELS oov LEVEL 1.3K 100pF tR, te< Sns t ANEL 25407 asi A.C. Write Characteristics Symbol Parameter Min Max Units tas, toes Address, OE Set-up Time 0 ns taH Address Hold Time 50 ns tes Chip Select Set-up Time - 0 ns tcH Chip Select Hold Time 0 ns twe Write Pulse Width (WE or CE) 100 ns tps Data Set-up Time 50 ns tpH, toEH Data, OE Hold Time 0 ns tov Time to Data Valid NR") Note: 1. NR =No Restiction A.C. Write Waveforms- WE Controlled tOES | {OEH ADDRESS x _ tAS| |.tAH __ ~ tcs"| Wwe TNR tWPH iWP A.C. Write Load Waveforms- CE Controlled OE = __ _ ee ADDRESS x tAS| |.tAH WE | tCH _ ____ tes" _ CE KN _ |_ tWPH_-| ___twp___-] ~ tDV tDS tDH eS 2-188 AT28HC256ees AT 28H C256 Page Mode Write Characteristics Symbol Parameter Min Typ Max Units two Write Cycle Time AT28HC256 5 10 ms AT28HC256F 2 3.0 ms tas Address Set-up Time 0 ns tAH Address Hold Time 50 ns tbs Data Set-up Time 50 ns {DH Data Hold Time 0 ns twp Write Pulse Width 100 ns tBLc Byte Load Cycle Time 150 ys tWPH Write Pulse Width High 50 ns Page Mode Write Waveforms) VALID ADD itDS DATA VALID DAT, K x BYTE 0 BYTE 1 BYTE 2 BYTE 3 BYTE 62 BYTE 63 | tWC J Notes: 1. A6 through Al4 must specify the same page address during each high to low transition of WE (or CE). 2. OE must be high only when WE and CE are both low. Chip Erase Waveforms ts = ty = 5 usec (min.) tw = 10 msec (min.) VH=12.0V+05V es =| LTTE] 2-189Almet Software Data Protection Enable Algorithm LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA AO TO ADDRESS 5555 (2) WRITES ENABLED LOAD DATA XX TO (4) ANY ADDRESS LOAD LAST BYTE TO LAST ADDRESS ENTER DATA PROTECT STATE Notes: 1. 2. 3. Data Format: 1/07 - 1/00 (Hex); Address Format: Al4 - AO (Hex). Write Protect state will be activated at end of write even if no other data is loaded. Write Protect state will be deactivated at end of write period even if no other data is loaded. . 1 to 64 bytes of data are loaded. Software Data w Protection Disable Algorithm Software Protected Write Cycle Waveforms) Notes: 1, 2-190 LOAD DATA AA ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 80 TO ADDRESS 5555 LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 20 TO ADDRESS 5555 EXIT DATA PROTECT STATE LOAD DATA XX TO (4) ANY ADDRESS LOAD LAST BYTE TO LAST ADDRESS ~ OE fon cE VS NS __ tWPR tWPH tBLC iL WE tAS tAH || tDH f AO-A5 x BYTE ADDRESS x L 2AAA 5555 ho nearer oe o tDS - (fom DATA x AA 85 AO x Xx _ Xx L BYTE 0 BYTE 62 BYTE 63 hr two software code has been entered. __ 2, OE must be high only when WE and CE are both low. AT28HC256 A6 through A1l4 must specify the same page address during each high to low transition of WE (or CE) after the (3)ees AT 2811 C256 Data Polling Characteristics' Symbol Parameter Min Typ Max Units tbH Data Hold Time 0 ns toEH OE Hold Time 0 ns toe OE to Output Delay) ns twa Write Recovery Time 0 ns Notes: 1. These parameters are characterized and not 100% tested. 2. See A.C. Read Characteristics. Data Polling Waveforms WE 7 Toggle Bit Characteristics' Symbol Parameter Min Typ Max Units {DH Data Hold Time 10 ns toEH OE Hold Time 10 ns toe OE to Output Delay) ns toEHP OE High Pulse 150 ns twa Write Recovery Time 0 ns Notes: 1. These parameters are characterized and not 100% tested. 2. See A.C. Read Characteristics. Toggle Bit Waveforms WE Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. 2. Beginning and ending state of 1/06 will vary. 3. Any address location may be used but the address should not vary. AMIEL 2101AIMEL NORMALIZED SUPPLY CURRENT vs. NORMALIZED SUPPLY CURRENT vs. i TEMPERATURE va SUPPLY VOLTAGE yn} nN 1 r 1.2 Py 1 m m 1.2 i V1 SJ : i ' 40 @ 10 MS : d - * og _ , 09 \ c os [~~ C 0.6 -55 -25 5 35 65 95 125 4.50 4.75 5.00 .25 5.50 Temperature (C) Supply Voltage (V) NORMALIZED SUPPLY CURRENT vs. ADDRESS FREQUENCY N 3 r 1.0 m Vec = 5V a T = 25C | og ee i z een e 08 d , o7 c Cc 06 0 2 4 6 8 10 Frequency (MHz) 2-192 AT28HC256 ummmOrdering Information" t Icc (mA ; (ns) ae ( Senay Ordering Code Package Operation Range 70 80 60 AT28HC256(E,F)-70DC 28D6 Commercial AT28HC256(E,F)-70JC 32J (0C to 70C) AT28HC256(E,F)-70PC 28P6 AT28HC256(E,F)-70DI 28D6 Industria! AT28HC256(E,F)-70J! 32J (-40C to 85C) AT28HC256(E,F)-70PI 28P6 90 80 0.3 AT28HC256(E,F)-90DC 28D6 Commercial AT28HC256(E,F)-90JC 32J (0C to 70C) AT28HC256(E,F)-90PC 28P6 AT28HC256(E,F)-90UC 28U AT28HC256(E,F)-90DI 28D6 Industrial AT28HC256(E,F)-90Jl 32J (-40C to 85C) AT28HC256(E,F)-90PI 28P6 AT28HC256(E,F)-90UI 28U AT28HC256(E,F)-90DM/883 28D6 Military/883C AT28HC256(E,F)-90FM/883 28F Class B, Fully Compliant AT28HC256(E,F)-90LM/883 32L (-55C to 125C) AT28HC256(E,F)-90UM/883 28U 120 80 0.3 AT28HC256(E,F)-12DC 28D6 Commercial AT28HC256(E,F)-12JNC 32J (0C to 70C) AT28HC256(E,F)-12PC 28P6 AT28HC256(E,F)-12SC 28S AT28HC256(E,F)-12TC 28T AT28HC256(E,F)-12UC 28U AT28HC256(E,F}-12D1 28D6 Industrial AT28HC256(E,F)-12JI 32d (-40C to 85C) AT28HC256(E,F)-12Pl 28P6 AT28HC256(E,F)-12SI 28S AT28HC256(E,F)-12Tl 28T AT28HC256(E,F)-12UI 28U AT28HC256(E,F)-12DM/883 28D6 Military/883C AT28HC256(E,F)-12FM/883 28F Class B, Fully Compliant AT28HC256(E,F)-12LM/883 32L (-55C to 125C) AT28HC256(E,F)-12UM/883 28U 90 80 0.3 5962-88634 03 UX 28U Military/883C 5962-88634 03 XX 28D6 Class B, Fully Compliant 5962-88634 03 YX 32L (-85C to 125C) 5962-88634 03 ZX 28F 5962-88634 04 UX 28U Military/883C 5962-88634 04 XX 28D6 Class B, Fully Compliant 5962-88634 04 YX 32L (-55C to 125C) 5962-88634 04 ZX 28F 120 80 0.3 5962-88634 01 UX 28U Military/883C 5962-88634 01 XX 28D6 Class B, Fully Compliant 5962-88634 01 YX 32L (-55C to 125C) 5962-88634 01 ZX 28F AIMEL 2-193i _ Ordering Information tacc lec (mA) ; Ordering Code Package Operation Range (ns) Active Standby g 9 P 9 120 80 0.3 5962-88634 02 UX 28U Military/883C 5962-88634 02 XX 28D6 Class B, Fully Compliant 5962-88634 02 YX 32L (-55C to 125C) 5962-88634 02 ZX 28F Note: 1. See Valid Part Number table below. Ordering Information Note Previous data sheets included the low power suffixes L, LE and LF on the AT28HC256 for 120 ns and 90 ns speeds. The low power parameters are now standard; therefore, the L, LE and LF suffixes are no longer required. Valid Part Numbers The following table lists standard Atmel products that can be ordered. Device Numbers Speed Package and Temperature Combinations AT28HC256 70 DC, DI, JC, JI, PC, Pi AT28HC256 90 DC, DI, JC, JI, PC, Pl, TC, Tl, OM/883, FM/883, UM/883 AT28HC256E 90 DC, DI, JC, JI, PC, Pl, TC, Tl, DM/883, FM/883, UM/883 AT28HC256F 90 DC, DI, JC, JI, PC, Pl, TC, Tl, OM/883, FM/883, UM/883 AT28HC256 12 DC, DI, JC, JI, PC, Pl, TC, Tl, DM/883, FM/883, UM/883 AT28HC256E 12 DC, DI, JC, JI, PC, Pl, TC, Tl, OM/883, FM/883, UM/883 AT28HC256F 12 DC, DI, JC, JI, PC, Pl, TC, Tl, OM/883, FM/883, UM/883 Package Type 28D6 28 Lead, 0.600" Wide, Non-Windowed, Ceramic Dual Inline Package (Cerdip) 28F 28 Lead, Non-Windowed, Ceramic Bottom-Brazed Flat Package (Flatpack) 32J 32 Lead, Plastic J-Leaded Chip Carrier (PLCC) 32L 32 Pad, Non-Windowed, Ceramic Leadless Chip Carrier (LCC) 28P6 28 Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) 28S 28 Lead, 0.300" Wide Plastic Gull Wing Small Outline (SOIC) 28T 28 Lead, Plastic Thin Small Outline Package (TSOP) 28U 28 Pin, Ceramic Pin Grid Array (PGA) Options Blank Standard Device: Endurance = 10K Write Cycles; Write Time = 10 ms E High Endurance Option: Endurance = 100K Write Cycles F Fast Write Option: Write Time = 3 ms 2-194 AT28HC256 mummmmS