ADVANCE 16, 32 MEG x 72 DDR REGISTERED SDRAM DIMMs MT18VDDT1672G, MT18VDDT3272G DDR SDRAM DIMM MODULE For the latest data sheet, please refer to the Micron Web site: www.micron.com/mti/msp/html/ datasheet.html FEATURES PIN ASSIGNMENT * 184-pin, dual in-line memory modules (DIMM) * Registered inputs with one-clock delay * Phase-lock loop (PLL) clock driver to reduce loading * Utilizes 100 MHz and 133 MHz DDR SDRAM components * ECC-optimized pinout * 128MB (16 Meg x 72), 256MB (32 Meg x 72) * VDD = +2.5V 0.2V, VDDQ = +2.5V 0.2V * VDDSPD = +2.5V to +3.3V * 2.5V I/O (SSTL_2 compatible) * Commands entered on each positive CK edge * DQS edge-aligned with data for READs; centeraligned with data for WRITEs * Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle * Bidirectional data strobe (DQS) transmitted/ received with data, i.e., source-synchronous data capture * Differential clock inputs (CK0 and CK0#) * Four internal banks for concurrent operation * Programmable burst lengths: 2, 4, or 8 * Auto precharge option * Auto Refresh and Self Refresh Modes * 15.6s maximum average periodic refresh interval OPTIONS PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 MARKING * Package 184-pin DIMM (gold) * Frequency/CAS Latency* 266 MHz/CL = 2 (133 MHz DDR SDRAMs) 266 MHz/CL = 2.5 (133 MHz DDR SDRAMs) 200 MHz/CL = 2 (100 MHz DDR SDRAMs) G -262 -265 -202 *Device latency only; extra clock cycle required due to input register. 184-Pin DIMM SYMBOL VREF DQ0 VSS DQ1 DQS0 DQ2 VDD DQ3 NC RESET# VSS DQ8 DQ9 DQS1 VDDQ DNU DNU VSS DQ10 DQ11 CKE0 VDDQ DQ16 DQ17 DQS2 VSS A9 DQ18 A7 VDDQ DQ19 A5 DQ24 VSS DQ25 DQS3 A4 VDD DQ26 DQ27 A2 VSS A1 CB0 CB1 VDD PIN SYMBOL 47 DQS8 48 A0 49 CB2 50 VSS 51 CB3 52 BA1 53 DQ32 54 VDDQ 55 DQ33 56 DQS4 57 DQ34 58 VSS 59 BA0 60 DQ35 61 DQ40 62 VDDQ 63 WE# 64 DQ41 65 CAS# 66 VSS 67 DQS5 68 DQ42 69 DQ43 70 VDD 71 DNU 72 DQ48 73 DQ49 74 VSS 75 DNU 76 DNU 77 VDDQ 78 DQS6 79 DQ50 80 DQ51 81 VSS 82 VDDID 83 DQ56 84 DQ57 85 VDD 86 DQS7 87 DQ58 88 DQ59 89 VSS 90 WP 91 SDA 92 SCL PIN SYMBOL PIN SYMBOL 93 VSS 139 VSS 94 DQ4 140 DQS17 95 DQ5 141 A10 96 VDDQ 142 CB6 97 DQS9 143 VDDQ 98 DQ6 144 CB7 99 DQ7 145 VSS 100 VSS 146 DQ36 101 NC 147 DQ37 102 NC 148 VDD 103 NC (A13) 149 DQS13 104 VDDQ 150 DQ38 105 DQ12 151 DQ39 106 DQ13 152 VSS 107 DQS10 153 DQ44 108 VDD 154 RAS# 109 DQ14 155 DQ45 110 DQ15 156 VDDQ 111 CKE1 157 S0# 112 VDDQ 158 NC (S1#) 113 NC (BA2) 159 DQS14 114 DQ20 160 VSS 115 NC (A12) 161 DQ46 116 VSS 162 DQ47 117 DQ21 163 DNU 118 A11 164 VDDQ 119 DQS11 165 DQ52 120 VDD 166 DQ53 121 DQ22 167 NC (FETEN) 122 A8 168 VDD 123 DQ23 169 DQS15 124 VSS 170 DQ54 125 A6 171 DQ55 126 DQ28 172 VDDQ 127 DQ29 173 NC 128 VDDQ 174 DQ60 129 DQS12 175 DQ61 130 A3 176 VSS 131 DQ30 177 DQS16 132 VSS 178 DQ62 133 DQ31 179 DQ63 134 CB4 180 VDDQ 135 CB5 181 SA0 136 VDDQ 182 SA1 137 CK0 183 SA2 138 CK0# 184 VDDSPD NOTE: Symbols in parentheses are not used on this module but may be used for other modules in this product family. They are for reference only. 16, 32 Meg x 72 DDR Registered SDRAM DIMMs ZM44.p65 - Rev. 4/00 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. ADVANCE 16, 32 MEG x 72 DDR REGISTERED SDRAM DIMMs KEY DDR SDRAM COMPONENT TIMING PARAMETERS MODULE MARKING -262 -265 -202 SPEED GRADE -7 (7.5ns @ CL = 2) -7 (7.5ns @ CL = 2.5) -75 (10ns @ CL = 2) output data is referenced to both edges of DQS, as well as to both edges of CK0. Read and write accesses to the DDR SDRAM modules are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and the starting column location for the burst access. The DDR SDRAM modules provide for programmable READ or WRITE burst lengths of 2, 4, or 8 locations. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard SDR SDRAM modules, the pipelined, multibank architecture of DDR SDRAM modules allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time. An auto refresh mode is provided, along with a power-saving power-down mode. All inputs are compatible with the JEDEC Standard for SSTL_2. All outputs are SSTL_2, Class II compatible. For more information regarding DDR SDRAM operation, refer to the 64Mb and 128Mb x 4 x 4 DDR SDRAM data sheets. CLOCK RATE (1/tCK) 133 MHz 143 MHz 100 MHz *CL = CAS (READ) latency PART NUMBERS PART NUMBER CONFIGURATION SYSTEM BUS SPEED MT18VDDT1672G-262__ 16 Meg x 72 CL = 2, 266 MHz MT18VDDT1672G-265__ 16 Meg x 72 CL = 2.5, 266 MHz MT18VDDT1672G-202__ 16 Meg x 72 CL = 2, 200 MHz MT18VDDT3272G-262__ 32 Meg x 72 CL = 2, 266 MHz MT18VDDT3272G-265__ 32 Meg x 72 CL = 2.5, 266 MHz MT18VDDT3272G-202__ 32 Meg x 72 CL = 2, 200 MHz NOTE: All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current revision codes. Example: MT18VDDT1672G-262A1 GENERAL DESCRIPTION The MT18VDDT1672 and MT18VDDT3272 are high-speed CMOS, dynamic random-access, 128MB and 256MB memories organized in a x72 configuration. These modules use internally configured quadbank DDR SDRAMs. The DDR SDRAM modules use a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR SDRAM module effectively consists of a single 2n-bit wide, one-clock-cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins. A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is an intermittent strobe transmitted by the DDR SDRAM during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. The DDR SDRAM modules operate from a differential clock (CK0 and CK0#); the crossing of CK0 going HIGH and CK0# going LOW will be referred to as the positive edge of CK0. Commands (address and control signals) are registered at every positive edge of CK0. Input data is registered on both edges of DQS, and 16, 32 Meg x 72 DDR Registered SDRAM DIMMs ZM44.p65 - Rev. 4/00 PLL AND REGISTER OPERATION The DDR SDRAM module is operated in registered mode where the control/address input signals are latched in the register on one rising clock edge and sent to the DDR SDRAM devices on the following rising clock edge (data access is delayed by one clock). A phase-lock loop (PLL) on the module is used to redrive the differential clock signals CK0 and CK0# to the DDR SDRAM devices to minimize system clock loading. SERIAL PRESENCE-DETECT OPERATION The DDR SDRAM module incorporates serial presence-detect (SPD). The SPD function is implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256 bytes. The first 128 bytes can be programmed by Micron to identify the module type and various SDRAM organizations and timing parameters. The remaining 128 bytes of storage are available for use by the customer. System READ/WRITE operations between the master (system logic) and the slave EEPROM device (DIMM) occur via a standard IIC bus using the DIMM's SCL (clock) and SDA (data) signals, together with SA(2:0), which provide eight unique DIMM/ EEPROM addresses. 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. ADVANCE 16, 32 MEG x 72 DDR REGISTERED SDRAM DIMMs FUNCTIONAL BLOCK DIAGRAM MT18VDDT1672 (128MB) and MT18VDDT3272 (256MB) VSS RS0# DQS9 DQS0 DQ0 DQ1 DQ2 DQ3 DM CS# DQS DQ0 DQ1 U0 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM CS# DQS DQ0 DQ1 U1 DQ2 DQ3 DQ8 DQ9 DQ10 DQ11 DM CS# DQS DQ0 DQ1 U2 DQ2 DQ3 DQ12 DQ13 DQ14 DQ15 DM CS# DQS DQ0 DQ1 U3 DQ2 DQ3 CB0 CB1 CB2 CB3 DM CS# DQS DQ0 DQ1 U4 DQ2 DQ3 DQ16 DQ17 DQ18 DQ19 DM CS# DQS DQ0 DQ1 U5 DQ2 DQ3 DQ20 DQ21 DQ22 DQ23 DM CS# DQS DQ0 DQ1 U6 DQ2 DQ3 DQ24 DQ25 DQ26 DQ27 DM CS# DQS DQ0 DQ1 U7 DQ2 DQ3 DQ28 DQ29 DQ30 DQ31 DM CS# DQS DQ0 DQ1 U8 DQ2 DQ3 DQS1 WE# PCK DM CS# DQS DQ0 DQ1 U12 DQ2 DQ3 CB4 CB5 CB6 CB7 DM CS# DQS DQ0 DQ1 U13 DQ2 DQ3 DQ48 DQ49 DQ50 DQ51 DM CS# DQS DQ0 DQ1 U14 DQ2 DQ3 DQ52 DQ53 DQ54 DQ55 DM CS# DQS DQ0 DQ1 U15 DQ2 DQ3 DQ56 DQ57 DQ58 DQ59 DM CS# DQS DQ0 DQ1 U16 DQ2 DQ3 DQ60 DQ61 DQ62 DQ63 DM CS# DQS DQ0 DQ1 U17 DQ2 DQ3 DQS16 DQS8 CKE0 DQ44 DQ45 DQ46 DQ47 DQS15 DQS7 CAS# DM CS# DQS DQ0 DQ1 U11 DQ2 DQ3 DQS14 DQS6 RAS# DQ40 DQ41 DQ41 DQ43 DQS13 DQS5 A0-A11 DM CS# DQS DQ0 DQ1 U10 DQ2 DQ3 DQS12 DQS4 R E G I S T E R S DQ36 DQ37 DQ38 DQ39 DQS11 DQS3 S0# DM CS# DQS DQ0 DQ1 U9 DQ2 DQ3 DQS10 DQS2 BA0, BA1 DQ32 DQ33 DQ34 DQ35 DQS17 SDRAM X 2 SDRAM X 2 SDRAM X 2 SDRAM X 2 SDRAM X 2 SDRAM X 2 SDRAM X 2 SDRAM X 2 SDRAM X 2 REGISTER X 2 120 RS0# CK0 CK0# RBA0, RBA1: SDRAMS U0-U17 RA0-RA11: SDRAMS U0-U17 PLL RRAS#: SDRAMS U0-U17 RCAS#: SDRAMS U0-U17 RCKE0: SDRAMS U0-U17 SERIAL PD SCL WP RWE#: SDRAMS U0-U17 47K SDA A0 A1 A2 SA0 SA1 SA2 RESET# PCK# U0-U17 = MT46V16M4A2TG SDRAMs for 128MB U0-U17 = MT46V32M4A2TG SDRAMS for 256MB NOTE: 16, 32 Meg x 72 DDR Registered SDRAM DIMMs ZM44.p65 - Rev. 4/00 VDDQ SDRAMS U0-U17 VDD SDRAMS U0-U17 VREF SDRAMS U0-U17 VSS SDRAMS U0-U17 1. All resistor values are 22 ohms unless otherwise specified. 2. Reference designators in this diagram do not necessarily match the actual module. 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. ADVANCE 16, 32 MEG x 72 DDR REGISTERED SDRAM DIMMs PIN DESCRIPTIONS PIN NUMBERS SYMBOL TYPE DESCRIPTION 63, 65, 154 WE#, CAS#, RAS# Input Command Inputs: RAS#, CAS# and WE# (along with S0#, S1#) define the command being entered. 137, 138 CK0, CK0# Input Clock: CK0 and CK0# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK0 and negative edge of CK0#. Output data (DQs and DQS) is referenced to the crossings of CK0 and CK0#. 21, 111 CKE0, CKE1 Input Clock Enable: CKE0 and CKE1 activate (HIGH) and deactivate (LOW) internal clock signals, and device input buffers and output drivers. Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWERDOWN (row ACTIVE in any bank). CKE0 and CKE1 are synchronous for all functions except for disabling outputs, which is achieved asynchronously. CKE0 and CKE1 must be maintained HIGH throughout read and write accesses. Input buffers (excluding CK0, CK0# and CKE) are disabled during POWER-DOWN. Input buffers (excluding CKE0 and CKE1) are disabled during SELF REFRESH. CKE0 and CKE1 are SSTL_2 inputs but will detect an LVCMOS LOW level after VDD is applied. 9, 101, 102, 103, 113, 115, 158, 167, 173 NC -- 157 S0# Input Chip Select: S0# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when S0# is registered HIGH. S0# provides for external bank selection on systems with multiple banks. S0# is considered part of the command code. 59, 52 BA0, BA1 Input Bank Address: BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRECHARGE command is being applied. 48, 43, 41, 130, 37, 32, 125, 29, 122, 27, 141, 118 A0-A11 Input Address Inputs: A0-A11 are sampled during the ACTIVE command (row-address A0-A11) and READ/WRITE command (column-address A0-A8, with A10 defining auto precharge) to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). The address inputs also provide the op-code during a MODE REGISTER SET command. 1 VREF Input SSTL_2 reference voltage. 82 VDDID Input VDD identification flag. 90 WP Input Write Protect: Serial presence-detect hardware write protect. 16, 32 Meg x 72 DDR Registered SDRAM DIMMs ZM44.p65 - Rev. 4/00 No Connect: These pins should be left unconnected. 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. ADVANCE 16, 32 MEG x 72 DDR REGISTERED SDRAM DIMMs PIN DESCRIPTIONS (continued) PIN NUMBERS SYMBOL TYPE DESCRIPTION 92 SCL Input Serial Clock for Presence-Detect: SCL is used to synchronize the presence-detect data transfer to and from the module. 181, 182, 183 SA0-SA2 Input Presence-Detect Address Inputs: These pins are used to configure the presence-detect device. 10 RESET# Input Asynchronously forces all register outputs LOW when RESET# is LOW. This signal can be used during powerup to ensure CKE0/1 are LOW and SDRAM DQs are High-Z. 44, 45, 49, 51, 134, 135, 142, 144 CB0-CB7 Input/ Output Data I/Os: Check bits. 5, 14, 25, 36, 47, 56, 67, 78, 86, 97, 107, 119, 129, 140, 149, 159, 169, 177 DQS0-DQS17 Input/ Output Data Strobes: Output with READ data, input with WRITE data Edge-aligned with READ data, centered in WRITE data. Used to capture WRITE data. 2, 4, 6, 8, 12, 13, 19, 20, 23, 24, 28, 31, 33, 35, 39, 40, 53, 55, 57, 60, 61, 64, 68, 69, 72, 73, 79, 80, 83, 84, 87, 88, 94, 95, 98, 99, 105, 106, 109, 110, 114, 117, 121, 123, 126, 127, 131, 133, 146, 147, 150, 151, 153, 155, 161, 162, 165, 166, 170, 171, 174, 175, 178, 179 DQ0-DQ63 Input/ Output Data I/Os: Data bus. 91 SDA Input/ Output Serial Presence-Detect Data: SDA is a bidirectional pin used to transfer addresses and data into and out of the presence-detect portion of the module. 15, 22, 30, 54, 62, 77, 96, 104, 112, 128, 136, 143, 156, 164, 172, 180 VDDQ Supply DQ Power Supply: +2.5V +0.2V. 7, 38, 46, 70, 85, 108, 120, 148, 168 VDD Supply Power Supply: +2.5V +0.2V. 3, 11, 18, 26, 34, 42, 50, 58, 66, 74, 81, 89, 93, 100, 116, 124, 132, 139, 145, 152, 160, 176 VSS Supply Ground. 184 VDDSPD Supply Serial EEPROM positive power supply. 16, 17, 71, 75, 76, 163 DNU - 16, 32 Meg x 72 DDR Registered SDRAM DIMMs ZM44.p65 - Rev. 4/00 Do Not Use: These pins are not connected on this module but are assigned pins on other modules in this product family. 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. ADVANCE 16, 32 MEG x 72 DDR REGISTERED SDRAM DIMMs SPD CLOCK AND DATA CONVENTIONS SPD ACKNOWLEDGE Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (Figures 1 and 2). Acknowledge is a software convention used to indicate successful data transfers. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data (Figure 3). The SPD device will always respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a write operation have been selected, the SPD device will respond with an acknowledge after the receipt of each subsequent eightbit word. In the read mode the SPD device will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the slave will continue to transmit data. If an acknowledge is not detected, the slave will terminate further data transmissions and await the stop condition to return to standby power mode. SPD START CONDITION All commands are preceded by the start condition, which is a HIGH-to-LOW transition of SDA when SCL is HIGH. The SPD device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. SPD STOP CONDITION All communications are terminated by a stop condition, which is a LOW-to-HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the SPD device into standby power mode. SCL SCL SDA SDA DATA STABLE DATA CHANGE DATA STABLE START BIT Figure 1 Data Validity STOP BIT Figure 2 Definition of Start and Stop SCL from Master 8 9 Data Output from Transmitter Data Output from Receiver Acknowledge Figure 3 Acknowledge Response From Receiver 16, 32 Meg x 72 DDR Registered SDRAM DIMMs ZM44.p65 - Rev. 4/00 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. ADVANCE 16, 32 MEG x 72 DDR REGISTERED SDRAM DIMMs SERIAL PRESENCE-DETECT MATRIX BYTE 0 1 2 3 4 5 6 7 8 9 DESCRIPTION NUMBER OF SPD BYTES USED BY MICRON TOTAL NUMBER OF BYTES IN SPD DEVICE FUNDAMENTAL MEMORY TYPE NUMBER OF ROW ADDRESSES ON ASSEMBLY NUMBER OF COLUMN ADDRESSES ON ASSEMBLY NUMBER OF PHYSICAL BANKS ON DIMM MODULE DATA WIDTH MODULE DATA WIDTH (continued) MODULE VOLTAGE INTERFACE LEVELS (VDDQ) SDRAM CYCLE TIME, (tCK) (CAS LATENCY = 2.5) ENTRY (VERSION) MT18VDDT1672 (Hex) 128 80 256 08 SDRAM DDR 07 12 0C 10 or 11 0A 1 01 72 48 0 00 SSTL 2.5V 04 7 ns (-262) 70 7.5 ns (-265) 75 8 ns (-202) 80 MT18VDDT3272 (Hex) 80 08 07 0C 0B 01 48 00 04 70 75 80 10 SDRAM ACCESS FROM CLOCK,(tAC) (CAS LATENCY = 2.5) 0.75 ns (-262/-265) 0.8 ns (-202) 75 80 75 80 11 12 13 14 15 MODULE CONFIGURATION TYPE REFRESH RATE/TYPE SDRAM DEVICE WIDTH (PRIMARY SDRAM) ERROR-CHECKING SDRAM DATA WIDTH MINIMUM CLOCK DELAY, BACK-TO-BACK RANDOM COLUMN ACCESS ECC 15.6s/SELF x4 x4 1 clock 02 80 04 04 01 02 80 04 04 01 16 17 18 19 20 21 22 23 BURST LENGTHS SUPPORTED NUMBER OF BANKS ON SDRAM DEVICE CAS LATENCIES SUPPORTED CS LATENCY WE LATENCY SDRAM MODULE ATTRIBUTES SDRAM DEVICE ATTRIBUTES: GENERAL SDRAM CYCLE TIME, (tCK) (CAS LATENCY = 2) 2, 4, 8 4 2, 2.5 0 1 REGISTERED, PLL 7.5 ns (-262) 10 ns (-265/-202) 0E 04 0C 01 02 26 00 75 A0 0E 04 0C 01 02 26 00 75 A0 24 SDRAM ACCESS FROM CK , (tAC) (CAS LATENCY = 2) 0.75 ns (-262/-265) 0.8 ns (-202) 75 80 75 80 25 SDRAM CYCLE TIME, (tCK) (CAS LATENCY = 1.5) N/A 00 00 26 SDRAM ACCESS FROM CK , (tAC) (CAS LATENCY = 1.5) N/A 00 00 27 MINIMUM ROW PRECHARGE TIME,(tRP) 28 29 MINIMUM ROW ACTIVE TO ROW ACTIVE, (tRRD) MINIMUM RAS# TO CAS# DELAY, (tRCD) 30 MINIMUM RAS# PULSE WIDTH, (tRAS) 15 ns (-262) 20 ns (-265/-202) 15 ns 15 ns (-262) 20 ns (-265/-202) 45 ns (-262/-265) 50 ns (-202) 3C 50 3C 3C 50 2D 32 3C 50 3C 3C 50 2D 32 31 MODULE BANK DENSITY 128MB or 256MB 20 40 NOTE: 1. "1"/"0": Serial Data, "driven to HIGH"/"driven to LOW." 16, 32 Meg x 72 DDR Registered SDRAM DIMMs ZM44.p65 - Rev. 4/00 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. ADVANCE 16, 32 MEG x 72 DDR REGISTERED SDRAM DIMMs SERIAL PRESENCE-DETECT MATRIX (continued) BYTE 32 DESCRIPTION ADDRESS AND COMMAND SETUP TIME, (tIS) ENTRY (VERSION) MT18VDDT1672G (Hex) MT18VDDT3272G (Hex) 0.9ns or 1.0ns (-262/-265) A0 90 1.1ns (-202) B0 B0 33 ADDRESS AND COMMAND HOLD TIME, (tIH) 0.9ns or 1.0ns (-262/-265) 1.1ns (-202) A0 B0 90 B0 34 DATA/DATA MASK INPUT SETUP TIME, (tDS) 0.5 (-262/-265) 0.6 (-202) 50 60 50 60 35 DATA/DATA MASK INPUT HOLD TIME, (tDH) 0.5 (-262/-265) 0.6 (-202) 50 60 50 60 00 00 1E 76 52 2C 00 01 02 03 04 05 06 07 08 09 00 00 75 CD 73 2C 00 01 02 03 04 05 06 07 08 09 36-61 62 63 RESERVED SPD REVISION CHECKSUM FOR BYTES 0-62 64 65-71 72 MANUFACTURER'S JEDEC ID CODE MANUFACTURER'S JEDEC ID CODE (continued) MANUFACTURING LOCATION 73-90 91 MODULE PART NUMBER (ASCII) PCB IDENTIFICATION CODE 92 93 94 95-98 99-127 IDENTIFICATION CODE (continued) YEAR OF MANUFACTURE IN BCD WEEK OF MANUFACTURE IN BCD MODULE SERIAL NUMBER MANUFACTURER-SPECIFIC DATA (RSVD) Initial Release 0.0 -262 -265 -202 MICRON x x 1 01 02 03 04 05 06 07 08 09 01 02 03 04 05 06 07 08 09 0 00 00 x x x x x x - - NOTE: 1. "1"/"0": Serial Data, "driven to HIGH"/"driven to LOW." 2. x = Variable Data. 16, 32 Meg x 72 DDR Registered SDRAM DIMMs ZM44.p65 - Rev. 4/00 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. ADVANCE 16, 32 MEG x 72 DDR REGISTERED SDRAM DIMMs Commands commands and operations, refer to the 64Mb or 128Mb: x4 SDRAM data sheet. Truth Table 1 provides a general reference of available commands. For a more detailed description of TRUTH TABLE 1A - COMMANDS (Note: 1) NAME (FUNCTION) CS# RAS# CAS# WE# ADDR NOTES DESELECT (NOP) H X X X X 9 NO OPERATION (NOP) L H H H X 9 ACTIVE (Select bank and activate row) L L H H Bank/Row 3 READ (Select bank and column, and start READ burst) L H L H Bank/Col 4 WRITE (Select bank and column, and start WRITE burst) L H L L Bank/Col 4 BURST TERMINATE L H H L X 8 PRECHARGE (Deactivate row in bank or banks) L L H L Code 5 AUTO REFRESH or SELF REFRESH (Enter self refresh mode) L L L H X 6, 7 LOAD MODE REGISTER L L L L Op-Code 2 TRUTH TABLE 1B - DM OPERATION (Note: 10) NAME (FUNCTION) DM DQs Write Enable L Valid Write Inhibit H X NOTE: 1. CKE is HIGH for all commands shown except SELF REFRESH. 2. BA0-BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register; BA0 = 1, BA1 = 0 select extended mode register; other combinations of BA0-BA1 are reserved). A0-A11 provide the op-code to be written to the selected mode register. 3. BA0-BA1 provide bank address and A0-A11 provide row address. 4. BA0-BA1 provide bank address; A0-A8 provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), and A10 LOW disables the auto precharge feature. 5. A10 LOW: BA0-BA1 determine which bank is precharged. A10 HIGH: all banks are precharged and BA0-BA1 are "Don't Care." 6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW. 7. Internal refresh counter controls row addressing; all inputs and I/Os are "Don't Care" except for CKE. 8. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for READ bursts with auto precharge enabled and for WRITE bursts. 9. DESELECT and NOP are functionally interchangeable. 10. Used to mask write data; provided coincident with the corresponding data. 16, 32 Meg x 72 DDR Registered SDRAM DIMMs ZM44.p65 - Rev. 4/00 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. ADVANCE 16, 32 MEG x 72 DDR REGISTERED SDRAM DIMMs BA0 BA1 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 13 12 0* 0* 11 10 9 8 7 6 5 4 3 2 1 0 Operating Mode CAS Latency BT Burst Length * M13 and M12 (BA0 and BA1) must be "0, 0" to select the base mode register (vs. the extended mode register). Table 1 Burst Definition Address Bus Mode Register (Mx) Burst Length Burst Length M2 M1 M0 M3 = 0 M3 = 1 0 0 0 Reserved Reserved 0 0 1 2 2 0 1 0 4 4 0 1 1 8 8 1 0 0 Reserved Reserved 1 0 1 Reserved Reserved 1 1 0 Reserved Reserved 1 1 1 Reserved Reserved 2 4 Burst Type M3 0 Sequential 1 Interleaved 8 CAS Latency M6 M5 M4 0 0 0 Reserved 0 0 1 Reserved 0 1 0 2 0 1 1 Reserved 1 0 0 Reserved 1 0 1 Reserved 1 1 0 2.5 1 1 1 Reserved M11 M10 M9 M8 M7 M6-M0 0 0 0 0 Valid Normal Operation 0 0 0 1 0 Valid Normal Operation/Reset DLL - - - - - - Order of Accesses Within a Burst Type=Sequential Type=Interleaved 0-1 1-0 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 NOTE: 1. For a burst length of two, A1-A8 select the twodata-element block; A0 selects the first access within the block. 2. For a burst length of four, A2-A8 select the fourdata-element block; A0-A1 select the first access within the block. 3. For a burst length of eight, A3-A8 select the eightdata-element block; A0-A2 select the first access within the block. 4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. Operating Mode 0 StartingColumn Address A0 0 1 A1 A0 0 0 0 1 1 0 1 1 A2 A1 A0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 All other states reserved Figure 4 Mode Register Definition 16, 32 Meg x 72 DDR Registered SDRAM DIMMs ZM44.p65 - Rev. 4/00 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. ADVANCE 16, 32 MEG x 72 DDR REGISTERED SDRAM DIMMs ABSOLUTE MAXIMUM RATINGS* *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. VDD Supply Voltage Relative to VSS ........ -1V to +3.6V VDDQ Supply Voltage Relative to VSS .... -1V to +3.6V VREF and Inputs Voltage Relative to VSS ..................................... -1V to +3.6V I/O Pins Voltage Relative to VSS ....................... -0.5V to VDDQ +0.5V Operating Temperature, TA (ambient) ... 0C to +70C Storage Temperature (plastic) ........... -55C to +150C Power Dissipation ................................................. 18W Short Circuit Output Current ............................ 50mA 16, 32 Meg x 72 DDR Registered SDRAM DIMMs ZM44.p65 - Rev. 4/00 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. ADVANCE 16, 32 MEG x 72 DDR REGISTERED SDRAM DIMMs DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (Notes: 1-5, 6) (0C TA +70C; VDD = +2.5V 0.2V, VDDQ = +2.5V 0.2V) PARAMETER/CONDITION SYMBOL MIN MAX VDD 2.3 2.7 V Supply Voltage I/O Supply Voltage UNITS NOTES VDDQ 2.3 2.7 V I/O Reference Voltage VREF 0.49 x VDDQ 0.51 x VDDQ V 7 I/O Termination Voltage (system) VTT VREF - 0.04 VREF + 0.04 V 8 Input High (Logic 1) Voltage VIH VREF + 0.18 VDD + 0.3 V 9 Input Low (Logic 0) Voltage VIL -0.3 VREF - 0.18 V 9 Clock Input Voltage Level; CK0 and CK0# VIN -0.3 VDDQ + 0.3 V Clock Input Differential Voltage; CK0 and CK0# VID 0.36 VDDQ + 0.6 V 10 Clock Input Crossing Point Voltage; CK0 and CK0# VIX 1.15 1.35 V 11 II -5 5 A 12 IOZ -5 5 A 13 IOH IOL -16.8 16.8 - - mA mA INPUT LEAKAGE CURRENT Any input 0V VIN VDD (All other pins not under test = 0V) OUTPUT LEAKAGE CURRENT (DQs are disabled; 0V VOUT VDDQ) OUTPUT LEVELS Output High Current (VOUT = 1.95V, maximum VTT) Output Low Current (VOUT = 0.35V, minimum VTT) NOTE: 1. All voltages referenced to VSS. 2. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. VTT 3. Outputs measured with equivalent load (QFC# is x4 only): Output (VOUT) VTT 50 Reference Point 30pF QFC# (VOUT) 75 Reference Point 15pF 4. AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK/CK#), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals used to test the device is 1V/ ns in the range between VIL(AC) and VIH(AC). 5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above [below] the DC input LOW [HIGH] level). 6. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE 0.3 x VDDQ is recognized as LOW. 7. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in the DC level of the same. Peakto-peak noise on VREF may not exceed 2 percent of the DC value. Thus, from VDDQ/2, VREF is allowed 25mV for DC error and 25mV for AC noise. 8. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF. 9. The DC values define where the input slew rate requirements are imposed, and the input signal must not violate these levels in order to maintain a valid level. The inputs require the AC value to be achieved during signal transition edge and the driver should achieve the same slew rate through the AC values. 10. VID is the magnitude of the difference between the input level on CK and the input level on CK#. 11. The value of VIX is expected to equal VDDQ/2 of the transmitting device and must track variations in the DC level of the same. 12. Referenced to each output group: x4 = DQS with DQ0-DQ3, x8 = DQS with DQ0-DQ7, x16 = LDQS with DQ0-DQ7 and UDQS with DQ8-DQ15. 13. The Input capacitance per pin group will not differ by more than this maximum amount for any given device. 16, 32 Meg x 72 DDR Registered SDRAM DIMMs ZM44.p65 - Rev. 4/00 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. ADVANCE 16, 32 MEG x 72 DDR REGISTERED SDRAM DIMMs AC OPERATING CONDITIONS (Notes: 1-5, 6, 7) (0C TA +70C; VDD = +2.5V 0.2V, VDDQ = +2.5V 0.2V) PARAMETER/CONDITION SYMBOL MIN MAX Input High (Logic 1) Voltage; DQ, DQS and DM signals VIH(AC) VREF + 0.310 - UNITS NOTES V 8, 9 Input Low (Logic 0) Voltage; DQ, DQS and DM signals VIL(AC) - VREF - 0.310 V 8, 9 Clock Input Differential Voltage; CK and CK# VID(AC) 0.7 VDDQ + 0.6 V 10 Clock Input Crossing Point Voltage; CK and CK# VIX(AC) 0.5 x VDDQ - 0.2 0.5 x VDDQ + 0.2 V 11 NOTE: 1. All voltages referenced to VSS. 2. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. VTT 3. Outputs measured with equivalent load (QFC# is x4 only): Output (VOUT) VTT 50 Reference Point 30pF QFC# (VOUT) 75 Reference Point 15pF 4. AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK/CK#), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals used to test the device is 1V/ ns in the range between VIL(AC) and VIH(AC). 5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above [below] the DC input LOW [HIGH] level). 6. Input slew rate = 1V/ns. If the slew rate exceeds the maximum specified by 20 percent, functionality is uncertain. If the slew rate exceeds the minimum specified, timing is no longer referenced to the mid-point but to the VIL(AC) maximum and VIH(AC) minimum points. For slew rates between 0.5V/ns and 1V/ns, tIS and tIH must be increased by at least 20 percent. 7. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE 0.3 x VDDQ is recognized as LOW. 8. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in the DC level of the same. Peakto-peak noise on VREF may not exceed 2 percent of the DC value. Thus, from VDDQ/2, VREF is allowed 25mV for DC error and 25mV for AC noise. 9. VID is the magnitude of the difference between the input level on CK and the input level on CK#. 10. The value of VIX is expected to equal VDDQ/2 of the transmitting device and must track variations in the DC level of the same. 11. IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open. 16, 32 Meg x 72 DDR Registered SDRAM DIMMs ZM44.p65 - Rev. 4/00 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. ADVANCE 16, 32 MEG x 72 DDR REGISTERED SDRAM DIMMs IDD SPECIFICATIONS AND CONDITIONS (Notes: 1-5, 6, 7, 8) (0C TA +70C; VDDQ = +2.5V 0.2V, VDD = +2.5V 0.2V) MAX PARAMETER/CONDITION SYMBOL SIZE OPERATING CURRENT: One bank; Active-Precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM and DQS inputs changing IDD0 twice per clock cyle; Address and control inputs changing once per clock cycle; CL = 2.5 -262 -265 -202 UNITS NOTES 128MB 1,620 1,440 1,260 256MB 1,800 1,620 1,260 128MB 2,070 1,890 1,620 256MB 2,160 2,070 1,620 mA 9 mA 9 OPERATING CURRENT: One bank; Active-Read-Precharge; Burst = 2; tRC = tRC (MIN); CL = 2.5; tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle IDD1 PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle; Power-down mode; CKE = LOW; tCK = tCK (MIN) IDD2P 128MB 256MB 90 90 90 90 90 90 mA IDLE STANDBY CURRENT: CS# = HIGH; All banks idle; CKE = HIGH; tCK = tCK (MIN); Address and other control inputs changing once per clock cycle IDD2N 128MB 900 900 720 mA 256MB 630 630 540 ACTIVE POWER-DOWN STANDBY CURRENT: One bank active; Power-down mode; CKE = LOW; tCK = tCK (MIN) IDD3P 128MB 256MB 126 126 126 126 126 126 mA ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One bank; Active-Precharge; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle IDD3N 128MB 900 900 720 mA 256MB 360 360 360 OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; CL = 2.5; tCK = tCK (MIN); IOUT = 0mA IDD4R 128MB 2,340 2,250 2,070 256MB 1,800 1,800 1,620 OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; CL = 2.5; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle IDD4W 128MB 2,070 1,890 1,800 256MB 1,800 1,800 1,620 128MB 2,520 2,340 2,250 256MB 4,140 3,780 3,240 128MB 90 90 90 256MB 90 90 90 128MB 18 18 36 256MB 36 36 54 128MB 10.8 10.8 10.8 256MB 18 18 18 AUTO REFRESH CURRENT SELF REFRESH CURRENT: CKE 0.2V tRC = tRFC (MIN) IDD5 tRC = 15.625s IDD6 Standard IDD7 Low power (L) IDD7 9 mA mA mA 9 mA 10 mA 11 mA 11 NOTE: 1. All voltages referenced to VSS. 2. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. VTT 3. Outputs measured with equivalent load (QFC# is x4 only): Output (VOUT) VTT 50 Reference Point 30pF QFC# (VOUT) 75 Reference Point 15pF (notes continued on following page) 16, 32 Meg x 72 DDR Registered SDRAM DIMMs ZM44.p65 - Rev. 4/00 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. ADVANCE 16, 32 MEG x 72 DDR REGISTERED SDRAM DIMMs NOTE (continued): 4. AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK/CK#), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals used to test the device is 1V/ ns in the range between VIL(AC) and VIH(AC). 5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above [below] the DC input LOW [HIGH] level). 6. IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open. 7. IDD specifications are tested after the device is properly initialized. 8. Command/Address input slew rate =0.5V/ns. For -7and -75 with slew rates 1V/ns or faster, tIS and tIH are reduced to 900 ps. If the slew rate is less than 0.5V/ns, timing is no longer referenced to the mid-point but to the VIL(AC) maximum and VIH(AC) minimum points.If the slew rate exceeds 3V/ns, functionality is uncertain. 9. MIN (tRC or tRFC) for IDD measurements is the smallest multiple of tCK that meets the minimum absolute value for the respective parameter. tRAS MAX for IDD measurements is the largest multiple of tCK that meets the maximum absolute value for tRAS. 10. This limit is actually a nominal value and does not result in a fail value. CKE is HIGH during REFRESH command period (tRFC [MIN]) else CKE is LOW (i.e., during standby). 11. Enables on-chip refresh and address counters. CAPACITANCE (Note: 1) PARAMETER 128MB 256MB SYMBOL MIN MAX MIN MAX UNITS NOTES Input/Output Capacitance: DQs, DQSs, DMs, CBs CIO 5.0 7.0 10.0 14.0 pF Input Capacitance: CK, CK# CI 1 - 3.0 - 3.0 pF 2 Input Capacitance: All other input-only pins CI 2 - 4.0 - 4.0 pF 2 NOTE: 1. All voltages referenced to VSS. 2. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 16, 32 Meg x 72 DDR Registered SDRAM DIMMs ZM44.p65 - Rev. 4/00 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. ADVANCE 16, 32 MEG x 72 DDR REGISTERED SDRAM DIMMs ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Notes: 1-5, 7-9) (0C TA +70C; VDDQ = +2.5V 0.2V, VDD = +2.5V 0.2V) AC CHARACTERISTICS PARAMETER SYMBOL tAC Access window of DQs from CK/CK# tCH CK high-level width tCL CK low-level width tCK Clock cycle time CL = 2.5 tCK CL = 2 tDAL Auto precharge write recovery plus precharge time tDH DQ and DM input hold time relative to DQS tDS DQ and DM input setup time relative to DQS tDIPW DQ and DM input pulse width (for each input) tDQSCK Access window of DQS from CK/CK# tDQSH DQS input high pulse width tDQSL DQS input low pulse width DQS-DQ skew, DQS to last DQ valid, per group, per access tDQSQ tDQSQA DQS-DQ skew, first DQS to last DQ valid, per access tDQSS Write command to first DQS latching transition tDSS DQS falling edge to CK rising - setup time tDSH DQS falling edge from CK rising - hold time tHP Half clock period tHZ Data-out high-impedance window from CK/CK# tLZ Data-out low-impedance window from CK/CK# tIH Address and control input hold time t IS Address and control input setup time tIPW Address and control input pulse width tMRD LOAD MODE REGISTER command cycle time tQH DQ-DQS hold, DQS to first DQ to go non-valid, per access -262 MIN MAX -0.75 +0.75 0.45 0.55 0.45 0.55 7 15 7.5 15 35 0.5 0.5 1.75 -0.75 +0.75 0.35 0.35 0.5 0.7 0.75 1.25 0.2 0.2 tCH,tCL -0.75 +0.75 -0.75 +0.75 1 1 2.2 15 tHP - 0.75ns -265 MIN MAX -0.75 +0.75 0.45 0.55 0.45 0.55 7.5 15 10 15 35 0.5 0.5 1.75 -0.75 +0.75 0.35 0.35 0.5 0.7 0.75 1.25 0.2 0.2 tCH,tCL -0.75 +0.75 -0.75 +0.75 1 1 2.2 15 tHP - 0.75ns MIN -0.8 0.45 0.45 8 10 35 0.6 0.6 2 -0.8 0.35 0.35 -202 MAX +0.8 0.55 0.55 15 15 0.75 0.2 0.2 tCH,tCL -0.8 -0.8 1.1 1.1 2.5 16 tHP - 1ns +0.8 0.6 0.8 1.25 +0.8 +0.8 UNITS ns tCK tCK ns ns ns ns ns ns ns tCK tCK ns ns tCK tCK tCK ns ns ns ns ns ns ns ns NOTES 10 10 11, 12 11, 12 12 11, 13 14 14 11, 13 1. All voltages referenced to VSS. 2. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. VTT 3. Outputs measured with equivalent load (QFC# is x4 only): Output (VOUT) VTT 50 Reference Point 30pF QFC# (VOUT) 75 Reference Point 15pF 4. AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK/CK#), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals used to test the device is 1V/ ns in the range between VIL(AC) and VIH(AC). 5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above [below] the DC input LOW [HIGH] level). 6. Input slew rate = 1V/ns. If the slew rate exceeds the maximum specified by 20 percent, functionality is uncertain. If the slew rate exceeds the minimum specified, timing is no longer referenced to the mid-point but to the VIL(AC) maximum and VIH(AC) minimum points. For slew rates between 0.5V/ns and 1V/ns, tIS and tIH must be increased by at least 20 percent. 7. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which CK and CK# cross; the input reference level for signals other than CK/CK# is VREF. 8. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE 0.3 x VDDQ is recognized as LOW. (continued on following page) 16, 32 Meg x 72 DDR Registered SDRAM DIMMs ZM44.p65 - Rev. 4/00 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. ADVANCE 16, 32 MEG x 72 DDR REGISTERED SDRAM DIMMs ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (continued) (Notes: 1-5, 7-9) (0C TA +70C; VDDQ = +2.5V 0.2V, VDD = +2.5V 0.2V) AC CHARACTERISTICS PARAMETER QFC# write preamble, output referenced from CK/CK# QFC# write postamble, output hold QFC# read preamble (CL = 2 or 2.5) QFC# read postamble ACTIVE to PRECHARGE command ACTIVE to ACTIVE/AUTO REFRESH command period AUTO REFRESH command period REFRESH to REFRESH command interval Average periodic refresh interval ACTIVE to READ or WRITE delay PRECHARGE command period DQS read preamble - (CL = 2 or 2.5) DQS read postamble ACTIVE bank a to ACTIVE bank b command Data valid output window Terminating voltage delay to VDD DQS write preamble DQS write preamble setup time DQS write postamble Write recovery time Internal WRITE to READ command delay Exit SELF REFRESH to non-READ command Exit SELF REFRESH to READ command SYMBOL -262 MIN MAX tQCK tQOH 1.25 0.9 tQPRE tQPST 0.4 45 60 67 tRAS tRC tRFC tREFC .4 2 1.1 0.6 120,000 140.6 15.6 tREFI tRCD 15 15 0.9 1.1 0.4 0.6 15 tQH - tDQSQ 0 0.25 0 0.4 0.6 15 1 75 200 tRP tRPRE tRPST tRRD na tVTD tWPRE tWPRES tWPST tWR tWTR tXSNR tXSRD -265 MIN MAX 1.25 0.9 0.4 45 65 75 .4 2 1.1 0.6 120,000 140.6 15.6 20 20 0.9 1.1 0.4 0.6 15 tQH - tDQSQ 0 0.25 0 0.4 0.6 15 1 75 200 MIN 1.25 0.9 0.4 50 70 80 -202 MAX UNITS NOTES .4 2 1.1 ns ns tCK 0.6 120,000 tCK 140.6 15.6 20 20 0.9 1.1 0.4 0.6 15 tQH - tDQSQ 0 0.25 0 0.4 0.6 15 1 80 200 ns ns ns s s ns ns tCK tCK ns ns ns tCK ns tCK ns tCK ns tCK 15 15 13 16, 17 18 NOTE (continued): 9. The output timing reference level, as measured at the timing reference point indicated in Note 3, is VTT. 10. CK and CK# input slew rate must be 1V/ns. 11. Referenced to each output group: x4 = DQS with DQ0-DQ3, x8 = DQS with DQ0-DQ7, x16 = LDQS with DQ0-DQ7 and UDQS with DQ8-DQ15. 12. DQ and DM input slew rates must not deviate from DQS by more than 10%. If the DQ/DM/DQS slew rate is less than 0.5V/ns, timing is no longer referenced to the mid-point but to the VIL(AC) maximum and VIH(AC) minimum points. 13. The valid data window is derived by achieving other specifications - tHP (tCK/2), tDQSQ, and tQH [tHP - 750ps (-7, -75) or t HP - 1ns (-8)]. The data valid window derates directly porportional with the clock duty cycle and a practical data valid window can be derived. The clock is allowed a maximum duty cycle variation of 45/55. Functionality is uncertain when operating beyond a 45/55 ratio. The data valid window derating curves are provided below for duty cycles ranging between 50/50 and 45/55. 14. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (HZ) or begins driving (LZ). 15. The refresh period 64ms. This equates to an average refresh rate of 15.625s. However, an AUTO REFRESH command must be asserted at least once every 31.2s; burst refreshing or postings greater than 2 are not allowed. 16. This is not a device limit. The device will operate with a negative value, but system performance could be degraded due to bus turnaround. 17. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The case shown (DQS going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in progress, DQS could be HIGH during this time, depending on tDQSS. 18. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 16, 32 Meg x 72 DDR Registered SDRAM DIMMs ZM44.p65 - Rev. 4/00 17 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. ADVANCE 16, 32 MEG x 72 DDR REGISTERED SDRAM DIMMs REGISTER TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS (Note: 1) TA = 0-70 C VDD = 2.5V 0.2V REGISTER SYMBOL Clock Frequency t PD Clock to Output Time t RST Reset to Output Time tS L 1:1 14 bit SSTL PARAMETER t CK CONDITIONS 30pF to GND and 50 ohms to VTT MAX 60 170 UNITS NOTES MHz 1.1 2.7 ns - 5 ns 0.5 4 V/ns Setup time, fast slew rate (see Notes 1 and 3) - 0.75 ns 2, 4 Setup time, slow slew rate (see Notes 2 and 3) - 0.9 ns 3, 4 Hold time, fast slew rate (see Notes 1 and 3) - 0.75 ns 2, 4 Hold time, slow slew rate (see Notes 2 and 3) - 0.9 ns 3, 4 CIN(CK) Clock Input Capacitance 2.5 3.5 pF CIN(data) Clock Input Capacitance 2.5 3.5 pF t su th Output Slew Rate MIN NOTE: 1. The timing specifications for the register listed above are critical for proper operation of the DDR SDRAM Registered DIMMs. These are meant to be a subset of the parameters for the specific device used on the module. Detailed information on this part has been shown at the JEDEC JC-40 Committee. Please contact Micron Technology's Module Applications Team if further information on the specific register model is required. 2. For data signal, input slew rate 1 V/ns. 3. For data signal, input slew rate 0.5 V/ns and < 1 V/ns. 4. For CK and CK# signals, input slew rates are 1 V/ns. 16, 32 Meg x 72 DDR Registered SDRAM DIMMs ZM44.p65 - Rev. 4/00 18 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. ADVANCE 16, 32 MEG x 72 DDR REGISTERED SDRAM DIMMs PLL CLOCK DRIVER TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS (Specifications for the PLL component used on the module.) PARAMETER Clock frequency SYMBOL TEST CONDITIONS fC Input clock duty cycle Stabilization MIN NOM MAX UNITS 66 167 40% 60% time1 MHz 0.1 ms 3.5 6 ns 3.5 6 ns Low-to high level propagation delay time t PLH CK mode/CK to any output 1.5 High-to low level propagation delay time t PHL CK mode/CK to any output 1.5 Output enable time t en CK mode/G to any Y output 3 ns Output disable time t dis CK mode/G to any Y output 3 ns Jitter (peak-to-peak) t(jitter) Jitter (cycle-to-cycle) t(jitter) Phase error t (phase 66 MHz 120 100/125/133/167 MHz 75 66 MHz 110 100/125/133/167 MHz 65 Terminated with 120 ohm/16pF -150 ps ps 150 ns error) Output skew Pulse skew tskew(o) Terminated with 120 ohm/16pF 100 ns t dis Terminated with 120 ohm/16pF 100 ns Duty cycle Output rise and fall times (20% - 80%) NOTE: tr, tf 66 MHz to 100 MHz 49.5% 101 MHz to 167 MHz 49% Load = 120 ohm/16pF 650 50.5% 51% 800 950 ps 1. Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. 16, 32 Meg x 72 DDR Registered SDRAM DIMMs ZM44.p65 - Rev. 4/00 19 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. ADVANCE 16, 32 MEG x 72 DDR REGISTERED SDRAM DIMMs SERIAL PRESENCE-DETECT EEPROM DC OPERATING CONDITIONS (Note: 1) (VDD = +2.5V 0.2V) PARAMETER/CONDITION SYMBOL MIN MAX UNITS SUPPLY VOLTAGE VDD 2.3 2.7 V INPUT HIGH VOLTAGE: Logic 1; All inputs VIH INPUT LOW VOLTAGE: Logic 0; All inputs VIL -1 VDD x 0.3 OUTPUT LOW VOLTAGE: IOUT = 3mA VDD x 0.7 VDD + 0.5 V V VOL - 0.4 V INPUT LEAKAGE CURRENT: VIN = GND to VDD ILI - 10 A OUTPUT LEAKAGE CURRENT: VOUT = GND to VDD ILO - 10 A STANDBY CURRENT: SCL = SDA = VDD - 0.2V; All other inputs = GND or 2.5V +10% ISB - 30 A POWER SUPPLY CURRENT: SCL clock frequency = 100 KHz ICC - 2 mA MIN 0.3 4.7 300 MAX 3.5 UNITS s s ns ns s s s ns s s KHz ns s s ms SERIAL PRESENCE-DETECT EEPROM AC OPERATING CONDITIONS (Note: 1) (VDD = +2.5V 0.2V) PARAMETER/CONDITION SCL LOW to SDA data-out valid Time the bus must be free before a new transition can start Data-out hold time SDA and SCL fall time Data-in hold time Start condition hold time Clock HIGH period Noise suppression time constant at SCL, SDA inputs Clock LOW period SDA and SCL rise time SCL clock frequency Data-in setup time Start condition setup time Stop condition setup time WRITE cycle time SYMBOL tAA tBUF tDH tF tHD:DAT tHD:STA tHIGH tI tLOW tR tSCL tSU:DAT tSU:STA tSU:STO tWRC 300 0 4 4 100 4.7 1 100 250 4.7 4.7 10 NOTE: 1. The refresh period is 64ms. This equates to an average refresh rate of 15.625s. However, an AUTO REFRESH command must be asserted at least once every 31.2s; burst refreshing or postings greater than 2 are not allowed. 16, 32 Meg x 72 DDR Registered SDRAM DIMMs ZM44.p65 - Rev. 4/00 20 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. ADVANCE 16, 32 MEG x 72 DDR REGISTERED SDRAM DIMMs SPD EEPROM tF t HIGH tR t LOW SCL t HD:STA t SU:STA t SU:DAT t HD:DAT t SU:STO SDA IN t DH t AA t BUF SDA OUT UNDEFINED SERIAL PRESENCE-DETECT EEPROM TIMING PARAMETERS SYMBOL tAA tBUF tDH tF tHD:DAT tHD:STA 16, 32 Meg x 72 DDR Registered SDRAM DIMMs ZM44.p65 - Rev. 4/00 MIN 0.3 4.7 300 MAX 3.5 300 0 4 UNITS s s ns ns s s SYMBOL tHIGH tLOW tR tSU:DAT tSU:STA tSU:STO 21 MIN 4 4.7 MAX 1 250 4.7 4.7 UNITS s s s ns s s Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. ADVANCE 16, 32 MEG x 72 DDR REGISTERED SDRAM DIMMs 184-PIN DIMM (128MB and 256MB) FRONT VIEW .157 (4.00) MAX 5.256 (133.50) 5.244 (133.20) 1.705 (43.31) 1.695 (43.05) .079 (2.00) R (4X) .700 (17.78) TYP. .098 (2.50) D (2X) .091 (2.30) TYP. PIN 1 (93 on back) .091 (2.30) TYP. .035 (0.90) R .050 (1.27) TYP. 2.55 (64.77) .040 (1.02) TYP. .394 (10.00) TYP. .250 (6.35) TYP. 1.95 (49.53) 4.750 (120.65) .054 (1.37) .046 (1.17) PIN 92 (184 on back) NOTE: 1. All dimensions in inches (millimeters) MAX or typical where noted. MIN 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron is a registered trademark of Micron Technology, Inc. 16, 32 Meg x 72 DDR Registered SDRAM DIMMs ZM44.p65 - Rev. 4/00 22 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.