MT18VDDT1672G-265XX - Micron Technology, Inc.

16, 32 MEG x 72

DDR REGISTERED SDRAM DIMMs

ADVANCE

16, 32 Meg x 72 DDR Registered SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.

PIN ASSIGNMENT

DDR SDRAM

DIMM MODULE

MT18VDDT1672G, MT18VDDT3272G

For the latest data sheet, please refer to the Micron

Web site: www.micron.com/mti/msp/html/

datasheet.html

FEATURES

• 184-pin, dual in-line memory modules (DIMM)

• Registered inputs with one-clock delay

• Phase-lock loop (PLL) clock driver to reduce

• Utilizes 100 MHz and 133 MHz DDR SDRAM

components

• ECC-optimized pinout

• 128MB (16 Meg x 72), 256MB (32 Meg x 72)

•VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V

•VDDSPD = +2.5V to +3.3V

• 2.5V I/O (SSTL_2 compatible)

• Commands entered on each positive CK edge

• DQS edge-aligned with data for READs; center-

aligned with data for WRITEs

• Internal, pipelined double data rate (DDR)

architecture; two data accesses per clock cycle

• Bidirectional data strobe (DQS) transmitted/

received with data, i.e., source-synchronous data

capture

• Differential clock inputs (CK0 and CK0#)

• Four internal banks for concurrent operation

• Programmable burst lengths: 2, 4, or 8

• Auto precharge option

• Auto Refresh and Self Refresh Modes

• 15.6µs maximum average periodic refresh interval

OPTIONS MARKING

• Package G

184-pin DIMM (gold)

• Frequency/CAS Latency*

266 MHz/CL = 2 -262

(133 MHz DDR SDRAMs)

266 MHz/CL = 2.5 -265

(133 MHz DDR SDRAMs)

200 MHz/CL = 2 -202

(100 MHz DDR SDRAMs)

*Device latency only; extra clock cycle required due to input

184-Pin DIMM

NOTE: Symbols in parentheses are not used on this module

but may be used for other modules in this product

family. They are for reference only.

PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL

1VREF 47 DQS8 93 VSS 139 VSS

2 DQ0 48 A0 94 DQ4 140 DQS17

3VSS 49 CB2 95 DQ5 141 A10

4 DQ1 50 VSS 96 VDDQ 142 CB6

5 DQS0 51 CB3 97 DQS9 143 VDDQ

6 DQ2 52 BA1 98 DQ6 144 CB7

7VDD 53 DQ32 99 DQ7 145 VSS

8 DQ3 54 VDDQ 100 VSS 146 DQ36

9NC55 DQ33 101 N C 147 DQ37

10 RESET# 56 DQS4 102 NC 148 VDD

11 VSS 57 DQ34 103 NC (A13)149 DQS13

12 DQ8 58 VSS 104 VDDQ150 DQ38

13 DQ9 59 BA0 105 DQ12 151 DQ39

14 DQS1 60 DQ35 106 DQ13 152 VSS

15 VDDQ61 DQ40 107 DQS10 153 DQ44

16 D N U 62 VDDQ 108 VDD 154 RAS#

17 D N U 63 WE# 109 DQ14 155 DQ45

18 VSS 64 DQ41 110 DQ15 156 VDDQ

19 DQ10 65 CAS# 111 CKE1 157 S0#

20 DQ11 66 VSS 112 VDDQ 158 NC (S1#)

21 CKE0 67 DQS5 113 NC (BA2) 159 DQS14

22 VDDQ68 DQ42 114 DQ20 160 VSS

23 DQ16 69 DQ43 115 NC (A12)161 DQ46

24 DQ17 70 VDD 116 VSS 162 DQ47

25 DQS2 71 DNU 117 DQ21 163 DNU

26 VSS 72 DQ48 118 A11 164 VDDQ

27 A9 73 DQ49 119 DQS11 165 DQ52

28 DQ18 74 VSS 120 VDD 166 DQ53

29 A7 75 DNU 121 DQ22 167

NC (FETEN)

30 VDDQ 76 DNU 122 A8 168 VDD

31 DQ19 77 VDDQ123 DQ23 169 DQS15

32 A5 78 DQS6 124 VSS 170 DQ54

33 DQ24 79 DQ50 125 A6 171 DQ55

34 VSS 80 DQ51 126 DQ28 172 VDDQ

35 DQ25 81 VSS 127 DQ29 173 N C

36 DQS3 82 VDDID 128 VDDQ174 DQ60

37 A4 83 DQ56 129 DQS12 175 DQ61

38 VDD 84 DQ57 130 A3 176 VSS

39 DQ26 85 VDD 131 DQ30 177 DQS16

40 DQ27 86 DQS7 132 VSS 178 DQ62

41 A2 87 DQ58 133 DQ31 179 DQ63

42 VSS 88 DQ59 134 CB4 180 VDDQ

43 A1 89 VSS 135 CB5 181 SA0

44 CB0 90 WP 136 VDDQ 182 SA1

45 CB1 91 SDA 137 CK0 183 SA2

46 VDD 92 SCL 138 CK0# 184 VDDSPD

16, 32 MEG x 72

DDR REGISTERED SDRAM DIMMs

ADVANCE

16, 32 Meg x 72 DDR Registered SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.

GENERAL DESCRIPTION

The MT18VDDT1672 and MT18VDDT3272 are

high-speed CMOS, dynamic random-access, 128MB

and 256MB memories organized in a x72 configura-

tion. These modules use internally configured quad-

bank DDR SDRAMs.

The DDR SDRAM modules use a double data rate

architecture to achieve high-speed operation. The

double data rate architecture is essentially a 2n-prefetch

architecture with an interface designed to transfer two

data words per clock cycle at the I/O pins. A single read

or write access for the DDR SDRAM module effectively

consists of a single 2n-bit wide, one-clock-cycle data

transfer at the internal DRAM core and two corre-

sponding n-bit wide, one-half-clock-cycle data trans-

fers at the I/O pins.

A bidirectional data strobe (DQS) is transmitted

externally, along with data, for use in data capture at

the receiver. DQS is an intermittent strobe transmitted

by the DDR SDRAM during READs and by the memory

controller during WRITEs. DQS is edge-aligned with

data for READs and center-aligned with data for

WRITEs.

The DDR SDRAM modules operate from a differen-

tial clock (CK0 and CK0#); the crossing of CK0 going

HIGH and CK0# going LOW will be referred to as the

positive edge of CK0. Commands (address and control

signals) are registered at every positive edge of CK0.

Input data is registered on both edges of DQS, and

output data is referenced to both edges of DQS, as well

as to both edges of CK0.

Read and write accesses to the DDR SDRAM mod-

ules are burst oriented; accesses start at a selected

location and continue for a programmed number of

locations in a programmed sequence. Accesses begin

with the registration of an ACTIVE command, which

is then followed by a READ or WRITE command. The

address bits registered coincident with the ACTIVE

command are used to select the bank and row to be

accessed. The address bits registered coincident with the

READ or WRITE command are used to select the bank

and the starting column location for the burst access.

The DDR SDRAM modules provide for program-

mable READ or WRITE burst lengths of 2, 4, or 8

locations. An auto precharge function may be enabled

to provide a self-timed row precharge that is initiated

at the end of the burst access.

As with standard SDR SDRAM modules, the

pipelined, multibank architecture of DDR SDRAM

modules allows for concurrent operation, thereby pro-

viding high effective bandwidth by hiding row precharge

and activation time.

An auto refresh mode is provided, along with a

power-saving power-down mode. All inputs are com-

patible with the JEDEC Standard for SSTL_2. All out-

puts are SSTL_2, Class II compatible. For more informa-

tion regarding DDR SDRAM operation, refer to the

64Mb and 128Mb x 4 x 4 DDR SDRAM data sheets.

PLL AND REGISTER OPERATION

The DDR SDRAM module is operated in registered

mode where the control/address input signals are latched

in the register on one rising clock edge and sent to the

DDR SDRAM devices on the following rising clock edge

(data access is delayed by one clock). A phase-lock loop

(PLL) on the module is used to redrive the differential

clock signals CK0 and CK0# to the DDR SDRAM devices

to minimize system clock loading.

SERIAL PRESENCE-DETECT OPERATION

The DDR SDRAM module incorporates serial pres-

ence-detect (SPD). The SPD function is implemented

using a 2,048-bit EEPROM. This nonvolatile storage

device contains 256 bytes. The first 128 bytes can be

programmed by Micron to identify the module type and

various SDRAM organizations and timing parameters.

The remaining 128 bytes of storage are available for use

by the customer. System READ/WRITE operations be-

tween the master (system logic) and the slave EEPROM

device (DIMM) occur via a standard IIC bus using the

DIMM’s SCL (clock) and SDA (data) signals, together

with SA(2:0), which provide eight unique DIMM/

EEPROM addresses.

KEY DDR SDRAM COMPONENT

TIMING PARAMETERS

MODULE SPEED CLOCK

MARKING GRADE RATE (1/tCK)

-262 -7 (7.5ns @ CL = 2) 133 MHz

-265 -7 (7.5ns @ CL = 2.5) 143 MHz

-202 -75 (10ns @ CL = 2) 100 MHz

*CL = CAS (READ) latency

PART NUMBERS

PART NUMBER CONFIGURATION SYSTEM BUS SPEED

MT18VDDT1672G-262__ 16 Meg x 72 CL = 2, 266 MHz

MT18VDDT1672G-265__ 16 Meg x 72 CL = 2.5, 266 MHz

MT18VDDT1672G-202__ 16 Meg x 72 CL = 2, 200 MHz

MT18VDDT3272G-262__ 32 Meg x 72 CL = 2, 266 MHz

MT18VDDT3272G-265__ 32 Meg x 72 CL = 2.5, 266 MHz

MT18VDDT3272G-202__ 32 Meg x 72 CL = 2, 200 MHz

NOTE: All part numbers end with a two-place code (not

shown), designating component and PCB revisions.

Consult factory for current revision codes.

Example: MT18VDDT1672G-262A1

16, 32 MEG x 72

DDR REGISTERED SDRAM DIMMs

ADVANCE

16, 32 Meg x 72 DDR Registered SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.

NOTE: 1. All resistor values are 22 ohms unless otherwise specified.

2. Reference designators in this diagram do not necessarily match the actual module.

RS0#

DQ0

DQ1

DQ2

DQ3

DQ0

DQ1

DQ2

DQ3

DM CS# DQS

DQ0

DQ1

DQ2

DQ3

DQ32

DQ33

DQ34

DQ35

DM CS# DQS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DM CS# DQS

U10

DQ0

DQ1

DQ2

DQ3

DQ36

DQ37

DQ38

DQ39

DM CS# DQS

DQ0

DQ1

DQ2

DQ3

DQ8

DQ9

DQ10

DQ11

DM CS# DQS

U11

DQ0

DQ1

DQ2

DQ3

DQ40

DQ41

DQ43

DM CS# DQS

DQ0

DQ1

DQ2

DQ3

DQ12

DQ13

DQ14

DQ15

DM CS# DQS

U12

DQ0

DQ1

DQ2

DQ3

DQ44

DQ45

DQ46

DQ47

DM CS# DQS

DQ0

DQ1

DQ2

DQ3

CB0

CB1

CB2

CB3

DM CS# DQS

U13

DQ0

DQ1

DQ2

DQ3

CB4

CB5

CB6

CB7

DM CS# DQS

DQ0

DQ1

DQ2

DQ3

DQ16

DQ17

DQ18

DQ19

DM CS# DQS

U14

DQ0

DQ1

DQ2

DQ3

DQ48

DQ49

DQ50

DQ51

DM CS# DQS

DQ0

DQ1

DQ2

DQ3

DQ20

DQ21

DQ22

DQ23

DM CS# DQS

U15

DQ0

DQ1

DQ2

DQ3

DQ52

DQ53

DQ54

DQ55

DM CS# DQS

DQ0

DQ1

DQ2

DQ3

DQ24

DQ25

DQ26

DQ27

DM CS# DQS

U16

DQ0

DQ1

DQ2

DQ3

DQ56

DQ57

DQ58

DQ59

DM CS# DQS

DQ0

DQ1

DQ2

DQ3

DQ28

DQ29

DQ30

DQ31

DM CS# DQS

U17

DQ0

DQ1

DQ2

DQ3

DQ60

DQ61

DQ62

DQ63

PLL

SDRAM X 2

CK0

CK0#

120

DM CS# DQS

VSS

DQS0

SA0

SERIAL PD

SDA

SA1

SA2

S0#

BA0, BA1

A0-A11

RAS#

RS0#

RBA0, RBA1: SDRAMS U0-U17

RA0-RA11: SDRAMS U0-U17

RRAS#: SDRAMS U0-U17

RCAS#: SDRAMS U0-U17

RCKE0: SDRAMS U0-U17

RWE#: SDRAMS U0-U17

CAS#

CKE0

WE#

REF

SDRAMS U0-U17

SCL

DDQ

SDRAMS U0-U17

U0-U17 = MT46V16M4A2TG SDRAMs for 128MB

U0-U17 = MT46V32M4A2TG SDRAMS for 256MB

DQS1

DQS2

DQS3

DQS4

DQS5

DQS7

DQS8

DQS6

DQS17

DQS16

DQS15

DQS14

DQS13

DQS12

DQS11

DQS10

DQS9

PCK

PCK# RESET# 47K

FUNCTIONAL BLOCK DIAGRAM

MT18VDDT1672 (128MB) and MT18VDDT3272 (256MB)

16, 32 MEG x 72

DDR REGISTERED SDRAM DIMMs

ADVANCE

16, 32 Meg x 72 DDR Registered SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.

PIN DESCRIPTIONS

PIN NUMBERS SYMBOL TYPE DESCRIPTION

63, 65, 154 WE#, CAS#, Input Command Inputs: RAS#, CAS# and WE# (along with

RAS# S0#, S1#) define the command being entered.

137, 138 CK0, CK0# Input Clock: CK0 and CK0# are differential clock inputs. All

address and control input signals are sampled on the

crossing of the positive edge of CK0 and negative

edge of CK0#. Output data (DQs and DQS) is

referenced to the crossings of CK0 and CK0#.

21, 111 CKE0, CKE1 Input Clock Enable: CKE0 and CKE1 activate (HIGH) and

deactivate (LOW) internal clock signals, and device

input buffers and output drivers. Deactivating the

clock provides PRECHARGE POWER-DOWN and SELF

REFRESH operation (all banks idle), or ACTIVE POWER-

DOWN (row ACTIVE in any bank). CKE0 and CKE1 are

synchronous for all functions except for disabling

outputs, which is achieved asynchronously. CKE0 and

CKE1 must be maintained HIGH throughout read and

write accesses. Input buffers (excluding CK0, CK0# and

CKE) are disabled during POWER-DOWN. Input buffers

(excluding CKE0 and CKE1) are disabled during SELF

REFRESH. CKE0 and CKE1 are SSTL_2 inputs but will

detect an LVCMOS LOW level after VDD is applied.

9, 101, 102, 103, 113, NC — No Connect: These pins should be left unconnected.

115, 158, 167, 173

157 S0# Input Chip Select: S0# enables (registered LOW) and disables

(registered HIGH) the command decoder. All com-

mands are masked when S0# is registered HIGH. S0#

provides for external bank selection on systems with

multiple banks. S0# is considered part of the command

code.

59, 52 BA0, BA1 Input Bank Address: BA0 and BA1 define to which bank an

ACTIVE, READ, WRITE or PRECHARGE command is

being applied.

48, 43, 41, 130, 37, 32, A0-A11 Input Address Inputs: A0-A11 are sampled during the ACTIVE

125, 29, 122, 27, 141, command (row-address A0-A11) and READ/WRITE

118 command (column-address A0-A8, with A10 defining

auto precharge) to select one location out of the

memory array in the respective bank. A10 is sampled

during a PRECHARGE command to determine whether

the PRECHARGE applies to one bank (A10 LOW) or all

banks (A10 HIGH). The address inputs also provide the

op-code during a MODE REGISTER SET command.

1VREF Input SSTL_2 reference voltage.

82 VDDID Input VDD identification flag.

90 WP Input Write Protect: Serial presence-detect hardware write

protect.

16, 32 MEG x 72

DDR REGISTERED SDRAM DIMMs

ADVANCE

16, 32 Meg x 72 DDR Registered SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.

PIN DESCRIPTIONS (continued)

PIN NUMBERS SYMBOL TYPE DESCRIPTION

92 SCL Input Serial Clock for Presence-Detect: SCL is used to

synchronize the presence-detect data transfer to and

from the module.

181, 182, 183 SA0-SA2 Input Presence-Detect Address Inputs: These pins are used

to configure the presence-detect device.

10 RESET# Input Asynchronously forces all register outputs LOW when

RESET# is LOW. This signal can be used during power-

up to ensure CKE0/1 are LOW and SDRAM DQs are

High-Z.

44, 45, 49, 51, 134, 135, CB0-CB7 Input/ Data I/Os: Check bits.

142, 144 Output

5, 14, 25, 36, 47, 56, 67, DQS0-DQS17 Input/ Data Strobes: Output with READ data, input with

78, 86, 97, 107, 119, 129, Output WRITE data Edge-aligned with READ data, centered

140, 149, 159, 169, 177 in WRITE data. Used to capture WRITE data.

2, 4, 6, 8, 12, 13, 19, 20, DQ0-DQ63 Input/ Data I/Os: Data bus.

23, 24, 28, 31, 33, 35, 39, Output

40, 53, 55, 57, 60, 61, 64,

68, 69, 72, 73, 79, 80, 83,

84, 87, 88, 94, 95, 98, 99,

105, 106, 109, 110, 114,

117, 121, 123, 126, 127,

131, 133, 146, 147, 150,

151, 153, 155, 161, 162,

165, 166, 170, 171, 174,

175, 178, 179

91 SDA Input/ Serial Presence-Detect Data: SDA is a bidirectional pin

Output used to transfer addresses and data into and out of

the presence-detect portion of the module.

15, 22, 30, 54, 62, 77, 96, VDDQ Supply DQ Power Supply: +2.5V +0.2V.

104, 112, 128, 136, 143,

156, 164, 172, 180

7, 38, 46, 70, 85, 108, VDD Supply Power Supply: +2.5V +0.2V.

120, 148, 168

3, 11, 18, 26, 34, 42, 50, VSS Supply Ground.

58, 66, 74, 81, 89, 93,

100, 116, 124, 132, 139,

145, 152, 160, 176

184 VDDSPD Supply Serial EEPROM positive power supply.

16, 17, 71, 75, 76, 163 DNU – Do Not Use: These pins are not connected on this

module but are assigned pins on other modules in

this product family.

16, 32 MEG x 72

DDR REGISTERED SDRAM DIMMs

ADVANCE

16, 32 Meg x 72 DDR Registered SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.

SCL

SDA

DATA STABLE DATA STABLEDATA

CHANGE

Figure 1

Data Validity

SCL

SDA

START

BIT

STOP

BIT

Figure 2

Definition of Start and Stop

SCL from Master

Data Output

from Transmitter

Data Output

from Receiver

Acknowledge

Figure 3

Acknowledge Response From Receiver

SPD CLOCK AND DATA CONVENTIONS

Data states on the SDA line can change only during

SCL LOW. SDA state changes during SCL HIGH are

reserved for indicating start and stop conditions (Fig-

ures 1 and 2).

SPD START CONDITION

All commands are preceded by the start condition,

which is a HIGH-to-LOW transition of SDA when SCL

is HIGH. The SPD device continuously monitors the

SDA and SCL lines for the start condition and will not

respond to any command until this condition has been

met.

SPD STOP CONDITION

All communications are terminated by a stop con-

dition, which is a LOW-to-HIGH transition of SDA

when SCL is HIGH. The stop condition is also used to

place the SPD device into standby power mode.

SPD ACKNOWLEDGE

Acknowledge is a software convention used to

indicate successful data transfers. The transmitting

device, either master or slave, will release the bus after

transmitting eight bits. During the ninth clock cycle, the

receiver will pull the SDA line LOW to acknowledge that

it received the eight bits of data (Figure 3).

The SPD device will always respond with an ac-

knowledge after recognition of a start condition and its

slave address. If both the device and a write operation

have been selected, the SPD device will respond with an

acknowledge after the receipt of each subsequent eight-

bit word. In the read mode the SPD device will transmit

eight bits of data, release the SDA line and monitor the

line for an acknowledge. If an acknowledge is detected

and no stop condition is generated by the master, the

slave will continue to transmit data. If an acknowledge

is not detected, the slave will terminate further data

transmissions and await the stop condition to return to

standby power mode.

16, 32 MEG x 72

DDR REGISTERED SDRAM DIMMs

ADVANCE

16, 32 Meg x 72 DDR Registered SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.

SERIAL PRESENCE-DETECT MATRIX

BYTE DESCRIPTION ENTRY (VERSION) MT18VDDT1672 (Hex) MT18VDDT3272 (Hex)

0 NUMBER OF SPD BYTES USED BY MICRON 128 80 80

1 TOTAL NUMBER OF BYTES IN SPD DEVICE 256 08 08

2 FUNDAMENTAL MEMORY TYPE SDRAM DDR 07 07

3 NUMBER OF ROW ADDRESSES ON ASSEMBLY 12 0C 0C

4 NUMBER OF COLUMN ADDRESSES ON ASSEMBLY 10 or 11 0A 0B

5 NUMBER OF PHYSICAL BANKS ON DIMM 1 01 01

6 MODULE DATA WIDTH 72 48 48

7 MODULE DATA WIDTH (continued) 0 00 00

8 MODULE VOLTAGE INTERFACE LEVELS (VDDQ) SSTL 2.5V 04 04

9 SDRAM CYCLE TIME, (tCK) 7 ns (-262) 70 70

(CAS LATENCY = 2.5) 7.5 ns (-265) 75 75

8 ns (-202) 80 80

10 SDRAM ACCESS FROM CLOCK,(tAC) 0.75 ns (-262/-265) 75 75

(CAS LATENCY = 2.5) 0.8 ns (-202) 80 80

11 MODULE CONFIGURATION TYPE ECC 02 02

12 REFRESH RATE/TYPE 15.6µs/SELF 80 80

13 SDRAM DEVICE WIDTH (PRIMARY SDRAM) x4 04 04

14 ERROR-CHECKING SDRAM DATA WIDTH x4 04 04

15 MINIMUM CLOCK DELAY, BACK-TO-BACK 1 clock 01 01

RANDOM COLUMN ACCESS

16 BURST LENGTHS SUPPORTED 2, 4, 8 0E 0E

17 NUMBER OF BANKS ON SDRAM DEVICE 4 04 04

18 CAS LATENCIES SUPPORTED 2, 2.5 0C 0C

19 CS LATENCY 0 01 01

20 WE LATENCY 1 02 02

21 SDRAM MODULE ATTRIBUTES REGISTERED, PLL 26 26

22 SDRAM DEVICE ATTRIBUTES: GENERAL 00 00

23 SDRAM CYCLE TIME, (tCK) 7.5 ns (-262) 75 75

(CAS LATENCY = 2) 10 ns (-265/-202) A0 A0

24 SDRAM ACCESS FROM CK , (tAC) 0.75 ns (-262/-265) 75 75

(CAS LATENCY = 2) 0.8 ns (-202) 80 80

25 SDRAM CYCLE TIME, (tCK) N/A 00 00

(CAS LATENCY = 1.5)

26 SDRAM ACCESS FROM CK , (tAC) N/A 00 00

(CAS LATENCY = 1.5)

27 MINIMUM ROW PRECHARGE TIME,(tRP) 15 ns (-262) 3C 3C

20 ns (-265/-202) 50 50

28 MINIMUM ROW ACTIVE TO ROW ACTIVE, (tRRD) 15 ns 3C 3C

29 MINIMUM RAS# TO CAS# DELAY, (tRCD) 15 ns (-262) 3C 3C

20 ns (-265/-202) 50 50

30 MINIMUM RAS# PULSE WIDTH, (tRAS) 45 ns (-262/-265) 2D 2D

50 ns (-202) 32 32

31 MODULE BANK DENSITY 128MB or 256MB 20 40

NOTE: 1. “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW.”

16, 32 MEG x 72

DDR REGISTERED SDRAM DIMMs

ADVANCE

16, 32 Meg x 72 DDR Registered SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.

SERIAL PRESENCE-DETECT MATRIX (continued)

BYTE DESCRIPTION ENTRY (VERSION) MT18VDDT1672G (Hex) MT18VDDT3272G (Hex)

32 ADDRESS AND COMMAND SETUP TIME, (tIS) 0.9ns or 1.0ns (-262/-265) A0 90

1.1ns (-202) B0 B0

33 ADDRESS AND COMMAND HOLD TIME, (tIH) 0.9ns or 1.0ns (-262/-265) A0 90

1.1ns (-202) B0 B0

34 DATA/DATA MASK INPUT SETUP TIME, (tDS) 0.5 (-262/-265) 50 50

0.6 (-202) 60 60

35 DATA/DATA MASK INPUT HOLD TIME, (tDH) 0.5 (-262/-265) 50 50

0.6 (-202) 60 60

36-61 RESERVED 00 00

62 SPD REVISION Initial Release 0.0 00 00

63 CHECKSUM FOR BYTES 0-62 -262 1E 75

-265 76 CD

-202 52 73

64 MANUFACTURER’S JEDEC ID CODE MICRON 2C 2C

65-71 MANUFACTURER’S JEDEC ID CODE (continued) 00 00

72 MANUFACTURING LOCATION 01 01

02 02

03 03

04 04

05 05

06 06

07 07

08 08

09 09

73-90 MODULE PART NUMBER (ASCII) xx

91 PCB IDENTIFICATION CODE 1 01 01

02 02

03 03

04 04

05 05

06 06

07 07

08 08

09 09

92 IDENTIFICATION CODE (continued) 0 00 00

93 YEAR OF MANUFACTURE IN BCD xx

94 WEEK OF MANUFACTURE IN BCD xx

95-98 MODULE SERIAL NUMBER xx

99-127 MANUFACTURER-SPECIFIC DATA (RSVD) – –

NOTE: 1. “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW.”

2. x = Variable Data.

16, 32 MEG x 72

DDR REGISTERED SDRAM DIMMs

ADVANCE

16, 32 Meg x 72 DDR Registered SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.

NOTE: 1. CKE is HIGH for all commands shown except SELF REFRESH.

2. BA0-BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register; BA0

= 1, BA1 = 0 select extended mode register; other combinations of BA0-BA1 are reserved). A0-A11 provide the op-code

to be written to the selected mode register.

3. BA0-BA1 provide bank address and A0-A11 provide row address.

4. BA0-BA1 provide bank address; A0-A8 provide column address; A10 HIGH enables the auto precharge feature (nonpersis-

tent), and A10 LOW disables the auto precharge feature.

5. A10 LOW: BA0-BA1 determine which bank is precharged.

A10 HIGH: all banks are precharged and BA0-BA1 are “Don’t Care.”

6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.

7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.

8. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for READ

bursts with auto precharge enabled and for WRITE bursts.

9. DESELECT and NOP are functionally interchangeable.

10. Used to mask write data; provided coincident with the corresponding data.

TRUTH TABLE 1A – COMMANDS

(Note: 1)

NAME (FUNCTION) CS# RAS# CAS# WE# ADDR NOTES

DESELECT (NOP) H X X X X 9

NO OPERATION (NOP) L H H H X 9

ACTIVE (Select bank and activate row) L L H H Bank/Row 3

READ (Select bank and column, and start READ burst) L H L H Bank/Col 4

WRITE (Select bank and column, and start WRITE burst) L H L L Bank/Col 4

BURST TERMINATE L H H L X 8

PRECHARGE (Deactivate row in bank or banks) L L H L Code 5

AUTO REFRESH or SELF REFRESH L L L H X 6, 7

(Enter self refresh mode)

LOAD MODE REGISTER LLLLOp-Code 2

TRUTH TABLE 1B – DM OPERATION

(Note: 10)

NAME (FUNCTION) DM DQs

Write Enable L Valid

Write Inhibit HX

Commands

Truth Table 1 provides a general reference of avail-

able commands. For a more detailed description of

commands and operations, refer to the 64Mb or 128Mb:

x4 SDRAM data sheet.

16, 32 MEG x 72

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M3 = 0

Reserved

M3 = 1

Reserved

Operating Mode

Normal Operation

Normal Operation/Reset DLL

All other states reserved

Valid

Burst Type

Sequential

Interleaved

CAS Latency

Reserved

2.5

Reserved

Burst Length

Burst LengthCAS Latency BT0*0*

A9 A7 A6 A5 A4 A3

A8 A2 A1 A0

Mode Register (Mx)

Address Bus

976543

8210

M6-M0

M8 M7

Operating Mode

A10

A11

BA1

BA0

* M13 and M12 (BA0 and BA1)

must be “0, 0” to select the

base mode register (vs. the

extended mode register).

M9M10M11

Figure 4

Mode Register Definition

Table 1

Burst Definition

Burst Starting Column Order of Accesses Within a Burst

Length Address Type = Sequential Type = Interleaved

20 0-1 0-1

1 1-0 1-0

A1 A0

0 0 0-1-2-3 0-1-2-3

40 1 1-2-3-0 1-0-3-2

1 0 2-3-0-1 2-3-0-1

1 1 3-0-1-2 3-2-1-0

A2 A1 A0

0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7

0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6

0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5

80 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4

1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3

1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2

1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1

1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0

NOTE: 1. For a burst length of two, A1-A8 select the two-

data-element block; A0 selects the first access

within the block.

2. For a burst length of four, A2-A8 select the four-

data-element block; A0-A1 select the first access

within the block.

3. For a burst length of eight, A3-A8 select the eight-

data-element block; A0-A2 select the first access

within the block.

4. Whenever a boundary of the block is reached

within a given sequence above, the following

access wraps within the block.

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ABSOLUTE MAXIMUM RATINGS*

VDD Supply Voltage Relative to VSS ........ -1V to +3.6V

VDDQ Supply Voltage Relative to VSS .... -1V to +3.6V

VREF and Inputs Voltage

Relative to VSS ..................................... -1V to +3.6V

I/O Pins Voltage

Relative to V

....................... -0.5V to V

Q +0.5V

Operating Temperature, TA (ambient) ... 0°C to +70°C

Storage Temperature (plastic) ........... -55°C to +150°C

Power Dissipation ................................................. 18W

Short Circuit Output Current ............................ 50mA

*Stresses greater than those listed under “Absolute

Maximum Ratings” may cause permanent damage to

the device. This is a stress rating only, and functional

operation of the device at these or any other conditions

above those indicated in the operational sections of this

specification is not implied. Exposure to absolute maxi-

mum rating conditions for extended periods may affect

reliability.

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DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS

(Notes: 1-5, 6) (0°C ≤ TA ≤ +70°C; VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V)

PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES

Supply Voltage VDD 2.3 2.7 V

I/O Supply Voltage VDDQ 2.3 2.7 V

I/O Reference Voltage VREF 0.49 x VDDQ 0.51 x VDDQV 7

I/O Termination Voltage (system) VTT VREF - 0.04 VREF + 0.04 V 8

Input High (Logic 1) Voltage VIH VREF + 0.18 VDD + 0.3 V 9

Input Low (Logic 0) Voltage VIL -0.3 VREF - 0.18 V 9

Clock Input Voltage Level; CK0 and CK0# VIN -0.3 VDDQ + 0.3 V

Clock Input Differential Voltage; CK0 and CK0# VID 0.36 VDDQ + 0.6 V 10

Clock Input Crossing Point Voltage; CK0 and CK0# VIX 1.15 1.35 V 11

INPUT LEAKAGE CURRENT

Any input 0V ≤ VIN ≤ VDD II-5 5 µA 12

(All other pins not under test = 0V)

OUTPUT LEAKAGE CURRENT IOZ -5 5 µA 13

(DQs are disabled; 0V ≤ VOUT ≤ VDDQ)

OUTPUT LEVELS

Output High Current (VOUT = 1.95V, maximum VTT)IOH -16.8 – mA

Output Low Current (VOUT = 0.35V, minimum VTT)IOL 16.8 – mA

NOTE: 1. All voltages referenced to VSS.

2. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage

levels, but the related specifications and device operation are guaranteed for the full voltage range specified.

3. Outputs measured with equivalent load (QFC# is x4 only):

Output

OUT

)

Reference

Point

Ω

30pF

QFC#

OUT

)

Reference

Point

Ω

15pF

4. AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing is still

referenced to VREF (or to the crossing point for CK/CK#), and parameter specifications are guaranteed for the specified

AC input levels under normal use conditions. The minimum slew rate for the input signals used to test the device is 1V/

ns in the range between VIL(AC) and VIH(AC).

5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will effectively switch

as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring

back above [below] the DC input LOW [HIGH] level).

6. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE ≤ 0.3 x

VDDQ is recognized as LOW.

7. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-

to-peak noise on VREF may not exceed ±2 percent of the DC value. Thus, from VDDQ/2, VREF is allowed ±25mV for DC

error and ±25mV for AC noise.

8. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set

equal to VREF and must track variations in the DC level of VREF.

9. The DC values define where the input slew rate requirements are imposed, and the input signal must not violate these

levels in order to maintain a valid level. The inputs require the AC value to be achieved during signal transition edge

and the driver should achieve the same slew rate through the AC values.

10. VID is the magnitude of the difference between the input level on CK and the input level on CK#.

11. The value of VIX is expected to equal VDDQ/2 of the transmitting device and must track variations in the DC level of

the same.

12. Referenced to each output group: x4 = DQS with DQ0-DQ3, x8 = DQS with DQ0-DQ7, x16 = LDQS with DQ0-DQ7 and

UDQS with

DQ8-DQ15.

13. The Input capacitance per pin group will not differ by more than this maximum amount for any given device.

16, 32 MEG x 72

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AC OPERATING CONDITIONS

(Notes: 1-5, 6, 7) (0°C ≤ TA ≤ +70°C; VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V)

PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES

Input High (Logic 1) Voltage; DQ, DQS and DM signals V

(

REF

+ 0.310 – V 8, 9

Input Low (Logic 0) Voltage; DQ, DQS and DM signals V

(

)– V

REF

- 0.310 V 8, 9

Clock Input Differential Voltage; CK and CK# V

(

) 0.7 V

Q + 0.6 V 10

Clock Input Crossing Point Voltage; CK and CK# V

(

) 0.5 x V

Q - 0.2 0.5 x V

Q + 0.2 V 11

NOTE: 1. All voltages referenced to VSS.

2. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage

levels, but the related specifications and device operation are guaranteed for the full voltage range specified.

3. Outputs measured with equivalent load (QFC# is x4 only):

Output

OUT

)

Reference

Point

Ω

30pF

QFC#

OUT

)

Reference

Point

Ω

15pF

4. AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing is still

referenced to VREF (or to the crossing point for CK/CK#), and parameter specifications are guaranteed for the specified

AC input levels under normal use conditions. The minimum slew rate for the input signals used to test the device is 1V/

ns in the range between VIL(AC) and VIH(AC).

5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will effectively switch

as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring

back above [below] the DC input LOW [HIGH] level).

6. Input slew rate = 1V/ns. If the slew rate exceeds the maximum specified by 20 percent, functionality is uncertain. If

the slew rate exceeds the minimum specified, timing is no longer referenced to the mid-point but to the VIL(AC)

maximum and VIH(AC) minimum points. For slew rates between 0.5V/ns and 1V/ns, tIS and tIH must be increased by at

least 20 percent.

7. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE ≤ 0.3 x

VDDQ is recognized as LOW.

8. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-

to-peak noise on VREF may not exceed ±2 percent of the DC value. Thus, from VDDQ/2, VREF is allowed ±25mV for DC

error and ±25mV for AC noise.

9. VID is the magnitude of the difference between the input level on CK and the input level on CK#.

10. The value of VIX is expected to equal VDDQ/2 of the transmitting device and must track variations in the DC level of

the same.

11. IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the

outputs open.

16, 32 MEG x 72

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IDD SPECIFICATIONS AND CONDITIONS

(Notes: 1-5, 6, 7, 8) (0°C ≤ TA ≤ +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V)

PARAMETER/CONDITION SYMBOL SIZE -262 -265 -202 UNITS NOTES

OPERATING CURRENT: One bank; Active-Precharge;

RC = I

0128MB 1,620 1,440 1,260 mA 9

RC (MIN);

CK =

CK (MIN); DQ, DM and DQS inputs changing

twice per clock cyle; Address and control inputs changing 256MB 1,800 1,620 1,260

once per clock cycle; CL = 2.5

OPERATING CURRENT: One bank; Active-Read-Precharge; I

1128MB 2,070 1,890 1,620 mA 9

Burst = 2;

RC =

RC (MIN); CL = 2.5;

CK =

CK (MIN); I

OUT

= 0mA;

Address and control inputs changing once per clock cycle 256MB 2,160 2,070 1,620

PRECHARGE POWER-DOWN STANDBY CURRENT: All banks I

2P 128MB 90 90 90 mA

idle; Power-down mode; CKE = LOW;

CK =

CK (MIN) 256MB 90 90 90

IDLE STANDBY CURRENT: CS# = HIGH; All banks idle; I

2N 128MB 900 900 720 mA

CKE = HIGH;

CK =

CK (MIN); Address and other control inputs

changing once per clock cycle 256MB 630 630 540

ACTIVE POWER-DOWN STANDBY CURRENT: One bank I

3P 128MB 126 126 126 mA

active; Power-down mode; CKE = LOW;

CK =

CK (MIN) 256MB 126 126 126

ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; I

3N 128MB 900 900 720 mA 9

One bank; Active-Precharge;

RC =

RAS (MAX);

CK =

CK (MIN);

DQ, DM, and DQS inputs changing twice per clock cycle; 256MB 360 360 360

Address and other control inputs changing once per clock cycle

OPERATING CURRENT: Burst = 2; Reads; Continuous burst; I

4R 128MB 2,340 2,250 2,070 mA

One bank active; Address and control inputs changing once per

clock cycle; CL = 2.5;

CK =

CK (MIN); I

OUT

= 0mA 256MB 1,800 1,800 1,620

OPERATING CURRENT: Burst = 2; Writes; Continuous burst; I

4W 128MB 2,070 1,890 1,800 mA

One bank active; Address and control inputs changing once per

clock cycle; CL = 2.5;

CK =

CK (MIN); DQ, DM, and DQS inputs 256MB 1,800 1,800 1,620

changing twice per clock cycle

AUTO REFRESH CURRENT

RC =

RFC (MIN) I

5128MB 2,520 2,340 2,250 mA 9

256MB 4,140 3,780 3,240

RC =

15.625µs I

6128MB 90 90 90 mA 10

256MB 90 90 90

SELF REFRESH CURRENT: CKE ≤ 0.2V Standard I

7128MB 18 18 36 mA 11

256MB 36 36 54

Low power (L) I

7128MB 10.8 10.8 10.8 mA 11

256MB 18 18 18

MAX

NOTE: 1. All voltages referenced to VSS.

2. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage

levels, but the related specifications and device operation are guaranteed for the full voltage range specified.

3. Outputs measured with equivalent load (QFC# is x4 only):

Output

OUT

)

Reference

Point

Ω

30pF

QFC#

OUT

)

Reference

Point

Ω

15pF

(notes continued on following page)

16, 32 MEG x 72

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128MB 256MB

CAPACITANCE

(Note: 1)

PARAMETER SYMBOL MIN MAX MIN MAX UNITS NOTES

Input/Output Capacitance: DQs, DQSs, DMs, CBs CIO 5.0 7.0 10.0 14.0 pF

Input Capacitance: CK, CK# CI1 – 3.0 – 3.0 pF 2

Input Capacitance: All other input-only pins CI2 – 4.0 – 4.0 pF 2

NOTE (continued):

4. AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing is still

referenced to VREF (or to the crossing point for CK/CK#), and parameter specifications are guaranteed for the specified

AC input levels under normal use conditions. The minimum slew rate for the input signals used to test the device is 1V/

ns in the range between VIL(AC) and VIH(AC).

5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will effectively switch

as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring

back above [below] the DC input LOW [HIGH] level).

6. IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the

outputs open.

7. IDD specifications are tested after the device is properly initialized.

8. Command/Address input slew rate =0.5V/ns. For

-7and -75 with slew rates 1V/ns or faster, tIS and tIH are reduced to 900 ps. If the slew rate is less than 0.5V/ns, timing

is no longer referenced to the mid-point but to the VIL(AC) maximum and VIH(AC) minimum points.If the slew rate

exceeds 3V/ns, functionality is uncertain.

9. MIN (tRC or tRFC) for IDD measurements is the smallest multiple of tCK that meets the minimum absolute value for the

respective parameter. tRAS MAX for IDD measurements is the largest multiple of tCK that meets the maximum absolute

value for tRAS.

10. This limit is actually a nominal value and does not result in a fail value. CKE is HIGH during REFRESH command period

(tRFC [MIN]) else CKE is LOW (i.e., during standby).

11. Enables on-chip refresh and address counters.

NOTE: 1. All voltages referenced to VSS.

2. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage

levels, but the related specifications and device operation are guaranteed for the full voltage range specified.

16, 32 MEG x 72

DDR REGISTERED SDRAM DIMMs

ADVANCE

16, 32 Meg x 72 DDR Registered SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS

(Notes: 1-5, 7-9) (0°C ≤ TA ≤ +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V)

AC CHARACTERISTICS -262 -265 -202

PARAMETER SYMBOL MIN MAX MIN MAX MIN MAX UNITS NOTES

Access window of DQs from CK/CK# tAC -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns

CK high-level width tCH 0.45 0.55 0.45 0.55 0.45 0.55 tCK 10

CK low-level width tCL 0.45 0.55 0.45 0.55 0.45 0.55 tCK 10

Clock cycle time CL = 2.5 tCK 7 15 7.5 15 8 15 ns

CL = 2 tCK 7.5 15 10 15 10 15 ns

Auto precharge write recovery plus precharge time tDAL 35 35 35 ns

DQ and DM input hold time relative to DQS tDH 0.5 0.5 0.6 ns 11, 12

DQ and DM input setup time relative to DQS tDS 0.5 0.5 0.6 ns 11, 12

DQ and DM input pulse width (for each input) tDIPW 1.75 1.75 2 ns 12

Access window of DQS from CK/CK# tDQSCK -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns

DQS input high pulse width tDQSH 0.35 0.35 0.35 tCK

DQS input low pulse width tDQSL 0.35 0.35 0.35 tCK

DQS-DQ skew, DQS to last DQ valid, per group, per access tDQSQ 0.5 0.5 0.6 ns 11, 13

DQS-DQ skew, first DQS to last DQ valid, per access tDQSQA 0.7 0.7 0.8 ns

Write command to first DQS latching transition tDQSS 0.75 1.25 0.75 1.25 0.75 1.25 tCK

DQS falling edge to CK rising - setup time tDSS 0.2 0.2 0.2 tCK

DQS falling edge from CK rising - hold time tDSH 0.2 0.2 0.2 tCK

Half clock period tHP tCH,tCL tCH,tCL tCH,tCL ns

Data-out high-impedance window from CK/CK# tHZ -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns 14

Data-out low-impedance window from CK/CK# tLZ -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns 14

Address and control input hold time tIH 1 1 1.1 ns

Address and control input setup time tIS 1 1 1.1 ns

Address and control input pulse width tIPW 2.2 2.2 2.5 ns

LOAD MODE REGISTER command cycle time tMRD 15 15 16 ns

DQ-DQS hold, DQS to first DQ to go non-valid, per access tQH tHP tHP tHP ns 11, 13

- 0.75ns - 0.75ns - 1ns

(continued on following page)

1. All voltages referenced to VSS.

2. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage

levels, but the related specifications and device operation are guaranteed for the full voltage range specified.

3. Outputs measured with equivalent load (QFC# is x4 only):

Output

OUT

)

Reference

Point

Ω

30pF

QFC#

OUT

)

Reference

Point

Ω

15pF

4. AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing is still

referenced to VREF (or to the crossing point for CK/CK#), and parameter specifications are guaranteed for the specified

AC input levels under normal use conditions. The minimum slew rate for the input signals used to test the device is 1V/

ns in the range between VIL(AC) and VIH(AC).

5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will effectively switch

as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring

back above [below] the DC input LOW [HIGH] level).

6. Input slew rate = 1V/ns. If the slew rate exceeds the maximum specified by 20 percent, functionality is uncertain. If

the slew rate exceeds the minimum specified, timing is no longer referenced to the mid-point but to the VIL(AC)

maximum and VIH(AC) minimum points. For slew rates between 0.5V/ns and 1V/ns, tIS and tIH must be increased by at

least 20 percent.

7. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which CK and CK# cross; the input

reference level for signals other than CK/CK# is VREF.

8. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE ≤ 0.3 x

VDDQ is recognized as LOW.

16, 32 MEG x 72

DDR REGISTERED SDRAM DIMMs

ADVANCE

16, 32 Meg x 72 DDR Registered SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS

(continued)

(Notes: 1-5, 7-9) (0°C ≤ TA ≤ +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V)

AC CHARACTERISTICS -262 -265 -202

PARAMETER SYMBOL MIN MAX MIN MAX MIN MAX UNITS NOTES

NOTE (continued):

9. The output timing reference level, as measured at the timing reference point indicated in Note 3, is VTT.

10. CK and CK# input slew rate must be  1V/ns.

11. Referenced to each output group: x4 = DQS with DQ0-DQ3, x8 = DQS with DQ0-DQ7, x16 = LDQS with DQ0-DQ7 and

UDQS with

DQ8-DQ15.

12. DQ and DM input slew rates must not deviate from DQS by more than 10%. If the DQ/DM/DQS slew rate is less than

0.5V/ns, timing is no longer referenced to the mid-point but to the VIL(AC) maximum and VIH(AC) minimum points.

13. The valid data window is derived by achieving other specifications - tHP (tCK/2), tDQSQ, and tQH [tHP - 750ps (-7, -75) or

tHP - 1ns (-8)]. The data valid window derates directly porportional with the clock duty cycle and a practical data valid

window can be derived. The clock is allowed a maximum duty cycle variation of 45/55. Functionality is uncertain when

operating beyond a 45/55 ratio. The data valid window derating curves are provided below for duty cycles ranging

between 50/50 and 45/55.

14. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not

referenced to a specific voltage level, but specify when the device output is no longer driving (HZ) or begins driving

(LZ).

15. The refresh period 64ms. This equates to an average refresh rate of 15.625µs. However, an AUTO REFRESH command

must be asserted at least once every 31.2µs; burst refreshing or postings greater than 2 are not allowed.

16. This is not a device limit. The device will operate with a negative value, but system performance could be degraded

due to bus turnaround.

17. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The case shown (DQS going from

High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in

progress, DQS could be HIGH during this time, depending on tDQSS.

18. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this

parameter, but system performance (bus turnaround) will degrade accordingly.

QFC# write preamble, output referenced from CK/CK# tQCK .4 .4 .4 ns

QFC# write postamble, output hold tQOH 1.25 2 1.25 2 1.25 2 ns

QFC# read preamble (CL = 2 or 2.5) tQPRE 0.9 1.1 0.9 1.1 0.9 1.1 tCK

QFC# read postamble tQPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK

ACTIVE to PRECHARGE command tRAS 45 120,000 45 120,000 50 120,000 ns

ACTIVE to ACTIVE/AUTO REFRESH command period tRC 60 65 70 ns

AUTO REFRESH command period tRFC 67 75 80 ns

REFRESH to REFRESH command interval tREFC 140.6 140.6 140.6 µs 15

Average periodic refresh interval tREFI 15.6 15.6 15.6 µs 15

ACTIVE to READ or WRITE delay tRCD 15 20 20 ns

PRECHARGE command period tRP 15 20 20 ns

DQS read preamble - (CL = 2 or 2.5) tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 tCK

DQS read postamble tRPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK

ACTIVE bank a to ACTIVE bank b command tRRD 15 15 15 ns

Data valid output window na tQH - tDQSQ tQH - tDQSQ tQH - tDQSQ ns 13

Terminating voltage delay to VDD tVTD 0 0 0 ns

DQS write preamble tWPRE 0.25 0.25 0.25 tCK

DQS write preamble setup time tWPRES 0 0 0 ns 16, 17

DQS write postamble tWPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK 18

Write recovery time tWR 15 15 15 ns

Internal WRITE to READ command delay tWTR 1 1 1 tCK

Exit SELF REFRESH to non-READ command tXSNR 75 75 80 ns

Exit SELF REFRESH to READ command tXSRD 200 200 200 tCK

16, 32 MEG x 72

DDR REGISTERED SDRAM DIMMs

ADVANCE

16, 32 Meg x 72 DDR Registered SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.

(Note: 1)

TA = 0-70° C

VDD = 2.5V ± 0.2V

tCK Clock Frequency 60 170 MHz

tPD Clock to Output Time 30pF to GND and 1.1 2.7 ns

50 ohms to VTT

tRST Reset to Output Time – 5 ns

tSL Output Slew Rate 0.5 4 V/ns

Setup time, fast slew rate – 0.75 ns 2, 4

1:1 (see Notes 1 and 3)

tsu

14 bit SSTL Setup time, slow slew rate – 0.9 ns 3, 4

(see Notes 2 and 3)

Hold time, fast slew rate – 0.75 ns 2, 4

(see Notes 1 and 3)

thHold time, slow slew rate – 0.9 ns 3, 4

(see Notes 2 and 3)

CIN(CK) Clock Input Capacitance 2.5 3.5 pF

CIN(data) Clock Input Capacitance 2.5 3.5 pF

NOTE: 1. The timing specifications for the register listed above are critical for proper operation of the DDR SDRAM Registered

DIMMs. These are meant to be a subset of the parameters for the specific device used on the module. Detailed

information on this part has been shown at the JEDEC JC-40 Committee. Please contact Micron Technology's Module

Applications Team if further information on the specific register model is required.

2. For data signal, input slew rate  1 V/ns.

3. For data signal, input slew rate  0.5 V/ns and < 1 V/ns.

4. For CK and CK# signals, input slew rates are  1 V/ns.

16, 32 MEG x 72

DDR REGISTERED SDRAM DIMMs

ADVANCE

16, 32 Meg x 72 DDR Registered SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.

PLL CLOCK DRIVER TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS

(Specifications for the PLL component used on the module.)

PARAMETER SYMBOL TEST CONDITIONS MIN NOM MAX UNITS

Clock frequency fC 66 167 MHz

Input clock duty cycle 40% 60%

Stabilization time10.1 ms

Low-to high level tPLH CK mode/CK to any output 1.5 3.5 6 ns

propagation delay time

High-to low level tPHL CK mode/CK to any output 1.5 3.5 6 ns

propagation delay time

Output enable time ten CK mode/G to any Y output 3 ns

Output disable time tdis CK mode/G to any Y output 3 ns

Jitter (peak-to-peak) t(jitter) 66 MHz 120 ps

100/125/133/167 MHz 75

Jitter (cycle-to-cycle) t(jitter) 66 MHz 110 ps

100/125/133/167 MHz 65

Phase error t(phase Terminated with 120 ohm/16pF -150 150 ns

error)

Output skew tskew(o) Terminated with 120 ohm/16pF 100 ns

Pulse skew tdis Terminated with 120 ohm/16pF 100 ns

Duty cycle 66 MHz to 100 MHz 49.5% 50.5%

101 MHz to 167 MHz 49% 51%

Output rise and fall times tr, tf Load = 120 ohm/16pF 650 800 950 ps

(20% - 80%)

NOTE: 1. Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal.

16, 32 MEG x 72

DDR REGISTERED SDRAM DIMMs

ADVANCE

16, 32 Meg x 72 DDR Registered SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.

SERIAL PRESENCE-DETECT EEPROM DC OPERATING CONDITIONS

(Note: 1) (VDD = +2.5V ± 0.2V)

PARAMETER/CONDITION SYMBOL MIN MAX UNITS

SUPPLY VOLTAGE VDD 2.3 2.7 V

INPUT HIGH VOLTAGE: Logic 1; All inputs VIH VDD x 0.7 VDD + 0.5 V

INPUT LOW VOLTAGE: Logic 0; All inputs VIL -1 VDD x 0.3 V

OUTPUT LOW VOLTAGE: IOUT = 3mA VOL – 0.4 V

INPUT LEAKAGE CURRENT: VIN = GND to VDD ILI –10µA

OUTPUT LEAKAGE CURRENT: VOUT = GND to VDD ILO –10µA

STANDBY CURRENT: ISB –30µA

SCL = SDA = VDD - 0.2V; All other inputs = GND or 2.5V +10%

POWER SUPPLY CURRENT: ICC –2mA

SCL clock frequency = 100 KHz

NOTE: 1. The refresh period is 64ms. This equates to an average refresh rate of 15.625µs. However, an AUTO REFRESH command

must be asserted at least once every 31.2µs; burst refreshing or postings greater than 2 are not allowed.

SERIAL PRESENCE-DETECT EEPROM AC OPERATING CONDITIONS

(Note: 1) (VDD = +2.5V ± 0.2V)

PARAMETER/CONDITION SYMBOL MIN MAX UNITS

SCL LOW to SDA data-out valid tAA 0.3 3.5 µs

Time the bus must be free before a new transition can start tBUF 4.7 µs

Data-out hold time tDH 300 ns

SDA and SCL fall time tF 300 ns

Data-in hold time tHD:DAT 0 µs

Start condition hold time tHD:STA 4 µs

Clock HIGH period tHIGH 4 µs

Noise suppression time constant at SCL, SDA inputs tI 100 ns

Clock LOW period tLOW 4.7 µs

SDA and SCL rise time tR1µs

SCL clock frequency tSCL 100 KHz

Data-in setup time tSU:DAT 250 ns

Start condition setup time tSU:STA 4.7 µs

Stop condition setup time tSU:STO 4.7 µs

WRITE cycle time tWRC 10 ms

16, 32 MEG x 72

DDR REGISTERED SDRAM DIMMs

ADVANCE

16, 32 Meg x 72 DDR Registered SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.

SPD EEPROM

SCL

SDA IN

SDA OUT

tLOW

tSU:STA tHD:STA

tFtHIGH tR

tBUF

tDH

tAA

tSU:STO

tSU:DAT

tHD:DAT

UNDEFINED

SERIAL PRESENCE-DETECT EEPROM

TIMING PARAMETERS

SYMBOL MIN MAX UNITS

tAA 0.3 3.5 µs

tBUF 4.7 µs

tDH 300 ns

tF 300 ns

tHD:DAT 0 µs

tHD:STA 4 µs

SYMBOL MIN MAX UNITS

tHIGH 4 µs

tLOW 4.7 µs

tR1µs

tSU:DAT 250 ns

tSU:STA 4.7 µs

tSU:STO 4.7 µs

16, 32 MEG x 72

DDR REGISTERED SDRAM DIMMs

ADVANCE

16, 32 Meg x 72 DDR Registered SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice.

NOTE: 1. All dimensions in inches (millimeters) MAX or typical where noted.

MIN

184-PIN DIMM

(128MB and 256MB)

1.705 (43.31)

1.695 (43.05)

PIN 1

(93 on back)

.700 (17.78)

TYP.

.098 (2.50) D

(2X)

.091 (2.30) TYP.

.250 (6.35) TYP.

4.750 (120.65)

.050 (1.27)

TYP.

.091 (2.30)

TYP.

.040 (1.02)

TYP.

.079 (2.00) R

(4X)

.035 (0.90) R

PIN 92

(184 on back)

FRONT VIEW

.054 (1.37)

.046 (1.17)

5.256 (133.50)

5.244 (133.20)

2.55 (64.77) 1.95 (49.53)

.394 (10.00)

TYP.

.157 (4.00)

MAX

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E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992

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