GS880F32CGT-7.5I - GSI Technology

GS880F18/32/36CT-xxxI

512K x 18, 256K x 32, 256K x 36

9Mb Sync Burst SRAMs

4.5 ns–7.5 ns

2.5 V or 3.3 V VDD

2.5 V or 3.3 V I/O

100-Pin TQFP

Industrial Temp

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Features

• Flow Through mode operati on; Pin 14 = No Connect

• 2.5 V or 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Byte Write (BW) and/or Global Wr ite (GW) operation

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC-standard 100-lead TQFP package

• RoHS-compliant 100-lead TQFP package available

Functional Description

Applications

The GS880F18/32/36CT is a 9,437,184-bit (8,388,608-bit for

x32 version) high performance synchronous SRA M with a

2-bit burst address counter. Although of a type originally

developed for Level 2 Cache applications supporting high

performance CPUs, the device now finds application in

synchronous SRAM applications, ranging from DSP main

store to networking chip set support.

Controls

Addresses, data I/Os, chip enables (E1, E2, E3), address burst

control inputs (ADSP, ADSC, ADV), and write control inputs

(Bx, BW, GW) are synchronous and are controlled by a

positive-edge-triggered clock input (CK). Output enable (G)

and power down control (ZZ) are asynchronous inputs. Burst

cycles can be initiated with either ADSP or ADSC inputs. In

Burst mode, subsequent burst addresses are generated

internally and are controlled by ADV. The burst address

counter may be configured to count in either linear or

interleave order with the Linear Burst Order (LBO) input. The

Burst function need not be used. New addresses can be loaded

on every cycle with no degradation of chip performance.

Designing For Compatibility

The JEDEC standard for Burst RAMS calls for a FT mode pin

option on Pin 14. Board sites for flow through Burst RAMS

should be designed with VSS connected to the FT pin location

to ensure the broadest access to multiple vendor sources.

Boards designed with FT pin pads tied low may be stuffed with

GSI’s pipeline/flow through-configurable Burst RAMs or any

vendor’s flow through or configurable Burst SRAM. Boards

designed with the FT pin location tied high or floating must

employ a non-configurable flow through Burst RAM, like this

RAM, to achieve flow through functionality.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write

control inputs.

Sleep Mode

Low power (Sleep mode) is attained through the assertion

(High) of the ZZ signal, or by stopping the clock (CK).

Memory data is retained during Sleep mode.

Core and Interface Voltages

The GS880F18/32/36CT operates on a 2.5 V or 3.3 V power

supply. All input are 3.3 V and 2.5 V compatible. Separate

output power (VDDQ) pins are used to decouple output noise

from the internal circuits and are 3.3 V and 2.5 V compatible.

Parameter Synopsis

-4.5I -5I -5.5I -6.5I -7.5I Unit

Flow Through

2-1-1-1

tKQ

tCycle 4.5

4.5 5.0

5.0 5.5

5.5 6.5

6.5 7.5

7.5 ns

Curr (x18)

Curr (x32/x36) 200

225 185

210 180

200 160

180 148

165 mA

VDDQ

VSS

DQB

VSS

VDDQ

DQB

VDD

VSS

DQB

VDDQ

VSS

DQB

DQPB

VSS

VDDQ

VSS

DQA

VSS

VDDQ

DQA

VSS

VDD

DQA

VDDQ

VSS

DQA

VSS

VDDQ

LBO

VSS

VDD

VSS

ADSC

ADSP

ADV

512K x 18

Top View

DQPA

NC 10099989796959493929190898887868584838281

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

GS880F18/32/36CT-xxxI

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS880F18C 100-Pin TQFP Pinout (Package T)

Note:

Pins marked with NC can be tied to either VDD or VSS. These pins can also be left floating.

VDDQ

VSS

DQC

VSS

VDDQ

DQC

VDD

VSS

DQD

VDDQ

VSS

DQD

VSS

VDDQ

VSS

DQB

VSS

VDDQ

DQB

VSS

VDD

DQA

VDDQ

VSS

DQA

VSS

VDDQ

LBO

VSS

VDD

VSS

ADSC

ADSP

ADV

256K x 32

Top View

DQB

DQA

DQC

DQD

DQC

NC 10099989796959493929190898887868584838281

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

GS880F18/32/36CT-xxxI

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS880F32C 100-Pin TQFP Pinout (Package T)

Note:

Pins marked with NC can be tied to either VDD or VSS. These pins can also be left floating.

VDDQ

VSS

DQC

VSS

VDDQ

DQC

VDD

VSS

DQD

VDDQ

VSS

DQD

VSS

VDDQ

VSS

DQB

VSS

VDDQ

DQB

VSS

VDD

DQA

VDDQ

VSS

DQA

VSS

VDDQ

LBO

VSS

VDD

VSS

ADSC

ADSP

ADV

256K x 36

Top View

DQB

DQPB

DQB

DQA

DQPA

DQC

DQD

DQPD

DQC

DQPC10099989796959493929190898887868584838281

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

GS880F18/32/36CT-xxxI

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS880F36C 100-Pin TQFP Pinout (Package T)

Note:

Pins marked with NC can be tied to either VDD or VSS. These pins can also be left floating.

TQFP Pin Description

Symbol Type Description

A0, A1IAddress field LSBs and Address Counter preset Inputs

AIAddress Inputs

DQA

DQB

DQC

DQD

I/O Data Input and Output pins

NC —No Connect

BW IByte Write—Writes all enabled bytes; active low

BA, BB, BC, BDIByte Write Enable for DQA, DQB Data I/Os; active low

CK IClock Input Signal; active high

GW IGlobal Write Enable—Writes all bytes; active low

E1IChip Enable; active low

GIOutput Enable; active low

ADV IBurst address counter advance enable; active low

ADSP, ADSC IAddress Strobe (Processor, Cache Controller); active low

ZZ ISleep Mode control; active high

LBO ILinear Burst Order mode; active low

VDD ICore power supply

VSS II/O and Core Ground

VDDQ IOutput driver power supply

GS880F18/32/36CT-xxxI

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS880F18/32/36CT-xxxI

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

A0 A0

A1 D0

D1 Q1

Counter

Load

A0–An

LBO

ADV

ADSC

ADSP

ZZ Power Down

Control

Memory

Array

36 36

DQx1–DQx9

Note: Only x36 version shown for simplicity.

GS880F18/32/36C Block Diagram

Mode Pin Functions

Mode Name Pin Name State Function

Burst Order Control LBO LLinear Burst

HInterleaved Burst

Power Down Control ZZ L or NC Active

H Standby, IDD = ISB

GS880F18/32/36CT-xxxI

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Note:

There is a pull-up device on the FT pin and a pull-down device on the ZZ pin , so this input pin can be unconnected and the chip will operate in

the default states as specified in the above tables.

Note:

The burst counter wraps to initial state on the 5th clock. Note:

The burst counter wraps to initial state on the 5th clock.

Linear Burst Sequence

A[1:0] A[1:0] A[1:0] A[1:0]

1st address 00 01 10 11

2nd address 01 10 11 00

3rd address 10 11 00 01

4th address 11 00 01 10

Interleaved Burst Sequence

A[1:0] A[1:0] A[1:0] A[1:0]

1st address 00 01 10 11

2nd address 01 00 11 10

3rd address 10 11 00 01

4th address 11 10 01 00

Burst Counter Sequences

BPR 1999.05.18

GS880F18/32/36CT-xxxI

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Byte Write Truth Table

Function GW BW BABBBCBDNotes

Read H H X X X X 1

Write No Bytes H L H H H H 1

Write byte a H L L H H H 2, 3

Write byte b H L H L H H 2, 3

Write byte c H L H H L H 2, 3, 4

Write byte d H L H H H L 2, 3, 4

Write all bytes H L L L L L 2, 3, 4

Write all bytes L X X X X X

Notes:

1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs, BA, BB, BC and/or BD.

2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes.

3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.

4. Bytes “C” and “D” are only available on the x32 and x36 versions.

Synchronous Truth Table

Operation Address

Used

State

Diagram

Key E1E2E3ADSP ADSC ADV WDQ3

Deselect Cycle, Power Down None X L X H X L X X High-Z

Deselect Cycle, Power Down None X L L X X L X X High-Z

Deselect Cycle, Power Down None X L X H L X X X High-Z

Deselect Cycle, Power Down None X L L X L X X X High-Z

Deselect Cycle, Power Down None X H X X X L X X High-Z

Read Cycle, Begin Burst External R L H L L X X X Q

Read Cycle, Begin Burst External R L H L H L X F Q

Write Cycle, Begin Burst External W L H L H L X T D

Read Cycle, Continue Burst Next CR X X X H H L F Q

Read Cycle, Continue Burst Next CR H X X X H L F Q

Write Cycle, Continue Burst Next CW X X X H H L T D

Write Cycle, Continue Burst Next CW H X X X H L T D

Read Cycle, Suspend Burst Current X X X H H H F Q

Read Cycle, Suspend Burst Current H X X X H H F Q

Write Cycle, Suspend Burst Current X X X H H H T D

Write Cycle, Suspend Burst Current H X X X H H T D

Notes:

1. X = Don’t Care, H = High, L = Low

2. E = T (True) if E2 = 1 and E1 = E3 = 0; E = F (False) if E2 = 0 or E1 = 1 or E3 = 1

3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.

4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown

as “Q” in the Truth Table above).

5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish

basic synchronous or synchronous burst operations and may be avoided for simplicity.

6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.

7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.

GS880F18/32/36CT-xxxI

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

First Write First Read

Burst Write Burst Read

Deselect

CRCW

Simple Synchronous OperationSimple Burst Synchronous Operation

CW CR

Notes:

1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.

2. The upper portion of the diagram assumes active use of only the Enable (E1, E2, and E3) and Write (BA, BB, BC, BD, BW, and GW) con-

trol inputs and that ADSP is tied high and ADSC is tied low.

3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs and

assumes ADSP is tied high and ADV is tied low.

GS880F18/32/36CT-xxxI

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Simplified State Diagram

First Write First Read

Burst Write Burst Read

Deselect

CRCW

CW CR

Notes:

1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.

2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passing

through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.

3. Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet

Data Input Set Up Time.

GS880F18/32/36CT-xxxI

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Simplified State Diagram with G

Absolute Maximum Ratings

(All voltages reference to VSS)

Symbol Description Value Unit

VDD Voltage on VDD Pins –0.5 to 4.6 V

VDDQ Voltage in VDDQ Pins –0.5 to 4.6 V

VI/O Voltage on I/O Pins –0.5 to VDD +0.5 (≤ 4.6 V max.) V

VIN Voltage on Other Input Pins –0.5 to VDD +0.5 (≤ 4.6 V max.) V

IIN Input Current on Any Pin +/–20 mA

IOUT Output Current on Any I/O Pin +/–20 mA

PDPackage Power Dissipation 1.5 W

TSTG Storage Temperature –55 to 125 oC

TBIAS Temperature Under Bias –55 to 125 oC

GS880F18/32/36CT-xxxI

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Notes:

Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended

Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of

this component.

Power Supply Voltage Ranges

Parameter Symbol Min. Typ. Max. Unit

3.3 V Supply V o ltage VDD3 3.0 3.3 3.6 V

2.5 V Supply V o ltage VDD2 2.3 2.5 2.7 V

3.3 V VDDQ I/O Supply Voltage VDDQ3 3.0 3.3 3.6 V

2.5 V VDDQ I/O Supply Voltage VDDQ2 2.3 2.5 2.7 V

VDD3 Range Logic Levels

Parameter Symbol Min. Typ. Max. Unit

VDD Input High Voltage VIH 2.0 —VDD + 0.3 V

VDD Input Low Vo ltag e VIL –0.3 —0.8 V

VDDQ Input High Voltage VIHQ 2.0 —VDDQ + 0.3 V

VDDQ Input Low Voltage VILQ –0.3 —0.8 V

Note:

VIHQ (max) is voltage on VDDQ pins plus 0.3 V.

GS880F18/32/36CT-xxxI

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

VDD2 Range Logic Levels

Parameter Symbol Min. Typ. Max. Unit

VDD Input High Voltage VIH 0.6*VDD —VDD + 0.3 V

VDD Input Low V oltage VIL –0.3 —0.3*VDD V

VDDQ Input Hig h Voltage VIHQ 0.6*VDD —VDDQ + 0.3 V

VDDQ Input Low Voltage VILQ –0.3 —0.3*VDD V

Note:

VIHQ (max) is voltage on VDDQ pins plus 0.3 V.

Recommended Operating Temperatures

Parameter Symbol Min. Typ. Max. Unit

Ambient Temperature (Industrial Range Versions)* TA–40 25 85 °C

Note:

The part numbers of Industrial Temperature Range versions end with the character “I”. Unless otherwise noted, all performance specifications

quoted are evaluated for worst case in the temperature range marked on the device.

Thermal Impedance

Package Test PCB

Substrate

θ JA (C°/W)

Airflow = 0 m/s

θ JA (C°/W)

Airflow = 1 m/s

θ JA (C°/W)

Airflow = 2 m/s θ JB (C°/W) θ JC (C°/W)

100 TQFP 4-layer 38.7 33.5 31.9 27.6 10.6

Notes:

1. Thermal Impedance data is based on a number of samples from multiple lots and should be viewed as a typical number.

2. Please refer to JEDEC standard JESD51-6.

3. The characteristics of the test fixture PCB influence reported thermal characteristics of the device. Be advised that a good thermal path to

the PCB can result in cooling or heating of the RAM depending on PCB temperature.

20% tKC

VSS – 2.0 V

50%

VSS

VIH

Undershoot Measurement and Timing Overshoot Measurement and Timing

20% tKC

VDD + 2.0 V

50%

VDD

VIL

Note:

Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

Capacitance

oC, f = 1 MHZ, VDD = 2.5 V)

Parameter Symbol Test conditions Typ. Max. Unit

Input Capacitance CIN VIN = 0 V 4 5 pF

Input/Output Capacitance CI/O VOUT = 0 V 6 7 pF

GS880F18/32/36CT-xxxI

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Note:

These parameters are sample tested.

AC Test Conditions

Parameter Conditions

Input high level VDD – 0.2 V

Input low level 0.2 V

Input slew rate 1 V/ns

Input reference level VDD/2

Output reference level VDDQ/2

Output load Fig. 1

Notes:

1. Include scope and jig capacitance.

2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted.

3. Device is deselected as defined by the Truth Table.

VDDQ/2

50Ω30pF*

Output Load 1

* Distributed Test Jig Capacitance

(TA = 25

DC Electrical Characteristics

Parameter Symbol Test Conditions Min Max

Input Leakage Current

(except mode pins) IIL VIN = 0 to VDD –1 uA 1 uA

ZZ Input Current IIN1 VDD ≥ VIN ≥ VIH

0 V ≤ VIN ≤ VIH

–1 uA

–1 uA 1 uA

100 uA

FT Input Current IIN2 VDD ≥ VIN ≥ VIL

0 V ≤ VIN ≤ VIL

–100 uA

–1 uA1 uA

1 uA

Output Leakage Current IOL Output Disable, VOUT = 0 to VDD –1 uA 1 uA

Output High Voltage VOH2 IOH = –8 mA, VDDQ = 2.375 V 1.7 V —

Output High Voltage VOH3 IOH = –8 mA, VDDQ = 3.135 V 2.4 V —

Output L ow Voltage VOL IOL = 8 mA —0.4 V

GS880F18/32/36CT-xxxI

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Operating Currents

Parameter Test Conditions Mode Symbol -4.5I -5I -5.5I -6.5I -7.5I Unit

–40

to 85°C –40

to 85°C

Operating

Current

Device Se le cted;

All other inputs

≥VIH or ≤ VIL

Output open

(x32/x36) Flow Through IDD

IDDQ

200

25 185

25 175

25 160

20 150

15 mA

(x18) Flow Through IDD

IDDQ

185

15 170

15 165

15 150

10 140

8mA

Standby

Current ZZ ≥ VDD – 0.2 V Flow Through ISB 45 45 45 45 45 mA

Deselect

Current

Device Deselected;

All other inputs

≥ VIH or ≤ VIL Flow Through IDD 90 85 85 85 80 mA

GS880F18/32/36CT-xxxI

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Notes:

1. IDD and IDDQ apply to any combination of VDD3, VDD2, VDDQ3, and VDDQ2 operation.

2. All parameters listed are worst case scenario.

AC Electrical Characteristics

Parameter Symbol -4.5I -5I -5.5I -6.5I -7.5I Unit

Min Max Min Max Min Max Min Max Min Max

Flow

Through

Clock Cycle Time tKC 4.5 —5.0 —5.5 —6.5 —7.5 —ns

Clock to Output Valid tKQ —4.5 —5.0 —5.5 —6.5 —7.5 ns

Clock to Output Invalid tKQX 2.0 —2.0 —2.0 —2.0 —2.0 —ns

Clock to Output in Low-Z tLZ12.0 —2.0 —2.0 —2.0 —2.0 —ns

Setup time tS 1.3 —1.4 —1.5 —1.5 —1.5 —ns

Hold time tH 0.3 —0.4 —0.5 —0.5 —0.5 —ns

Clock HIGH Time tKH 1.0 —1.0 —1.3 —1.3 —1.5 —ns

Clock LOW Time tKL 1.2 —1.2 —1.5 —1.5 —1.7 —ns

Clock to Output in

High-Z tHZ11.5 2.5 1.5 2.5 1.5 2.5 1.5 3.0 1.5 3.0 ns

G to Output Val id tOE —2.5 —2.5 —2.5 —3.0 —3.8 ns

G to output in Low-Z tOLZ10—0—0—0—0—ns

G to output in High-Z tOHZ1—2.5 —2.5 —2.5 —3.0 —3.8 ns

ZZ setup time tZZS25—5—5—5—5—ns

ZZ hold time tZZH21—1—1—1—1—ns

ZZ recovery tZZR 20 —20 —20 —20 —20 —ns

GS880F18/32/36CT-xxxI

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Notes:

1. These parameters are sampled and are not 100% tested.

2. ZZ is an asynchronous signal. However, In order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold

times as specified above.

GS880F18/32/36CT-xxxI

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Flow Through Mode Timing

Begin Read A Cont Cont Write B Read C Read C+1 Read C+2 Read C+3 Read C Cont Deselect

tHZtKQX

tKQ

tLZ

tOHZtOE

tKCtKC

tKLtKL

tKHtKH

ABC

Q(A) D(B) Q(C) Q(C+1) Q(C+2) Q(C+3) Q(C)

E2 and E3 only sampled with ADSC

ADSC initiated read

Deselected with E1

Fixed High

ADSP

ADSC

ADV

A0–An

Ba–Bd

DQa–DQd

GS880F18/32/36CT-xxxI

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Sleep Mode

During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high,

the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to

low, the SRAM operates normally after ZZ recovery time.

Sleep mode is a low current, power-down mode in whi c h the device is deselected and current is reduced to ISB2. The duration of

Sleep mode is dictated by the length of ti me th e ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become

disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.

When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending

operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initi ated

until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands

may be applied while the SRAM is recovering from Sleep mode.

Sleep Mode Timing Diagram

tZZR

tZZHtZZS

Hold

Setup

tKLtKL

tKHtKH

tKCtKC

ADSP

ADSC

GS880F18/32/36CT-xxxI

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

TQFP Package Drawing (Package T)

Pin 1

Notes:

1. All dimensions are in millimeters (mm).

2. Package width and length do not include mold protrusion.

Symbol Description Min. Nom. Max

A1 Standoff 0.05 0.10 0.15

A2 Body Thickness 1.35 1.40 1.45

b Lead Width 0.20 0.30 0.40

c Lead Thickness 0.09 —0.20

D Terminal Dimension 21.9 22.0 22.1

D1 Package Body 19.9 20.0 20.1

E Terminal Dimension 15.9 16.0 16.1

E1 Package Body 13.9 14.0 14.1

e Lead Pitch —0.65 —

L Foot Length 0.45 0.60 0.75

L1 Lead Length —1.00 —

Y Coplanarity 0.10

θLead Angle 0°—7°

GS880F18/32/36CT-xxxI

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Ordering Information for GSI Synchronous Burst RAMs

Org Part Number1Type Package Speed2

(MHz/ns) TA3

512K x 18 GS880F18CT-4.5I Flow Through TQFP 4.5 I

512K x 18 GS880F18CT-5I Flow Through TQFP 5 I

512K x 18 GS880F18CT-5.5I Flow Through TQFP 5.5 I

512K x 18 GS880F18CT-6.5I Flow Through TQFP 6.5 I

512K x 18 GS880F18CT-7.5I Flow Through TQFP 7.5 I

256K x 32 GS880F32CT-4.5I Flow Through TQFP 4.5 I

256K x 32 GS880F32CT-5I Flow Through TQFP 5 I

256K x 32 GS880F32CT-5.5I Flow Through TQFP 5.5 I

256K x 32 GS880F32CT-6.5I Flow Through TQFP 6.5 I

256K x 32 GS880F32CT-7.5I Flow Through TQFP 7.5 I

256K x 36 GS880F36CT-4.5I Flow Through TQFP 4.5 I

256K x 36 GS880F36CT-5I Flow Through TQFP 5 I

256K x 36 GS880F36CT-5.5I Flow Through TQFP 5.5 I

256K x 36 GS880F36CT-6.5I Flow Through TQFP 6.5 I

256K x 36 GS880F36CT-7.5I Flow Through TQFP 7.5 I

512K x 18 GS880F18CGT-4.5I Flow Through RoHS-compliant TQFP 4.5 I

512K x 18 GS880F18CGT-5I Flow Through RoHS-compliant TQFP 5 I

512K x 18 GS880F18CGT-5.5I Flow Through RoHS-compliant TQFP 5.5 I

512K x 18 GS880F18CGT-6.5I Flow Through RoHS-compliant TQFP 6.5 I

512K x 18 GS880F18CGT-7.5I Flow Through RoHS-compliant TQFP 7.5 I

256K x 32 GS880F32CGT-4.5I Flow Through RoHS-compliant TQFP 4.5 I

256K x 32 GS880F32CGT-5I Flow Through RoHS-compliant TQFP 5 I

256K x 32 GS880F32CGT-5.5I Flow Through RoHS-compliant TQFP 5.5 I

256K x 32 GS880F32CGT-6.5I Flow Through RoHS-compliant TQFP 6.5 I

256K x 32 GS880F32CGT-7.5I Flow Through RoHS-compliant TQFP 7.5 I

Notes:

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS880F18CT-5IT.

2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each

device is Pipeline/Flow through mode-selectable by the user.

3. TA = I = Industrial Temperature Range.

4. GSI offers other versions this type of device in ma ny dif ferent configurations and with a variety of different features, only some of which are

covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.

GS880F18/32/36CT-xxxI

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

256K x 36 GS880F36CGT-4.5I Flow Through RoHS-compliant TQFP 4.5 I

256K x 36 GS880F36CGT-5I Flow Through RoHS-compliant TQFP 5 I

256K x 36 GS880F36CGT-5.5I Flow Through RoHS-compliant TQFP 5.5 I

256K x 36 GS880F36CGT-6.5I Flow Through RoHS-compliant TQFP 6.5 I

256K x 36 GS880F36CGT-7.5I Flow Through RoHS-compliant TQFP 7.5 I

Ordering Information for GSI Synchronous Burst RAMs

Org Part Number1Type Package Speed2

(MHz/ns) TA3

Notes:

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS880F18CT-5IT.

2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each

device is Pipeline/Flow through mode-selectable by the user.

3. TA = I = Industrial Temperature Range.

4. GSI offers other versions this type of device in ma ny dif ferent configurations and with a variety of different features, only some of which are

covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.

9Mb Sync SRAM Datasheet Revision History

File Name Types of Changes

Format or Content Revision

880FxxC_r1 • Creation of new datasheet

880FxxC_r1_01 Content • Update to MP datasheet

880FxxC_r1_02 Content • Upd ated Absolute Maximum Ratings

• Deleted conditional text

880FxxC_r1_03 Content • Upd ated Absolute Maximum Ratings

• Added thermal information

• Updated Ordering Information

880FxxC_r1_04 Content • Upd ated Absolute Maximum Ratings

• Removed Comm Temp references

GS880F18/32/36CT-xxxI

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.