2018 Microchip Technology Inc. DS20005947B-page 1
MCP33131D/21D/11D-XX
Features
• Sample Rate (Throughput):
- MCP33131D/21D/11D-10: 1 Msps
- MCP33131D/21D/11D-05: 500 kSPS
• 16/14/12-Bit Resolution with No Missing Codes
• No Latency Output
• Wide Operating Voltage Range:
- Analog Supply Voltage (AVDD): 1.8V
- Digital Input/Output Interface Voltage (DVIO):
1.7V - 5.5V
- External Reference (VREF): 2.5V - 5.1V
• Differential Input Operation
- Input Full-Scale Range: -VREF to +VREF
•Ultra Low Current Consumption (typical):
- During Input Acquisition (Standby): ~ 0.8 µA
- During Conversion:
MCP33131D/21D/11D-10: ~1.6 mA
MCP33131D/21D/11D-05: ~1.4 mA
• SPI-Compatible Serial Communication:
- SCLK Clock Rate: up to 100 MHz
• ADC Self-Calibration for Offset, Gain, and
Linearity Errors:
- During Power-Up (automatic)
- On-Demand via user’s command during
normal operation
• AEC-Q100 Qualified:
- Temperature Grade 1: -40°C to +125°C
• Package Options: MSOP-10 and TDFN-10
Typical Applications
• High-Precision Data Acquisition
• Medical Instruments
• Test Equipment
• Electric Vehicle Battery Management Systems
• Motor Control Applications
• Switch-Mode Power Supply Applications
• Battery-Powered Equipment
System Design Supports
The MCP331x1D-XX Evaluation Kit demonstrates the
performance of the MCP331x1D-XX SAR ADC family
devices. The evaluation kit includes: (a) MCP331x1D
Evaluation Board, (b) PIC32MZ EF Curiosity Board for
data collection, and (c) SAR ADC Utility PC GUI.
Contact Microchip Technology Inc. for the evaluation
tools and the PIC32 MCU firmware example codes.
Package Types
10
MSOP-10
AIN+
AVDD
AIN-
SDI
SCLK
1
2
3
4
9
8
7SDO
DVIO
VREF
TDFN-10
AIN+
AVDD
AIN-
SDI
SCLK
1
2
3
4
10
9
8
7SDO
DVIO
VREF
56
GND CNVST
56
GND CNVST
Top View
Top Vi e w
MCP331x1D-XX Device Offering (Note 1):
Part Number Resolution Sample
Rate Input Type Input Range
(Differential)
Performance (Typical)
SNR
(dBFS)
SFDR
(dB)
THD
(dB)
INL
(LSB)
DNL
(LSB)
MCP33131D-10 16-bit 1 Msps Differential ±5.1V 91.3 103.5 -99.3 ±2 ±0.8
MCP33121D-10 14-bit 1 Msps Differential ±5.1V 85.1 103.5 -99.2 ±0.5 ±0.25
MCP33111D-10 12-bit 1 Msps Differential ±5.1V 73.9 99.3 -96.7 ±0.12 ±0.06
MCP33131D-05 16-bit 500 kSPS Differential ±5.1V 91.3 103.5 -99.3 ±2 ±0.8
MCP33121D-05 14-bit 500 kSPS Differential ±5.1V 85.1 103.5 -99.2 ±0.5 ±0.25
MCP33111D-05 12-bit 500 kSPS Differential ±5.1V 73.9 99.3 -96.7 ±0.12 ±0.06
Note 1: SNR, SFDR, and THD are measured with fIN = 10 kHz, VIN = -1 dBFS, VREF = 5.1V.
1 Msps/500 kSPS 16/14/12-Bit Differential Input SAR ADC
MCP33131D/MCP33121D/MCP33111D-XX
DS20005947B-page 2 2018 Microchip Technology Inc.
Application Diagram
Description
The MCP33131D/MCP33121D/MCP33111D-10 and
MCP33131D/MCP33121D/MCP33111D-05 are
fully-differential 16, 14, and 12-bit, single-channel
1 Msps and 500 kSPS ADC family devices,
respectively, featuring low power consumption and
high performance, using a successive approximation
register (SAR) architecture.
The device operates with a 2.5V to 5.1V external
reference (VREF), which supports a wide range of input
full-scale range from -VREF to +VREF
. The reference
voltage setting is independent of the analog supply
voltage (AVDD) and is higher than AVDD. The
conversion output is available through an easy-to-use
simple SPI- compatible 3-wire interface.
The device requires a 1.8V analog supply voltage
(AVDD) and a 1.7V to 5.5V digital I/O interface supply
voltage (DVIO). The wide digital I/O interface supply
(DVIO) range (1.7V – 5.5V) allows the device to
interface with most host devices (Master) available in
the current industry such as the PIC32
microcontrollers, without using external voltage level
shifters.
When the device is first powered-up, it performs a
self-calibration to minimize offset, gain and linearity
errors. The device performance stays stable across the
specified temperature range. However, when extreme
changes in the operating environment, such as in the
reference voltage, are made with respect to the initial
conditions (e.g. the reference voltage was not fully
settled during the initial power-up sequence), the user
may send a recalibrate command anytime to initiate
another self-calibration to restore optimum
performance.
When the initial power-up sequence is completed, the
device enters a low-current input acquisition mode,
where sampling capacitors are connected to the input
pins. This mode is called Standby.
During Standby, most of the internal analog circuitry is
shutdown in order to reduce current consumption.
Typically, the device consumes less than 1 µA during
Standby. A new conversion is started on the rising edge
of CNVST. When the conversion is complete and the
host lowers CNVST, the output data is presented on
SDO, and the device enters Standby to begin acquiring
the next input sample. The user can clock out the ADC
output data using the SPI-compatible serial clock
during Standby.
The ADC system clock is generated by the internal
on-chip clock, therefore the conversion is performed
independent of the SPI serial clock (SCLK).
This device can be used for various high-speed and
high-accuracy analog-to-digital data conversion
applications, where design simplicity, low power, and
no output latency are needed.
The device is AEC-Q100 qualified for automotive appli-
cations and operates over the extended temperature
range of -40°C to +125°C. The available package
options are Pb-free small 3 mm x 3 mm TDFN-10 and
MSOP-10.
1.7 nF
22Ω
0V to VREF
AIN+
AIN-
VREF AVDD DVIO
SDI
SCLK
SDO
CNVST
2.5V to 5.1V 1.8V 1.8V to 5.5V
GND
(PIC32MZ)
Host Device
1.7 nF
22Ω
0V to VREF
MCP331x1D-XX
2018 Microchip Technology Inc. DS20005947B-page 3
MCP33131D/MCP33121D/MCP33111D-XX
1.0 KEY ELECTRICAL
CHARACTERISTICS
1.1 Absolute Maximum Ratings†
External Analog Supply Voltage (AVDD)............. -0.3V to 2.0V
External Digital Supply Voltage (DVIO)............... -0.3V to 5.8V
External Reference Voltage (VREF).................... -0.3V to 5.8V
Analog Inputs w.r.t GND ............... .......... -0.3V to VREF+0.3V
Current at Input Pins ....................................................±2 mA
Current at Output and Supply Pins ..........................±250 mA
Storage Temperature ....................................-65°C to +150°C
Maximum Junction Temperature (TJ). .........................+150°C
ESD protection on all pins .... ≤2kV HBM, ≤200V MM, ≤2kV CDM
†Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
1.2 Electrical Specifications
TABLE 1-1: KEY ELECTRICAL CHARACTERISTICS
Electrical Specifications: Unless otherwise specified, all parameters apply for TA= -40°C to +125°C, AVDD =1.8V, DV
IO =3.3V, V
REF =5V,
GND = 0V, Differential Analog Input (VIN) = -1 dBFS sine wave, fIN =10kHz, C
LOAD_SDO =20pF
• MCP331x1D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
• MCP331x1D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
Parameters Sym. Min. Typ. Max. Units Conditions
Power Supply Requirements
Analog Supply Voltage Range AVDD 1.7 1.8 1.9 V (Note 3)
Digital Input/Output Interface Voltage
Range
DVIO 1.7 — 5.5 V (Note 3)
Analog Supply Current at AVDD pin:
During Conversion
During Standby
IDDAN
IDDAN_STBY
—
—
—
1.6
1.4
0.8
2.4
2.0
—
mA
mA
µA
fs = 1 Msps (MCP331x1D-10)
fs = 500 kSPS (MCP331x1D-05)
During input acquisition (tACQ)
Digital Supply Current At DVDD pin:
During Output Data Reading
During Standby
IIO_DATA
IIO_STBY
—
—
—
290
200
30
—
—
—
A
A
nA
fs = 1 Msps (MCP331x1D-10)
fs = 500 kSPS (MCP331x1D-05)
During input acquisition (tACQ)
External Reference Voltage Input
Reference Voltage
(Note 2), (Note 3)
VREF 2.5
2.7
5.1
5.1
V-40°C ≤TA≤ 85°C
85°C < TA≤ 125°C
Reference Load Current at VREF pin:
During Conversion
During Standby
IREF
IREF_STBY
—
—
450
220
240
600
360
—
µA
µA
nA
fs = 1 Msps (MCP331x1D-10)
fs = 500 kSPS (MCP331x1D-05)
During input acquisition (tACQ)
Total Power Consumption (Including AVDD, DVIO, VREF pins)
MCP331x1D-10
at 1 Msps
at 500 kSPS
at 100 kSPS
During Standby
PDISS_TOTAL
PDISS_STBY
—
—
—
—
6.2
3.1
0.6
2.6
—
—
—
—
mW
mW
mW
W
Averaged power for tACQ + tCNV
During input acquisition (tACQ)
MCP331x1D-05
at 500 kSPS
at 100 kSPS
During Standby
PDISS_TOTAL
PDISS_STBY
—
—
—
4.2
0.8
2.6
—
—
—
mW
mW
W
Averaged power for tACQ + tCNV
During input acquisition (tACQ)
Note 1: This parameter is ensured by design and not 100% tested.
2: This parameter is ensured by characterization and not 100% tested.
3: Decoupling capacitor is recommended on the following pins:
(a) AVDD pin: 1 F ceramic capacitor, (b) DVIO pin: 0.1 F ceramic capacitor, (c) VREF pin: 10 F tantalum capacitor.
4: Differential Input Full-Scale Range (FSR) = 2 x VREF
5: PSRR (dB) = -20 log (DVOUT/AVDD), where DVOUT = change in conversion result.
6: ENOB = (SINAD - 1.76)/6.02
DS20005947B-page 4 2018 Microchip Technology Inc.
MCP33131D/MCP33121D/MCP33111D-XX
Analog Inputs
Input Voltage Range
(Note 2)
VIN+ -0.1 — VREF+0.1 V Differential Input:
VIN = (VIN+ - VIN-)
VIN- -0.1 — VREF+0.1 V
Input Full-Scale Voltage Range FSR -VREF —+V
REF VPP Differential Input (Note 2), (Note 4)
Input Common-Mode Voltage Range VCM 0V
REF/2 VREF (Note 2)
Input Sampling Capacitance CS—31—pF(Note 1)
-3dB Input Bandwidth BW-3dB —25—MHz
(Note 1)
Aperture Delay
(Note 1)
— 2.5 — ns Time delay between CNVST rising
edge and when input is sampled
Leakage Current at Analog Input Pin ILEAK_AN_INPUT — ±2 ±200 nA During input acquisition (tACQ)
System Performance
Sample Rate
(Throughput rate)
fs— — 1 Msps MCP331x1D-10
— — 500 kSPS MCP331x1D-05
Resolution
(No Missing Codes)
16 — — Bits MCP33131D-10 and MCP33131D-05
14 — — Bits MCP33121D-10 and MCP33121D-05
12 — — Bits MCP33111D-10 and MCP33111D-05
Integral Nonlinearity INL -6 ±2 +6 LSB MCP33131D-10 and MCP33131D-05
-1.5 ±0.5 +1.5 LSB MCP33121D-10 and MCP33121D-05
±0.12 LSB MCP33111D-10 and MCP33111D-05
Differential Nonlinearity DNL -0.98 ±0.8 +1.8 LSB MCP33131D-10 and MCP33131D-05
-0.8 ±0.25 +0.8 LSB MCP33121D-10 and MCP33121D-05
-0.3 ±0.06 +0.3 LSB MCP33111D-10 and MCP33111D-05
Offset Error ±0.1 ±2.3 mV MCP33131D-10 and MCP33131D-05
— ±0.125 ±3 mV MCP33121D-10 and MCP33121D-05
—±0.8 ±3.66 mV MCP33111D-10 and MCP33111D-05
Offset Error Drift with Temperature — ±0.8 — V/oC
Gain Error GER —±2 —LSB MCP33131D-10 and MCP33131D-05
— ±0.5 — LSB MCP33121D-10 and MCP33121D-05
—±0.1 —LSB MCP33111D-10 and MCP33111D-05
Gain Error Drift with temperature — ±0.35 — V/oC
Input common-mode rejection ratio CMRR — 84 — dB
Power Supply Rejection Ratio PSRR — 70 — dB (Note 5)
TABLE 1-1: KEY ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise specified, all parameters apply for TA= -40°C to +125°C, AVDD =1.8V, DV
IO =3.3V, V
REF =5V,
GND = 0V, Differential Analog Input (VIN) = -1 dBFS sine wave, fIN =10kHz, C
LOAD_SDO =20pF
• MCP331x1D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
• MCP331x1D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
Parameters Sym. Min. Typ. Max. Units Conditions
Note 1: This parameter is ensured by design and not 100% tested.
2: This parameter is ensured by characterization and not 100% tested.
3: Decoupling capacitor is recommended on the following pins:
(a) AVDD pin: 1 F ceramic capacitor, (b) DVIO pin: 0.1 F ceramic capacitor, (c) VREF pin: 10 F tantalum capacitor.
4: Differential Input Full-Scale Range (FSR) = 2 x VREF
5: PSRR (dB) = -20 log (DVOUT/AVDD), where DVOUT = change in conversion result.
6: ENOB = (SINAD - 1.76)/6.02
2018 Microchip Technology Inc. DS20005947B-page 5
MCP33131D/MCP33121D/MCP33111D-XX
Dynamic Performance
Signal-to-Noise Ratio SNR MCP33131D-10 and MCP33131D-05: 16-bit ADC
— 91.6 — dBFS VREF = 5V, fIN = 1 kHz
— 86.6 — VREF = 2.5V, fIN = 1 kHz
88.7 91.3 — VREF = 5V, fIN = 10 kHz
— 86.6 — VREF = 2.5V, fIN = 10 kHz
MCP33121D-10 and MCP33121D-05: 14-bit ADC
— 85.2 — dBFS VREF = 5V, fIN = 1 kHz
— 83.5 — VREF = 2.5V, fIN = 1 kHz
81.7 85.1 — VREF = 5V, fIN = 10 kHz
— 83.5 — VREF = 2.5V, fIN = 10 kHz
MCP33111D-10 and MCP33111D-05: 12-bit ADC
— 73.9 — dBFS VREF = 5V, fIN = 1 kHz
— 73.8 — VREF = 2.5V, fIN = 1 kHz
71.1 73.9 — VREF = 5V, fIN = 10 kHz
— 73.8 — VREF = 2.5V, fIN = 10 kHz
Signal-to-Noise and Distortion Ratio
(Note 6)
SINAD MCP33131D-10 and MCP33131D-05: 16-bit ADC
— 91.5 — dBFS VREF = 5V, fIN = 1 kHz
— 86.6 — VREF = 2.5V, fIN = 1 kHz
—91— V
REF = 5V, fIN = 10 kHz
— 86.2 — VREF = 2.5V, fIN = 10 kHz
MCP33121D-10 and MCP33121D-05: 14-bit ADC
— 85.2 — dBFS VREF = 5V, fIN = 1 kHz
— 83.5 — VREF = 2.5V, fIN = 1 kHz
—85— V
REF = 5V, fIN = 10 kHz
— 83.3 — VREF = 2.5V, fIN = 10 kHz
MCP33111D-10 and MCP33111D-05: 12-bit ADC
— 73.9 — dBFS VREF = 5V, fIN = 1 kHz
— 73.8 — VREF = 2.5V, fIN = 1 kHz
— 73.9 — VREF = 5V, fIN = 10 kHz
— 73.8 — VREF = 2.5V, fIN = 10 kHz
TABLE 1-1: KEY ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise specified, all parameters apply for TA= -40°C to +125°C, AVDD =1.8V, DV
IO =3.3V, V
REF =5V,
GND = 0V, Differential Analog Input (VIN) = -1 dBFS sine wave, fIN =10kHz, C
LOAD_SDO =20pF
• MCP331x1D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
• MCP331x1D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
Parameters Sym. Min. Typ. Max. Units Conditions
Note 1: This parameter is ensured by design and not 100% tested.
2: This parameter is ensured by characterization and not 100% tested.
3: Decoupling capacitor is recommended on the following pins:
(a) AVDD pin: 1 F ceramic capacitor, (b) DVIO pin: 0.1 F ceramic capacitor, (c) VREF pin: 10 F tantalum capacitor.
4: Differential Input Full-Scale Range (FSR) = 2 x VREF
5: PSRR (dB) = -20 log (DVOUT/AVDD), where DVOUT = change in conversion result.
6: ENOB = (SINAD - 1.76)/6.02
DS20005947B-page 6 2018 Microchip Technology Inc.
MCP33131D/MCP33121D/MCP33111D-XX
Spurious Free Dynamic Range SFDR MCP33131D-10 and MCP33131D-05: 16-bit ADC
— 103.7 — dBc VREF = 5V, fIN = 1 kHz
—98— V
REF = 2.5V, fIN = 1 kHz
— 103.5 — VREF = 5V, fIN = 10 kHz
— 97.5 — VREF = 2.5V, fIN = 10 kHz
MCP33121D-10 and MCP33121D-05: 14-bit ADC
— 103.6 — dBc VREF = 5V, fIN = 1 kHz
—98— V
REF = 2.5V, fIN = 1 kHz
— 103.5 — VREF = 5V, fIN = 10 kHz
— 97.4 — VREF = 2.5V, fIN = 10 kHz
MCP33111D-10 and MCP33111D-05: 12-bit ADC
— 99.3 — dBc VREF = 5V, fIN = 1 kHz
— 97.7 — VREF = 2.5V, fIN = 1 kHz
— 99.3 — VREF = 5V, fIN = 10 kHz
— 97.2 — VREF = 2.5V, fIN = 10 kHz
Total Harmonic Distortion
(first five harmonics)
THD MCP33131D-10 and MCP33131D-05: 16-bit ADC
— -100.4 — dBc VREF = 5V, fIN = 1 kHz
— -95.4 — VREF = 2.5V, fIN = 1 kHz
— -99.3 — VREF = 5V, fIN = 10 kHz
— -95.4 — VREF = 2.5V, fIN = 10 kHz
MCP33121D-10 and MCP33121D-05: 14-bit ADC
— -100.1 — dBc VREF = 5V, fIN = 1 kHz
— -95.3 — VREF = 2.5V, fIN = 1 kHz
— -99.2 — VREF = 5V, fIN = 10 kHz
— -95.3 — VREF = 2.5V, fIN = 10 kHz
MCP33111D-10 and MCP33111D-05: 12-bit ADC
— -97.5 — dBc VREF = 5V, fIN = 1 kHz
— -94.4 — VREF = 2.5V, fIN = 1 kHz
— -96.7 — VREF = 5V, fIN = 10 kHz
— -94.4 — VREF = 2.5V, fIN = 10 kHz
TABLE 1-1: KEY ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise specified, all parameters apply for TA= -40°C to +125°C, AVDD =1.8V, DV
IO =3.3V, V
REF =5V,
GND = 0V, Differential Analog Input (VIN) = -1 dBFS sine wave, fIN =10kHz, C
LOAD_SDO =20pF
• MCP331x1D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
• MCP331x1D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
Parameters Sym. Min. Typ. Max. Units Conditions
Note 1: This parameter is ensured by design and not 100% tested.
2: This parameter is ensured by characterization and not 100% tested.
3: Decoupling capacitor is recommended on the following pins:
(a) AVDD pin: 1 F ceramic capacitor, (b) DVIO pin: 0.1 F ceramic capacitor, (c) VREF pin: 10 F tantalum capacitor.
4: Differential Input Full-Scale Range (FSR) = 2 x VREF
5: PSRR (dB) = -20 log (DVOUT/AVDD), where DVOUT = change in conversion result.
6: ENOB = (SINAD - 1.76)/6.02
2018 Microchip Technology Inc. DS20005947B-page 7
MCP33131D/MCP33121D/MCP33111D-XX
System Self-Calibration
Self-Calibration Time tCAL — 500 650 ms (Note 2)
Number of SCLK Clocks for
Recalibrate Command
ReCalNSCLK — 1024 — clocks Includes clocks for data bits
Serial Interface Timing Information: See Table 1-2
Digital Inputs/Outputs
High-level Input voltage VIH 0.7 * DVIO —DV
IO + 0.3 V DVIO ≥2.3V
0.9 * DVIO —DV
IO + 0.3 V DVIO <2.3V
Low-level input voltage VIL -0.3 — 0.3 * DVIO VDV
IO ≥2.3V
-0.3 — 0.2 * DVIO VDV
IO <2.3V
Hysteresis of Schmitt Trigger Inputs VHYST —0.2 * DV
IO — V All digital inputs
Low-level output voltage VOL — — 0.2 * DVIO VI
OL = 500 µA (sink)
High-level output voltage VOH 0.8 * DVIO — —VI
OL = - 500 µA (source)
Input leakage current ILI — — ±1 µA CNVST/SDI/SCLK = GND or DVIO
Output leakage current ILO — — ±1 µA Output is high-Z, SDO = GND or
DVIO
Internal capacitance
(all digital inputs and outputs)
CINT —7—pFT
A = 25°C (Note 1)
TABLE 1-1: KEY ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise specified, all parameters apply for TA= -40°C to +125°C, AVDD =1.8V, DV
IO =3.3V, V
REF =5V,
GND = 0V, Differential Analog Input (VIN) = -1 dBFS sine wave, fIN =10kHz, C
LOAD_SDO =20pF
• MCP331x1D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
• MCP331x1D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
Parameters Sym. Min. Typ. Max. Units Conditions
Note 1: This parameter is ensured by design and not 100% tested.
2: This parameter is ensured by characterization and not 100% tested.
3: Decoupling capacitor is recommended on the following pins:
(a) AVDD pin: 1 F ceramic capacitor, (b) DVIO pin: 0.1 F ceramic capacitor, (c) VREF pin: 10 F tantalum capacitor.
4: Differential Input Full-Scale Range (FSR) = 2 x VREF
5: PSRR (dB) = -20 log (DVOUT/AVDD), where DVOUT = change in conversion result.
6: ENOB = (SINAD - 1.76)/6.02
DS20005947B-page 8 2018 Microchip Technology Inc.
MCP33131D/MCP33121D/MCP33111D-XX
TABLE 1-2: SERIAL INTERFACE TIMING SPECIFICATIONS
TABLE 1-3: TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise specified, all parameters apply for TA= -40°C to +125°C, AVDD =1.8V, DV
IO =3.3V, V
REF =5V,
GND = 0V, Differential Analog Input (VIN) = -1 dBFS sine wave, fIN =10kHz, C
LOAD_SDO = 20 pF. +25°C is applied for typical value. All timings are
measured at 50%. See Figure 1-1 for timing diagram.
• MCP331x1D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
• MCP331x1D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
Parameters Symbol Min. Typ. Max. Units Conditions
Serial Clock frequency fSCLK — — 100 MHz See tSCLK specification
SCLK Period tSCLK 10 — — ns DVIO ≥ 3.3V, fSCLK = 100 MHz (Max)
12 — — ns DVIO ≥ 2.3V, fSCLK = 83.3 MHz (Max)
16 — — ns DVIO ≥ 1.7V, fSCLK = 62.5 MHz (Max)
SCLK Low Time tSCLK_L 3— —ns
DVIO ≥ 2.3V
4.5 — — ns DVIO ≥ 1.7V
SCLK High Time tSCLK_H 3— —ns
DVIO ≥ 2.3V
4.5 — — ns DVIO ≥ 1.7V
Output Valid from SCLK Low tDO —— 9.5nsDV
IO ≥ 3.3V
—— 12nsDV
IO ≥ 2.3V
—— 16nsDV
IO ≥ 1.7V
Quiet time tQUIET 10 — — ns (Note 2)
3-Wire Operation:
SDI Valid Setup time tSU_SDIH_CNV 5 — — ns SDI High to CNVST Rising Edge
CNVST Pulse Width High Time tCNVH 10 — — ns
Output Enable Time tEN —— 10nsDV
IO ≥ 2.3V
—— 15nsDV
IO ≥ 1.7V
Output Disable Time tDIS —— 15ns(Note 2)
MCP331x1D-10
Sample Rate fs— — 1 Msps Throughput rate
Input Acquisition Time
(Note 2)
tACQ 290
250
300 —
—
ns -40°C ≤TA≤ 85°C
85°C < TA≤ 125°C
Data Conversion Time tCNV —
—
700 710
750
ns -40°C ≤TA≤ 85°C
85°C < TA≤ 125°C
Time between Conversions tCYC 1— —µst
CYC = tACQ + tCNV, fS = 1 Msps
MCP331x1D-05
Sample Rate fs— — 500 kSPS Throughput rate
Input Acquisition Time (Note 2) tACQ 700 800 — ns -40°C ≤TA≤ 125°C
Data Conversion Time tCNV — 1200 1300 ns -40°C ≤TA≤ 125°C
Time between Conversions tCYC 2— —µst
CYC = tACQ + tCNV, fS = 500 kSPS
Note 1: This parameter is ensured by design and not 100% tested.
2: This parameter is ensured by characterization and not 100% tested.
Parameters Symbol Min. Typ. Max. Units Conditions
Temperature Ranges
Operating Temperature Range TA-40 — +125 °C (Note 1)
Storage Temperature Range TA-65 — +150 °C (Note 1)
Thermal Package Resistance
Thermal Resistance, MSOP-10 JA — 202 — °C/W
Thermal Resistance, TDFN-10 JA —68—°C/W
Note 1: The internal junction temperature (Tj) must not exceed the absolute maximum specification of +150oC.
2018 Microchip Technology Inc. DS20005947B-page 9
MCP33131D/MCP33121D/MCP33111D-XX
FIGURE 1-1: Interface Timing Diagram. CNVST is used as chip select. See Figure 7-2 for more
details.
CNVST
SDO
SCLK 123n-1 n
Dn-1 Dn-2 Dn-3 D1D0
ADC State
(MSB)
Hi-Z Hi-Z
tCNVH
tCNV (MAX)
tSCLK
tSCLK_L tSCLK_H
tDO
tDIS
Conversion
2: tEN when CNVST is lowered after tCNV (MAX).
Input Acquisition
Input Acquisition
(tCNV)(tACQ)
(tACQ)
tCYC
SDI = “High”
tSU_SDIH_CNV
tEN
tQUIET
tEN
3: tEN when CNVST is lowered before tCNV (MAX).
= 1/fS
(Note 2)
(Note 3)
(Note 1)
Note 1: n = 16 for 16-bit, 14 for 14-bit device, and 12 for 12-bit device.
DS20005947B-page 10 2018 Microchip Technology Inc.
MCP33131D/MCP33121D/MCP33111D-XX
NOTES:
2017 Microchip Technology Inc. DS20005947B-page 11
MCP33131D/MCP33121D/MCP33111D-XX
2.0 TYPICAL PERFORMANCE CURVES FOR 16-BIT DEVICES (MCP33131D-XX)
Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33131D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33131D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
FIGURE 2-1: INL vs. Output Code.
FIGURE 2-2: DNL vs. Output Code.
FIGURE 2-3: INL vs. Temperature.
FIGURE 2-4: INL vs. Output Code.
FIGURE 2-5: DNL vs. Output Code.
FIGURE 2-6: DNL vs. Temperature.
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
0 16,384 32,768 49,152 65,536
Code
-2
-1
0
1
2
INL (LSB)
V
REF
= 5V
0 16,384 32,768 49,152 65,536
Code
-1
-0.5
0
0.5
1
DNL (LSB)
V
REF
= 5V
-40 -20 0 20 40 60 80 100 120 140
Temperature (oC)
-3
-2
-1
0
1
2
3
INL (LSB)
VREF = 5V
Max INL (LSB)
Min INL (LSB)
0 16,384 32,768 49,152 65,536
Code
-3
-2
-1
0
1
2
3
INL (LSB)
V
REF
= 2.5V
0 16,384 32,768 49,152 65,536
Code
-1
-0.5
0
0.5
1
DNL (LSB)
V
REF
= 2.5V
-40 -20 0 20 40 60 80 100 120 140
Temperature (
o
C)
-1
-0.5
0
0.5
1
DNL (LSB)
V
REF
= 5V
Max DNL (LSB)
Min DNL (LSB)
MCP33131D/MCP33121D/MCP33111D-XX
DS20005947B-page 12 2017 Microchip Technology Inc.
Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33131D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33131D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
FIGURE 2-7: INL vs. Reference Voltage.
FIGURE 2-8: FFT for 10 kHz Input Signal:
fS = 1 Msps, VIN = -1 dBFS, VREF = 5V.
FIGURE 2-9: FFT for 10 kHz Input Signal:
fS = 500 kSPS, VIN = -1 dBFS, VREF = 5V.
FIGURE 2-10: DNL vs. Reference Voltage.
FIGURE 2-11: FFT for 10 kHz Input Signal:
fS = 1 Msps, VIN = -1 dBFS, VREF = 2.5V.
FIGURE 2-12: FFT for 10 kHz Input Signal:
fS = 500 kSPS, VIN = -1 dBFS, VREF = 2.5V.
2 2.5 3 3.5 4 4.5 5 5.5
Reference Voltage (V)
-4
-3
-2
-1
0
1
2
3
4
INL (LSB)
Max INL (LSB)
Min INL (LSB)
0 100 200 300 400 500
Frequency (kHz)
-160
-140
-120
-100
-80
-60
-40
-20
0
Amplitude (dBFS)
VREF = 5V
fs = 1 Msps
SNR = 91.5 dBFS
SINAD = 91.3 dBFS
SFDR = 108.5 dBc
THD = -102.2 dBc
Offset = 1 LSB
Resolution = 16-bit
MCP33131D-10
0 50 100 150 200 250
Frequency (kHz)
-160
-140
-120
-100
-80
-60
-40
-20
0
Amplitude (dBFS)
VREF = 5V
fs = 0.5 Msps
SNR = 91.5 dBFS
SINAD = 91.3 dBFS
SFDR = 108.0 dBc
THD = -102.5 dBc
Offset = 1 LSB
Resolution = 16-bit
MCP33131D-05
2 2.5 3 3.5 4 4.5 5 5.5
Reference Voltage (V)
-1
-0.5
0
0.5
1
DNL (LSB)
Min DNL (LSB)
Max DNL (LSB)
0 100 200 300 400 500
Frequency (kHz)
-160
-140
-120
-100
-80
-60
-40
-20
0
Amplitude (dBFS)
VREF = 2.5V
fs = 1 Msps
SNR = 86.7 dBFS
SINAD = 86.2 dBFS
SFDR = 97.4 dBc
THD = -95.6 dBc
Offset = -2 LSB
Resolution = 16-bit
MCP33131D-10
MCP33131D-05
2017 Microchip Technology Inc. DS20005947B-page 13
MCP33131D/MCP33121D/MCP33111D-XX
Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33131D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33131D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
FIGURE 2-13: SNR/SINAD/ENOB vs. VREF
FIGURE 2-14: SNR/SINAD vs.
Temperature: VREF = 5V.
FIGURE 2-15: SNR/SINAD vs. Input
Amplitude: FIN = 10 kHz.
FIGURE 2-16: SFDR/THD vs. VREF
FIGURE 2-17: SNR/SINAD vs.
Temperature: VREF = 2.5V.
FIGURE 2-18: SNR/SINAD vs. Input
Amplitude: FIN = 10 kHz.
2 2.5 3 3.5 4 4.5 5 5.5
Reference Voltage (V)
80
82.5
85
87.5
90
92.5
95
SNR/SINAD (dB)
2 2.5 3 3.5 4 4.5 5 5.5
Reference Voltage (V)
12.5
13.5
14.5
15.5
ENOB (Bits)
ENOB
SNR (dB)
SINAD (dB)
-40 -20 0 20 40 60 80 100 120 140
Temperature (oC)
89.6
89.8
90
90.2
90.4
90.6
SNR/SINAD (dB)
SNR (dB)
SINAD (dB)
VREF = 5V
-30 -25 -20 -15 -10 -5 0
Input Amplitude (dBFS)
85
87
89
91
93
95
SNR/SINAD (dBFS)
SNR (dBFS)
SINAD(dBFS)
VREF = 5V
2 2.5 3 3.5 4 4.5 5 5.5
Reference Voltage (V)
-101
-98
-95
-92
THD (dB)
2 2.5 3 3.5 4 4.5 5 5.5
Reference Voltage (V)
92
97
102
107
SFDR (dB)
THD (dB)
SFDR (dB)
-40 -20 0 20 40 60 80 100 120 140
Temperature (oC)
83
84
85
86
87
SNR/SINAD (dB)
SNR (dB)
SINAD (dB)
VREF = 2.5V
-30 -25 -20 -15 -10 -5 0
Input Amplitude (dBFS)
80
81
82
83
84
85
86
87
88
89
90
SNR/SINAD (dBFS)
SNR (dBFS)
SINAD(dBFS)
V
REF
= 2.5V
MCP33131D/MCP33121D/MCP33111D-XX
DS20005947B-page 14 2017 Microchip Technology Inc.
Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33131D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33131D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
FIGURE 2-19: SNR/SINAD vs.Input
Frequency: VIN = -1 dBFS.
FIGURE 2-20: THD/SFDR vs.
Temperature: VREF = 5V.
FIGURE 2-21: THD/SFDR vs. Input
Frequency: VREF = 5V.
FIGURE 2-22: SNR/SINAD vs.Input
Frequency: VIN = -1 dBFS.
FIGURE 2-23: THD/SFDR vs.
Temperature: VREF = 2.5V.
FIGURE 2-24: THD/SFDR vs. Input
Frequency: VREF = 2.5V.
10
0
10
1
10
2
10
3
Input Frequency (kHz)
70
75
80
85
90
95
SNR/SINAD (dB)
SNR (dB)
SINAD (dB)
V
REF
= 5V
-40 -20 0 20 40 60 80 100 120 140
Temperature (oC)
-102
-100
-98
-96
-94
-92
THD (dB)
THD (dB)
SFDR (dB)
96
98
100
102
104
106
SFDR (dB)
V
REF
= 5V
10
0
10
1
10
2
10
3
Input Frequency (kHz)
-110
-105
-100
-95
-90
-85
-80
-75
THD (dB)
75
80
85
90
95
100
105
110
SFDR (dB)
THD (dB)
SFDR (dB)
V
REF
= 5V
10
0
10
1
10
2
10
3
Input Frequency (kHz)
70
75
80
85
90
95
SNR/SINAD (dB)
SNR (dB)
SINAD (dB)
V
REF
= 2.5V
-40 -20 0 20 40 60 80 100 120 140
Temperature (oC)
-98
-97
-96
-95
-94
-93
-92
THD (dB)
THD (dB)
SFDR (dB)
94
95
96
97
98
99
100
SFDR (dB)
VREF = 2.5V
10
0
10
1
10
2
10
3
Input Frequency (kHz)
-110
-105
-100
-95
-90
-85
-80
-75
THD (dB)
75
80
85
90
95
100
105
110
SFDR (dB)
THD (dB)
SFDR (dB)
V
REF
= 2.5V
2017 Microchip Technology Inc. DS20005947B-page 15
MCP33131D/MCP33121D/MCP33111D-XX
Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33131D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33131D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
FIGURE 2-25: THD/SFDR vs. Input
Amplitude: VREF = 5V.
FIGURE 2-26: Shorted Input Histogram:
VREF = 5V.
FIGURE 2-27: Offset and Gain Error vs.
Temperature: VREF = 5V.
FIGURE 2-28: THD/SFDR vs. Input
Amplitude: VREF = 2.5V.
FIGURE 2-29: Shorted Input Histogram:
VREF = 2.5V.
FIGURE 2-30: Offset and Gain Error vs.
Temperature: VREF = 2.5V.
-30 -25 -20 -15 -10 -5 0
Input Amplitude (dBFS)
-105
-100
-95
-90
-85
-80
-75
-70
-65
THD (dB)
70
75
80
85
90
95
100
105
110
SFDR (dB)
THD (dB)
SFDR (dB)
VREF = 5V
-6-5-4-3-2-10123456
Output Code
0
2
4
6
8
Occurrences
10
5
V
REF
= 5V
665631
41102
117
134228
41867
33
165598
-40 -20 0 20 40 60 80 100 120 140
Temperature (
o
C)
-100
0
100
200
300
400
500
600
Offset/Gain Error (uV)
-0.66
0
0.66
1.3
2
2.6
3.3
3.9
Offset/Gain Error (LSB)
Gain Error
Offset Error V
REF
= 5V
-30 -25 -20 -15 -10 -5 0
Input Amplitude (dBFS)
-105
-100
-95
-90
-85
-80
-75
-70
-65
THD (dB)
65
70
75
80
85
90
95
100
105
SFDR (dB)
THD (dB)
SFDR (dB)
VREF = 2.5V
-10-9-8-7-6-5-4-3-2-10123456
Output Code
0
1
2
3
4
5
6
Occurrences
10
5
V
REF
= 2.5V
485575
242712
490
32905
10
125959
63608
83720
13523
73
-40 -20 0 20 40 60 80 100 120 140
Temperature (
o
C)
-300
-200
-100
0
100
200
300
400
Offset/Gain Error (uV)
-3.9
-2.6
-1.3
0
1.3
2.6
3.9
5.2
Offset/Gain Error (LSB)
Offset Error
Gain Error
V
REF
= 2.5V
MCP33131D/MCP33121D/MCP33111D-XX
DS20005947B-page 16 2017 Microchip Technology Inc.
Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33131D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33131D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
FIGURE 2-31: CMRR vs. Input Frequency:
VREF = 5V.
FIGURE 2-32: Power Consumption vs.
Sample Rate: CLOAD_SDO = 20 pF.
FIGURE 2-33: Power Consumption vs.
Temperature: CLOAD_SDO = 20 pF.
FIGURE 2-34: Power Consumption vs.
Temperature during Shutdown.
FIGURE 2-35: Power Consumption vs.
Sample Rate: CLOAD_SDO = 20 pF.
FIGURE 2-36: Power Consumption vs.
Temperature: CLOAD_SDO = 20 pF.
10
-3
10
-2
10
-1
10
0
10
1
10
2
10
3
Input Frequency (kHz)
74
76
78
80
82
84
86
CMRR (dB)
V
REF
= 5V
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Sample Rate (Msps)
0
0.5
1
1.5
2
Current (mA)
Total Power Consumption
I
IO_DATA
(DV
IO
= 3.3V)
IDDAN (AVDD = 1.8V)
IREF (VREF = 5V)
0
2
4
6
8
Total Power (mW)
MCP331x1D-10
-40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature (°C)
0
0.5
1
1.5
2
2.5
Current (mA)
Total Power Consumption
I
IO_DATA
(DV
IO
= 3.3V)
IDDAN (AVDD = 1.8V)
I
REF
(V
REF
= 5V)
0
2
4
6
8
10
Total Power (mW)
MCP331x1D-10
-40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature (°C)
0
2
4
6
8
Current (A)
Total Power Consumption
IIO_STBY (DVIO = 3.3V)
IDDAN_STBY (AVDD = 1.8V)
IREF_STBY (VREF = 5V)
0
4
8
12
16
Total Power (W)
0.1 0.2 0.3 0.4 0.5
Sample Rate (Msps)
0
0.5
1
1.5
2
Current (mA)
Total Power Consumption
IIO_DATA (DVIO = 3.3V)
I
DDAN
(AV
DD
= 1.8V)
IREF (VREF = 5V)
0
2
4
6
8
Total Power (mW)
MCP331x1D-05
-40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature (°C)
0
0.5
1
1.5
2
Current (mA)
Total Power Consumption
IIO_DATA (DVIO = 3.3V)
IDDAN (AVDD = 1.8V)
IREF (VREF = 5V)
0
2
4
6
8
Total Power (mW)
MCP331x1D-05
2017 Microchip Technology Inc. DS20005947B-page 17
MCP33131D/MCP33121D/MCP33111D-XX
3.0 TYPICAL PERFORMANCE CURVES FOR 14-BIT DEVICES (MCP33121D-XX)
Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33121D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33121D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
FIGURE 3-1: INL vs. Output Code.
FIGURE 3-2: DNL vs. Output Code.
FIGURE 3-3: INL vs. Temperature.
FIGURE 3-4: INL vs. Output Code.
FIGURE 3-5: DNL vs. Output Code.
FIGURE 3-6: DNL vs. Temperature.
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
0 4,096 8,192 12,288 16,384
Code
-1
-0.5
0
0.5
1
INL (LSB)
V
REF
= 5V
0 4,096 8,192 12,288 16,384
Code
-1
-0.5
0
0.5
1
DNL (LSB)
V
REF
= 5V
-40 -20 0 20 40 60 80 100 120 140
Temperature (
o
C)
-1
-0.5
0
0.5
1
INL (LSB)
V
REF
= 5V
Max INL (LSB)
Min INL (LSB)
0 4,096 8,192 12,288 16,384
Code
-1
-0.5
0
0.5
1
INL (LSB)
V
REF
= 2.5V
0 4,096 8,192 12,288 16,384
Code
-1
-0.5
0
0.5
1
DNL (LSB)
V
REF
= 2.5V
-40 -20 0 20 40 60 80 100 120 140
Temperature (
o
C)
-1
-0.5
0
0.5
1
DNL (LSB)
VREF = 5V
Max DNL (LSB)
Min DNL (LSB)
MCP33131D/MCP33121D/MCP33111D-XX
DS20005947B-page 18 2017 Microchip Technology Inc.
Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33121D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33121D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
FIGURE 3-7: INL vs. Reference Voltage.
FIGURE 3-8: FFT for 10 kHz Input Signal:
fS = 1 Msps, VIN = -1 dBFS, VREF = 5V.
FIGURE 3-9: FFT for 10 kHz Input Signal:
fS = 500 kSPS, VIN = -1 dBFS, VREF = 5V.
FIGURE 3-10: DNL vs. Reference Voltage.
FIGURE 3-11: FFT for 10 kHz Input Signal:
fS = 1 Msps, VIN = -1 dBFS, VREF = 2.5V.
FIGURE 3-12: FFT for 10 kHz Input Signal:
fS = 500 kSPS, VIN = -1 dBFS, VREF = 2.5V.
2 2.5 3 3.5 4 4.5 5 5.5
Reference Voltage (V)
-1
-0.5
0
0.5
1
INL (LSB)
Max INL (LSB)
Min INL (LSB)
0 100 200 300 400 500
Frequency (kHz)
-160
-140
-120
-100
-80
-60
-40
-20
0
Amplitude (dBFS)
VREF = 5V
fs = 1 Msps
SNR = 85.2 dBFS
SINAD = 85.2 dBFS
SFDR = 106.9 dBc
THD = -100.2 dBc
Offset = 0 LSB
Resolution = 14-bit
MCP33121D-10
0 50 100 150 200 250
Frequency (kHz)
-160
-140
-120
-100
-80
-60
-40
-20
0
Amplitude (dBFS)
VREF = 5V
fs = 0.5 Msps
SNR = 85.1 dBFS
SINAD = 85.1 dBFS
SFDR = 107.9 dBc
THD = -102.1 dBc
Offset = 0 LSB
Resolution = 14-bit
MCP33121D-05
2 2.5 3 3.5 4 4.5 5 5.5
Reference Voltage (V)
-1
-0.5
0
0.5
1
DNL (LSB)
Max DNL (LSB)
Min DNL (LSB)
0 100 200 300 400 500
Frequency (kHz)
-160
-140
-120
-100
-80
-60
-40
-20
0
Amplitude (dBFS)
VREF = 2.5V
fs = 1 Msps
SNR = 83.4 dBFS
SINAD = 83.2 dBFS
SFDR = 96.9 dBc
THD = -95.4 dBc
Offset = -1 LSB
Resolution = 14-bit
MCP33121D-10
0 50 100 150 200 250
Frequency (kHz)
-160
-140
-120
-100
-80
-60
-40
-20
0
Amplitude (dBFS)
VREF = 2.5V
fs = 0.5 Msps
SNR = 83.6 dBFS
SINAD = 83.4 dBFS
SFDR = 97.3 dBc
THD = -95.5 dBc
Offset = -1 LSB
Resolution = 14-bit
MCP33121D-05
2017 Microchip Technology Inc. DS20005947B-page 19
MCP33131D/MCP33121D/MCP33111D-XX
Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33121D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33121D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
FIGURE 3-13: SNR/SINAD/ENOB vs. VREF
FIGURE 3-14: SNR/SINAD vs.
Temperature: VREF = 5V.
FIGURE 3-15: SNR/SINAD vs. Input
Amplitude: FIN = 10 kHz.
FIGURE 3-16: SFDR/THD vs. VREF
FIGURE 3-17: SNR/SINAD vs.
Temperature: VREF = 2.5V.
FIGURE 3-18: SNR/SINAD vs. Input
Amplitude: FIN = 10 kHz.
2 2.5 3 3.5 4 4.5 5 5.5
Reference Voltage (V)
80
81
82
83
84
85
86
SNR/SINAD (dB)
2 2.5 3 3.5 4 4.5 5 5.5
Reference Voltage (V)
11.5
12.5
13.5
14.5
ENOB (Bits)
ENOB
SNR (dB)
SINAD (dB)
-40 -20 0 20 40 60 80 100 120 140
Temperature (oC)
83.6
83.8
84
84.2
84.4
84.6
SNR/SINAD (dB)
SNR (dB)
SINAD (dB)
V
REF
= 5V
-30 -25 -20 -15 -10 -5 0
Input Amplitude (dBFS)
78
80
82
84
86
88
SNR/SINAD (dBFS)
SNR (dBFS)
SINAD(dBFS)
V
REF
= 5V
2 2.5 3 3.5 4 4.5 5 5.5
Reference Voltage (V)
-101
-98
-95
-92
THD (dB)
2 2.5 3 3.5 4 4.5 5 5.5
Reference Voltage (V)
92
97
102
107
SFDR (dB)
THD (dB)
SFDR (dB)
-40 -20 0 20 40 60 80 100 120 140
Temperature (oC)
81
81.5
82
82.5
83
SNR/SINAD (dB)
SNR (dB)
SINAD (dB)
V
REF
= 2.5V
-30 -25 -20 -15 -10 -5 0
Input Amplitude (dBFS)
78
80
82
84
86
88
SNR/SINAD (dBFS)
SNR (dBFS)
SINAD(dBFS)
V
REF
= 2.5V
MCP33131D/MCP33121D/MCP33111D-XX
DS20005947B-page 20 2017 Microchip Technology Inc.
Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33121D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33121D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
FIGURE 3-19: SNR/SINAD vs.Input
Frequency: VIN = -1 dBFS.
FIGURE 3-20: THD/SFDR vs.
Temperature: VREF = 5V.
FIGURE 3-21: THD/SFDR vs. Input
Frequency: VREF = 5V.
FIGURE 3-22: SNR/SINAD vs.Input
Frequency: VIN = -1 dBFS.
FIGURE 3-23: THD/SFDR vs.
Temperature: VREF = 2.5V.
FIGURE 3-24: THD/SFDR vs. Input
Frequency: VREF = 2.5V.
10
0
10
1
10
2
10
3
Input Frequency (kHz)
65
70
75
80
85
90
SNR/SINAD (dB)
SNR (dB)
SINAD (dB)
V
REF
= 5V
-40 -20 0 20 40 60 80 100 120 140
Temperature (oC)
-102
-100
-98
-96
-94
-92
THD (dB)
96
98
100
102
104
106
SFDR (dB)
SFDR (dB)
THD (dB)
V
REF
= 5V
100101102103
Input Frequency (kHz)
-110
-105
-100
-95
-90
-85
-80
-75
THD (dB)
75
80
85
90
95
100
105
110
SFDR (dB)
THD (dB)
SFDR (dB)
VREF = 5V
10
0
10
1
10
2
10
3
Input Frequency (kHz)
65
70
75
80
85
90
SNR/SINAD (dB)
SNR (dB)
SINAD (dB)
V
REF
= 2.5V
Temperature (oC)
-40 -20 0 20 40 60 80 100 120 140
Temperature (
o
C)
-98
-96
-94
-92
THD (dB)
THD (dB)
SFDR (dB)
94
96
98
100
SFDR (dB)
V
REF
= 2.5V
100101102103
Input Frequency (kHz)
-110
-105
-100
-95
-90
-85
-80
-75
THD (dB)
75
80
85
90
95
100
105
110
SFDR (dB)
THD (dB)
SFDR (dB)
VREF = 2.5V
2017 Microchip Technology Inc. DS20005947B-page 21
MCP33131D/MCP33121D/MCP33111D-XX
Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33121D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33121D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
FIGURE 3-25: THD/SFDR vs. Input
Amplitude: VREF = 5V.
FIGURE 3-26: Shorted Input Histogram:
VREF = 5V.
FIGURE 3-27: Offset and Gain Error vs.
Temperature: VREF = 5V.
FIGURE 3-28: THD/SFDR vs. Input
Amplitude: VREF = 2.5V.
FIGURE 3-29: Shorted Input Histogram:
VREF = 2.5V.
FIGURE 3-30: Offset and Gain Error vs.
Temperature: VREF = 2.5V.
-30 -25 -20 -15 -10 -5 0
Input Amplitude (dBFS)
-105
-100
-95
-90
-85
-80
-75
-70
-65
THD (dB)
70
75
80
85
90
95
100
105
110
SFDR (dB)
THD (dB)
SFDR (dB)
VREF = 5V
-3-2-10123
Output Code
0
2
4
6
8
10
Occurrences
105
VREF = 5V
872448
176128
-40 -20 0 20 40 60 80 100 120 140
Temperature (
o
C)
-200
-100
0
100
200
300
400
500
Offset/Gain Error (uV)
-0.33
-0.16
0
0.16
0.33
0.49
0.66
0.82
Offset/Gain Error (LSB)
Gain Error
Offset Error V
REF
= 5V
-30 -25 -20 -15 -10 -5 0
Input Amplitude (dBFS)
-105
-100
-95
-90
-85
-80
-75
-70
-65
THD (dB)
65
70
75
80
85
90
95
100
105
SFDR (dB)
THD (dB)
SFDR (dB)
VREF = 2.5V
-4-3-2-10123
Output Code
0
2
4
6
8
10
Occurrences
105
VREF = 2.5V
844912
203163
501
-40 -20 0 20 40 60 80 100 120 140
Temperature (
o
C)
-400
-300
-200
-100
0
100
200
300
Offset/Gain Error (uV)
-1.3
-0.98
-0.66
-0.33
0
0.33
0.66
0.98
Offset/Gain Error (LSB)
Gain Error
Offset Error V
REF
= 2.5V
MCP33131D/MCP33121D/MCP33111D-XX
DS20005947B-page 22 2017 Microchip Technology Inc.
Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33121D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33121D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
FIGURE 3-31: CMRR vs. Input Frequency:
VREF = 5V.
FIGURE 3-32: Power Consumption vs.
Sample Rate: CLOAD_SDO = 20 pF.
FIGURE 3-33: Power Consumption vs.
Temperature: CLOAD_SDO = 20 pF.
FIGURE 3-34: Power Consumption vs.
Temperature during Shutdown.
FIGURE 3-35: Power Consumption vs.
Sample Rate: CLOAD_SDO = 20 pF.
FIGURE 3-36: Power Consumption vs.
10-3 10-2 10-1 100101102103
Input Frequency (kHz)
74
76
78
80
82
84
86
CMRR (dB)
V
REF
= 5V
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Sample Rate (Msps)
0
0.5
1
1.5
2
Current (mA)
Total Power Consumption
I
IO_DATA
(DV
IO
= 3.3V)
IDDAN (AVDD = 1.8V)
IREF (VREF = 5V)
0
2
4
6
8
Total Power (mW)
MCP331x1D-10
-40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature (°C)
0
0.5
1
1.5
2
2.5
Current (mA)
Total Power Consumption
I
IO_DATA
(DV
IO
= 3.3V)
IDDAN (AVDD = 1.8V)
I
REF
(V
REF
= 5V)
0
2
4
6
8
10
Total Power (mW)
MCP331x1D-10
-40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature (°C)
0
2
4
6
8
Current (A)
Total Power Consumption
IIO_STBY (DVIO = 3.3V)
IDDAN_STBY (AVDD = 1.8V)
IREF_STBY (VREF = 5V)
0
4
8
12
16
Total Power (W)
0.1 0.2 0.3 0.4 0.5
Sample Rate (Msps)
0
0.5
1
1.5
2
Current (mA)
Total Power Consumption
I
IO_DATA
(DV
IO
= 3.3V)
I
DDAN
(AV
DD
= 1.8V)
I
REF
(V
REF
= 5V)
0
2
4
6
8
Total Power (mW)
MCP331x1D-05
-40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature (°C)
0
0.5
1
1.5
2
Current (mA)
Total Power Consumption
IIO_DATA (DVIO = 3.3V)
IDDAN (AVDD = 1.8V)
IREF (VREF = 5V)
0
2
4
6
8
Total Power (mW)
MCP331x1D-05
2017 Microchip Technology Inc. DS20005947B-page 23
MCP33131D/MCP33121D/MCP33111D-XX
4.0 TYPICAL PERFORMANCE CURVES FOR 12-BIT DEVICES (MCP33111D-XX)
Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33111D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33111D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
FIGURE 4-1: INL vs. Output Code.
FIGURE 4-2: DNL vs. Output Code.
FIGURE 4-3: INL vs. Temperature.
FIGURE 4-4: INL vs. Output Code.
FIGURE 4-5: DNL vs. Output Code.
FIGURE 4-6: DNL vs. Temperature.
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
0 1,024 2,048 3,072 4,096
Code
-0.5
-0.3
-0.1
0.1
0.3
0.5
INL (LSB)
V
REF
= 5V
0 1,024 2,048 3,072 4,096
Code
-0.5
-0.3
-0.1
0.1
0.3
0.5
DNL (LSB)
V
REF
= 2.5V
-40 -20 0 20 40 60 80 100 120 140
Temperature (oC)
-0.2
-0.15
-0.1
-0.05
0
0.05
0.1
0.15
0.2
INL (LSB)
V
REF
= 5V
Max INL (LSB)
Min INL (LSB)
0 1,024 2,048 3,072 4,096
Code
-0.5
-0.3
-0.1
0.1
0.3
0.5
INL (LSB)
V
REF
= 2.5V
0 1,024 2,048 3,072 4,096
Code
-0.5
-0.3
-0.1
0.1
0.3
0.5
DNL (LSB)
V
REF
= 5V
-40 -20 0 20 40 60 80 100 120 140
Temperature (oC)
-0.2
-0.15
-0.1
-0.05
0
0.05
0.1
0.15
0.2
DNL (LSB)
V
REF
= 5V
Max DNL (LSB)
Min DNL (LSB)
MCP33131D/MCP33121D/MCP33111D-XX
DS20005947B-page 24 2017 Microchip Technology Inc.
Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33111D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33111D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
FIGURE 4-7: INL vs. Reference Voltage.
FIGURE 4-8: FFT for 10 kHz Input Signal:
fS = 1 Msps, VIN = -1 dBFS, VREF = 5V.
FIGURE 4-9: FFT for 10 kHz Input Signal:
fS = 500 kSPS, VIN = -1 dBFS, VREF = 5V.
FIGURE 4-10: DNL vs. Reference Voltage.
FIGURE 4-11: FFT for 10 kHz Input Signal:
fS = 1 Msps, VIN = -1 dBFS, VREF = 2.5V.
FIGURE 4-12: FFT for 10 kHz Input Signal:
fS = 500 kSPS, VIN = -1 dBFS, VREF = 2.5V.
2 2.5 3 3.5 4 4.5 5 5.5
Reference Voltage (V)
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
INL (LSB)
Min INL (LSB)
Max INL (LSB)
0 100 200 300 400 500
Frequency (kHz)
-120
-100
-80
-60
-40
-20
0
Amplitude (dBFS)
fs = 1 Msps
SNR = 73.9 dBFS
SINAD = 73.9 dBFS
SFDR = 99.8 dBc
THD = -96.5 dBc
Offset = 0 LSB
Resolution = 12-bit
VREF = 5V
MCP33111D-10
0 50 100 150 200 250
Frequency (kHz)
-120
-100
-80
-60
-40
-20
0
Amplitude (dBFS)
fs = 0.5 Msps
SNR = 74.0 dBFS
SINAD = 73.9 dBFS
SFDR = 99.5 dBc
THD = -95.1 dBc
Offset = 0 LSB
Resolution = 12-bit
VREF = 5V
MCP33111D-05
2 2.5 3 3.5 4 4.5 5 5.5
Reference Voltage (V)
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
DNL (LSB)
Min DNL (LSB)
Max DNL (LSB)
0 100 200 300 400 500
Frequency (kHz)
-120
-100
-80
-60
-40
-20
0
Amplitude (dBFS)
fs = 1 Msps
SNR = 73.8 dBFS
SINAD = 73.7 dBFS
SFDR = 97.0 dBc
THD = -95.6 dBc
Offset = -1 LSB
Resolution = 12-bit
VREF = 2.5V
MCP33111D-10
0 50 100 150 200 250
Frequency (kHz)
-120
-100
-80
-60
-40
-20
0
Amplitude (dBFS)
fs = 0.5 Msps
SNR = 73.8 dBFS
SINAD = 73.8 dBFS
SFDR = 96.2 dBc
THD = -94.3 dBc
Offset = -1 LSB
Resolution = 12-bit
VREF = 2.5V
MCP33111D-05
2017 Microchip Technology Inc. DS20005947B-page 25
MCP33131D/MCP33121D/MCP33111D-XX
Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33111D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33111D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
FIGURE 4-13: SNR/SINAD/ENOB vs. VREF
FIGURE 4-14: SNR/SINAD vs.
Temperature: VREF = 5V.
FIGURE 4-15: SNR/SINAD vs. Input
Amplitude: FIN = 10 kHz.
FIGURE 4-16: SFDR/THD vs. VREF
FIGURE 4-17: SNR/SINAD vs.
Temperature: VREF = 2.5V.
FIGURE 4-18: SNR/SINAD vs. Input
Amplitude: FIN = 10 kHz.
2 2.5 3 3.5 4 4.5 5 5.5
Reference Voltage (V)
72.6
72.8
73
73.2
SNR/SINAD (dB)
2 2.5 3 3.5 4 4.5 5 5.5
Reference Voltage (V)
10
11
12
13
ENOB (Bits)
ENOB
SNR (dB)
SINAD (dB)
-40 -20 0 20 40 60 80 100 120 140
Temperature (oC)
72.92
72.93
72.94
72.95
72.96
72.97
72.98
SNR/SINAD (dB)
SNR (dB)
SINAD (dB)
VREF = 5V
-30 -25 -20 -15 -10 -5 0
Input Amplitude (dBFS)
70
71
72
73
74
75
SNR/SINAD (dBFS)
SNR (dBFS)
SINAD(dBFS)
V
REF
= 5V
2 2.5 3 3.5 4 4.5 5 5.5
Reference Voltage (V)
-100
-97
-94
-91
THD (dB)
2 2.5 3 3.5 4 4.5 5 5.5
Reference Voltage (V)
90
95
100
105
SFDR (dB)
THD (dB)
SFDR (dB)
-40 -20 0 20 40 60 80 100 120 140
Temperature (oC)
72.65
72.7
72.75
72.8
72.85
72.9
SNR/SINAD (dB)
SNR (dB)
SINAD (dB)
VREF = 2.5V
-30 -25 -20 -15 -10 -5 0
Input Amplitude (dBFS)
70
71
72
73
74
75
SNR/SINAD (dBFS)
SNR (dBFS)
SINAD(dBFS)
V
REF
= 2.5V
MCP33131D/MCP33121D/MCP33111D-XX
DS20005947B-page 26 2017 Microchip Technology Inc.
Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33111D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33111D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
FIGURE 4-19: SNR/SINAD vs. Input
Frequency: VIN = -1 dBFS
FIGURE 4-20: THD/SFDR vs.
Temperature: VREF = 5V.
FIGURE 4-21: THD/SFDR vs. Input
Frequency: VREF = 5V.
FIGURE 4-22: SNR/SINAD vs. Input
Frequency: VIN = -1 dBFS.
FIGURE 4-23: THD/SFDR vs.
Temperature: VREF = 2.5V.
FIGURE 4-24: THD/SFDR vs. Input
Frequency: VREF = 2.5V.
10
0
10
1
10
2
10
3
Input Frequency (kHz)
60
65
70
75
80
SNR/SINAD (dB)
SNR (dB)
SINAD (dB)
VREF = 5V
-40 -20 0 20 40 60 80 100 120 140
Temperature (oC)
-98
-97
-96
-95
-94
-93
-92
THD (dB)
94
96
98
100
102
SFDR (dB)
THD (dB)
SFDR (dB)
V
REF
= 5V
100101102103
Input Frequency (kHz)
-110
-105
-100
-95
-90
-85
-80
-75
THD (dB)
75
80
85
90
95
100
105
110
SFDR (dB)
THD (dB)
SFDR (dB)
VREF = 5V
10
0
10
1
10
2
10
3
Input Frequency (kHz)
60
65
70
75
80
SNR/SINAD (dB)
SNR (dB)
SINAD (dB)
VREF = 2.5V
-40 -20 0 20 40 60 80 100 120 140
Temperature (oC)
-96
-95
-94
-93
-92
-91
THD (dB)
THD (dB)
SFDR (dB)
94
95
96
97
98
99
SFDR (dB)
VREF = 2.5V
100101102103
Input Frequency (kHz)
-110
-105
-100
-95
-90
-85
-80
-75
THD (dB)
75
80
85
90
95
100
105
110
SFDR (dB)
THD (dB)
SFDR (dB)
V
REF
= 2.5V
2017 Microchip Technology Inc. DS20005947B-page 27
MCP33131D/MCP33121D/MCP33111D-XX
Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33111D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33111D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
FIGURE 4-25: THD/SFDR vs. Input
Amplitude: VREF = 5V.
FIGURE 4-26: Shorted Input Histogram:
VREF = 5V.
FIGURE 4-27: Offset and Gain Error vs.
Temperature: VREF = 5V.
FIGURE 4-28: THD/SFDR vs. Input
Amplitude: VREF = 2.5V.
FIGURE 4-29: Shorted Input Histogram:
VREF = 2.5V.
FIGURE 4-30: Offset and Gain Error vs.
Temperature: VREF = 2.5V.
-30 -25 -20 -15 -10 -5 0
Input Amplitude (dBFS)
-105
-100
-95
-90
-85
-80
-75
-70
-65
-60
THD (dB)
60
65
70
75
80
85
90
95
100
105
SFDR (dB)
THD (dB)
SFDR (dB)
VREF = 5V
-3-2-10123
Output Code
0
2
4
6
8
10
Occurrences
10
5
872448
176128
V
REF
= 5V
-40 -20 0 20 40 60 80 100 120 140
Temperature (
o
C)
-1000
-800
-600
-400
-200
0
200
400
Offset/Gain Error (uV)
-0.41
-0.33
-0.25
-0.16
-0.082
0
0.082
0.16
Offset/Gain Error (LSB)
Offset Error
Gain Error
V
REF
= 5V
-30 -25 -20 -15 -10 -5 0
Input Amplitude (dBFS)
-105
-100
-95
-90
-85
-80
-75
-70
-65
-60
THD (dB)
60
65
70
75
80
85
90
95
100
105
SFDR (dB)
THD (dB)
SFDR (dB)
VREF = 2.5V
-3 -2 -1 0 1 2
Output Code
0
2
4
6
8
10
Occurrences
10
5
VREF = 2.5V
845413
203163
-40 -20 0 20 40 60 80 100 120 140
Temperature (
o
C)
-800
-600
-400
-200
0
Offset/Gain Error (uV)
-0.66
-0.49
-0.33
-0.16
0
Offset/Gain Error (LSB)
Gain Error
Offset Error
V
REF
= 2.5V
MCP33131D/MCP33121D/MCP33111D-XX
DS20005947B-page 28 2017 Microchip Technology Inc.
Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33111D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33111D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
FIGURE 4-31: CMRR vs. Input Frequency:
VREF = 5V.
FIGURE 4-32: Power Consumption vs.
Sample Rate: CLOAD_SDO = 20 pF.
FIGURE 4-33: Power Consumption vs.
Temperature: CLOAD_SDO = 20 pF.
FIGURE 4-34: Power Consumption vs.
Temperature during Shutdown.
FIGURE 4-35: Power Consumption vs.
Sample Rate: CLOAD_SDO = 20 pF.
MCP331x1D-10
FIGURE 4-36: Power Consumption vs.
Temperature: CLOAD_SDO = 20 pF.
10
-3
10
-2
10
-1
10
0
10
1
10
2
10
3
Input Frequency (kHz)
74
76
78
80
82
84
86
CMRR (dB)
V
REF
= 5V
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Sample Rate (Msps)
0
0.5
1
1.5
2
Current (mA)
Total Power Consumption
I
IO_DATA
(DV
IO
= 3.3V)
IDDAN (AVDD = 1.8V)
IREF (VREF = 5V)
0
2
4
6
8
Total Power (mW)
MCP331x1D-10
-40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature (°C)
0
0.5
1
1.5
2
2.5
Current (mA)
Total Power Consumption
I
IO_DATA
(DV
IO
= 3.3V)
IDDAN (AVDD = 1.8V)
I
REF
(V
REF
= 5V)
0
2
4
6
8
10
Total Power (mW)
MCP331x1D-10
-40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature (°C)
0
2
4
6
8
Current (A)
Total Power Consumption
IIO_STBY (DVIO = 3.3V)
IDDAN_STBY (AVDD = 1.8V)
IREF_STBY (VREF = 5V)
0
4
8
12
16
Total Power (W)
0.1 0.2 0.3 0.4 0.5
Sample Rate (Msps)
0
0.5
1
1.5
2
Current (mA)
Total Power Consumption
I
IO_DATA
(DV
IO
= 3.3V)
I
DDAN
(AV
DD
= 1.8V)
I
REF
(V
REF
= 5V)
0
2
4
6
8
Total Power (mW)
MCP331x1D-05
-40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature (°C)
0
0.5
1
1.5
2
Current (mA)
Total Power Consumption
IIO_DATA (DVIO = 3.3V)
IDDAN (AVDD = 1.8V)
IREF (VREF = 5V)
0
2
4
6
8
Total Power (mW)
MCP331x1D-05
2018 Microchip Technology Inc. DS20005947B-page 29
MCP33131D/MCP33121D/MCP33111D-XX
5.0 PIN FUNCTION DESCRIPTIONS
TABLE 5-1: PIN FUNCTION TABLE
5.1 Supply Voltages and Reference
Voltage
The device has two power supply pins:
a) Analog power supply (AVDD): 1.8V
b) Digital input/output interface power supply
(DVIO): 1.7V to 5.5V.
The large supply voltage range of DVIO allows the
device to interface with various host devices that are
operating with different supply voltages. See Table 1-2
for timing specifications for I/O interface signal param-
eters depending on DVIO voltage.
5.2 Reference Voltage (VREF)
The device requires a single-ended external reference
voltage (VREF). The external input reference range is
from 2.5V to 5.1V. This reference voltage sets the
input full-scale range from 0V to VREF. See Figure 6-2
to Figure 6-8 for example application circuits and
reference voltage settings.
5.2.1 VOLTAGE REFERENCE
SELECTION
The performance of the voltage reference has a large
impact on the accuracy of high-precision data
acquisition systems. The voltage reference should
have high-accuracy, low-noise, and low-temperature
drift. A ±0.1% output accuracy of the reference directly
corresponds to ±0.1% absolute accuracy of the ADC
output. The RMS output noise voltage of the reference
should be less than 1/2 LSB of the ADC.
Pin Number Pin Name Function
1
VREF Reference voltage input (2.5V - 5.1V).
This pin should be decoupled with a 10 F tantalum capacitor.
2AV
DD DC supply voltage input for analog section (1.8V).
This pin should be decoupled with a 1 F ceramic capacitor.
3A
IN+ Differential positive analog input.
4A
IN- Differential negative analog input.
5 GND Power supply ground reference. This pin is a common ground for both the analog
power supply (AVDD) and digital I/O supply (DVIO).
6 CNVST Conversion-start control and active-low SPI chip-select digital input.
A new conversion is started on the rising edge of CNVST.
When the conversion is complete, output data is available at SDO by lowering CNVST.
7 SDO SPI-compatible serial digital data output: ADC conversion data is shifted out by SCLK
clock, with MSB first.
8 SCLK SPI-compatible serial data clock digital input.
The ADC output is synchronously shifted out by this clock.
9 SDI SPI-compatible serial data digital input. Tie to DVIO for normal operation.
10 DVIO DC supply voltage for digital input/output interface (1.7V - 5.5V).
This pin should be decoupled with a 0.1 F ceramic capacitor.
Note: Proper decoupling capacitors (1 F to
AVDD, 0.1 F to DVIO) should be mounted
as close as possible to the respective
pins.
Note: The reference pin needs a tantalum
decoupling capacitor (10 F, 10V rating).
Additional multiple ceramic capacitors can
be added in parallel to decouple
high-frequency noises.
Note: During the initial power-up sequence, the
reference voltage (VREF) must be
provided prior to supplying AVDD or within
about 64 ms after supplying AVDD.
Otherwise, it is strongly recommended to
send a recalibrate command. See
Section 7.1 “Recalibrate Command” for
more details.
y
DS20005947B-page 30 2018 Microchip Technology Inc.
MCP33131D/MCP33121D/MCP33111D-XX
6.0 DEVICE OVERVIEW
When the MCP33131D/MCP33121D/MCP33111D-XX
is first powered-up, it performs a self-calibration and
enters a low current input acquisition mode (Standby)
by itself.
The external reference voltage (VREF) ranging from
2.5V to 5.1V sets the differential input full-scale range
(FSR) from -VREF to +VREF
.
The differential input signal needs an appropriate input
common-mode voltage from 0V to VREF
, depending on
the input signal condition. VREF/2 is typically used for a
symmetric differential input.
During input acquisition (Standby), the internal input
sampling capacitors are connected to the input signal,
while most of the internal analog circuits are shutdown
to save power. During this input acquisition time
(tACQ), the device consumes less than 1 A.
The user can operate the device with an easy-to-use
SPI-compatible 3-wire interface.
The device initiates data conversion on the rising edge
of the conversion-start control (CNVST). The data con-
version time (tCNV) is set by the internal clock. Once
the conversion is complete and the host lowers
CNVST, the output data is available on SDO and the
device starts the next input acquisition by itself. During
this input acquisition time (tACQ), the user can clock
out the output data by providing the SPI-compatible
serial clock (SCLK).
The device provides conversion data with no missing
codes. This ADC device family has a large input
full-scale range, high precision, high throughput with
no output latency, and is an ideal choice for various
ADC applications.
6.1 Analog Inputs
Figure 6-1 shows a simplified equivalent circuit of the
differential input architecture with a switched capacitor
input stage. The input sampling capacitors
(CS+and CS-) are about 31 pF each. The back-to-back
diodes (D1 - D2) at each input are ESD protection
diodes. Note that these ESD diodes are tied to VREF
, so
that each input signal can swing from 0V to +VREF and
from -VREF to +VREF differentially.
During input acquisition (Standby), the sampling
switches are closed and each input sees the sampling
capacitor (≈ 31 pF) in series with the on-resistance of
the sampling switch, RSON (≈ 200).
For high-precision data conversion applications, the
input voltage needs to be fully settled within 1/2 LSB
during the input acquisition period (tACQ). The settling
time is directly related to the source impedance: A
lower impedance source results in faster input settling
time. Although the device can be driven directly with a
low impedance source, using a low noise input driver is
highly recommended.
FIGURE 6-1: Simplified Equivalent
Analog Input Circuit.
6.1.1 ABSOLUTE MAXIMUM INPUT
VOLTAGE RANGE
The input voltage at each input pin (AIN+ and AIN-)
must meet the following absolute maximum input
voltage limits:
•(V
IN+, VIN-) < VREF + 0.1V
•(V
IN+, VIN-) > GND - 0.1V
Note: The ESD diodes at the analog input pins
are biased from VREF
. Any input voltage
outside the absolute maximum range can
turn on the input ESD protection diodes
and results in input leakage current which
may cause conversion errors and
permanent damage to the device. Care
must be taken in setting the input voltage
ranges so that the input voltage does not
exceed the absolute maximum input
voltage range.
VT = 0.6V
D2
D1
V
REF
Sample V
IN
+
ILEAKAGE
(~ ±1 nA)
AIN+
MCP331x1D-XX
RSON
C
PIN
RSON
= On-resistance of the sampling switch ≈ 200 
CPIN = Package pin + ESD capacitor ≈ 2 pF.
where:
V
REF
CS+, CS-
= Input sample and hold capacitor ≈ 31 pF.
VT = 0.6V
D2
D1
ILEAKAGE
(~ ±1 nA)
AIN-
C
PIN
(200 )
Sample V
IN
-
RSON
SW1
+
SW2
+
SW1
-
SW2
-
C
S+
(31 pF)
(200 )
(31 pF)
C
S-
2018 Microchip Technology Inc. DS20005947B-page 31
MCP33131D/MCP33121D/MCP33111D-XX
6.1.2 INPUT VOLTAGE RANGE
The differential input (VIN) and common-mode voltage
(VCM) at the input pins are defined by:
EQUATION 6-1: DIFFERENTIAL INPUT
where VIN+ is the input at the AIN+ pin and VIN- is the
input at AIN- pin. The input signal swings around an
input common-mode voltage (VCM), typically centered
at VREF/2 for the best performance.
The absolute value of the differential input (VIN) needs
to be less than the reference voltage. The device will
output saturated output codes (all 0s or all 1s except
sign bit) if the absolute value of the input (VIN) is greater
than the reference voltage.
The differential input full-scale voltage range (FSR) is
given by the external reference voltage (VREF) setting:
EQUATION 6-2: FSR AND INPUT RANGE
6.2 Analog Input Conditioning
Circuits
The MCP33131D/MCP33121D/MCP33111D-XX
supports various input types, such as: (a)
fully-differential inputs, (b) arbitrary waveform inputs
and (c) single-ended inputs.
6.2.1 FULLY-DIFFERENTIAL INPUT
SIGNALS
The MCP33131D/MCP33121D/MCP33111D-XX
provides the best linearity performance with
fully-differential inputs. Figure 6-2 shows an example
of a fully-differential input conditioning circuit with a
differential input driver followed by an RC anti-aliasing
filter. Figure 6-3 shows its transfer function.
The differential input (VIN) between the two differential
ADC analog input pins (AIN+, AIN-) swings from -VREF
to +VREF centered at the input common-mode voltage
(VOCM).
The front-end differential driver provides a low output
impedance, which provides fast settling of the analog
inputs during the acquisition phase and provides
isolation between the signal source and the ADC. The
RC low-pass anti-aliasing filter band-limits the output
noise of the input driver and attenuates the kick-back
noise spikes from the ADC during conversion.
Figure 6-2 is the reference circuit that is used to collect
most of the linearity performance data shown in
Table 1-1.
The differential input driver shown in Figure 6-2 can be
replaced with a low noise dual-channel op-amp. See
Section 6.3 “ADC Input Driver Selection” for the
driver selection.
6.2.2 ARBITRARY WAVEFORM INPUT
SIGNALS
The MCP33131D/MCP33121D/MCP33111D-XX can
convert input signals with arbitrary waveforms at the
inputs AIN+ and AIN-. These inputs can be symmetric,
non-symmetric or independent with respect to each
other.
In the arbitrary input configuration, each ADC analog
input is connected to a single ended source ranging
from 0V to VREF
. In this case, the ADC converts the
voltage difference between the two input signals.
Figure 6-4 shows the configuration example for the
arbitrary input signals.
6.2.3 SINGLE-ENDED INPUT SIGNALS
Although the
MCP33131D/MCP33121D/MCP33111D-XX
is a fully-differential input device, it can also convert
single-ended input signals. The most commonly
recommended single-ended configurations are:
(a) pseudo-differential bipolar configuration and
(b) pseudo-differential unipolar configuration.
6.2.3.1 Pseudo-Differential Bipolar
Configuration
In the pseudo-differential bipolar configuration, one of
the ADC analog inputs (typically AIN-) is driven with a
fixed DC voltage (typically VREF/2), while the other
(AIN+) is connected to a single-ended signal in the
range 0V to VREF
.
In this case, the ADC converts the voltage difference
between the single-ended signal and the DC voltage.
Figure 6-5 shows the configuration example and
Figure 6-6 shows its transfer function.
6.2.3.2 Pseudo-Differential Unipolar
Configuration
In the pseudo-differential unipolar input configuration,
one of the ADC analog inputs (typically AIN-) is
connected to ground, while the other (AIN+) is
connected to a single ended signal in the range 0V to
VREF
.
In this case, the ADC converts the voltage difference
between the single ended signal and ground.
Figure 6-7 shows the configuration example and
Figure 6-8 shows its transfer function.
VIN VIN+VIN-–=
VCM
VIN+VIN-+
2
-----------------------------=
VREF
–VIN VREF 1LSB–
2VREF
=
Input Full-Scale Range (FSR)
Input Range:
-
DS20005947B-page 32 2018 Microchip Technology Inc.
MCP33131D/MCP33121D/MCP33111D-XX
FIGURE 6-2: Input Conditional Circuit for Fully-Differential Input.
FIGURE 6-3: Transfer Function for Figure 6-2.
AIN+
+
-
R1
C1
10 F
(22

±0.1%
)
(1.7nF, NPO)
RG1
VREF/2
Input Driver
2R1C1
1
fC =
Reference
Voltage
VOCM
CR
Differential Inputs
AIN-
VREF AVDD DVIO
SDI
SCLK
SDO
CNVST
1.8V 1.8V to 5.5V
GND
(1.7nF, NPO)
(22

±0.1%
)
VREF
(PIC32MZ)
Host Device
Note 1: Contact Microchip Technology Inc. for availability of the differential input driver amplifiers.
(Note 1)
(Note 2)
2: Contact Microchip Technology Inc. for the MCP1501 voltage reference application circuit.
0V
V
REF
0V
V
REF
VREF/2
VREF/2
RG2
RF1
RF2
VDC
0V
V
REF
0V
V
REF
R1
C1
MCP331x1D-XX
Differential Input Voltage
+VREF - 1 LSB
Digital Output Code (Two’s Complement)
-VREF
0
VIN
Available VIN range
2n/2 - 1
- 2n/2
2018 Microchip Technology Inc. DS20005947B-page 33
MCP33131D/MCP33121D/MCP33111D-XX
FIGURE 6-4: Input Configuration for Arbitrary Waveform Input Signals.
FIGURE 6-5: Pseudo-Differential Bipolar-Input Configuration for Single-Ended Input Signal.
FIGURE 6-6: Transfer Function for Figure 6-5.
Low Noise Input Buffer
Note 1: Contact Microchip Technology Inc. for availability of the low-noise input driver amplifiers.
(Note 1)
2: Contact Microchip Technology Inc. for the MCP1501 voltage reference application circuit.
0V
V
REF
V
REF
0V
AIN+
R1
C1
10 F
2R1C1
1
fC =
Reference
Voltage
CR
AIN-
VREF AVDD DVIO
SDI
SCLK
SDO
CNVST
1.8V 1.8V to 5.5V
GND
VREF
(PIC32MZ)
Host Device
(Note 2)
VDC
R1
C1
Arbitrary Waveform Differential Inputs
MCP331x1D-XX
Low Noise Input Buffer
Note 1: Contact Microchip Technology Inc. for availability of the low-noise input driver amplifiers.
(Note 1)
2: Contact Microchip Technology Inc. for the MCP1501 voltage reference application circuit.
AIN+
R1
C1
10 F
Reference
Voltage
CR
AIN-
VREF AVDD DVIO
SDI
SCLK
SDO
CNVST
1.8V 1.8V to 5.5V
GND
VREF
(PIC32MZ)
Host Device
(Note 2)
VDC
VREF/2
Single-Ended Input
0V
V
REF
VREF/2
1 F
VREF/2
(22

±0.1%
)
(1.7nF, NPO)
0V
V
REF
VREF/2
R1
C1
(22

±0.1%
)
(1.7nF, NPO)
2R1C1
1
fC =
MCP331x1D-XX
Analog Input Voltage
+VREF - 1 LSB
Digital Output Code (Two’s Complement)
-VREF
- 2n/2
0
VIN
+VREF/2
2n/4
- 2n/4
-VREF/2
Available VIN range
2n/2 - 1
DS20005947B-page 34 2018 Microchip Technology Inc.
MCP33131D/MCP33121D/MCP33111D-XX
FIGURE 6-7: Pseudo-Differential Unipolar-Input Configuration for Single-Ended Input Signal.
FIGURE 6-8: Transfer Function for Figure 6-7.
Low Noise Input Buffer
Note 1: Contact Microchip Technology Inc. for availability of the low-noise input driver amplifiers.
(Note 1)
2: Contact Microchip Technology Inc. for the MCP1501 voltage reference application circuit.
AIN+
R1
C1
10 F
Reference
Voltage
CR
AIN-
VREF AVDD DVIO
SDI
SCLK
SDO
CNVST
1.8V 1.8V to 5.5V
GND
VREF
(PIC32MZ)
Host Device
(Note 2)
VDC
Single-Ended Input
(22

±0.1%
)
(1.7nF, NPO)
(22

±0.1%
)
R1
0V
V
REF
VREF/2
0V
V
REF
VREF/2
C1
(1.7nF, NPO)
MCP331x1D-XX
Analog Input Voltage
+VREF
Digital Output Code (Two’s Complement)
-VREF
0
VIN
+VREF/2
2n/4
-VREF/2
- 2n/4
- 2n/2
Available VIN range
2n/2 - 1
2018 Microchip Technology Inc. DS20005947B-page 35
MCP33131D/MCP33121D/MCP33111D-XX
6.3 ADC Input Driver Selection
The noise and distortion of the ADC input driver can
degrade the dynamic performance (SNR, SFDR, and
THD) of the overall ADC application system. Therefore,
the ADC input driver needs better performance
specifications than the ADC itself. The data sheet of the
driver typically shows the output noise voltage and
harmonic distortion parameters.
Figure 6-9 shows a simplified system noise
presentation block diagram for the front-end driver and
ADC.
FIGURE 6-9: Simplified System Noise
Representation.
• Unity-Gain Bandwidth:
An input driver with higher bandwidth usually results in
better overall linearity performance. Typically, the driver
should have the unity-gain bandwidth greater than 5
times the -3 dB cutoff frequency of the anti-aliasing
filter:
EQUATION 6-3: BANDWIDTH
REQUIREMENT FOR ADC
INPUT DRIVER
where, fB = -3 dB bandwidth of RC anti-aliasing filter as
shown in Figure 6-9.
•Distortion:
The nonlinearity characteristics of the input driver
cause distortions in the ADC output. Therefore, the
input driver should have less distortion than the ADC
itself. The recommended total harmonic distortion
(THD) of the driver is at least 10 dB less than that of the
ADC:
EQUATION 6-4: RECOMMENDED THD
FOR ADC INPUT DRIVER
• ADC Input-Referred Noise:
When the ADC is operating with a full-scale input
range, the ADC input-referred RMS noise is
approximated as shown in Equation 6-5.
EQUATION 6-5: ADC INPUT-REFERRED
NOISE
where FSR is the input full-scale range of ADC.
•Noise Contribution from the Front-End Driver:
The noise from the input driver can degrade the ADC’s
SNR performance. Therefore, the selected input driver
should have the lowest possible broadband noise
density and 1/f noise. When an anti-aliasing filter is
used after the input driver, the output noise density of
the input driver is integrated over the -3 dB bandwidth
of the filter.
Equation 6-6 shows the RMS output noise voltage
calculation using the RC filter’s bandwidth and noise
density (eN) of the input driver. GN in Equation 6-6 is
the noise gain of the driver amplifier and becomes 1 for
a unity gain buffer driver.
EQUATION 6-6: NOISE FROM FRONT-END
DRIVER AMPLIFIER
where eN is the broadband noise density (V/√Hz) of the
front-end driver amplifier and is typically given in its
data sheet. In Equation 6-6, 1/f noise (eNFlicker) is
ignored assuming it is very small compared to the
broadband noise (eN).
For high precision ADC applications, the noise
contribution from the front-end input driver amplifier is
typically constrained to be less than about 20% (or 1/5
times) of the ADC input-referred noise as shown in
Equation 6-7:
EQUATION 6-7: RECOMMENDED ADC
INPUT DRIVER NOISE
Using Equation 6-5 to Equation 6-7, the recommended
noise voltage density (eN) limit of the ADC input driver
is expressed in Equation 6-8:
Front-End Driver
ADC
VN_ADC Input-Referred Noise
VN_RMS_Driver Noise
+- +
-
R
C
5
2RC
---------------
(Hz)
BWInput Driver 5 x fB
for a single-pole RC filter
THDInput Driver ≤ THDADC -10 (dB)
.
FSR
22
------------
=10
SNR
20
-----------–
VN_ADC Input-Referred Noise
(V)
VREF
2
--------------
=10
SNR
20
-----------–
VREF
22
--------------
=10
SNR
20
-----------–
for differential input
for single-ended input
V
N_RMS_Driver Noise
GN
eN
2
-------fB
(V)
VN_ADC Input-Referred Noise
VN_RMS_Driver Noise
1
5
---
DS20005947B-page 36 2018 Microchip Technology Inc.
MCP33131D/MCP33121D/MCP33111D-XX
EQUATION 6-8: NOISE DENSITY FOR ADC
INPUT DRIVER
Using Equation 6-8, the recommended maximum
noise voltage density limit for unity gain input driver for
differential input ADC can be estimated. Ta b l e 6- 1 to
Table 6-3 show a few example results with GN = 1. The
user may use these tables as a reference when
selecting the ADC input driver amplifier.
TABLE 6-1: Noise Voltage Density (eN) of
Input Driver for MCP33131D-XX
TABLE 6-2: Noise Voltage Density (eN) of
Input Driver for MCP33121D-XX
TABLE 6-3: Noise Voltage Density (eN) of
Input Driver for MCP33111D-XX
ADC
(Note 1)
RC
Filter
ADC Input Driver
Amplifier (GN = 1)
VREF
SNR
(dBFS)
ADC
Input-Referred
Noise
fB
(Table 2)
Noise Voltage
Density (eN)
2.5V 87 79.1
V
3 MHZ7.3 nV/√Hz
4 MHz 6.3 nV/√Hz
5 MHZ5.6 nV/√Hz
3.3V 89 82.8 V
3 MHZ7.6 nV/√Hz
4 MHz 6.6 nV/√Hz
5 MHZ5.9 nV/√Hz
5V 92 88.8 V
3 MHZ8.2 nV/√Hz
4 MHz 7.1 nV/√Hz
5 MHZ6.3 nV/√Hz
Note 1: See Equation 6-5 for the ADC input-referred noise
calculation for differential input.
2: fB is -3dB bandwidth of the RC anti-aliasing filter.
(a) eN for differential input ADC:
(b) eN for single-ended input ADC:
V
Hz
-----------


eN
1
5GN
-------------------
1
fB
--------------- VREF 10
SNR
20
-----------–
eN
1
10 GN
----------------------
V
Hz
-----------


1
fB
--------------- VREF 10
SNR
20
-----------–
1
5
---
VN_ADC Input-Referred Noise
GN
eN
2
-------fB
ADC
(Note 1)
RC
Filter
ADC Input Driver
Amplifier (GN = 1)
VREF
SNR
(dBFS)
ADC
Input-Referred
Noise
fB
(Note 2)
Noise Voltage
Density (eN)
2.5V 84 111.5
V
3 MHZ10.3 nV/√Hz
4 MHz 8.9 nV/√Hz
5 MHZ8 nV/√Hz
3.3V 84.5 139 V
3 MHZ12.8 nV/√Hz
4 MHz 11.1 nV/√Hz
5 MHZ9.9 nV/√Hz
5V 85 198.8 V
3 MHZ18.3 nV/√Hz
4 MHz 15.9 nV/√Hz
5 MHZ14.2 nV/√Hz
Note 1: See Equation 6-5 for the ADC input-referred noise
calculation for differential input.
2: fB is -3dB bandwidth of the RC anti-aliasing filter.
ADC
(Note 1)
RC
Filter
ADC Input Driver
Amplifier (GN = 1)
VREF
SNR
(dBFS)
ADC
Input-Referred
Noise
fB
(Note 2)
Noise Voltage
Density (eN)
2.5V 73.8 360.9
V
3 MHZ33.3 nV/√Hz
4 MHz 28.8 nV/√Hz
5 MHZ25.8 nV/√Hz
3.3V 73.9 471 V
3 MHZ43.4 nV/√Hz
4 MHz 37.6 nV/√Hz
5 MHZ33.6 nV/√Hz
5V 74 705.4 V
3 MHZ 65 nV/√Hz
4 MHz 56.3 nV/√Hz
5 MHZ50.3 nV/√Hz
Note 1: See Equation 6-5 for the ADC input-referred noise cal-
culation for differential input.
2: fB is -3dB bandwidth of the RC anti-aliasing filter.
2018 Microchip Technology Inc. DS20005947B-page 37
MCP33131D/MCP33121D/MCP33111D-XX
6.4 Device Operation
When the MCP33131D/MCP33121D/MCP33111D-XX
is first powered-up, it self-calibrates internal systems
and enters input acquisition mode by itself. The device
operates in two phases: (a) Input Acquisition (Standby)
and (b) Data Conversion. Figure 6-10 shows the ADC
operating sequence.
6.4.1 INPUT ACQUISITION PHASE
(STANDBY)
During the input acquisition phase (tACQ), also called
Standby, the two input sampling capacitors, CS+ and
CS-, are connected to the AIN+ and AIN- pins,
respectively. The input voltage is sampled until a rising
edge on CNVST is detected. The input voltage should
be fully settled within 1/2 LSB during tACQ.
During this input acquisition time (tACQ), the ADC
consumes less than 1 A. The acquisition time (tACQ)
is user-controllable. The system designer can increase
the acquisition time (tACQ) as long as needed for
additional power savings.
6.4.2 DATA CONVERSION PHASE
The start of the conversion is controlled by CNVST. On
the rising edge of CNVST, the sampled charge is
locked (sample switches are opened) and the ADC
performs the conversion. Once a conversion is started,
it will not stop until the current conversion is complete.
The data conversion time (tCNV) is not user
controllable. After the conversion is complete and the
host lowers CNVST, the output data is presented on
SDO.
Any noise injection during the conversion phase may
affect the accuracy of the conversion. To reduce
external environment noise, minimize I/O events and
running clocks during the conversion time.
The output data is clocked out MSB first. While the
output data is being transferred, the device enters the
next input acquisition phase.
FIGURE 6-10: Device Operating Sequence.
Note: Transferring output data during the
acquisition phase can disturb the next
input sample. It is highly recommended to
allow at least tQUIET (10 ns, typical)
between the last edge on the SPI interface
and the rising edge on CNVST. See
Figure 1-1 for tQUIET
.
Operating tACQ
(b) All circuits are turned-on.
(a) ADC acquires input sample #1.
Condition
I
(c) Most analog circuits are
(a) Device is first powered-up and
(b) No ADC output is available yet.
(c) ADC output is not available yet.
t
ACQ
(b) Performs a power-up self-calibration.
IDDAN
(a) Conversion is initiated at the rising edge of CNVST.
(a) At the falling edge of CNVST,
ADC output is available at SDO.
(b) ADC output can be clocked out
(c) ADC acquires input sample #2.
(d) Most analog circuits are turned off.
Input Acquisition Data Conversion Input Acquisition
turned off.
SDO Output Data
~ 0.8 A
Off
(Standby) (Standby)
MCP331x1D-10: 300 ns (typical)
by providing clocks.
t
CNV
tCYC = 1/fS
MCP331x1D-05: 800 ns (typical)
MCP331x1D-10: 700 ns (typical)
MCP331x1D-05: 1200 ns (typical)
MCP331x1D-10: 300 ns (typical)
MCP331x1D-05: 800 ns (typical)
MCP331x1D-10: ~1.6 mA
MCP331x1D-05: ~1.4 mA
DS20005947B-page 38 2018 Microchip Technology Inc.
MCP33131D/MCP33121D/MCP33111D-XX
6.4.3 SAMPLE (THROUGHPUT) RATE
The device completes data conversion within the
maximum specification of the data conversion time
(tCNV). The continuous input sample rate is the inverse
of the sum of input acquisition time (tACQ) and data
conversion time (tCNV). Equation 6-9 shows the
continuous sample rate calculation using the minimum
and maximum specifications of the input acquisition
time (tACQ) and data conversion time (tCNV).
EQUATION 6-9: SAMPLE RATE
6.4.4 SERIAL SPI CLOCK FREQUENCY
REQUIREMENT
The ADC output is collected during the input acquisition
time (tACQ). For continuous input sampling and data
conversion sequence, the SPI clock frequency should
be fast enough to clock out all output data bits during
the input acquisition time (tACQ). For the continuous
sampling rate (fS), the minimum SPI clock frequency
requirement is determined by the following equation:
EQUATION 6-10: SPI CLOCK FREQUENCY
REQUIREMENT
where fSCLK is the minimum SPI serial clock frequency
required to transfer all N-bits of the output data during
input acquisition time (tACQ).
Table 6-4 and Table 6-5 show the examples of
calculated minimum SPI clock (fSCLK) requirements for
various input acquisition times for 1 Msps and 500 kSPS
family devices, respectively.
1
tACQ tCNV
+
----------------------------------
Sample Rate =
1
290ns 710ns+
-----------------------------------------1Msps=
(a) MCP331x1D-10:
Sample Rate =
1
700ns 1300ns+
--------------------------------------------500kSPS=
(b) MCP331x1D-05:
Sample Rate =
where N is the number of output data bits, given by
N = 16-bit for MCP33131D-XX
= 14-bit for MCP33121D-XX
= 12-bit for MCP33111D-XX
fSCLK
1
TSCLK
--------------- N
tACQ tQUIET tEN
+–
------------------------------------------------------
==
tACQ NT
SCLK
tQUIET tEN
++=
tQUIET = Quiet time between the last output bit and
beginning of the next conversion start.
= 10 ns (min)
tEN = Output enable time = 10 ns (max),
Note: See Figure 1-1 for interface timing diagram.
TSCLK = Period of SPI clock
N x TSCLK = Output data window
with DVIO 2.3V
TABLE 6-4: SPI CLOCK SPEED VS. INPUT ACQUISITION TIME (TACQ) FOR MCP331X1D-10
Input
Acquisition Time:
tACQ (nS)
Data Conversion
Time (nS)
SPI Clock (fSCLK) Speed Requirement
(Note 1), (Note 2) Sample Rate:
fS (Msps) Conditions
MCP33131D-10
(16-bit)
MCP33121D-10
(14-bit)
MCP33111D-10
(12-bit)
250
750
69.57 MHz 60.87 MHz 52.17 MHz 1
85°C < TA≤ 125°C
(Note 3)
270 64 MHz 56 MHz 48 MHz 0.98
280 61.54 MHz 53.85 MHz 46.15 MHz 0.97
290
710
59.26 MHz 51.85 MHz 44.44 MHz 1
-40°C ≤TA≤ 85°C
300 57.15 MHz 50 MHz 42.86 MHz 0.99
320 53.33 MHz 46.67 MHz 40 MHz 0.97
400 42.11 MHz 36.84 MHz 30 MHz 0.9
540 30.77 MHz 26.92 MHz 23.08 MHz 0.8
720 22.86 MHz 20 MHz 17.14 MHz 0.7
720 17.2 MHz 15.05MHz 12.9 MHz 0.6
1290 12.6 MHz 11.02 MHz 9.45 MHz 0.5
1750 9.04 MHz 7.91 MHz 6.78 MHz 0.4
2620 6.15 MHz 5.39 MHz 4.62 MHz 0.3
4290 3.75 MHz 3.28 MHz 2.81 MHz 0.2
9290 1.73 MHz 1.51 MHz 1.3 MHz 0.1
Note 1: This is the minimum SPI clock speed requirement to collect all N-bits of the ADC output during the input acquisition time (tACQ), when
the ADC is operating in continuous input sampling mode.
2: See Equation 6-10 for the calculation of the SPI clock speed requirement.
3: In extended temperature range, the device takes longer data conversion time (tCNV: 750 nS, max). Using a shorter input acquisition time
is recommended (tACQ: 250 nS) for 1 Msps throughput rate.
2018 Microchip Technology Inc. DS20005947B-page 39
MCP33131D/MCP33121D/MCP33111D-XX
6.5 Transfer Function
The differential analog input is
VIN = (VIN+) - (VIN-).
The LSB size is given by Equation 6-11. and an
example of LSB size vs. reference voltage is
summarized in Tabl e 6 - 6 .
EQUATION 6-11: LSB SIZE - EXAMPLE
where N is the resolution of the ADC in bits.
TABLE 6-6: LSB SIZE VS. REFERENCE
Figure 6-11 shows the ideal transfer function and
Table 6-7 shows the digital output codes for the
MCP33131D/MCP33121D/MCP33111D-XX.
FIGURE 6-11: Ideal Transfer Function for
Fully-Differential Input Signal.
TABLE 6-5: SPI CLOCK SPEED VS. INPUT ACQUISITION TIME (TACQ) FOR MCP331X1D-05
Input
Acquisition Time:
tACQ (nS)
Data Conversion
Time (nS)
SPI Clock (fSCLK) Speed Requirement
(Note 1), (Note 2) Sample Rate:
fS (kSPS) Conditions
MCP33131D-05
(16-bit)
MCP33121D-05
(14-bit)
MCP33111D-05
(12-bit)
700
1300
23.53MHz 20.59 MHz 17.65 MHz 500
-40°C ≤TA≤ 125°C
740 22.22 MHz 19.44 MHz 16.67 MHz 490
790 20.78 MHz 18.18 MHz 15.58 MHz 480
930 17.58 MHz 15.39 MHz 13.19 MHz 450
1200 13.56 MHz 11.86 MHz 10.17 MHz 400
1560 10.39 MHz 9.09 MHz 7.79 MHz 350
2030 7.96 MHz 6.97 MHz 5.97 MHz 300
2700 5.97 MHz 5.22MHz 4.48 MHz 250
3700 4.35 MHz 3.8 MHz 3.26 MHz 200
5370 2.99 MHz 2.62 MHz 2.25 MHz 150
8700 1.84 MHz 1.61 MHz 1.38 MHz 100
Note 1: This is the minimum SPI clock speed requirement to collect all N-bits of the ADC output during the input acquisition time (tACQ), when the
ADC is operating in continuous input sampling mode.
2: See Equation 6-10 for the calculation of the SPI clock speed requirement.
Reference
Voltage
(VREF)
LSB Size
MCP33131D-XX
(16-bit)
MCP33121D-XX
(14-bit)
MCP33111D-XX
(12-bit)
2.5V 76.3 V 305.2 V 1.2207 mV
2.7V 82.4 V 329.6 V 1.3184 mV
3V 91.6 V 366.2 V 1.4648 mV
3.3V 100.7 V 402.8 V1.6113 mV
3.5V 106.8 V 427.3 V 1.7090 mV
4V 122.1 V 488.3 V 1.9531 mV
4.5V 137.3 V 549.3 V 2.1973 mV
5V 152.6 V 610.4 V 2.4414 mV
5.1V 155.6 V 622.6 V 2.4902 mV
LSB
2VREF
2N
----------------=
-VREF
Differential Analog Input Voltage
0V
+VREF - 1 LSB
-VREF + 0.5 LSB +VREF - 1.5 LSB
Digital Output Code (Two’s Complement)
011 ...111
000 ...000
011 ...110
100 ...001
100 ...000
-VREF + 1 LSB
DS20005947B-page 40 2018 Microchip Technology Inc.
MCP33131D/MCP33121D/MCP33111D-XX
6.6 Digital Output Code
The digital output code is proportional to the input
voltage. The output data is in binary two’s complement
format. With this coding scheme the MSB can be
considered a sign indicator. When the MSB is a logic
‘0’, the input is positive. When the MSB is a logic ‘1’, the
input is negative. The following is an example of the
output code:
(a) for a negative full-scale input:
Analog Input: (VIN+) - (VIN-) = -VREF
Output Code: 1000...0000
(b) for a zero differential input:
Analog Input: (VIN+) - (VIN-) = 0V
Output Code: 0000...0000
(c) for a positive full-scale input:
Analog Input: (VIN+) - (VIN-) = +VREF
Output Code: 0111...1111
The MSB (sign bit) is always transmitted first through
the SDO pin.
The code will be locked at 0111...11 for all voltages
greater than (VREF - 1 LSB) and 1000...00 for
voltages less than -VREF
. Ta b l e 6 - 7 shows an example
of output codes of various input levels.
TABLE 6-7: DIGITAL OUTPUT CODE
Input Voltage (V)
Digital Output Codes
MCP33131D-XX
(16-bit)
MCP33121D-XX
(14-bit)
MCP33111D-XX
(12-bit)
VREF 0111-1111-1111-1111 01-1111-1111-1111 0111-1111-1111
VREF - 1 LSB 0111-1111-1111-1111 01-1111-1111-1111 0111-1111-1111
.
.
.
.
.
.
.
.
2LSB 0000-0000-0000-0010 00-0000-0000-0010 0000-0000-0010
1LSB 0000-0000-0000-0001 00-0000-0000-0001 0000-0000-0001
0V 0000-0000-0000-0000 00-0000-0000-0000 0000-0000-0000
-1 LSB 1111-1111-1111-1111 11-1111-1111-1111 1111-1111-1111
-2 LSB 1111-1111-1111-1110 11-1111-1111-1110 1111-1111-1110
.
.
.
.
.
.
.
.
- VREF 1000-0000-0000-0000 10-0000-0000-0000 1000-0000-0000
< -VREF 1000-0000-0000-0000 10-0000-0000-0000 1000-0000-0000
2018 Microchip Technology Inc. DS20005947B-page 41
MCP33131D/MCP33121D/MCP33111D-XX
7.0 DIGITAL SERIAL INTERFACE
The device has a SPI-compatible serial digital
interface using four digital pins: CNVST, SDI, SDO and
SCLK.
Figure 7-1 shows the connection diagram with the host
device and Figure 7-2 shows the SPI-compatible serial
interface timing diagram.
The SDI pin can be tied to the digital I/O interface
supply voltage (DVIO) or just maintain logic “High” level
by the host. The CNVST pin is used for both chip select
(CS) and conversion-start control.
A rising edge on CNVST initiates the conversion
process. Once the conversion is initiated, the device
will complete the conversion regardless of the state of
CNVST. This means the CNVST pin can be used for
other purposes during tCNV.
When the conversion is complete, the output is
available at SDO by lowering CNVST. Data is sent
MSB-first and changes on the falling edge of SCLK.
Output data can be sampled on either edge of SCLK.
However, a digital host capturing data on the falling
edge of SCLK can achieve a faster read out rate.
SDO returns to high-Z state after the last data bit is
clocked out or when CNVST goes high, whichever
occurs first.
FIGURE 7-1: Digital Interface Connection
Diagram.
FIGURE 7-2: SPITMCompatible Serial Interface Timing Diagram (16-bit device).
CNVST
SCLK
SDO
CS
SCLK
SDI
(a) MCP33131D/21D/11D-XX (b) Host Device (Master)
Note 1: Adding this pull-up is needed when monitoring
status of Recalibrate.
DVIO
(Note 1)
10 k
SDI
DVIO
CNVST
SDO
SCLK 12314 15 16
4
D15 D14 D13 D12 D2 D1 D0
ADC State
(MSB)
Hi-Z Hi-Z
tCNVH
tCNV (MAX)
tSCLK
tSCLK_L tSCLK_H
tDO
tDIS
Conversion
(a) Exit input acquisition mode and
(b) Enter new conversion mode
Note 1: SDI must maintain “High” during the entire tCYC.
(Note 2)
Input Acquisition
Input Acquisition
(tCNV)(tACQ)
(tACQ)
tCYC
2: Any SCLK toggling events (dummy clocks) before CNVST is changed to “Low” are ignored.
SDI = DVIO
tSU_SDIH_CNV
(Note 1)
tEN
tQUIET
tEN
(Note 3)
(Note 4)
3: tEN when CNVST is lowered after tCNV (Max).
4: tEN when CNVST is lowered before tCNV (Max).
= 1/fS
(Note 5)
5: Recommended data detection: Detect SDO on the falling edge of SCLK.
DS20005947B-page 42 2018 Microchip Technology Inc.
MCP33131D/MCP33121D/MCP33111D-XX
7.1 Recalibrate Command
The user may use the recalibrate command in the
following cases:
• When the reference voltage was not fully settled
during the first-power sequence.
• During operation, to ensure optimum performance
across varying environment conditions, such as
reference voltage and temperature.
A self-calibration is initiated by sending the recalibrate
command. The host device sends a recalibrate
command by transmitting 1024 SCLK pulses (including
the clocks for data bits) while the device is in the
acquisition phase (Standby).
The device drives SDO low during the recalibration
procedure, and returns to high-Z once completed. The
status of the recalibration procedure can be monitored
by placing a pull-up on SDO, so that SDO goes high
when the recalibration is complete.
Figure 7-3 shows the recalibrate command timing
diagram. The calibration takes approximately 500 ms
(tCAL).
FIGURE 7-3: Recalibrate Command Timing Diagram.
Note: When the device performs a self-calibration, it is important to note that both AVDD and the reference voltage
(VREF) must be stabilized for a correct calibration. This is also true when the device is first powered-up, the
reference voltage (VREF) must be stabilized before self-calibration begins. This means the VREF must be
provided prior to supplying AVDD or within about 64 ms after supplying AVDD.
1024 clocks
Start recalibration
tCAL
16
1
(SPITM Recalibrate command)
Hi-Z
Hi-Z
Note
“Low”
1024
“High” with Pull-up
Hi-Z
ADC Output Data Stream
“High” with Pull-up
2: The 1024 clocks include the clocks for data bits.
tCNV
Complete da
ta reading
Finish recalibration
Device Recalibration
(Note 3)
(Note 2)
1: SDI must remain “High” during the entire recalibration cycle.
(Note 4)
3: SDO outputs “Low” during calibration, and Hi-Z when exiting the calibration.
SDI = DVIO
4: After finishing the recalibration procedure, the device is ready for a new input sampling immediately.
(Note 1)
CNVST
SDO
SCLK
ADC State
23 15
2018 Microchip Technology Inc. DS20005947B-page 43
MCP33131D/MCP33121D/MCP33111D-XX
8.0 DEVELOPMENT SUPPORT
8.1 Device Evaluation Board
Microchip offers a high speed/high precision SAR ADC
evaluation platform which can be used to evaluate
Microchip’s latest high speed/high resolution SAR ADC
products. The platform consists of an MCP331x1D-XX
evaluation board, a data capture board (PIC32MZ EF
Curiosity Board), and a PC-based Graphical User
Interface (GUI) software.
Figure 8-1 and Figure 8-2 show this evaluation tool.
This evaluation platform allows users to quickly
evaluate the ADC's performance for their specific
application requirements.
FIGURE 8-1: MCP331x1D-XX Evaluation Kit.
FIGURE 8-2: PC-Based Graphical User Interface Software.
Note: Contact Microchip Technology Inc. for the
PIC32 MCU firmware and the
MCP331x1D-XX Evaluation Kit.
(a) MCP331x1D-XX Evaluation Board
(b) PIC32 MZ EF Curiosity Board
DS20005947B-page 44 2018 Microchip Technology Inc.
MCP33131D/MCP33121D/MCP33111D-XX
8.2 PCB Layout Guidelines:
Microchip provides the schematics and PCB layout of
the MCP331x1D-XX Evaluation Board. It is strongly
recommended that the user references the example
circuits and PCB layouts.
A good schematic with low noise PCB layout is critical
for high performing ADC application system designs. A
few guidelines are listed below:
• Use low noise supplies (AVDD, DVIO, and VREF).
• All supply voltage pins, including reference volt-
age, need decoupling capacitors. Decoupling
capacitor requirements for each supply pin are
shown in Table 5-1.
• Use NPO or COG type capacitor for the RC anti-
aliasing filters in the analog input network.
• Keep the analog circuit section (analog input
driver amplifiers, filters, voltage reference, ADC,
etc.) with an analog ground plane, and the digital
circuit section (MCU, digital I/O interface) with a
digital ground plane. Keep these sections as
much apart as possible. This will minimize any
digital switching noise coupling into the analog
section.
• Connect the analog and digital ground planes at a
single point (away from the sensitive analog sec-
tions) with a 0 resistor or with a ferrite bead.
See Figure 8-3 as an example of separated
ground planes.
• Keep the clock and digital output data lines short
and away from the sensitive analog sections as
much as possible.
•PCB material and Layers: Low loss FR-4 mate-
rial is most commonly used. The following 4 lay-
ers are recommended:
(a) Top Layer: Most of the noise-sensitive ana-
log components are populated on the top layer.
Use all unused surface area as ground planes:
analog ground plane in analog circuit section
and digital ground in digital circuit section. These
ground planes need to be tied to the corre-
sponding ground planes in the second and bot-
tom layers using multiple vias.
(b) 2nd Layer: Use this layer as the ground
plane: Analog ground plane under the analog
circuit section of the top layer and digital ground
plane under the digital circuit section on the top
layer. Each ground plane is tied to its corre-
sponding ground plane of top and bottom layers
using multiple vias.
(c) 3rd Layer: This layer is used to distribute
various power supplies of the circuits. Use sep-
arate trace paths for the power supplies of ana-
log and digital sections. Do not use the same
power supply source for both analog and digital
circuits.
(d) Bottom Layer: This layer is mostly used as
a solid ground plane: Analog ground plane
under the analog circuit section of the top layer
and digital ground plane under the digital circuit
section on the top layer. Each ground plane is
tied to its corresponding ground plane of all lay-
ers using multiple vias.
Figure 8-3 and Figure 8-4 show brief examples
of the PCB layout. See more details of the sche-
matics and PCB layout in the MCP331x1D-XX
Evaluation Board User’s Guide.
FIGURE 8-3: PCB Layout Example: Analog and Digital Ground Planes
Digital Ground Plane
Analog Ground Plane
Digital Interface
(DGND)
Connectors for MCU
(GND)
Note: Analog and digital
ground planes are
connected via R56.
MCP331x1D-XX
SDO
SCLK
R56
Analog Ground Plane
(GND)
Digital Ground Plane
(DGND)
2018 Microchip Technology Inc. DS20005947B-page 45
MCP33131D/MCP33121D/MCP33111D-XX
FIGURE 8-4: PCB Layout Example: See more details in the MCP331x1D-XX EV Kit User’s Guide.
VIN+
VIN-
MCP331x1D-XX
AIN+
AIN-
VREF
AVDD
GND
CNVST
SDO
SCLK
SDI
VIO
C9 C59
C7 C6
C10
VREF
MCP331x1D-XX
R24 = 0 for Single-Ended
Configuration
33R
33R
33R
33R
SDI
SDO
SCLK
CNVST
(a) PCB layout example
(b) Schematic example from the MCP331x1D-XX Evaluation Board
C6
10uF
(Tantalum)
C7
100pF
R3
22R
R8
22R C37
1.7nF
(NPO)
C35
1.7nF
(NPO)
DS20005947B-page 46 2018 Microchip Technology Inc.
MCP33131D/MCP33121D/MCP33111D-XX
NOTES:
2018 Microchip Technology Inc. DS20005947B-page 47
MCP33131D/MCP33121D/MCP33111D-XX
9.0 TERMINOLOGY
Analog Input Bandwidth (Full-Power
Bandwidth)
The analog input frequency at which the spectral power
of the fundamental frequency (as determined by FFT
analysis) is reduced by 3 dB.
Aperture Delay or Sampling Delay
This is the time delay between the rising edge of the
CNVST input and when the input signal is held for a
conversion.
Differential Nonlinearity
(DNL, No Missing Codes)
An ideal ADC exhibits code transitions that are exactly
1 LSB apart. DNL is the deviation from this ideal value.
No missing codes to 16-bit resolution indicates that all
65,536 codes (16,384 codes for 14-bit, 4096 codes for
12-bit) must be present over all the operating
conditions.
Integral Nonlinearity (INL)
INL is the maximum deviation of each individual code
from an ideal straight line drawn from negative full
scale through positive full scale.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the power of the fundamental (PS) to
the noise floor power (PN), below the Nyquist frequency
and excluding the power at DC and the first nine
harmonics.
EQUATION 9-1:
SNR is either given in units of dBc (dB to carrier), when
the absolute power of the fundamental is used as the
reference, or dBFS (dB to full-scale), when the power
of the fundamental is extrapolated to the converter
full-scale range.
Signal-to-Noise and Distortion (SINAD)
SINAD is the ratio of the power of the fundamental (PS)
to the power of all the other spectral components
including noise (PN) and distortion (PD) below the
Nyquist frequency, but excluding DC:
EQUATION 9-2:
SINAD is either given in units of dBc (dB to carrier),
when the absolute power of the fundamental is used as
the reference, or dBFS (dB to full-scale), when the
power of the fundamental is extrapolated to the
converter full-scale range.
Effective Number of Bits (ENOB)
The effective number of bits for a sine wave input at a
given input frequency can be calculated directly from its
measured SINAD using the following formula:
EQUATION 9-3:
Gain Error
Gain error is the deviation of the ADC’s actual input
full-scale range from its ideal value. The gain error is
given as a percentage of the ideal input full-scale
range. Gain error is usually expressed in LSB or as a
percentage of full-scale range (%FSR).
Offset Error
The major carry transition should occur for an analog
value of ½ LSB below AIN+=A
IN−. Offset error is
defined as the deviation of the actual transition from
that point.
Temperature Drift
The temperature drift for offset error and gain error
specifies the maximum change from the initial (+25°C)
value to the value at across the TMIN to TMAX range.
The value is normalized by the reference voltage and
expressed in V/oC or ppm/oC.
Maximum Conversion Rate
The maximum clock rate at which parametric testing is
performed.
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio of the power of the fundamental to the
highest other spectral component (either spur or
harmonic). SFDR is typically given in units of dBc (dB
to carrier) or dBFS.
SNR 10
PS
PN
-------



log=
SINAD 10
PS
PDPN
+
----------------------



log=
10–=10
SNR
10
-----------–
10
THD
10
------------–
–log
ENOB SINAD 1.76–
6.02
----------------------------------=
MCP33131D/MCP33121D/MCP33111D-XX
DS20005947B-page 48 2018 Microchip Technology Inc.
Total Harmonic Distortion (THD)
THD is the ratio of the power of the fundamental (PS) to
the summed power of the first 13 harmonics (PD).
EQUATION 9-4:
THD is typically given in units of dBc (dB to carrier).
THD is also shown by:
EQUATION 9-5:
Common-Mode Rejection Ratio (CMRR)
Common-mode rejection is the ability of a device to
reject a signal that is common to both sides of a
differential input pair. The common-mode signal can be
an AC or DC signal or a combination of the two. CMRR
is measured using the ratio of the differential signal
gain to the common-mode signal gain and expressed in
dB with the following equation:
EQUATION 9-6:
THD 10
PS
PD
--------



log=
THD 20
V2
2V3
2V4
2
Vn
2
++++
V1
2
------------------------------------------------------------------log–=
Where:
V1= RMS amplitude of the
fundamental frequency
V1 through Vn= Amplitudes of the second
through nth harmonics
CMRR 20
ADIFF
ACM
------------------



log=
Where:
ADIFF =Output Code/Differential Voltage
ADIFF =Output Code/Common-Mode Voltage
2018 Microchip Technology Inc. DS20005947B-page 49
MCP33131D/MCP33121D/MCP33111D-XX
10.0 PACKAGING INFORMATION
10.1 Package Marking Information
PIN 1
10-Lead TDFN (3x3x0.9 mm) Example
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
31D1
1839
256
10-Lead MSOP (3x3 mm) Example
31D-10
839256
31D-10 = MCP33131D-10
31D-05 = MCP33131D-05
21D-10 = MCP33121D-10
21D-05 = MCP33121D-05
11D-10 = MCP33111D-10
11D-05 = MCP33111D-05
XXXX
YYWW
NNN
PIN 1
31D1 = MCP33131D-10
31D0 = MCP33131D-05
21D1 = MCP33121D-10
21D0 = MCP33121D-05
11D1 = MCP33111D-10
11D0 = MCP33111D-05
Corresponding Part Number:
Corresponding Part Number:
MCP33131D/MCP33121D/MCP33111D-XX
DS20005947B-page 50 2018 Microchip Technology Inc.
0.13 C A B
12
N
TOP VIEW
SIDE VIEW END VIEW
Microchip Technology Drawing C04-021D Sheet 1 of 2
http://www.microchip.com/packaging
For the most current package drawings, please see the Microchip Packaging Specification located atNote:
10-Lead Plastic Micro Small Outline Package (MS) [MSOP]
D
EE1
D
2
E1
2
E
2
0.20 H
0.25 C
0.20 H
A
B
e
8X b
AA2
A1 0.10 C
8X
C
SEATING
PLANE
H
SEE DETAIL A
2018 Microchip Technology Inc. DS20005947B-page 51
MCP33131D/MCP33121D/MCP33111D-XX
Microchip Technology Drawing C04-021D Sheet 2 of 2
10-Lead Plastic Micro Small Outline Package (MS) [MSOP]
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
REF: Reference Dimension, usually without tolerance, for information purposes only.
3.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
1.
Notes:
2.
Pin 1 visual index feature may vary, but must be located within the hatched area.
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
Dimensioning and tolerancing per ASME Y14.5M.
protrusions shall not exceed 0.15mm per side.
L1Footprint
Mold Draft Angle
Lead Width
Lead Thickness c
b
Dimension Limits
Overall Height
Molded Package Thickness
Molded Package Width
Overall Length
Foot Length
Standoff
Overall Width
Number of Pins
Pitch
A
L
E1
D
A1
E
A2
e
N
Units
0.95 REF
-
-
0.08
0.15
0.23
0.33
MILLIMETERS
0.50 BSC
0.85
3.00 BSC
3.00 BSC
0.60
4.90 BSC
0.40
0.00
0.75
MIN NOM
1.10
0.80
0.15
0.95
MAX
10
-
--
8°0°
-
C
SEATING
PLANE
L
(L1)
c
Ĭ
Ĭ
DETAIL A
Foot Angle - 15°5°
Ĭ1
4X Ĭ1
4X Ĭ1
MCP33131D/MCP33121D/MCP33111D-XX
DS20005947B-page 52 2018 Microchip Technology Inc.
RECOMMENDED LAND PATTERN
Microchip Technology Drawing No. C04-2021B
10-Lead Plastic Micro Small Outline Package (MS) [MSOP]
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Notes:
Dimensioning and tolerancing per ASME Y14.5M1.
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
Dimension Limits
Units
CContact Pad Spacing
Overall Width
Contact Pitch
Z
MILLIMETERS
0.50 BSC
MIN
E
MAX
4.40
5.80
Contact Pad Length (X10)
Contact Pad Width (X10)
Y1
X1
1.40
0.30
GDistance Between Pads (X8) 0.20
NOM
Distance Between Pads (X5) G1 3.00
E
C
ZG1
X1
G
Y1
SILK SCREEN
2018 Microchip Technology Inc. DS20005947B-page 53
MCP33131D/MCP33121D/MCP33111D-XX
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
MCP33131D/MCP33121D/MCP33111D-XX
DS20005947B-page 54 2018 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2018 Microchip Technology Inc. DS20005947B-page 55
MCP33131D/MCP33121D/MCP33111D-XX
APPENDIX A: REVISION HISTORY
Revision B (November 2018)
• Added TDFN-10 package release
• Added AEC-Q100 qualification
• Added 500 kSPS family devices (MCP33131D/
MCP33121D/MCP33111D-05)
• Minor typographical corrections
Revision A (March 2018)
• Original release of this document
2018 Microchip Technology Inc. DS20005947B-page 56
MCP33131D/MCP33121D/MCP33111D-XX
NOTES:
MCP33131D/MCP33121D/MCP33111D-XX
DS20005947B-page 57 2018 Microchip Technology Inc.
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. ─X/XXX
Tape PackageTemperature
Range
Device
Device: MCP33131D-10: 1 Msps 16-Bit Differential Input SAR ADC
MCP33121D-10: 1 Msps 14-Bit Differential Input SAR ADC
MCP33111D-10: 1 Msps 12-Bit Differential Input SAR ADC
MCP33131D-05: 500 kSPS 16-Bit Differential Input SAR ADC
MCP33121D-05: 500 kSPS 14-Bit Differential Input SAR ADC
MCP33111D-05: 500 kSPS 12-Bit Differential Input SAR ADC
Input Type D: Differential Input
Sample Rate: 10 = 1 Msps
05 = 500 kSPS
Tape and
Reel Option:
Blank = Standard packaging (tube or tray)
T = Tape and Reel
Temperature
Range:
E= -40C to +125C (Extended)
I= -40C to +85C (Industrial)
Package: MS = Plastic Micro Small Outline Package (MSOP), 10-Lead
MN = Thin Plastic Dual Flat No Lead Package (TDFN),
10-Lead
Note: Tape and Reel identifier appears only in the catalog part number
description. This identifier is used for ordering purposes and is not
printed on the device package. Check with your Microchip Sales Office
for package availability with the Tape and Reel option.
─XX
Sample Rate
Examples:
a) MCP33131D-10-I/MS: 1 Msps, 10LD MSOP,
16-bit device
b) MCP33131D-10T-I/MS: 1 Msps, 10LD MSOP,
Tape and Reel,
16-bit device
c) MCP33131D-10-I/MN: 1 Msps, 10LD TDFN,
16-bit device
d) MCP33131D-10T-I/MN: 1 Msps, 10LD TDFN,
Tape and Reel,
16-bit device
e) MCP33121D-10-I/MS: 1 Msps, 10LD MSOP,
14-bit device
f) MCP33121D-10T-I/MS: 1 Msps, 10LD MSOP,
Tape and Reel,
14-bit device
g) MCP33121D-10-I/MN: 1 Msps, 10LD TDFN,
14-bit device
h) MCP33121D-10T-I/MN: 1 Msps, 10LD TDFN,
Tape and Reel,
14-bit device
i) MCP33111D-10-I/MS: 1 Msps, 10LD MSOP,
12-bit device
j) MCP33111D-10T-I/MS: 1 Msps, 10LD MSOP,
Tape and Reel,
12-bit device
k) MCP33111D-10-I/MN: 1 Msps, 10LD TDFN,
12-bit device
l) MCP33111D-10T-I/MN: 1 Msps, 10LD TDFN,
Tape and Reel,
12-bit device
m) MCP33131D-05-I/MS: 500 kSPS, 10LD MSOP,
16-bit device
n) MCP33131D-05T-I/MS: 500 kSPS, 10LD MSOP,
Tape and Reel,
16-bit device
o) MCP33131D-05-I/MN: 500 kSPS, 10LD TDFN,
16-bit device
p) MCP33131D-05T-I/MN: 500 kSPS, 10LD TDFN,
Tape and Reel,
16-bit device
q) MCP33121D-05-I/MS: 500 kSPS, 10LD MSOP,
14-bit device
r) MCP33121D-05T-I/MS: 500 kSPS, 10LD MSOP,
Tape and Reel,
14-bit device
s) MCP33121D-05-I/MN: 500 kSPS, 10LD TDFN,
14-bit device
t) MCP33121D-05T-I/MN: 500 kSPS, 10LD TDFN,
Tape and Reel,
14-bit device
u) MCP33111D-10-I/MS: 500 kSPS, 10LD MSOP,
12-bit device
v) MCP33111D-10T-I/MS: 500 kSPS, 10LD MSOP,
Tape and Reel,
12-bit device
w) MCP33111D-10-I/MN: 500 kSPS, 10LD TDFN,
12-bit device
x) MCP33111D-10T-I/MN: 500 kSPS, 10LD TDFN,
Tape and Reel,
12-bit device
Input Type
X
Reel
and
2018 Microchip Technology Inc. DS20005947B-page 58
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate, AVR,
AVR logo, AVR Freaks, BitCloud, chipKIT, chipKIT logo,
CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo,
JukeBlox, KeeLoq, Kleer, LANCheck, LINK MD, maXStylus,
maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip
Designer, QTouch, SAM-BA, SpyNIC, SST, SST Logo,
SuperFlash, tinyAVR, UNI/O, and XMEGA are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
and other countries.
ClockWorks, The Embedded Control Solutions Company,
EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS,
mTouch, Precision Edge, and Quiet-Wire are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard,
CryptoAuthentication, CryptoAutomotive, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, INICnet, Inter-Chip Connectivity,
JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi,
motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB,
MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation,
PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon,
QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O,
SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
Silicon Storage Technology is a registered trademark of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2018, Microchip Technology Incorporated, All Rights
Reserved.
ISBN: 978-1-5224-3863-2
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITYMANAGEMENTS
YSTEM
CERTIFIEDBYDNV
== ISO/TS16949==
DS20005947B-page 59 2018 Microchip Technology Inc.
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