2018 Microchip Technology Inc. DS20005947B-page 1
MCP33131D/21D/11D-XX
Features
• Sample Rate (Throughput):
- MCP33131D/21D/11D-10: 1 Msps
- MCP33131D/21D/11D-05: 500 kSPS
• 16/14/12-Bit Resolution with No Missing Codes
• No Latency Output
• Wide Operating Voltage Range:
- Analog Supply Voltage (AVDD): 1.8V
- Digital Input/Output Interface Voltage (DVIO):
1.7V - 5.5V
- External Reference (VREF): 2.5V - 5.1V
• Differential Input Operation
- Input Full-Scale Range: -VREF to +VREF
•Ultra Low Current Consumption (typical):
- During Input Acquisition (Standby): ~ 0.8 µA
- During Conversion:
MCP33131D/21D/11D-10: ~1.6 mA
MCP33131D/21D/11D-05: ~1.4 mA
• SPI-Compatible Serial Communication:
- SCLK Clock Rate: up to 100 MHz
• ADC Self-Calibration for Offset, Gain, and
Linearity Errors:
- During Power-Up (automatic)
- On-Demand via user’s command during
normal operation
• AEC-Q100 Qualified:
- Temperature Grade 1: -40°C to +125°C
• Package Options: MSOP-10 and TDFN-10
Typical Applications
• High-Precision Data Acquisition
• Medical Instruments
• Test Equipment
• Electric Vehicle Battery Management Systems
• Motor Control Applications
• Switch-Mode Power Supply Applications
• Battery-Powered Equipment
System Design Supports
The MCP331x1D-XX Evaluation Kit demonstrates the
performance of the MCP331x1D-XX SAR ADC family
devices. The evaluation kit includes: (a) MCP331x1D
Evaluation Board, (b) PIC32MZ EF Curiosity Board for
data collection, and (c) SAR ADC Utility PC GUI.
Contact Microchip Technology Inc. for the evaluation
tools and the PIC32 MCU firmware example codes.
Package Types
10
MSOP-10
AIN+
AVDD
AIN-
SDI
SCLK
1
2
3
4
9
8
7SDO
DVIO
VREF
TDFN-10
AIN+
AVDD
AIN-
SDI
SCLK
1
2
3
4
10
9
8
7SDO
DVIO
VREF
56
GND CNVST
56
GND CNVST
Top View
Top Vi e w
MCP331x1D-XX Device Offering (Note 1):
Part Number Resolution Sample
Rate Input Type Input Range
(Differential)
Performance (Typical)
SNR
(dBFS)
SFDR
(dB)
THD
(dB)
INL
(LSB)
DNL
(LSB)
MCP33131D-10 16-bit 1 Msps Differential ±5.1V 91.3 103.5 -99.3 ±2 ±0.8
MCP33121D-10 14-bit 1 Msps Differential ±5.1V 85.1 103.5 -99.2 ±0.5 ±0.25
MCP33111D-10 12-bit 1 Msps Differential ±5.1V 73.9 99.3 -96.7 ±0.12 ±0.06
MCP33131D-05 16-bit 500 kSPS Differential ±5.1V 91.3 103.5 -99.3 ±2 ±0.8
MCP33121D-05 14-bit 500 kSPS Differential ±5.1V 85.1 103.5 -99.2 ±0.5 ±0.25
MCP33111D-05 12-bit 500 kSPS Differential ±5.1V 73.9 99.3 -96.7 ±0.12 ±0.06
Note 1: SNR, SFDR, and THD are measured with fIN = 10 kHz, VIN = -1 dBFS, VREF = 5.1V.
1 Msps/500 kSPS 16/14/12-Bit Differential Input SAR ADC
MCP33131D/MCP33121D/MCP33111D-XX
DS20005947B-page 2 2018 Microchip Technology Inc.
Application Diagram
Description
The MCP33131D/MCP33121D/MCP33111D-10 and
MCP33131D/MCP33121D/MCP33111D-05 are
fully-differential 16, 14, and 12-bit, single-channel
1 Msps and 500 kSPS ADC family devices,
respectively, featuring low power consumption and
high performance, using a successive approximation
register (SAR) architecture.
The device operates with a 2.5V to 5.1V external
reference (VREF), which supports a wide range of input
full-scale range from -VREF to +VREF
. The reference
voltage setting is independent of the analog supply
voltage (AVDD) and is higher than AVDD. The
conversion output is available through an easy-to-use
simple SPI- compatible 3-wire interface.
The device requires a 1.8V analog supply voltage
(AVDD) and a 1.7V to 5.5V digital I/O interface supply
voltage (DVIO). The wide digital I/O interface supply
(DVIO) range (1.7V – 5.5V) allows the device to
interface with most host devices (Master) available in
the current industry such as the PIC32
microcontrollers, without using external voltage level
shifters.
When the device is first powered-up, it performs a
self-calibration to minimize offset, gain and linearity
errors. The device performance stays stable across the
specified temperature range. However, when extreme
changes in the operating environment, such as in the
reference voltage, are made with respect to the initial
conditions (e.g. the reference voltage was not fully
settled during the initial power-up sequence), the user
may send a recalibrate command anytime to initiate
another self-calibration to restore optimum
performance.
When the initial power-up sequence is completed, the
device enters a low-current input acquisition mode,
where sampling capacitors are connected to the input
pins. This mode is called Standby.
During Standby, most of the internal analog circuitry is
shutdown in order to reduce current consumption.
Typically, the device consumes less than 1 µA during
Standby. A new conversion is started on the rising edge
of CNVST. When the conversion is complete and the
host lowers CNVST, the output data is presented on
SDO, and the device enters Standby to begin acquiring
the next input sample. The user can clock out the ADC
output data using the SPI-compatible serial clock
during Standby.
The ADC system clock is generated by the internal
on-chip clock, therefore the conversion is performed
independent of the SPI serial clock (SCLK).
This device can be used for various high-speed and
high-accuracy analog-to-digital data conversion
applications, where design simplicity, low power, and
no output latency are needed.
The device is AEC-Q100 qualified for automotive appli-
cations and operates over the extended temperature
range of -40°C to +125°C. The available package
options are Pb-free small 3 mm x 3 mm TDFN-10 and
MSOP-10.
1.7 nF
22Ω
0V to VREF
AIN+
AIN-
VREF AVDD DVIO
SDI
SCLK
SDO
CNVST
2.5V to 5.1V 1.8V 1.8V to 5.5V
GND
(PIC32MZ)
Host Device
1.7 nF
22Ω
0V to VREF
MCP331x1D-XX
2018 Microchip Technology Inc. DS20005947B-page 3
MCP33131D/MCP33121D/MCP33111D-XX
1.0 KEY ELECTRICAL
CHARACTERISTICS
1.1 Absolute Maximum Ratings†
External Analog Supply Voltage (AVDD)............. -0.3V to 2.0V
External Digital Supply Voltage (DVIO)............... -0.3V to 5.8V
External Reference Voltage (VREF).................... -0.3V to 5.8V
Analog Inputs w.r.t GND ............... .......... -0.3V to VREF+0.3V
Current at Input Pins ....................................................±2 mA
Current at Output and Supply Pins ..........................±250 mA
Storage Temperature ....................................-65°C to +150°C
Maximum Junction Temperature (TJ). .........................+150°C
ESD protection on all pins .... ≤2kV HBM, ≤200V MM, ≤2kV CDM
†Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
1.2 Electrical Specifications
TABLE 1-1: KEY ELECTRICAL CHARACTERISTICS
Electrical Specifications: Unless otherwise specified, all parameters apply for TA= -40°C to +125°C, AVDD =1.8V, DV
IO =3.3V, V
REF =5V,
GND = 0V, Differential Analog Input (VIN) = -1 dBFS sine wave, fIN =10kHz, C
LOAD_SDO =20pF
• MCP331x1D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
• MCP331x1D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
Parameters Sym. Min. Typ. Max. Units Conditions
Power Supply Requirements
Analog Supply Voltage Range AVDD 1.7 1.8 1.9 V (Note 3)
Digital Input/Output Interface Voltage
Range
DVIO 1.7 — 5.5 V (Note 3)
Analog Supply Current at AVDD pin:
During Conversion
During Standby
IDDAN
IDDAN_STBY
—
—
—
1.6
1.4
0.8
2.4
2.0
—
mA
mA
µA
fs = 1 Msps (MCP331x1D-10)
fs = 500 kSPS (MCP331x1D-05)
During input acquisition (tACQ)
Digital Supply Current At DVDD pin:
During Output Data Reading
During Standby
IIO_DATA
IIO_STBY
—
—
—
290
200
30
—
—
—
A
A
nA
fs = 1 Msps (MCP331x1D-10)
fs = 500 kSPS (MCP331x1D-05)
During input acquisition (tACQ)
External Reference Voltage Input
Reference Voltage
(Note 2), (Note 3)
VREF 2.5
2.7
5.1
5.1
V-40°C ≤TA≤ 85°C
85°C < TA≤ 125°C
Reference Load Current at VREF pin:
During Conversion
During Standby
IREF
IREF_STBY
—
—
450
220
240
600
360
—
µA
µA
nA
fs = 1 Msps (MCP331x1D-10)
fs = 500 kSPS (MCP331x1D-05)
During input acquisition (tACQ)
Total Power Consumption (Including AVDD, DVIO, VREF pins)
MCP331x1D-10
at 1 Msps
at 500 kSPS
at 100 kSPS
During Standby
PDISS_TOTAL
PDISS_STBY
—
—
—
—
6.2
3.1
0.6
2.6
—
—
—
—
mW
mW
mW
W
Averaged power for tACQ + tCNV
During input acquisition (tACQ)
MCP331x1D-05
at 500 kSPS
at 100 kSPS
During Standby
PDISS_TOTAL
PDISS_STBY
—
—
—
4.2
0.8
2.6
—
—
—
mW
mW
W
Averaged power for tACQ + tCNV
During input acquisition (tACQ)
Note 1: This parameter is ensured by design and not 100% tested.
2: This parameter is ensured by characterization and not 100% tested.
3: Decoupling capacitor is recommended on the following pins:
(a) AVDD pin: 1 F ceramic capacitor, (b) DVIO pin: 0.1 F ceramic capacitor, (c) VREF pin: 10 F tantalum capacitor.
4: Differential Input Full-Scale Range (FSR) = 2 x VREF
5: PSRR (dB) = -20 log (DVOUT/AVDD), where DVOUT = change in conversion result.
6: ENOB = (SINAD - 1.76)/6.02
DS20005947B-page 4 2018 Microchip Technology Inc.
MCP33131D/MCP33121D/MCP33111D-XX
Analog Inputs
Input Voltage Range
(Note 2)
VIN+ -0.1 — VREF+0.1 V Differential Input:
VIN = (VIN+ - VIN-)
VIN- -0.1 — VREF+0.1 V
Input Full-Scale Voltage Range FSR -VREF —+V
REF VPP Differential Input (Note 2), (Note 4)
Input Common-Mode Voltage Range VCM 0V
REF/2 VREF (Note 2)
Input Sampling Capacitance CS—31—pF(Note 1)
-3dB Input Bandwidth BW-3dB —25—MHz
(Note 1)
Aperture Delay
(Note 1)
— 2.5 — ns Time delay between CNVST rising
edge and when input is sampled
Leakage Current at Analog Input Pin ILEAK_AN_INPUT — ±2 ±200 nA During input acquisition (tACQ)
System Performance
Sample Rate
(Throughput rate)
fs— — 1 Msps MCP331x1D-10
— — 500 kSPS MCP331x1D-05
Resolution
(No Missing Codes)
16 — — Bits MCP33131D-10 and MCP33131D-05
14 — — Bits MCP33121D-10 and MCP33121D-05
12 — — Bits MCP33111D-10 and MCP33111D-05
Integral Nonlinearity INL -6 ±2 +6 LSB MCP33131D-10 and MCP33131D-05
-1.5 ±0.5 +1.5 LSB MCP33121D-10 and MCP33121D-05
±0.12 LSB MCP33111D-10 and MCP33111D-05
Differential Nonlinearity DNL -0.98 ±0.8 +1.8 LSB MCP33131D-10 and MCP33131D-05
-0.8 ±0.25 +0.8 LSB MCP33121D-10 and MCP33121D-05
-0.3 ±0.06 +0.3 LSB MCP33111D-10 and MCP33111D-05
Offset Error ±0.1 ±2.3 mV MCP33131D-10 and MCP33131D-05
— ±0.125 ±3 mV MCP33121D-10 and MCP33121D-05
—±0.8 ±3.66 mV MCP33111D-10 and MCP33111D-05
Offset Error Drift with Temperature — ±0.8 — V/oC
Gain Error GER —±2 —LSB MCP33131D-10 and MCP33131D-05
— ±0.5 — LSB MCP33121D-10 and MCP33121D-05
—±0.1 —LSB MCP33111D-10 and MCP33111D-05
Gain Error Drift with temperature — ±0.35 — V/oC
Input common-mode rejection ratio CMRR — 84 — dB
Power Supply Rejection Ratio PSRR — 70 — dB (Note 5)
TABLE 1-1: KEY ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise specified, all parameters apply for TA= -40°C to +125°C, AVDD =1.8V, DV
IO =3.3V, V
REF =5V,
GND = 0V, Differential Analog Input (VIN) = -1 dBFS sine wave, fIN =10kHz, C
LOAD_SDO =20pF
• MCP331x1D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
• MCP331x1D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
Parameters Sym. Min. Typ. Max. Units Conditions
Note 1: This parameter is ensured by design and not 100% tested.
2: This parameter is ensured by characterization and not 100% tested.
3: Decoupling capacitor is recommended on the following pins:
(a) AVDD pin: 1 F ceramic capacitor, (b) DVIO pin: 0.1 F ceramic capacitor, (c) VREF pin: 10 F tantalum capacitor.
4: Differential Input Full-Scale Range (FSR) = 2 x VREF
5: PSRR (dB) = -20 log (DVOUT/AVDD), where DVOUT = change in conversion result.
6: ENOB = (SINAD - 1.76)/6.02
2018 Microchip Technology Inc. DS20005947B-page 5
MCP33131D/MCP33121D/MCP33111D-XX
Dynamic Performance
Signal-to-Noise Ratio SNR MCP33131D-10 and MCP33131D-05: 16-bit ADC
— 91.6 — dBFS VREF = 5V, fIN = 1 kHz
— 86.6 — VREF = 2.5V, fIN = 1 kHz
88.7 91.3 — VREF = 5V, fIN = 10 kHz
— 86.6 — VREF = 2.5V, fIN = 10 kHz
MCP33121D-10 and MCP33121D-05: 14-bit ADC
— 85.2 — dBFS VREF = 5V, fIN = 1 kHz
— 83.5 — VREF = 2.5V, fIN = 1 kHz
81.7 85.1 — VREF = 5V, fIN = 10 kHz
— 83.5 — VREF = 2.5V, fIN = 10 kHz
MCP33111D-10 and MCP33111D-05: 12-bit ADC
— 73.9 — dBFS VREF = 5V, fIN = 1 kHz
— 73.8 — VREF = 2.5V, fIN = 1 kHz
71.1 73.9 — VREF = 5V, fIN = 10 kHz
— 73.8 — VREF = 2.5V, fIN = 10 kHz
Signal-to-Noise and Distortion Ratio
(Note 6)
SINAD MCP33131D-10 and MCP33131D-05: 16-bit ADC
— 91.5 — dBFS VREF = 5V, fIN = 1 kHz
— 86.6 — VREF = 2.5V, fIN = 1 kHz
—91— V
REF = 5V, fIN = 10 kHz
— 86.2 — VREF = 2.5V, fIN = 10 kHz
MCP33121D-10 and MCP33121D-05: 14-bit ADC
— 85.2 — dBFS VREF = 5V, fIN = 1 kHz
— 83.5 — VREF = 2.5V, fIN = 1 kHz
—85— V
REF = 5V, fIN = 10 kHz
— 83.3 — VREF = 2.5V, fIN = 10 kHz
MCP33111D-10 and MCP33111D-05: 12-bit ADC
— 73.9 — dBFS VREF = 5V, fIN = 1 kHz
— 73.8 — VREF = 2.5V, fIN = 1 kHz
— 73.9 — VREF = 5V, fIN = 10 kHz
— 73.8 — VREF = 2.5V, fIN = 10 kHz
TABLE 1-1: KEY ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise specified, all parameters apply for TA= -40°C to +125°C, AVDD =1.8V, DV
IO =3.3V, V
REF =5V,
GND = 0V, Differential Analog Input (VIN) = -1 dBFS sine wave, fIN =10kHz, C
LOAD_SDO =20pF
• MCP331x1D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
• MCP331x1D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
Parameters Sym. Min. Typ. Max. Units Conditions
Note 1: This parameter is ensured by design and not 100% tested.
2: This parameter is ensured by characterization and not 100% tested.
3: Decoupling capacitor is recommended on the following pins:
(a) AVDD pin: 1 F ceramic capacitor, (b) DVIO pin: 0.1 F ceramic capacitor, (c) VREF pin: 10 F tantalum capacitor.
4: Differential Input Full-Scale Range (FSR) = 2 x VREF
5: PSRR (dB) = -20 log (DVOUT/AVDD), where DVOUT = change in conversion result.
6: ENOB = (SINAD - 1.76)/6.02
DS20005947B-page 6 2018 Microchip Technology Inc.
MCP33131D/MCP33121D/MCP33111D-XX
Spurious Free Dynamic Range SFDR MCP33131D-10 and MCP33131D-05: 16-bit ADC
— 103.7 — dBc VREF = 5V, fIN = 1 kHz
—98— V
REF = 2.5V, fIN = 1 kHz
— 103.5 — VREF = 5V, fIN = 10 kHz
— 97.5 — VREF = 2.5V, fIN = 10 kHz
MCP33121D-10 and MCP33121D-05: 14-bit ADC
— 103.6 — dBc VREF = 5V, fIN = 1 kHz
—98— V
REF = 2.5V, fIN = 1 kHz
— 103.5 — VREF = 5V, fIN = 10 kHz
— 97.4 — VREF = 2.5V, fIN = 10 kHz
MCP33111D-10 and MCP33111D-05: 12-bit ADC
— 99.3 — dBc VREF = 5V, fIN = 1 kHz
— 97.7 — VREF = 2.5V, fIN = 1 kHz
— 99.3 — VREF = 5V, fIN = 10 kHz
— 97.2 — VREF = 2.5V, fIN = 10 kHz
Total Harmonic Distortion
(first five harmonics)
THD MCP33131D-10 and MCP33131D-05: 16-bit ADC
— -100.4 — dBc VREF = 5V, fIN = 1 kHz
— -95.4 — VREF = 2.5V, fIN = 1 kHz
— -99.3 — VREF = 5V, fIN = 10 kHz
— -95.4 — VREF = 2.5V, fIN = 10 kHz
MCP33121D-10 and MCP33121D-05: 14-bit ADC
— -100.1 — dBc VREF = 5V, fIN = 1 kHz
— -95.3 — VREF = 2.5V, fIN = 1 kHz
— -99.2 — VREF = 5V, fIN = 10 kHz
— -95.3 — VREF = 2.5V, fIN = 10 kHz
MCP33111D-10 and MCP33111D-05: 12-bit ADC
— -97.5 — dBc VREF = 5V, fIN = 1 kHz
— -94.4 — VREF = 2.5V, fIN = 1 kHz
— -96.7 — VREF = 5V, fIN = 10 kHz
— -94.4 — VREF = 2.5V, fIN = 10 kHz
TABLE 1-1: KEY ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise specified, all parameters apply for TA= -40°C to +125°C, AVDD =1.8V, DV
IO =3.3V, V
REF =5V,
GND = 0V, Differential Analog Input (VIN) = -1 dBFS sine wave, fIN =10kHz, C
LOAD_SDO =20pF
• MCP331x1D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
• MCP331x1D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
Parameters Sym. Min. Typ. Max. Units Conditions
Note 1: This parameter is ensured by design and not 100% tested.
2: This parameter is ensured by characterization and not 100% tested.
3: Decoupling capacitor is recommended on the following pins:
(a) AVDD pin: 1 F ceramic capacitor, (b) DVIO pin: 0.1 F ceramic capacitor, (c) VREF pin: 10 F tantalum capacitor.
4: Differential Input Full-Scale Range (FSR) = 2 x VREF
5: PSRR (dB) = -20 log (DVOUT/AVDD), where DVOUT = change in conversion result.
6: ENOB = (SINAD - 1.76)/6.02
2018 Microchip Technology Inc. DS20005947B-page 7
MCP33131D/MCP33121D/MCP33111D-XX
System Self-Calibration
Self-Calibration Time tCAL — 500 650 ms (Note 2)
Number of SCLK Clocks for
Recalibrate Command
ReCalNSCLK — 1024 — clocks Includes clocks for data bits
Serial Interface Timing Information: See Table 1-2
Digital Inputs/Outputs
High-level Input voltage VIH 0.7 * DVIO —DV
IO + 0.3 V DVIO ≥2.3V
0.9 * DVIO —DV
IO + 0.3 V DVIO <2.3V
Low-level input voltage VIL -0.3 — 0.3 * DVIO VDV
IO ≥2.3V
-0.3 — 0.2 * DVIO VDV
IO <2.3V
Hysteresis of Schmitt Trigger Inputs VHYST —0.2 * DV
IO — V All digital inputs
Low-level output voltage VOL — — 0.2 * DVIO VI
OL = 500 µA (sink)
High-level output voltage VOH 0.8 * DVIO — —VI
OL = - 500 µA (source)
Input leakage current ILI — — ±1 µA CNVST/SDI/SCLK = GND or DVIO
Output leakage current ILO — — ±1 µA Output is high-Z, SDO = GND or
DVIO
Internal capacitance
(all digital inputs and outputs)
CINT —7—pFT
A = 25°C (Note 1)
TABLE 1-1: KEY ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise specified, all parameters apply for TA= -40°C to +125°C, AVDD =1.8V, DV
IO =3.3V, V
REF =5V,
GND = 0V, Differential Analog Input (VIN) = -1 dBFS sine wave, fIN =10kHz, C
LOAD_SDO =20pF
• MCP331x1D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
• MCP331x1D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
Parameters Sym. Min. Typ. Max. Units Conditions
Note 1: This parameter is ensured by design and not 100% tested.
2: This parameter is ensured by characterization and not 100% tested.
3: Decoupling capacitor is recommended on the following pins:
(a) AVDD pin: 1 F ceramic capacitor, (b) DVIO pin: 0.1 F ceramic capacitor, (c) VREF pin: 10 F tantalum capacitor.
4: Differential Input Full-Scale Range (FSR) = 2 x VREF
5: PSRR (dB) = -20 log (DVOUT/AVDD), where DVOUT = change in conversion result.
6: ENOB = (SINAD - 1.76)/6.02
DS20005947B-page 8 2018 Microchip Technology Inc.
MCP33131D/MCP33121D/MCP33111D-XX
TABLE 1-2: SERIAL INTERFACE TIMING SPECIFICATIONS
TABLE 1-3: TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise specified, all parameters apply for TA= -40°C to +125°C, AVDD =1.8V, DV
IO =3.3V, V
REF =5V,
GND = 0V, Differential Analog Input (VIN) = -1 dBFS sine wave, fIN =10kHz, C
LOAD_SDO = 20 pF. +25°C is applied for typical value. All timings are
measured at 50%. See Figure 1-1 for timing diagram.
• MCP331x1D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
• MCP331x1D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
Parameters Symbol Min. Typ. Max. Units Conditions
Serial Clock frequency fSCLK — — 100 MHz See tSCLK specification
SCLK Period tSCLK 10 — — ns DVIO ≥ 3.3V, fSCLK = 100 MHz (Max)
12 — — ns DVIO ≥ 2.3V, fSCLK = 83.3 MHz (Max)
16 — — ns DVIO ≥ 1.7V, fSCLK = 62.5 MHz (Max)
SCLK Low Time tSCLK_L 3— —ns
DVIO ≥ 2.3V
4.5 — — ns DVIO ≥ 1.7V
SCLK High Time tSCLK_H 3— —ns
DVIO ≥ 2.3V
4.5 — — ns DVIO ≥ 1.7V
Output Valid from SCLK Low tDO —— 9.5nsDV
IO ≥ 3.3V
—— 12nsDV
IO ≥ 2.3V
—— 16nsDV
IO ≥ 1.7V
Quiet time tQUIET 10 — — ns (Note 2)
3-Wire Operation:
SDI Valid Setup time tSU_SDIH_CNV 5 — — ns SDI High to CNVST Rising Edge
CNVST Pulse Width High Time tCNVH 10 — — ns
Output Enable Time tEN —— 10nsDV
IO ≥ 2.3V
—— 15nsDV
IO ≥ 1.7V
Output Disable Time tDIS —— 15ns(Note 2)
MCP331x1D-10
Sample Rate fs— — 1 Msps Throughput rate
Input Acquisition Time
(Note 2)
tACQ 290
250
300 —
—
ns -40°C ≤TA≤ 85°C
85°C < TA≤ 125°C
Data Conversion Time tCNV —
—
700 710
750
ns -40°C ≤TA≤ 85°C
85°C < TA≤ 125°C
Time between Conversions tCYC 1— —µst
CYC = tACQ + tCNV, fS = 1 Msps
MCP331x1D-05
Sample Rate fs— — 500 kSPS Throughput rate
Input Acquisition Time (Note 2) tACQ 700 800 — ns -40°C ≤TA≤ 125°C
Data Conversion Time tCNV — 1200 1300 ns -40°C ≤TA≤ 125°C
Time between Conversions tCYC 2— —µst
CYC = tACQ + tCNV, fS = 500 kSPS
Note 1: This parameter is ensured by design and not 100% tested.
2: This parameter is ensured by characterization and not 100% tested.
Parameters Symbol Min. Typ. Max. Units Conditions
Temperature Ranges
Operating Temperature Range TA-40 — +125 °C (Note 1)
Storage Temperature Range TA-65 — +150 °C (Note 1)
Thermal Package Resistance
Thermal Resistance, MSOP-10 JA — 202 — °C/W
Thermal Resistance, TDFN-10 JA —68—°C/W
Note 1: The internal junction temperature (Tj) must not exceed the absolute maximum specification of +150oC.
2018 Microchip Technology Inc. DS20005947B-page 9
MCP33131D/MCP33121D/MCP33111D-XX
FIGURE 1-1: Interface Timing Diagram. CNVST is used as chip select. See Figure 7-2 for more
details.
CNVST
SDO
SCLK 123n-1 n
Dn-1 Dn-2 Dn-3 D1D0
ADC State
(MSB)
Hi-Z Hi-Z
tCNVH
tCNV (MAX)
tSCLK
tSCLK_L tSCLK_H
tDO
tDIS
Conversion
2: tEN when CNVST is lowered after tCNV (MAX).
Input Acquisition
Input Acquisition
(tCNV)(tACQ)
(tACQ)
tCYC
SDI = “High”
tSU_SDIH_CNV
tEN
tQUIET
tEN
3: tEN when CNVST is lowered before tCNV (MAX).
= 1/fS
(Note 2)
(Note 3)
(Note 1)
Note 1: n = 16 for 16-bit, 14 for 14-bit device, and 12 for 12-bit device.
DS20005947B-page 10 2018 Microchip Technology Inc.
MCP33131D/MCP33121D/MCP33111D-XX
NOTES:
2017 Microchip Technology Inc. DS20005947B-page 11
MCP33131D/MCP33121D/MCP33111D-XX
2.0 TYPICAL PERFORMANCE CURVES FOR 16-BIT DEVICES (MCP33131D-XX)
Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33131D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33131D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
FIGURE 2-1: INL vs. Output Code.
FIGURE 2-2: DNL vs. Output Code.
FIGURE 2-3: INL vs. Temperature.
FIGURE 2-4: INL vs. Output Code.
FIGURE 2-5: DNL vs. Output Code.
FIGURE 2-6: DNL vs. Temperature.
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
0 16,384 32,768 49,152 65,536
Code
-2
-1
0
1
2
INL (LSB)
V
REF
= 5V
0 16,384 32,768 49,152 65,536
Code
-1
-0.5
0
0.5
1
DNL (LSB)
V
REF
= 5V
-40 -20 0 20 40 60 80 100 120 140
Temperature (oC)
-3
-2
-1
0
1
2
3
INL (LSB)
VREF = 5V
Max INL (LSB)
Min INL (LSB)
0 16,384 32,768 49,152 65,536
Code
-3
-2
-1
0
1
2
3
INL (LSB)
V
REF
= 2.5V
0 16,384 32,768 49,152 65,536
Code
-1
-0.5
0
0.5
1
DNL (LSB)
V
REF
= 2.5V
-40 -20 0 20 40 60 80 100 120 140
Temperature (
o
C)
-1
-0.5
0
0.5
1
DNL (LSB)
V
REF
= 5V
Max DNL (LSB)
Min DNL (LSB)
MCP33131D/MCP33121D/MCP33111D-XX
DS20005947B-page 12 2017 Microchip Technology Inc.
Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33131D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33131D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
FIGURE 2-7: INL vs. Reference Voltage.
FIGURE 2-8: FFT for 10 kHz Input Signal:
fS = 1 Msps, VIN = -1 dBFS, VREF = 5V.
FIGURE 2-9: FFT for 10 kHz Input Signal:
fS = 500 kSPS, VIN = -1 dBFS, VREF = 5V.
FIGURE 2-10: DNL vs. Reference Voltage.
FIGURE 2-11: FFT for 10 kHz Input Signal:
fS = 1 Msps, VIN = -1 dBFS, VREF = 2.5V.
FIGURE 2-12: FFT for 10 kHz Input Signal:
fS = 500 kSPS, VIN = -1 dBFS, VREF = 2.5V.
2 2.5 3 3.5 4 4.5 5 5.5
Reference Voltage (V)
-4
-3
-2
-1
0
1
2
3
4
INL (LSB)
Max INL (LSB)
Min INL (LSB)
0 100 200 300 400 500
Frequency (kHz)
-160
-140
-120
-100
-80
-60
-40
-20
0
Amplitude (dBFS)
VREF = 5V
fs = 1 Msps
SNR = 91.5 dBFS
SINAD = 91.3 dBFS
SFDR = 108.5 dBc
THD = -102.2 dBc
Offset = 1 LSB
Resolution = 16-bit
MCP33131D-10
0 50 100 150 200 250
Frequency (kHz)
-160
-140
-120
-100
-80
-60
-40
-20
0
Amplitude (dBFS)
VREF = 5V
fs = 0.5 Msps
SNR = 91.5 dBFS
SINAD = 91.3 dBFS
SFDR = 108.0 dBc
THD = -102.5 dBc
Offset = 1 LSB
Resolution = 16-bit
MCP33131D-05
2 2.5 3 3.5 4 4.5 5 5.5
Reference Voltage (V)
-1
-0.5
0
0.5
1
DNL (LSB)
Min DNL (LSB)
Max DNL (LSB)
0 100 200 300 400 500
Frequency (kHz)
-160
-140
-120
-100
-80
-60
-40
-20
0
Amplitude (dBFS)
VREF = 2.5V
fs = 1 Msps
SNR = 86.7 dBFS
SINAD = 86.2 dBFS
SFDR = 97.4 dBc
THD = -95.6 dBc
Offset = -2 LSB
Resolution = 16-bit
MCP33131D-10
MCP33131D-05
2017 Microchip Technology Inc. DS20005947B-page 13
MCP33131D/MCP33121D/MCP33111D-XX
Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33131D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33131D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
FIGURE 2-13: SNR/SINAD/ENOB vs. VREF
FIGURE 2-14: SNR/SINAD vs.
Temperature: VREF = 5V.
FIGURE 2-15: SNR/SINAD vs. Input
Amplitude: FIN = 10 kHz.
FIGURE 2-16: SFDR/THD vs. VREF
FIGURE 2-17: SNR/SINAD vs.
Temperature: VREF = 2.5V.
FIGURE 2-18: SNR/SINAD vs. Input
Amplitude: FIN = 10 kHz.
2 2.5 3 3.5 4 4.5 5 5.5
Reference Voltage (V)
80
82.5
85
87.5
90
92.5
95
SNR/SINAD (dB)
2 2.5 3 3.5 4 4.5 5 5.5
Reference Voltage (V)
12.5
13.5
14.5
15.5
ENOB (Bits)
ENOB
SNR (dB)
SINAD (dB)
-40 -20 0 20 40 60 80 100 120 140
Temperature (oC)
89.6
89.8
90
90.2
90.4
90.6
SNR/SINAD (dB)
SNR (dB)
SINAD (dB)
VREF = 5V
-30 -25 -20 -15 -10 -5 0
Input Amplitude (dBFS)
85
87
89
91
93
95
SNR/SINAD (dBFS)
SNR (dBFS)
SINAD(dBFS)
VREF = 5V
2 2.5 3 3.5 4 4.5 5 5.5
Reference Voltage (V)
-101
-98
-95
-92
THD (dB)
2 2.5 3 3.5 4 4.5 5 5.5
Reference Voltage (V)
92
97
102
107
SFDR (dB)
THD (dB)
SFDR (dB)
-40 -20 0 20 40 60 80 100 120 140
Temperature (oC)
83
84
85
86
87
SNR/SINAD (dB)
SNR (dB)
SINAD (dB)
VREF = 2.5V
-30 -25 -20 -15 -10 -5 0
Input Amplitude (dBFS)
80
81
82
83
84
85
86
87
88
89
90
SNR/SINAD (dBFS)
SNR (dBFS)
SINAD(dBFS)
V
REF
= 2.5V
MCP33131D/MCP33121D/MCP33111D-XX
DS20005947B-page 14 2017 Microchip Technology Inc.
Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33131D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33131D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
FIGURE 2-19: SNR/SINAD vs.Input
Frequency: VIN = -1 dBFS.
FIGURE 2-20: THD/SFDR vs.
Temperature: VREF = 5V.
FIGURE 2-21: THD/SFDR vs. Input
Frequency: VREF = 5V.
FIGURE 2-22: SNR/SINAD vs.Input
Frequency: VIN = -1 dBFS.
FIGURE 2-23: THD/SFDR vs.
Temperature: VREF = 2.5V.
FIGURE 2-24: THD/SFDR vs. Input
Frequency: VREF = 2.5V.
10
0
10
1
10
2
10
3
Input Frequency (kHz)
70
75
80
85
90
95
SNR/SINAD (dB)
SNR (dB)
SINAD (dB)
V
REF
= 5V
-40 -20 0 20 40 60 80 100 120 140
Temperature (oC)
-102
-100
-98
-96
-94
-92
THD (dB)
THD (dB)
SFDR (dB)
96
98
100
102
104
106
SFDR (dB)
V
REF
= 5V
10
0
10
1
10
2
10
3
Input Frequency (kHz)
-110
-105
-100
-95
-90
-85
-80
-75
THD (dB)
75
80
85
90
95
100
105
110
SFDR (dB)
THD (dB)
SFDR (dB)
V
REF
= 5V
10
0
10
1
10
2
10
3
Input Frequency (kHz)
70
75
80
85
90
95
SNR/SINAD (dB)
SNR (dB)
SINAD (dB)
V
REF
= 2.5V
-40 -20 0 20 40 60 80 100 120 140
Temperature (oC)
-98
-97
-96
-95
-94
-93
-92
THD (dB)
THD (dB)
SFDR (dB)
94
95
96
97
98
99
100
SFDR (dB)
VREF = 2.5V
10
0
10
1
10
2
10
3
Input Frequency (kHz)
-110
-105
-100
-95
-90
-85
-80
-75
THD (dB)
75
80
85
90
95
100
105
110
SFDR (dB)
THD (dB)
SFDR (dB)
V
REF
= 2.5V