TL/F/5300
MM54HC27/MM74HC27 Triple 3-Input NOR Gate
January 1988
MM54HC27/MM74HC27
Triple 3-Input NOR Gate
General Description
These NOR gates utilize advanced silicon-gate CMOS tech-
nology, to achieve operating speeds similar to LS-TTL gates
with the low power consumption of standard CMOS inte-
grated circuits. All gates have buffered outputs, providing
high noise immunity and the ability to drive 10 LS-TTL loads.
The 54HC/74HC logic family is functionally as well as pin-
out compatible with the standard 54LS/74LS logic family.
All inputs are protected from damage due to static dis-
charge by internal diode clamps to VCC and ground.
Features
YTypical propagation delay: 8 ns
YWide operating supply voltage range: 26V
YLow input current: k1mA
YLow quiescent supply current: 20 mA maximum
(74HC Series)
YFanout of 10 LS-TTL Loads
Connection and Logic Diagrams
Dual-In-Line Package
TL/F/53001
Top View
Order Number MM54HC27 or MM74HC27
TL/F/5300 2
C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.
Absolute Maximum Ratings (Notes1&2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (VCC)b0.5 to a7.0V
DC Input Voltage (VIN)b1.5 to VCCa1.5V
DC Output Voltage (VOUT)b0.5 to VCCa0.5V
Clamp Diode Current (IIK,I
OK)g20 mA
DC Output Current, per pin (IOUT)g25 mA
DC VCC or GND Current, per pin (ICC)g50 mA
Storage Temperature Range (TSTG)b65§Ctoa
150§C
Power Dissipation (PD)
(Note 3) 600 mW
S.O. Package only 500 mW
Lead Temperature (TL)
(Soldering 10 seconds) 260§C
Operating Conditions
Min Max Units
Supply Voltage (VCC)26V
DC Input or Output Voltage 0 VCC V
(VIN,VOUT)
Operating Temp. Range (TA)
MM74HC b40 a85 §C
MM54HC b55 a125 §C
Input Rise or Fall Times
VCCe2.0V(tr,t
f
) 1000 ns
VCCe4.5V 500 ns
VCCe6.0V 400 ns
DC Electrical Characteristics (Note 4)
TAe25§C74HC 54HC
Symbol Parameter Conditions VCC TAeb40 to 85§CT
A
eb55 to 125§CUnits
Typ Guaranteed Limits
VIH Minimum High Level 2.0V 1.5 1.5 1.5 V
Input Voltage 4.5V 3.15 3.15 3.15 V
6.0V 4.2 4.2 4.2 V
VIL Maximum Low Level 2.0V 0.5 0.5 0.5 V
Input Voltage** 4.5V 1.35 1.35 1.35 V
6.0V 1.8 1.8 1.8 V
VOH Minimum High Level VINeVIL
Output Voltage
l
IOUT
l
s20 mA 2.0V 2.0 1.9 1.9 1.9 V
4.5V 4.5 4.4 4.4 4.4 V
6.0V 6.0 5.9 5.9 5.9 V
VINeVIL
l
IOUT
l
s4.0 mA 4.5V 4.2 3.98 3.84 3.7 V
l
IOUT
l
s5.2 mA 6.0V 5.7 5.48 5.34 5.2 V
VOL Maximum Low Level VINeVIH or VIL
Output Voltage
l
IOUT
l
s20 mA 2.0V 0 0.1 0.1 0.1 V
4.5V 0 0.1 0.1 0.1 V
6.0V 0 0.1 0.1 0.1 V
VINeVIH or VIL
l
IOUT
l
s4.0 mA 4.5V 0.2 0.26 0.33 0.4 V
l
IOUT
l
s5.2 mA 6.0V 0.2 0.26 0.33 0.4 V
IIN Maximum Input VINeVCC or GND 6.0V g0.1 g1.0 g1.0 mA
Current
ICC Maximum Quiescent VINeVCC or GND 6.0V 2.0 20 40 mA
Supply Current IOUTe0mA
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package: b12 mW/§C from 65§Cto85
§
C; ceramic ‘‘J’’ package: b12 mW/§C from 100§Cto125
§
C.
Note 4: For a power supply of 5V g10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing
with this supply. Worst case VIH and VIL occur at VCCe5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN,I
CC, and
IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
**VIL limits are currently tested at 20% of VCC. The above VIL specification (30% of VCC) will be implemented no later than Q1, CY’89.
2
AC Electrical Characteristics VCCe5V, TAe25§C, CLe15 pF, tretfe6ns
Symbol Parameter Conditions Typ Guaranteed Units
Limit
tPHL,t
PLH Maximum Propagation 8 15 ns
Delay
AC Electrical Characteristics VCCe2.0V to 6.0V, CLe50 pF, tretfe6 ns (unless otherwise specified)
TAe25§C74HC 54HC
Symbol Parameter Conditions VCC TAeb40 to 85§CT
A
eb55 to 125§CUnits
Typ Guaranteed Limits
tPHL,t
PLH Maximum Propagation 2.0V 45 90 113 134 ns
Delay 4.5V 9 18 23 27 ns
6.0V 8 15 19 23 ns
tTLH,t
THL Maximum Output Rise 2.0V 30 75 95 110 ns
and Fall Time 4.5V 8 15 19 22 ns
6.0V 7 13 16 19 ns
CPD Power Dissipation (per gate) 36 pF
Capacitance (Note 5)
CIN Maximum Input 5 10 10 10 pF
Capacitance
Note 5: CPD determines the no load dynamic power consumption, PDeCPD VCC2faICC VCC, and the no load dynamic current consumption, ISeCPD VCC faICC.
Physical Dimensions inches (millimeters)
Order Number MM54HC27J or MM74HC27J
NS Package Number J14A
3
MM54HC27/MM74HC27 Triple 3-Input NOR Gate
Physical Dimensions inches (millimeters) (Continued)
Order Number MM74HC27N
NS Package Number N14A
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