1
FN7311.10
EL5172, EL5372
250MHz Differential Line Receivers
The EL5172 and EL5372 are single and triple high
bandwidth amplifiers designed to extract the difference
signal from noisy environments. They are primarily targeted
for applications such as receiving signa ls from twisted-pair
lines or any application where common mode noise injection
is likely to occur.
The EL5172 and EL5372 are stable for a gain of one and
requires two external resistors to set the voltage gain.
The output common mode level is set by the refe rence pin
(VREF), which has a -3dB bandwidth of over 120MHz.
Generally, this pin is grounded but it can be tied to any
voltage reference.
The output can deliver a maximum of ±60mA and is shor t
circuit protected to withstand a temporary overload
condition.
The EL5172 is availa ble in the 8 Ld SOIC and 8 Ld MSOP
packages and the EL5372 in a 24 Ld QSOP package. Both
are specified for operation over the full -40°C to +85°C
temperature range.
Features
• Differential input range ±2.3V
• 250MHz 3dB ban dwi dth
• 800V/µs slew rate
• 60mA maximum output current
• Single 5V or dual ±5V supplies
• Low power - 5mA to 6mA per channel
• Pb-free available (RoHS co mpliant)
Applications
• Twisted-pair receivers
• Differential line receivers
• VGA over twisted-pair
• ADSL/HDSL receivers
• Differential to single-ended amplification
• Reception of analog signals in a noisy en vironment
Pinouts
EL5172
(8 LD SOIC, MSOP)
TOP VIEW
EL5372
(24 LD QSOP)
TOP VIEW
1
2
3
4
8
7
6
5
OUT
VS-
VS+
EN
FB
IN+
IN-
REF
-
+
1
2
3
4
16
15
14
13
5
6
7
12
11
9
8
10
20
19
18
17
24
23
22
21
REF1
INP1
INN1
NC
REF2
INP2
INN2
NC
REF3
INP3
INN3
NC
NC
FB1
OUT1
NC
VSP
VSN
NC
FB2
OUT2
EN
FB3
OUT3
-
+
-
+
-
+
Data Sheet September 4, 2012
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002-2005, 2010, 2012. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
2FN7311.10
September 4, 2012
Ordering Information
PART
NUMBER PART
MARKING PACKAGE PKG.
DWG. #
EL5172IS 5172IS 8 Ld SOIC (150 mil) M8.15E
EL5172IS-T13* 5172IS 8 Ld SOIC (150 mil) M8.15E
EL5172ISZ
(Note) 5172ISZ 8 Ld SOIC (150 mil) (Pb-free) M8.15E
EL5172ISZ-T7*
(Note) 5172ISZ 8 Ld SOIC (150 mil) (Pb-free) M8.15E
EL5172ISZ-T13*
(Note) 5172ISZ 8 Ld SOIC (150 mil) (Pb-free) M8.15E
EL5172IY-T7* h 8 Ld MSOP (3.0mm) M8.118A
EL5172IYZ
(Note) BAAWA 8 Ld MSOP (3.0mm) (Pb-free) M8.118A
EL5172IYZ-T7*
(Note) BAAWA 8 Ld MSOP (3.0mm) (Pb-free) M8.118A
EL5172IYZ-T13*
(Note) BAAWA 8 Ld MSOP (3.0mm) (Pb-free) M8.118A
EL5372IUZ
(Note) EL5372IUZ 24 Ld QSOP (150 mil) (Pb-free) MDP0040
EL5372IUZ-T7*
(Note) EL5372IUZ 24 Ld QSOP (150 mil) (Pb-free) MDP0040
EL5372IUZ-T13*
(Note) EL5372IUZ 24 Ld QSOP (150 mil) (Pb-free) MDP0040
*Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die atta ch materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations).
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.
EL5172, EL5372
3FN7311.10
September 4, 2012
IMPORTANT NOTE: All parameters having Min/Max specifications are guarant eed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Absolute Maximum Ratings (TA = +25°C) Thermal Information
Supply Voltage (VS+ to VS-) . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V
Supply Voltage Rate-of-rise (dV/d T) . . . . . . . . . . . . . . . . . . . . 1V/µs
Input Voltage (IN+, IN- to VS+, VS-). . . . . . VS- - 0.3V to VS+ + 0.3V
Differential Input Voltage (IN+ to IN-). . . . . . . . . . . . . . . . . . . . ±4.8V
Maximum Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . ±60mA
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . .+135°C
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product relia bility and
result in failures not covered by warranty.
Electrical Specifications VS+ = +5V, VS- = -5V, TA = +25°C, VIN = 0V, RL = 500, RF = 0, RG = OPEN, CL = 2.7pF, Unless Otherwise
Specified.
PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT
AC PERFORMANCE
BW -3dB Bandwidth AV =1, CL = 2.7pF 250 MHz
AV =2, RF = 1000, CL = 2.7pF 70 MHz
AV =10, RF = 1000, CL = 2.7pF 10 MHz
BW ±0.1dB Bandwidth AV =1, CL = 2.7pF 25 MHz
SR Slew Rate VOUT = 3VP-P, 20% to 80%, EL5172 550 800 1000 V/µs
VOUT = 3VP-P, 20% to 80%, EL5372 550 700 1000 V/µs
tSTL Settling Time to 0.1% VOUT = 2VP-P 10 ns
tOVR Output Overdrive Recovery Time 20 ns
GBWP Gain Bandwidth Product 100 MHz
VREFBW (-3dB) VREF -3dB Bandwidth AV =1, CL = 2.7pF 120 MHz
VREFSR VREF Slew Rate VOUT = 2VP-P, 20% to 80% 600 V/µs
VNInput Voltage Noise at f = 11kHz 26 nV/Hz
INInput Current Noise at f = 11kHz 2 pA/Hz
HD2 Second Harmonic Distortion VOUT = 1VP-P, 5MHz -66 dBc
VOUT = 2VP-P, 50MHz -63 dBc
HD3 Third Harmonic Distortion VOUT = 1VP-P, 5MHz -84 dBc
VOUT = 2VP-P, 50MHz -76 dBc
dG Differential Gain at 3.58MHz RL = 150AV = 2 0.04 %
dDifferential Phase at 3.58MHz RL = 150AV = 2 0.41 °
eSChannel Separation at 100kHz EL5372 only 90 dB
INPUT CHARACTERISTICS
VOS Input Referred Offset Voltage ±7 ±25 mV
IIN Input Bias Current (VIN, VINB, VREF)-14-6-3µA
RIN Differential Input Resistance 300 k
CIN Differential Input Capacitance 1pF
DMIR Differential Input Range ±2.1 ±2.38 ±2.5 V
CMIR+ Common Mode Po sitive Input Range at VIN+, VIN-3.33.5V
CMIR- Common Mode Po sitive Input Range at VIN+, VIN- -4.5 -4.3
VREFIN+ Reference Input Positive Voltage Range VIN+ = VIN- = 0V 3.3 3.7 V
EL5172, EL5372
4FN7311.10
September 4, 2012
VREFIN- Reference Input Negative Voltage Range VIN+ = VIN- = 0V -3.9 -3.6
CMRR Input Common Mode Rejection Ratio VIN = ±2.5V 75 95 dB
Gain Gain Accuracy VIN = 1 0.985 1 1.015 V
OUTPUT CHARACTERISTICS
VOUT Positive Output Voltage Swing RL = 500 to GND 3.3 3.63 V
Negative Output Voltage Swing RL = 500 to GND -3.87 -3.5 V
IOUT(Max) Maximum Output Current RL = 10±60 ±95 mA
ROUT Output Impedance 100 m
SUPPLY
VSUPPLY Supply Operating Range VS+ to VS-4.7511V
IS (on) Power Supply Current Per Chann el - E nabled 4.6 5.6 7 mA
IS (off)+ Positive Power Supply Current - Disabled EN pin tied to 4.8V, EL5172 80 100 µA
EN pin tied to 4.8V, EL5372 1.7 5 µA
IS (off)- Negative Power Supply Current - Disabled -150 -120 -90 µA
PSRR Power Supply Rejection Ratio VS from ±4.5V to ±5.5V 50 58 dB
ENABLE
tEN Enable Time 150 ns
tDS Disable Time 1.4 µs
VIH EN Pin Voltage for Power-up VS+ - 1.5 V
VIL EN Pin Voltage for Shutdown VS+ - 0.5 V
IIH-EN EN Pin Input Current High Per Channel At VEN = 5V 40 60 µA
IIL-EN EN Pin Input Current Low Per Channel At VEN = 0V -10 -3 µA
Electrical Specifications VS+ = +5V, VS- = -5V, TA = +25°C, VIN = 0V, RL = 500, RF = 0, RG = OPEN, CL = 2.7pF, Unless Otherwise
Specified. (Continued)
PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT
EL5172, EL5372
5FN7311.10
September 4, 2012
Pin Descriptions
EL5172 EL5372 PIN NAME PIN FUNCTION
1 FB Feedback input
2 IN+ Non-inverting input
3 IN- Inverting input
4 REF Sets the common mode output voltage level
5EN
Enabled when this pin is floating or the applied voltage VS+ - 1.5
6 VS+ Positive supply voltage
7 VS- Negative supply voltage
8 OUT Output voltage
1, 5, 9 REF1, REF2, REF3 Reference input, controls common-mode output voltage
2, 6, 10 INP1, INP2, INP3 Non-inverting inputs
3, 7, 11 INN1, INN2, INN3 Inverting inputs
4, 8, 12, 18, 21, 24 NC No connect; grounded for best crosstalk performance
13, 16, 22 OUT3, OUT2, OUT1 Non-inverting outputs
14, 17, 23 FB3, FB2, FB1 Feedback from outputs
15 EN Enabled when this pin is floating or the applied voltage VS+ - 1.5
19 VSN Negative supply
20 VSP Positive supply
EL5172, EL5372
6FN7311.10
September 4, 2012
Typical Performance Curves
FIGURE 1. FREQUENCY RESPONSE vs SUPPLY VOLTAGE FIGURE 2. FREQUENCY RESPONSE vs SUPPLY VOLTAGE
FIGURE 3. FREQUENCY RESPONSE vs VARIOUS GAIN FIGURE 4. FREQUENCY RESPONSE vs CL
FIGURE 5. FREQUENCY RESPONSE vs CLFIGURE 6. FREQUENCY RESPONSE FOR VARIOUS RF
4
3
1
0
-2
-3
-5
-6 10M 100M 1G
MAGNITUDE (dB)
FREQUENCY (Hz)
-4
-1
2
1M
VS = ±5V
VS = ±2.5V
AV = 1, RL = 500, CL = 2.7pF
4
3
1
0
-2
-3
-5
-6 10M 100M 1G
FREQUENCY (Hz)
-4
-1
2
1M
VS = ±5V
VS = ±2.5V
MAGNITUDE (dB)
AV = 1, RL = 100, CL = 2.7pF
4
3
1
0
-2
-3
-5
-6 10M 100M 1G
NORMALIZED GAIN (dB)
FREQUENCY (Hz)
-4
-1
2
1M
AV = 1
AV = 2
AV = 5
AV = 10
VS = ±5V, RL = 500, CL = 2.7pF
5
4
2
1
-1
-2
-4
-5 10M 100M 1G
FREQUENCY (Hz)
-3
0
3
1M
MAGNITUDE (dB)
VS = ±5V, AV = 1, RL = 500
CL = 56pF
CL = 33pF
CL = 15pF
CL = 10pF
CL = 2.7pF
10M 100M 1G
FREQUENCY (Hz)
1M
MAGNITUDE (dB)
5
4
2
1
-1
-2
-4
-5
-3
0
3
VS = ±5V, AV = 1, RL = 500
CL = 2.7pF
CL = 10pF
CL = 15pF
CL = 33pF
CL = 56pF
4
3
1
0
-2
-3
-5
-6 10M 100M 1G
NORMALIZED GAIN (dB)
FREQUENCY (Hz)
-4
-1
2
1M
RF = 200
RF = 500
VS = ±5V, AV = 2, RL = 500, CL = 2.7pF
RF = 1k
EL5172, EL5372
7FN7311.10
September 4, 2012
FIGURE 7. FREQUENCY RESPONSE FOR VREF FIGURE 8. OPEN LOOP GAIN
FIGURE 9. OUTPUT IMPEDANCE vs FREQUENCY FIGURE 10. PSRR vs FREQUENCY
FIGURE 11. CMRR vs FREQUENCY FIGURE 12. VOLTAGE AND CURRENT NOISE vs FREQUENCY
Typical Performance Curves (Continued)
4
3
1
0
-2
-3
-5
-6 10M 100M 1G
NORMINALIZED GAIN (dB)
FREQUENCY (Hz)
-4
-1
2
1M
VS = ±2.5V
VS = ±5V
AV = 1, RL = 500, CL = 2.7pF
60
50
30
20
0
-10
-30
-40 100k 10M 500M
GAIN (dB)
FREQUENCY (Hz)
-20
10
40
10k 1M 100M
270
225
135
90
0
-45
-135
-180
-90
45
180
PHASE (°)
100
10
1
0.1 100k 1M 100M
IMPEDANCE ()
FREQUENCY (Hz)
10k 10M
0
-10
-30
-50
-60
-80
-90 10k 1M 100M
PSRR (dB)
FREQUENCY (Hz)
-70
-40
-20
1k 100k 10M
PSRR+
PSRR-
1M 100M
CMRR (dB)
FREQUENCY (Hz)
100k 10M 1G
100
90
70
60
40
30
10
0
20
50
80
1k
100
10
1
VOLTAGE NOISE (nV/Hz)
100 100k 10M
FREQUENCY (Hz)
10 10k 1M
1k
EN
IN
CURRENT NOISE (pA/Hz)
EL5172, EL5372
8FN7311.10
September 4, 2012
FIGURE 13. CHANNEL ISOLATION vs FREQUENCY FIGURE 14. HARMONIC DISTORTION vs OUTPUT VOLTAGE
FIGURE 15. HARMONIC DISTORTION vs LOAD RESISTANCE FIGURE 16. HARMONIC DISTORTION vs FREQUENCY
FIGURE 17. SMALL SIGNAL TRANSIENT RESPONSE FIGURE 18. LARGE SIGNAL TRANSIENT RESPONSE
Typical Performance Curves (Continued)
1M 100M
GAIN (dB)
FREQUENCY (Hz)
100k 10M 1G
0
-10
-30
-40
-60
-70
-90
-100
-80
-50
-20
CH1 <=> CH2, CH2 <=> CH3
CH1 <=> CH3
-45
-50
-60
-70
-80
-85
DISTORTION (dB)
-75
-65
-55
25
VOP-P (V)
146
37
HD2 (A
V
= 2)
HD3 (A
V
= 2)
HD2 (AV = 1)
HD3 (AV = 1)
VS = ±5V, RL = 500, f = 5MHz
-45
-50
-60
-70
-80
-85
DISTORTION (dB)
-75
-65
-55
200 700
RLOAD ()
100 600 900400 1000
HD3 (AV = 1)
-80 300 500 800
HD3 (A
V
= 2)
VS = ±5V, f = 5MHz, VOP-P = 1V @AV = 1,
VOP-P = 2V @AV = 2
HD2 (AV = 2)
HD2 (AV = 1)
-40
-50
-60
-70
-90
DISTORTION (dB)
-80
525
FREQUENCY (MHz)
03515 40
-100 10 20 30
HD2 (A
V
= 2)
HD3 (AV = 1)
HD2 (A
V
= 1)
VS = ±5V, RL = 500, VOP-P = 1V FOR AV = 1,
VOP-P = 2V for AV = 2
HD3 (AV = 2)
50mV/DIV
10ns/DIV
0.5V/DIV
10ns/DIV
EL5172, EL5372
9FN7311.10
September 4, 2012
Simplified Schematic
FIGURE 19. ENABLED RESPONSE FIGURE 20. DISABLED RESPONSE
FIGURE 21. P ACKAGE POWER DISSIPA TION vs AMBIENT
TEMPERATURE FIGURE 22. P ACKAGE POWER DISSIPA TION vs AMBIENT
TEMPERATURE
Typical Performance Curves (Continued)
CH1
CH2
100ns/DIV
M = 100ns, CH1 = 200mV/DIV, CH2 = 5V/DIV
CH1
CH2
400ns/DIV
M = 400ns, CH1 = 200mV/DIV, CH2 = 5V/DIV
486mW
JA = +206°C/W
MSOP8
870mW
JA = +115°C/W
QSOP24
1.2
1.0
0.8
0.6
0.4
00 255075100 150
AMBIENT TEMPERATURE (°C)
POWER DISSIPATION (W)
12585
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
0.2
625mW
JA = +160°C/W
SOIC8
1.136W
JA = +88°C/W
QSOP24
1.4
1.2
1.0
0.8
0.6
0.2
00 255075100 150
AMBIENT TEMPERATURE (°C)
POWER DISSIPATION (W)
12585
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
0.4
909mW
JA = +110°C/W
SOIC8
870mW
JA = +115°C/W
MSOP8/10
R2
R1
R4
R3
RD2
RD1
Q8
FBN
Q4
FBP
Q3
VIN-
Q2
VIN+
Q1
Q6
VS+
I4
I3
I2
I1
Q7VB1
VS-
25
Q9
VB2
x1 VOUT
CC
EL5172, EL5372
10 FN7311.10
September 4, 2012
Description of Operation and Application
Information
Product Descr iption
The EL5172 and EL5372 are wide bandwidth, low power
and single/differential ended to single-ended output
amplifiers. The EL5172 is a single channel differential to
single-ended amplifier. The EL5372 is a triple channel
differential to single-ended amplifier. The EL5172 and
EL5372 are internally compensated for closed loo p gain of
+1 or greater. Conn ected in gain of 1 and driving a 500
load, the EL5172 and EL5372 have a -3dB ban dwidth of
250MHz. Driving a 150 load at gain of 2, the bandwidth is
about 50MHz. The bandwidth at the REF input is about
450MHz. The EL5172 and EL5372 are available with a
power-down feature to reduce the power while the amplifier
is disabled.
Input, Output and Supply Voltage Range
The EL5172 and EL5372 have been designed to operate
with a single supply voltage of 5V to 10V or split supplies
with its total voltage from 5V to 10V. The amplifiers have an
input common mode voltage range from -4.3V to 3.3V for
±5V supply. The differential mode input range (DMIR)
between the two inputs is about from -2.3V to +2.3V. The
input voltage range at the REF pin is from -3.6V to 3.3V. If
the input common mode or differential mode signal is outside
the above-specified ranges, it will cause the output signal to
be distorted.
The output of the EL5172 and EL5372 can swing from -3.8V
to 3.6V at 500 load at ±5V supply. As the load resistance
becomes lower, the output swin g is reduced respectively.
Overall Gain Settings
The gain setting for the EL5172 and the EL5372 is similar to
the conventional operational amplifier. The output voltage is
equal to the difference of the inputs plus VREF and then
times the gain, as expressed in Equation 1.
FIGURE 23.
Choice of Feedback Resistor and Gain Bandwidth
Product
For applications that require a gain of +1, no feedback
resistor is required; just short the OUT pin to the FB pin. For
gains greater than +1, the feedback resi stor forms a pole
with the parasitic capacitance at the inverting input. As this
pole becomes smaller, the amplifier's phase margin is
reduced. This causes ringing in the time do main and
peaking in the frequency domain. Therefore, RF has some
maximum value that should not be exceeded for optimum
performance. If a large value of RF must be used, a small
capacitor in the few Pico farad range in parallel with RF can
help to reduce the ringing and peakin g at the expense of
reducing the bandwidth.
The bandwidth of the EL5172 and EL5372 depends on the
load and the feedback network. RF and RG appear in
parallel with the load for gains other than +1. As this
combination gets smaller, the bandwidth falls off.
Consequently, RF also has a minimum value that should not
be exceeded for optimum bandwidth performance. For a
gain of +1, RF = 0 is optimum. For the gains other th an +1,
optimum response is obtained with RF between 500 to
1k. For A V = 2 and RF = RG = 1k, the BW is about 80MHz
and the frequency response is very flat.
The EL5172 and EL5372 have a gain bandwidth product of
100MHz. For gains 5, its bandwidth can be predicted using
Equation 2:
Driving Capacitive Loads and Cables
The EL5172 and EL5372 can dri v e 56pF capacitance in
parallel with 500 load to ground with 4dB of peaking at a
gain of +1. If less peaking is desired in applications, a small
series resistor (usually between 5 to 50) can be placed in
series with each output to eliminate most peaking. However ,
this will reduce the gain slightly. If the gain setting is greater
than 1, the gain resistor RG can then be chosen to make-up
for any gain loss which may be created by the additional
series resistor at the output.
When used as a cable driver, doubl e termination is always
recommended for reflection-free performance. For those
applications, a back-termination series resistor at the
amplifier's output will isolate the amplifier from the cable and
allow extensive capacitive drive. However , other applications
may have high capacitive loads without a back-termination
resistor. Again, a small series resistor at the output can help
to reduce peaking.
Disable/Power-Down
The EL5172 and EL5372 can be disab led and its outputs
placed in a high impedance state. The turn-off time is about
1.4µs and the turn-on time is about 150ns. When disab led,
the amplifier's supply current is reduced to 80µA for IS+ and
120µA for IS- typically, thereby effectively eliminating the
VOVIN+V
IN-V
REF
+1RF
RG
--------
+



–= (EQ. 1)
-
+
-
+
G/B VO
EN
VIN+
VIN-
VREF
FB
RG
RF
Gain BW 100MHz=(EQ. 2)
EL5172, EL5372
11 FN7311.10
September 4, 2012
power consumption. The amplifier's power-down can be
controlled by standard CMOS signal levels at the ENABLE
pin. The applied logic signal is relative to VS+ pin. Letting the
EN pin float or applying a signal that is less than 1.5V below
VS+ will enable the amplifier. The amplifier will be disabled
when the sign a l at EN pin is above VS+ - 0.5V. If a TTL
signal is used to control the enabled/disabled function,
Figure 24 could be used to convert the TTL signal to CMOS
signal.
FIGURE 24.
Output Drive Capability
The EL5172 and EL5372 have internal short circuit
protection. Its typical short circuit current is ±95mA. If the
output is shorted indefinitely, the power dissipation could
easily increase such that the part will be destroyed.
Maximum reliability is maintained if the output current never
exceeds ±60mA. This limit is set by the design of the internal
metal interconnections.
Power Dissipation
With the high output drive capability of the EL5172 and
EL5372, it is possible to exceed the +135°C absolute
maximum junction temperature under certain load current
conditions. Therefore, it is important to calculate the
maximum junction temperature for the application to
determine if the load conditions or package types need to be
modified for the amplifier to remain in the safe operating
area.
The maximum power dissipation allowed in a package is
determined according to Equation 3:
•T
JMAX = Maximum junction temperature
•T
AMAX = Maximum ambient temp erature
•JA = Thermal resistance of the package
Assuming the REF pin is tied to GND for VS = ±5V
application, the maximum power dissipation actually
produced by an IC is the total quiescent supply current times
the total power supply voltage, plus the power in the IC due
to the load, or:
For sourcing, use Equation 4:
For sinking, use Equation 5:
Where:
•V
S = Tot al supply voltage
•I
SMAX = Maximum quiescent supply current per channel
•V
OUT = Maximum output voltage of the application
•R
LOAD = Load resistance
•I
LOAD = Load current
• i = Number of channels
By setting the two PDMAX equations equal to each other , we
can solve the output current and RLOAD to avoid th e device
overheat.
Power Supply Bypassing and Printed Circuit
Board Layout
As with any high frequency device, a good printed circuit
board layout is necessary for optimum performance. Lead
lengths should be as short as possi ble. The power supply
pin must be well bypassed to reduce the risk of oscillation.
For normal single supply operation, where the VS- pin is
connected to the ground plane, a sing le 4.7µF tantalum
capacitor in parallel with a 0.1µF ceramic capacitor from VS+
to GND will suffice. This same capacitor combination should
be placed at each supply pin to ground if split supplies are to
be used. In this case, the VS- pin becomes the negative
supply rail.
For good AC performance, parasitic capacitance should be
kept to a minimum. Use of wire wound resistors should be
avoided because of their additi onal series inductance. Use
of sockets should also be avoided if possible. Sockets add
parasitic inductance and capacitance that can result in
compromised performance. Minimizing parasitic capacitance
at the amplifier's inverting input pin is very im portant. The
feedback resistor should be placed very close to the
inverting input pin. S trip line design techniques are
recommended for the signal traces.
1k
10k
5V
EN
CMOS/TTL
PDMAX TJMAX TAMAX
–
JA
---------------------------------------------
=(EQ. 3)
PDMAX VSISMAX VS+VOUTVOUT
RLOAD
--------------------i–+=(EQ. 4)
PDMAX VSISMAX VOUT
VS-ILOADi–+=(EQ. 5)
EL5172, EL5372
12 FN7311.10
September 4, 2012
Typical Applications
FIGURE 25. TWISTED PAIR CABLE RECEIVER
FIGURE 26. COMPENSATED LINE RECEIVER
As the signal is transmitted through a cable, the high
frequency signal will be attenuated. One way to compensate
for this loss is to boost the high frequency gain at the
receiver side.
Level Shifter and Sign al Summer
The EL5172 and EL5372 contains two pairs of differential
pair input stages, which make sure that the inputs are all
high impedance inputs. To take advantage of the two high
impedance inputs, the EL5172 and EL5372 can be used as
a signal summer to add two signals together . One signal can
be applied to VIN+, the second signal can be applied to REF
and VIN- is ground. The output is equal to Equation 6:
Also, the EL5172 and EL5372 can be used as a level shifter
by applying a level control signal to the REF input.
0
VFB
VINB
VREF
EL5172,
EL5372
EL5173,
EL5373 VOUT
50
50
ZO = 100
VIN
50
50
R2
VFB
VINB
VREF
EL5172,
EL5372 VOUT
VIN
50
50
R1
R3
C1
ZO = 100
fAfCf
GAIN
(dB)
1 + R2/R1
1 + R2/(R1 + R3)
VOVIN
+V
REFGain+= (EQ. 6)
EL5172, EL5372
13 FN7311.10
September 4, 2012
EL5172, EL5372
Package Outline Drawing
M8.15E
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 0, 08/09
Unless otherwise specified, tolerance : Decimal ± 0.05
The pin #1 identifier may be either a mold or mark feature.
Interlead flash or protrusions shall not exceed 0.25mm per side.
Dimension does not include interlead flash or protrusions.
Dimensions in ( ) for Reference Only.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
5.
4.
2.
Dimensions are in millimeters.1.
NOTES:
DETAIL "A"
SIDE VIEW “A
TYPICAL RECOMMENDED LAND PATTERN
TOP VIEW
A
B
4
4
0.25 AMC B
C
0.10 C
5
ID MARK
PIN NO.1
(0.35) x 45°
SEATING PLANE
GAUGE PLANE
0.25
(5.40)
(1.50)
4.90 ± 0.10
3.90 ± 0.10
1.27 0.43 ± 0.076
0.63 ±0.23
4° ± 4°
DETAIL "A" 0.22 ± 0.03
0.175 ± 0.075
1.45 ± 0.1
1.75 MAX
(1.27) (0.60)
6.0 ± 0.20
Reference to JEDEC MS-012.
6.
SIDE VIEW “B”
14 FN7311.10
September 4, 2012
EL5172, EL5372
Package Outline Drawing
M8.118A
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE (MSOP)
Rev 0, 9/09
Plastic or metal protrusions of 0.15mm max per side are not
Dimensions “D” and “E1” are measured at Datum Plane “H”.
This replaces existing drawing # MDP0043 MSOP 8L.
Plastic interlead protrusions of 0.25mm max per side are not
Dimensioning and tolerancing conform to JEDEC MO-187-AA
6.
3.
5.
4.
2.
Dimensions are in millimeters.1.
NOTES:
DETAIL "X"
SIDE VIEW 1
TYPICAL RECOMMENDED LAND PATTERN
TOP VIEW
SIDE VIEW 2
included.
included.
GAUGE
PLANE
3°±3°
0.25 CAB
B
0.10 C
0.08 CAB
A
0.25
0.55 ± 0.15
0.95 BSC
0.18 ± 0.05
1.10 Max
C
H
4.40
3.00
5.80
0.65
3.0±0.1 4.9±0.15
1.40
0.40
0.65 BSC
PIN# 1 ID
DETAIL "X"
0.33 +0.07/ -0.08 0.10 ± 0.05
3.0±0.1
12
8
0.86±0.09
SEATING PLANE
and AMSE Y14.5m-1994.
15 FN7311.10
September 4, 2012
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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For information regarding Intersil Corporation and its products, see www.intersil.com
EL5172, EL5372
Quarter Size Outline Plastic Packages Family (QSOP)
0.010 CAB
SEATING
PLANE
DETAIL X
EE1
1(N/2)
(N/2)+1
N
PIN #1
I.D. MARK
b
0.004 C
c
A
SEE DETAIL "X"
A2
4¬¨Ðó
GAUGE
PLANE
0.010
L
A1
D
B
H
C
e
A
0.007 CAB
L1
MDP0040
QUARTER SIZE OUTLINE PLASTIC PACKAGES FAMILY
SYMBOL
INCHES
TOLERANCE NOTESQSOP16 QSOP24 QSOP28
A 0.068 0.068 0.068 Max. -
A1 0.006 0.006 0.006 ±0.002 -
A2 0.056 0.056 0.056 ±0.004 -
b 0.010 0.010 0.010 ±0.002 -
c 0.008 0.008 0.008 ±0.001 -
D 0.193 0.341 0.390 ±0.004 1, 3
E 0.236 0.236 0.236 ±0.008 -
E1 0.154 0.154 0.154 ±0.004 2, 3
e 0.025 0.025 0.025 Basic -
L 0.025 0.025 0.025 ±0.009 -
L1 0.041 0.041 0.041 Basic -
N 16 24 28 Reference -
Rev. F 2/07
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not
included.
2. Plastic interlead protrusions of 0.010” maximum per side are not
included.
3. Dimensions “D” and “E1” are measur ed at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.