512K (32K x 16) Static RAM
CY7C1020DPRELIMINARY
Cypress Semiconductor Corporation • 3901 North First Street • San Jose,CA 95134 • 408-943-2600
Document #: 38-05463 Rev. *C Revised January 11, 2005
Features
• Pin- and function-compatible with CY7C1020B
•High speed
—t
AA = 10 ns
• CMOS for optimum speed/po we r
• Low active pow er
—I
CC = 60 mA @ 10ns
• Low CMOS Standby Pow er
—I
SB2 = 1.2 mA (“L” Version only)
• Automatic power-down when deselected
• Data Retention at 2.0V
• Independent control of upper and lowe r bits
• Available in 44-pin TSOP II and 400-mil SOJ Pb-Free
Packages
Functional Description[1]
The CY7C1020D is a high-performance CMOS static RAM
organized as 32,768 words by 16 bits. This device has an
automatic power-down feature that significantly reduces
power consumption when deselected.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0
through A14). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A14).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified b y the address
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) i s
LOW , then data from memory will appear on I/O8 to I/O15. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
The input/output pins (I/O0 through I/O15) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1020D is available in standard 44-pin TSOP T ype II
and 400-mil-wide SOJ Pb-Free packages.
Note:
1. For guidelines on SRAM system design, pl ease refer to the ‘System Design Guidelines’ Cypress appl ication note, available on the internet at www.cypress.com.
WE
Logic Block Diagram Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
14 31
32
36
35
34
33
37
40
39
38
Top View
SOJ / TSOP II
12
13
41
44
43
42
16
15 29
30
VCC
A4
A14
A13
A12
NC
NC
A3
OE
VSS
A5
I/O15
A2
CE
I/O2
I/O0
I/O1
BHE
NC
A1
A0
18
17
20
19
I/O3
27
28
25
26
22
21 23
24 NC
VSS
I/O6
I/O4
I/O5
I/O7
A6
A7
BLE
VCC
I/O14
I/O13
I/O12
I/O11
I/O10
I/O9
I/O8
A8
A9
A10
A11
32K x 16
RAM Array I/O0–I/O7
ROW DECODER
A7
A6
A5
A4
A3
A0
COLUMN DECODER
A9
A10
A11
A12
A13
A14
SENSE AMPS
DATA IN DRIVERS
OE
A2
A1
I/O8–I/O15
CE
WE
BLE
BHE
A8
CY7C1020D
PRELIMINARY
Document #: 38-05463 Rev. *C Page 2 of 10
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............. ... .............. ... ... ........–55°C to +125°C
Supply Voltage on VCC to Relative GND[Notes:]–0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State[2] ..................... .............. ...–0.5V to VCC+0.5V
DC Input V oltage[2]................ .. .............. ...–0.5V to VCC+0.5V
Current into Outputs (LOW).........................................20 mA
Static Discharge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.....................................................>200 mA
Selection Guide
CY7C1020D-10 CY7C1020D-12
Maximum Access Time (ns) Com’l / Ind’l 10 12
Maximum Operating Current (mA) Com’l / Ind’l 60 50
Maximum CMOS Standby Current (mA) Com’l / Ind’l 3 3
L-Version Only 1.2 1.2
Operating Range
Range Ambient
Temperature VCC
Commercial 0°C to +70°C 5V ± 10%
Industrial –40°C to +85°C5V ± 10%
Electrical Characteristics Over the Operating Range
Parameter Description Test
Conditions
7C1020D-10 7C1020D-12
UnitMin. Max. Min. Max.
VOH Output HIGH Voltage VCC = Min.,
IOH = –4.0 mA 2.4 2.4 V
VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA 0.4 0.4 V
VIH Input HIGH Voltage 2.0 VCC + 0.3V 2.0 VCC + 0.3V V
VIL Input LOW Voltage[2] –0.5 0.8 –0.5 0.8 V
IIX Input Load Current GND < VI < VCC –1 +1 –1 +1 µA
IOZ Output Leakage
Current GND < VI < VCC,
Output Disabled –1 +1 –1 +1 µA
IOS Output Short
Circuit Current[3] VCC = Max.,
VOUT = GND –300 –300 mA
ICC VCC Operating
Supply Current VCC = Max.,
IOUT = 0 mA,
f = fMAX = 1/tRC
60 50 mA
ISB1 Automatic CE
Power-Down
Current—TTL Inputs
Max. VCC,
CE > VIH
VIN > VIH or
VIN < VIL,
f = fMAX
10 10 mA
ISB2 Automatic CE
Power-Down
Current—CMOS
Inputs
Max. VCC,
CE >
VCC – 0.3V, VIN >
VCC – 0.3V,
or VIN < 0.3V, f = 0
Non-L, Com’l / Ind’l 3 3 mA
L-Version Only 1.2 1.2 mA
Capacitance[4]
Parameter Description Test Co nditions Max. Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz,
VCC = 5.0V 8pF
COUT Output Capacitance 8 pF
Notes:
2. VIL (min.) = –2.0V and VIH(max) = VCC + 2V for pulse durat ions of less than 20 ns.
3. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
CY7C1020D
PRELIMINARY
Document #: 38-05463 Rev. *C Page 3 of 10
Thermal Resistance[4]
Parameter Description Test Conditions All - Packages Unit
ΘJA Thermal Resistance
(Junction to Ambient)[4] S till Air , soldered on a 3 × 4.5 inch, two-layer printed circuit board TBD °C/W
ΘJC Thermal Resistance
(Junction to Case)[4] TBD °C/W
AC Test Loads and Waveforms
Switching Characteristics[5] Over the Operating Range
Parameter Description
7C1020D-10 7C1020D-12
UnitMin. Max. Min. Max.
Read Cycle
tpower[6] VCC(typical) to the first access 100 100 µs
tRC Read Cycle Time 10 12 ns
tAA Address to Data Valid 10 12 ns
tOHA Data Hold from Address Change 3 3 ns
tACE CE LOW to Data Valid 10 12 ns
tDOE OE LOW to Data Valid 5 6 ns
tLZOE OE LOW to Low Z[7] 00ns
tHZOE OE HIGH to High Z[7, 8] 56ns
tLZCE CE LOW to Low Z[7] 03ns
tHZCE CE HIGH to High Z[7, 8] 56ns
tPU CE LOW to Power-Up 0 0 ns
tPD CE HIGH to Power-Down 10 12 ns
tDBE Byte Enable to Data Valid 5 6 ns
tLZBE Byte Enable to Low Z 0 0 ns
tHZBE Byte Disable to High Z 5 6 ns
Notes:
4. Tested initially and after any design or process changes that may af fect these paramet ers.
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load cap acitanc e.
6. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed.
7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
8. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±200 mV from st eady-stat e voltage.
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(b)
(c)
OUTPUT
R 480Ω
R 480Ω
R2
255Ω
R2
255Ω
167Ω
Equivalent to: THÉVENIN
EQUIVALENT 1.73V
Rise Time: 1 V/ns Fall Time: 1 V/ns
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
30 pF*
OUTPUT Z = 50Ω
50Ω
1.5V
(a)
10-ns Device 12 -ns Devices
High-Z Characteristics
CY7C1020D
PRELIMINARY
Document #: 38-05463 Rev. *C Page 4 of 10
Write Cycle[9]
tWC Write Cycle Time 10 12 ns
tSCE CE LOW to Write End 7 9 ns
tAW Address Set-Up to Write End 7 8 ns
tHA Address Hold from Write End 0 0 ns
tSA Address Set-Up to Write Start 0 0 ns
tPWE WE Pulse Width 7 8 ns
tSD Data Set-Up to Write End 6 6 ns
tHD Data Hold from Write End 0 0 ns
tLZWE WE HIGH to Low Z[7] 33ns
tHZWE WE LOW to High Z[7, 8] 66ns
tBW Byte Enable to End of Write 7 8 ns
Data Retention Characteristics Over the Operating Range
Parameter Description Conditions Min. Max. Unit
VDR VCC for Data Retention VCC = VDR = 2.0V,
CE > VCC – 0.3V,
VIN > VCC – 0.3V or
VIN < 0.3V
2.0 V
ICCDR Data Retention Current Non-L, Com’l / Ind’l 3 mA
L-Version Only 1.2 mA
tCDR[4] Chip Deselect to Data Retention Time 0 ns
tR[10] Operation Recovery Time tRC ns
Data Retention Waveform
Notes:
9. The internal write time of the memory is defined by the overlap of CE LOW , WE LO W and BHE / BLE LOW . CE, WE and BHE / BLE must be LOW to initiate a wr ite, and
the transition of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the sign al that termin ates the writ e.
10.Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 µs or stable at VCC(min.) > 50 µs.
Switching Characteristics[5] Over the Operating Range
Parameter Description
7C1020D-10 7C1020D-12
UnitMin. Max. Min. Max.
4.5V4.5V
tCDR
VDR >2V
DATA RETENTION MODE
tR
CE
VCC
CY7C1020D
PRELIMINARY
Document #: 38-05463 Rev. *C Page 5 of 10
Switching Waveforms
Read Cycle No. 1[1 1, 12]
Read Cycle No. 2 (OE Controlled)[12, 13]
Notes:
11.Device is continuously selected. OE, CE, BHE an d/or BHE = VIL.
12.WE is HIGH for read cycle.
13.Address valid prior to or coincident with CE transition LO W.
PREVIOUS DATA VALID DATA VALID
tRC
tAA
tOHA
ADDRESS
DATA OUT
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE
tHZOE
tHZBE
tPD
HIGH
OE
CE
ICC
ISB
IMPEDANCE
ADDRESS
DATA OUT
VCC
SUPPLY
tDBE
tLZBE
tHZCE
BHE,BLE
CURRENT
ICC
ISB
CY7C1020D
PRELIMINARY
Document #: 38-05463 Rev. *C Page 6 of 10
Write Cycle No. 1 (CE Controlled)[14, 15]
Write Cycle No. 2 (BLE or BHE Cont ro lled)
Notes:
14.Data I/O is high impedance if OE or BHE and/or BLE= VIH.
15.If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
Switching Waveforms (continued)
tHD
tSD
tSCE
tSA
tHA
tAW
tPWE
tWC
BW
DATA I/O
ADDRESS
CE
WE
BHE,BLE
t
tHD
tSD
tBW
tSA
tHA
tAW
tPWE
tWC
tSCE
DATA I/O
ADDRESS
BHE,BLE
WE
CE
CY7C1020D
PRELIMINARY
Document #: 38-05463 Rev. *C Page 7 of 10
Write Cycle No. 3 (WE Controlled) OE LO W
Truth Table
CE OE WE BLE BHE I/O0–I/O7I/O8–I/O15 Mode Power
H X X X X High Z High Z Power-Down Standby (ISB)
L L H L L Data Out Data Out Read – All bits Active (ICC)
L H Data Out High Z Rea d – Lower bits only Active (ICC)
H L High Z Data Out Read – Upper bits only Active (ICC)
L X L L L Data In Data In Write – All bits Active (ICC)
L H Data In High Z Write – Lower bits only Active (ICC)
H L High Z Data In Write – Upper bits only Active (ICC)
L H H X X High Z High Z Selected, Outputs Disabled Active (ICC)
L X X H H High Z High Z Selected, Outputs Disabled Active (ICC)
Ordering Information
Speed
(ns) Ordering Code Package
Name Pa ckage Type Operating
Range
10 CY7C1020D-10VXC V34 44-Lead (400-Mil) Molded SOJ (Pb-Free) Commercial
CY7C1020D-10ZXC V34 44-Lead TSOP Type II (Pb-Free)
CY7C1020D-10VXI Z44 44-Lead (400-Mil) Molded SOJ (Pb-Free) Industrial
CY7C1020D-10ZXI Z44 44-Lead TSOP Type II (Pb-Free)
12 CY7C1020D-12VXC V34 44-Lead (400-Mil) Molded SOJ (Pb-Free) Commercial
CY7C1020D-12ZXC V34 44-Lead TSOP Type II (Pb-Free)
CY7C1020D-12VXI Z44 44-Lead (400-Mil) Molded SOJ (Pb-Free) Industrial
CY7C1020D-12ZXI Z44 44-Lead TSOP Type II (Pb-Free)
Shaded areas conta i n advance information. Please contact your local Cypress sales representative for availability of these parts.
Switching Waveforms (continued)
tHD
tSD
tSCE
tHA
tAW
tPWE
tWC
tBW
DATA I/O
ADDRESS
CE
WE
BHE,BLE
tSA
tLZWE
tHZWE
CY7C1020D
PRELIMINARY
Document #: 38-05463 Rev. *C Page 8 of 10
Package Diagrams
44-Lead (400-Mil) Molded SOJ V34
51-85082-B
CY7C1020D
PRELIMINARY
Document #: 38-05463 Rev. *C Page 9 of 10
© Cypress Semi con duct or Cor po rati on , 20 05 . The information con t a in ed he re i n is su bject to change without notice. C ypr ess S em i con duct or Corpo ration assu me s no resp onsib ility for th e u se
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypres s. Furthermore, Cypress does no t authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
All product and company names mentioned in this document may be the trademarks of their respective holders.
Package Diagrams (continued)
44-Pin TSOP II Z44
51-85087-A
CY7C1020D
PRELIMINARY
Document #: 38-05463 Rev. *C Page 10 of 10
Document History Page
Document Title: CY7C1020D 512K (32K x 16) Static RAM (Preliminary)
Document #: 38-05463
REV. ECN NO. Issue Date Orig. of
Change Description of Ch a nge
** 201560 See ECN SWI Advance Datasheet for C9 IPP
*A 233695 See ECN RKF 1) DC parameters modified as per EROS (Spec # 01 -0216)
2) Pb-free Offering in the ‘Ordering Information’
*B 263769 See ECN RKF 1) Corrected Pin #18 on SOJ/TSOPII Pinout (Page #1 ) from A15 to A4
2) Changed I/O1 - I/O16 to I/O0 - I/O15 on the Pin-out diagram
3) Added Tpower Spec in Switching Characteristics Table
4) Added Data Retention Char acteristics Table and Waveforms
5) Shaded ‘Ordering Information’
*C 307594 See ECN RKF Reduced Speed bins to -10, -12 and -15 ns
