October 2012
Revision: EB52_01.3
LatticeECP3™ Video Protocol Board – Revision C
User’s Guide
2
LatticeECP3 Video Protocol Board – Revision C
User’s Guide
Introduction
The LatticeECP3™ FPGA family includes many features for video applications. For example, DisplayPort, SMPTE
standards (SD-SDI, HD-SDI and 3G-SDI), DVB-ASI, DVI and HDMI can be implemented with 16 channels of
embedded SERDES/PCS. 7:1 LVDS video interfaces like ChannelLink and CameraLink can be supported by the
generic DDRX2 mode on the I/O pins. When configuring to TRLVDS mode, the I/O pins on banks 0 and 1 can also
be used to receive the TMDS signals of DVI or HDMI video standard.
This user’s guide describes revision C of the LatticeECP3 Video Protocol Board featuring the LatticeECP3 LFE3-
95E-7FN1156C FPGA device. The stand-alone evaluation PCB provides a functional platform for development and
rapid prototyping of many different video applications.
Figure 1. LatticeECP3 Video Protocol Board – Revision C
Features
• Video interfaces for interconnection to video standard equipment
• Allow the demonstration of SD/HD/3G-SDI, DisplayPort and PCI Express (x4) interfaces using SERDES chan-
nels
• High speed Mezzanine connector connected to SERDES channels for future expansion
• Allows the demonstration of LVDS video standards – ChannelLink and CameraLink
• Allows control of SERDES PCS registers using the Serial Client Interface (ORCAstra)
• Allows the demonstration of receiving TMDS signals using the DVI interface
• On-board Boot Flash with Serial SPI Flash memory device
• Shows interoperation with high performance DDR2 memory components
• Driver-based “run-time” device configuration capability via an ORCAstra or RS232 interface
• SMAs for external high-speed clock / PLL inputs
• Switches, LEDs and LCD display header for demo purposes
• Mictor connector for using Logic Analyzer in the debugging phase
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LatticeECP3 Video Protocol Board – Revision C
User’s Guide
• Input connection for lab-power supply
• Power connections and power sources
• ispVM™ programming support
• On-board and external reference clock sources
• Various high-speed layout structures
• User-defined input and output points
• Performance monitoring via test headers, LEDs and switches
The contents of this user’s guide include top-level functional descriptions of the various portions of the evaluation
board, descriptions of the on-board connectors, diodes and switches and a complete set of schematics of the
board. Figure 2 shows the functional partitioning of the board.
Figure 2. LatticeECP3 Video Protocol Board – Revision C Functional Partition
Refclk
Ch3
Ch2
Ch1
Ch0
Refclk
Refclk
Quad CQuad BQuad A
Bank 6 Bank 7
Bank 0
Bank 1
Bank 2Bank 3
SERDES
Ch3
Ch2
Ch1
Ch0
Ch3
Ch2
Ch1
Ch0
DDR2
Memory
DDR2
Memory
DVI
Tx
DVI
Rx
3G-SDI
Equalizer
3G-SDI
Driver
3G-SDI
Driver
3G-SDI
Equalizer
ChannelLink
Tx
ChannelLink
Rx
RJ45
Tx/Rx
CameraLink
Rx
LatticeECP3-95
1156 fpBGA
DisplayPort
Tx
DisplayPort
Rx
PCI Express
x4 Edge
GS4915
VCO
Tx Refclk Generation Circuitry
SDI
Tx #0
SDI
Rx #0
SDI
Tx #1
SDI
Rx #1
from internal PLL(s)
GS4911
27MHz
Differences Between the Revision B and Revision C Boards
The major changes in revision C are summarized below:
1. The Revision C board includes eight pull-up resistors, R362-R369, to the DVI Rx signals placed close to the
LatticeECP3 device. These resistors are used for termination of the DVI’s TMDS signals and are not included
on the Revision B board.
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LatticeECP3 Video Protocol Board – Revision C
User’s Guide
2. The Revision C board includes eight pull-up resistors, R370-R377, to the DDR2 memory’s DQS signals. These
resistors are placed close to the LatticeECP3 device. These resistors are not included on the Revision B board.
3. The Revision C board includes R75 between the P and N reference clocks of SERDES Quad C (Mezzanine
daughter board) for future use. No resistor is populated. This resistor is not included on the Revision B board.
4. On the Revision C board, the Gennum clock generators (GS4911) on U2 and U3 are not populated.
LatticeECP3 Device
This board features a LatticeECP3 FPGA with a 1.2V core supply. It can accommodate all pin compatible
LatticeECP3 devices in the 1156-ball fpBGA (1mm pitch) package. A complete description of this device can be
found in the LatticeECP3 Family Data Sheet.
Applying Power to the Board
The LatticeECP3 Video Protocol Board is ready to power on. This board can be supplied with power from an AC
wall-type transformer power supply shipped with the board. Or it can be supplied from a bench top supply via termi-
nal screw connections. It also has provisions to be supplied from the PCI Express edge fingers from a host board.
To supply power from the factory-supplied wall transformer, simply connect the output connection of the power cord
to J15 and plug wall-transformer into an AC wall outlet.
Supply Power from Bench Power Supply
The evaluation board incorporates an alternate scheme to provide power to the board. The board is equipped to
accept a main supply via the TB1 connection. This connection is intended to be used with a bench top supply
adjusted to provide a nominal 12V DC.
All input power sources and on-board power supplies are fused with surface mounted fuses. Table 1 shows these
fuses and the corresponding powers.
Table 1. Board Power Supply Fuses
Fuse # Rating Voltage Usage
F1 3A 2.5V EEPROM, DDR2 regulator, Bank 1, 2 and 3 I/Os, DIP switches
F2 3A 1.8V Bank 6, Bank 7 I/Os, DDR2 regulator, DDR2 memory, Gennum clock chips
F3 3A 5.0V
Cable driver/equalizer power regulator, Gennum clock chips power regulators, Dis-
playPort power output regulators, Mezzanine connector, DVI power output for EDID,
LCD module
F4 3A 1.2V LatticeECP3 SERDES
F5 10A 12V Main power supply
F6 10A 1.2V LatticeECP3 Core
F7 10A 3.3V
LatticeECP3 VCCAUX, PLL, JTAG, Bank 0 and 8 I/Os, SPI Flash memory, push-button
debouncer, DVI transmitter, RS-232 driver/receiver, zero delay clock buffer, clock
oscillators, MachXO™, cable driver/equalizer
The Lattice ispPAC® Power Manager II device, the ispPAC-POWR1220AT8, is used for monitoring various voltages
on the board. There are six LEDs used to indicate the status of the monitoring voltages. If the monitoring voltage is
not in the +/- 5% voltage window, the corresponding LED will flash; otherwise, the LED will stay ON. Tab l e 2 shows
these six voltages and the corresponding LEDs.
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LatticeECP3 Video Protocol Board – Revision C
User’s Guide
Table 2. Board Power Supply Monitoring Indicators
Power LED # Voltage Range In Range Out of Range
LatticeECP3 SERDES D33 1.2V +/- 5% On Flash
LatticeECP3 Core D32 1.2V +/- 5% On Flash
3.3V D31 3.3V +/- 5% On Flash
2.5V D29 2.5V +/- 5% On Flash
5.0V D28 5.0V +/- 5% On Flash
1.8V D27 1.8V +/- 5% On Flash
External power can be alternatively connected through TB1 rather than the wall transformer power pack.
Table 3. Board Supply Disconnects
TB1
Screw terminal for 12V DC
+12V: Pin1 (closer to the wall transformer power jack J15) 12V DC
GND: Pin2 (closer to the LCD connector)
PCI Express Power Interface
Power can be sourced to the board via the PCB edge-finger (CN1). This interface allows the user to provide power
from a PCI Express host board.
Configuration/Programming Headers
Two programming headers are provided on the board for accessing to the LatticeECP3 JTAG port and sysCON-
FIG™ port. The JTAG connector is a 1x10 header and the sysCONFIG connector is a 2x17 header.
Table 4. sysCONFIG Connector Pinout (J37)
Net Name LatticceECP3 Pin Header Pin Net Name Lattic ceECP3 Pin Header Pin
CCLK C34 1GND — 2
SISPI F33 3D6 J34 4
CSSPI0N D34 53.3V — 6
CSSP1N E34 7INITN C33 8
DONE G31 9PROGRAMN B34 10
D7 F32 11 GND —12
D6 J34 13 GND —14
D5 H34 15 GND —16
D4 G32 17 GND —18
D3 G33 19 GND —20
D2 H33 21 GND —22
D1 G34 23 GND —24
D0 E32 25 GND —26
CSN F31 27 WRITE E31 28
CS1 G30 29 CFG0 B33 30
3.3V —31 CFG1 F30 32
GND — 33 CFG2 D32 34
J28 is a 10-pin JTAG connector used in conjunction with the ispVM download cable to program and control the Lat-
tice devices on this board.
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LatticeECP3 Video Protocol Board – Revision C
User’s Guide
Table 5. ispVM JTAG Connector (J28)
Pin # Description
Pin 1 VCC
Pin 2 TDO
Pin 3 TDI
Pin 4 PROGRAMN
Pin 5 NC
Pin 6 TMS
Pin 7 GND
Pin 8 TCK
Pin 9 DONE
Pin 10 INITN
This board includes three Lattice programmable devices that can be programmed in a daisy chain (U30 =
LatticeECP3-95, U1 = MachXO™ LCMXO256, and U36 = ispPAC-POWR1220AT8). Other than the LatticeECP3-
95, the JTAG connector provides access to the JTAG ports of the ispPAC-POWR1220AT8 and the MachXO. With
proper jumper selection, the JTAG ports of these devices can be chained together for programming. Tab l e 6 shows
the jumper settings of J32, J33 and J34 used to configure the JTAG connections.
Table 6. JTAG Connection Settings (J32, J33, J34)
Jumper Settings JTAG Connection
1
J32 J33 J34
ECP3 MachXO ispPACTDI
TDO
2
J32 J33 J34
ECP3 MachXO ispPACTDI
TDO
3
J32 J33 J34
ECP3 MachXO ispPAC
TDI
TDO
4
J32 J33 J34
ECP3 MachXO ispPAC
TDI
TDO
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LatticeECP3 Video Protocol Board – Revision C
User’s Guide
There are several LEDs on the board to indicate the LatticeECP3 programming status. They are listed in Ta bl e 7.
Table 7. LED Indicators for Configuration Status
LED # Color Function
D19 Red LED illuminated to indicate that the programming was aborted or reinitialized driving the INITN
output low.
D18 Green LED illuminated to indicate the successful completion of configuration by releasing the open col-
lector DONE output pin.
D20 Red LED illuminated to indicate that PROGRAMN is low.
D21 Red LED illuminated to indicate that GSRN is low.
The PROGRAMN pin of the LatticeECP3-95 is connected to a push-button switch (SW5). Depressing this button
drives a logic level “0” to the PROGRAMN pin. This will force the LatticeECP3 into the configuration mode and initi-
ate the configuration sequence.
The FPGA CFG pins are set on the board for a particular programming mode via the SW2 DIP switch. JTAG pro-
gramming is independent of the MODE pins and is always available to the user. Pushing down the switch will turn it
on and set the CFG value to 0.
Table 8. CFG Mode Selections
CFG2
(SW2-1) CFG1
(SW2-2) CFG0
(SW2-3) Selected Configuration Mode
0 (ON) 0 (ON) 0 (ON) SPI Flash Mode (available on-board)
0 (ON) 1 (OFF) 0 (ON) SPIm
1 (OFF) 0 (ON) 0 (ON) Master Serial
1 (OFF) 0 (ON) 1 (OFF) Slave Serial
1 (OFF) 1 (OFF) 0 (ON) Master Parallel
1 (OFF) 1 (OFF) 1 (OFF) Slave Parallel
5
J32 J33 J34
ECP3 MachXO ispPACTDI
TDO
6
J32 J33 J34
ECP3 MachXO ispPAC
TDI
TDO
7
J32 J33 J34
ECP3 MachXO ispPAC
TDI
TDO
Table 6. JTAG Connection Settings (J32, J33, J34) (Continued)
Jumper Settings JTAG Connection
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LatticeECP3 Video Protocol Board – Revision C
User’s Guide
On-Board Flash Memory
One SPI (16-pin TSSOP 64M) Flash memory device (U32) is on board for non-volatile configuration memory stor-
age. The CFG [2:0] setting must be [000] for the LatticeECP3 to enable the SPI Flash mode.
Video Clock Management and SDI Cable Driver/Equalizer
Industry standard video clocks are generated and managed via Gennum chipsets. These chipsets are used to gen-
erate both transmit and receive reference clocks for LatticeECP3 SERDES. The GS4911 clock generator device
produces multiple video standard reference clocks from an on-board 27MHz crystal. The GS4915 clock cleaner is
used to reduce clock jitter to produce a clean clock for video signal quality using a high-performance VCO. The
Gennum clock devices are used to generate clocks for SD/HD/3G-SDI applications. Since the PLL in LatticeECP3
FPGAs is designed to support all the frequencies required by SD/HD/3G-SDI, the GS4911 clock generator is no
longer needed. The two GS4911 devices found on the Revision B board are included on the Revision C board but
not populated.
Two cable drivers and two cable equalizers are placed on-board for SD/HD/3G-SDI applications that require deliv-
ering video signal over 75 ohm coaxial cable.
The control and status pins of the Gennum chipsets and the cable drivers/equalizers are connected to the MachXO
I/O pins. By using the signals connected between the MachXO and LatticeECP3, the Gennum chipsets and cable
drivers/equalizers can be controlled from the design in the LatticeECP3. Figure 3 shows the block diagram of the
control/status buses of the connections between these devices. The MachXO pins connected to these devices are
shown in Tables 9 to 12.
Figure 3. Block Diagram of Gennum Chipsets and Cable Driver/Equalizer Controls
Rx Refclk
Generator
GS4911
(U2)
Rx Refclk
Cleaner
GS4915
(U6)
Tx Refclk
Generator
GS4911
(U3)
Tx Refclk
Cleaner
GS4915
(U7)
MachXO
LatticeECP3
12
RX_GS4911_RESETn
TX_GS4911_RESETn
SDI Tx #1
Cable
Driver
(U24)
SDI Rx #1
Cable
Equalizer
(U21)
SDI Tx #0
Cable
Driver
(U22)
SDI Rx #0
Cable
Equalizer
(U25)
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LatticeECP3 Video Protocol Board – Revision C
User’s Guide
Table 9. MachXO Pin Connections to GS4911 Devices (GS4911 Devices are Not Populated on the Revision
C Board)
Signal Type GS4911 Pin Name U2 (for Rx Refclk) U3 (for Tx Refclk) Pull-low/high
Control
VID_STD0 K2 G13 High
VID_STD1 L1 H13 Low
VID_STD2 L2 J13 High
VID_STD3 M1 J14 Low
VID_STD4 M2 K13 High
VID_STD5 N1 K14 Low
/GENLOCK M3 M13 High
ASR_SEL0 H2 —Low
ASR_SEL1 G2 —Low
ASR_SEL2 F2 —Low
JTAG / HOSTn1N11 N11 —
SCLK_TCLK1P13 P13 —
SDIN_TDI — N12 —
SDOUT_TDO P12 — —
CSn_TMS P11 P14 —
/RESET D17 (from LatticeECP3) D12 (from LatticeECP3) Low
Status
LOCK_LOST —L14 —
REF_LOST —L13 —
TIMING_OUT_1 K1 F14 —
TIMING_OUT_2 J2 F13 —
TIMING_OUT_3 J1 E14 —
TIMING_OUT_4 —E13 —
1. These are the signals controlled by the same MachXO I/O pins.
Table 10. MachXO Pin Connections to GS4915 Devices
Signal Type GS4915 Pin Name U6 (for Rx Refclk) U7 (for Tx Refclk) Pull-low/high
Control
/RESET F1 D14 High
IPSEL E2 D13 Low
BYPASS E1 C14 Low
/AUTOBYPASS C2 C13 Low
FCTRL0 D1 B14 Low
FCTRL1 D2 C12 Low
DOUBLE C1 A13 Low
SKEW_EN B1 A12 Low
Status LOCK B11 B12 —
Table 11. MachXO Pin Connections to LMH0303 or GS2 978 Cable Driver Devices
Signal Type Dr iver Pin Name U22 (for Tx #0) U24 (for Tx #1) Pull-low/high
Control
SD / HDn N5 N14 Low
ENABLE (/DISABLE) N6 M14 High
/RSTI N7 —High
Status /FAULT N13 N13 —
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LatticeECP3 Video Protocol Board – Revision C
User’s Guide
Table 12. MachXO Pin Connections GS2974 Cable Equalizer Devices
Signal Type Dr iver Pin Name U25 (for Rx #0) U21 (for Rx #1) Pull-low/high
Control
BYPASS P3 P8 Low
MUTE P4 N8 Low
MCLADJ Controlled by
potentiometer VR3
Controlled by
potentiometer VR2 —
Status /CD N3 P9 —
Table 13. MachXO Pin Connections to LatticeECP3
Net Name MachXO Pin LatticeECP3 Pin
ECP3_XO_SIG0 B10 AM31
ECP3_XO_SIG1 A9 AL31
ECP3_XO_SIG2 A7 AN31
ECP3_XO_SIG3 A6 AP31
ECP3_XO_SIG4 A5 AM32
ECP3_XO_SIG5 B4 AN32
ECP3_XO_SIG6 A3 AB33
ECP3_XO_SIG7 B3 AB34
ECP3_XO_SIG8 A2 Y31
ECP3_XO_SIG9 C3 Y32
ECP3_XO_SIG10 A1 Y33
ECP3_XO_SIG11 B2 Y34
The status pins of these devices can also be observed from LED indicators. Ta b l e 13 shows the these LEDs with
the associated signals.
Table 14. LED Indicators for Video Clocking and Cable Equalizer Status
LED # Color Function Description
D4
Red
Rx GS4911 REF LOST LED illuminates to indicate that no reference signal is applied or the
FSYNC, VSYNC, HSYNC input reference signals do not meet the
min/max timing requirement.
D1 Tx GS4911 REF LOST
D3 Rx GS4911 LOCK LOST LED illuminates to indicate the GS4911 clock output is not genlocked to
the input reference signals.
D2 Tx GS4911 LOCK LOST
D5 Green Rx GS4915 LOCK LED illuminates to indicate that the GS4915 output clock is locked to the
input clock selected by IPSEL.
D6 Tx GS4915 LOCK
D9 Orange SDI Rx #0 Carrier Detect LED illuminates to indicate that the equalizer has detected the presence
of a good input video signal.
D8 SDI Rx #1 Carrier Detect
SERDES
There are three SERDES quads available for the LatticeECP3-95. Each quad include four SERDES channels.
These 12 SERDES channels are used for implementing high-speed serial link interfaces. Figure 4 shows the how
these channels are used.
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LatticeECP3 Video Protocol Board – Revision C
User’s Guide
Figure 4. Block Diagram of SERDES Usage
Refclk
Ch3
Ch2
Ch1
Ch0
Refclk
Refclk Bank 6
Bank 3
SERDES
Ch3
Ch2
Ch1
Ch0
Ch3
Ch2
Ch1
Ch0
Equalizer
(U25)
Driver
(U22)
Driver
(U24)
Equalizer
(U21)
DisplayPort
Tx (J4)
DisplayPort
Rx (J3)
PCI Express
x4 Edge
SDI
Tx #0
(J5)
SDI
Rx #0
(J6)
SDI
Tx #1
(J2)
SDI
Rx #1
(J1)
3.3V Voltage
Regulator
3.3V Voltage
Regulator
Si570
(U9)
SMA (J7, J8) Mezz
Mezzanine
Connector
(J19)
from internal PLL(s)
GS4915
VCO
GS4911
27MHz
Quad CQuad BQuad A
LatticeECP3-95
1156 fpBGA
Tx Refclk Generation Circuitry
The power supply of the input and output buffers of the SERDES quads can be individually set to either 1.2V or
1.5V. This is done by headers J18, J20~J24. Ta bl e 15 shows the jumper settings of these headers for applying
either 1.2V or 1.5V power to the SERDES input and output buffers.
Table 15. Jumper Settings for SERDES I/O Buffer (J18, J20~J24)
Header Buffer Jumper
Setting Function
J24 Quad A Input
(SDI/DP)
1-2 Set PCSA_VCCIB (J24 pin 2) to 1.2V
2-3 Set PCSA_VCCIB (J24 pin 2) to 1.5V
J20 Quad A Output
(SDI/DP)
1-2 Set PCSA_VCCOB (J20 pin 2) to 1.2V
2-3 Set PCSA_VCCOB (J20 pin 2) to 1.5V
J23 Quad B Input
(PCI Express)
1-2 Set PCSB_VCCIB (J23 pin 2) to 1.2V
2-3 Set PCSB_VCCIB (J23 pin 2) to 1.5V
J21 Quad B Output
(PCI Express)
1-2 Set PCSB_VCCOB (J21 pin 2) to 1.2V
2-3 Set PCSB_VCCOB (J21 pin 2) to 1.5V
J22 Quad C Input
(Mezzanine)
1-2 Set PCSC_VCCIB (J22 pin 2) to 1.2V
2-3 Set PCSC_VCCIB (J22 pin 2) to 1.5V
J18 Quad C Output
(Mezzanine)
1-2 Set PCSC_VCCOB (J18 pin 2) to 1.2V
2-3 Set PCSC_VCCOB (J18 pin 2) to 1.5V
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LatticeECP3 Video Protocol Board – Revision C
User’s Guide
Quad A (3G-SDI and DisplayPort Video Interfaces)
Quad 0 is used for SDI and DisplayPort video protocols. Channel 0 and 1 of quad 0 are used for SD/HD/3G-SDI.
The SD/HD/3G-SDI video signal is a signal-ended video signal transmitting through 75-ohm coaxial cable connect-
ing through BNC connectors. Two cable drivers and two cable equalizers are placed on board for using longer
coaxial cable. Channels 2 and 3 are used for support Displayport up to two data lanes.
Ta bl e 16 shows the ECP3 connections for the SD/HD/3G-SDI video interface connectors.
Table 16. SD/HD/3G-SDI Connections (J1, J2, J5 and J6)
Connector Description Cable Driver/Equalizer SERDES Pin Names LatticeECP3 Pin #
J5 SDI Tx #0 Driver (U22) PCSA_HDOUT[P:N]0 AP21, AN21
J6 SDI Rx #0 Equalizer (U25) PCSA_HDIN[P:N]0 AL21, AK21
J2 SDI Tx #1 Driver (U24) PCSA_HDOUT[P:N]1 AP20, AN20
J1 SDI Rx #1 Equalizer (U21) PCSA_HDIN[P:N]1 AL20, AK20
There are two instances of Gennum clocking circuitry on this board, one for Rx side and the other for Tx side. Since
the specification of the high-speed video output stream jitter is critical, it is important to have a clean reference
clock for the Tx side serializer. The reference clock of the SERDES channel can come from different a path, but the
clock coming in through the dedicated reference clock pins will have the lowest jitter.
The dedicated reference clock pins of quad 0 can be sourcing from the following clocks:
• Clock generated by the on-board Gennum clocking chipsets
•Clock generated by the Silicon Labs Si570
• External differential clock coming through the two SMA connectors
Other than generating from the Gennum chipsets, the transmit reference clock can also receive input clock from an
external clock source via a pair of SMA connectors, or from the on-board Silicon Labs Si570. To avoid PCB trace
stub and minimize the jitter of the Tx reference clock, two zero-ohm resistors are used for selecting the clock from
one of the three clock sources. Figure 5 shows how these two zero-ohm resistors are installed to select a differ-
ence clock source. See the schematic in Appendix A (Figure 16) for the detailed clock multiplexing circuitry.
Figure 5. Resistors for Quad 0 Reference Clock Selection
R47
R48
TP11 TP13
TP12 TP14
Select clock from
Gennum chipsets
Select clock from
SMA connectors
Select clock from
Silicon Labs Si570
On-board Default
Figure 6 shows the block diagram of the DisplayPort circuitry on this board. Since only two channels in SERDES
Quad 0 are used, the DisplayPort video interface on this board can only support up to two lanes. Two instances of
3.3V voltage regulators are used for providing power to the off-board DisplayPort devices when necessary.
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LatticeECP3 Video Protocol Board – Revision C
User’s Guide
Figure 6. Block Diagram of the DisplayPort Video Interface
ML0_P_IN
ML0_N_IN
ML1_P_IN
ML1_N_IN
AUX_P
49.9 100
49.9
100
1M
1M
3.3V
AUX_N
N27
N28
AL19
AK19
AL18
AK18
Quad 0
CH3
Quad 0
CH2
LatticeECP3
(U30)
49.9100
49.9
100
100K
100K
3.3V
R26
R25
AP19
AN19
AP18
AN18
0.01uF0.01uF
CONFIG1
CONFIG2
HPD_OUT
PWR_OUT
100K
3.3V Voltage
Regulator
(U19)
1K
1K
C31
ML0_P_OUT
ML0_N_OUT
ML1_P_OUT
ML1_N_OUT
AUX_P
AUX_N
CONFIG1
CONFIG2
HPD_OUT
PWR_OUT
1K
1K
100K
C32
3.3V Voltage
Regulator
(U23)
J16
elbaneelbane
DisplayPort
Tx (J4)
DisplayPort
Rx (J3)
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
G17
5.0V
5.0V
Ta bl e 17 shows the pin connections of the DisplayPort video interface.
Table 17. DisplayPort Connections (J3 and J4)
Connector Pin Name Pin # LatticeECP3 Pin Name LatticeECP3 Pin #
DisplayPort
Tx (J4)
ML0_[P:N]_OUT 1 and 2 PCSA_HDOUT[P:N]2 AP19, AN19
ML1_[P:N]_OUT 4 and 6 PCSA_HDOUT[P:N]3 AL18, AK18
AUX_[P:N] 15 and 17 PR31[A:B] R26, R25
HPD_IN 18 PT143B C32
DisplayPort
Rx (J3)
ML0_[P:N]_IN 10 and 12 PCSA_HDIN[P:N]2 AL19, AK19
ML1_[P:N]_IN 7 and 8 PCSA_HDIN[P:N]3 AL18, AK18
AUX_[P:N] 15 and 17 PR22[A:B] N27, N28
HPD_OUT 18 PT145B C31
Quad B (PCI Express x4)
This board is equipped to communicate directly as an add-on card to a PCI Express host. It is designed with edge-
fingers (CN1) to fit directly into a x1 host receptacle. Power can be supplied directly from the PCI Express host via
the edge-finger connections.
All channels of Quad 1 are connected to the PCI Express Edge connector (CN1) for implementing a PCI Express
x4 interface. The dedicated reference clock input pins and a reset control signal are also connected to the PCI
Express edge connector.
Table 18. SERDES PCI Express Interconnections
PCI Express
Name PCI Express
Pin # LatticeECP3
Pin Name LatticeECP3
Pin # AC
Coupling PCI Express Pin Description
PERp0 A16 PCSB_HDOUTP0 AP17 C365 Receiver differential pair, Lane 0
PERn0 A17 PCSB_HDOUTN0 AN17 C366
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LatticeECP3 Video Protocol Board – Revision C
User’s Guide
Quad C (Daughter Board Expansion)
All channels of Quad 2 are connected to a high-speed Molex Mezzanine connector for working with a 3.2 x 2.5”
daughter board. Users can design a daughter board for implementing anything that requires the SERDES quad,
such as the high-speed HDMI/DVI video interface.
Figure 7. Daughter Board Connection
Power
D
P
D
P
T
x
R
x
T
x
R
x
MDR MDR MDR MDR
3.2" x 2.5"
Hole for standoffs
to secure the
Daughter Board
Mezzanine
DVI
Connector
(J19)
Daughter Board
Control Connector
(J47)
Daughter Board
Power Connector
(J17)
Lattice
ECP3
Other than the four input/output Quad 2 SERDES channels and the differential reference clock pair, there are three
differential pairs of general purpose I/Os connected between the Mezzanine connector and the LatticeECP3
device. These signals can be used for the control or status signals of the daughter board. A 4-pin power connector
is used to provide power to the daughter board. Tables 19 and 20 show the pin connections of the Mezzanine and
the power connectors. Ta bl e 21 shows the pin connections between the LatticeECP3 and the daughter board con-
PERp1 A21 PCSB_HDOUTP1 AP16 C372 Receiver differential pair, Lane 1
PERn1 A22 PCSB_HDOUTN1 AN16 C375
PERp2 A25 PCSB_HDOUTP2 AP15 C376 Receiver differential pair, Lane 2
PERn2 A26 PCSB_HDOUTN2 AN15 C379
PERp3 A29 PCSB_HDOUTP3 AP14 C382 Receiver differential pair, Lane 3
PERn3 A30 PCSB_HDOUTN3 AN14 C383
PETp0 B14 PCSB_HDINP0 AL17 None Transmitter differential pair, Lane 0
PETn0 B15 PCSB_HDINN0 AK17 None
PETp1 B19 PCSB_HDINP1 AL16 None Transmitter differential pair, Lane 1
PETn1 B20 PCSB_HDINN1 AK16 None
PETp2 B23 PCSB_HDINP2 AL15 None Transmitter differential pair, Lane 2
PETn2 B24 PCSB_HDINN2 AK15 None
PETp3 B27 PCSB_HDINP3 AL14 None Transmitter differential pair, Lane 3
PETn3 B28 PCSB_HDINN3 AK14 None
REFCLK+ A13 PCSB_REFCLKP AH15 None Reference clock (differential pair)
REFCLK- A14 PCSB_REFCLKN AH16 None
PERST# A11 PT109A J21 None Fundamental reset
Table 18. SERDES PCI Express Interconnections (Continued)
PCI Express
Name PCI Express
Pin # LatticeECP3
Pin Name LatticeECP3
Pin # AC
Coupling PCI Express Pin Description
15
LatticeECP3 Video Protocol Board – Revision C
User’s Guide
trol connector.
Table 19. Mezzanine Connections (J19)
J19 Pin # LatticeECP3 Pin Name LatticeECP3 Pin # Description
1PCSC_HDINP3 AL22 SERDES Quad 2 Channel 3 Input
2PCSC_HDINN3 AK22
3PCSC_HDINP2 AL23 SERDES Quad 2 Channel 2 Input
4PCSC_HDINN2 AK23
5PCSC_HDINP1 AL24 SERDES Quad 2 Channel 1 Input
6PCSC_HDINN1 AK24
7PCSC_HDINP0 AL25 SERDES Quad 2 Channel 0 Input
8PCSC_HDINN0 AK25
9PR25A P28 User-defined Differential Signal Pair 1
10 PR25B P27
11 PR28A R28 User-defined Differential Signal Pair 2
12 PR28B R27
13 PCSC_HDOUTP3 AL22 SERDES Quad 2 Channel 3 Output
14 PCSC_HDOUTN3 AK22
15 PCSC_HDOUTP2 AL23 SERDES Quad 2 Channel 2 Output
16 PCSC_HDOUTN2 AK23
17 PCSC_HDOUTP1 AL24 SERDES Quad 2 Channel 1 Output
18 PCSC_HDOUTN1 AK24
19 PCSC_HDOUTP0 AL25 SERDES Quad 2 Channel 0 Output
20 PCSC_HDOUTN0 AK25
21 PCSC_REFCLKP AH22 SERDES Quad 2 Reference Clock
22 PCSC_REFCLKN AH23
23 PR19A N26 User-defined Differential Signal Pair 0
24 PR19B P26
Table 20. Daughter Board Power Connections (J17)
J17 Pin Number Voltage Maximum Current
2, 4 5.0V ~8A
6, 8 3.3V ~8A
10 1.8V ~2A
1, 3, 5, 7, 9 GND
16
LatticeECP3 Video Protocol Board – Revision C
User’s Guide
Table 21.
J47 Pin
Number LatticeECP3
Pin Number Signal Name J47 Pin
Number LatticeECP3
Pin Number Signal Name
1 AM8 MZ_CTRL0 2 AM7 MZ_CTRL1
3AK8 MZ_CTRL2 4AK7 MZ_CTRL3
5AG9 MZ_CTRL4 6AF9 MZ_CTRL5
7AK6 MZ_CTRL6 8AE9 MZ_CTRL7
9AH7 MZ_CTRL8 10 AL3 MZ_CTRL9
11 AJ3 MZ_CTRL10 12 AJ2 MZ_CTRL11
13 AN8 MZ_CTRL12 14 AN7 MZ_CTRL13
15 AH9 MZ_CTRL14 16 AE3 MZ_CTRL15
17 AE4 MZ_CTRL16 18 AD3 MZ_CTRL17
19 AD4 MZ_CTRL18 20 AA8 MZ_CTRL19
Daughter Board Control Signals Connections (J47)
Figure 8 shows the mechanical dimensions required for designing a daughter board.
Figure 8. Mechanical Drawing of the Daughter Board Connection
1.9"
0.2"
1.2"
0.45"
Daughter Board
(Size 3.2" x 2.5")
2.20"
0.3"
0.937"
0.0689"
0.4"
Circuit #1
J47
2.50"
Circuit #13
Circuit #1
Circuit #2 J17
J19
Circuit #1
Circuit #2
0.68"
1.4"
Circuit #12 Circuit #24
Circuit #10
LatticeECP3
ChannelLink and CameraLink Video Interfaces
There are two LVDS video interfaces on the board, ChannelLink and CameraLink. Both interfaces include a receive
channel, but only the ChannelLink interface includes a transmit channel. All of these channels use the same on-
board 3M MDR-26 (p/n 10226-1210VE) connectors. However, since the pinouts of these two interfaces are differ-
ent, different 3M Mini D Ribbon (MDR) cables must be used. The cables are listed below. They look the same but
have different pinouts.
17
LatticeECP3 Video Protocol Board – Revision C
User’s Guide
• 3M ChannelLink Cable: 14526-EZ8B-XXX-07C
• 3M CameraLink Cable: 14X26-SZLB-XXX-0LC
Other than the ChannelLink and CameraLink LVDS signals, some of the LVDS signals are also connected to the
two RJ45 connectors on J44 and J45. Tables 22 to 25 show the connections of these LVDS connectors.
Table 22. ChannelLink Tx Connections (J9)
Signal Name J9 Pin # LatticeECP3 Pin # LatticeECP3 Pin Type External Resistor
TX OUT0+ 15 AM29 True LVDS Output None
TX OUT0- 14 AN29
TX OUT1+ 5AL30 True LVDS Output None
TX OUT1- 4AM30
TX OUT2+ 7AJ31 True LVDS Output None
TX OUT2- 6AK31
TX OUT3+ 13 AA28 True LVDS Output None
TX OUT3- 12 AA27
TX CLKOUT+ 23 AH33 True LVDS Output None
TX CLKOUT- 22 AJ33
Table 23. ChannelLink Rx Connections (J10)
Signal Names J10 Pin # LatticeECP3 Pin# LatticeECP3 Pin Type External Resistor
RX IN0+ 12 V31 LVDS Input R65 (100 )
RX IN0- 13 V30
RX IN1+ 22 W34 LVDS Input R63 (100 )
RX IN1- 23 W33
RX IN2+ 20 W32 LVDS Input R60 (100 )
RX IN2- 21 W31
RX IN3+ 14 W29 LVDS Input R58 (100 )
RX IN3- 15 W28
RX CLKIN+ 4U28 LVDS Input R61 (100 )
RX CLKIN- 5V28
Table 24. RJ45 Connections (J44 and J45)
Signal Name Pin# LatticeECP3 Pin# LatticeECP3 Pin Type External Resistor
RJ45_OUT_P0 1 (J44) W27 True LVDS Output None
RJ45_OUT_N0 2 (J44) W26
RJ45_OUT_P1 3 (J44) AA25 True LVDS Output None
RJ45_OUT_N1 6 (J44) AA26
RJ45_OUT_P2 4 (J44) W30 Emulated LVDS Output None
RJ45_OUT_N2 5 (J44) W29
RJ45_OUT_P3 7 (J44) Y26 True LVDS Output None
RJ45_OUT_N3 8 (J44) Y25
RJ45_IN_P0 1 (J45) AM34 LVDS Input R65 (100 )
RJ45_IN_N0 2 (J45) AM33
RJ45_IN_P1 3 (J45) AC32 LVDS Input R63 (100 )
RJ45_IN_N1 6 (J45) AC31
18
LatticeECP3 Video Protocol Board – Revision C
User’s Guide
DVI Video Interface
There are two DVI video connectors on this board, one for DVI receive and the other for DVI transmit. The I/Os on
the banks 0 and 1 of LatticeECP3 support the TRLVDS (Transition Reduced LVDS) I/O standard and can be used
to receive video signals with TMDS standard such as DVI and HDMI. These I/Os can support a maximum band-
RJ45_IN_P2 4 (J45) AA34 LVDS Input R60 (100 )
RJ45_IN_N2 5 (J45) AA33
RJ45_IN_P3 7 (J45) P30 LVDS Input R58 (100 )
RJ45_IN_N3 8 (J45) R29
Table 25. CameraLink Rx Connections (J12)
Signal Name J12 Pin # LatticeECP3 Pin # LatticeECP3 Pin Type External Resistor
X0+ 12 U32 LVDS Input R80 (100 )
X0- 25 U31
X1+ 11 U34 LVDS Input R76 (100 )
X1- 24 U33
X2+ 10 T34 LVDS Input R71 (100 )
X2- 23 T33
X3+ 8T32 LVDS Input R68 (100 )
X3- 21 T31
XCLK+ 9U26 LVDS Input R70 (100 )
XCLK- 22 U27
SerTC+ 20 N30
Emulated LVDS Output
RN33A
165
165
140
ECP3
SerTC- 7N29
SerTFG+ 6P32 LVDS Input R206 (100 )
SerTFG- 19 P31
CC1+ 5R34
Emulated LVDS Output
RN32A
165
165
140
ECP3
CC1- 18 R33
CC2+ 17 R31
Emulated LVDS Output
RN32B
165
165
140
ECP3
CC2- 4R30
CC3+ 3P34
Emulated LVDS Output
RN31A
165
165
140
ECP3
CC3- 16 P33
CC4+ 15 N34
Emulated LVDS Output
RN31B
165
165
140
ECP3
CC4- 2N33
Table 24. RJ45 Connections (J44 and J45) (Continued)
Signal Name Pin# LatticeECP3 Pin# LatticeECP3 Pin Type External Resistor
19
LatticeECP3 Video Protocol Board – Revision C
User’s Guide
width of up to 1Gbps. The TMDS signals of DVI Rx connector (J16). For DVI Tx, the TMDS transmitter TFP410
from TI is used to convert and encode the parallel R, G, B pixel data to TMDS signals. These TMDS signals are
then connected to J14.
Tabl e s 26 and 27 show the LatticeECP3 pin connections to these two DVI connectors.
Table 26. DVI Rx Connections (J16)
J16 Pin # Pin Name LatticeECP3 Pin # Description
18 TMDS_Data0+ C16 TMDS Blue Data Channel
17 TMDS_Data0- D16
10 TMDS_Data1+ A16 TMDS Green Data Channel
9TMDS_Data1- B16
2TMDS_Data2+ C17 TMDS Red Data Channel
1TMDS_Data2- D17
23 TMDS_Clock0+ J17 TMDS Clock Channel
24 TMDS_Clock0- H17
6DDC_Clock D14 DVI Rx DDC Clock
7DDC_Data J15 DVI Rx DDC Data
16 Hot Plug Detect F13 DVI Rx Hot Plug Detect
Table 27. DVI Tx Connections (J14)
J14 Pin # J14 Pin Name TFP410 Pin TFP410 Pin # LatticeECP3 Pin # Description
18 and 17 TMDS_Data0+TMDS_Data0-
DATA7 54 A4 (MSB)
TMDS Blue Data Channel
DATA6 55 A5
DATA5 58 G12
DATA4 59 G13
DATA3 60 A12
DATA2 61 B12
DATA1 62 J14
DATA0 63 H13 (LSB)
10 and 9 TMDS_Data1+TMDS_Data1-
DATA15 44 B3 (MSB)
TMDS Green Data Channel
DATA14 45 A2
DATA13 46 D5
DATA12 47 C6
DATA11 50 B4
DATA10 51 A3
DATA9 52 D6
DATA8 53 C5 (LSB)
2 and 1 TMDS_Data2+TMDS_Data2-
DATA23 36 C3 (MSB)
TMDS Red Data Channel
DATA22 37 C4
DATA21 38 D3
DATA20 39 C2
DATA19 40 B1
DATA18 41 B2
DATA17 42 E4
DATA16 43 D4 (LSB)
6DDC_Clock — — C14 DVI Tx DDC Clock
20
LatticeECP3 Video Protocol Board – Revision C
User’s Guide
RS-232 Interface
A 2x5 header (J38) provides a RS-232 port connection to the LatticeECP3 device via a RS-232 transceiver
MAX232. Either the DB25 or DB9 cable can be connected to this header for providing a RS-232 pot with industrial
standard pinout. Ta b l e 28 shows the pin connections of this header.
Table 28. RS-232 Interface Header Pin Connections (J38)
J38 Pin # Pin Name Net Name LatticeECP3
Pin # J38 Pin # Pin Name Net Name LatticeECP3
Pin #
1 N.C. — — 2 N.C. — —
3TXD RS232_TXD F12 (Input) 4N.C. — —
5RXD RS232_RXD E11 (Output) 6N.C. — —
7 N.C. — — 8 N.C. — —
9 N.C. GND — 10 N.C. — —
LCD Interface
A 2x9 header (J43) provides a connection to LCD modules such as the 20-character x 2 line LCD module LCM-
S02002DSR or LCM-S02002DSR (with backlight LED) from Lumex. The board includes two variable resistors for
LCD adjustments. VR6 adjusts the backlight and VR5 provides contrast adjustment. A user design must be
included in the FPGA to drive this feature. This header can also be used for probe points for observing FPGA pins.
Pin 1 and Pin 2 of header J43 are dummy pins that connect to nothing. When installing the Lumex LCD module,
these two pins should be skipped. Ta bl e 29 shows the pin connections of this header.
Table 29. LCD Interface Header Pin Connections (J43)
J43 Pin# LatticeECP3
Pin # LCM-S02002
Pin # Net Names J43 Pin# LatticeECP3
Pin # LCM-S02002
Pin# Net Names
1 — — N.C. (Dummy) 2 — — N.C. (Dummy)
3 — 1 GND 4 — 2 5V
5 — 3 VO (Contrast) 6H15 4LCD5 / LCD_RS
7A8 5LCD0 / LCD_R/W 8E17 6LCD6 / LCD_E
9A9 7LCD1 / LCD_DB0 10 B14 8LCD7 / LCD_DB1
11 A7 9LCD2 / LCD_DB2 12 A14 10 LCD8 / LCD_DB3
13 E15 11 LCD3 / LCD_DB4 14 E13 12 LCD9 / LCD_DB5
15 D15 13 LCD4 / LCD_DB6 16 E12 14 LCD10 / LCD_DB7
17 —15 ANODE (Backlight) 18 —16 GND
7DDC_Data — — G15 DVI Tx DDC Data
— — IDCKP 57 K14 —
— — DE 2D13 —
— — VSYNC 5J13 —
— — HSYNC 4H14 —
— — ISEL/RSTN 13 G21 —
— — BSEL/SCL 15 B13 —
— — DSEL/SDA 14 A13 —
Table 27. DVI Tx Connections (J14) (Continued)
J14 Pin # J14 Pin Name TFP410 Pin TFP410 Pin # LatticeECP3 Pin # Description
21
LatticeECP3 Video Protocol Board – Revision C
User’s Guide
Switches and LEDs
There are many on-board DIP switches, push-button switches, discrete LEDs and a 16-segment LED display that
can be used to provide static inputs and outputs for a design. Figure 9 shows the locations of these components.
Figure 9. Switch and LED Locations
SW1 SW3 SW4
SW7
SW8
SW9
SW10
SW6
D10
D11
D12
D13
D14
D15
D16
D17
D22
D23
D24
D26
D30
DIP Switches (SW1, SW3 and SW4)
There are three SPDT toggle-DIP switches on this board. Each of these switches includes four positions to make a
total number of 12 static input signals to a design. Tabl e 30 shows the pin connections and colors of these LEDs.
Table 30. DIP Switch Connections
Switch # Position # Signal LatticeECP3 Pin # LatticeECP3 I/O Bank
(Voltage)
SW1
1SWITCH1 Y5
Bank 6 (1.8V)
2SWITCH2 Y4
3SWITCH3 Y9
4SWITCH4 Y10
SW3
1SWITCH5 AD2
2SWITCH6 AD1
3SWITCH7 AC6
4SWITCH8 AC7
SW4
1SWITCH9 AM1
2SWITCH10 AM2
3SWITCH11 AE1
4SWITCH12 AE2
22
LatticeECP3 Video Protocol Board – Revision C
User’s Guide
Push-button Switches (SW6, SW7, SW8, SW9 and SW10)
Five push-buttons can also be used to provide inputs that require pulses. There are de-bouncers between the
push-buttons and the LatticeECP3 to remove the glitches of the push-button signals. When pressing these push-
buttons, logic 0 will be sent to the connected LatticeECP3 pins. Ta bl e 31 shows the corresponding pin connections
between the push-buttons and the LatticeECP3 pins.
Table 31. Push-button Switch Connections
Signal Switch # LatticeECP3 Pin # LatticeECP3 I/O Bank
(Voltage)
GSRN SW6 J20 Bank 1 (2.5V)
PB4 SW7 U4
Bank 7 (1.8V)
PB3 SW8 U5
PB2 SW9 P1
PB1 SW10 P2
Discrete LEDs (D10~D17, D22~D24, and D26)
There are 12 discrete LEDs for use as status indicators. These 12 LEDs are divided into three groups, (D10, D11,
D12, D13), (D14, D15, D16, D17) and (D22, D23, D24, D26). Each group has four LEDs and each LED is in a dif-
ferent color. Ta b l e 32 shows the pin connections and colors of these LEDs.
Table 32. Discrete LED Connections
Signal LED # LatticeECP3 Pin # ECP3 I/O Bank
(Voltage) Color
LED12 D10 AA31
Bank 3 (2.5V)
Blue
LED11 D11 AN34 Green
LED10 D12 AN33 Orange
LED9 D13 AP33 Red
LED8 D14 AP32 Blue
LED7 D15 AL32 Green
LED6 D16 AK32 Orange
LED5 D17 N32
Bank 2 (2.5V)
Red
LED4 D22 N31 Blue
LED3 D23 T29 Green
LED2 D24 T28 Orange
LED1 D26 T27 Red
23
LatticeECP3 Video Protocol Board – Revision C
User’s Guide
16-Segment LED Display (D30)
The LatticeECP3 general-purpose I/O pins are connected to a 16-segment display, as shown in Ta b l e 33. These
pins can be driven low to illuminate the display segments.
Table 33. 16-Segment LED Display Connections
Segment LatticeECP3
Pin
AB
C
D
G
FE DP
H
TSR
KMN
UP
AH20
BA18
CG18
DD18
DP B18
EL19
FC19
GJ19
HK19
KG19
MH19
NK20
PF19
RH18
SJ18
TD19
UE18
Logic Analyzer Connector and Test Points
For debugging purposes, all unused LatticeECP3 I/Os are connected to connectors/headers for debugging a
design using test equipment such as logic analyzers or scopes.
Logic Analyzer Connector
An on-board Mictor connector is connected to many LatticeECP3 I/Os to make it easy to use a logic analyzer for
debugging the FPGA design. The Mictor connector pins are connected to different I/O banks with different Vccio
voltages. Users may need to configure the threshold voltage of the logic analyzer pod to match the signals being
monitored. Other than connecting to the Mictor connector, these LatticeECP3 pins are also connected to two stan-
dard 100-mil pitch headers for use with logic analyzers or scopes that do not support Mictor connection. Ta b l e 34
shows the LatticeECP3 pin connections to the Mictor connector and the two headers.
Table 34. Logic Analyzer Connections (J29, J35 and J36)
J29 Pin # Signal J35 Pin # J36 Pin # LatticeECP3
Pin # LatticeECP3 I/O
Bank (Volta ge )
1 —————
2 —————
3 — — — GND —
4 —————
5LA1 — 1 D33 Bank 8 (3.3V)
6LA2 1 — D31
7LA3 — 2 K15 Bank 0 (3.3V)
8LA4 2 — C13
24
LatticeECP3 Video Protocol Board – Revision C
User’s Guide
Known Issues
1. DDR2 Reference Voltage
There are two DDR2 devices on the board – U29 and U31. When the design is using only one DDR2 device,
the DDR2_REF signal for the unused DDR2 device will be pulled up by the unused LatticeECP3 pin. This pulls
the Vref voltage away from the 0.9V generated by the LP2997 voltage regulator to around 1.6~1.7V. The
DDR2 will not work with the wrong reference voltage; the DDR2 accesses will fail. The DDR2_REF generated
by LP2997 is connected to LatticeECP3 pin-V7(VREF1 of Bank 6 for the DDR2 device on U29) and pin-R9
(VREF1 of Bank 7 for the DDR2 device on U31). To avoid being pulled up to the wrong voltage, the unused
VREF1 pin cannot be left unused because all unused pins will be pulled up by default. The easiest workaround
is adding dummy logic with one input and one output, and then assigning this input pin to the unused VREF1
pin.
9LA5 — 3 J22
Bank 1 (2.5V)
10 LA6 3 — J23
11 LA7 — 4 F22
12 LA8 4 — G23
13 LA9 — 5 A24
14 LA10 5 — B24
15 LA11 — 6 H22
16 LA12 6 — H23
17 LA13 — 7 K23
18 LA14 7 — K24
19 LA15 — 8 C28
20 LA16 8 — D28
21 LA17 — 9 G26
22 LA18 9 — AA2
Bank 6 (1.8V)
23 LA19 —10 AJ6
24 LA20 10 —AL8
25 LA21 —11 AM5
26 LA22 11 — AM6
27 LA23 —12 AN6
28 LA24 12 —AL7
29 LA25 —13 AM4
30 LA26 13 —AP5
31 LA27 —14 AP6
32 LA28 14 — — —
33 LA29 —15 — —
34 LA30 15 — — —
35 LA31 —16 — —
36 LA32 16 — — —
37 LA33 —17 — —
38 LA34 17 — — —
Table 34. Logic Analyzer Connections (J29, J35 and J36) (Continued)
J29 Pin # Signal J35 Pin # J36 Pin # LatticeECP3
Pin # LatticeECP3 I/O
Bank (Volta ge)
25
LatticeECP3 Video Protocol Board – Revision C
User’s Guide
2. DDR2 Bandwidth
This board does not include the recommended DDR2 termination resistors. Because of this, DDR2 may not
work correctly on this board at all frequencies. Performance on individual boards may vary, but testing shows
the best results at 125MHz, 150 MHz and 250MHz. 200MHz operation may be compromised due to this termi-
nation issue. It has also been found that U31 tends to have such issue more likely than U29. Based on the
above findings, the following is strongly recommended when using the on-board DDR2 memory:
– If only one memory device is needed, U29 is recommended over U31.
– DDR2 memory operating frequency around 200 MHz on this board should be avoided if possible.
If the operating frequency around 200 MHz cannot be avoided, the following may help work around or mitigate
the issue:
– Set the DDR2 memory interface related pins on FPGA DRIVE = 8 and SLEWRATE = SLOW in Design
Planner.
– Change the on-die-termination (ODT) of the DDR2 memory device. This can be done by setting the
desired value for the extended mode register. ODT = 50 appears to be better than the others on the
board tested, but this may vary from board to board. Users may wish to experiment with different ODT
options to determine the best ODT value.
Ordering Information
Description Ordering Part Number China RoHS Environment-Friendly
Use Period (EFUP)
LatticeECP3 Video Protocol Board LFE3-95EA-V-EVN1
1. Some early revision C LatticeECP3 Video Protocol Boards have the LatticeECP3 “E” device installed (LFE3-95E-V-EVN). For these
boards, see TN1180, LatticeECP3 High-Speed I/O Interface, for information on the differences between the LatticeECP3 “E” and “EA”
devices.
Technical Support Assistance
Hotline: 1-800-LATTICE (North America)
+1-503-268-8001 (Outside North America)
e-mail: techsupport@latticesemi.com
Internet: www.latticesemi.com
Revision History
Date Version Change Summary
March 2010 01.0 Initial release.
March 2011 01.1 Added Known Issues text section.
May 2011 01.2 Updated Ordering Information table for LFE3-95EA-V-EVN part number.
October 2012 01.3 Updated document with new corporate logo.
Updated LatticeECP3 pin numbers in the Push-button Switch Connec-
tions table.
FPGA Configuration schematic – Updated name of PR5A in the ECP3
Configuration I/Os section.
© 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as
listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of
their respective holders. The specifications and information herein are subject to change without notice.
26
LatticeECP3 Video Protocol Board – Revision C
User’s Guide
Appendix A. Schematic
Figure 10. Block Diagram
5
5
4
4
3
3
2
2
1
1
DD
C C
B B
A A
Title
Size Project Rev
Date: Sheet of
Lattice Semiconductor Corporation
5555 N.E. Moore Court
Hillsboro, Oregon. 97124
ECP3 Video Protocol Board Schematic
C
Block Diagram
C
116Tuesday, March 09, 2010
Title
Size Project Rev
Date: Sheet of
Lattice Semiconductor Corporation
5555 N.E. Moore Court
Hillsboro, Oregon. 97124
ECP3 Video Protocol Board Schematic
C
Block Diagram
C
116Tuesday, March 09, 2010
Title
Size Project Rev
Date: Sheet of
Lattice Semiconductor Corporation
5555 N.E. Moore Court
Hillsboro, Oregon. 97124
ECP3 Video Protocol Board Schematic
C
Block Diagram
C
116Tuesday, March 09, 2010
FPGA Config
(Sheet 6)
TI ADC
(Sheet 11)
(Sheet 12)
16-Seg LED
ECP3
FPGA
Bank8
(Sheet 6)
Bank0 Bank1
Bank2
Bank3
(Sheet 10)
(Sheet 11)(Sheet 9)
(Sheet 10)
(Sheet 10)
(Sheet 11)
Clocks
(Sheet 12)
(Sheet 10)
LEDs
Channel-Link
Tx/Rx
Camera-Link Rx
Bank7
(Sheet 8)
Bank6
(Sheet 8)
(Sheet 12)
(Sheet 8)
DDR2 Memory
RS232
DVI
(Sheet 9)
(Sheet 9)
LCD
(Sheet 9)
SerDes
(Sheet 7)
Quad B Quad A Quad C
PCIe x4
(Sheet 7)
Mezzanine
Connector
(Sheet 7)
(Sheet 13)
SDI
Cable Drivers &
Cable Equalizers
(Sheet 3)
Power
Generation
(Sheet 5)
FPGA
Power
(Sheet 4)
Power
Management
SDI
Reference
Clock
Control
(Sheet 14)
Other Devices
RJ45 Tx/Rx
(Sheet 10)
(Sheet 15, Sheet 16)
SDI
Rx Reference Clock &
Tx Reference Clock
(Sheet 7)
DisplayPort
(1156fpBGA)
ECP3 Video Protocol Board
Switches
Push Buttons
(Sheet 12)
27
LatticeECP3 Video Protocol Board – Revision C
User’s Guide
Figure 11. Assembly Drawing
5
5
4
4
3
3
2
2
1
1
DD
C C
B B
A A
Title
Size Project Rev
Date: Sheet of
Lattice Semiconductor Corporation
5555 N.E. Moore Court
Hillsboro, Oregon. 97124
ECP3 Video Protocol Board Schematic
C
Assembly Drawing
C
216Friday, March 19, 2010
Title
Size Project Rev
Date: Sheet of
Lattice Semiconductor Corporation
5555 N.E. Moore Court
Hillsboro, Oregon. 97124
ECP3 Video Protocol Board Schematic
C
Assembly Drawing
C
216Friday, March 19, 2010
Title
Size Project Rev
Date: Sheet of
Lattice Semiconductor Corporation
5555 N.E. Moore Court
Hillsboro, Oregon. 97124
ECP3 Video Protocol Board Schematic
C
Assembly Drawing
C
216Friday, March 19, 2010
28
LatticeECP3 Video Protocol Board – Revision C
User’s Guide
Figure 12. Power Generation
5
5
4
4
3
3
2
2
1
1
DD
C C
B B
A A
3_3VIN 3_3VIN3_3VIN
SERDES_PWR_EN SERDES_PWR_EN SERDES_PWR_ENSERDES_PWR_EN
3_3VIN
3_3VIN
12_0VIN
12_0V
12_0VIN
12_0V 12_0V
12_0VIN
12_0V
2_5V
5_0V
12_0V
5_0V
3_3V_SDI_DE
12_0V
12_0V
3_3V VCC_CORE3_3VIN
1_8V 1_2V_A
1_2V_IO 1_5V_IO
5_0V
3_3V_SDI_CLK
2_5V_EN[4]
VCC_TRIM[4]
3_3_TRIM [4]
CORE_EN[4]
3_3V_GATE[4]
1_8V_EN[4] SERDES_PWR_EN[4]
5_0_TRIM [4]
VCCA_TRIM[4]
1_8_TRIM[4]
2_5_TRIM[4]
5_0V_EN[4]
Title
Size Project Rev
Date: Sheet of
Lattice Semiconductor Corporation
5555 N.E. Moore Court
Hillsboro, Oregon. 97124
ECP3 Video Protocol Board Schematic
C
Power Generation
C
316Wednesday, November 04, 2009
Title
Size Project Rev
Date: Sheet of
Lattice Semiconductor Corporation
5555 N.E. Moore Court
Hillsboro, Oregon. 97124
ECP3 Video Protocol Board Schematic
C
Power Generation
C
316Wednesday, November 04, 2009
Title
Size Project Rev
Date: Sheet of
Lattice Semiconductor Corporation
5555 N.E. Moore Court
Hillsboro, Oregon. 97124
ECP3 Video Protocol Board Schematic
C
Power Generation
C
316Wednesday, November 04, 2009
GND Vias (40-mil) for soldering pins.
Distributed around the board as GND
reference for test equipments.
12VIN GOOD
+12VDC
GND
POWER INPUT
2.5V
5.0V
3.3V
for SD/HD/3G-SDI
Cable Drivers and
Equalizers
1.2V Core
3.3V
1.8V 1.2V
1.2V
for SerDes
I/O Buffer
1.5V
for SerDes
I/O Buffer
Vout = 1.21 * ( 1 + 191/180 ) + 0.000003 * 191 = 2.4945V
Vout = 1.21 * ( 1 + 191/390 ) + 0.000003 * 191 = 1.8032V
Vout = 1.21 * ( 1 + 0/390 ) + 0.000003 * 0 = 1.21V
Vout = 1 + (113/560) = 1.2018V Vout = 1 + (113/226) = 1.5000VVout = 1 + (390/169) = 3.3078V
3.3V
for SD/HD/3G-SDI
Clocking Circuitry
Vout = 1 + (390/169) = 3.3078V
fz = 1 / (2*3.1416*390*0.01uF) = 40KHz
fz is within the recommanded 20KHz to 100KHz range
fz = 1 / (2*3.1416*390*0.01uF) = 40KHz
fz is within the recommanded 20KHz to 100KHz range
fz = 1 / (2*3.1416*113*0.01uF) = 140KHz
fz is within the recommanded 50KHz to 200KHz range
fz = 1 / (2*3.1416*113*0.01uF) = 140KHz
fz is within the recommanded 50KHz to 200KHz range
Voltage adjustment range : 1.0V to 1.2V
Turn clockwise to increase the voltage
J39
HEADER 2x1
J39
HEADER 2x1
1
2
U16
LT
LT1764AEQ#PBF
U16
LT
LT1764AEQ#PBF
SHDN 1
IN 2
GND 3
OUT 4
ADJ 5
GND6
6
C377
22uF, X5R, 6.3V
0805
C377
22uF, X5R, 6.3V
0805
12
GP10GP10
R340 0RR340 0R
R331OPENR331OPEN
U14
LT
LT1764AEQ#PBF
U14
LT
LT1764AEQ#PBF
SHDN 1
IN 2
GND 3
OUT 4
ADJ 5
GND6
6
+
C267
100uF, Tant
EIA3528
+
C267
100uF, Tant
EIA3528
F6
0154010.DR
FUSEBLOCK W/10A FUSE SMD
F6
0154010.DR
FUSEBLOCK W/10A FUSE SMD
F2
0154003.DR
FUSEBLOCK W/3A FUSE SMD
F2
0154003.DR
FUSEBLOCK W/3A FUSE SMD
GP14GP14 GP11GP11
R341
0R
R341
0R
R120
10K
R120
10K
D7
SCHOTTKY
V12P10-E3/87A
Vishay
D7
SCHOTTKY
V12P10-E3/87A
Vishay
C64
0.01uF, NPO
1206
C64
0.01uF, NPO
1206
1 2
C373
22uF, X5R, 6.3V
0805
C373
22uF, X5R, 6.3V
0805
12
GP15GP15
R322 12.1KR322 12.1K R342
280
R342
280
TB1
Terminal Block
ED120/2DS
TB1
Terminal Block
ED120/2DS
1
2
F5
0154010.DR
FUSEBLOCK W/10A FUSE SMD
F5
0154010.DR
FUSEBLOCK W/10A FUSE SMD
C380
0.01uF, NPO
1206
C380
0.01uF, NPO
1206
1 2
+
C412
10uF, Tant
0805
+
C412
10uF, Tant
0805
C34
0.01uF
C34
0.01uF
1 2
C298
22uF, X5R, 6.3V
0805
C298
22uF, X5R, 6.3V
0805
12
GP22GP22
R122
191, 1%
R122
191, 1%
+
C266
33uF, Tant
0805
+
C266
33uF, Tant
0805
+
C264
100uF, Tant
EIA3528
+
C264
100uF, Tant
EIA3528
+
C419
10uF, Tant
0805
+
C419
10uF, Tant
0805
U40
PTH12060W
U40
PTH12060W
GND1
1
VIN
2
INHIBIT#
3
ADJUST
4
SENSE 5
VOUT 6
GND7
7TRACK 8
MDWN 9
MUP 10
GP20GP20
Q28
NTMS4503NR2G
SOIC-8
Q28
NTMS4503NR2G
SOIC-8
S1 1
S2 2
S3 3
G4
D1
5D2
6D3
7D4
8
+
C422
10uF, Tant
0805
+
C422
10uF, Tant
0805
F7
0154010.DR
FUSEBLOCK W/10A FUSE SMD
F7
0154010.DR
FUSEBLOCK W/10A FUSE SMD
GP17GP17
C368
0.01uF
C368
0.01uF
1 2
+
C285
33uF, Tant
0805
+
C285
33uF, Tant
0805
D35
LED-SMT1206_GREEN
D35
LED-SMT1206_GREEN
R318 0RR318 0R
GP19GP19GP23GP23
R132
390, 1%
R132
390, 1%
U27
NS
LP3878MR-ADJ/NOPB
U27
NS
LP3878MR-ADJ/NOPB
BYPASS
1
NC1
2
GND3
3
IN
4OUT 5
ADJ 6
NC2 7
SHDN 8
GND9
9
R121
390, 1%
R121
390, 1%
GP7GP7
+
C273
100uF, Tant
EIA3528
+
C273
100uF, Tant
EIA3528
U26
NS
LP3878MR-ADJ/NOPB
U26
NS
LP3878MR-ADJ/NOPB
BYPASS
1
NC1
2
GND3
3
IN
4OUT 5
ADJ 6
NC2 7
SHDN 8
GND9
9
GP24GP24
R124
10K
R124
10K
R323 OPENR323 OPEN
R134
10K
R134
10K
R324 0RR324 0R
C324
0.01uF
C324
0.01uF
1 2
+
C413
330uF, Tant
+
C413
330uF, Tant
C56
22uF, X5R, 6.3V
0805
C56
22uF, X5R, 6.3V
0805
12
U20
NS
LP3878MR-ADJ/NOPB
U20
NS
LP3878MR-ADJ/NOPB
BYPASS
1
NC1
2
GND3
3
IN
4OUT 5
ADJ 6
NC2 7
SHDN 8
GND9
9
GP2GP2
GP4GP4
C367
0.01uF
C367
0.01uF
1 2
GP8GP8
U4
NS
LP3878MR-ADJ/NOPB
U4
NS
LP3878MR-ADJ/NOPB
BYPASS
1
NC1
2
GND3
3
IN
4OUT 5
ADJ 6
NC2 7
SHDN 8
GND9
9
R326OPENR326OPEN
F4
0154003.DR
FUSEBLOCK W/3A FUSE SMD
F4
0154003.DR
FUSEBLOCK W/3A FUSE SMD
GP1GP1
+
C418
330uF, Tant
+
C418
330uF, Tant
R115
191, 1%
R115
191, 1%
GP13GP13
R325
0R
R325
0R
R188
113, 1%
R188
113, 1%
C41
22uF, X5R, 6.3V
0805
C41
22uF, X5R, 6.3V
0805
12
U12
LT
LT1764AEQ#PBF
U12
LT
LT1764AEQ#PBF
SHDN 1
IN 2
GND 3
OUT 4
ADJ 5
GND6
6
R189
113, 1%
R189
113, 1%
R328 0RR328 0R
F1
0154003.DR
FUSEBLOCK W/3A FUSE SMD
F1
0154003.DR
FUSEBLOCK W/3A FUSE SMD
GP9GP9
R16
390, 1%
R16
390, 1%
GP16GP16
U17
PTH12060L
U17
PTH12060L
GND1
1
VIN
2
INHIBIT#
3
ADJUST
4
SENSE 5
VOUT 6
GND7
7TRACK 8
MDWN 9
MUP 10
R114
180, 1%
R114
180, 1%
R190
560, 1%
R190
560, 1%
VR4
20K
ST32ETB203
Copal
VR4
20K
ST32ETB203
Copal
13
2
C378
22uF, X5R, 6.3V
0805
C378
22uF, X5R, 6.3V
0805
12
GP5GP5
+
C416
10uF, Tant
0805
+
C416
10uF, Tant
0805
R17
169, 1%
R17
169, 1%
C415
0.01uF
C415
0.01uF
12
R191
226, 1%
R191
226, 1%
GP3GP3
GP21GP21
R334
680
PCB Footprint = 1206
R334
680
PCB Footprint = 1206
J15
Power Jack
Male Power Jack 2.1mm 2.5A 16V
PJ-002A
J15
Power Jack
Male Power Jack 2.1mm 2.5A 16V
PJ-002A
1
3
2
+
C282
100uF, Tant
EIA3528
+
C282
100uF, Tant
EIA3528
R176
169, 1%
R176
169, 1%
C381
0.01uF, NPO
1206
C381
0.01uF, NPO
1206
1 2
GP18GP18
C374
22uF, X5R, 6.3V
0805
C374
22uF, X5R, 6.3V
0805
12
+
C286
330uF, Tant
+
C286
330uF, Tant
+
C268
33uF, Tant
0805
+
C268
33uF, Tant
0805
GP6GP6
+
C421
330uF, Tant
+
C421
330uF, Tant
R339 OPEN
R339 OPEN
R321
2K
R321
2K
F3
0154010.DR
FUSEBLOCK W/10A FUSE SMD
F3
0154010.DR
FUSEBLOCK W/10A FUSE SMD
U18
PTH12060W
U18
PTH12060W
GND1
1
VIN
2
INHIBIT#
3
ADJUST
4
SENSE 5
VOUT 6
GND7
7TRACK 8
MDWN 9
MUP 10
C289
0.01uF, NPO
1206
C289
0.01uF, NPO
1206
1 2
R178
390, 1%
R178
390, 1%
GP12GP12
C316
22uF, X5R, 6.3V
0805
C316
22uF, X5R, 6.3V
0805
12
29
LatticeECP3 Video Protocol Board – Revision C
User’s Guide
Figure 13. Power Management
5
5
4
4
3
3
2
2
1
1
DD
C C
B B
A A
HVOUT1
PAC_MCLK
PLDCLK
PAC_RESETn
PAC_VPS1
PAC_VPS0
TDI_ PA C
TCK_PAC
TMS_PAC
TDO_PAC
TDIS EL _P AC
ATDI_PAC
2_5V
PWR_GOOD_VCCA
PWR_GOOD_VCC
PWR_GOOD_3_3V
PWR_GOOD_2_5V
PWR_GOOD_5_0V
PWR_GOOD_1_8V
PWR_GOOD_VCCA
PWR_GOOD_VCC
PWR_GOOD_3_3V
PWR_GOOD_2_5V
PWR_GOOD_5_0V
PWR_GOOD_1_8V
PWR_GOOD_VCCA
PWR_GOOD_VCC
PWR_GOOD_3_3V
PWR_GOOD_2_5V
PWR_GOOD_5_0V
PWR_GOOD_1_8V
TRIM8
TRIM7
TRIM1
TRIM2
TRIM3
TRIM4
TRIM5
TRIM6
TRIM5
TRIM6
TRIM2
TRIM3
TRIM4
TRIM1
PAC_IN3
PAC_IN4
PAC_IN5
PAC_VMON12
PAC_VMON11
PAC_VMON10
PAC_VMON9
PAC_OUT9
PAC_OUT8
PAC_OUT7
PAC_OUT6
PAC_OUT5
HVOUT4
HVOUT3
HVOUT2
TCK_PAC
TDO_PAC
TDI_ PA C
TMS_PAC
3_3V
3_3VIN
3_3VIN
3_3VIN
3_3VIN
3_3VIN
3_3VIN
3_3VIN
3_3VIN
3_3VIN
2_5V
3_3VIN
3_3VIN
12_0VIN
12_0V
VCC_CORE
3_3V
1_2V_A
5_0V
1_8V
2_5V
3_3V
3_3VIN
TEMP[6]
TEMP_GND[6]
I2C_SDA [9,13,14]
I2C_SCL [9,13,14]
3_3V_GATE [3]
5_0V_EN [3]
1_8V_EN [3]
2_5V_EN [3]
CORE_EN [3]
SERDES_PWR_EN [3]
VCC_TRIM [3]
3_3_TRIM [3]
VCCA_TRIM [3]
1_8_TRIM [3]
2_5_TRIM [3]
5_0_TRIM [3]
TDO_ PAC [6 ]
TDI_ PA C [6 ]
TCK_ PAC [6 ]
TMS_ PAC [6 ]
DONE_ECP3[6]
INITN_ECP3[6]
GSRN[6,11]
Title
Size Project Rev
Date: Sheet of
Lattice Semiconductor Corporation
5555 N.E. Moore Court
Hillsboro, Oregon. 97124
ECP3 Video Protocol Board Schematic
C
Power Management
C
416Wednesday, November 04, 2009
Title
Size Project Rev
Date: Sheet of
Lattice Semiconductor Corporation
5555 N.E. Moore Court
Hillsboro, Oregon. 97124
ECP3 Video Protocol Board Schematic
C
Power Management
C
416Wednesday, November 04, 2009
Title
Size Project Rev
Date: Sheet of
Lattice Semiconductor Corporation
5555 N.E. Moore Court
Hillsboro, Oregon. 97124
ECP3 Video Protocol Board Schematic
C
Power Management
C
416Wednesday, November 04, 2009
EEPROM
1.8V
2.5V
3.3V
5.0V
VCCA
VCC CORE
LDO
POL
LDO
LP3878
VCC_CORE,
(+1.2v, 10A)
3_3VIN,
(+3.3V, 10A)
1_5V_IO, SerDes I/O Buffer
(+1.5V, 0.8A)
3_3V,
(+3.3V, 3.2A)
ispPAC
12V INPUT
PCIe Edge
12V Wall Adapter
12V Input Terminal
1_8V, DDR2
(+1.8V, 3A)
1_2V_A, SerDes
(+1.2V, 3A)
2_5V, LVDS
(+2.5V, 3A)
LDO 1_2V_IO, SerDes I/O Buffer
(+1.2V, 0.8A)
LP3878
POL
PTH12060W
PTH12060L
LDO
LP3878
LDO
LP3878
3_3V_SDI_CLK,
SDI Clock
(+3.3V, 0.8A)
DP_RX_PWR_OUT,
DisplayPort Rx
(+3.3V, 0.8A)
DP_TX_PWR_OUT,
DisplayPort Tx
(+3.3V, 0.8A)
LDO
LT1764
LDO
LT1764
LDO
LT1764
MOSFET
NTR4501N
5_0V, LCD
(+5V,10A)
LP3878
LDO
LP3878
3_3V_SDI_DE,
SerDes VCCAUX
Drivers/Equalizers
(+3.3V, 0.8A)
Top View
1(Anode)
2(Anode)
3(Cathode)
SOT-23
BAV74LT1
Monolithic Dual
Switching Diode
POL
PTH12060W
R265 OPENR265 OPEN
TP25TP25
TP33TP33
R259
3K
R259
3K
U35
EEPROM
24AA1025-I/SM
Microchip
U35
EEPROM
24AA1025-I/SM
Microchip
GND
4VCC 8
SDA 5
SCL 6
A0
1
A1
2
A2
3WP 7
R281 OPENR281 OPEN
D31 LED-SMT1206_GREEND31 LED-SMT1206_GREEN
TP19TP19
TP16TP1 6
R315 100R315 100
TP20TP2 0
TP24TP24
R261
1K
R261
1K
R286 OPENR286 OPEN
TP18TP18
C400
0.1uF
C400
0.1uF
12
R291 10KR291 10K
R125
10K
R125
10K
Q8
2N2222
MMBT2222ALT1G
Q8
2N2222
MMBT2222ALT1G
3
1
2
D25
BAV74/SOT
D25
BAV74/SOT
3
1
2
RN26 1K EXB28V102JVRN26 1K EXB28V102JV
1
2
3
4
8
7
6
5
TP39TP39
R258 226, 1%R258 226, 1%
R282 OPENR282 OPEN
R307 0R
R307 0R
C398
0.1uF
C398
0.1uF
12
R133
10K
R133
10K
R267 OPENR267 OPEN
R296 10KR296 10K
D28 LED-SMT1206_GREEND28 LED-SMT1206_GREEN
R314 150R314 150
C278
0.01uF
C278
0.01uF
12
R295 OPENR295 OPEN
C396
0.1uF
C396
0.1uF
Q7
2N2222
MMBT2222ALT1G
Q7
2N2222
MMBT2222ALT1G
3
1
2
R270 10KR270 10K
R269 OPENR269 OPEN
R279 10KR279 10K
C271
0.1uF
C271
0.1uF
12
R266
0R
R266
0R
D32 LED-SMT1206_GREEND32 LED-SMT1206_GREEN
R308 0R
R308 0R
TP21TP21
R276 OPENR276 OPEN
C275
0.01uF
C275
0.01uF
12
R283 OPENR283 OPEN
R131
10K
R131
10K
TP37TP3 7
TP34TP3 4
R306 150R306 150
Q10
2N2222
MMBT2222ALT1G
Q10
2N2222
MMBT2222ALT1G
3
1
2
+
C269
22uF, Tant
0805
+
C269
22uF, Tant
0805
R280 150R280 150
R277 OPENR277 OPEN
R272
0R
R272
0R
R278 OPENR278 OPEN
D33 LED-SMT1206_GREEND33 LED-SMT1206_GREEN
TP32TP3 2
TP38TP3 8
TP23TP2 3
R313 10KR313 10K
R288 150R288 150
C276
1uF, X5R, 6.3V
C276
1uF, X5R, 6.3V
R273 OPENR273 OPEN
R123
10K
R123
10K
TP28TP28
R275 OPENR275 OPEN
C397
2200pF
C397
2200pF
D29 LED-SMT1206_GREEND29 LED-SMT1206_GREEN
C277
0.1uF
C277
0.1uF
12
R305 10KR305 10K
R285 OPENR285 OPEN
TP17TP1 7
C399
0.1uF
C399
0.1uF
12
TP35TP3 5
R268 OPENR268 OPEN
TP26
TP
TP26
TP
R135
10K
R135
10K
R274 OPENR274 OPEN
U34
MAX6692
U34
MAX6692
VCC
1
GND
5
DXP
2
SDA 7
SCLK 8
ALERT 6
OVERT 4
DXN
3
ispPAC
Lattice
U36
POWR1220AT8
TQFP 100
ispPAC
Lattice
U36
POWR1220AT8
TQFP 100
OUT20 25
OUT19 24
OUT18 23
OUT17 21
OUT16 20
OUT15 19
OUT14 18
OUT13 17
OUT12 16
OUT11 15
OUT10 14
OUT9 12
OUT8 11
OUT7 10
OUT6 9
SMBA/OUT5 8
HVOUT4 40
HVOUT3 42
HVOUT2 85
HVOUT1 86
TRIM8 73
TRIM7 74
TRIM6 75
TRIM5 79
TRIM4 80
TRIM3 82
TRIM2 83
TRIM1 84
VMON1+
47
VMON2+
50
VMON3+
52
VMON4+
54
VMON5+
56
VMON6+
58
VMON7+
62
VMON8+
64
VMON9+
66
VMON10+
68
VMON11+
70
VMON12+
72
VMON1GS
46
VMON2GS
48
VMON3GS
51
VMON4GS
53
VMON5GS
55
VMON6GS
57
VMON7GS
61
VMON8GS
63
VMON9GS
65
VMON10GS
67
VMON11GS
69
VMON12GS
71
IN6 7
IN5 6
IN4 4
IN3 2
IN2 1
IN1 97
GNDD3
3
GNDD22
22
GNDD36
36
GNDD43
43
GNDD88
88
GNDD98
98
GNDA87
87
GNDA45
45
VCCD94
94 VCCD38
38 VCCD13
13
VCCA
60
VCCPROG
39
VCCINP 5
VCCJ 33
TDO 34
TDI 31
ATDI 30
TMS 28
TCK 37
TDISEL 32
SCL 92
SDA 93
VPS0 89
VPS1 90
MCLK 96
PLDCLK 95
RESETb 91
NC6
49
NC7
76
NC1
26
NC2
27
NC3
29
NC4
35
NC5
41
NC8
77
NC9
78
RES2 59
NC12 100
NC11 99
NC10
81 RES1 44
TP22TP2 2
R29010K R29010K
R297 150R297 150
R292
10K
R292
10K
R264 OPENR264 OPEN
R263 OPENR263 OPEN
R262
1K
R262
1K
TP36TP3 6
D27 LED-SMT1206_GREEND27 LED-SMT1206_GREEN
R287 10KR287 10K
R29810K R29810K
R271 150R271 150
R260
3K
R260
3K
Q9
2N2222
MMBT2222ALT1G
Q9
2N2222
MMBT2222ALT1G
3
1
2
R284 OPENR284 OPEN
Q11
2N2222
MMBT2222ALT1G
Q11
2N2222
MMBT2222ALT1G
3
1
2
TP27TP27
TP15TP1 5
30
LatticeECP3 Video Protocol Board – Revision C
User’s Guide
Figure 14. FPGA Power
5
5
4
4
3
3
2
2
1
1
DD
C C
B B
A A
VCC_CORE
VCC_CORE
VCC_CORE
3_3V
1_2V_A
VCCPLL
VCC_CORE
2_5V
3_3V
VCCPLL
1_2V_A
3_3V
1_8V
3_3V
Title
Size Project Rev
Date: Sheet of
Lattice Semiconductor Corporation
5555 N.E. Moore Court
Hillsboro, Oregon. 97124
ECP3 Video Protocol Board Schematic
C
FPGA Power
C
516Wednesday, November 04, 2009
Title
Size Project Rev
Date: Sheet of
Lattice Semiconductor Corporation
5555 N.E. Moore Court
Hillsboro, Oregon. 97124
ECP3 Video Protocol Board Schematic
C
FPGA Power
C
516Wednesday, November 04, 2009
Title
Size Project Rev
Date: Sheet of
Lattice Semiconductor Corporation
5555 N.E. Moore Court
Hillsboro, Oregon. 97124
ECP3 Video Protocol Board Schematic
C
FPGA Power
C
516Wednesday, November 04, 2009
ALL CAPS PLACED UNDER BGA
ALL CAPS PLACED UNDER BGA
ALL CAPS PLACED UNDER BGA
C177
0.01uF
C177
0.01uF
12
C158
0.1uF
C158
0.1uF
12
C220
0.01uF
C220
0.01uF
12
C154
1000pF
C154
1000pF
12
C170
0.01uF
C170
0.01uF
12
C156
0.1uF
C156
0.1uF
12
C209
1000pF
C209
1000pF
12
VCC CORE
ECP3-95
U30I
VCC CORE
ECP3-95
U30I
VCC1 AA13
VCC2 AA22
VCC3 AB13
VCC4 AB14
VCC5 AB15
VCC6 AB16
VCC7 AB17
VCC8 AB18
VCC9 AB19
VCC10 AB20
VCC11 AB21
VCC12 AB22
VCC13 N13
VCC14 N14
VCC15 N15
VCC16 N16
VCC17 N17
VCC18 N18
VCC19 N19
VCC20 N20
VCC21 N21
VCC22 N22
VCC23 P13
VCC24 P22
VCC25 R13
VCC26 R22
VCC27 U13
VCC28 U22
VCC29 V13
VCC30 V22
VCC31 Y13
VCC32 Y22
C164
0.1uF
C164
0.1uF
12
C181
1000pF
C181
1000pF
12
C211
1000pF
C211
1000pF
12
OTHER SUPPLIES
ECP3-95
U30J
OTHER SUPPLIES
ECP3-95
U30J
VCCA1 AD16
VCCA2 AD18
VCCA3 AE19
VCCA4 AC17
VCCA5 AC18
VCCA6 AD13
VCCA7 AE16
VCCA8 AD17
VCCA9 AC22
VCCA10 AE23
VCCA11 AE12
VCCA12 AD22
VCCA13 AE22
VCCA14 AC13
VCCA15 AE13
VCCA16 AD19
VCCAUX1 Y23
VCCAUX2 AA23
VCCAUX3 P12
VCCAUX4 AC20
VCCAUX5 AC14
VCCAUX6 M20
VCCAUX7 AA12
VCCAUX8 Y12
VCCAUX9 R12
VCCAUX10 AC15
VCCAUX11 AC21
VCCAUX12 M21
VCCAUX13 R23
VCCAUX14 M15
VCCAUX15 M14
VCCAUX16 P23
VCCPLL_L_1 T13
VCCPLL_L_2 W13
VCCPLL_R_1 T22
VCCPLL_R_2 W22
VSS
ECP3-95
U30L
VSS
ECP3-95
U30L
GND115 A1
GND116 A34
GND117 AA11
GND118 AA14
GND119 AA15
GND120 AA16
GND121 AA17
GND122 AA18
GND123 AA19
GND124 AA20
GND125 AA21
GND126 AA24
GND127 AA32
GND128 AA6
GND129 AC11
GND130 AC16
GND131 AC19
GND132 AC24
GND133 AC29
GND134 AC3
GND135 AD11
GND136 AD12
GND137 AD14
GND138 AD15
GND139 AD20
GND140 AD21
GND141 AD23
GND142 AD24
GND143 AD32
GND144 AD6
GND145 AE10
GND146 AE11
GND147 AE17
GND148 AE18
GND149 AE24
GND150 AE25
GND151 AF10
GND152 AF2
GND153 AF25
GND154 AF30
GND155 AF33
GND156 AF5
GND157 AG10
GND158 AG25
GND159 AG27
GND160 AG8
GND161 AH10
GND162 AH11
GND163 AH14
GND164 AH17
GND165 AH18
GND166 AH21
GND167 AH24
GND168 AH25
GND169 AJ10
GND170 AJ11
GND171 AJ12
GND172 AJ13
GND173 AJ14
GND174 AJ15
GND175 AJ16
GND176 AJ17
GND177 AJ18
GND178 AJ19
GND179 AJ20
GND180 AJ21
GND181 AJ22
GND182 AJ23
GND183 AJ24
GND184 AJ25
GND185 AJ26
GND186 AJ9
GND187 AK2
GND188 AK26
GND189 AK30
GND190 AK33
GND191 AK5
GND192 AK9
GND193 AL26
GND194 AL9
GND195 AM10
GND196 AM11
GND197 AM12
GND198 AM13
GND199 AM14
GND200 AM15
GND201 AM16
GND202 AM17
GND203 AM18
GND204 AM19
GND205 AM20
GND206 AM21
GND207 AM22
GND208 AM23
GND209 AM24
GND210 AM25
GND211 AM26
GND212 AM9
GND213 AN26
GND214 AN30
GND215 AN5
GND216 AN9
GND217 AP1
GND218 AP26
GND219 AP34
GND220 AP9
GND221 B26
GND222 B30
GND223 B5
GND224 B9
GND225 C12
GND226 C15
GND227 C18
GND228 C21
GND229 C24
GND114
E2 GND113
E26 GND112
E30 GND111
E33 GND110
E5 GND109
E9 GND108
F11 GND107
F14 GND106
F17 GND105
F20 GND104
F23 GND103
H27 GND102
H8 GND101
J2 GND100
J30 GND99
J33 GND98
J5 GND97
K17 GND96
K18 GND95
L11 GND94
L12 GND93
L14 GND92
L15 GND91
L20 GND90
L21 GND89
L23 GND88
L24 GND87
L29 GND86
L3 GND85
M11 GND84
M16 GND83
M19 GND82
M24 GND81
M32 GND80
M6 GND79
P11 GND78
P14 GND77
P15 GND76
P16 GND75
P17 GND74
P18 GND73
P19 GND72
P20 GND71
P21 GND70
P24 GND69
P29 GND68
P3 GND67
R11 GND66
R14 GND65
R15 GND64
R16 GND63
R17 GND62
R18 GND61
R19 GND60
R20 GND59
R21 GND58
R24 GND57
R32 GND56
R6 GND55
T12 GND54
T14 GND53
T15 GND52
T16 GND51
T17 GND50
T18 GND49
T19 GND48
T20 GND47
T21 GND46
T23 GND45
U10 GND44
U14 GND43
U15 GND42
U16 GND41
U17 GND40
U18 GND39
U19 GND38
U20 GND37
U21 GND36
U25 GND35
U29 GND34
U3 GND33
V10 GND32
V14 GND31
V15 GND30
V16 GND29
V17 GND28
V18 GND27
V19 GND26
V20 GND25
V21 GND24
V25 GND23
V32 GND22
V6 GND21
W12 GND20
W14 GND19
W15 GND18
W16 GND17
W17 GND16
W18 GND15
W19 GND14
W20 GND13
W21 GND12
Y11 GND11
Y14 GND10
Y15 GND9
Y16 GND8
Y17 GND7
Y18 GND6
Y19 GND5
Y20 GND4
Y21 GND3
Y24 GND2
Y29 GND1
Y3
GND401
M12
GND402
M23 GND403 AC12
GND404 AC23
C131
0.01uF
C131
0.01uF
12
C201
0.1uF
C201
0.1uF
12
C223
1000pF
C223
1000pF
12
+
C240
22uF, Tant
0805
+
C240
22uF, Tant
0805
C150
0.1uF
C150
0.1uF
12
C207
1000pF
C207
1000pF
12
C172
0.01uF
C172
0.01uF
12
C261
1uF, X5R, 6.3V
C261
1uF, X5R, 6.3V
C163
1000pF
C163
1000pF
12
C182
1000pF
C182
1000pF
12
C188
1000pF
C188
1000pF
12
+
C127
22uF, Tant
0805
+
C127
22uF, Tant
0805
C215
0.01uF
C215
0.01uF
12
C161
0.1uF
C161
0.1uF
12
C213
0.01uF
C213
0.01uF
12
C214
0.1uF
C214
0.1uF
12
C189
0.01uF
C189
0.01uF
12
C205
1000pF
C205
1000pF
12
C198
1000pF
C198
1000pF
12
C169
0.01uF
C169
0.01uF
12
C152
0.1uF
C152
0.1uF
12
C153
0.01uF
C153
0.01uF
12
C149
0.1uF
C149
0.1uF
12
C200
1000pF
C200
1000pF
12
C225
0.1uF
C225
0.1uF
12
C160
0.1uF
C160
0.1uF
12
C173
1000pF
C173
1000pF
12
C222
0.01uF
C222
0.01uF
12
C146
0.01uF
C146
0.01uF
12
C206
0.01uF
C206
0.01uF
12
C133
0.1uF
C133
0.1uF
12
C212
1000pF
C212
1000pF
12
C229
0.01uF
C229
0.01uF
12
C196
0.01uF
C196
0.01uF
12
C151
0.1uF
C151
0.1uF
12
C185
0.01uF
C185
0.01uF
12
C148
0.1uF
C148
0.1uF
12
C234
1000pF
C234
1000pF
12
C219
0.1uF
C219
0.1uF
12
C197
0.01uF
C197
0.01uF
12
C195
0.01uF
C195
0.01uF
12
+
C232
22uF, Tant
0805
+
C232
22uF, Tant
0805
C175
0.01uF
C175
0.01uF
12
C141
1uF, X5R, 6.3V
C141
1uF, X5R, 6.3V
C227
0.1uF
C227
0.1uF
12
C187
1000pF
C187
1000pF
12
C168
0.1uF
C168
0.1uF
12
C233
0.1uF
C233
0.1uF
12
C144
0.01uF
C144
0.01uF
12
C208
1000pF
C208
1000pF
12
C184
0.1uF
C184
0.1uF
12
C171
0.01uF
C171
0.01uF
12
C134
0.1uF
C134
0.1uF
12
C204
0.01uF
C204
0.01uF
12
C162
0.1uF
C162
0.1uF
12
C157
0.1uF
C157
0.1uF
12
C166
0.01uF
C166
0.01uF
12
C237
1uF, X5R, 6.3V
C237
1uF, X5R, 6.3V
FB40
BLM21AG601SN1D
FB40
BLM21AG601SN1D
C167
1000pF
C167
1000pF
12
C145
0.01uF
C145
0.01uF
12
C260
0.1uF
C260
0.1uF
C199
0.01uF
C199
0.01uF
12
C228
1uF, X5R, 6.3V
C228
1uF, X5R, 6.3V
C226
0.01uF
C226
0.01uF
12
C217
1000pF
C217
1000pF
12
NO CONNECT
ECP3-95
U30K
NO CONNECT
ECP3-95
U30K
NC7
AA9 NC8
AB10 NC9
AB25 NC10
AB26 NC11
AB27
NC13
AB3 NC14
AB31 NC15
AB32 NC16
AB4 NC17
AB6 NC18
AB7 NC19
AB8 NC20
AC1 NC21
AC10 NC22
AC2 NC23
AC25 NC24
AC26 NC25
AC27 NC26
AC28
NC30
AC4 NC31
AC5 NC32
AC8 NC33
AC9
NC35
AD25 NC36
AD26 NC37
AD27 NC38
AD28 NC39
AD29
NC41
AD30 NC42
AD31 NC43
AD33 NC44
AD34
NC46
AD5 NC47
AD7
NC51
AE14 NC52
AE15
NC62
AE33 NC63
AE34
NC65
AE5 NC66
AE6 NC67
AE7 NC68
AE8
NC70
AF1 NC71
AF11 NC72
AF12 NC73
AF13
NC75
AF27 NC76
AF28 NC77
AF29 NC78
AF3
NC81
AF34 NC82
AF4 NC83
AF6 NC84
AF7 NC85
AF8
NC87
AG1 NC88
AG11 NC89
AG12 NC90
AG13 NC91
AG2
NC93
AG28 NC94
AG29 NC95
AG3 NC96
AG30 NC97
AG31 NC98
AG32 NC99
AG33 NC100
AG34 NC101
AG4 NC102
AG5 NC103
AG6 NC104
AG7
NC106
AH1 NC107
AH12 NC108
AH13 NC109
AH2
NC113
AH29 NC114
AH3 NC115
AH30 NC116
AH31 NC117
AH32 NC118
AH34 NC119
AH4 NC120
AH5 NC121
AH6
NC123
AH8
NC127
AJ29 NC128
AJ30 NC129
AJ32
NC132
AK10 NC133
AK11 NC134
AK12 NC135
AK13
NC142
AL10 NC143
AL11 NC144
AL12 NC145
AL13
NC156
AN10 NC157
AN11 NC158
AN12
NC164 AP10
NC165 AP11
NC166 AP12
NC167 AP13
NC175 B27
NC176 B29
NC177 B8
NC181 C26
NC182 C27
NC183 C7
NC184 C8
NC185 C9
NC189 D26
NC190 D27
NC191 D7
NC192 D8
NC193 D9
NC195 E14
NC200 E25
NC201 E27
NC202 E28
NC203 E29
NC204 E6
NC205 E7
NC206 E8
NC210 F24
NC211 F25
NC212 F26
NC213 F27
NC214 F28
NC215 F29
NC216 F4
NC217 F5
NC218 F6
NC219 F7
NC220 F8
NC221 F9
NC222 G10
NC226 G24
NC227 G27
NC228 G28
NC229 G29
NC232 G6
NC233 G7
NC234 G8
NC235 G9
NC236 H10
NC237 H11
NC238 H12
NC239 H24
NC240 H28
NC241 H29
NC242 H30
NC243 H31
NC244 H32
NC247 H6
NC248 H7
NC249 H9
NC250 J10
NC251 J11
NC254 J24
NC255 J25
NC256 J26
NC257 J27
NC258 J28
NC259 J29
NC260 J31
NC261 J32
NC262 J4
NC263 J6
NC264 J7
NC265 J8
NC266 J9
NC267 K1
NC268 K11
NC271 K2
NC272 K25
NC273 K26
NC274 K27
NC275 K28
NC276 K29
NC277 K3
NC278 K30
NC279 K31
NC280 K32
NC281 K33
NC282 K34
NC283 K4
NC284 K5
NC285 K6
NC286 K7
NC289 L1
NC290 L10
NC291 L2
NC292 L25
NC293 L26
NC294 L27
NC295 L28
NC296 L30
NC297 L31
NC298 L32
NC299 L33
NC300 L34
NC301 L4
NC302 L5
NC303 L6
NC304 L7
NC305 L8
NC306 L9
NC307 M1
NC308 M2
NC309 M25
NC310 M26
NC311 M27
NC312 M28
NC313 M29
NC314 M3
NC315 M30
NC316 M31
NC317 M33
NC318 M34
NC319 M4
NC320 M7
NC321 M8
NC322 M9
NC323 N9
NC159
AN13
NC56
AE28
NC55
AE27
NC401
G14
NC402
G15
NC403
F15
NC404
E16
NC405
F16
NC406
H21
NC407
G22
NC408
AJ1
NC409
AK1
C218
1000pF
C218
1000pF
12
C159
0.1uF
C159
0.1uF
12
C224
0.1uF
C224
0.1uF
12
+
C262
22uF, Tant
0805
+
C262
22uF, Tant
0805
C210
1000pF
C210
1000pF
12
C230
0.1uF
C230
0.1uF
12
31
LatticeECP3 Video Protocol Board – Revision C
User’s Guide
Figure 15. FPGA Configuration
5
5
4
4
3
3
2
2
1
1
DD
C C
B B
A A
FPGA_CS1N
FPGA_CSSPI1N_DOUT
PROGRAMN_ECP3
TCK_ECP3
FPGA_CSN
CFG2
CFG1
CFG0
TI_ADC4
FPGA_D1
FPGA_D0
FPGA_D3
FPGA_D4
FPGA_D5
FPGA_D6
FPGA_D2
TDI
TCK
TMS
INITN
TI_ADC3
TDO
TI_ADC2
PROGRAMN
FLASH_DIS
TI_ADC1
PROGRAMN_ECP3
TI_ADC0
FPGA_XRES
FPGA_CSSPI0N_DI
SPI0_QFPGA_D7
DONE_ECP3
TMS_ECP3
PROGRAMN_ECP3
FPGA_CSSPI1N_DOUT
GSRN
TCK_ECP3
CFG2
CFG1
CFG0
INITN_ECP3
PROGRAMN_ECP3
FPGA_SISPI
TDI_ ECP3
FPGA_CSSPI0N_DI
INITN_ECP3
DONE_ECP3
FPGA_CCLK
FPGA_CSN
SPI_CLK
FPGA_CSN
Q_0IPS7D_AGPF
FPGA_SISPI
FPGA_W RITEN
3_3V
FPGA_W RITEN
DONE_ECP3
PROGRAMN_ECP3
3_3V
FPGA_D2
FPGA_D0SPIFASTN
FPGA_D3
FPGA_D4
FPGA_D6
FPGA_D5
FPGA_D6
FPGA_D7
FPGA_CCLK
TDO_ECP3
FPGA_D0
INITN_ECP3
DONE_ECP3
INITN_ECP3
FPGA_SISPI
FPGA_D1
CFG2
CFG1
PROGRAMN_ECP3
CFG0
FPGA_CS1N
FPGA_CSSPI0N_DI
FPGA_CS1N
TCK_ECP3
TMS_ECP3
TDI_ECP3
TDO_ECP3
DONE
LA1
TDO_ECP3
TMS_ECP3
TDI_ ECP3
SPI_CLK
LA2
3_3V
3_3V
3_3V
3_3V
3_3V
3_3V
3_3V
3_3V
3_3V
3_3V
3_3V
3_3V
3_3V
3_3VIN
TDI_XO [14]
TDO_PAC [4]
TMS_ XO[14]
TMS_PAC[4]
TCK_ XO[14]
TCK_PAC[4]
TDI_ PA C [4 ]
TDO_XO [14]
GSRN [4,11]
TI_ADC[0..4] [11]
TEMP [ 4]
TEMP _GND [ 4]
INITN_ECP3[4]
DONE_ECP3[4]
DP_RX_HPD_OUT [7]
LA[1..33] [8,9,11,12]
DP_TX_HPD_OUT [7]
Title
Size Project Rev
Date: Sheet of
Lattice Semiconductor Corporation
5555 N.E. Moore Court
Hillsboro, Oregon. 97124
ECP3 Video Protocol Board Schematic
C
FPGA Configuration
C
616Wednesday, November 04, 2009
Title
Size Project Rev
Date: Sheet of
Lattice Semiconductor Corporation
5555 N.E. Moore Court
Hillsboro, Oregon. 97124
ECP3 Video Protocol Board Schematic
C
FPGA Configuration
C
616Wednesday, November 04, 2009
Title
Size Project Rev
Date: Sheet of
Lattice Semiconductor Corporation
5555 N.E. Moore Court
Hillsboro, Oregon. 97124
ECP3 Video Protocol Board Schematic
C
FPGA Configuration
C
616Wednesday, November 04, 2009
CONFIG
CFG Switches
TDI
TDO
SPI FLASH
ON
(From ispVM Download Cable)
ECP3
TDI
TDO
ECP3 PAC
XO
PAC
ECP3 PACXO
XO
J32 J33 J34
TDI
JTAG CONNECTOR
FPGA GSRN
PROGRAMN
TDO
ECP3 PACXO
TDI
TDO
DONE indicator will light when
configuration is successfully
completed
INITN indicator will light
if an error occurs during
configuration programming
edoM
n
oitaru
g
i
fnoC2GFC CFG1 CFG0
ispJTAG
Slave Serial
SPIm
SPI Flash
Slave Parallel
0(ON)
XX
1(OFF)1(OFF)1(OFF)
1(OFF) 1(OFF)
0(ON)0(ON) 1(OFF)
0(ON)
0(ON) 0(ON)
X
TMS
TCK
DONE
INITn
+3.3V
TDI
GND
TDO
PROGRAMn
J32 J33 J34
J32 J33 J34
J32 J33 J34
ECP3 Configuration I/Os
TDI
TDO
ECP3 PACXO
sysCONFIG
Connector
ECP3 PACXO
TDI
TDO
ECP3 PACXO
TDI
TDO
J32 J33 J34
J32 J33 J34
CONFIG
Status LEDs
J32 J33 J34
PROGRAMN
& GSRN
Pushbuttons
Top View
1(G) 2(S)
3(D)
SOT-23
(J20)
J31
HEADER 3x1
J31
HEADER 3x1
1
2
3
R242
150
R242
150
R214
10K
R214
10K
J27
HEADER 3x1
J27
HEADER 3x1
1
2
3
D20
LED-SMT1206_RED
D20
LED-SMT1206_RED
J33
HEADER 4x1
J33
HEADER 4x1
1
2
3
4
R112 OPEN
R112 OPEN
R59 10K, 1%R59 10K, 1%
R116
4.7K
R116
4.7K
R99
10K
R99
10K
Q22
MOSFET N GSD
BSS138LT1G
Q22
MOSFET N GSD
BSS138LT1G
1
32
RN12 1K EXB28V102JVRN12 1K EXB28V102JV
1
2
3
4
8
7
6
5
SW5
TL3301SPF160QG
Tactile Switch
SW5
TL3301SPF160QG
Tactile Switch
1 3
2 4
R107
100
R107
100
R101
10K
R101
10K
R111
100
R111
100
C265
0.1uF
C265
0.1uF
R108 0R
R108 0R
R100 10KR100 10K
C263
0.1uF
C263
0.1uF
R119OPEN R119OPEN
R106 0R
R106 0R
D21
LED-SMT1206_RED
D21
LED-SMT1206_RED
U32
Flash
STMicroelectronics
M25P64-VMF6TP
U32
Flash
STMicroelectronics
M25P64-VMF6TP
S#
7
Q
8
DU1
3
DU2
4
VCC
2HOLD#
1
DU4
6DU3
5
W# 9
VSS 10
DU5 11
DU6 12
DU7 13
DU8 14
D15
CK 16
J32
HEADER 4x1
J32
HEADER 4x1
1
2
3
4
R223
10K
R223
10K
R244
150
R244
150
R226
10K
R226
10K
SW2
SW DIP-3 CTS 194-3MST
SW2
SW DIP-3 CTS 194-3MST
1
2
3
6
5
4
SW6
TL3301SPF160QG
Tactile Switch
SW6
TL3301SPF160QG
Tactile Switch
13
2 4
U11B
74LVC125
U11B
74LVC125
3Y
83A 9
3OE_N 10
4Y
11 4A 12
4OE_N 13
VCC 14
R239 10KR239 10K
R104 0R
R104 0R
R241 150R241 150
R97 10KR97 10K
R98 10KR98 10K
R110
10K
R110
10K
J34
HEADER 4x1
J34
HEADER 4x1
1
2
3
4
R102 0R
R102 0R
R243 0R
R243 0R
BANK 8/CONFIG
ECP3-95
U30G
BANK 8/CONFIG
ECP3-95
U30G
PR16B/BUSY/SISPI/AVDN F33
PR14B/D6/SPID1 J34
PR16A/D7/SPID0 F32
PR14A/D5 H34
PR13B/D4/SO G32
PR11B/D2 H33
PR13A/D3/SI G33
PR11A/D1 G34
PR10B/D0/SPIFASTN E32
PR8B/MCLK F34
PR10A/WRITEN E31
PR8A/DOUT/CSON/CSSPI1N E34
PR7B/CSN/SN/CONT1N/OEN F31
PR5B/DI/CSSPI0N/CEN D34
PR7A/CS1N/HOLD/CONT2N/RDY G30
PR5A D33
DONE G31
CCLK C34
INITN C33
PROGRAMN B34
CFG0 B33
CFG1 F30
CFG2 D32
PT145B/XD15 C31
PT143B/XD13 C32
PT145A/XD14 D31
PT143A/XD12 B32
PT142B/XD11 D29
PT140B/XD9 A33
PT142A/XD10 D30
PT140A/XD8 A32
TMS D2
TDO C1
VCCJ K10
TCK D1
TDI E1
XRES W23
VCCIO8_1 P25
VCCIO8_2 N25
TEMPSENSE AN4
TEMPVSS AP4
U13
MAX6817
U13
MAX6817
IN1
1
GND
2
IN2
3
OUT2 4
VCC 5
OUT1 6
R240
150
R240
150
R96 10KR96 10K
VCC
GND
TDO
TDI
ispEN_N
NC
TMS
TCK
DONE
INITN
J28
HEADER 10x1
VCC
GND
TDO
TDI
ispEN_N
NC
TMS
TCK
DONE
INITN
J28
HEADER 10x1
12
3
4
5
6
7
8
9
10
R113
10K
R113
10K
R117OPEN R117OPEN
C389
0.01uF
C389
0.01uF
C390
0.1uF
C390
0.1uF
R103
10K
R103
10K
R225
10K
R225
10K
R118
4.7K
R118
4.7K
R109 OPEN
R109 OPEN
R245 0R
R245 0R
R105 0R
R105 0R
J30
HEADER 2x1
J30
HEADER 2x1
1
2
J37
HEADER 17x2
J37
HEADER 17x2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
D19
LED-SMT1206_RED
D19
LED-SMT1206_RED
D18
LED-SMT1206_GREEN
D18
LED-SMT1206_GREEN
U11A
74LVC125
U11A
74LVC125
1OE_N 1
1A 2
1Y
3
2OE_N 4
2A 5
2Y
6
GND
7
32
LatticeECP3 Video Protocol Board – Revision C
User’s Guide
Figure 16. SERDES
5
5
4
4
3
3
2
2
1
1
DD
C C
B B
A A
x4_PERp0
x4_PERn0
x4_PERp1
x4_PERn1
x4_PETp3
x4_PERp2
x4_PERn2
x4_PERp3
x4_PERn3
PCIE_3V3
x4_PETp0
x4_PETn0
x4_PETp1
x4_PETn1
x4_PETp2
x4_PETn2
x4_PETn3
PCIE_3V3
x4_PCIE_CLKN
x4_PCIE_CLKP
x4_PERp3
x4_PERn3
PCSB_HDOUTP3
PCSB_HDOUTN3
x4_PERp2
x4_PERn2
PCSB_HDOUTP2
PCSB_HDOUTN2
x4_PERp1
x4_PERn1
PCSB_HDOUTP1
PCSB_HDOUTN1
x4_PERp0
x4_PERn0
PCSB_HDOUTP0
PCSB_HDOUTN0
x4_PCIE_CLKP x4_PCIE_CLKN
PCSB_HDOUTP0
PCSB_HDOUTN0
PCSB_HDOUTP1
PCSB_HDOUTN1
PCSB_HDOUTP2
PCSB_HDOUTN2
PCSB_HDOUTP3
PCSB_HDOUTN3
x4_PCIE_CLKP
x4_PCIE_CLKN
x4_PETp0
x4_PETn0
x4_PETp1
x4_PETn1
x4_PETp2
x4_PETn2
x4_PETp3
x4_PETn3
PCSA_SMA_P
PCSA_SMA_N
SI570_CLK_P
SI570_CLK_N
MZ_HDOUTP3
MZ_HDOUTP0
MZ_HDOUTN0
MZ_HDOUTP2
MZ_HDOUTN3
MZ_HDOUTN2
MZ_HDOUTN1
MZ_HDOUTP1
MZ_HDINP0
MZ_HDINN0
MZ_HDINP1
MZ_HDINN1
MZ_HDINP2
MZ_HDINN2
MZ_HDINP3
MZ_HDINN3
MZ_REFCLKP
MZ_REFCLKN
PCSA_HDOUTN3
PCSA_HDOUTP3
PCSA_HDINP2
PCSA_HDINN2
PCSA_HDINP3
PCSA_HDINN3
PCSA_HDOUTP2
PCSA_HDOUTN2
PCSA_REFCLKP
PCSA_REFCLKN
MZ_HDINP0
MZ_HDINN0
PCSA_REFCLKP
PCSA_REFCLKN
PCSA_HDINN3
PCSA_HDINP3
PCSA_HDOUTP2
PCSA_HDOUTN2
PCSA_HDINP2
PCSA_HDINN2
PCSA_HDOUTN3
PCSA_HDOUTP3
MZ_HDINN3
MZ_HDINP3 MZ_HDOUTP3
MZ_HDOUTN3
MZ_HDINN2 MZ_HDOUTN2
MZ_HDINP2 MZ_HDOUTP2
MZ_HDINN1
MZ_HDINP1 MZ_HDOUTP1
MZ_HDOUTN1
MZ_REFCLKN
MZ_REFCLKP
MZ_HDOUTN0
MZ_HDOUTP0
MZ_CTRL1MZ_CTRL0
MZ_CTRL2
MZ_CTRL4
MZ_CTRL6
MZ_CTRL8
MZ_CTRL14
MZ_CTRL10
MZ_CTRL16
MZ_CTRL18
MZ_CTRL12
MZ_CTRL5
MZ_CTRL15
MZ_CTRL11
MZ_CTRL17
MZ_CTRL19
MZ_CTRL13
MZ_CTRL7
MZ_CTRL9
MZ_CTRL3
MZ_REFCLKP
MZ_REFCLKN
5_0V
5_0V
3_3V
3_3V_SDI_CLK
PCSA_VCCIB
1_5V_IO
1_2V_IO
1_5V_IO
1_2V_IO
PCSB_VCCIB
1_5V_IO
1_2V_IO
PCSA_VCCOB
1_5V_IO
1_2V_IO
PCSB_VCCOB
PCSA_VCCIB
PCSB_VCCIB
PCSC_VCCIB
PCSA_VCCOB
PCSB_VCCOB
PCSC_VCCOB
3_3V
5_0V
3_3V
3_3V
PCSA_VCCIB
PCSA_VCCOB
PCSB_VCCIB
PCSB_VCCOB
PCSC_VCCIB
PCSC_VCCOB
3_3V 1_8V
1_2V_IO
PCSC_VCCOB
1_5V_IO
PCSC_VCCIB
1_5V_IO
1_2V_IO
12_0VIN
PCIE_PERSTN[11]
SI570_SCL[11]
SI570_SDA[11]
SI570_EN[8,11]
PCSA_HDINN0 [13]
PCSA_HDINP0 [13]
PCSA_HDOUTN0 [13]
PCSA_HDOUTP0 [13]
PCSA_HDOUTP1 [13]
PCSA_HDOUTN1 [13]
PCSA_HDINP1 [13]
PCSA_HDINN1 [13]
DP_RX_PWR_OUT_EN [9]
DP_TX_PWR_OUT_EN [9]
MZ_SIG0_P [10]
MZ_SIG0_N [10]
MZ_SE_SIG0[10]
MZ_SE_SIG1[10]
TX_GC4915_CLKOUTP [16]
TX_GC4915_CLKOUTN [16]
MZ_SIG1_P[10]
MZ_SIG1_N[10]
DP_RX_HPD_OUT [6]
DP_RX_AUX_P[10]
DP_RX_AUX_N[10]
DP_TX_HPD_OUT [6]
DP_TX_AUX_P[10]
DP_TX_AUX_N[10]
MZ_CTRL[0..19] [8]
Title
Size Project Rev
Date: Sheet of
Lattice Semiconductor Corporation
5555 N.E. Moore Court
Hillsboro, Oregon. 97124
ECP3 Video Protocol Board Schematic
C
SERDES
C
716Tuesday, January 12, 2010
Title
Size Project Rev
Date: Sheet of
Lattice Semiconductor Corporation
5555 N.E. Moore Court
Hillsboro, Oregon. 97124
ECP3 Video Protocol Board Schematic
C
SERDES
C
716Tuesday, January 12, 2010
Title
Size Project Rev
Date: Sheet of
Lattice Semiconductor Corporation
5555 N.E. Moore Court
Hillsboro, Oregon. 97124
ECP3 Video Protocol Board Schematic
C
SERDES
C
716Tuesday, January 12, 2010
Place near ECP3
X4 PCIe Board Fingers
B side = PRIMARY Component Side(TOP)
A side = SECONDARY Component Side(BOTTOM)
All Nets are 100-ohm differential pairs.
The P and N traces shall be <20mil matched in length
Quad A Reference Clock Options:
(1) Gennum Clock Chips
(2) Silicon Labs Si570
(3) SMA Connectors
PCIe x4
(Quad B)
DisplayPort
(Quad A, Ch 2, Ch3)
Mezzanine Board Connection
(Quad C)
Quad A Reference Clock
fz = 1 / (2*3.1416*390*0.01uF) = 40KHz
fz is within the recommanded 20KHz to 100KHz range
Vout = 1 + (390/169) = 3.3078V
fz = 1 / (2*3.1416*390*0.01uF) = 40KHz
fz is within the recommanded 20KHz to 100KHz range
Vout = 1 + (390/169) = 3.3078V
Tx
Rx
Place under ECP3 device
R140 1MR140 1M
FB32
BLM21AG601SN1D
FB32
BLM21AG601SN1D
U9
Si570
Silicon Labs
570QAC000215DG
U9
Si570
Silicon Labs
570QAC000215DG
NC
1
OE
2
GND 3
CLK+ 4
CLK- 5
VDD
6
SDA
7
SCL
8
J21
HEADER 3x1
J21
HEADER 3x1
1
2
3
R162
169, 1%
R162
169, 1%
C138
0.01uF
C138
0.01uF
12
C110
1uF, X5R, 6.3V
C110
1uF, X5R, 6.3V
R154
169, 1%
R154
169, 1%
C117
0.1uF
C117
0.1uF
12
J20
HEADER 3x1
J20
HEADER 3x1
1
2
3
PCS/SERDES
ECP3-95
U30H
PCS/SERDES
ECP3-95
U30H
PCSA_HDINP0 AL21
PCSA_HDINN0 AK21
PCSA_HDINP1 AL20
PCSA_HDINN1 AK20
PCSA_HDINP2 AL19
PCSA_HDINN2 AK19
PCSA_HDINP3 AL18
PCSA_HDINN3 AK18
PCSA_HDOUTP0 AP21
PCSA_HDOUTN0 AN21
PCSA_HDOUTP1 AP20
PCSA_HDOUTN1 AN20
PCSA_HDOUTP2 AP19
PCSA_HDOUTN2 AN19
PCSA_HDOUTP3 AP18
PCSA_HDOUTN3 AN18
PCSA_REFCLKP AH19
PCSA_REFCLKN AH20
PCSA_VCCIB0 AF21
PCSA_VCCIB1 AF20
PCSA_VCCIB2 AF19
PCSA_VCCIB3 AF18
PCSA_VCCOB0 AG21
PCSA_VCCOB1 AG20
PCSA_VCCOB2 AG19
PCSA_VCCOB3 AG18
PCSB_HDINP0 AL17
PCSB_HDINN0 AK17
PCSB_HDINP1 AL16
PCSB_HDINN1 AK16
PCSB_HDINP2 AL15
PCSB_HDINN2 AK15
PCSB_HDINP3 AL14
PCSB_HDINN3 AK14
PCSB_HDOUTP0 AP17
PCSB_HDOUTN0 AN17
PCSB_HDOUTP1 AP16
PCSB_HDOUTN1 AN16
PCSB_HDOUTP2 AP15
PCSB_HDOUTN2 AN15
PCSB_HDOUTP3 AP14
PCSB_HDOUTN3 AN14
PCSB_REFCLKP AH15
PCSB_REFCLKN AH16
PCSB_VCCIB0 AF17
PCSB_VCCIB1 AF16
PCSB_VCCIB2 AF15
PCSB_VCCIB3 AF14
PCSB_VCCOB0 AG17
PCSB_VCCOB1 AG16
PCSB_VCCOB2 AG15
PCSB_VCCOB3 AG14
PCSC_HDINP0 AL25
PCSC_HDINN0 AK25
PCSC_HDINP1 AL24
PCSC_HDINN1 AK24
PCSC_HDINP2 AL23
PCSC_HDINN2 AK23
PCSC_HDINP3 AL22
PCSC_HDINN3 AK22
PCSC_HDOUTP0 AP25
PCSC_HDOUTN0 AN25
PCSC_HDOUTP1 AP24
PCSC_HDOUTN1 AN24
PCSC_HDOUTP2 AP23
PCSC_HDOUTN2 AN23
PCSC_HDOUTP3 AP22
PCSC_HDOUTN3 AN22
PCSC_REFCLKP AH22
PCSC_REFCLKN AH23
PCSC_VCCIB0 AF24
PCSC_VCCIB1 AF23
PCSC_VCCIB2 AF22
PCSC_VCCIB3 AE20
PCSC_VCCOB0 AG24
PCSC_VCCOB1 AG23
PCSC_VCCOB2 AG22
PCSC_VCCOB3 AE21
R50
OPEN
R50
OPEN
R47 0RR47 0R
C118
0.01uF
C118
0.01uF
12
C328
0.01uF, NPO
1206
C328
0.01uF, NPO
1206
1 2
C120
1uF, X5R, 6.3V
C120
1uF, X5R, 6.3V
C107
1uF, X5R, 6.3V
C107
1uF, X5R, 6.3V
C6 0.1uF, X5R, 10V
C6 0.1uF, X5R, 10V
R49 OPENR49 OPEN
C101
1uF, X5R, 6.3V
C101
1uF, X5R, 6.3V
C111
0.1uF
C111
0.1uF
12
C119
1uF, X5R, 6.3V
C119
1uF, X5R, 6.3V
R139 1MR139 1M
R145 1KR145 1K
CN1 PCIe x4 FingerCN1 PCIe x4 Finger
PRSNT1#
A1
+12V_A2
A2
+12V_A3
A3
GND_A4
A4
JTAG2
A5
JTAG3
A6
JTAG4
A7
JTAG5
A8
+3.3V_A9
A9
+3.3V_A10
A10
PERST#
A11
GND_A12
A12
REFCLK+
A13
REFCLK-
A14
GND_A15
A15
PERp0
A16
PERn0
A17
GND_A18
A18
RSVD_A19
A19
GND_A20
A20
PERp1
A21
PERn1
A22
GND_A23
A23
GND_A24
A24
PERp2
A25
PERn2
A26
GND_A27
A27
GND_A28
A28
PERp3
A29
PERn3
A30
GND_A31
A31
+12V_B1 B1
+12V_B2 B2
RSVD_B3 B3
GND_B4 B4
SMCLK B5
SMDAT B6
GND_B7 B7
+3.3V_B8 B8
JTAG1 B9
3.3Vaux B10
WAKE# B11
RSVD_B12 B12
GND_B13 B13
PETp0 B14
PETn0 B15
GND_B16 B16
PRSNT3# B17
GND_B18 B18
PETp1 B19
PETn1 B20
GND_B21 B21
GND_B22 B22
PETp2 B23
PETn2 B24
GND_B25 B25
GND_B26 B26
PETp3 B27
PETn3 B28
GND_B29 B29
RSVD_B30 B30
PRSNT4# B31
GND_B32 B32
RSVD_A32
A32
C124
1uF, X5R, 6.3V
C124
1uF, X5R, 6.3V
C114
0.1uF
C114
0.1uF
12
C309
22uF, X5R, 6.3V
0805
C309
22uF, X5R, 6.3V
0805
12
R358 1KR358 1K
R143 100KR143 100K
+
C98
22uF, Tant
0805
+
C98
22uF, Tant
0805
C4 0.1uF, X5R, 10V
C4 0.1uF, X5R, 10V
+
C104
22uF, Tant
0805
+
C104
22uF, Tant
0805
J22
HEADER 3x1
J22
HEADER 3x1
1
2
3
C372 0.1uF, X5R, 10VC372 0.1uF, X5R, 10V
C363
0.01uF
C363
0.01uF
12
C125
0.1uF
C125
0.1uF
12
U23
NS
LP3878MR-ADJ/NOPB
U23
NS
LP3878MR-ADJ/NOPB
BYPASS
1
NC1
2
GND3
3
IN
4OUT 5
ADJ 6
NC2 7
SHDN 8
GND9
9
C11 0.1uF, X5R, 10V
C11 0.1uF, X5R, 10V
J8
SMA
73391-0060
J8
SMA
73391-0060
1
FB34
BLM21AG601SN1D
FB34
BLM21AG601SN1D
C128
0.1uF
C128
0.1uF
12
C292
22uF, X5R, 6.3V
0805
C292
22uF, X5R, 6.3V
0805
12
C102
1uF, X5R, 6.3V
C102
1uF, X5R, 6.3V
R75
OPEN
R75
OPEN
FB37
BLM21AG601SN1D
FB37
BLM21AG601SN1D
R149
390, 1%
R149
390, 1%
J3
DP-CON
47272-0001Molex
J3
DP-CON
47272-0001Molex
ML3_N_IN
1
GND2 2
ML3_P_IN
3
ML2_N_IN 4
GND5
5
ML2_P_IN 6
ML1_N_IN
7
GND8 8
ML1_P_IN
9
ML0_N_IN 10
GND11
11
ML0_P_IN 12
CONFIG1
13
CONFIG2 14
AUX_P
15
GND16 16
AUX_N
17
HPD_OUT 18
RTN
19
PWR_OUT 20
C9 0.1uF, X5R, 10V
C9 0.1uF, X5R, 10V
FB35
BLM21AG601SN1D
FB35
BLM21AG601SN1D
C132
0.1uF
C132
0.1uF
12
J24
HEADER 3x1
J24
HEADER 3x1
1
2
3
C130
0.1uF
C130
0.1uF
12
J19 Mez Molex 75005-0006J19 Mez Molex 75005-0006
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
S1
S2
S3
C365 0.1uF, X5R, 10VC365 0.1uF, X5R, 10V
FB33
BLM21AG601SN1D
FB33
BLM21AG601SN1D
R171 10KR171 10K
J17 HEADER_5X2
Samtec DW-05-08-F-D-275
J17 HEADER_5X2
Samtec DW-05-08-F-D-275
2
4
6
8
10
1
3
5
7
9
C293
22uF, X5R, 6.3V
0805
C293
22uF, X5R, 6.3V
0805
12
C135
1uF, X5R, 6.3V
C135
1uF, X5R, 6.3V
C375 0.1uF, X5R, 10VC375 0.1uF, X5R, 10V
R137 100KR137 100K
C379 0.1uF, X5R, 10VC379 0.1uF, X5R, 10V
C112
0.01uF
C112
0.01uF
12
J7
SMA
73391-0060
J7
SMA
73391-0060
1
R160
390, 1%
R160
390, 1%
C136
0.1uF
C136
0.1uF
12
C123
0.1uF
C123
0.1uF
12
C366 0.1uF, X5R, 10VC366 0.1uF, X5R, 10V
R359 1KR359 1K
TP13TP1 3
+
C105
22uF, Tant
0805
+
C105
22uF, Tant
0805
C5 0.1uF, X5R, 10V
C5 0.1uF, X5R, 10V
+
C99
22uF, Tant
0805
+
C99
22uF, Tant
0805
C115
0.01uF
C115
0.01uF
12
C299
0.01uF
C299
0.01uF
1 2
R349 470R349 470
C121
0.1uF
C121
0.1uF
12
TP12TP1 2
C122
1uF, X5R, 6.3V
C122
1uF, X5R, 6.3V
C116
0.1uF
C116
0.1uF
12
C7 0.1uF, X5R, 10V
C7 0.1uF, X5R, 10V
R142 100KR142 100K
C100
1uF, X5R, 6.3V
C100
1uF, X5R, 6.3V
C364
0.01uF
C364
0.01uF
12
R144 100KR144 100K
TP11TP1 1
R350 470R350 470
R146 1KR146 1K
R354 1KR354 1K
C382 0.1uF, X5R, 10VC382 0.1uF, X5R, 10V
C362
0.1uF
C362
0.1uF
12
+
C103
22uF, Tant
0805
+
C103
22uF, Tant
0805
C140
0.01uF
C140
0.01uF
12
C383 0.1uF, X5R, 10VC383 0.1uF, X5R, 10V
TP14TP1 4
C108
1uF, X5R, 6.3V
C108
1uF, X5R, 6.3V
R138 1KR138 1K
C10 0.1uF, X5R, 10V
C10 0.1uF, X5R, 10V
J47 HEADER 10X2
Samtec DW-10-08-F-D-275
J47 HEADER 10X2
Samtec DW-10-08-F-D-275
1
3
5
7
9
11
13
15
17
19
2
4
6
8
10
12
14
16
18
20
J4
DP-CON
47272-0001Molex
J4
DP-CON
47272-0001Molex
ML0_P_out
1
GND2 2
ML0_N_out
3
ML1_P_out 4
GND5
5
ML1_N_out 6
ML2_P_out
7
GND8 8
ML2_N_out
9
ML3_P_out 10
GND11
11
ML3_N_out 12
CONFIG1
13
CONFIG2 14
AUX_P
15
GND16 16
AUX_N
17
HPD_IN 18
RTN
19
PWR_OUT 20
C106
1uF, X5R, 6.3V
C106
1uF, X5R, 6.3V
+
C97
22uF, Tant
0805
+
C97
22uF, Tant
0805
C296
0.01uF
C296
0.01uF
1 2
R353 1KR353 1K
R54 0RR54 0R
R141 1KR141 1K
R352 1KR352 1K
FB36
BLM21AG601SN1D
FB36
BLM21AG601SN1D
C8 0.1uF, X5R, 10V
C8 0.1uF, X5R, 10V
J18
HEADER 3x1
J18
HEADER 3x1
1
2
3
C142
0.01uF
C142
0.01uF
12
U19
NS
LP3878MR-ADJ/NOPB
U19
NS
LP3878MR-ADJ/NOPB
BYPASS
1
NC1
2
GND3
3
IN
4OUT 5
ADJ 6
NC2 7
SHDN 8
GND9
9
C137
0.1uF
C137
0.1uF
12
C308
0.01uF, NPO
1206
C308
0.01uF, NPO
1206
1 2
R51 OPENR51 OPEN
J23
HEADER 3x1
J23
HEADER 3x1
1
2
3
C321
22uF, X5R, 6.3V
0805
C321
22uF, X5R, 6.3V
0805
12
C376 0.1uF, X5R, 10VC376 0.1uF, X5R, 10V
R48 0RR48 0R
R351 1KR351 1K
TP10TP10
R155 10KR155 10K
33
LatticeECP3 Video Protocol Board – Revision C
User’s Guide
Figure 17. DDR2 Memory
5
5
4
4
3
3
2
2
1
1
DD
C C
B B
A A
2_DDR2_K
2_DDR2_K#
2_DDR2_DQS0#
2_DDR2_DM0
PB1
PB2
PB3
PB4
DDR2_VREF
DDR2_DQS1#
DDR2_DQS0#
DDR2_DQS0
DDR2_DQ0
DDR2_DQ1
DDR2_DQ4
DDR2_DQ6
DDR2_DQ2
DDR2_DQ5
DDR2_DQ7
DDR2_DQ3
DDR2_DQ8
DDR2_DQ9
DDR2_DQ14
DDR2_DQ13
DDR2_DQ11
DDR2_DQ10
DDR2_DQ15
DDR2_DQ12
DDR2_DQS1
DDR2_A5
DDR2_A3
DDR2_A0
DDR2_A8
DDR2_A4
DDR2_A1
DDR2_A7
DDR2_A6
DDR2_A2
DDR2_A9
DDR2_A10
DDR2_A12
DDR2_A11
DDR2_DM0
DDR2_DM1
DDR2_ODT0
DDR2_RAS#
DDR2_WE#
DDR2_CS0#
DDR2_CKE
DDR2_BA0
DDR2_BA1
DDR2_K#
DDR2_K
DDR2_CAS#
DDR2_A14
DDR2_A13
DDR2_BA2
VDDL
DDR2_VREF DDR2_VREF
2_VDDL
2_DDR2_DQS1#
2_DDR2_DQS0#
2_DDR2_DQS0
2_DDR2_DQ0
2_DDR2_DQ1
2_DDR2_DQ4
2_DDR2_DQ6
2_DDR2_DQ2
2_DDR2_DQ5
2_DDR2_DQ7
2_DDR2_DQ3
2_DDR2_DQ8
2_DDR2_DQ9
2_DDR2_DQ14
2_DDR2_DQ13
2_DDR2_DQ11
2_DDR2_DQ10
2_DDR2_DQ15
2_DDR2_DQ12
2_DDR2_DQS1
2_DDR2_A5
2_DDR2_A3
2_DDR2_A0
2_DDR2_A8
2_DDR2_A4
2_DDR2_A1
2_DDR2_A7
2_DDR2_A6
2_DDR2_A2
2_DDR2_A9
2_DDR2_A10
2_DDR2_A12
2_DDR2_A11
2_DDR2_DM0
2_DDR2_DM1
2_DDR2_ODT0
2_DDR2_RAS#
2_DDR2_WE#
2_DDR2_CS0#
2_DDR2_CKE
2_DDR2_BA0
2_DDR2_BA1
2_DDR2_K#
2_DDR2_K
2_DDR2_CAS#
2_DDR2_A14
2_DDR2_A13
2_DDR2_BA2
DDR2_VREF
2_DDR2_DM1
2_DDR2_DQ11
2_DDR2_DQ15
2_DDR2_DQ8
2_DDR2_DQ10
2_DDR2_DQ13
2_DDR2_DQ7
2_DDR2_DQ0
2_DDR2_DQ2
2_DDR2_DQ5
2_DDR2_DQ6
2_DDR2_DQ1
2_DDR2_DQ3
2_DDR2_DQ4
2_DDR2_DQ12
2_DDR2_DQ14
2_DDR2_DQ9
2_DDR2_A8
2_DDR2_BA1
2_DDR2_A7
2_DDR2_A13
2_DDR2_BA0
2_DDR2_A14
2_DDR2_A1
2_DDR2_A4
2_DDR2_CKE
2_DDR2_A11
2_DDR2_A3
2_DDR2_A9
2_DDR2_A12
2_DDR2_BA2
SWITCH12
SWITCH11
DDR2_DQ14
DDR2_DQ9
DDR2_DQ12
DDR2_DQ11
DDR2_DQ13
DDR2_DM1
DDR2_DQ10
DDR2_DQ8
DDR2_VREF
DDR2_DQ15
DDR2_DQ6
DDR2_DM0
DDR2_DQ0
DDR2_DQ4
DDR2_DQ3
DDR2_DQS0#
DDR2_DQ1
2_DDR2_CS0#
SWITCH1
SWITCH2
SWITCH3
SWITCH4
DDR2_DQ7
DDR2_DQ2
DDR2_DQ5
SWITCH8
SWITCH9
SWITCH10
DDR2_K#
SWITCH7
DDR2_K
SWITCH5
SWITCH6
DDR2_A4
DDR2_A0
DDR2_A8
DDR2_A13
DDR2_ODT0
DDR2_CAS#
DDR2_CS0#
DDR2_A7
DDR2_A9
DDR2_A12
DDR2_A11
DDR2_A14
DDR2_WE#
DDR2_CKE
DDR2_BA2
DDR2_RAS#
LA25
LA21
LA22
LA23
LA26
LA27
LA19
LA18
DDR2_BA0
DDR2_A10
DDR2_A6
DDR2_A2
DDR2_A3
DDR2_A5
ACLK1
ACLK2
2_DDR2_ODT0
2_DDR2_CAS#
2_DDR2_A2
2_DDR2_A6
2_DDR2_WE#
2_DDR2_A0
2_DDR2_RAS#
2_DDR2_A10
2_DDR2_A5
SI570_2_CLK_N
SI570_2_CLK_P
SI570_2_CLK_N
SI570_2_CLK_P
SI570_2_SCL
SI570_2_SDA
SI570_2_SDA
SI570_2_SCL
MZ_CTRL0
MZ_CTRL2
MZ_CTRL3
MZ_CTRL4
MZ_CTRL1
MZ_CTRL5
MZ_CTRL6
MZ_CTRL7
MZ_CTRL8
MZ_CTRL9
DDR2_A1
DDR2_BA1
LA20
LA24
MZ_CTRL10
MZ_CTRL11
MZ_CTRL12
MZ_CTRL13
MZ_CTRL14
MZ_CTRL15
MZ_CTRL16
MZ_CTRL17
MZ_CTRL18
MZ_CTRL19
MZ_CTRL[0..19]
DDR2_DQS0
DDR2_DQS1#
DDR2_DQS1
2_DDR2_DQS1#
2_DDR2_DQS1
2_DDR2_DQS0
FPGA_VTT
1_8V
1_8V
FPGA_VTT
2_5V
1_8V
1_8V
1_8V 1_8V
1_8V
FPGA_VTT
1_8V
1_8V
3_3V_SDI_CLK
FPGA_VTT FPGA_VTT
SMA_CLK_P [11]
SMA_CLK_N [11]
PB[1..4] [12]SWITCH[1..12] [12]
LA[1..34][6,9,11,12]
ACLK[1..3] [10,15]
SI570_EN[7,11]
MZ_CTRL[0..19] [7]
Title
Size Project Rev
Date: Sheet of
Lattice Semiconductor Corporation
5555 N.E. Moore Court
Hillsboro, Oregon. 97124
ECP3 Video Protocol Board Schematic
C
DDR2 Memory
C
816Wednesday, November 04, 2009
Title
Size Project Rev
Date: Sheet of
Lattice Semiconductor Corporation
5555 N.E. Moore Court
Hillsboro, Oregon. 97124
ECP3 Video Protocol Board Schematic
C
DDR2 Memory
C
816Wednesday, November 04, 2009
Title
Size Project Rev
Date: Sheet of
Lattice Semiconductor Corporation
5555 N.E. Moore Court
Hillsboro, Oregon. 97124
ECP3 Video Protocol Board Schematic
C
DDR2 Memory
C
816Wednesday, November 04, 2009
ALL Memory controller
buses, clocks, and control
traces must be no more than
1.5 inches long using 50 Ohm
Transmission lines
ALL Memory controller
buses, clocks, and control
traces must be no more than
1.5 inches long using 50 Ohm
Transmission lines
Controller
Instance #2
Controller
Instance #1
Voltage adjustment range : 0.82V to 0.98V
Turn clockwise to increase the voltage
Place under ECP3
Place under ECP3
Place resistors close to ECP3Place resistors close to ECP3
C183
0.01uF
C183
0.01uF
12
U10
LP2997
LP2997MR
National Semiconductor
U10
LP2997
LP2997MR
National Semiconductor
GND
1
SD
2
VSENSE 3
VREF
4
VDDQ
5
AVIN 6
PVIN 7
VTT 8
BGND
9
VR1
100
ST32ETB101Copal
VR1
100
ST32ETB101Copal
1 3
2
C244
1uF, X5R, 6.3V
C244
1uF, X5R, 6.3V
C176
0.01uF
C176
0.01uF
12
C259
0.01uF
C259
0.01uF
R57
100
R57
100
R370
49.9, 1%
R370
49.9, 1%
C193
1uF, X5R, 6.3V
C193
1uF, X5R, 6.3V
+
C247
22uF, Tant
0805
+
C247
22uF, Tant
0805
C190
0.1uF
C190
0.1uF
12
+
C202
22uF, Tant
0805
+
C202
22uF, Tant
0805
C238
0.01uF
C238
0.01uF
C251
0.1uF
C251
0.1uF
12
R374
49.9, 1%
R374
49.9, 1%
R2244.7K R2244.7K
C254
0.01uF
C254
0.01uF
12
C174
0.01uF
C174
0.01uF
12
C236
0.1uF
C236
0.1uF
R93
OPEN
R93
OPEN
+
C191
22uF, Tant
0805
+
C191
22uF, Tant
0805
C253
0.01uF
C253
0.01uF
12
C252
0.1uF
C252
0.1uF
12
C186
0.1uF
C186
0.1uF
12
R375
49.9, 1%
R375
49.9, 1%
C139
0.1uF
C139
0.1uF
+
C246
22uF, Tant
0805
+
C246
22uF, Tant
0805
R94
510, 1%
R94
510, 1%
U31A
DDR2
MT47H128M16HG-3 IT
Micron
U31A
DDR2
MT47H128M16HG-3 IT
Micron
NC_A2
A2
DQ14
B1 DQ15
B9
DQ9
C2
DQ8
C8
DQ12
D1
DQ11
D3
DQ10
D7
DQ13
D9
DQ6
F1 DQ7
F9
DQ1
G2
DQ0
G8
DQ4
H1
DQ3
H3
DQ2
H7
DQ5
H9
NC_E2
E2
LDQS#/NU
E8
LDM
F3
LDQS
F7
CK
J8
CK#
K8
CKE
K2
WE#
K3
RAS#
K7
ODT
K9
BA0
L2
BA1
L3
CAS#
L7
CS#
L8
RFU_L1
L1
A0
M8
A1
M3
A2
M7
A3
N2
A4
N8
A5
N3
A6
N7
A7
P2
A8
P8
A9
P3
A10
M2
A11
P7
A12
R2
RFU_R3
R3
RFU_R7
R7
NC_R8
R8
UDM
B3
UDQS
B7
UDQS#/NU
A8
FB39
BLM21AG601SN1D
FB39
BLM21AG601SN1D
C155
0.01uF
C155
0.01uF
FB38
BLM21AG601SN1D
FB38
BLM21AG601SN1D
C258
22uF, X5R, 6.3V
0805
C258
22uF, X5R, 6.3V
0805
C256
0.01uF
C256
0.01uF
12
C245
1uF, X5R, 6.3V
C245
1uF, X5R, 6.3V
R360 1KR360 1K
C235
1uF, X5R, 6.3V
C235
1uF, X5R, 6.3V
R79
100
R79
100
C147
0.1uF
C147
0.1uF
U29A
DDR2
MT47H128M16HG-3 IT
Micron
U29A
DDR2
MT47H128M16HG-3 IT
Micron
NC_A2
A2
DQ14
B1 DQ15
B9
DQ9
C2
DQ8
C8
DQ12
D1
DQ11
D3
DQ10
D7
DQ13
D9
DQ6
F1 DQ7
F9
DQ1
G2
DQ0
G8
DQ4
H1
DQ3
H3
DQ2
H7
DQ5
H9
NC_E2
E2
LDQS#/NU
E8
LDM
F3
LDQS
F7
CK
J8
CK#
K8
CKE
K2
WE#
K3
RAS#
K7
ODT
K9
BA0
L2
BA1
L3
CAS#
L7
CS#
L8
RFU_L1
L1
A0
M8
A1
M3
A2
M7
A3
N2
A4
N8
A5
N3
A6
N7
A7
P2
A8
P8
A9
P3
A10
M2
A11
P7
A12
R2
RFU_R3
R3
RFU_R7
R7
NC_R8
R8
UDM
B3
UDQS
B7
UDQS#/NU
A8
R372
49.9, 1%
R372
49.9, 1%
R95
510, 1%
R95
510, 1%
C126
1uF, X5R, 6.3V
C126
1uF, X5R, 6.3V
R361 1KR361 1K
U15
Si570
Silicon Labs
570QAC000215DG
U15
Si570
Silicon Labs
570QAC000215DG
NC
1
OE
2
GND 3
CLK+ 4
CLK- 5
VDD
6
SDA
7
SCL
8
U31B
DDR2
MT47H128M16HG-3 IT
Micron
U31B
DDR2
MT47H128M16HG-3 IT
Micron
VDD_A1
A1
VDD_E1
E1
VDD_J9
J9
VDD_M9
M9
VDD_R1
R1
VSS_A3
A3
VSS_E3
E3
VSS_J3
J3
VSS_N1
N1
VSS_P9
P9
VDDQ_A9
A9
VDDQ_C1
C1
VDDQ_C3
C3
VDDQ_C7
C7
VDDQ_C9
C9
VDDQ_E9
E9
VDDQ_G1
G1
VDDQ_G3
G3
VDDQ_G7
G7
VDDQ_G9
G9
VSSQ_A7
A7
VSSQ_B2
B2
VSSQ_B8
B8
VSSQ_D2
D2
VSSQ_D8
D8
VSSQ_E7
E7
VSSQ_F2
F2
VSSQ_F8
F8
VSSQ_H2
H2
VSSQ_H8
H8
VDDL_J1
J1 VREF_J2
J2
VSSDL_J7
J7
C243
0.01uF
C243
0.01uF
BANK 7
LDQS22 LDQS31 LDQS40
LDQS13
ECP3-95
U30F
BANK 7
LDQS22 LDQS31 LDQS40
LDQS13
ECP3-95
U30F
PL10A* F3
PL10B* E3
PL11A G2
PL11B G1
PL13A/LDQS13 G3
PL13B H3
PL14A H1
PL14B J1
PL16A* J3
PL16B* H2
PL17A N4
PL17B N3
PL19A* M5
PL19B* N5
PL20A N2
PL20B N1
PL22A/LDQS22 M10
PL22B N10
PL23A P5
PL23B P4
PL25A* N8
PL25B* P8
PL25E_A/LUM2_GPLLT_FB_A P2
PL25E_B/LUM2_GPLLT_FB_B P1
PL25E_C/LUM2_GPLLT_IN_A N7
PL25E_D/LUM2_GPLLT_IN_B N6
PL26A R7
PL26B R5
PL28A* P9
PL28B* P10
PL29A R2
PL29B R1
PL31A/LDQS31 P7
PL31B P6
PL32A R4
PL32B R3
PL34A*/VREF1_7 R9
PL34B*/VREF2_7 R10
PL35A T6
PL35B T5
PL37A*/LUM0_GDLLT_IN_A R8
PL37B*/LUM0_GDLLT_IN_B T7
PL38A/LUM0_GDLLT_FB_A T4
PL38B/LUM0_GDLLT_FB_B T3
PL40A/LDQS40 T9
PL40B T8
PL41A T2
PL41B T1
PL43A*/PCLKT7_0 U9
PL43B*/PCLKC7_0 U8
PL43E_A/LUM0_GPLLT_FB_A U5
PL43E_B/LUM0_GPLLT_FB_B U4
PL43E_C/LUM0_GPLLT_IN_A U6
PL43E_D/LUM0_GPLLT_IN_B U7
PL8A F2
PL8B F1
VCCIO7_1 U12
VCCIO7_2 U11
VCCIO7_3 N12
VCCIO7_4 N11
VTT7_1 T11
VTT7_2 T10
PL2A
G4
PL2B
G5
PL4A
K9
PL4B
K8
PL5A
H5
PL5B
H4
+
C221
22uF, Tant
0805
+
C221
22uF, Tant
0805
C257
0.1uF
C257
0.1uF
12
C249
0.01uF
C249
0.01uF
12
+
C113
22uF, Tant
0805
+
C113
22uF, Tant
0805
C194
0.1uF
C194
0.1uF
12
C239
0.1uF
C239
0.1uF
R373
49.9, 1%
R373
49.9, 1%
C179
0.1uF
C179
0.1uF
12
+
C388
120uF, SP-Cap
EIA7343
Panasonic
EEF-SL0E121R
+
C388
120uF, SP-Cap
EIA7343
Panasonic
EEF-SL0E121R
U29B
DDR2
MT47H128M16HG-3 IT
Micron
U29B
DDR2
MT47H128M16HG-3 IT
Micron
VDD_A1
A1
VDD_E1
E1
VDD_J9
J9
VDD_M9
M9
VDD_R1
R1
VSS_A3
A3
VSS_E3
E3
VSS_J3
J3
VSS_N1
N1
VSS_P9
P9
VDDQ_A9
A9
VDDQ_C1
C1
VDDQ_C3
C3
VDDQ_C7
C7
VDDQ_C9
C9
VDDQ_E9
E9
VDDQ_G1
G1
VDDQ_G3
G3
VDDQ_G7
G7
VDDQ_G9
G9
VSSQ_A7
A7
VSSQ_B2
B2
VSSQ_B8
B8
VSSQ_D2
D2
VSSQ_D8
D8
VSSQ_E7
E7
VSSQ_F2
F2
VSSQ_F8
F8
VSSQ_H2
H2
VSSQ_H8
H8
VDDL_J1
J1 VREF_J2
J2
VSSDL_J7
J7
R92 0RR92 0R
C203
0.01uF
C203
0.01uF
12
C248
0.1uF
C248
0.1uF
12
C424
0.01uF
C424
0.01uF
12
C178
1uF, X5R, 6.3V
C178
1uF, X5R, 6.3V
C242
0.1uF
C242
0.1uF
R371
49.9, 1%
R371
49.9, 1% R376
49.9, 1%
R376
49.9, 1%
C109
0.01uF
C109
0.01uF
12
C216
0.01uF
C216
0.01uF
12
+
C192
22uF, Tant
0805
+
C192
22uF, Tant
0805
C143
0.1uF
C143
0.1uF
R69
0R
R69
0R
C255
0.1uF
C255
0.1uF
12
C425
0.01uF
C425
0.01uF
12
BANK 6
LDQS49 LDQS58 LDQS67 LDQS85 LDQS94
ECP3-95
U30E
BANK 6
LDQS49 LDQS58 LDQS67 LDQS85 LDQS94
ECP3-95
U30E
PL44A U2
PL44B U1
PL46A*/PCLKT6_0 V9
PL46B*/PCLKC6_0 V8
PL47A V2
PL47B V1
PL49A/LDQS49 V5
PL49B W5
PL50A V4
PL50B V3
PL52A*/VREF1_6 V7
PL52B*/VREF2_6 W7
PL53A W2
PL53B W1
PL55A* W8
PL55B* W9
PL56A W4
PL56B W3
PL58A/LDQS58 W6
PL58B Y6
PL59A Y2
PL59B Y1
PL61A* Y8
PL61B* AA8
PL61E_A/LLM1_GPLLT_FB_A Y5
PL61E_B/LLM1_GPLLT_FB_B Y4
PL61E_C/LLM1_GPLLT_IN_A Y9
PL61E_D/LLM1_GPLLT_IN_B Y10
PL62A AA2
PL62B AA1
PL64A* Y7
PL64B* AA7
PL65A AA4
PL65B AA3
PL67A/LDQS67 AA10
PL67B AB9
PL68A AB2
PL68B AB1
PL70A* AA5
PL70B* AB5
PL70E_A/LLM2_GPLLT_FB_A AD2
PL70E_B/LLM2_GPLLT_FB_B AD1
PL70E_C/LLM2_GPLLT_IN_A AC6
PL70E_D/LLM2_GPLLT_IN_B AC7
PL79E_A/LLM3_GPLLT_FB_A AM1
PL79E_B/LLM3_GPLLT_FB_B AM2
PL80A AN1
PL80B AN2
PL79E_C/LLM3_GPLLT_IN_A AL1
PL79E_D/LLM3_GPLLT_IN_B AL2
PL83A AP2
PL83B AP3
PL85A/LDQS85 AJ2
PL85B AJ3
PL86A AL3
PL86B AK3
PL88A* AJ4
PL88B* AK4
PL89A AN3
PL89B AM3
PL91A* AJ5
PL91B* AJ6
PL92A AL5
PL92B AM5
PL94A/LDQS94 AM6
PL94B AN6
PL95A AL4
PL95B AM4
PL97A* AP5
PL97B* AP6
VCCIO6_1 AB11
VCCIO6_2 AB12
VCCIO6_3 V11
VCCIO6_4 V12
VTT6_1 W11
VTT6_2 W10
PL71A AD4
PL71B AD3
PL74A AE2
PL74B AE1
PL77A AE4
PL77B AE3
PL82A* AD9
PL82B* AD8
PB2A
AH7
PB2B
AJ7
PB4A
AE9
PB4B
AD10
PB5A
AK6
PB5B
AL6
PB7A
AF9
PB7B
AG9
PB8A
AK7
PB8B
AL7
PB14A AN7
PB14B AP7
PB16A AN8
PB16B AP8
PB10A
AK8
PB10B
AL8
PB11A
AM7
PB11B
AM8
PB13A AH9
PB13B AJ8
R377
49.9, 1%
R377
49.9, 1%
C129
0.01uF
C129
0.01uF
C250
0.01uF
C250
0.01uF
12
C426
0.1uF
C426
0.1uF
12
34
LatticeECP3 Video Protocol Board – Revision C
User’s Guide
Figure 18. DVI/LCD/RS-232
5
5
4
4
3
3
2
2
1
1
DD
C C
B B
A A
DVDD
TFP410_D7
TFP410_D21
TMDS _TX _D ATA 0_ N
TI_TVDD
TFP410_D3
TMDS _TX _C LK _P
TFP410_D20
TFP410_D17
TFP410_D6 TMDS_TX _CLK _N
TFP410_D19
TFP410_D16
TFP410_D2
TFP410_D18
TFP410_D5
TFP410_D15
TFP410_D1
TI_TVDD
TFP410_D10
TFP410_D14
TMDS _TX _D ATA 2_ P
TFP410_D13
TFP4 10_VREF
TMDS _TX _D ATA 2_ N
TFP410_D9
TI_PVDD
TFP410_D12
TMDS _TX _D ATA 1_ P
TFP410_D0
DVDD
TFP410_D11
TMDS _TX _D ATA 1_ N
TFP410_D22
TFP410_D4
TFP410_D8
TFP410_D23
TMDS _TX _D ATA 0_ P
TI_PVDD
TI_TVDD
DVDD
TMDS _RX_ DATA2_N
TMDS _RX_ DATA2_P
TMDS_RX_DATA1_N
TMDS _RX_ DATA1_P
TMDS_RX_DATA0_N
TMDS _RX_ DATA0_P
TMDS_RX_CLK_P
TMDS_RX_CLK_N
DVI_RX_HPD
DVI_TX_G0
DVI_TX_G1
DVI_TX_G2
DVI_TX_G3
DVI_TX_G5
DVI_TX_G6
DVI_TX_G7
DVI_TX_R7
DVI_TX_R6
DVI_TX_R5
DVI_TX_R4
DVI_TX_R3
DVI_TX_R2
DVI_TX_R1
DVI_TX_R0
DVI_TX_G4
TFP4 10_VSYNC
TFP410_HSYNC
DVDD
I2C_SCL
I2C_SDA
DVDD
DKENDVDD
PDNDVDD
TX_DDC_CLK
TX_DDC_DATARX_DDC_CLK
RX_DDC_DATA
DVDD
DVI_RX_HPD
DVI_TX_B7
DVI_TX_B6
DVI_TX_B0
DVI_TX_B2
DVI_TX_B3
DVI_TX_B4
DVI_TX_B1
DVI_TX_B5
DVI_RX_DDC_CLK
DVI_TX_DDC_DATA
DVI_RX_DDC_DATA
DVI_TX_DDC_CLK
LCD3
LCD4
LCD6
LCD5
LCD8
LCD7
LCD10
LCD9
LCD_RS LCD5
LCD_E LCD6
LCD_DB1 LCD7
LCD_DB3 LCD8
LCD_DB5 LCD9
LCD_DB7 LCD10
LCD_R/WLCD0
LCD_DB0LCD1
LCD_DB2LCD2
LCD_DB4LCD3
LCD_DB6LCD4
ANODE
RS232_RXD
RS232_TXD
RS232_TXD
RS232_RXD
TMDS_RX_CLK_P
TMDS_RX_CLK_N
LCD[0..10]
LA3
LA4
MSEN
DVDD
TFP4 10_IDCK
DVI_TX_CLK TFP4 10 _DE
DVI_TX_DE
DVI_TX_VSYNC
DVI_TX_HSYNC
EDGE
SEG_C LED_SEG10
SEG_P LED_SEG11
TMDS_RX_DATA1_N
TMDS_RX_DATA2_P
TMDS_RX_DATA1_P
TMDS_RX_DATA0_P
TMDS_RX_DATA0_N
TMDS_RX_DATA2_N
LCD1
LCD0
LCD2
3_3V
3_3V
5_0V
5_0V
3_3V
5_0V
3_3V
I2C_SCL [4,13,14]
I2C_SDA [4,13,14]
TFP410_ISEL[11]
TX_HSYNC [1 6]
TX_VSYNC [16]
RX_HSYNC [15]
RX_VSYNC [15]
RX_FSYNC [15]
RX_SE_REFCLK [15]
TX_SE_REFCLK [16]
DP_TX_PWR_OUT_EN [7]
DP_RX_PWR_OUT_EN [7]
LA[1..34] [6,8,11,12]
LED_SEG[1..17] [11,12]
TX_FSYNC [1 6]
RX_GS4911_RESETn [15]
TX_GS4911_RESETn [16]
Title
Size Project Rev
Date: Sheet of
Lattice Semiconductor Corporation
5555 N.E. Moore Court
Hillsboro, Oregon. 97124
ECP3 Video Protocol Board Schematic
C
DVI / LCD / RS-232
C
916Wednesday, November 04, 2009
Title
Size Project Rev
Date: Sheet of
Lattice Semiconductor Corporation
5555 N.E. Moore Court
Hillsboro, Oregon. 97124
ECP3 Video Protocol Board Schematic
C
DVI / LCD / RS-232
C
916Wednesday, November 04, 2009
Title
Size Project Rev
Date: Sheet of
Lattice Semiconductor Corporation
5555 N.E. Moore Court
Hillsboro, Oregon. 97124
ECP3 Video Protocol Board Schematic
C
DVI / LCD / RS-232
C
916Wednesday, November 04, 2009
LED will be ON
when connecting
a powered DVI
receiver to the
DVI Tx connector.
1(G) 2(S)
3(D)
SOT-23
DVI
Top View
Backlight
Adjustment
Contrast
Adjustment
LCD Connector
RS-232
Tx
DVI
Rx
Place resistors
close to ECP3
Place resistors
close to ECP3
C165
1uF, X5R, 6.3V
C165
1uF, X5R, 6.3V
RN15 33 EXB28V330JVRN15 33 EXB28V330JV
1
2
3
4
8
7
6
5
R309 4.7KR309 4.7K
R302 OPENR302 OPEN
DVI-Integrated
J16
Molex 74320-1004
DVI-Integrated
J16
Molex 74320-1004
TMDS_Data2+
2TMDS_Data2-
1
TMDS_Data4-
4
TMDS_Data4+
5
TMDS_Data2/4_Shield
3
DDC_Clock
6
DDC_Data
7
Analog_Vertical_Sync
8
TMDS_Data1-
9
TMDS_Data1+
10
TMDS_Data1/3_Shield
11
TMDS_Data3-
12
TMDS_Data3+
13
+5V_Power
14
GND(for +5V)
15
Hot_Plug_Detect
16
TMDS_Data0-
17
TMDS_Data0+
18
TMDS_Data0/5_Shield
19
TMDS_Data5-
20
TMDS_Data5+
21
TMDS_Clock_Shield
22
TMDS _Clock +
23
TMDS _Clock -
24
Analog_Red
C1
Analog_Green
C2
Analog_Blue
C3
Analog_Horizontal_Sync
C4
Analog_Ground_1
C5
Analog_Ground_2
C6
+
C241
22uF, Tant
0805
+
C241
22uF, Tant
0805
C407
0.1uF
C407
0.1uF
R136
10K
R136
10K
R365
49.9, 1%
R365
49.9, 1%
R338 33R338 33
TP30TP3 0
R368
49.9, 1%
R368
49.9, 1%
R304 4.7KR304 4.7K
J43
HDR 9x2
J43
HDR 9x2
NC1
1NC2 2
VSS
3
RS 6
VO
5VDD 4
R/W
7E8
DB0
9DB1 10
DB2
11 DB3 12
DB4
13 DB5 14
DB6
15 DB7 16
ANODE
17 CATHODE 18
C280
0.01uF
C280
0.01uF
12
C406
1000pF
C406
1000pF
C409
0.1uF
C409
0.1uF
FB41
BLM21AG601SN1D
FB41
BLM21AG601SN1D
RN14 33 EXB28V330JVRN14 33 EXB28V330JV
1
2
3
4
8
7
6
5
TP31TP3 1
R364
49.9, 1%
R364
49.9, 1%
C402
1000pF
C402
1000pF
12
R367
49.9, 1%
R367
49.9, 1%
C410
0.01uF
C410
0.01uF
VR5
10K
Copal ST3 2E TB103
VR5
10K
Copal ST3 2E TB103
1 3
2
R346 OPENR346 OPEN
U33
MAX3232IPWR
U33
MAX3232IPWR
GND 15
VCC
16
R1IN
13
R2IN
8
T2IN
10 T1IN
11
C1+
1
C1-
3
C2+
4
C2-
5
R1OUT 12
R2OUT 9
T1OUT 14
T2OUT 7
V+
2
V-
6
R337 33R337 33
R289 OPENR289 OPEN
C279
0.1uF
C279
0.1uF
12
D34
LED-SMT1206_GREEN
D34
LED-SMT1206_GREEN
C411
1000pF
C411
1000pF
Q27
MOSFET N GSD
BSS138LT1G
Q27
MOSFET N GSD
BSS138LT1G
1
32
R363
49.9, 1%
R363
49.9, 1%
R366
49.9, 1%
R366
49.9, 1%
R362
49.9, 1%
R362
49.9, 1%
BANK 0
ECP3-95
U30A
BANK 0
ECP3-95
U30A
PT10A D5
PT10B C6
PT11A B4
PT11B A3
PT13A D6
PT13B C5
PT14A A4
PT14B A5
PT16A B7
PT16B A7
PT17A B6
PT17B A6
PT19A A8
PT19B A9
PT35A D12
PT35B E12
PT2A C3
PT2B C4
PT25B G12
PT40A G13
PT32A A12
PT32B B12
PT34A J14
PT34B H13
PT38A E13
PT38B F13
PT37A K14
PT37B K15
PT44A C13
PT44B D13
PT28B J13
PT40B H14
PT41A A13
PT41B B13
PT29B F12
PT29A E11
PT50A C14
PT50B D14
PT28A K13
PT46A J15
PT56A A14
PT56B B14
PT64A E17
PT46B H15
PT59A D15
PT59B E15
VCCIO0_1 M17
VCCIO0_2 L13
VCCIO0_3 M13
VCCIO0_4 L17
PT4A/VREF1_0 D3
PT4B/VREF2_0 C2
PT62A A15
PT62B B15
PT61B H16
PT58A G16
PT65A C16
PT65B D16
PT67A K16
PT67B L16
PT68A A16
PT68B B16
PT61A J16
PT58B G17
PT71A C17
PT71B D17
PT73A/PCLKT0_0 J17
PT73B/PCLKC0_0 H17
PT5A B1
PT5B B2
PT7B D4
PT7A E4
PT8B A2
PT8A B3
PT20A
A10
PT20B
B10
PT22A
J12
PT22B
K12
PT23A
C11
PT23B
D11
PT25A
G11
PT26A
A11
PT26B
B11
PT31A
F10
PT31B
E10
PT43A
D10
PT43B
C10
PT64B
F18
PT70A
G18
PT70B
F19
C405
0.1uF
C405
0.1uF
12
TP29TP2 9
J41 HEADER 2x2J41 HEADER 2x2
3
4
1
2
DVI-Integrated
J14
Molex 74320-1004
DVI-Integrated
J14
Molex 74320-1004
TMDS_Data2+
2TMDS_Data2-
1
TMDS_Data4-
4
TMDS_Data4+
5
TMDS_Data2/4_Shield
3
DDC_Clock
6
DDC_Data
7
Analog_Vertical_Sync
8
TMDS_Data1-
9
TMDS_Data1+
10
TMDS_Data1/3_Shield
11
TMDS_Data3-
12
TMDS_Data3+
13
+5V_Power
14
GND(for +5V)
15
Hot_Plug_Detect
16
TMDS_Data0-
17
TMDS_Data0+
18
TMDS_Data0/5_Shield
19
TMDS_Data5-
20
TMDS_Data5+
21
TMDS_Clock_Shield
22
TMDS _Clock +
23
TMDS _Clock -
24
Analog_Red
C1
Analog_Green
C2
Analog_Blue
C3
Analog_Horizontal_Sync
C4
Analog_Ground_1
C5
Analog_Ground_2
C6
R293 4.7KR293 4.7K
C391
0.1uF
C391
0.1uF
+
C284
10uF, Tant
0805
+
C284
10uF, Tant
0805
R310
4.7K
R310
4.7K
C403
0.01uF
C403
0.01uF
12
RN16 33 EXB28V330JVRN16 33 EXB28V330JV
1
2
3
4
8
7
6
5
RN17 33 EXB28V330JVRN17 33 EXB28V330JV
1
2
3
4
8
7
6
5
C408
0.01uF
C408
0.01uF
C404
1000pF
C404
1000pF
12
R299 4.7KR299 4.7K
R294 OPENR294 OPEN
R126 4.7KR126 4.7K
C394
0.1uF
C394
0.1uF
J46
HEADER 3x1
J46
HEADER 3x1
1
2
3
FB43
BLM21AG601SN1D
FB43
BLM21AG601SN1D
R335 33R335 33
+
C270
22uF, Tant
0805
+
C270
22uF, Tant
0805
R300 OPENR300 OPEN
RN38 33 EXB28V330JVRN38 33 EXB28V330JV
1
2
3
4
8
7
6
5
FB42
BLM21AG601SN1D
FB42
BLM21AG601SN1D
C395
0.1uF
C395
0.1uF
R345
1K
R345
1K
C272
0.1uF
C272
0.1uF
Q31
MOSFET N GSD
BSS138LT1G
Q31
MOSFET N GSD
BSS138LT1G
1
32
+
C283
22uF, Tant
0805
+
C283
22uF, Tant
0805
R327 1KR327 1K
C392
0.1uF
C392
0.1uF
J38
HEADER 5x2
J38
HEADER 5x2
2
4
6
8
10
1
3
5
7
9
R301 4.7KR301 4.7K
RN13 33 EXB28V330JVRN13 33 EXB28V330JV
1
2
3
4
8
7
6
5
C401
1000pF
C401
1000pF
R/HVSync
G/CTL1
B/CTL3:2
Clk Out
TFP4 10
U37
R/HVSync
G/CTL1
B/CTL3:2
Clk Out
TFP4 10
U37
IDCKP
57
IDCKN
56
DE
2
DSEL/SDA
14
ISEL/RSTN
13
PDN
10
N/C 49
DKEN
35
RESERVED (Tie to GND) 34
BSEL/SCL
15
TXCN 21
TXCP 22
TVDD _2 3 23
TX0N 24
TX0P 25
TGND _2 6 26
TX1N 27
TX1P 28
TVDD _2 9 29
TX2N 30
TX2P 31
TGND _3 2 32
MSEN/PO1 11
DATA1
62 DATA2
61 DATA3
60 DATA4
59 DATA5
58 DATA6
55 DATA7
54 DATA8
53 DATA9
52 DATA10
51 DATA11
50
DATA12
47 DATA13
46 DATA14
45 DATA15
44 DATA16
43 DATA17
42 DATA18
41 DATA19
40 DATA20
39 DATA21
38 DATA22
37 DATA23
36
TGND _2 0 20
CTL3/A3/DK3
6
CTL2/A2/DK2
7
CTL1/A1/DK1
8
VREF
3
HSYNC
4
TFAD J 19
VSYNC
5
EDGE/HTPLG
9DGND_16 16
DGND_48 48
DVDD_33 33
DGND_64 64
DVDD_1 1
DVDD_12 12
PVDD 18
PGND 17
DATA0
63
GND65
65
R336 33R336 33
+
C288
10uF, Tant
0805
+
C288
10uF, Tant
0805
R312 510, 1%R312 510, 1%
R311
150
R311
150
VR6
10K
Copal ST32ETB103
VR6
10K
Copal ST32ETB103
13
2
J40 HEADER 2x2J40 HEADER 2x2
3
4
1
2
C287
0.1uF
C287
0.1uF
C274
0.01uF
C274
0.01uF
C414
0.1uF
C414
0.1uF
R303 4.7KR303 4.7K
R369
49.9, 1%
R369
49.9, 1%
C393
0.1uF
C393
0.1uF
35
LatticeECP3 Video Protocol Board – Revision C
User’s Guide
Figure 19. ChannelLink/CameraLink
5
5
4
4
3
3
2
2
1
1
DD
C C
B B
A A
CMR_SerTC_P
CM_RX_CC1_P
CM_RX_CC1_N
CMR_CC4_N
CMR_CC3_N
CMR_CC2_N
CMR_CC1_N
CMR_CC2_P CM_RX_CC2_P
CM_RX_CC2_N
CN_RX_CLKIN_P
CN_RX_CLKIN_N
CN_RX_IN0_N
CN_RX_IN1_P
CN_RX_IN1_N
CN_RX_IN0_P
CM_RX_SerTC_P
CMR_SerTC_N
CN_RX_IN0_N
CN_RX_IN1_P
CN_RX_IN1_N
CN_RX_IN0_P
CN_RX_IN2_N
CN_RX_IN2_P
CN_RX_CLKIN_P
CN_RX_CLKIN_N
CN_RX_IN3_P
CN_RX_IN3_N
CMR_CC3_P CM_RX_CC3_P
CM_RX_CC3_N
CM_RX_SerTC_N
CMR_CC4_P CM_RX_CC4_P
CM_RX_CC4_N
CM_RX_SerTFG_N
RJ45_IN_P3
RJ45_IN_N3
CM_RX_SerTFG_P
CM_RX_X0_N
CM_RX_X0_P
CM_RX_X1_P
CM_RX_X1_N
RJ45_IN_P0
RJ45_IN_N0
RJ45_IN_N1
CM_RX_X2_P
CM_RX_X2_N
RJ45_IN_P1
RJ45_IN_N2
RJ45_IN_P2
CM_RX_X3_P
CM_RX_X3_N
CM_RX_XCLK_P
CM_RX_XCLK_N
MZ_SIG0_N
MZ_SIG0_P
MZ_SIG1_N
MZ_SIG1_P
CN_RX_IN0_P
CN_TX_OUT2_N
CN_TX_OUT1_N
CN_TX_OUT0_P
CN_TX_OUT0_N
CN_TX_CLKOUT_P
CN_TX_OUT3_P
CN_TX_OUT2_P
CN_TX_CLKOUT_N
CN_TX_OUT3_N
CN_TX_OUT1_P CN_RX_IN3_N
CN_RX_IN1_N
CN_RX_IN3_P
CN_RX_IN2_N
CN_RX_CLKIN_P
CN_RX_CLKIN_N
CN_RX_IN2_P
CN_RX_IN1_P
CN_RX_IN0_N
CM_RX_CC2_N
CM_RX_CC3_P
CM_RX_CC4_N
CM_RX_SerTC_N
CM_RX_CC1_P
CM_RX_SerTFG_P
CM_RX_X1_P
CM_RX_X2_N
CM_RX_X2_P
CM_RX_XCLK_N
CM_RX_XCLK_P
CM_RX_X3_N
CM_RX_X3_P
CM_RX_SerTC_P
CM_RX_SerTFG_N
CM_RX_CC1_N
CM_RX_CC2_P
CM_RX_CC3_N
CM_RX_CC4_P
CM_RX_X0_N
CM_RX_X0_P
CM_RX_X1_N
CMR_SerTC_P
CMR_SerTC_N
CN_RX_IN2_N
CN_RX_IN2_P
LED5
LED4
CM_RX_SerTFG_P
CM_RX_SerTFG_N
CMR_CC4_P
CMR_CC4_N
DPR_AUX_P
DPR_AUX_N
DPR_AUX_P
DPR_AUX_N
DPT_AUX_P
DPT_AUX_N
CMR_CC1_P
ECP3_XO_SIG1
ECP3_XO_SIG5
ECP3_XO_SIG4
ECP3_XO_SIG0
ECP3_XO_SIG3
ECP3_XO_SIG2
LED8
LED9
LED7
LED6
LED11
LED10
ECP3_XO_SIG6
ECP3_XO_SIG7
ECP3_XO_SIG8
ECP3_XO_SIG11
ECP3_XO_SIG10
ECP3_XO_SIG9
LED12
OSC_IN2
LED1
OSC_IN2
CM_RX_XCLK_P
CM_RX_XCLK_N
CM_RX_X0_P
CM_RX_X0_N
OSC_IN1
ACLK3
CM_RX_X3_P
CM_RX_X3_N
CM_RX_X2_P
CM_RX_X2_N
CMR_CC3_N
CMR_CC3_P
LED3
LED2
DPT_AUX_P
DPT_AUX_N
CMR_CC2_N
CMR_CC2_P
CMR_CC1_N
CMR_CC1_P
CN_TX_CLKOUT_P
CN_TX_CLKOUT_N
CN_TX_OUT0_P
CN_TX_OUT0_N
CN_TX_OUT2_N
CN_TX_OUT2_P
CN_TX_OUT1_N
CN_TX_OUT1_P
CN_TX_OUT3_P
CN_TX_OUT3_N
CN_RX_IN3_P
CN_RX_IN3_N
CM_RX_X1_N
CM_RX_X1_P
RJ45_OUT_P1
RJ45_OUT_N0
RJ45_OUT_P3
RJ45_OUT_N2 RJ45_OUT_N1
RJ45_OUT_P2
RJ45_OUT_P0
RJ45_OUT_N3
RJ45_IN_P1
RJ45_IN_N0
RJ45_IN_P3
RJ45_IN_N2 RJ45_IN_N1
RJ45_IN_P2
RJ45_IN_P0
RJ45_IN_N3
RJ45_OUT_P1
RJ45_OUT_P3
RJ45_OUT_N1
RJ45_OUT_N3
RJ45_IN_P1
RJ45_IN_P3
RJ45_IN_N0
RJ45_IN_N2
RJ45_IN_P2
RJ45_IN_N1
RJ45_IN_P0
RJ45_IN_N3
RJ45_OUT_N2
RJ45_OUT_P2
RJ45_OUT_N0
RJ45_OUT_P0
ECP3_RJ45_OUT_N2
ECP3_RJ45_OUT_P2
2_5V
2_5V
LED[1..12][12]
MZ_SE_SIG0 [7]
MZ_SE_SIG1 [7]
MZ_SIG0_P [7]
MZ_SIG0_N [7]
DP_RX_AUX_P [7]
DP_RX_AUX_N [7]
DP_TX_AUX_P [7]
DP_TX_AUX_N [7]
RX_GS4911_PCLK1 [15]
ECP3_XO_SIG[0..11] [14]
RX_GC4915_CLKOUTP [15]
RX_GC4915_CLKOUTN [15]
TX_X1 [11]
TX_GS4911_PCLK1 [16]
RX_X1 [11]
ACLK[1..3] [8,15]
OSC_IN[1..4] [11,14]
MZ_SIG1_N [7]
MZ_SIG1_P [7]
TX_CLKIN_SE[16]
RX_CLKIN_SE[15]
Title
Size Project Rev
Date: Sheet of
Lattice Semiconductor Corporation
5555 N.E. Moore Court
Hillsboro, Oregon. 97124
ECP3 Video Protocol Board Schematic
C
ChannelLink/CameraLink
C
10 16Wednesday, November 04, 2009
Title
Size Project Rev
Date: Sheet of
Lattice Semiconductor Corporation
5555 N.E. Moore Court
Hillsboro, Oregon. 97124
ECP3 Video Protocol Board Schematic
C
ChannelLink/CameraLink
C
10 16Wednesday, November 04, 2009
Title
Size Project Rev
Date: Sheet of
Lattice Semiconductor Corporation
5555 N.E. Moore Court
Hillsboro, Oregon. 97124
ECP3 Video Protocol Board Schematic
C
ChannelLink/CameraLink
C
10 16Wednesday, November 04, 2009
BANK 3 (2.5V)
BANK 2 (2.5V)
ChannelLink
CameraLink
Tx
Rx
Rx
Place under ECP3 device Place close to ECP3 devicePlace close to ECP3 devicePlace close to ECP3 device
Place close to ECP3 device
RJ-45 Connector for signal quality
measurement across CAT-5 cable
(Not an Ethernet Port)
Pair 1 (AA25, AA26)
Pair 0 (W27, W26)
Pair 3 (Y26, Y25)
Pair 2 (W30, W29)
RJ-45 Output
Differential Output Pair Traces
Category-5 Cable
Pairing Information:
(1,2), (3,6), (4,5), (7,8)
RJ-45 Connector for signal quality
measurement across CAT-5 cable
(Not an Ethernet Port)
Pair 1 (AC32, AC31)
Pair 0 (AM34, AM33)
Pair 3 (P30, R29)
Pair 2 (AA34, AA33)
RJ-45 Input
Differential Input Pair Traces
Category-5 Cable
Pairing Information:
(1,2), (3,6), (4,5), (7,8)
R74
49.9, 1%
R74
49.9, 1%
J12
MDR-26
3M 10226-1210VE
J12
MDR-26
3M 10226-1210VE
inner shield1
1
inner shield2
14
X0-
25
X0+
12
X1-
24
X1+
11
X2-
23
X2+
10
XCLK-
22
XCLK+
9
X3-
21
X3+
8
SerTC+
20
SerTC-
7
SerTFG-
19
SerTFG+
6
CC1-
18
CC1+
5
CC2+
17
CC2-
4
CC3-
16
CC3+
3
CC4+
15
CC4-
2
inner shield3
13
inner shield4
26
mount-L
27
mount-R
28
R81 100
R81 100
R128
140
R128
140
R56 510, 1%R56 510, 1%
J9
MDR-26
10226-1210VE3M
J9
MDR-26
10226-1210VE3M
DDC_Gnd_1
1
TxOut0-
14
TxOut0Gnd
2
TxOut0+
15
Sense
3
USB/DDC_Gnd
16
TxOut1-
4
TxOut1Gnd
17
TxOut1+
5
DDC/SDA
18
TxOut2-
6
TxOut2Gnd
19
TxOut2+
7
USB+
20
USB_Shield
8
USB-
21
DDC/SCL
9
TxClkOut-
22
TxClkOutGn d
10
TxClkOut+
23
USB_+5VDC
11
DDC_+5VDC
24
TxOut3-
12
TxOut3Gnd
25
TxOut3+
13
DDC_Gnd_26
26
Mounting_R
27
Mounting_L
28
BANK 3
RDQS49 RDQS58
RDQS67 RDQS85 RDQS94
ECP3-95
U30D
BANK 3
RDQS49 RDQS58
RDQS67 RDQS85 RDQS94
ECP3-95
U30D
PR44A V31
PR44B V30
PR46A*/PCLKT3_0 U28
PR46B*/PCLKC3_0 V28
PR47A W34
PR47B W33
PR49A/RDQS49 V27
PR49B V26
PR50A W32
PR50B W31
PR52A*/VREF1_3 V29
PR52B*/VREF2_3 W28
PR53A W30
PR53B W29
PR55A* W27
PR55B* W26
PR56A Y34
PR56B Y33
PR61E_C/RLM1_GPLLT_IN_A Y28
PR61E_D/RLM1_GPLLT_IN_B Y27
PR59A Y32
PR59B Y31
PR61A* Y26
PR61B* Y25
PR61E_A/RLM1_GPLLT_FB_A AA34
PR61E_B/RLM1_GPLLT_FB_B AA33
PR58A/RDQS58 Y30
PR58B AA29
PR62A AB34
PR62B AB33
PR64A* AA25
PR64B* AA26
PR65A AA31
PR70E_A/RLM2_GPLLT_FB_A AC32
PR70E_B/RLM2_GPLLT_FB_B AC31
PR67A/RDQS67 AB30
PR70E_D/RLM2_GPLLT_IN_B AB29
PR79E_A/RLM3_GPLLT_FB_A AM34
PR79E_B/RLM3_GPLLT_FB_B AM33
PR79E_C/RLM3_GPLLT_IN_A AJ34
PR79E_D/RLM3_GPLLT_IN_B AK34
PR80A AN34
PR80B AN33
PR82A* AH33
PR82B* AJ33
PR83A AP33
PR83B AP32
PR85A/RDQS85 AL34
PR85B AL33
PR86A AL32
PR86B AK32
PR88A* AJ31
PR88B* AK31
PR89A AN32
PR89B AM32
PR91A* AL30
PR91B* AM30
PR92A AP31
PR92B AN31
PR94A/RDQS94 AP29
PR94B AP30
PR95A AL31
PR95B AM31
PR97A* AM29
PR97B* AN29
VCCIO3_1 AB23
VCCIO3_2 AB24
VCCIO3_3 V24
VCCIO3_4 V23
VTT3_1 W25
VTT3_2 W24
PR70E_C/RLM2_GPLLT_IN_A AB28
PR65B AA30
PR67B AC30
PR68A AC34
PR68B AC33
PR70A* AA28
PR70B* AA27
PR71A
AE32
PR71B
AE31
PR74A
AE30
PR74B
AE29
PR77A
AF32
PR77B
AF31
PR131A
AP28
PR131B
AN28
PR133A
AP27
PR133B
AN27
PR134A
AM27
PR134B
AL27
PR136A
AH26
PR136B
AG26
PR137A
AM28
PR137B
AL28
PR139A
AK27
PR139B
AJ27
PR140A
AK28
PR140B
AJ28
PR142A
AH27
PR142B
AH28
PR143A
AL29
PR143B
AK29
PR145A
AF26
PR145B
AE26
C180
0.01uF
C180
0.01uF
R77
49.9, 1%
R77
49.9, 1%
R55
510, 1%
R55
510, 1%
R67 100
R67 100
R61 100R61 100
R195 100R195 100
BANK 2
RDQS22 RDQS31 RDQS40
ECP3-95
U30C
BANK 2
RDQS22 RDQS31 RDQS40
ECP3-95
U30C
PR17A N30
PR17B N29
PR19A* N26
PR19B* P26
PR20A N32
PR20B N31
PR22A/RDQS22 N27
PR22B N28
PR23A N34
PR23B N33
PR25A* P28
PR25B* P27
PR25E_A/RUM2_GPLLT_FB_A P32
PR25E_B/RUM2_GPLLT_FB_B P31
PR25E_C/RUM2_GPLLT_IN_A P30
PR25E_D/RUM2_GPLLT_IN_B R29
PR26A P34
PR26B P33
PR28A* R28
PR28B* R27
PR29A R31
PR29B R30
PR31A/RDQS31 R26
PR31B R25
PR32A R34
PR32B R33
PR34A*/VREF1_2 T29
PR34B*/VREF2_2 T28
PR35A T32
PR35B T31
PR37A*/RUM0_GDLLT_IN_A T26
PR37B*/RUM0_GDLLT_IN_B T27
PR38A/RUM0_GDLLT_FB_A T34
PR38B/RUM0_GDLLT_FB_B T33
PR40A/RDQS40 T30
PR40B U30
PR41A U32
PR41B U31
PR43A*/PCLKT2_0 U26
PR43B*/PCLKC2_0 U27
PR43E_A/RUM0_GPLLT_FB_A U34
PR43E_B/RUM0_GPLLT_FB_B U33
PR43E_C/RUM0_GPLLT_IN_A V34
PR43E_D/RUM0_GPLLT_IN_B V33
VCCIO2_1 N24
VCCIO2_2 U23
VCCIO2_3 N23
VCCIO2_4 U24
VTT2_1 T25
VTT2_2 T24
R194 100R194 100
R129 158R129 158
R192 100R192 100
R80 100R80 100
R73 100
R73 100
R204 100R204 100
R206 100R206 100
R70 100R70 100
R68 100R68 100
140
165
165
140
165
165
RN32 CAT16-LV2F6LF
140
165
165
140
165
165
RN32 CAT16-LV2F6LF
5
6
7
81
2
3
4
J44
RJ-45
J44
RJ-45
1
122
3
344
5
566
7
788
11
11
12
12
R71 100R71 100
R76 100R76 100
R52
510, 1%
R52
510, 1%
J10
MDR-26
10226-1210VE3M
J10
MDR-26
10226-1210VE3M
DDC_Gnd_1
1
RxIn3+
14
RxIn3Gnd
2
RxIn3-
15
DDC_+5VDC
3
USB_+5VDC
16
RxClkIn+
4
RxClkInGnd
17
RxClkIn-
5
DDC/SCL
18
USB-
6
USB_Shield
19
USB+
7
RxIn2+
20
RxIn2Gnd
8
RxIn2-
21
DDC/SDA
9
RxIn1+
22
RxIn1Gnd
10
RxIn1-
23
USB/DDC_Gnd
11
Sense
24
RxIn0+
12
RxIn0Gnd
25
RxIn0-
13
DDC_Gnd_26
26
Mounting_R
27 Mounting_L
28
R65 100R65 100
R78 OPENR78 OPEN
R53
510, 1%
R53
510, 1%
140
165
165
140
165
165
RN33 CAT16-LV2F6LF
140
165
165
140
165
165
RN33 CAT16-LV2F6LF
5
6
7
8
1
2
3
4
R130 158R130 158
R62
49.9, 1%
R62
49.9, 1%
140
165
165
140
165
165
RN31 CAT16-LV2F6LF
140
165
165
140
165
165
RN31 CAT16-LV2F6LF
5
6
7
81
2
3
4
R72 OPENR72 OPEN
R64 100
R64 100
C231
0.01uF
C231
0.01uF
R60 100R60 100
R66
49.9, 1%
R66
49.9, 1%
R58 100R58 100
R63 100R63 100
J45
RJ-45
J45
RJ-45
1
122
3
344
5
566
7
788
11
11
12
12
36
LatticeECP3 Video Protocol Board – Revision C
User’s Guide
Figure 20. TI-ADC/Clocks
5
5
4
4
3
3
2
2
1
1
DD
C C
B B
A A
D2_M
D2_P
DA1_M
DA1_P
DA0_P
DA0_M
D0_P
D1_P
D1_M
D3_M
D3_P
D6_M
D5_M
D5_P
D6_P
D7_M
D7_P
DB0_M
DB0_P
DB1_M
DB1_P
DCLK_M
DCLK_P
DD1_M
DD1_P
DC1_M
DC1_P
DD0_M
DD0_P
DC0_M
DC0_P
D4_M
D4_P
D0_M
LED_SEG9SEG_N
LED_SEG3SEG_K
LED_SEG12
SEG_U
LED_SEG15SEG_S
LED_SEG8SEG_E
LED_SEG5SEG_G
LED_SEG14SEG_R
LED_SEG16SEG_DP
LED_SEG7SEG_F
LED_SEG17SEG_B
LED_SEG4SEG_H
LED_SEG13SEG_D
SEG_A LED_SEG1
LED_SEG2SEG_M
LED_SEG6SEG_T
D0_P
FCLK_PS
DCLK_PS
OSC_IN2
OSC_IN4
OSC_IN3
OSC_IN1
SMA_CLK_P
SMA_CLK_N
FCLK_P
FCLK_M
DB1_PS
DB0_MS
DB1_MS
DB0_PS
D5_PS
D4_MS
D5_MS
D4_PS
D1_PS
FCLK_PS
DCLK_MS DCLK_MS
FCLK_MS FCLK_MS
DCLK_PS
D7_PS
D6_MS
D7_MS
D6_PS
DC1_PS
DC0_MS
DC1_MS
DC0_PS
D0_MS
D1_MS
D0_PS
DD1_PS
DD0_MS
DD1_MS
DD0_PS
D3_PS
D2_MS
D3_MS
D2_PS
DA1_PS
DA0_MS
DA1_MS
DA0_PS
D0_M
D1_M
D3_P
D2_P
DA1_P
DA0_P
DB1_M
DB0_M
FCLK_M
DCLK_M
DC0_M
DC1_M
DD0_P
DD1_M
DD0_M
D5_M
D4_M
D7_P
D6_P
FPGA_SDATA TI_ADC3
FPGA_SCLK TI_ADC4
FPGA_PDN TI_ADC1
FPGA_SEN TI_ADC2
ADC_RST TI_ADC0
TI_ADC4
TI_ADC1
TI_ADC2
TI_ADC3
TI_ADC0
LA5
LA6
LA7
LA8
LA9
LA10
LA11
LA12
LA13
LA14
LA15
LA16
LA17
DD1_P
DC0_P
FCLK_P
DA1_M
D5_P
DB1_P
D7_M
D3_M
D4_P
DCLK_P
DC1_P
DB0_P
DA0_M
D6_M
D2_M
D1_P
2_5V
3_3V3_3V
3_3V
3_3V
PCIE_PERSTN [7]
SI570_EN [7,8]
SI570_SCL [7]
SI570_SDA [7]
SMA_CLK_P [8]
SMA_CLK_N [8]
TX_X1 [10]
RX_X1 [10]
LED_SEG[1..17] [9,12]
TFP410_ISEL [9]
GSRN [4,6]
TI_ADC[0..4][6]
LA[1..34] [6,8,9,12]
OSC_IN[1..4] [10,14]
Title
Size Project Rev
Date: Sheet of
Lattice Semiconductor Corporation
5555 N.E. Moore Court
Hillsboro, Oregon. 97124
ECP3 Video Protocol Board Schematic
C
TI-ADC / Clocks
C
11 16Wednesday, November 04, 2009
Title
Size Project Rev
Date: Sheet of
Lattice Semiconductor Corporation
5555 N.E. Moore Court
Hillsboro, Oregon. 97124
ECP3 Video Protocol Board Schematic
C
TI-ADC / Clocks
C
11 16Wednesday, November 04, 2009
Title
Size Project Rev
Date: Sheet of
Lattice Semiconductor Corporation
5555 N.E. Moore Court
Hillsboro, Oregon. 97124
ECP3 Video Protocol Board Schematic
C
TI-ADC / Clocks
C
11 16Wednesday, November 04, 2009
100MHZ
GENERAL PURPOSE CLOCKS
TI ADC
SMA & OSC REF CLKs
BANK 1 (2.5V)
For LVDS Rx:
Populate EXBV8VR000V (Zero Ohm Jumper) and 100 Ohm Resistor
For LVDS Tx:
Populate CAT16-LV2F6LF instead and remove 100 Ohm Resistor
Place close to ECP3
(N7)
(N6)
U28
CY2304-1
U28
CY2304-1
REF
1
CLKA1
2
CLKA2
3
GND
4CLKB1 5
CLKB2 6
VDD 7
FBK 8
R82100 R82100
R193 33R193 33FB44
BLM21AG601SN1D
FB44
BLM21AG601SN1D
140
165
165
140
165
165
RN22 EXBV8VR000V
140
165
165
140
165
165
RN22 EXBV8VR000V
5
6
7
81
2
3
4
J42
Samtec QSH
QSH-060-01-F-D-A
J42
Samtec QSH
QSH-060-01-F-D-A
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121122
123124
125126
127
128
J26
SMA
73391-0060
J26
SMA
73391-0060
1
R208
OPEN
R208
OPEN
R221 100R221 100
C384
0.1uF
C384
0.1uF
12
140
165
165
140
165
165
RN37 EXBV8VR000V
140
165
165
140
165
165
RN37 EXBV8VR000V
5
6
7
81
2
3
4
Y5
OSC
OSC 27 MHz 3.3V SMD 25ppm
Y5
OSC
OSC 27 MHz 3.3V SMD 25ppm
N/C
1
GND
2OUT 3
Vcc 4
BANK 1
ECP3-95
U30B
BANK 1
ECP3-95
U30B
PT101A D21
PT101B E21
PT103A H20
PT103B J20
PT104A A22
PT104B B22
PT106A J22
PT106B J23
PT107A C22
PT107B D22
PT109A J21
PT110A A23
PT110B B23
PT118A G23
PT113A C23
PT113B D23
PT115A K22
PT115B K21
PT116A A24
PT116B B24
PT109B H22
PT118B H23
PT119A D24
PT119B E24
PT121A K23
PT121B K24
PT122A A25
PT122B B25
PT124A C28
PT124B D28
PT125A C25
PT125B D25
PT127A G26
PT127B G25
PT128A B28
PT128B A28
PT130A A26
PT130B A27
PT131A A29
PT131B A30
PT133A H26
PT133B H25
PT134A A31
PT134B B31
PT136A/VREF1_1 C29
PT136B/VREF2_1 C30
PT74A A17
PT74B B17
PT76A/PCLKT1_0 E19
PT76B/PCLKC1_0 E20
PT77A A18
PT77B B18
PT79A J18
PT79B H18
PT80A D18
PT80B E18
PT83A A19
PT83B B19
PT85A K20
PT85B L19
PT86A C19
PT86B D19
PT88A J19
PT88B K19
PT89A A20
PT89B B20
PT82A G19
PT82B H19
VCCIO1_1 L22
VCCIO1_2 L18
VCCIO1_3 M22
VCCIO1_4 M18
PT91A
G20 PT91B G21
PT95A
C20
PT95B
D20
PT97A
F21 PT97B F22
PT98A
A21
PT98B
B21
PT112A
E22
PT112B
E23
J13
HEADER 5x1
J13
HEADER 5x1
1
2
3
4
5
140
165
165
140
165
165
RN20 EXBV8VR000V
140
165
165
140
165
165
RN20 EXBV8VR000V
5
6
7
8
1
2
3
4
R84100 R84100
R215 100R215 100
FB45
BLM21AG601SN1D
FB45
BLM21AG601SN1D
R88100 R88100
Y4
OSC
OSC 27 MHz 3.3V SMD 25ppm
Y4
OSC
OSC 27 MHz 3.3V SMD 25ppm
N/C
1
GND
2OUT 3
Vcc 4
R222 100R222 100
140
165
165
140
165
165
RN18 EXBV8VR000V
140
165
165
140
165
165
RN18 EXBV8VR000V
5
6
7
8
1
2
3
4
R83100 R83100
R87100 R87100
R90100 R90100
R219100 R219100
C387
1uF, X5R, 6.3V
C387
1uF, X5R, 6.3V
Y3
OSC
OSC 100 MHz 3.3V SMD 50ppm
Y3
OSC
OSC 100 MHz 3.3V SMD 50ppm
N/C 1
GND 2
OUT
3
Vcc
4
R198
OPEN
R198
OPEN
R217 100R217 100
140
165
165
140
165
165
RN36 EXBV8VR000V
140
165
165
140
165
165
RN36 EXBV8VR000V
5
6
7
8
1
2
3
4
R218 100R218 100
C371
0.1uF
C371
0.1uF
12
C386
0.1uF
C386
0.1uF
12
R85100 R85100
R220100 R220100
140
165
165
140
165
165
RN34 EXBV8VR000V
140
165
165
140
165
165
RN34 EXBV8VR000V
5
6
7
81
2
3
4
C369
0.1uF
C369
0.1uF
12
R91100 R91100
140
165
165
140
165
165
RN19 EXBV8VR000V
140
165
165
140
165
165
RN19 EXBV8VR000V
5
6
7
81
2
3
4
C385
1uF, X5R, 6.3V
C385
1uF, X5R, 6.3V
R86100 R86100
J25
SMA
73391-0060
J25
SMA
73391-0060
1
C370
0.01uF
C370
0.01uF
12
R89100 R89100
R200 33R200 33
140
165
165
140
165
165
RN35 EXBV8VR000V
140
165
165
140
165
165
RN35 EXBV8VR000V
5
6
7
81
2
3
4
140
165
165
140
165
165
RN21 EXBV8VR000V
140
165
165
140
165
165
RN21 EXBV8VR000V
5
6
7
8
1
2
3
4
R216 100R216 100
37
LatticeECP3 Video Protocol Board – Revision C
User’s Guide
Figure 21. LEDs/Switches/LA Probe
5
5
4
4
3
3
2
2
1
1
DD
C C
B B
A A
LED3
LED6
LED1
LED8
LED4
LED5
LED2
LED7
LED9
LED11
LED10
LED12
LED9
LED10
LED11
LED12
LED2
LED3
LED1
LED4
LED5
LED6
LED7
LED8LED_SEG9 SEG_N
LED_SEG3 SEG_K
LED_SEG12 SEG_U
LED_SEG15 SEG_S
LED_SEG8 SEG_E
LED_SEG5 SEG_G
LED_SEG11 SEG_P
LED_SEG14 SEG_R
LED_SEG16 SEG_DP
LED_SEG7 SEG_F
LED_SEG17 SEG_B
LED_SEG10 SEG_C
LED_SEG4 SEG_H
LED_SEG13 SEG_D
SG_B
SEG_ALED_SEG1
LED_SEG2 SEG_M
LED_SEG6 SEG_T
SG_DP
SG_DP
SG_S
SG_R
SG_D
SG_U
SG_P
SG_C
SG_N
SG_E
SG_F
SG_T
SG_G
SG_H
SG_K
SG_M
SG_A
SG_U
SG_T
SG_S
SG_R
SG_P
SG_N
SG_M
SG_K
SG_H
SG_G
SG_F
SG_E
SG_D
SG_C
SG_B
SG_A
LA34
LA32
LA22
LA26
LA16
LA30
LA14
LA20
LA12
LA28
LA24
LA10
LA6
LA8
LA4
LA2
LA18
LA27
LA33
LA31
LA25
LA29
LA17
LA13
LA23
LA21
LA5
LA15
LA11
LA7
LA19
LA3
LA1
LA9
LA34
LA32
LA22
LA26
LA16
LA30
LA14
LA20
LA12
LA28
LA24
LA10
LA6
LA8
LA4
LA2
LA18
LA27
LA33
LA31
LA25
LA29
LA17
LA13
LA23
LA21
LA5
LA15
LA11
LA7
LA19
LA3
LA1
LA9
SWITCH12
SWITCH11
SWITCH10
SWITCH9
SWITCH4
SWITCH3
SWITCH2
SWITCH1
SWITCH6
SWITCH7
SWITCH5
SWITCH8
PB3
PB1
PB2
PB4
12_0V
12_0V
12_0V
12_0V
12_0V
12_0V
12_0V
12_0V
12_0V
12_0V
12_0V
12_0V
3_3V
2_5V
3_3V
3_3V
LED[1..12][10]
LED_SEG[1..17][9,11]
LA[1..34] [6,8,9,11]
SWITCH[1..12] [8]
PB[1..4] [8]
Title
Size Project Rev
Date: Sheet of
Lattice Semiconductor Corporation
5555 N.E. Moore Court
Hillsboro, Oregon. 97124
ECP3 Video Protocol Board Schematic
C
LEDs/Switches/LA Probe
C
12 16Wednesday, November 04, 2009
Title
Size Project Rev
Date: Sheet of
Lattice Semiconductor Corporation
5555 N.E. Moore Court
Hillsboro, Oregon. 97124
ECP3 Video Protocol Board Schematic
C
LEDs/Switches/LA Probe
C
12 16Wednesday, November 04, 2009
Title
Size Project Rev
Date: Sheet of
Lattice Semiconductor Corporation
5555 N.E. Moore Court
Hillsboro, Oregon. 97124
ECP3 Video Protocol Board Schematic
C
LEDs/Switches/LA Probe
C
12 16Wednesday, November 04, 2009
LEDs
SIGNAL SEGMENT BGA
------ ------- ---
LED_SEG1 A H20
LED_SEG2 M H19
LED_SEG3 K G19
LED_SEG4 H K19
LED_SEG5 G J19
LED_SEG6 T D19
LED_SEG7 F C19
LED_SEG8 E L19
LED_SEG9 N K20
LED_SEG10 C G18
LED_SEG11 P F19
LED_SEG12 U E18
LED_SEG13 D D18
LED_SEG14 R H18
LED_SEG15 S J18
LED_SEG16 DP B18
LED_SEG17 B A18
16-SEGMENT DISPLAY
SIGNAL DIODE COLOR BGA
------ ----- ----- ---
LED1 D26 Red T27
LED2 D24 Orange T28
LED3 D23 Green T29
LED4 D22 Blue N31
LED5 D17 Red N32
LED6 D16 Orange AK32
LED7 D15 Green AL32
LED8 D14 Blue AP32
LED9 D13 Red AP33
LED10 D12 Orange AN33
LED11 D11 Green AN34
LED12 D10 Blue AA31
Top View
1(G) 2(S)
3(D)
SOT-23 MOSFET
N-Channel
BSS138LT1G
PLACE CLOSE TO
LA CONNECTOR
LOGIC ANALYZER PROBE
DIP SWITCHES
PB2
TACT SWITCHES
PB4
PB3
PB1
SIGNAL SWITCH/POS BGA
------ ---------- ---
SWITCH1 SW1-1 Y5
SWITCH2 SW1-2 Y4
SWITCH3 SW1-3 Y9
SWITCH4 SW1-4 Y10
SWITCH5 SW3-1 AD2
SWITCH6 SW3-2 AD1
SWITCH7 SW3-3 AC6
SWITCH8 SW3-4 AC7
SWITCH9 SW4-1 AM1
SWITCH10 SW4-2 AM2
SWITCH11 SW4-3 AE1
SWITCH12 SW4-4 AE2
(P1)
(U5)
(U4)
(P2)
R227
680
R227
680
R231 1KR231 1K
R257 10KR257 10K
R235 10KR235 10K
A
BCDEFGH
KMNPRSTU
DP
D30
16-Seg
Lite-On
LTP-587HR
A
BCDEFGH
KMNPRSTU
DP
D30
16-Seg
Lite-On
LTP-587HR
18
2
1
16
13
9
8
6
5
4
7
3
11
17
15
12
14
10
RN30 150 EXB28V151JVRN30 150 EXB28V151JV
1
2
3
4
8
7
6
5
SW8
TL3301SPF160QG
Tactile Switch
SW8
TL3301SPF160QG
Tactile Switch
1 3
2 4
R251 10KR251 10K
1
0
SW1A
76STC04T
1
0
SW1A
76STC04T
12
11
1
R213 10KR213 10K
J36
HEADER 18x1
J36
HEADER 18x1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
R236
680
R236
680
R207
680
R207
680
R228 1KR228 1K
D26
LED-SMT1206_RED
D26
LED-SMT1206_RED
Q19
MOSFET N GSD
BSS138LT1G
Q19
MOSFET N GSD
BSS138LT1G
1
32
D23
LED-SMT1206_GREEN
D23
LED-SMT1206_GREEN
1
0
SW1C
76STC04T
1
0
SW1C
76STC04T
9
8
4
R329
4.7K
R329
4.7K
R316
4.7K
R316
4.7K
RN24 1K EXB28V102JVRN24 1K EXB28V102JV
1
2
3
4
8
7
6
5
D10
LED-SMT1206_BLUE
D10
LED-SMT1206_BLUE
R199 10KR199 10K
1
0
SW4A
76STC04T
1
0
SW4A
76STC04T
12
11
1
R212 1KR212 1K
R333
4.7K
R333
4.7K
Q18
MOSFET N GSD
BSS138LT1G
Q18
MOSFET N GSD
BSS138LT1G
1
32
D22
LED-SMT1206_BLUE
D22
LED-SMT1206_BLUE
R202
680
R202
680
R256 1KR256 1K
R332
4.7K
R332
4.7K
D11
LED-SMT1206_GREEN
D11
LED-SMT1206_GREEN
R255
680
R255
680
1
0
SW4B
76STC04T
1
0
SW4B
76STC04T
10
2
3
1
0
SW3D
76STC04T
1
0
SW3D
76STC04T
7
5
6
RN29 150 EXB28V151JVRN29 150 EXB28V151JV
1
2
3
4
8
7
6
5
R209 1KR209 1K
R238 10KR238 10K
R229 10KR229 10K
SW7
TL3301SPF160QG
Tactile Switch
SW7
TL3301SPF160QG
Tactile Switch
1 3
2 4
SW10
TL3301SPF160QG
Tactile Switch
SW10
TL3301SPF160QG
Tactile Switch
1 3
2 4
Q17
MOSFET N GSD
BSS138LT1G
Q17
MOSFET N GSD
BSS138LT1G
1
32
R253 1KR253 1K
R254 10KR254 10K
D13
LED-SMT1206_RED
D13
LED-SMT1206_RED
1
0
SW3C
76STC04T
1
0
SW3C
76STC04T
9
8
4
J29
Mictor Conn
J29
Mictor Conn
5V
1SCL 2
GND
3SDA 4
CLK1
5CLK 6
7
788
9
910 10
11
11 12 12
13
13 14 14
15
15 16 16
17
17 18 18
19
19 20 20
21
21 22 22
23
23 24 24
25
25 26 26
27
27 28 28
29
29 30 30
31
31 32 32
33
33 34 34
35
35 36 36
37
37 38 38
GND39
39
GND40
40
GND41
41
GND42
42
GND43
43
Q25
MOSFET N GSD
BSS138LT1G
Q25
MOSFET N GSD
BSS138LT1G
1
32
R127 150R127 150
D16
LED-SMT1206_ORANGE
D16
LED-SMT1206_ORANGE
RN25 1K EXB28V102JVRN25 1K EXB28V102JV
1
2
3
4
8
7
6
5
R249
680
R249
680
R203 1KR203 1K
R205 10KR205 10K
R330
4.7K
R330
4.7K
R233
680
R233
680
Q26
MOSFET N GSD
BSS138LT1G
Q26
MOSFET N GSD
BSS138LT1G
1
32
1
0
SW3A
76STC04T
1
0
SW3A
76STC04T
12
11
1
R250 1KR250 1K
U38
MAX6817
U38
MAX6817
IN1
1
GND
2
IN2
3
OUT2 4
VCC 5
OUT1 6
RN27 150 EXB28V151JVRN27 150 EXB28V151JV
1
2
3
4
8
7
6
5
Q16
MOSFET N GSD
BSS138LT1G
Q16
MOSFET N GSD
BSS138LT1G
1
32
D12
LED-SMT1206_ORANGE
D12
LED-SMT1206_ORANGE
J35
HEADER 18x1
J35
HEADER 18x1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
R230
680
R230
680
Q24
MOSFET N GSD
BSS138LT1G
Q24
MOSFET N GSD
BSS138LT1G
1
32
R197 1KR197 1K
D14
LED-SMT1206_BLUE
D14
LED-SMT1206_BLUE
R196
680
R196
680
R247 1KR247 1K
C417
0.1uF
C417
0.1uF
RN23 1K EXB28V102JVRN23 1K EXB28V102JV
1
2
3
4
8
7
6
5
Q15
MOSFET N GSD
BSS138LT1G
Q15
MOSFET N GSD
BSS138LT1G
1
32
1
0
SW3B
76STC04T
1
0
SW3B
76STC04T
10
2
3
R232 10KR232 10K
R248 10KR248 10K
Q23
MOSFET N GSD
BSS138LT1G
Q23
MOSFET N GSD
BSS138LT1G
1
32
RN28 150 EXB28V151JVRN28 150 EXB28V151JV
1
2
3
4
8
7
6
5
SW9
TL3301SPF160QG
Tactile Switch
SW9
TL3301SPF160QG
Tactile Switch
13
2 4
1
0
SW4C
76STC04T
1
0
SW4C
76STC04T
9
8
4
R252
680
R252
680
R237 1KR237 1K
R210 10KR210 10K
R246
680
R246
680
D17
LED-SMT1206_RED
D17
LED-SMT1206_RED
Q14
MOSFET N GSD
BSS138LT1G
Q14
MOSFET N GSD
BSS138LT1G
1
32
R317
4.7K
R317
4.7K
D15
LED-SMT1206_GREEN
D15
LED-SMT1206_GREEN
C420
0.1uF
C420
0.1uF
1
0
SW4D
76STC04T
1
0
SW4D
76STC04T
7
5
6
1
0
SW1D
76STC04T
1
0
SW1D
76STC04T
7
5
6
Q21
MOSFET N GSD
BSS138LT1G
Q21
MOSFET N GSD
BSS138LT1G
1
32
D24
LED-SMT1206_ORANGE
D24
LED-SMT1206_ORANGE
R234 1KR234 1K
U39
MAX6817
U39
MAX6817
IN1
1
GND
2
IN2
3
OUT2 4
VCC 5
OUT1 6
1
0
SW1B
76STC04T
1
0
SW1B
76STC04T
10
2
3
R211
680
R211
680
R320
4.7K
R320
4.7K
Q20
MOSFET N GSD
BSS138LT1G
Q20
MOSFET N GSD
BSS138LT1G
1
32
R319
4.7K
R319
4.7K
38
LatticeECP3 Video Protocol Board – Revision C
User’s Guide
Figure 22. SDI Drivers and Equalizers
5
5
4
4
3
3
2
2
1
1
DD
C C
B B
A A
I2C_SDA
I2C_SCL
3_3V_SDI_DE 3_3V_SDI_DE
3_3V_SDI_DE
3_3V_SDI_DE
3_3V_SDI_DE
3_3V_SDI_DE
3_3V_SDI_DE 3_3V_SDI_DE
3_3V_SDI_DE 3_3V_SDI_DE
3_3V_SDI_DE
3_3V_SDI_DE
3_3V_SDI_DE
3_3V_SDI_DE
3_3V_SDI_DE
3_3V 3_3V
3_3V_SDI_DE
3_3V
3_3V
CD_CH0 [14]
MUTE_CH0 [14]
PCSA_HDINP0 [7]
PCSA_HDINN0 [7]
PCSA_HDOUTN0[7]
PCSA_HDOUTP0[7]
DISABLE_CH0[14]
I2C_SDA [4,9,14]
I2C_SCL [4,9,14]
SDI_DRV_RSTI[14]
SDI_DRV_FAULT[14]
BYPASS_CH0 [14]
SD_HD_CH0 [14]
MUTE_CH1 [14]
BYPASS_CH1 [14]
PCSA_HDINP1 [7]
PCSA_HDINN1 [7]
CD_CH1 [14]
SD_HD_CH1 [14]
DISABLE_CH1[14]
PCSA_HDOUTN1[7]
PCSA_HDOUTP1[7]
Title
Size Project Rev
Date: Sheet of
Lattice Semiconductor Corporation
5555 N.E. Moore Court
Hillsboro, Oregon. 97124
ECP3 Video Protocol Board Schematic
C
SDI Drivers and Equalizers
C
13 16Wednesday, November 04, 2009
Title
Size Project Rev
Date: Sheet of
Lattice Semiconductor Corporation
5555 N.E. Moore Court
Hillsboro, Oregon. 97124
ECP3 Video Protocol Board Schematic
C
SDI Drivers and Equalizers
C
13 16Wednesday, November 04, 2009
Title
Size Project Rev
Date: Sheet of
Lattice Semiconductor Corporation
5555 N.E. Moore Court
Hillsboro, Oregon. 97124
ECP3 Video Protocol Board Schematic
C
SDI Drivers and Equalizers
C
13 16Wednesday, November 04, 2009
SDI Rx #0
Equalizer
Driver
channel 0
Driver
channel 1
Equalizer
SDI Rx #1
SDI Tx #1
Voltage adjustment range : 0.0V to 3.3V
Turn clockwise to increase the voltage
Voltage adjustment range : 0.0V to 3.3V
Turn clockwise to increase the voltage
SDI Tx #0
channel 0 channel 1
R165 75
R165 75
C297
0.01uF
C297
0.01uF
R172 75
R172 75
R187
4.7K
R187
4.7K
C360
0.47uF
C360
0.47uF
C306
0.47uF
C306
0.47uF
U21
GS2974B
U21
GS2974B
VEE_A_1
1
SDI
2
SDI
3
VEE_A_4
4
AGC
5
AGC
6
BYPASS
7
MCLADJ
8
VEE_D_9 9
SDO 10
SDO 11
VEE_D_12 12
VCC_D 13
MUTE 14
CD 15
VCC_A 16
Center PAD
17
U22
LMH0303
U22
LMH0303
DDI
1
DDI
2
VEE
3
RSET
4
RSTI
5
ENABLE
6
SDA
7
SCL
8
VCC 9
SD/HD 10
SDO 11
SDO 12
FAULT 13
NC2 14
NC1 15
RSTO 16
Center PAD
17
R157
150
R157
150
+
C300
4.7uF, Tant
0805_1
+
C300
4.7uF, Tant
0805_1
Q29
MOSFET N GSD
BSS138LT1G
Q29
MOSFET N GSD
BSS138LT1G
1
32
+
C323 4.7uF, Tant
0805_1
+
C323 4.7uF, Tant
0805_1
C359
0.47uF
C359
0.47uF
Q13
MOSFET N GSD
BSS138LT1G
Q13
MOSFET N GSD
BSS138LT1G
1
32
J6
BNC C-SX-069
J6
BNC C-SX-069
+
C322 4.7uF, Tant
0805_1
+
C322 4.7uF, Tant
0805_1
L2 6.2nHL2 6.2nH
R343
150
R343
150
U24
LMH0303
U24
LMH0303
DDI
1
DDI
2
VEE
3
RSET
4
RSTI
5
ENABLE
6
SDA
7
SCL
8
VCC 9
SD/HD 10
SDO 11
SDO 12
FAULT 13
NC2 14
NC1 15
RSTO 16
Center PAD
17
C303
0.01uF
C303
0.01uF
J5
BNC C-SX-069
J5
BNC C-SX-069
+
C307
4.7uF, Tant
0805_1
+
C307
4.7uF, Tant
0805_1
C348
1uF, X5R, 6.3V
C348
1uF, X5R, 6.3V
R186 OPENR186 OPEN
R181
150
R181
150
R166 75
R166 75
R152
4.7K
R152
4.7K
Q30
MOSFET N GSD
BSS138LT1G
Q30
MOSFET N GSD
BSS138LT1G
1
32
C319 0.25pF
C319 0.25pF
J1
BNC C-SX-069
J1
BNC C-SX-069
R175
4.7K
R175
4.7K
+
C12
22uF, Tant
0805
+
C12
22uF, Tant
0805
R174 75
R174 75
R169 OPENR169 OPEN
D9
LED-SMT1206_ORANGE
D9
LED-SMT1206_ORANGE
+
C291
4.7uF, Tant
0805_1
+
C291
4.7uF, Tant
0805_1
R344
150
R344
150
C295
1uF, X5R, 6.3V
C295
1uF, X5R, 6.3V
+
C333
4.7uF, Tant
0805_1
+
C333
4.7uF, Tant
0805_1
R148
4.7K
R148
4.7K
L3 6.2nHL3 6.2nH
C342
0.01uF
C342
0.01uF
R182
4.7K
R182
4.7K
L1 6.2nHL1 6.2nH
VR3
10K
Copal ST32ETB103
VR3
10K
Copal ST32ETB103
1 3
2
R151
75
R151
75
C315
0.01uF
C315
0.01uF
C343
0.01uF
C343
0.01uF
R173 49.9, 1%
R173 49.9, 1%
C290 0.25pF
C290 0.25pF
R159
75
R159
75
+
C1
22uF, Tant
0805
+
C1
22uF, Tant
0805
+
C320
4.7uF, Tant
0805_1
+
C320
4.7uF, Tant
0805_1
R158
750, 1%
R158
750, 1%
C294
1uF, X5R, 6.3V
C294
1uF, X5R, 6.3V
U25
GS2974B
U25
GS2974B
VEE_A_1
1
SDI
2
SDI
3
VEE_A_4
4
AGC
5
AGC
6
BYPASS
7
MCLADJ
8
VEE_D_9 9
SDO 10
SDO 11
VEE_D_12 12
VCC_D 13
MUTE 14
CD 15
VCC_A 16
Center PAD
17
R183
75
R183
75
R147 75
R147 75
VR2
10K
Copal ST32ETB103
VR2
10K
Copal ST32ETB103
1 3
2
+
C334
4.7uF, Tant
0805_1
+
C334
4.7uF, Tant
0805_1
J2
BNC C-SX-069
J2
BNC C-SX-069
+
C310
4.7uF, Tant
0805_1
+
C310
4.7uF, Tant
0805_1
C314
0.01uF
C314
0.01uF
+
C345 4.7uF, Tant
0805_1
+
C345 4.7uF, Tant
0805_1
R163
4.7K
R163
4.7K
L4 6.2nHL4 6.2nH
R150
37.4, 1%
R150
37.4, 1%
C313
0.01uF
C313
0.01uF
R164 75
R164 75
R170
4.7K
R170
4.7K
+
C357 4.7uF, Tant
0805_1
+
C357 4.7uF, Tant
0805_1
R177
750, 1%
R177
750, 1%
R156
4.7K
R156
4.7K
C312
0.01uF
C312
0.01uF
+
C65
22uF, Tant
0805
+
C65
22uF, Tant
0805
R184 75
R184 75
C355
1uF, X5R, 6.3V
C355
1uF, X5R, 6.3V
R179 49.9, 1%
R179 49.9, 1%
R167 49.9, 1%
R167 49.9, 1%
Q12
MOSFET N GSD
BSS138LT1G
Q12
MOSFET N GSD
BSS138LT1G
1
32
C332
0.01uF
C332
0.01uF
C356 0.25pF
C356 0.25pF
R185
37.4, 1%
R185
37.4, 1%
C302
0.01uF
C302
0.01uF
R153
75
R153
75
C301 0.25pF
C301 0.25pF
C305
0.47uF
C305
0.47uF
R161
4.7K
R161
4.7K
R180 49.9, 1%
R180 49.9, 1%
R168 75
R168 75
D8
LED-SMT1206_ORANGE
D8
LED-SMT1206_ORANGE
+
C317
4.7uF, Tant
0805_1
+
C317
4.7uF, Tant
0805_1
39
LatticeECP3 Video Protocol Board – Revision C
User’s Guide
Figure 23. SDI Reference Clock Control
5
5
4
4
3
3
2
2
1
1
DD
C C
B B
A A
ECP3_XO_SIG2
ECP3_XO_SIG3
ECP3_XO_SIG4
ECP3_XO_SIG5
ECP3_XO_SIG6
ECP3_XO_SIG7
ECP3_XO_SIG8
ECP3_XO_SIG9
ECP3_XO_SIG10
ECP3_XO_SIG1
ECP3_XO_SIG0
XO_SCL
XO_SDA
OSC_IN3
OSC_IN4
TDI_ XO
TDO_ XO
TCK_ XO
ECP3_XO_SIG11
RX_GS4915_CTRL7
RX_GS4915_CTRL2
RX_GS4915_CTRL3
RX_GS4915_CTRL4
RX_GS4915_CTRL5
RX_GS4915_CTRL0
RX_GS4915_CTRL6
RX_GS4915_CTRL1
TX_GS4915_CTRL0
TX_GS4915_CTRL5
TX_GS4915_CTRL4
TX_GS4915_CTRL3
TX_GS4915_CTRL6
TX_GS4915_CTRL2
TX_GS4915_CTRL1
TX_GS4915_CTRL7
TX_GS4911_OUT2
TX_GS4911_OUT3
TX_GS4911_OUT4
TX_GS4911_OUT1
ASR_SEL2
ASR_SEL0
ASR_SEL1
RX_GS4911_OUT2
RX_GS4911_OUT3
RX_GS4911_OUT1
RX_GS4911_CTRL2
RX_GS4911_CTRL3
RX_GS4911_CTRL4
RX_GS4911_CTRL5
RX_GS4911_CTRL7
RX_GS4911_CTRL6
RX_GS4911_CTRL1
TX_GS4911_CTRL2
TX_GS4911_CTRL3
TX_GS4911_CTRL4
TX_GS4911_CTRL5
TX_GS4911_CTRL6
TX_GS4911_CTRL7
TX_GS4911_CTRL1
TMS_ XO
3_3V
3_3V
3_3V
3_3V
3_3V
3_3V
TMS_XO[6]
TCK_XO[6]
TDO_ XO[6]
TDI_ XO[6]
I2C_SCL [4,9,13]
I2C_SDA [4,9,13]
OSC_IN[1..4] [10,11]
ECP3_XO_SIG[0..11] [10]
RX_GSPI_CSn[15]
GSPI_CLK[15,16]
GSPI_DI[16]
GSPI_DO[15]
GSPI_HST_JTAG[15,16]
RX_GS4915_CTRL[0:7][15]
TX_LOCK_GS4915 [16]
RX_LOCK_GS4915 [15]
SDI_DRV_RSTI[13]
MUTE_CH0[13]
BYPASS_CH0[13]
CD_CH0[13]
BYPASS_CH1[13]
CD_CH1[13]
MUTE_CH1[13]
DISABLE_CH0[13]
TX_GS4915_CTRL[0:7] [16]
SD_HD_CH0[13]
TX_GS4911_OUT[1:4] [16]
ASR_SEL[0..2][15]
RX_GS4911_OUT[1:3][15]
RX_GS4911_CTRL[1:7][15]
TX_LOCK_LOST [16]
TX_REF_LOST [16]
TX_GS4911_CTRL[1:7] [16]
DISABLE_CH1 [13]
SD_HD_CH1 [13]
SDI_DRV_FAULT[13]
TX_GSPI_CSn[16]
Title
Size Project Rev
Date: Sheet of
Lattice Semiconductor Corporation
5555 N.E. Moore Court
Hillsboro, Oregon. 97124
ECP3 Video Protocol Board Schematic
C
SDI Reference Clock Control
C
14 16Friday, March 19, 2010
Title
Size Project Rev
Date: Sheet of
Lattice Semiconductor Corporation
5555 N.E. Moore Court
Hillsboro, Oregon. 97124
ECP3 Video Protocol Board Schematic
C
SDI Reference Clock Control
C
14 16Friday, March 19, 2010
Title
Size Project Rev
Date: Sheet of
Lattice Semiconductor Corporation
5555 N.E. Moore Court
Hillsboro, Oregon. 97124
ECP3 Video Protocol Board Schematic
C
SDI Reference Clock Control
C
14 16Friday, March 19, 2010
NOTE:
1. All GPIOs' connection order can
be changed for PCB layout.
2. All Clock input pins can be
exchaged with each other for PCB
layout.
POWER FILTER
RN1 1K EXB28V102JVRN1 1K EXB28V102JV
1
2
3
4
8
7
6
5
R20 0RR20 0R
C22
0.1uF
C22
0.1uF
C50
0.1uF
C50
0.1uF
M12 is NC for E devices
(2 of 2)
XO
U1-2
LCMXO256C-4MN100C
M12 is NC for E devices
(2 of 2)
XO
U1-2
LCMXO256C-4MN100C
VCC_P7
P7
SLEEPN
M12
VCCAUX
B7
VCC_B6
B6
GND_N9 N9
GND_B9 B9
+
C57
22uF, Tant
0805
+
C57
22uF, Tant
0805
(1 of 2)
XO
U1-1
LCMXO256C-4MN100C
(1 of 2)
XO
U1-1
LCMXO256C-4MN100C
PL2A
B1
PL2B
C1
PL3A
D2
PL3B
D1
PL3C
C2
PL3D
E1
PL4A
E2
PL4B
F1
PL5A
F2
PL5B
G2
GNDIO1_H1
H1
PL5C
H2
PL5D (GSRN)
J1
PL6A
J2
PL6B (TSALL)
K1
PL7A
K2
PL7B
L1
PL7C
L2
PL7D
M1
PL8A
M2
PL8B
N1
PL9A
M3
GNDIO1_N2
N2
TMS
P2
PL9B
P3
TCK
N4
PB2A
P4
PB2B
N3
TDO
P5
PB2C
N5
TDI
P6
PB2D
N6
PB3A (PCLK1_1)
N7
PB3B
P8
PB3C (PCLK1_0)
N8
PB3D
P9
GNDIO1_N10
N10
PB4A
P11
PB4B
N11
PB4C
P12
PB4D
N12
PB5A
P13
PB5C
P14
PB5D
N13
VCCIO1_P10
P10
VCCIO1_G1
G1
VCCIO1_P1
P1
PR9B N14
PR9A M14
PR8B L13
PR8A L14
PR7D M13
PR7C K14
PR7B K13
PR7A J14
PR6B J13
PR6A H13
GNDIO0_G14 G14
PR5D G13
PR5C F14
PR5B F13
PR5A E14
PR4B E13
PR4A D14
PR3D D13
PR3C C14
PR3B C13
PR3A B14
PR2B C12
GNDIO0_B13 B13
PR2A A13
PT5C A12
PT5B B11
PT5A A11
PT4F B12
PT4E A10
PT4D B10
PT4C A9
PT4B (PCLK0_1) A8
PT4A (PCLK0_0) B8
PT3D A7
PT3C A6
PT3B A5
GNDIO0_A4 A4
PT3A B4
PT2F A3
PT2E B3
PT2D A2
PT2C C3
PT2B A1
PT2A B2
VCCIO0_B5 B5
VCCIO0_A14 A14
VCCIO0_H14 H14
R15
1K
R15
1K
C39
0.1uF
C39
0.1uF
C47
0.1uF
C47
0.1uF
R21 0RR21 0R
C23
0.1uF
C23
0.1uF
C38
0.1uF
C38
0.1uF
C30
0.1uF
C30
0.1uF
40
LatticeECP3 Video Protocol Board – Revision C
User’s Guide
Figure 24. SDI Rx Reference Clock
5
5
4
4
3
3
2
2
1
1
DD
C C
B B
A A
1V8_PLL
RX_GS4915_CTRL6
3V3_D_2
GND_A_2
RX_DOUBLE
RX_TIMING_OUT1
1V8_A_2
RX_VID_STD0RX_GS4911_CTRL7
RX_VID_STD2RX_GS4911_CTRL5
RX_VID_STD3RX_GS4911_CTRL4
RX_IPSEL
RX_VID_STD1RX_GS4911_CTRL6
GND_A_2
1V8_A_2
IO_VDD
1V8_PLL
XTAL_VDD
RX_CLKOUT_SE
1V8_D_2
4911_CORE_VDD
RX_SKEW_EN
RX_GS4911_CTRL3 RX_VID_STD4
IO_VDD
RX_GS4915_CTRL7
RX_BYPASS
PLL_GND
GND_D_2
XTAL_GND
RX_GS4911_CTRL1 RX_GENLOCKn
RX_TIMING_OUT8
1V8_APLL
RX_GS4915_CTRL2
RX_TIMING_OUT8
RX_TIMING_OUT2
RX_TIMING_OUT3
RX_TIMING_OUT4
RX_TIMING_OUT5
RX_TIMING_OUT6
RX_TIMING_OUT7
RX_TIMING_OUT1
GND_A_2
VCO_GND_2
APLL_GND
GND_A_2
RX_GS4911_CTRL2 RX_VID_STD5
RX_TIMING_OUT7
RX_GS4915_CTRL1
RX_AUTOBYPASS
VCO_GND_2
RX_GS4911_RESETn
GND_A_2
IO_VDD
RX_TIMING_OUT6
RX_GS4915_CTRL3
RX_GENLOCKn
1V8_APLL
RX_GS4915_RESETn
IO_VDD
GND_A_2
RX_TIMING_OUT5
RX_FCTRL0
4911_CORE_VDD PLL_GND
RX_GS4915_CTRL4
1V8_D_2
GND_A_2
RX_TIMING_OUT4
RX_LOCK_GS4915
1V8_A_2
VCO_VDD_2
RX_TIMING_OUT3
RX_FCTRL1
1V8_A_2
1V8_PCLK
PCLK_GND
PCLK_GND
RX_GS4915_CTRL5
RX_TIMING_OUT2
RX_GS4915_CTRL0RX_GS4915_RESETn
1V8_PCLK
RX_TIMING_OUT[1..8]
RX_GS4911_OUT1
RX_GS4911_OUT2
RX_GS4911_OUT3
RX_LOCK_LOST
RX_REF_LOST
ACLK1
ACLK2
ACLK3
ASR_SEL2
ASR_SEL1
ASR_SEL0
RX_PCLK3_P
RX_PCLK3_N
IO_VDD
VCO_VDD_2
3_3V_FLTRD_2
IO_VDD
PLL_GND
VCO_VDD_2
XTAL_VDD
1V8_A_2
XTAL_GND
1V8_D_2
XTAL_GND
1V8_PCLK
PCLK_GND
VCO_VDD_2
4911_CORE_VDD
VCO_VDD_2
1V8_APLL
APLL_GND
1V8_PLL
3_3V
3_3V
3_3V
3_3V
3_3V
2_5V
1_8V_FLTRD
GND_D_2GND_A_2
1_8V_FLTRD
GND_A_2
GND_D_2
GND_D_2
GND_A_2 GND_D_2
3_3V
3V3_D_2
3_3V_FLTRD_2
RX_GS4911_CTRL[1:7][14]
RX_GS4915_CTRL[0:7] [14]
RX_GSPI_CSn [14]
GSPI_DO [14]
GSPI_DO_TX [16]
GSPI_CLK [14,16]
GSPI_HST_JTAG [14,16]
RX_GC4915_CLKOUTP [10]
RX_GC4915_CLKOUTN [10]
RX_SE_REFCLK [9]
RX_HSYNC[9]
RX_VSYNC[9]
RX_FSYNC[9]
RX_GS4911_OUT[1:3][14]
RX_CLKIN_SE[10]
RX_LOCK_GS4915 [14]
RX_GS4911_PCLK1 [10]
RX_GS4911_RESETn [9]
ACLK[1..3] [8,10]
ASR_SEL[0..2] [14]
Title
Size Project Rev
Date: Sheet of
Lattice Semiconductor Corporation
5555 N.E. Moore Court
Hillsboro, Oregon. 97124
ECP3 Video Protocol Board Schematic
C
SDI Rx Reference Clock
C
15 16Wednesday, November 04, 2009
Title
Size Project Rev
Date: Sheet of
Lattice Semiconductor Corporation
5555 N.E. Moore Court
Hillsboro, Oregon. 97124
ECP3 Video Protocol Board Schematic
C
SDI Rx Reference Clock
C
15 16Wednesday, November 04, 2009
Title
Size Project Rev
Date: Sheet of
Lattice Semiconductor Corporation
5555 N.E. Moore Court
Hillsboro, Oregon. 97124
ECP3 Video Protocol Board Schematic
C
SDI Rx Reference Clock
C
15 16Wednesday, November 04, 2009
Place @ P3 & P54 of
GS4911 device
Place on P3, P7, P27, P32
of GS4915 device
Place on P15, P25
of GS4915 device
Place @ P26 & P44 of
GS4911 device
RX REF
LOST
RX LOCK
LOST
RX LOCK
Locate close to GS4911
Locate close to U1
Place on P38 of
GS4915 device
Place @ P10 & P14 of
GS4911 device
Place @ P45 & P53 of
GS4911 device
RX GS4915
STATUS LED
100-ohm Diffential
matched pair
Place @ P18, 31, 38, 50, 62
of GS4911 device
Place on P5 of
GS4911 device
Default VID_STD[5:0] to 21d = 010101b
Place close
to GS4915
RX GS4911
STATUS LEDs
Place on P1
of GS4915 device
Place on P23
of GS4915 device
+
C352
33uF, Tant
0805
+
C352
33uF, Tant
0805
R28 22R28 22
FB23
BLM21AG601SN1D
FB23
BLM21AG601SN1D
Q6
MOSFET N GSD
BSS138LT1G
Q6
MOSFET N GSD
BSS138LT1G
1
32
FB16
BLM21AG601SN1D
FB16
BLM21AG601SN1D
FB21
BLM21AG601SN1D
FB21
BLM21AG601SN1D
RN2 1K EXB28V102JVRN2 1K EXB28V102JV
1
2
3
4
8
7
6
5
C69
0.01uF
C69
0.01uF
RN6 33 EXB28V330JVRN6 33 EXB28V330JV
1
2
3
4
8
7
6
5
R39 10KR39 10K
R7 10KR7 10K
RN11 1K EXB28V102JVRN11 1K EXB28V102JV
1
2
3
4
8
7
6
5
C59
0.01uF
C59
0.01uF
C42
0.01uF
C42
0.01uF
R4
150
R4
150
C43
0.01uF
C43
0.01uF
FB28
BLM21AG601SN1D
FB28
BLM21AG601SN1D
FB22
BLM21AG601SN1D
FB22
BLM21AG601SN1D
U2
GS4911B
U2
GS4911B
VID_PLL_GND
4VID_PLL_VDD
3
XTAL_VDD
5
X1
6
X2
7
XTAL_GND
8
CORE_GND
9
PHS_GND 55
PHS_VDD 54
ANALOG_VDD
10
NC1
11
ANALOG_GND
12
AUD_PLL_GND
13
AUD_PLL_VDD
14
10FID
15
HSYNC
16
VSYNC
17
IO_VDD_18
18
FSYNC
19
NC2
20
VID_STD0
21
VID_STD1
22
VID_STD2
23
VID_STD3
24
VID_STD4
25
VID_STD5
27
ACLK1
28
ACLK2
29
ACLK3
30
IO_VDD_31
31
CORE_VDD_26
26
ASR_SEL2
32
ASR_SEL1 33
ASR_SEL0 34
TIMING_OUT1 35
TIMING_OUT2 36
IO_VDD_38 38
TIMING_OUT4 39
TIMING_OUT3 37
TIMING_OUT5 40
LVDS/PCLK3_VDD 45
PCLK3 46
LVDS/PCLK3_GND 48
PCLK3 47
PCLK2 49
PCLK1&2_GND 52
PCLK1 51
IO_VDD_50 50
TIMING_OUT6 41
TIMING_OUT7 42
TIMING_OUT8 43
PCLK1&2_VDD 53
LOCK_LOST
1
REF_LOST
2
GENLOCK 64
CORE_VDD_44 44
JTAG/HOST 56
SCLK_TCLK 57
SDIN_TDI 58
SDOUT_TDO 59
CS_TMS 60
RESET 61
IO_VDD_62 62
NC3 63
GND_PAD
65
RN4 1K EXB28V102JVRN4 1K EXB28V102JV
1
2
3
4
8
7
6
5
C17 39pFC17 39pF
C25
0.01uF
C25
0.01uF
C92
0.01uF
C92
0.01uF
C85
0.1uF
C85
0.1uF
C330
0.01uF
C330
0.01uF
Q4
MOSFET N GSD
BSS138LT1G
Q4
MOSFET N GSD
BSS138LT1G
1
32
R32
150K
R32
150K
U6
GS4915
U6
GS4915
REG_VDD (3.3)
1
AGND_2
2
PLL_VDD (1.8)
3
CLKIN+
4
CLKIN-
5
AGND_6
6
SE_IN_VDD(1.8)
7
CLKIN_SE
8
AGND_9
9
RESETb
10
IPSEL
11
GND_12
12
BYPASS
13
AUTOBYPASSb
14
D_VDD (1.8)
15
FCTR0
16
FCTR1
17
DOUBLE
18
SKEW_EN
19
GND_20
20
LOCK 21
GND_22 22
SE_LVL_VDD(1.8 or 3.3) 23
CLKOUT_SE 24
SE_OUT_VDD (1.8) 25
AGND_26 26
DIFF_OUT_VDD(1.8) 27
CLKOUT- 28
CLKOUT+ 29
AGND_30 30
AGND_31 31
DIV_VDD(1.8) 32
VCO 33
VCOb 34
VCO_GND 35
LF 36
CP_CTRL/Rset 37
CP_VDD (2.5) 38
VCO_VDD(2.5) 39
AGND_40 40
PAD
41
C72
0.1uF
C72
0.1uF
R9
1M
R9
1M
C48
0.01uF
C48
0.01uF
C36
0.01uF
C36
0.01uF
R3
150
R3
150
C31
0.01uF
C31
0.01uF
D3
LED-SMT1206_RED
D3
LED-SMT1206_RED
U5
GO1555
U5
GO1555
O/P 1
GND2 2
NC 3
GND4
4
VCTR
5
GND6
6
VCC
7
GND8 8
+
C346
100uF, Tant
EIA3528
+
C346
100uF, Tant
EIA3528
C75
0.01uF
C75
0.01uF
R8 10KR8 10K
R11
0R
R11
0R
TP1TP1
C26
0.01uF
C26
0.01uF
C84
0.01uF
C84
0.01uF
C76
0.1uF
C76
0.1uF
FB14
BLM21AG601SN1D
FB14
BLM21AG601SN1D
D5
LED-SMT1206_GREEN
D5
LED-SMT1206_GREEN
FB15
BLM21AG601SN1D
FB15
BLM21AG601SN1D
C29
0.01uF
C29
0.01uF
R18
10K
R18
10K
RN9 1K EXB28V102JVRN9 1K EXB28V102JV
1
2
3
4
8
7
6
5
Q3
MOSFET N GSD
BSS138LT1G
Q3
MOSFET N GSD
BSS138LT1G
1
32
TP9TP9
R23
22
R23
22
R45 22R45 22
C70
0.01uF
C70
0.01uF
R37
1, 1%
R37
1, 1%
C79
0.01uF
C79
0.01uF
TP7TP7
TP3TP3
R34
100
R34
100
D4
LED-SMT1206_RED
D4
LED-SMT1206_RED
C52
0.01uF
C52
0.01uF
+
C82
33uF, Tant
0805
+
C82
33uF, Tant
0805
C87
0.01uF
C87
0.01uF
+
C349
10uF, Tant
0805
+
C349
10uF, Tant
0805
C91
0.01uF
C91
0.01uF
R30 22R30 22
C53
0.01uF
C53
0.01uF
R12 22R12 22
TP5TP5
C89
0.1uF
C89
0.1uF
R43 10KR43 10K
C18 24pFC18 24pF
C60
0.01uF
C60
0.01uF
FB29
BLM21AG601SN1D
FB29
BLM21AG601SN1D
R19
22
R19
22
FB20
BLM21AG601SN1D
FB20
BLM21AG601SN1D
FB17
BLM21AG601SN1D
FB17
BLM21AG601SN1D
R42
150
R42
150
Y2
XTAL
CS10-27.000MABJ-UT
Citizen
Y2
XTAL
CS10-27.000MABJ-UT
Citizen
+
C358
33uF, Tant
0805
+
C358
33uF, Tant
0805
+
C351
33uF, Tant
0805
+
C351
33uF, Tant
0805
R31
150K
R31
150K
R29 22R29 22
C338
0.01uF
C338
0.01uF
C90
0.01uF
C90
0.01uF
41
LatticeECP3 Video Protocol Board – Revision C
User’s Guide
Figure 25. SDI Tx Reference Clock
5
5
4
4
3
3
2
2
1
1
DD
C C
B B
A A
TX_VID_S TD2TX_GS4911_CTRL5
GND_A
IO_VDD
TX_TIMING_OUT6
TX_GS4915_CTRL3
TX_GENLOCKn
1V8_APLL
TX_GS4915_RESETn
TX_GS4911_CTRL7 TX_VID_STD0
IO_VDD
3_3V_FLTRD
GND_A
TX_TIMING_OUT5
TX_FCTRL0
4911_CORE_VDD PLL_GND
IO_VDD
TX_GS4915_CTRL4
1V8_D
GND_A
TX_TIMING_OUT4
1V8_A
VCO_VDD
TX_TIMING_OUT3
TX_FCTRL1
1V8_PLL
1V8_A
1V8_PCLK
PCLK_GND
PCLK_GND
TX_GS4915_CTRL5
TX_TIMING_OUT2
1V8_PCLK
1V8_PLL
TX_GS4915_CTRL6
3V3_D
GND_A
TX_DOUBLE
TX_TIMING_OUT1
1V8_A
TX_VID_S TD3TX_GS4911_CTRL4
TX_IPSEL
TX_VID_S TD1TX_GS4911_CTRL6
GND_A
1V8_A
IO_VDD
1V8_PLL
XTAL_VDD
TX_CLKOUT_SE
1V8_D
4911_CORE_VDD
TX_SKEW_EN
TX_GS4911_CTRL3 TX_VID_STD4
IO_VDD
TX_GS4915_CTRL7
TX_BYPASS
PLL_GND
GND_D
XTAL_GND
TX_GS4911_CTRL1 TX_GENLOCKn
TX_PCLK3_N
TX_TIMING_OUT8
IO_VDD
1V8_APLL
TX_GS4915_CTRL2
TX_TIMING_OUT8
TX_TIMING_OUT2
TX_TIMING_OUT3
TX_TIMING_OUT4
TX_TIMING_OUT5
TX_TIMING_OUT6
TX_TIMING_OUT7
TX_TIMING_OUT1
GND_A
VCO_GND
APLL_GND
GND_A
TX_GS4911_CTRL2 TX_VID_STD5
TX_TIMING_OUT7
TX_GS4915_CTRL1
TX_AUTOBYPASS
VCO_GND
VCO_VDD
TX_GS4911_RESETn
TX_TIMING_OUT[1..8]
TX_GS4911_OUT1
TX_GS4911_OUT2
TX_GS4911_OUT3
TX_GS4911_OUT4
TX_LOCK_LOST
TX_REF_LOST TX_PCLK3_P
1V8_APLL
TX_GS4915_CTRL0TX_GS4915_RESETn
GND_D
TX_LOCK_GS4915
1V8_PCLK
PCLK_GND
1_8V
VCO_VDD
3_3V
4911_CORE_VDD
3V3_D
VCO_VDD
1V8_APLL
1_8V
APLL_GND
1_8V_FLTRD
1_8V
1V8_PLL
2_5V
3_3V_SDI_CLK
IO_VDD
PLL_GND
1_8V 3_3V_SDI_CLK
VCO_VDD
XTAL_VDD
3_3V_FLTRD
XTAL_GND
XTAL_GND
1_8V
1V8_D
3_3V
3_3V
3_3V
3_3V
3_3V
GND_A GND_D
1V8_A
1_8V_FLTRD
GND_DGND_A
GND_D
GND_D
GND_A
XTAL_VDD
XTAL_GND XTAL_GND
TX_SE_REFCLK [9]
TX_GSPI_CSn [1 4]
GSPI_DO_TX [15]
GSPI_DI [14]
GSPI_CLK [14,15]
GSPI_HST_JTAG [14,15]
TX_GS4911_CTRL[1:7][14]
TX_HSYNC[9]
TX_GS4915_CTRL[0:7] [14]
TX_GC4915_CLKOUTP [7]
TX_GC4915_CLKOUTN [7]
TX_VSYNC[9]
TX_FSYNC[9]
TX_GS4911_OUT[1:4][14]
TX_CLKIN_SE[10]
TX_GS4911_RESETn [9]
TX_GS4911_PCLK1 [10]
TX_LOCK_GS4915 [14]
TX_LOCK_LOST [14]
TX_REF_LOST [14]
Title
Size Project Rev
Date: Sheet of
Lattice Semiconductor Corporation
5555 N.E. Moore Court
Hillsboro, Oregon. 97124
ECP3 Video Protocol Board Schematic
C
SDI Tx Reference Clock
C
16 16Wednesday, November 04, 2009
Title
Size Project Rev
Date: Sheet of
Lattice Semiconductor Corporation
5555 N.E. Moore Court
Hillsboro, Oregon. 97124
ECP3 Video Protocol Board Schematic
C
SDI Tx Reference Clock
C
16 16Wednesday, November 04, 2009
Title
Size Project Rev
Date: Sheet of
Lattice Semiconductor Corporation
5555 N.E. Moore Court
Hillsboro, Oregon. 97124
ECP3 Video Protocol Board Schematic
C
SDI Tx Reference Clock
C
16 16Wednesday, November 04, 2009
Locate close to U1
Place on P23
of GS4915 device
Place on P38 of
GS4915 device
Place @ P10 & P14
of GS4911 device
Place @ P45 & P53
of GS4911 device
100-ohm Diffential
matched pair
Place @ P18, 31, 38, 50, 62
of GS4911 device
Place on P5 of
GS4911 device
Place @ P3 & P54 of
GS4911 device
Place on P3, P7, P27, P32
of GS4915 device
Place on P15, P25
of GS4915 device
Place @ P26 & P44
of GS4911 device
Locate close to GS4911
Place close
to GS4915
Default VID_STD[5:0] to 21d = 010101b
TX LOCK
TX GS4915
STATUS LED
TX GS4911
STATUS LEDs
TX REF
LOST
TX LOCK
LOST
Place on P1
of GS4915 device
+
C350
10uF, Tant
0805
+
C350
10uF, Tant
0805
C46
0.01uF
C46
0.01uF
U8
GO1555
U8
GO1555
O/P 1
GND2 2
NC 3
GND4
4
VCTR
5
GND6
6
VCC
7
GND8 8
U7
GS4915
U7
GS4915
REG_VDD (3.3)
1
AGND_2
2
PLL_VDD (1.8)
3
CLKIN+
4
CLKIN-
5
AGND_6
6
SE_IN_VDD(1.8)
7
CLKIN_SE
8
AGND_9
9
RESETb
10
IPSEL
11
GND_12
12
BYPASS
13
AUTOBYPASSb
14
D_VDD (1.8)
15
FCTR0
16
FCTR1
17
DOUBLE
18
SKEW_EN
19
GND_20
20
LOCK 21
GND_22 22
SE_LVL_VDD(1.8 or 3.3) 23
CLKOUT_SE 24
SE_OUT_VDD (1.8) 25
AGND_26 26
DIFF_OUT_VDD(1.8) 27
CLKOUT- 28
CLKOUT+ 29
AGND_30 30
AGND_31 31
DIV_VDD(1.8) 32
VCO 33
VCOb 34
VCO_GND 35
LF 36
CP_CTRL/Rset 37
CP_VDD (2.5) 38
VCO_VDD(2.5) 39
AGND_40 40
PAD
41
+
C81
33uF, Tant
0805
+
C81
33uF, Tant
0805
C304
0.1uF
C304
0.1uF
C95
0.01uF
C95
0.01uF
+
C335
10uF, Tant
0805
+
C335
10uF, Tant
0805
C93
0.1uF
C93
0.1uF
RN10 1K EXB28V102JVRN10 1K EXB28V102JV
1
2
3
4
8
7
6
5
C68
0.01uF
C68
0.01uF
Q5
MOSFET N GSD
BSS138LT1G
Q5
MOSFET N GSD
BSS138LT1G
1
32
FB11
BLM21AG601SN1D
FB11
BLM21AG601SN1D
C77
0.1uF
C77
0.1uF
R348
OPEN
R348
OPEN
R2
150
R2
150
U3
GS4911B
U3
GS4911B
VID_PLL_GND
4VID_PLL_VDD
3
XTAL_VDD
5
X1
6
X2
7
XTAL_GND
8
CORE_GND
9
PHS_GND 55
PHS_VDD 54
ANALOG_VDD
10
NC1
11
ANALOG_GND
12
AUD_PLL_GND
13
AUD_PLL_VDD
14
10FID
15
HSYNC
16
VSYNC
17
IO_VDD_18
18
FSYNC
19
NC2
20
VID_STD0
21
VID_STD1
22
VID_STD2
23
VID_STD3
24
VID_STD4
25
VID_STD5
27
ACLK1
28
ACLK2
29
ACLK3
30
IO_VDD_31
31
CORE_VDD_26
26
ASR_SEL2
32
ASR_SEL1 33
ASR_SEL0 34
TIMING_OUT1 35
TIMING_OUT2 36
IO_VDD_38 38
TIMING_OUT4 39
TIMING_OUT3 37
TIMING_OUT5 40
LVDS/PCLK3_VDD 45
PCLK3 46
LVDS/PCLK3_GND 48
PCLK3 47
PCLK2 49
PCLK1&2_GND 52
PCLK1 51
IO_VDD_50 50
TIMING_OUT6 41
TIMING_OUT7 42
TIMING_OUT8 43
PCLK1&2_VDD 53
LOCK_LOST
1
REF_LOST
2
GENLOCK 64
CORE_VDD_44 44
JTAG/HOST 56
SCLK_TCLK 57
SDIN_TDI 58
SDOUT_TDO 59
CS_TMS 60
RESET 61
IO_VDD_62 62
NC3 63
GND_PAD
65
+
C353
33uF, Tant
0805
+
C353
33uF, Tant
0805
C54
0.01uF
C54
0.01uF
C80
0.01uF
C80
0.01uF
TP8TP8
C20
0.1uF
C20
0.1uF
C67
0.1uF
C67
0.1uF
C423
0.01uF
C423
0.01uF
12
+
C339
10uF, Tant
0805
+
C339
10uF, Tant
0805
C32
0.1uF
C32
0.1uF
C37
0.01uF
C37
0.01uF FB19
BLM21AG601SN1D
FB19
BLM21AG601SN1D
R38
1, 1%
R38
1, 1%
D1
LED-SMT1206_RED
D1
LED-SMT1206_RED
D6
LED-SMT1206_GREEN
D6
LED-SMT1206_GREEN
R26 22R26 22
C71
0.01uF
C71
0.01uF
R1
150
R1
150
+
C336
33uF, Tant
0805
+
C336
33uF, Tant
0805
C74
0.1uF
C74
0.1uF
+
C325
33uF, Tant
0805
+
C325
33uF, Tant
0805
R44 10KR44 10K
RN7 33 EXB28V330JVRN7 33 EXB28V330JV
1
2
3
4
8
7
6
5
R40 10KR40 10K
FB18
BLM21AG601SN1D
FB18
BLM21AG601SN1D
D2
LED-SMT1206_RED
D2
LED-SMT1206_RED
C340
0.01uF
C340
0.01uF
C21
0.1uF
C21
0.1uF C19
0.1uF
C19
0.1uF
C96
0.01uF
C96
0.01uF
+
C341
33uF, Tant
0805
+
C341
33uF, Tant
0805
FB12
BLM21AG601SN1D
FB12
BLM21AG601SN1D
C15 24pFC15 24pF
C63
0.01uF
C63
0.01uF
R24
22
R24
22
FB30
BLM21AG601SN1D
FB30
BLM21AG601SN1D
FB13
BLM21AG601SN1D
FB13
BLM21AG601SN1D
C86
0.1uF
C86
0.1uF
R46 22R46 22
C78
0.1uF
C78
0.1uF
C45
0.01uF
C45
0.01uF
FB8
BLM21AG601SN1D
FB8
BLM21AG601SN1D
RN5 1K EXB28V102JVRN5 1K EXB28V102JV
1
2
3
4
8
7
6
5
R13 22R13 22
TP4TP4
FB26
BLM21AG601SN1D
FB26
BLM21AG601SN1D
FB7
BLM21AG601SN1D
FB7
BLM21AG601SN1D
R22
22
R22
22
C83
0.01uF
C83
0.01uF
R10
1M
R10
1M
RN3 1K EXB28V102JVRN3 1K EXB28V102JV
1
2
3
4
8
7
6
5
FB1
BLM21AG601SN1D
FB1
BLM21AG601SN1D
C35
0.1uF
C35
0.1uF
R14
0R
R14
0R
+
C329
10uF, Tant
0805
+
C329
10uF, Tant
0805
R36
100
R36
100
R347 OPENR347 OPEN
C94
0.01uF
C94
0.01uF
Y6
OSC
OSC 27 MHz 3.3V SMD 25ppm
Y6
OSC
OSC 27 MHz 3.3V SMD 25ppm
N/C
1
GND
2OUT 3
Vcc 4
C40
0.1uF
C40
0.1uF
+
C361
33uF, Tant
0805
+
C361
33uF, Tant
0805
+
C318
10uF, Tant
0805
+
C318
10uF, Tant
0805
+
C344
10uF, Tant
0805
+
C344
10uF, Tant
0805
C24
0.01uF
C24
0.01uF
FB10
BLM21AG601SN1D
FB10
BLM21AG601SN1D
R6 10KR6 10K
C27
0.01uF
C27
0.01uF
Q2
MOSFET N GSD
BSS138LT1G
Q2
MOSFET N GSD
BSS138LT1G
1
32
+
C326
33uF, Tant
0805
+
C326
33uF, Tant
0805
C16 39pFC16 39pF
C88
0.01uF
C88
0.01uF
+
C327
10uF, Tant
0805
+
C327
10uF, Tant
0805
C62
0.1uF
C62
0.1uF
R25 22R25 22
R5 10KR5 10K
FB3
BLM21AG601SN1D
FB3
BLM21AG601SN1D
Q1
MOSFET N GSD
BSS138LT1G
Q1
MOSFET N GSD
BSS138LT1G
1
32
+
C311
33uF, Tant
0805
+
C311
33uF, Tant
0805
+
C337
33uF, Tant
0805
+
C337
33uF, Tant
0805
R41
150
R41
150
C58
0.1uF
C58
0.1uF
TP2TP2
FB2
BLM21AG601SN1D
FB2
BLM21AG601SN1D
C28
0.01uF
C28
0.01uF
+
C347
100uF, Tant
EIA3528
+
C347
100uF, Tant
EIA3528
R35
150K
R35
150K
C51
0.1uF
C51
0.1uF
C73
0.01uF
C73
0.01uF
C44
0.1uF
C44
0.1uF
+
C66
100uF, Tant
EIA3528
+
C66
100uF, Tant
EIA3528
TP6TP6
C55
0.01uF
C55
0.01uF
C33
0.01uF
C33
0.01uF
+
C354
33uF, Tant
0805
+
C354
33uF, Tant
0805
FB5
BLM21AG601SN1D
FB5
BLM21AG601SN1D
FB4
BLM21AG601SN1D
FB4
BLM21AG601SN1D
FB9
BLM41PG600SN1L
FB9
BLM41PG600SN1L
FB25
BLM21AG601SN1D
FB25
BLM21AG601SN1D
C49
0.01uF
C49
0.01uF
R33
150K
R33
150K
FB6
BLM21AG601SN1D
FB6
BLM21AG601SN1D
FB31
BLM21AG601SN1D
FB31
BLM21AG601SN1D
C331
0.01uF
C331
0.01uF
C61
0.01uF
C61
0.01uF
RN8 1K EXB28V102JVRN8 1K EXB28V102JV
1
2
3
4
8
7
6
5
Y1
XTAL
CS10-27.000MABJ-UT
Citizen
Y1
XTAL
CS10-27.000MABJ-UT
Citizen
FB24
BLM21AG601SN1D
FB24
BLM21AG601SN1D
FB27
BLM21AG601SN1D
FB27
BLM21AG601SN1D
R27 22R27 22
