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TSL210
640 × 1 LINEAR SENSOR ARRAY
TAOS039D − AUGUST 2011
1
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Copyright E 2011, TAOS Inc.
www.taosinc.com
D640 × 1 Sensor-Element Organization
D200 Dots-Per-Inch (DPI) Sensor Pitch
DHigh Linearity and Uniformity
DWide Dynamic Range . . . 2000:1 (66 dB)
DOutput Referenced to Ground
DLow Image Lag . . . 0.5% Typ
DOperation to 5 MHz
DSingle 5-V Supply
Description
The TSL210 linear sensor array consists of five
sections of 128 photodiodes, each with
associated charge amplifier circuitry, running from
a common clock. These sections can be
connected to form a contiguous 640 × 1 pixel
array. Device pixels measure 120 μm (H) by
70 μm (W) with 125-μm center-to-center pixel
spacing. Operation is simplified by internal logic
that requires only a serial input (SI1 through SI5)
for each section and a common clock for the five
sections.
The device is intended for use in a wide variety of
applications including contact imaging, mark and
code reading, bar-code reading, edge detection
and positioning, OCR, level detection, and linear
and rotational encoding.
Functional Block Diagram (each section)
SI
CLK 128-Bit Shift Register
Q128
Switch Control Logic
Pixel
2
Pixel
128
Pixel
3
Analog
Bus
Output
Amplifier
Gain
Trim
Q3Q2Q1
VDD
RL
(External
330 W
Load)
AO
SO
GND
Integrator
Reset
_
+
Pixel 1
Sample/
Output
S1
S2
2
13
1
2
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Texas Advanced Optoelectronic Solutions Inc.
1001 Klein Road S Suite 300 S Plano, TX 75074 S (972) 673-0759
PACKAGE
(TOP VIEW)
1 VDD
2 CLK
3 SI1
4 AO1
5 SO1
6 SI2
7 AO2
8 SO2
9 GND
10 SI3
11 AO3
12 SO3
13 SI4
14 AO4
15 SO4
16 SI5
17 AO5
18 SO5
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TSL210
640 × 1 LINEAR SENSOR ARRAY
TAOS039D − AUGUST 2011
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Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME NO. I/O DESCRIPTION
AO1 4 O Analog output of section 1.
AO2 7 O Analog output of section 2.
AO3 11 OAnalog output of section 3.
AO4 14 O Analog output of section 4.
AO5 17 O Analog output of section 5.
CLK 2 I Clock input for all sections. The clock controls the charge transfer, pixel output, and reset.
GND 9 Ground (substrate). All voltages are referenced to the substrate.
SI1 3 I SI1 defines the start of the data out sequence for section 1.
SI2 6 I SI2 defines the start of the data out sequence for section 2.
SI3 10 I SI3 defines the start of the data out sequence for section 3.
SI4 13 I SI4 defines the start of the data out sequence for section 4.
SI5 16 I SI5 defines the start of the data out sequence for section 5.
SO1 5 O SO1 provides the signal to drive the SI2 input in serial mode or end of data for section 1 in parallel mode.
SO2 8 O SO2 provides the signal to drive the SI3 input in serial mode or end of data for section 2 in parallel mode.
SO3 12 O SO3 provides the signal to drive the SI4 input in serial mode or end of data for section 3 in parallel mode.
SO4 15 O SO4 provides the signal to drive the SI5 input in serial mode or end of data for section 4 in parallel mode.
SO5 18 O SO5 provides the signal to drive the SI input of another device for cascading or as an end of data indication.
VDD 1 Supply voltage for both analog and digital circuits.
Detailed Description
The device consists of five sections of 128 photodiodes (called pixels — 640 total in the device) arranged in a
linear array. Each section has its own signal input and output lines, and all five sections are connected to a
common clock line. Light energy impinging on a pixel generates photocurrent that is then integrated by the active
integration circuitry associated with that pixel.
During the integration period, a sampling capacitor connects to the output of the integrator through an analog
switch. The amount of charge accumulated at each pixel is directly proportional to the light intensity on that pixel
and the integration time. The voltage output developed for each pixel is according to the following relationship:
Vout = Vdrk + (Re) (Ee) (tint)
where:
Vout is the analog output voltage for white condition
Vdrk is the analog output voltage for dark condition
Reis the device responsivity for a given wavelength of light given in V/(μJ/cm2)
Eeis the incident irradiance in μW/cm2
tint is integration time in seconds
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640 × 1 LINEAR SENSOR ARRAY
TAOS039D − AUGUST 2011
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The output and reset of the integrators in each section are controlled by a 128-bit shift register and reset logic.
An output cycle is initiated by clocking in a logic 1 on SI. As the SI pulse is clocked through the shift register,
the charge stored on the sampling capacitors of each pixel is sequentially connected to a charge-coupled output
amplifier that generates a voltage on analog output AO (given above). After being read, the pixel integrator is
then reset, and the next integration period begins for that pixel. On the 129th clock rising edge, the SO pulse
is clocked out on SO signifying the end of the read cycle. The section is then ready for another read cycle. The
SO of each section can be connected to SI on the next section in the array (Figure 4). SO can be used to signify
the read is complete.
AO is driven by a source follower that requires an external pulldown resistor (330-Ω typical). The output is
nominally 0 V for no light input, 2 V for normal white-level, and 3.4 V for saturation light level. When the device
is not in the output phase, AO is in a high impedance state.
A 0.1 μF bypass capacitor should be connected between VDD and ground as close as possible to the device.
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640 × 1 LINEAR SENSOR ARRAY
TAOS039D − AUGUST 2011
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Absolute Maximum Ratings†
Supply voltage range, VDD −0.3 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI −0.3 V to VDD + 0.3V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VDD) −20 mA to 20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VDD) −25 mA to 25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high impedance or
power-off state, VO −0.3 V to VDD + 0.3V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VDD) −25 mA to 25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VDD or GND −100 mA to 100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog output current range, IO −25 mA to 25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA −25°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −25°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature on connection pad for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ESD tolerance, human body model 2000 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “Recommended Operating Conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Recommended Operating Conditions (see Figure 1 and Figure 2)
MIN NOM MAX UNIT
Supply voltage, VDD 4.5 5 5.5 V
Input voltage, VI0 VDD V
High-level input voltage, VIH 2 VDD V
Low-level input voltage, VIL 0 0.8 V
Wavelength of light source, λ400 1000 nm
Clock frequency, fclock 5 5000 kHz
Sensor integration time, serial, tint 0.128 100 ms
Sensor integration time, parallel, tint 0.026 100 ms
Load capacitance, CL330 pF
Load resistance, RL300 4700 Ω
Operating free-air temperature, TA0 70 °C
NOTE 1: SI must go low before the rising edge of the next clock pulse.
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640 × 1 LINEAR SENSOR ARRAY
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Electrical Characteristics at fclock = 200 kHz, VDD = 5 V, TA = 25°C, λp = 640 nm, tint = 5 ms,
RL = 330 Ω, Ee = 18μW/cm2 (unless otherwise noted) (see Note 3)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOUT Analog output voltage (white, average over 640 pixels) See Note 2 1.6 2 2.4 V
VDRK Analog output voltage (dark, average over 640 pixels) Ee = 0 0 0.05 0.15 V
PRNU Pixel response nonuniformity See Note 4 ±20 %
Nonlinearity of analog output voltage See Note 5 ±0.4% FS
Output noise voltage See Note 6 1 mVrms
ReResponsivity 16 22 28
V/
(μJ/
cm2)
SE Saturation exposure See Note 7 155 nJ/cm2
VSAT Analog output saturation voltage 2.5 3.4 V
DSNU Dark signal nonuniformity All pixels, Ee = 0, See Note 8 0.04 0.12 V
IL Image lag See Note 9 0.5 %
IDD Supply current 37 50 mA
IIH High-level input current VI = VDD 10 μA
IIL Low-level input current VI = 0 10 μA
V
High level output voltage SO1 SO5
IO = 50 μA 4.5 4.95
V
VOH High-level output voltage, SO1 − SO5 IO = 4 mA 4.6 V
V
Low level output voltage SO1 SO5
IO = 50 μA 0.01 0.1
V
VOL Low-level output voltage, SO1 − SO5 IO = 4 mA 0.4 V
Ci(SI) Input capacitance, SI 20 pF
Ci(CLK) Input capacitance, CLK 50 pF
NOTES: 2. The array is uniformly illuminated with a diffused LED source having a peak wavelength of 640 nm.
3. Clock duty cycle is assumed to be 50%.
4. PRNU is the maximum difference between the voltage from any single pixel and the average output voltage from all pixels of the
device under test when the array is uniformly illuminated.
5. Nonlinearity is defined as the maximum deviation from a best-fit straight line over the dark-to-white irradiance levels, as a percent
of analog output voltage (white).
6. RMS noise is the standard deviation of a single-pixel output under constant illumination as observed over a 5-second period.
7. Minimum saturation exposure is calculated using the minimum Vsat, the maximum Vdrk, and the maximum Re.
8. DSNU is the difference between the maximum and minimum output voltage in the absence of illumination.
9. Image lag is a residual signal left in a pixel from a previous exposure. It is defined as a percent of white-level signal remaining after
a pixel is exposed to a white condition followed by a dark condition:
IL +
Vout (IL) *Vdrk
Vout (white) *Vdrk 100
Timing Requirements (see Figure 1 and Figure 2)
MIN NOM MAX UNIT
tsu(SI) Setup time, serial input (see Note 10) 20 ns
th(SI) Hold time, serial input (see Note 10 and Note 11) 0 ns
twPulse duration, clock high or low 50 ns
tr, tfInput transition (rise and fall) time 0 500 ns
NOTES: 10. Input pulses have the following characteristics: tr = 6 ns, tf = 6 ns.
11. SI must go low before the rising edge of the next clock pulse.
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TSL210
640 × 1 LINEAR SENSOR ARRAY
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Dynamic Characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Figure 2)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tsAnalog output settling time to ±1% CL = 10 pF 185 ns
TYPICAL CHARACTERISTICS
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
129 Clock Cycles
CLK
SI1
AO
Hi-Z
Hi-Z
Figure 1. Timing Waveforms (each section)
50%
AO
SI
CLK
Pixel 128
ts
0 V
0 V
5 V
2.5 V
th(SI)
5 V
tsu(SI)
tw1 2 128 129
ts
Pixel 1
Figure 2. Operational Waveforms (each section)
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TSL210
640 × 1 LINEAR SENSOR ARRAY
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TYPICAL CHARACTERISTICS
0.4
0
300 500 700 900
0.6
0.8
PHOTODIODE SPECTRAL RESPONSIVITY
0.2
λ − Wavelength − nm
Normalized Responsivity
TA = 25°C
1
1100400 600 800 1000
Figure 3
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640 × 1 LINEAR SENSOR ARRAY
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APPLICATION INFORMATION
Integration Time
The integration time of the linear array is the period during which light is sampled and charge accumulates on
each pixel’s integrating capacitor. The flexibility to adjust the integration period is a powerful and useful feature
of the TAOS TSL2xx linear array family. By changing the integration time, a desired output voltage can be
obtained on the output pin while avoiding saturation for a wide range of light levels.
Each pixel of the linear array consists of a light-sensitive photodiode. The photodiode converts light intensity
to a voltage. The voltage is sampled on the Sampling Capacitor by closing switch S2 (position 1) (see the
functional block diagram on page 1). Logic controls the resetting of the Integrating Capacitor to zero by closing
switch S1 (position 2).
At SI input (Start Integration), pixel 1 is accessed. During this event, S2 moves from position 1 (sampling) to
position 3 (holding). This holds the sampled voltage for pixel 1. Switch S1 for pixel 1 is then moved to position
2. This resets (clears) the voltage previously integrated for that pixel so that pixel 1 is now ready to start a new
integration cycle. When the next clock period starts, the S1 switch is returned to position 1 to be ready to
start integrating again. S2 is returned to position 1 to start sampling the next light integration. Then the next pixel
starts the same procedure. The integration time is the time from a specific pixel read to the next time that pixel
is read again. If either the clock speed or the time between successive SI pulses is changed, the integration time
will vary. After the final (nth) pixel in the array is read on the output, the output goes into a high-impedance mode.
A new SI pulse can occur on the (n+1) clock causing a new cycle of integration/output to begin. Note that the
time between successive SI pulses must not exceed the maximum integration time of 100 msec.
The minimum integration time for any given array is determined by time required to clock out all the pixels in
the array and the time to discharge the pixels. The time required to discharge the pixels is a constant. Therefore,
the minimum integration period is simply a function of the clock frequency and the number of pixels in the array.
A slower clock speed increases the minimum integration time and reduces the maximum light level for saturation
on the output. The minimum integration time shown in this data sheet is based on the maximum clock frequency
of 5 MHz.
The minimum integration time can be calculated from the equation:
Tint(min) +ǒ1
maximum clock frequencyǓ n
where:
nis the number of pixels
In the case of the TSL210, the minimum integration time would be:
Tint(min) +200 ns 640 +128 ms
It is important to note that not all pixels will have the same integration time if the clock frequency is varied while
data is being output.
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640 × 1 LINEAR SENSOR ARRAY
TAOS039D − AUGUST 2011
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APPLICATION INFORMATION
It is good practice on initial power up to run the clock (n+1) times after the first SI pulse to clock out indeterminate
data from power up. After that, the SI pulse is valid from the time following (n+1) clocks. The output will go into
a high-impedance state after the n+1 high clock edge. It is good practice to leave the clock in a low state when
inactive because the SI pulse required to start a new cycle is a low-to-high transition.
The integration time chosen is valid as long as it falls in the range between the minimum and maximum limits
for integration time. If the amount of light incident on the array during a given integration period produces a
saturated output (Max Voltage output), then the data is not accurate. If this occurs, the integration period should
be reduced until the analog output voltage for each pixel falls below the saturation level. The goal of reducing
the period of time the light sampling window is active is to lower the output voltage level to prevent saturation.
However, the integration time must still be greater than or equal to the minimum integration period.
If the light intensity produces an output below desired signal levels, the output voltage level can be increased
by increasing the integration period provided that the maximum integration time is not exceeded. The maximum
integration time is limited by the length of time the integrating capacitors on the pixels can hold their accumulated
charge. The maximum integration time should not exceed 100 ms for accurate measurements.
Although the linear array is capable of running over a wide range of operating frequencies up to a maximum
of 5 MHz, the speed of the A/D converter used in the application is likely to be the limiter for the maximum clock
frequency. The voltage output is available for the whole period of the clock, so the setup and hold times required
for the analog-to-digital conversion must be less than the clock period.
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640 × 1 LINEAR SENSOR ARRAY
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APPLICATION INFORMATION
Connection Diagrams
SERIAL
TSL210
1 VDD
2 CLK
3 SI1
4 AO1
5 SO1
6 SI2
7 AO2
8 SO2
9 GND
10 SI3
11 AO3
12 SO3
13 SI4
14 AO4
15 SO4
16 SI5
17 AO5
18 SO5
RL
330 Ω
PARALLEL
TSL210
1 VDD
2 CLK
3 SI1
4 AO1
5 SO1
6 SI2
7 AO2
8 SO2
9 GND
10 SI3
11 AO3
12 SO3
13 SI4
14 AO4
15 SO4
16 SI5
17 AO5
18 SO5
RL
330 Ω
Output 5
Output 4
Output 3
Output 2
Output 1
Output
Input
Input
Figure 4. Connection Diagrams
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640 × 1 LINEAR SENSOR ARRAY
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MECHANICAL INFORMATION
17 y 0.10 (2,54)
Pin 1 2 y j 0.090 (2,29)
TOP VIEW
Bonded Die Bypass Capacitor
Cover Glass 0.0272 (0,69)
CROSS SECTION
SIDE VIEW
SIDE VIEW
18 y j0.0272 (0,69)
0.0208 (0,53)
0.510 (12,95)
0.490 (12,45)
1.869 (47,46)
1.858 (47,20)
3.706 (94,125)
3.696 (93,875)
3.54 (89,92)
3.53 (89,66)
0.242 (6,15)
0.222 (5,64)
C
L
0.158 (4,01)
0.150 (3,81)
0.878 (22,30)
0.858 (21,80)
0.048 (1,22)
0.038 (0,97)
0.130 (3,30)
0.120 (3,05)
Pixel 640Pixel 1
NOTES: A. All linear dimensions are in inches (millimeters).
B. Pixel centers are located along the center line of the mounting holes.
C. Cover glass index of refraction is 1.52.
D. This drawing is subject to change without notice.
Figure 5. TSL210 Mechanical Specifications
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640 × 1 LINEAR SENSOR ARRAY
TAOS039D − AUGUST 2011
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PRODUCTION DATA — information in this document is current at publication date. Products conform to
specifications in accordance with the terms of Texas Advanced Optoelectronic Solutions, Inc. standard
warranty. Production processing does not necessarily include testing of all parameters.
NOTICE
Texas Advanced Optoelectronic Solutions, Inc. (TAOS) reserves the right to make changes to the products contained in this
document to improve performance or for any other purpose, or to discontinue them without notice. Customers are advised
to contact TAOS to obtain the latest product information before placing orders or designing TAOS products into systems.
TAOS assumes no responsibility for the use of any products or circuits described in this document or customer product
design, conveys no license, either expressed or implied, under any patent or other right, and makes no representation that
the circuits are free of patent infringement. TAOS further makes no claim as to the suitability of its products for any particular
purpose, nor does TAOS assume any liability arising out of the use of any product or circuit, and specifically disclaims any
and all liability, including without limitation consequential or incidental damages.
TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS, INC. PRODUCTS ARE NOT DESIGNED OR INTENDED FOR
USE IN CRITICAL APPLICATIONS IN WHICH THE FAILURE OR MALFUNCTION OF THE TAOS PRODUCT MAY
RESULT IN PERSONAL INJURY OR DEATH. USE OF TAOS PRODUCTS IN LIFE SUPPORT SYSTEMS IS EXPRESSLY
UNAUTHORIZED AND ANY SUCH USE BY A CUSTOMER IS COMPLETELY AT THE CUSTOMER’S RISK.
LUMENOLOGY, TAOS, the TAOS logo, and Texas Advanced Optoelectronic Solutions are registered trademarks of Texas Advanced
Optoelectronic Solutions Incorporated.
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