Digital Phase Shifter
4-Bit, 8.0 - 12.0 GHz
Rev. V3
MAPS-010146
5
5
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5
P/S LE Mode
1 X Serial
0 N/A Direct Parallel
Serial Mode
Direct Parallel Mode
The serial control interface (SERIN, CLK, LE,
SEROUT) is compatible with the SPI protocol. SPI
mode is activated when P/S is kept high. The 6-bit
serial word must be loaded with the MSB first. After
shifting in the 6 bit word, a rising edge on LE will set
the phase shifter to the desired state. While LE is
high the CLK is masked to protect the data while
implementing the change. SEROUT is SERIN
delayed by 6 clock cycles.
When P/S is low, the serial control interface is
disabled. When P/S is set high, Pins 22, 23, and 24
have the LE, CLK, and SER IN function.
In serial mode operation, the outputs will stay
constant while LE is kept low.
The parallel mode is enabled when P/S is set low. In
the direct parallel mode, the phase shifter is
controlled by the parallel control inputs directly.
When P/S is set low, Pins 22, 23, and 24 have the
D3, D2, and D1 function.
Modes of Operation:
Serial and Direct Parallel
Mode Truth Table 8,9
Serial Interface Timing Characteristics
Symbol Parameter
Typical Performance
Units
-40°C 25°C +85°C
tSCK Min. Serial Clock Period 100 100 100 ns
tCS Min. Control Set-up Time 20 20 20 ns
tCH Min. Control Hold Time 20 20 20 ns
tLS Min. LE Set-up Time 10 10 10 ns
tLEW Min. LE Pulse Width 10 10 10 ns
tLH Min. Serial Clock Hold Time from LE 10 10 10 ns
tLES Min. LE Pulse Spacing 630 630 630 ns
Truth Table (Digital Phase Shifter) 10
D6 D5 D4 D3 D2 D1 Phase Shift
0 0 0 0 X X Reference Phase
0 0 0 1 X X 22.5 deg
0 0 1 0 X X 45 deg
0 1 0 0 X X 90 deg
1 0 0 0 X X 180 deg
1 1 1 1 X X 337.5 deg
10. 0 = CMOS Low; 1 = CMOS High, X is CMOS Low or High
8. There are two dummy bits (D1 & D2), that must be sent in the
serial mode. This is because the 4 bit phase shifter uses the
same driver as the 6 bit phase shifter.
9. In the parallel mode, D1 and D2 should be tied to ground or to
VCC.