KV31F Sub-Family Reference Manual Supports: MKV31F512VLL12, MKV31F512VLH12, MKV31512VLL12P Document Number: KV31P100M120SF7RM Rev. 4, 02/2016 KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 2 Freescale Semiconductor, Inc. Contents Section number Title Page Chapter 1 About This Document 1.1 1.2 Overview.......................................................................................................................................................................43 1.1.1 Purpose.........................................................................................................................................................43 1.1.2 Audience...................................................................................................................................................... 43 Conventions.................................................................................................................................................................. 43 1.2.1 Numbering systems......................................................................................................................................43 1.2.2 Typographic notation................................................................................................................................... 44 1.2.3 Special terms................................................................................................................................................ 44 Chapter 2 Introduction 2.1 Overview.......................................................................................................................................................................45 2.2 Module Functional Categories......................................................................................................................................45 2.3 2.2.1 ARM(R) Cortex(R)-M4 Core Modules............................................................................................................ 46 2.2.2 System Modules........................................................................................................................................... 47 2.2.3 Memories and Memory Interfaces............................................................................................................... 48 2.2.4 Clocks...........................................................................................................................................................48 2.2.5 Security and Integrity modules.................................................................................................................... 48 2.2.6 Analog modules........................................................................................................................................... 49 2.2.7 Timer modules............................................................................................................................................. 49 2.2.8 Communication interfaces........................................................................................................................... 50 2.2.9 Human-machine interfaces.......................................................................................................................... 50 2.2.10 Kinetis Motor Suite...................................................................................................................................... 51 Orderable part numbers.................................................................................................................................................51 Chapter 3 Chip Configuration 3.1 Introduction...................................................................................................................................................................53 3.2 Core modules................................................................................................................................................................ 53 KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 3 Section number 3.3 3.4 3.5 3.6 Title Page 3.2.1 ARM Cortex-M4 Core Configuration..........................................................................................................53 3.2.2 Nested Vectored Interrupt Controller (NVIC) Configuration......................................................................55 3.2.3 Asynchronous Wake-up Interrupt Controller (AWIC) Configuration.........................................................61 3.2.4 FPU Configuration....................................................................................................................................... 62 3.2.5 JTAG Controller Configuration................................................................................................................... 62 System modules............................................................................................................................................................ 63 3.3.1 SIM Configuration....................................................................................................................................... 63 3.3.2 System Mode Controller (SMC) Configuration...........................................................................................64 3.3.3 PMC Configuration......................................................................................................................................64 3.3.4 Low-Leakage Wake-up Unit (LLWU) Configuration................................................................................. 65 3.3.5 MCM Configuration.................................................................................................................................... 66 3.3.6 Crossbar-Light Switch Configuration.......................................................................................................... 67 3.3.7 Peripheral Bridge Configuration.................................................................................................................. 69 3.3.8 DMA request multiplexer configuration......................................................................................................70 3.3.9 DMA Controller Configuration................................................................................................................... 73 3.3.10 External Watchdog Monitor (EWM) Configuration....................................................................................74 3.3.11 Watchdog Configuration..............................................................................................................................76 Clock modules.............................................................................................................................................................. 77 3.4.1 MCG Configuration..................................................................................................................................... 77 3.4.2 OSC Configuration...................................................................................................................................... 79 Memories and memory interfaces.................................................................................................................................79 3.5.1 Flash Memory Configuration.......................................................................................................................79 3.5.2 Flash Memory Controller Configuration..................................................................................................... 82 3.5.3 SRAM Configuration................................................................................................................................... 83 3.5.4 System Register File Configuration............................................................................................................. 84 3.5.5 EzPort Configuration................................................................................................................................... 85 3.5.6 FlexBus Configuration................................................................................................................................. 86 Security......................................................................................................................................................................... 89 3.6.1 CRC Configuration...................................................................................................................................... 89 KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 4 Freescale Semiconductor, Inc. Section number 3.6.2 3.7 3.8 3.9 3.10 Page RNG Configuration......................................................................................................................................90 Analog...........................................................................................................................................................................91 3.7.1 16-bit SAR ADC Configuration.................................................................................................................. 91 3.7.2 CMP Configuration......................................................................................................................................97 3.7.3 12-bit DAC Configuration........................................................................................................................... 99 3.7.4 VREF Configuration.................................................................................................................................... 101 Timers........................................................................................................................................................................... 102 3.8.1 PDB Configuration...................................................................................................................................... 102 3.8.2 FlexTimer Configuration............................................................................................................................. 105 3.8.3 PIT Configuration........................................................................................................................................ 111 3.8.4 Low-power timer configuration................................................................................................................... 112 Communication interfaces............................................................................................................................................ 114 3.9.1 SPI configuration......................................................................................................................................... 114 3.9.2 I2C Configuration........................................................................................................................................ 118 3.9.3 UART Configuration................................................................................................................................... 118 3.9.4 LPUART configuration................................................................................................................................121 Human-machine interfaces........................................................................................................................................... 121 3.10.1 3.11 Title GPIO configuration......................................................................................................................................122 Kinetis Motor Suite Configuration............................................................................................................................... 122 3.11.1 KMS configuration...................................................................................................................................... 123 3.11.2 KMS Library................................................................................................................................................ 123 3.11.3 Library Protection........................................................................................................................................ 124 3.11.4 Flash protection............................................................................................................................................124 Chapter 4 Memory Map 4.1 Introduction...................................................................................................................................................................125 4.2 System memory map.....................................................................................................................................................125 4.2.1 Aliased bit-band regions.............................................................................................................................. 127 4.2.2 Flash Access Control Introduction...............................................................................................................128 KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 5 Section number 4.3 Title Page Flash Memory Map.......................................................................................................................................................128 4.3.1 Alternate Non-Volatile IRC User Trim Description....................................................................................129 4.4 SRAM memory map..................................................................................................................................................... 129 4.5 Peripheral bridge (AIPS-Lite) memory map.................................................................................................................130 4.6 4.5.1 Read-after-write sequence and required serialization of memory operations..............................................130 4.5.2 Peripheral Bridge 0 (AIPS-Lite 0) Memory Map........................................................................................ 130 Private Peripheral Bus (PPB) memory map..................................................................................................................134 Chapter 5 Clock Distribution 5.1 Introduction...................................................................................................................................................................137 5.2 Programming model......................................................................................................................................................137 5.3 High-Level device clocking diagram............................................................................................................................137 5.4 Clock definitions...........................................................................................................................................................138 5.4.1 5.5 Device clock summary.................................................................................................................................139 Internal clocking requirements..................................................................................................................................... 141 5.5.1 Clock divider values after reset....................................................................................................................142 5.5.2 VLPR mode clocking...................................................................................................................................143 5.6 Clock Gating................................................................................................................................................................. 143 5.7 Module clocks...............................................................................................................................................................143 5.7.1 PMC 1-kHz LPO clock................................................................................................................................ 145 5.7.2 IRC 48MHz clock........................................................................................................................................ 145 5.7.3 WDOG clocking.......................................................................................................................................... 146 5.7.4 Debug trace clock.........................................................................................................................................146 5.7.5 PORT digital filter clocking.........................................................................................................................147 5.7.6 LPTMR clocking..........................................................................................................................................147 5.7.7 CLKOUT32K clocking................................................................................................................................148 5.7.8 UART clocking............................................................................................................................................ 148 5.7.9 LPUART0 clocking..................................................................................................................................... 149 Chapter 6 KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 6 Freescale Semiconductor, Inc. Section number Title Page Reset and Boot 6.1 Introduction...................................................................................................................................................................151 6.2 Reset..............................................................................................................................................................................152 6.3 6.2.1 Power-on reset (POR).................................................................................................................................. 152 6.2.2 System reset sources.................................................................................................................................... 152 6.2.3 MCU Resets................................................................................................................................................. 156 6.2.4 Reset Pin ..................................................................................................................................................... 157 6.2.5 Debug resets................................................................................................................................................. 158 Boot...............................................................................................................................................................................159 6.3.1 Boot sources................................................................................................................................................. 159 6.3.2 Boot options................................................................................................................................................. 159 6.3.3 FOPT boot options....................................................................................................................................... 159 6.3.4 Boot sequence.............................................................................................................................................. 161 Chapter 7 Power Management 7.1 Introduction...................................................................................................................................................................163 7.2 Clocking modes............................................................................................................................................................ 163 7.2.1 Partial Stop................................................................................................................................................... 163 7.2.2 DMA Wakeup.............................................................................................................................................. 164 7.2.3 Compute Operation...................................................................................................................................... 165 7.2.4 Peripheral Doze............................................................................................................................................166 7.2.5 Clock Gating................................................................................................................................................ 167 7.3 Power Modes Description.............................................................................................................................................167 7.4 Entering and exiting power modes............................................................................................................................... 169 7.5 Power mode transitions.................................................................................................................................................170 7.6 Power modes shutdown sequencing............................................................................................................................. 171 7.7 Flash Program Restrictions........................................................................................................................................... 172 7.8 Module Operation in Low Power Modes......................................................................................................................172 Chapter 8 Security KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 7 Section number Title Page 8.1 Introduction...................................................................................................................................................................177 8.2 Flash Security............................................................................................................................................................... 177 8.3 Security Interactions with other Modules..................................................................................................................... 178 8.3.1 Security interactions with FlexBus.............................................................................................................. 178 8.3.2 Security Interactions with EzPort................................................................................................................ 178 8.3.3 Security Interactions with Debug.................................................................................................................178 Chapter 9 Debug 9.1 Introduction...................................................................................................................................................................181 9.1.1 9.2 References.................................................................................................................................................... 183 The Debug Port............................................................................................................................................................. 183 9.2.1 JTAG-to-SWD change sequence................................................................................................................. 184 9.2.2 JTAG-to-cJTAG change sequence...............................................................................................................184 9.3 Debug Port Pin Descriptions.........................................................................................................................................185 9.4 System TAP connection................................................................................................................................................185 9.4.1 9.5 IR Codes.......................................................................................................................................................185 JTAG status and control registers................................................................................................................................. 186 9.5.1 MDM-AP Control Register..........................................................................................................................187 9.5.2 MDM-AP Status Register............................................................................................................................ 189 9.6 Debug Resets................................................................................................................................................................ 190 9.7 AHB-AP........................................................................................................................................................................191 9.8 ITM............................................................................................................................................................................... 191 9.9 Core Trace Connectivity............................................................................................................................................... 192 9.10 TPIU..............................................................................................................................................................................192 9.11 DWT............................................................................................................................................................................. 192 9.12 Debug in Low Power Modes........................................................................................................................................ 193 9.12.1 9.13 Debug Module State in Low Power Modes................................................................................................. 193 Debug & Security......................................................................................................................................................... 194 Chapter 10 KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 8 Freescale Semiconductor, Inc. Section number Title Page Signal Multiplexing and Signal Descriptions 10.1 Introduction...................................................................................................................................................................195 10.2 Signal Multiplexing Integration....................................................................................................................................195 10.3 10.4 10.2.1 Port control and interrupt module features.................................................................................................. 196 10.2.2 Clock gating................................................................................................................................................. 197 10.2.3 Signal multiplexing constraints....................................................................................................................197 Pinout............................................................................................................................................................................ 197 10.3.1 KV31F Signal Multiplexing and Pin Assignments......................................................................................197 10.3.2 KV31F Pinouts.............................................................................................................................................201 Module Signal Description Tables................................................................................................................................204 10.4.1 Core Modules............................................................................................................................................... 204 10.4.2 System Modules........................................................................................................................................... 204 10.4.3 Clock Modules............................................................................................................................................. 205 10.4.4 Memories and Memory Interfaces............................................................................................................... 205 10.4.5 Analog.......................................................................................................................................................... 208 10.4.6 Timer Modules............................................................................................................................................. 209 10.4.7 Communication Interfaces........................................................................................................................... 210 10.4.8 Human-Machine Interfaces (HMI).............................................................................................................. 212 Chapter 11 Port Control and Interrupts (PORT) 11.1 Introduction...................................................................................................................................................................213 11.2 Overview.......................................................................................................................................................................213 11.2.1 Features........................................................................................................................................................ 213 11.2.2 Modes of operation...................................................................................................................................... 214 11.3 External signal description............................................................................................................................................215 11.4 Detailed signal description............................................................................................................................................215 11.5 Memory map and register definition.............................................................................................................................215 11.5.1 Pin Control Register n (PORTx_PCRn).......................................................................................................222 11.5.2 Global Pin Control Low Register (PORTx_GPCLR).................................................................................. 225 KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 9 Section number 11.6 Title Page 11.5.3 Global Pin Control High Register (PORTx_GPCHR)................................................................................. 225 11.5.4 Interrupt Status Flag Register (PORTx_ISFR)............................................................................................ 226 11.5.5 Digital Filter Enable Register (PORTx_DFER)...........................................................................................226 11.5.6 Digital Filter Clock Register (PORTx_DFCR)............................................................................................ 227 11.5.7 Digital Filter Width Register (PORTx_DFWR).......................................................................................... 227 Functional description...................................................................................................................................................228 11.6.1 Pin control.................................................................................................................................................... 228 11.6.2 Global pin control........................................................................................................................................ 229 11.6.3 External interrupts........................................................................................................................................229 11.6.4 Digital filter..................................................................................................................................................230 Chapter 12 System Integration Module (SIM) 12.1 Introduction...................................................................................................................................................................233 12.1.1 12.2 Features........................................................................................................................................................ 233 Memory map and register definition.............................................................................................................................234 12.2.1 System Options Register 1 (SIM_SOPT1).................................................................................................. 235 12.2.2 SOPT1 Configuration Register (SIM_SOPT1CFG)....................................................................................236 12.2.3 System Options Register 2 (SIM_SOPT2).................................................................................................. 237 12.2.4 System Options Register 4 (SIM_SOPT4).................................................................................................. 239 12.2.5 System Options Register 5 (SIM_SOPT5).................................................................................................. 242 12.2.6 System Options Register 7 (SIM_SOPT7).................................................................................................. 243 12.2.7 System Options Register 8 (SIM_SOPT8).................................................................................................. 245 12.2.8 System Device Identification Register (SIM_SDID)...................................................................................247 12.2.9 System Clock Gating Control Register 4 (SIM_SCGC4)............................................................................249 12.2.10 System Clock Gating Control Register 5 (SIM_SCGC5)............................................................................251 12.2.11 System Clock Gating Control Register 6 (SIM_SCGC6)............................................................................253 12.2.12 System Clock Gating Control Register 7 (SIM_SCGC7)............................................................................256 12.2.13 System Clock Divider Register 1 (SIM_CLKDIV1)................................................................................... 256 12.2.14 Flash Configuration Register 1 (SIM_FCFG1)........................................................................................... 259 KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 10 Freescale Semiconductor, Inc. Section number 12.3 Title Page 12.2.15 Flash Configuration Register 2 (SIM_FCFG2)........................................................................................... 261 12.2.16 Unique Identification Register High (SIM_UIDH)..................................................................................... 261 12.2.17 Unique Identification Register Mid-High (SIM_UIDMH)..........................................................................262 12.2.18 Unique Identification Register Mid Low (SIM_UIDML)........................................................................... 262 12.2.19 Unique Identification Register Low (SIM_UIDL)...................................................................................... 263 Functional description...................................................................................................................................................263 Chapter 13 Kinetis Flashloader 13.1 Chip-Specific Information............................................................................................................................................ 265 13.2 Introduction...................................................................................................................................................................265 13.3 Functional Description..................................................................................................................................................267 13.4 13.5 13.3.1 Memory Maps.............................................................................................................................................. 267 13.3.2 Start-up Process............................................................................................................................................267 13.3.3 Clock Configuration.....................................................................................................................................268 13.3.4 Flashloader Protocol.................................................................................................................................... 268 13.3.5 Flashloader Packet Types.............................................................................................................................273 13.3.6 Flashloader Command API.......................................................................................................................... 280 Peripherals Supported................................................................................................................................................... 299 13.4.1 I2C Peripheral.............................................................................................................................................. 299 13.4.2 SPI Peripheral.............................................................................................................................................. 301 13.4.3 UART Peripheral......................................................................................................................................... 303 Get/SetProperty Command Properties..........................................................................................................................306 13.5.1 13.6 Property Definitions..................................................................................................................................... 307 Kinetis Flashloader Status Error Codes........................................................................................................................ 309 Chapter 14 Reset Control Module (RCM) 14.1 Introduction...................................................................................................................................................................311 14.2 Reset memory map and register descriptions............................................................................................................... 311 14.2.1 System Reset Status Register 0 (RCM_SRS0)............................................................................................ 312 KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 11 Section number Title Page 14.2.2 System Reset Status Register 1 (RCM_SRS1)............................................................................................ 313 14.2.3 Reset Pin Filter Control register (RCM_RPFC).......................................................................................... 315 14.2.4 Reset Pin Filter Width register (RCM_RPFW)........................................................................................... 316 14.2.5 Mode Register (RCM_MR)......................................................................................................................... 317 14.2.6 Sticky System Reset Status Register 0 (RCM_SSRS0)...............................................................................318 14.2.7 Sticky System Reset Status Register 1 (RCM_SSRS1)...............................................................................319 Chapter 15 System Mode Controller (SMC) 15.1 Introduction...................................................................................................................................................................321 15.2 Modes of operation....................................................................................................................................................... 321 15.3 Memory map and register descriptions.........................................................................................................................323 15.4 15.3.1 Power Mode Protection register (SMC_PMPROT).....................................................................................324 15.3.2 Power Mode Control register (SMC_PMCTRL).........................................................................................325 15.3.3 Stop Control Register (SMC_STOPCTRL).................................................................................................327 15.3.4 Power Mode Status register (SMC_PMSTAT)........................................................................................... 328 Functional description...................................................................................................................................................329 15.4.1 Power mode transitions................................................................................................................................ 329 15.4.2 Power mode entry/exit sequencing.............................................................................................................. 332 15.4.3 Run modes....................................................................................................................................................334 15.4.4 Wait modes.................................................................................................................................................. 336 15.4.5 Stop modes................................................................................................................................................... 337 15.4.6 Debug in low power modes......................................................................................................................... 340 Chapter 16 Power Management Controller (PMC) 16.1 Introduction...................................................................................................................................................................343 16.2 Features......................................................................................................................................................................... 343 16.3 Low-voltage detect (LVD) system................................................................................................................................343 16.3.1 LVD reset operation.....................................................................................................................................344 16.3.2 LVD interrupt operation...............................................................................................................................344 KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 12 Freescale Semiconductor, Inc. Section number 16.3.3 Title Page Low-voltage warning (LVW) interrupt operation....................................................................................... 344 16.4 I/O retention.................................................................................................................................................................. 345 16.5 Memory map and register descriptions.........................................................................................................................345 16.5.1 Low Voltage Detect Status And Control 1 register (PMC_LVDSC1)........................................................ 346 16.5.2 Low Voltage Detect Status And Control 2 register (PMC_LVDSC2)........................................................ 347 16.5.3 Regulator Status And Control register (PMC_REGSC).............................................................................. 348 Chapter 17 Low-Leakage Wakeup Unit (LLWU) 17.1 Introduction...................................................................................................................................................................351 17.1.1 Features........................................................................................................................................................ 351 17.1.2 Modes of operation...................................................................................................................................... 352 17.1.3 Block diagram.............................................................................................................................................. 353 17.2 LLWU signal descriptions............................................................................................................................................ 354 17.3 Memory map/register definition................................................................................................................................... 354 17.4 17.3.1 LLWU Pin Enable 1 register (LLWU_PE1)................................................................................................355 17.3.2 LLWU Pin Enable 2 register (LLWU_PE2)................................................................................................356 17.3.3 LLWU Pin Enable 3 register (LLWU_PE3)................................................................................................357 17.3.4 LLWU Pin Enable 4 register (LLWU_PE4)................................................................................................358 17.3.5 LLWU Module Enable register (LLWU_ME)............................................................................................ 359 17.3.6 LLWU Flag 1 register (LLWU_F1).............................................................................................................361 17.3.7 LLWU Flag 2 register (LLWU_F2).............................................................................................................363 17.3.8 LLWU Flag 3 register (LLWU_F3).............................................................................................................364 17.3.9 LLWU Pin Filter 1 register (LLWU_FILT1).............................................................................................. 366 17.3.10 LLWU Pin Filter 2 register (LLWU_FILT2).............................................................................................. 367 Functional description...................................................................................................................................................368 17.4.1 LLS mode.....................................................................................................................................................369 17.4.2 VLLS modes................................................................................................................................................ 369 17.4.3 Initialization................................................................................................................................................. 369 Chapter 18 KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 13 Section number Title Page Miscellaneous Control Module (MCM) 18.1 Introduction...................................................................................................................................................................371 18.1.1 18.2 18.3 Features........................................................................................................................................................ 371 Memory map/register descriptions............................................................................................................................... 371 18.2.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)................................................................372 18.2.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC)............................................................ 372 18.2.3 Crossbar Switch (AXBS) Control Register (MCM_PLACR)..................................................................... 373 18.2.4 Interrupt Status and Control Register (MCM_ISCR).................................................................................. 373 18.2.5 Compute Operation Control Register (MCM_CPO)................................................................................... 376 Functional description...................................................................................................................................................377 18.3.1 Interrupts...................................................................................................................................................... 377 Chapter 19 Crossbar Switch Lite (AXBS-Lite) 19.1 Introduction...................................................................................................................................................................379 19.1.1 Features........................................................................................................................................................ 379 19.2 Memory Map / Register Definition...............................................................................................................................380 19.3 Functional Description..................................................................................................................................................380 19.4 19.3.1 General operation......................................................................................................................................... 380 19.3.2 Arbitration.................................................................................................................................................... 381 Initialization/application information........................................................................................................................... 382 Chapter 20 Peripheral Bridge (AIPS-Lite) 20.1 Introduction...................................................................................................................................................................383 20.1.1 Features........................................................................................................................................................ 383 20.1.2 General operation......................................................................................................................................... 383 20.2 Memory map/register definition................................................................................................................................... 384 20.3 Functional description...................................................................................................................................................384 20.3.1 Access support............................................................................................................................................. 384 Chapter 21 Direct Memory Access Multiplexer (DMAMUX) KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 14 Freescale Semiconductor, Inc. Section number 21.1 Title Page Introduction...................................................................................................................................................................385 21.1.1 Overview...................................................................................................................................................... 385 21.1.2 Features........................................................................................................................................................ 386 21.1.3 Modes of operation...................................................................................................................................... 386 21.2 External signal description............................................................................................................................................387 21.3 Memory map/register definition................................................................................................................................... 387 21.3.1 21.4 21.5 Channel Configuration register (DMAMUX_CHCFGn)............................................................................ 388 Functional description...................................................................................................................................................389 21.4.1 DMA channels with periodic triggering capability......................................................................................389 21.4.2 DMA channels with no triggering capability...............................................................................................391 21.4.3 Always-enabled DMA sources.................................................................................................................... 392 Initialization/application information........................................................................................................................... 393 21.5.1 Reset.............................................................................................................................................................393 21.5.2 Enabling and configuring sources................................................................................................................393 Chapter 22 Enhanced Direct Memory Access (eDMA) 22.1 Introduction...................................................................................................................................................................397 22.1.1 eDMA system block diagram...................................................................................................................... 397 22.1.2 Block parts................................................................................................................................................... 398 22.1.3 Features........................................................................................................................................................ 399 22.2 Modes of operation....................................................................................................................................................... 400 22.3 Memory map/register definition................................................................................................................................... 401 22.3.1 TCD memory............................................................................................................................................... 401 22.3.2 TCD initialization........................................................................................................................................ 401 22.3.3 TCD structure...............................................................................................................................................401 22.3.4 Reserved memory and bit fields...................................................................................................................402 22.3.1 Control Register (DMA_CR).......................................................................................................................413 22.3.2 Error Status Register (DMA_ES)................................................................................................................ 416 22.3.3 Enable Request Register (DMA_ERQ)....................................................................................................... 418 KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 15 Section number Title Page 22.3.4 Enable Error Interrupt Register (DMA_EEI)...............................................................................................420 22.3.5 Clear Enable Error Interrupt Register (DMA_CEEI).................................................................................. 422 22.3.6 Set Enable Error Interrupt Register (DMA_SEEI)...................................................................................... 423 22.3.7 Clear Enable Request Register (DMA_CERQ)........................................................................................... 424 22.3.8 Set Enable Request Register (DMA_SERQ)............................................................................................... 425 22.3.9 Clear DONE Status Bit Register (DMA_CDNE)........................................................................................ 426 22.3.10 Set START Bit Register (DMA_SSRT)...................................................................................................... 427 22.3.11 Clear Error Register (DMA_CERR)............................................................................................................428 22.3.12 Clear Interrupt Request Register (DMA_CINT)......................................................................................... 429 22.3.13 Interrupt Request Register (DMA_INT)......................................................................................................430 22.3.14 Error Register (DMA_ERR)........................................................................................................................ 432 22.3.15 Hardware Request Status Register (DMA_HRS)........................................................................................ 435 22.3.16 Enable Asynchronous Request in Stop Register (DMA_EARS).................................................................438 22.3.17 Channel n Priority Register (DMA_DCHPRIn).......................................................................................... 440 22.3.18 TCD Source Address (DMA_TCDn_SADDR)........................................................................................... 441 22.3.19 TCD Signed Source Address Offset (DMA_TCDn_SOFF)........................................................................441 22.3.20 TCD Transfer Attributes (DMA_TCDn_ATTR).........................................................................................442 22.3.21 TCD Minor Byte Count (Minor Loop Mapping Disabled) (DMA_TCDn_NBYTES_MLNO)................. 443 22.3.22 TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) (DMA_TCDn_NBYTES_MLOFFNO)....................................................................................................... 444 22.3.23 TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) (DMA_TCDn_NBYTES_MLOFFYES)..................................................................................................... 445 22.3.24 TCD Last Source Address Adjustment (DMA_TCDn_SLAST).................................................................446 22.3.25 TCD Destination Address (DMA_TCDn_DADDR)................................................................................... 447 22.3.26 TCD Signed Destination Address Offset (DMA_TCDn_DOFF)................................................................447 22.3.27 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCDn_CITER_ELINKYES)...........................................................................................................448 22.3.28 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCDn_CITER_ELINKNO)............................................................................................................ 449 22.3.29 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCDn_DLASTSGA).......... 450 KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 16 Freescale Semiconductor, Inc. Section number Title Page 22.3.30 TCD Control and Status (DMA_TCDn_CSR)............................................................................................ 451 22.3.31 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCDn_BITER_ELINKYES)...........................................................................................................453 22.3.32 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCDn_BITER_ELINKNO)............................................................................................................ 454 22.4 22.5 Functional description...................................................................................................................................................455 22.4.1 eDMA basic data flow................................................................................................................................. 455 22.4.2 Fault reporting and handling........................................................................................................................ 458 22.4.3 Channel preemption..................................................................................................................................... 461 22.4.4 Performance................................................................................................................................................. 461 Initialization/application information........................................................................................................................... 465 22.5.1 eDMA initialization..................................................................................................................................... 465 22.5.2 Programming errors..................................................................................................................................... 467 22.5.3 Arbitration mode considerations.................................................................................................................. 468 22.5.4 Performing DMA transfers.......................................................................................................................... 468 22.5.5 Monitoring transfer descriptor status........................................................................................................... 472 22.5.6 Channel Linking...........................................................................................................................................474 22.5.7 Dynamic programming................................................................................................................................ 475 Chapter 23 External Watchdog Monitor (EWM) 23.1 Introduction...................................................................................................................................................................481 23.1.1 Features........................................................................................................................................................ 481 23.1.2 Modes of Operation..................................................................................................................................... 482 23.1.3 Block Diagram............................................................................................................................................. 483 23.2 EWM Signal Descriptions............................................................................................................................................ 484 23.3 Memory Map/Register Definition.................................................................................................................................484 23.3.1 Control Register (EWM_CTRL)................................................................................................................. 484 23.3.2 Service Register (EWM_SERV)..................................................................................................................485 23.3.3 Compare Low Register (EWM_CMPL)...................................................................................................... 485 23.3.4 Compare High Register (EWM_CMPH)..................................................................................................... 486 KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 17 Section number 23.3.5 23.4 Title Page Clock Prescaler Register (EWM_CLKPRESCALER)................................................................................ 487 Functional Description..................................................................................................................................................487 23.4.1 The EWM_out Signal.................................................................................................................................. 487 23.4.2 The EWM_in Signal.................................................................................................................................... 488 23.4.3 EWM Counter.............................................................................................................................................. 489 23.4.4 EWM Compare Registers............................................................................................................................ 489 23.4.5 EWM Refresh Mechanism...........................................................................................................................489 23.4.6 EWM Interrupt............................................................................................................................................. 490 23.4.7 Counter clock prescaler................................................................................................................................490 Chapter 24 Watchdog Timer (WDOG) 24.1 Introduction...................................................................................................................................................................491 24.2 Features......................................................................................................................................................................... 491 24.3 Functional overview......................................................................................................................................................492 24.4 24.3.1 Unlocking and updating the watchdog.........................................................................................................494 24.3.2 Watchdog configuration time (WCT).......................................................................................................... 495 24.3.3 Refreshing the watchdog..............................................................................................................................496 24.3.4 Windowed mode of operation......................................................................................................................496 24.3.5 Watchdog disabled mode of operation.........................................................................................................496 24.3.6 Debug modes of operation........................................................................................................................... 496 Testing the watchdog.................................................................................................................................................... 497 24.4.1 Quick test..................................................................................................................................................... 498 24.4.2 Byte test........................................................................................................................................................498 24.5 Backup reset generator..................................................................................................................................................499 24.6 Generated resets and interrupts.....................................................................................................................................500 24.7 Memory map and register definition.............................................................................................................................500 24.7.1 Watchdog Status and Control Register High (WDOG_STCTRLH)........................................................... 501 24.7.2 Watchdog Status and Control Register Low (WDOG_STCTRLL)............................................................ 503 24.7.3 Watchdog Time-out Value Register High (WDOG_TOVALH)................................................................. 503 KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 18 Freescale Semiconductor, Inc. Section number 24.8 24.9 Title Page 24.7.4 Watchdog Time-out Value Register Low (WDOG_TOVALL).................................................................. 504 24.7.5 Watchdog Window Register High (WDOG_WINH).................................................................................. 504 24.7.6 Watchdog Window Register Low (WDOG_WINL)................................................................................... 505 24.7.7 Watchdog Refresh register (WDOG_REFRESH)....................................................................................... 505 24.7.8 Watchdog Unlock register (WDOG_UNLOCK).........................................................................................505 24.7.9 Watchdog Timer Output Register High (WDOG_TMROUTH)................................................................. 506 24.7.10 Watchdog Timer Output Register Low (WDOG_TMROUTL).................................................................. 506 24.7.11 Watchdog Reset Count register (WDOG_RSTCNT).................................................................................. 507 24.7.12 Watchdog Prescaler register (WDOG_PRESC).......................................................................................... 507 Watchdog operation with 8-bit access.......................................................................................................................... 507 24.8.1 General guideline......................................................................................................................................... 507 24.8.2 Refresh and unlock operations with 8-bit access......................................................................................... 508 Restrictions on watchdog operation..............................................................................................................................509 Chapter 25 Multipurpose Clock Generator (MCG) 25.1 Introduction...................................................................................................................................................................511 25.1.1 Features........................................................................................................................................................ 511 25.1.2 Modes of Operation..................................................................................................................................... 515 25.2 External Signal Description.......................................................................................................................................... 515 25.3 Memory Map/Register Definition.................................................................................................................................515 25.3.1 MCG Control 1 Register (MCG_C1)...........................................................................................................516 25.3.2 MCG Control 2 Register (MCG_C2)...........................................................................................................517 25.3.3 MCG Control 3 Register (MCG_C3)...........................................................................................................518 25.3.4 MCG Control 4 Register (MCG_C4)...........................................................................................................519 25.3.5 MCG Control 5 Register (MCG_C5)...........................................................................................................520 25.3.6 MCG Control 6 Register (MCG_C6)...........................................................................................................521 25.3.7 MCG Status Register (MCG_S).................................................................................................................. 523 25.3.8 MCG Status and Control Register (MCG_SC)............................................................................................524 25.3.9 MCG Auto Trim Compare Value High Register (MCG_ATCVH)............................................................ 526 KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 19 Section number 25.4 25.5 Title Page 25.3.10 MCG Auto Trim Compare Value Low Register (MCG_ATCVL)..............................................................526 25.3.11 MCG Control 7 Register (MCG_C7)...........................................................................................................526 25.3.12 MCG Control 8 Register (MCG_C8)...........................................................................................................527 25.3.13 MCG Control 12 Register (MCG_C12).......................................................................................................528 25.3.13 MCG Status 2 Register (MCG_S2)............................................................................................................. 528 25.3.13 MCG Test 3 Register (MCG_T3)................................................................................................................ 529 Functional description...................................................................................................................................................529 25.4.1 MCG mode state diagram............................................................................................................................ 529 25.4.2 Low-power bit usage....................................................................................................................................533 25.4.3 MCG Internal Reference Clocks..................................................................................................................533 25.4.4 External Reference Clock............................................................................................................................ 534 25.4.5 MCG Fixed Frequency Clock ..................................................................................................................... 535 25.4.6 MCG PLL clock ..........................................................................................................................................535 25.4.7 MCG Auto TRIM (ATM)............................................................................................................................ 535 Initialization / Application information........................................................................................................................ 536 25.5.1 MCG module initialization sequence...........................................................................................................536 25.5.2 Using a 32.768 kHz reference......................................................................................................................539 25.5.3 MCG mode switching.................................................................................................................................. 539 Chapter 26 Oscillator (OSC) 26.1 Introduction...................................................................................................................................................................549 26.2 Features and Modes...................................................................................................................................................... 549 26.3 Block Diagram.............................................................................................................................................................. 550 26.4 OSC Signal Descriptions.............................................................................................................................................. 550 26.5 External Crystal / Resonator Connections.................................................................................................................... 551 26.6 External Clock Connections......................................................................................................................................... 552 26.7 Memory Map/Register Definitions............................................................................................................................... 553 26.7.1 26.8 OSC Memory Map/Register Definition....................................................................................................... 553 Functional Description..................................................................................................................................................555 KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 20 Freescale Semiconductor, Inc. Section number 26.9 Title Page 26.8.1 OSC module states....................................................................................................................................... 555 26.8.2 OSC module modes..................................................................................................................................... 557 26.8.3 Counter.........................................................................................................................................................559 26.8.4 Reference clock pin requirements................................................................................................................559 Reset..............................................................................................................................................................................559 26.10 Low power modes operation.........................................................................................................................................560 26.11 Interrupts....................................................................................................................................................................... 560 Chapter 27 Flash Memory Controller (FMC) 27.1 Introduction...................................................................................................................................................................561 27.1.1 Overview...................................................................................................................................................... 561 27.1.2 Features........................................................................................................................................................ 561 27.2 Modes of operation....................................................................................................................................................... 562 27.3 External signal description............................................................................................................................................562 27.4 Memory map and register descriptions.........................................................................................................................562 27.4.1 Flash Access Protection Register (FMC_PFAPR).......................................................................................568 27.4.2 Flash Bank 0 Control Register (FMC_PFB0CR)........................................................................................ 570 27.4.3 Flash Bank 1 Control Register (FMC_PFB1CR)........................................................................................ 573 27.4.4 Cache Tag Storage (FMC_TAGVDW0Sn)................................................................................................. 575 27.4.5 Cache Tag Storage (FMC_TAGVDW1Sn)................................................................................................. 576 27.4.6 Cache Tag Storage (FMC_TAGVDW2Sn)................................................................................................. 577 27.4.7 Cache Tag Storage (FMC_TAGVDW3Sn)................................................................................................. 578 27.4.8 Cache Data Storage (upper word) (FMC_DATAW0SnU)..........................................................................578 27.4.9 Cache Data Storage (lower word) (FMC_DATAW0SnL).......................................................................... 579 27.4.10 Cache Data Storage (upper word) (FMC_DATAW1SnU)..........................................................................579 27.4.11 Cache Data Storage (lower word) (FMC_DATAW1SnL).......................................................................... 580 27.4.12 Cache Data Storage (upper word) (FMC_DATAW2SnU)..........................................................................580 27.4.13 Cache Data Storage (lower word) (FMC_DATAW2SnL).......................................................................... 581 27.4.14 Cache Data Storage (upper word) (FMC_DATAW3SnU)..........................................................................581 KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 21 Section number 27.4.15 27.5 27.6 Title Page Cache Data Storage (lower word) (FMC_DATAW3SnL).......................................................................... 582 Functional description...................................................................................................................................................582 27.5.1 Default configuration................................................................................................................................... 582 27.5.2 Configuration options.................................................................................................................................. 583 27.5.3 Speculative reads..........................................................................................................................................583 27.5.4 Flash Access Control (FAC) Function.........................................................................................................584 Initialization and application information.....................................................................................................................595 Chapter 28 Flash Memory Module (FTFA) 28.1 Introduction...................................................................................................................................................................597 28.1.1 Features........................................................................................................................................................ 598 28.1.2 Block Diagram............................................................................................................................................. 598 28.1.3 Glossary....................................................................................................................................................... 599 28.2 External Signal Description.......................................................................................................................................... 600 28.3 Memory Map and Registers..........................................................................................................................................601 28.4 28.3.1 Flash Configuration Field Description.........................................................................................................601 28.3.2 Program Flash IFR Map...............................................................................................................................601 28.3.3 Register Descriptions................................................................................................................................... 602 Functional Description..................................................................................................................................................616 28.4.1 Flash Protection............................................................................................................................................616 28.4.2 Flash Access Protection............................................................................................................................... 616 28.4.3 Interrupts...................................................................................................................................................... 618 28.4.4 Flash Operation in Low-Power Modes........................................................................................................ 619 28.4.5 Functional Modes of Operation................................................................................................................... 619 28.4.6 Flash Reads and Ignored Writes.................................................................................................................. 619 28.4.7 Read While Write (RWW)...........................................................................................................................620 28.4.8 Flash Program and Erase..............................................................................................................................620 28.4.9 Flash Command Operations.........................................................................................................................620 28.4.10 Margin Read Commands............................................................................................................................. 626 KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 22 Freescale Semiconductor, Inc. Section number Title Page 28.4.11 Flash Command Description........................................................................................................................627 28.4.12 Security........................................................................................................................................................ 645 28.4.13 Reset Sequence............................................................................................................................................ 647 Chapter 29 EzPort 29.1 29.2 29.3 Overview.......................................................................................................................................................................649 29.1.1 Block diagram.............................................................................................................................................. 649 29.1.2 Features........................................................................................................................................................ 650 29.1.3 Modes of operation...................................................................................................................................... 650 External signal descriptions.......................................................................................................................................... 651 29.2.1 EzPort Clock (EZP_CK).............................................................................................................................. 651 29.2.2 EzPort Chip Select (EZP_CS)......................................................................................................................652 29.2.3 EzPort Serial Data In (EZP_D).................................................................................................................... 652 29.2.4 EzPort Serial Data Out (EZP_Q)................................................................................................................. 652 Command definition..................................................................................................................................................... 652 29.3.1 29.4 Command descriptions.................................................................................................................................653 Flash memory map for EzPort access...........................................................................................................................660 Chapter 30 External Bus Interface (FlexBus) 30.1 Introduction...................................................................................................................................................................661 30.1.1 Definition..................................................................................................................................................... 661 30.1.2 Features........................................................................................................................................................ 661 30.2 Signal descriptions........................................................................................................................................................ 662 30.3 Memory Map/Register Definition.................................................................................................................................664 30.4 30.3.1 Chip Select Address Register (FB_CSARn)................................................................................................665 30.3.2 Chip Select Mask Register (FB_CSMRn)................................................................................................... 666 30.3.3 Chip Select Control Register (FB_CSCRn).................................................................................................667 30.3.4 Chip Select port Multiplexing Control Register (FB_CSPMCR)................................................................670 Functional description...................................................................................................................................................671 KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 23 Section number 30.5 Title Page 30.4.1 Use cases...................................................................................................................................................... 671 30.4.2 Address comparison..................................................................................................................................... 672 30.4.3 Address driven on address bus.....................................................................................................................672 30.4.4 Connecting address/data lines...................................................................................................................... 672 30.4.5 Bit ordering.................................................................................................................................................. 673 30.4.6 Data transfer signals.....................................................................................................................................673 30.4.7 Signal transitions..........................................................................................................................................673 30.4.8 Data-byte alignment and physical connections............................................................................................673 30.4.9 Address/data bus multiplexing.....................................................................................................................675 30.4.10 Data transfer states....................................................................................................................................... 676 30.4.11 FlexBus Timing Examples...........................................................................................................................677 30.4.12 Burst cycles.................................................................................................................................................. 696 30.4.13 Extended Transfer Start/Address Latch Enable........................................................................................... 705 30.4.14 Bus errors..................................................................................................................................................... 706 Initialization/Application Information.......................................................................................................................... 707 30.5.1 Initializing a chip-select............................................................................................................................... 707 30.5.2 Reconfiguring a chip-select......................................................................................................................... 707 Chapter 31 Cyclic Redundancy Check (CRC) 31.1 31.2 31.3 Introduction...................................................................................................................................................................709 31.1.1 Features........................................................................................................................................................ 709 31.1.2 Block diagram.............................................................................................................................................. 709 31.1.3 Modes of operation...................................................................................................................................... 710 Memory map and register descriptions.........................................................................................................................710 31.2.1 CRC Data register (CRC_DATA)............................................................................................................... 711 31.2.2 CRC Polynomial register (CRC_GPOLY).................................................................................................. 712 31.2.3 CRC Control register (CRC_CTRL)............................................................................................................712 Functional description...................................................................................................................................................713 31.3.1 CRC initialization/reinitialization................................................................................................................ 713 KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 24 Freescale Semiconductor, Inc. Section number Title Page 31.3.2 CRC calculations..........................................................................................................................................714 31.3.3 Transpose feature......................................................................................................................................... 715 31.3.4 CRC result complement............................................................................................................................... 717 Chapter 32 Random Number Generator Accelerator (RNGA) 32.1 Introduction...................................................................................................................................................................719 32.1.1 32.2 32.3 32.4 32.5 Overview...................................................................................................................................................... 719 Modes of operation....................................................................................................................................................... 720 32.2.1 Entering Normal mode.................................................................................................................................720 32.2.2 Entering Sleep mode.................................................................................................................................... 720 Memory map and register definition.............................................................................................................................721 32.3.1 RNGA Control Register (RNG_CR)........................................................................................................... 721 32.3.2 RNGA Status Register (RNG_SR).............................................................................................................. 723 32.3.3 RNGA Entropy Register (RNG_ER)........................................................................................................... 725 32.3.4 RNGA Output Register (RNG_OR)............................................................................................................ 725 Functional description...................................................................................................................................................726 32.4.1 Output (OR) register.................................................................................................................................... 726 32.4.2 Core engine / control logic...........................................................................................................................726 Initialization/application information........................................................................................................................... 727 Chapter 33 Analog-to-Digital Converter (ADC) 33.1 33.2 Introduction...................................................................................................................................................................729 33.1.1 Features........................................................................................................................................................ 729 33.1.2 Block diagram.............................................................................................................................................. 730 ADC signal descriptions............................................................................................................................................... 731 33.2.1 Analog Power (VDDA)............................................................................................................................... 732 33.2.2 Analog Ground (VSSA)...............................................................................................................................732 33.2.3 Voltage Reference Select............................................................................................................................. 732 33.2.4 Analog Channel Inputs (ADx)..................................................................................................................... 733 KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 25 Section number 33.2.5 33.3 33.4 Title Page Differential Analog Channel Inputs (DADx)...............................................................................................733 Memory map and register definitions........................................................................................................................... 733 33.3.1 ADC Status and Control Registers 1 (ADCx_SC1n)...................................................................................735 33.3.2 ADC Configuration Register 1 (ADCx_CFG1)...........................................................................................739 33.3.3 ADC Configuration Register 2 (ADCx_CFG2)...........................................................................................740 33.3.4 ADC Data Result Register (ADCx_Rn).......................................................................................................741 33.3.5 Compare Value Registers (ADCx_CVn)..................................................................................................... 743 33.3.6 Status and Control Register 2 (ADCx_SC2)................................................................................................744 33.3.7 Status and Control Register 3 (ADCx_SC3)................................................................................................746 33.3.8 ADC Offset Correction Register (ADCx_OFS)...........................................................................................747 33.3.9 ADC Plus-Side Gain Register (ADCx_PG).................................................................................................748 33.3.10 ADC Minus-Side Gain Register (ADCx_MG)............................................................................................ 748 33.3.11 ADC Plus-Side General Calibration Value Register (ADCx_CLPD)......................................................... 749 33.3.12 ADC Plus-Side General Calibration Value Register (ADCx_CLPS).......................................................... 750 33.3.13 ADC Plus-Side General Calibration Value Register (ADCx_CLP4).......................................................... 750 33.3.14 ADC Plus-Side General Calibration Value Register (ADCx_CLP3).......................................................... 751 33.3.15 ADC Plus-Side General Calibration Value Register (ADCx_CLP2).......................................................... 751 33.3.16 ADC Plus-Side General Calibration Value Register (ADCx_CLP1).......................................................... 752 33.3.17 ADC Plus-Side General Calibration Value Register (ADCx_CLP0).......................................................... 752 33.3.18 ADC Minus-Side General Calibration Value Register (ADCx_CLMD).....................................................753 33.3.19 ADC Minus-Side General Calibration Value Register (ADCx_CLMS)..................................................... 753 33.3.20 ADC Minus-Side General Calibration Value Register (ADCx_CLM4)..................................................... 754 33.3.21 ADC Minus-Side General Calibration Value Register (ADCx_CLM3)..................................................... 754 33.3.22 ADC Minus-Side General Calibration Value Register (ADCx_CLM2)..................................................... 755 33.3.23 ADC Minus-Side General Calibration Value Register (ADCx_CLM1)..................................................... 755 33.3.24 ADC Minus-Side General Calibration Value Register (ADCx_CLM0)..................................................... 756 Functional description...................................................................................................................................................756 33.4.1 Clock select and divide control.................................................................................................................... 757 33.4.2 Hardware trigger and channel selects.......................................................................................................... 758 KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 26 Freescale Semiconductor, Inc. Section number 33.5 Page 33.4.3 Conversion control....................................................................................................................................... 759 33.4.4 Automatic compare function........................................................................................................................766 33.4.5 Calibration function..................................................................................................................................... 768 33.4.6 User-defined offset function........................................................................................................................ 769 33.4.7 Temperature sensor...................................................................................................................................... 770 33.4.8 MCU wait mode operation...........................................................................................................................771 33.4.9 MCU Normal Stop mode operation............................................................................................................. 772 33.4.10 MCU Low-Power Stop mode operation...................................................................................................... 773 Initialization information.............................................................................................................................................. 773 33.5.1 33.6 Title ADC module initialization example............................................................................................................ 773 Application information................................................................................................................................................775 33.6.1 External pins and routing............................................................................................................................. 775 33.6.2 Sources of error............................................................................................................................................ 777 Chapter 34 Comparator (CMP) 34.1 34.2 34.3 Introduction...................................................................................................................................................................783 34.1.1 CMP features................................................................................................................................................783 34.1.2 6-bit DAC key features................................................................................................................................ 784 34.1.3 ANMUX key features.................................................................................................................................. 784 34.1.4 CMP, DAC and ANMUX diagram..............................................................................................................785 34.1.5 CMP block diagram..................................................................................................................................... 786 Memory map/register definitions..................................................................................................................................788 34.2.1 CMP Control Register 0 (CMPx_CR0)....................................................................................................... 788 34.2.2 CMP Control Register 1 (CMPx_CR1)....................................................................................................... 789 34.2.3 CMP Filter Period Register (CMPx_FPR)...................................................................................................791 34.2.4 CMP Status and Control Register (CMPx_SCR).........................................................................................791 34.2.5 DAC Control Register (CMPx_DACCR).................................................................................................... 792 34.2.6 MUX Control Register (CMPx_MUXCR).................................................................................................. 793 Functional description...................................................................................................................................................794 KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 27 Section number Title Page 34.3.1 CMP functional modes.................................................................................................................................794 34.3.2 Power modes................................................................................................................................................ 803 34.3.3 Startup and operation................................................................................................................................... 804 34.3.4 Low-pass filter............................................................................................................................................. 805 34.4 CMP interrupts..............................................................................................................................................................807 34.5 DMA support................................................................................................................................................................ 807 34.6 CMP Asynchronous DMA support...............................................................................................................................808 34.7 Digital-to-analog converter...........................................................................................................................................809 34.8 DAC functional description.......................................................................................................................................... 809 34.8.1 34.9 Voltage reference source select....................................................................................................................809 DAC resets.................................................................................................................................................................... 810 34.10 DAC clocks...................................................................................................................................................................810 34.11 DAC interrupts..............................................................................................................................................................810 Chapter 35 12-bit Digital-to-Analog Converter (DAC) 35.1 Introduction...................................................................................................................................................................811 35.2 Features......................................................................................................................................................................... 811 35.3 Block diagram...............................................................................................................................................................811 35.4 Memory map/register definition................................................................................................................................... 812 35.5 35.4.1 DAC Data Low Register (DACx_DATnL)................................................................................................. 815 35.4.2 DAC Data High Register (DACx_DATnH)................................................................................................ 815 35.4.3 DAC Status Register (DACx_SR)............................................................................................................... 816 35.4.4 DAC Control Register (DACx_C0)............................................................................................................. 817 35.4.5 DAC Control Register 1 (DACx_C1).......................................................................................................... 818 35.4.6 DAC Control Register 2 (DACx_C2).......................................................................................................... 819 Functional description...................................................................................................................................................819 35.5.1 DAC data buffer operation...........................................................................................................................819 35.5.2 DMA operation............................................................................................................................................ 821 35.5.3 Resets........................................................................................................................................................... 821 KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 28 Freescale Semiconductor, Inc. Section number 35.5.4 Title Page Low-Power mode operation.........................................................................................................................821 Chapter 36 Voltage Reference (VREFV1) 36.1 36.2 36.3 36.4 Introduction...................................................................................................................................................................823 36.1.1 Overview...................................................................................................................................................... 824 36.1.2 Features........................................................................................................................................................ 824 36.1.3 Modes of Operation..................................................................................................................................... 825 36.1.4 VREF Signal Descriptions........................................................................................................................... 825 Memory Map and Register Definition..........................................................................................................................826 36.2.1 VREF Trim Register (VREF_TRM)............................................................................................................826 36.2.2 VREF Status and Control Register (VREF_SC)..........................................................................................827 Functional Description..................................................................................................................................................828 36.3.1 Voltage Reference Disabled, SC[VREFEN] = 0......................................................................................... 829 36.3.2 Voltage Reference Enabled, SC[VREFEN] = 1.......................................................................................... 829 36.3.3 Internal voltage regulator............................................................................................................................. 830 Initialization/Application Information.......................................................................................................................... 831 Chapter 37 Programmable Delay Block (PDB) 37.1 Introduction...................................................................................................................................................................833 37.1.1 Features........................................................................................................................................................ 833 37.1.2 Implementation............................................................................................................................................ 834 37.1.3 Back-to-back acknowledgment connections................................................................................................835 37.1.4 DAC External Trigger Input Connections................................................................................................... 835 37.1.5 Block diagram.............................................................................................................................................. 835 37.1.6 Modes of operation...................................................................................................................................... 837 37.2 PDB signal descriptions................................................................................................................................................837 37.3 Memory map and register definition.............................................................................................................................837 37.3.1 Status and Control register (PDBx_SC).......................................................................................................839 37.3.2 Modulus register (PDBx_MOD).................................................................................................................. 842 KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 29 Section number 37.4 37.5 Title Page 37.3.3 Counter register (PDBx_CNT).....................................................................................................................842 37.3.4 Interrupt Delay register (PDBx_IDLY)....................................................................................................... 843 37.3.5 Channel n Control register 1 (PDBx_CHnC1).............................................................................................843 37.3.6 Channel n Status register (PDBx_CHnS).....................................................................................................844 37.3.7 Channel n Delay 0 register (PDBx_CHnDLY0)..........................................................................................845 37.3.8 Channel n Delay 1 register (PDBx_CHnDLY1)..........................................................................................846 37.3.9 DAC Interval Trigger n Control register (PDBx_DACINTCn)...................................................................846 37.3.10 DAC Interval n register (PDBx_DACINTn)............................................................................................... 847 37.3.11 Pulse-Out n Enable register (PDBx_POEN)................................................................................................ 848 37.3.12 Pulse-Out n Delay register (PDBx_POnDLY).............................................................................................848 Functional description...................................................................................................................................................849 37.4.1 PDB pre-trigger and trigger outputs.............................................................................................................849 37.4.2 PDB trigger input source selection.............................................................................................................. 851 37.4.3 Pulse-Out's................................................................................................................................................... 851 37.4.4 Updating the delay registers.........................................................................................................................852 37.4.5 Interrupts...................................................................................................................................................... 854 37.4.6 DMA............................................................................................................................................................ 854 Application information................................................................................................................................................854 37.5.1 Impact of using the prescaler and multiplication factor on timing resolution............................................. 854 Chapter 38 FlexTimer Module (FTM) 38.1 Introduction...................................................................................................................................................................857 38.1.1 FlexTimer philosophy.................................................................................................................................. 857 38.1.2 Features........................................................................................................................................................ 858 38.1.3 Modes of operation...................................................................................................................................... 859 38.1.4 Block diagram.............................................................................................................................................. 860 38.2 FTM signal descriptions............................................................................................................................................... 862 38.3 Memory map and register definition.............................................................................................................................862 38.3.1 Memory map................................................................................................................................................ 862 KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 30 Freescale Semiconductor, Inc. Section number 38.4 Title Page 38.3.2 Register descriptions.................................................................................................................................... 863 38.3.3 Status And Control (FTMx_SC).................................................................................................................. 869 38.3.4 Counter (FTMx_CNT)................................................................................................................................. 870 38.3.5 Modulo (FTMx_MOD)................................................................................................................................ 871 38.3.6 Channel (n) Status And Control (FTMx_CnSC)..........................................................................................872 38.3.7 Channel (n) Value (FTMx_CnV)................................................................................................................. 875 38.3.8 Counter Initial Value (FTMx_CNTIN)........................................................................................................875 38.3.9 Capture And Compare Status (FTMx_STATUS)........................................................................................ 876 38.3.10 Features Mode Selection (FTMx_MODE).................................................................................................. 878 38.3.11 Synchronization (FTMx_SYNC)................................................................................................................. 880 38.3.12 Initial State For Channels Output (FTMx_OUTINIT).................................................................................882 38.3.13 Output Mask (FTMx_OUTMASK)............................................................................................................. 883 38.3.14 Function For Linked Channels (FTMx_COMBINE)...................................................................................885 38.3.15 Deadtime Insertion Control (FTMx_DEADTIME)..................................................................................... 890 38.3.16 FTM External Trigger (FTMx_EXTTRIG)................................................................................................. 891 38.3.17 Channels Polarity (FTMx_POL).................................................................................................................. 893 38.3.18 Fault Mode Status (FTMx_FMS).................................................................................................................895 38.3.19 Input Capture Filter Control (FTMx_FILTER)........................................................................................... 897 38.3.20 Fault Control (FTMx_FLTCTRL)............................................................................................................... 898 38.3.21 Quadrature Decoder Control And Status (FTMx_QDCTRL)......................................................................901 38.3.22 Configuration (FTMx_CONF)..................................................................................................................... 903 38.3.23 FTM Fault Input Polarity (FTMx_FLTPOL)...............................................................................................904 38.3.24 Synchronization Configuration (FTMx_SYNCONF)..................................................................................905 38.3.25 FTM Inverting Control (FTMx_INVCTRL)................................................................................................907 38.3.26 FTM Software Output Control (FTMx_SWOCTRL).................................................................................. 908 38.3.27 FTM PWM Load (FTMx_PWMLOAD)..................................................................................................... 911 Functional description...................................................................................................................................................912 38.4.1 Clock source.................................................................................................................................................913 38.4.2 Prescaler....................................................................................................................................................... 914 KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 31 Section number Title Page 38.4.3 Counter.........................................................................................................................................................914 38.4.4 Input Capture mode......................................................................................................................................920 38.4.5 Output Compare mode................................................................................................................................. 924 38.4.6 Edge-Aligned PWM (EPWM) mode........................................................................................................... 925 38.4.7 Center-Aligned PWM (CPWM) mode........................................................................................................ 927 38.4.8 Combine mode............................................................................................................................................. 929 38.4.9 Complementary mode.................................................................................................................................. 936 38.4.10 Registers updated from write buffers...........................................................................................................937 38.4.11 PWM synchronization..................................................................................................................................939 38.4.12 Inverting....................................................................................................................................................... 955 38.4.13 Software output control................................................................................................................................956 38.4.14 Deadtime insertion....................................................................................................................................... 958 38.4.15 Output mask................................................................................................................................................. 961 38.4.16 Fault control................................................................................................................................................. 961 38.4.17 Polarity control.............................................................................................................................................965 38.4.18 Initialization................................................................................................................................................. 966 38.4.19 Features priority........................................................................................................................................... 966 38.4.20 Channel trigger output................................................................................................................................. 967 38.4.21 Initialization trigger......................................................................................................................................968 38.4.22 Capture Test mode....................................................................................................................................... 971 38.4.23 DMA............................................................................................................................................................ 971 38.4.24 Dual Edge Capture mode............................................................................................................................. 972 38.4.25 Quadrature Decoder mode........................................................................................................................... 980 38.4.26 BDM mode...................................................................................................................................................985 38.4.27 Intermediate load..........................................................................................................................................986 38.4.28 Global time base (GTB)............................................................................................................................... 988 38.5 Reset overview..............................................................................................................................................................990 38.6 FTM Interrupts..............................................................................................................................................................991 38.6.1 Timer Overflow Interrupt.............................................................................................................................992 KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 32 Freescale Semiconductor, Inc. Section number 38.7 Title Page 38.6.2 Channel (n) Interrupt....................................................................................................................................992 38.6.3 Fault Interrupt.............................................................................................................................................. 992 Initialization Procedure.................................................................................................................................................992 Chapter 39 Periodic Interrupt Timer (PIT) 39.1 Introduction...................................................................................................................................................................995 39.1.1 Block diagram.............................................................................................................................................. 995 39.1.2 Features........................................................................................................................................................ 996 39.2 Signal description..........................................................................................................................................................996 39.3 Memory map/register description................................................................................................................................. 997 39.4 39.3.1 PIT Module Control Register (PIT_MCR).................................................................................................. 997 39.3.2 Timer Load Value Register (PIT_LDVALn)...............................................................................................999 39.3.3 Current Timer Value Register (PIT_CVALn)............................................................................................. 999 39.3.4 Timer Control Register (PIT_TCTRLn)...................................................................................................... 1000 39.3.5 Timer Flag Register (PIT_TFLGn)..............................................................................................................1000 Functional description...................................................................................................................................................1001 39.4.1 General operation......................................................................................................................................... 1001 39.4.2 Interrupts...................................................................................................................................................... 1003 39.4.3 Chained timers............................................................................................................................................. 1003 39.5 Initialization and application information.....................................................................................................................1003 39.6 Example configuration for chained timers....................................................................................................................1004 Chapter 40 Low-Power Timer (LPTMR) 40.1 40.2 Introduction...................................................................................................................................................................1007 40.1.1 Features........................................................................................................................................................ 1007 40.1.2 Modes of operation...................................................................................................................................... 1007 LPTMR signal descriptions.......................................................................................................................................... 1008 40.2.1 40.3 Detailed signal descriptions......................................................................................................................... 1008 Memory map and register definition.............................................................................................................................1008 KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 33 Section number 40.4 Title Page 40.3.1 Low Power Timer Control Status Register (LPTMRx_CSR)......................................................................1009 40.3.2 Low Power Timer Prescale Register (LPTMRx_PSR)................................................................................1010 40.3.3 Low Power Timer Compare Register (LPTMRx_CMR).............................................................................1012 40.3.4 Low Power Timer Counter Register (LPTMRx_CNR)............................................................................... 1012 Functional description...................................................................................................................................................1013 40.4.1 LPTMR power and reset.............................................................................................................................. 1013 40.4.2 LPTMR clocking..........................................................................................................................................1013 40.4.3 LPTMR prescaler/glitch filter...................................................................................................................... 1013 40.4.4 LPTMR compare..........................................................................................................................................1015 40.4.5 LPTMR counter........................................................................................................................................... 1015 40.4.6 LPTMR hardware trigger.............................................................................................................................1016 40.4.7 LPTMR interrupt..........................................................................................................................................1016 Chapter 41 Serial Peripheral Interface (SPI) 41.1 41.2 41.3 Introduction...................................................................................................................................................................1017 41.1.1 Block Diagram............................................................................................................................................. 1017 41.1.2 Features........................................................................................................................................................ 1018 41.1.3 Interface configurations............................................................................................................................... 1020 41.1.4 Modes of Operation..................................................................................................................................... 1020 Module signal descriptions........................................................................................................................................... 1022 41.2.1 PCS0/SS--Peripheral Chip Select/Slave Select.......................................................................................... 1022 41.2.2 PCS1-PCS3--Peripheral Chip Selects 1-3................................................................................................. 1023 41.2.3 PCS4--Peripheral Chip Select 4..................................................................................................................1023 41.2.4 PCS5/PCSS--Peripheral Chip Select 5/Peripheral Chip Select Strobe.......................................................1023 41.2.5 SCK--Serial Clock...................................................................................................................................... 1023 41.2.6 SIN--Serial Input........................................................................................................................................ 1023 41.2.7 SOUT--Serial Output..................................................................................................................................1024 Memory Map/Register Definition.................................................................................................................................1024 41.3.1 Module Configuration Register (SPIx_MCR)............................................................................................. 1026 KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 34 Freescale Semiconductor, Inc. Section number 41.4 41.5 Title Page 41.3.2 Transfer Count Register (SPIx_TCR).......................................................................................................... 1029 41.3.3 Clock and Transfer Attributes Register (In Master Mode) (SPIx_CTARn)................................................ 1030 41.3.4 Clock and Transfer Attributes Register (In Slave Mode) (SPIx_CTARn_SLAVE)................................... 1034 41.3.5 Status Register (SPIx_SR)........................................................................................................................... 1036 41.3.6 DMA/Interrupt Request Select and Enable Register (SPIx_RSER)............................................................ 1039 41.3.7 PUSH TX FIFO Register In Master Mode (SPIx_PUSHR)........................................................................ 1041 41.3.8 PUSH TX FIFO Register In Slave Mode (SPIx_PUSHR_SLAVE)............................................................1043 41.3.9 POP RX FIFO Register (SPIx_POPR).........................................................................................................1043 41.3.10 Transmit FIFO Registers (SPIx_TXFRn).................................................................................................... 1044 41.3.11 Receive FIFO Registers (SPIx_RXFRn)......................................................................................................1044 Functional description...................................................................................................................................................1045 41.4.1 Start and Stop of module transfers............................................................................................................... 1046 41.4.2 Serial Peripheral Interface (SPI) configuration............................................................................................1046 41.4.3 Module baud rate and clock delay generation............................................................................................. 1050 41.4.4 Transfer formats........................................................................................................................................... 1054 41.4.5 Continuous Serial Communications Clock.................................................................................................. 1063 41.4.6 Slave Mode Operation Constraints.............................................................................................................. 1065 41.4.7 Interrupts/DMA requests..............................................................................................................................1065 41.4.8 Power saving features.................................................................................................................................. 1067 Initialization/application information........................................................................................................................... 1068 41.5.1 How to manage queues................................................................................................................................ 1069 41.5.2 Switching Master and Slave mode...............................................................................................................1069 41.5.3 Initializing Module in Master/Slave Modes.................................................................................................1070 41.5.4 Baud rate settings......................................................................................................................................... 1070 41.5.5 Delay settings............................................................................................................................................... 1071 41.5.6 Calculation of FIFO pointer addresses.........................................................................................................1072 Chapter 42 Inter-Integrated Circuit (I2C) 42.1 Introduction...................................................................................................................................................................1075 KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 35 Section number Title Page 42.1.1 Features........................................................................................................................................................ 1075 42.1.2 Modes of operation...................................................................................................................................... 1076 42.1.3 Block diagram.............................................................................................................................................. 1076 42.2 I2C signal descriptions..................................................................................................................................................1077 42.3 Memory map/register definition................................................................................................................................... 1078 42.4 42.5 42.3.1 I2C Address Register 1 (I2Cx_A1).............................................................................................................. 1079 42.3.2 I2C Frequency Divider register (I2Cx_F).................................................................................................... 1079 42.3.3 I2C Control Register 1 (I2Cx_C1)............................................................................................................... 1080 42.3.4 I2C Status register (I2Cx_S)........................................................................................................................ 1082 42.3.5 I2C Data I/O register (I2Cx_D)................................................................................................................... 1084 42.3.6 I2C Control Register 2 (I2Cx_C2)............................................................................................................... 1084 42.3.7 I2C Programmable Input Glitch Filter Register (I2Cx_FLT)...................................................................... 1085 42.3.8 I2C Range Address register (I2Cx_RA)...................................................................................................... 1087 42.3.9 I2C SMBus Control and Status register (I2Cx_SMB)................................................................................. 1087 42.3.10 I2C Address Register 2 (I2Cx_A2).............................................................................................................. 1089 42.3.11 I2C SCL Low Timeout Register High (I2Cx_SLTH)..................................................................................1089 42.3.12 I2C SCL Low Timeout Register Low (I2Cx_SLTL)...................................................................................1090 Functional description...................................................................................................................................................1090 42.4.1 I2C protocol................................................................................................................................................. 1090 42.4.2 10-bit address............................................................................................................................................... 1095 42.4.3 Address matching.........................................................................................................................................1097 42.4.4 System management bus specification........................................................................................................ 1098 42.4.5 Resets........................................................................................................................................................... 1100 42.4.6 Interrupts...................................................................................................................................................... 1100 42.4.7 Programmable input glitch filter.................................................................................................................. 1103 42.4.8 Address matching wake-up.......................................................................................................................... 1103 42.4.9 DMA support............................................................................................................................................... 1104 Initialization/application information........................................................................................................................... 1105 Chapter 43 KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 36 Freescale Semiconductor, Inc. Section number Title Page Universal Asynchronous Receiver/Transmitter (UART) 43.1 43.2 Introduction...................................................................................................................................................................1109 43.1.1 Features........................................................................................................................................................ 1109 43.1.2 Modes of operation...................................................................................................................................... 1111 UART signal descriptions.............................................................................................................................................1112 43.2.1 43.3 Detailed signal descriptions......................................................................................................................... 1112 Memory map and registers............................................................................................................................................1113 43.3.1 UART Baud Rate Registers: High (UARTx_BDH).................................................................................... 1118 43.3.2 UART Baud Rate Registers: Low (UARTx_BDL)..................................................................................... 1119 43.3.3 UART Control Register 1 (UARTx_C1)..................................................................................................... 1120 43.3.4 UART Control Register 2 (UARTx_C2)..................................................................................................... 1121 43.3.5 UART Status Register 1 (UARTx_S1)........................................................................................................ 1123 43.3.6 UART Status Register 2 (UARTx_S2)........................................................................................................ 1126 43.3.7 UART Control Register 3 (UARTx_C3)..................................................................................................... 1128 43.3.8 UART Data Register (UARTx_D)...............................................................................................................1129 43.3.9 UART Match Address Registers 1 (UARTx_MA1)....................................................................................1130 43.3.10 UART Match Address Registers 2 (UARTx_MA2)....................................................................................1131 43.3.11 UART Control Register 4 (UARTx_C4)..................................................................................................... 1131 43.3.12 UART Control Register 5 (UARTx_C5)..................................................................................................... 1132 43.3.13 UART Extended Data Register (UARTx_ED)............................................................................................ 1133 43.3.14 UART Modem Register (UARTx_MODEM)............................................................................................. 1134 43.3.15 UART Infrared Register (UARTx_IR)........................................................................................................ 1135 43.3.16 UART FIFO Parameters (UARTx_PFIFO)................................................................................................. 1136 43.3.17 UART FIFO Control Register (UARTx_CFIFO)........................................................................................ 1137 43.3.18 UART FIFO Status Register (UARTx_SFIFO)...........................................................................................1138 43.3.19 UART FIFO Transmit Watermark (UARTx_TWFIFO)............................................................................. 1139 43.3.20 UART FIFO Transmit Count (UARTx_TCFIFO).......................................................................................1140 43.3.21 UART FIFO Receive Watermark (UARTx_RWFIFO)...............................................................................1140 43.3.22 UART FIFO Receive Count (UARTx_RCFIFO)........................................................................................ 1141 KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 37 Section number 43.4 Title Page 43.3.23 UART 7816 Control Register (UARTx_C7816)......................................................................................... 1141 43.3.24 UART 7816 Interrupt Enable Register (UARTx_IE7816).......................................................................... 1143 43.3.25 UART 7816 Interrupt Status Register (UARTx_IS7816)............................................................................1144 43.3.26 UART 7816 Wait Parameter Register (UARTx_WP7816)......................................................................... 1146 43.3.27 UART 7816 Wait N Register (UARTx_WN7816)......................................................................................1146 43.3.28 UART 7816 Wait FD Register (UARTx_WF7816).................................................................................... 1147 43.3.29 UART 7816 Error Threshold Register (UARTx_ET7816)..........................................................................1147 43.3.30 UART 7816 Transmit Length Register (UARTx_TL7816)........................................................................ 1148 43.3.31 UART 7816 ATR Duration Timer Register A (UARTx_AP7816A_T0)....................................................1148 43.3.32 UART 7816 ATR Duration Timer Register B (UARTx_AP7816B_T0).................................................... 1149 43.3.33 UART 7816 Wait Parameter Register A (UARTx_WP7816A_T0)............................................................ 1150 43.3.34 UART 7816 Wait Parameter Register A (UARTx_WP7816A_T1)............................................................ 1150 43.3.35 UART 7816 Wait Parameter Register B (UARTx_WP7816B_T0)............................................................ 1151 43.3.36 UART 7816 Wait Parameter Register B (UARTx_WP7816B_T1)............................................................ 1151 43.3.37 UART 7816 Wait and Guard Parameter Register (UARTx_WGP7816_T1).............................................. 1152 43.3.38 UART 7816 Wait Parameter Register C (UARTx_WP7816C_T1)............................................................ 1152 Functional description...................................................................................................................................................1153 43.4.1 Transmitter................................................................................................................................................... 1153 43.4.2 Receiver....................................................................................................................................................... 1159 43.4.3 Baud rate generation.................................................................................................................................... 1173 43.4.4 Data format (non ISO-7816)........................................................................................................................ 1175 43.4.5 Single-wire operation................................................................................................................................... 1178 43.4.6 Loop operation............................................................................................................................................. 1179 43.4.7 ISO-7816/smartcard support........................................................................................................................ 1179 43.4.8 Infrared interface..........................................................................................................................................1184 43.5 Reset..............................................................................................................................................................................1186 43.6 System level interrupt sources...................................................................................................................................... 1186 43.6.1 43.7 RXEDGIF description..................................................................................................................................1186 DMA operation............................................................................................................................................................. 1187 KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 38 Freescale Semiconductor, Inc. Section number 43.8 Title Page Application information................................................................................................................................................1188 43.8.1 Transmit/receive data buffer operation........................................................................................................ 1188 43.8.2 ISO-7816 initialization sequence................................................................................................................. 1188 43.8.3 Initialization sequence (non ISO-7816)....................................................................................................... 1190 43.8.4 Overrun (OR) flag implications................................................................................................................... 1191 43.8.5 Overrun NACK considerations.................................................................................................................... 1192 43.8.6 Match address registers................................................................................................................................ 1193 43.8.7 Modem feature............................................................................................................................................. 1193 43.8.8 IrDA minimum pulse width......................................................................................................................... 1194 43.8.9 Clearing 7816 wait timer (WT, BWT, CWT) interrupts..............................................................................1194 43.8.10 Legacy and reverse compatibility considerations........................................................................................ 1195 Chapter 44 Low Power Universal Asynchronous Receiver/Transmitter (LPUART) 44.1 44.2 44.3 Introduction...................................................................................................................................................................1197 44.1.1 Features........................................................................................................................................................ 1197 44.1.2 Modes of operation...................................................................................................................................... 1198 44.1.3 Signal Descriptions...................................................................................................................................... 1198 44.1.4 Block diagram.............................................................................................................................................. 1199 Register definition.........................................................................................................................................................1200 44.2.1 LPUART Baud Rate Register (LPUARTx_BAUD)....................................................................................1201 44.2.2 LPUART Status Register (LPUARTx_STAT)............................................................................................ 1203 44.2.3 LPUART Control Register (LPUARTx_CTRL)......................................................................................... 1207 44.2.4 LPUART Data Register (LPUARTx_DATA)............................................................................................. 1212 44.2.5 LPUART Match Address Register (LPUARTx_MATCH)......................................................................... 1214 44.2.6 LPUART Modem IrDA Register (LPUARTx_MODIR).............................................................................1214 Functional description...................................................................................................................................................1216 44.3.1 Baud rate generation.................................................................................................................................... 1216 44.3.2 Transmitter functional description............................................................................................................... 1217 44.3.3 Receiver functional description................................................................................................................... 1220 KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 39 Section number Title Page 44.3.4 Additional LPUART functions.................................................................................................................... 1226 44.3.5 Infrared interface..........................................................................................................................................1228 44.3.6 Interrupts and status flags............................................................................................................................ 1229 Chapter 45 General-Purpose Input/Output (GPIO) 45.1 45.2 45.3 Introduction...................................................................................................................................................................1231 45.1.1 Features........................................................................................................................................................ 1231 45.1.2 Modes of operation...................................................................................................................................... 1231 45.1.3 GPIO signal descriptions............................................................................................................................. 1232 Memory map and register definition.............................................................................................................................1233 45.2.1 Port Data Output Register (GPIOx_PDOR).................................................................................................1234 45.2.2 Port Set Output Register (GPIOx_PSOR)....................................................................................................1235 45.2.3 Port Clear Output Register (GPIOx_PCOR)................................................................................................1236 45.2.4 Port Toggle Output Register (GPIOx_PTOR)............................................................................................. 1236 45.2.5 Port Data Input Register (GPIOx_PDIR).....................................................................................................1237 45.2.6 Port Data Direction Register (GPIOx_PDDR).............................................................................................1237 Functional description...................................................................................................................................................1238 45.3.1 General-purpose input..................................................................................................................................1238 45.3.2 General-purpose output................................................................................................................................1238 Chapter 46 JTAG Controller (JTAGC) 46.1 46.2 Introduction...................................................................................................................................................................1239 46.1.1 Block diagram.............................................................................................................................................. 1239 46.1.2 Features........................................................................................................................................................ 1240 46.1.3 Modes of operation...................................................................................................................................... 1240 External signal description............................................................................................................................................1242 46.2.1 TCK--Test clock input................................................................................................................................ 1242 46.2.2 TDI--Test data input................................................................................................................................... 1242 46.2.3 TDO--Test data output................................................................................................................................1242 KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 40 Freescale Semiconductor, Inc. Section number 46.2.4 46.3 46.4 46.5 Title Page TMS--Test mode select...............................................................................................................................1242 Register description...................................................................................................................................................... 1243 46.3.1 Instruction register....................................................................................................................................... 1243 46.3.2 Bypass register............................................................................................................................................. 1243 46.3.3 Device identification register....................................................................................................................... 1243 46.3.4 Boundary scan register.................................................................................................................................1244 Functional description...................................................................................................................................................1245 46.4.1 JTAGC reset configuration.......................................................................................................................... 1245 46.4.2 IEEE 1149.1-2001 (JTAG) Test Access Port.............................................................................................. 1245 46.4.3 TAP controller state machine.......................................................................................................................1245 46.4.4 JTAGC block instructions............................................................................................................................1247 46.4.5 Boundary scan..............................................................................................................................................1250 Initialization/Application information.......................................................................................................................... 1250 KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 41 KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 42 Freescale Semiconductor, Inc. Chapter 1 About This Document 1.1 Overview 1.1.1 Purpose This document describes the features, architecture, and programming model of the microcontroller. 1.1.2 Audience This document is intended for system architects and software application developers who are using (or considering using) the microcontroller in a system. 1.2 Conventions 1.2.1 Numbering systems The following suffixes identify different numbering systems: This suffix Identifies a b Binary number. For example, the binary equivalent of the number 5 is written 101b. In some cases, binary numbers are shown with the prefix 0b. d Decimal number. Decimal numbers are followed by this suffix only when the possibility of confusion exists. In general, decimal numbers are shown without a suffix. h Hexadecimal number. For example, the hexadecimal equivalent of the number 60 is written 3Ch. In some cases, hexadecimal numbers are shown with the prefix 0x. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 43 Conventions 1.2.2 Typographic notation The following typographic notation is used throughout this document: Example Description placeholder, x Items in italics are placeholders for information that you provide. Italicized text is also used for the titles of publications and for emphasis. Plain lowercase letters are also used as placeholders for single letters and numbers. code Fixed-width type indicates text that must be typed exactly as shown. It is used for instruction mnemonics, directives, symbols, subcommands, parameters, and operators. Fixed-width type is also used for example code. Instruction mnemonics and directives in text and tables are shown in all caps; for example, BSR. SR[SCM] A mnemonic in brackets represents a named field in a register. This example refers to the Scaling Mode (SCM) field in the Status Register (SR). REVNO[6:4], XAD[7:0] Numbers in brackets and separated by a colon represent either: * A subset of a register's named field For example, REVNO[6:4] refers to bits 6-4 that are part of the COREREV field that occupies bits 6-0 of the REVNO register. * A continuous range of individual signals of a bus For example, XAD[7:0] refers to signals 7-0 of the XAD bus. 1.2.3 Special terms The following terms have special meanings: Term Meaning asserted Refers to the state of a signal as follows: * An active-high signal is asserted when high (1). * An active-low signal is asserted when low (0). deasserted Refers to the state of a signal as follows: * An active-high signal is deasserted when low (0). * An active-low signal is deasserted when high (1). In some cases, deasserted signals are described as negated. reserved Refers to a memory space, register, or field that is either reserved for future use or for which, when written to, the module or chip behavior is unpredictable. w1c Write 1 to clear: Refers to a register bitfield that must be written as 1 to be "cleared." KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 44 Freescale Semiconductor, Inc. Chapter 2 Introduction 2.1 Overview This chapter provides high-level descriptions of the modules available on the devices covered by this document. 2.2 Module Functional Categories The modules on this device are grouped into functional categories. The following sections describe the modules assigned to each category in more detail. Table 2-1. Module functional categories Module category Description ARM(R) Cortex(R)-M4 core * 32-bit MCU core from ARM's Cortex-M class adding DSP instructions and single-precision floating point unit based on ARMv7 architecture System * System integration module * Power management and mode controllers * Multiple power modes available based on high speed run, run, wait, stop, and power-down modes * Low-leakage wakeup unit * Miscellaneous control module * Crossbar switch * Peripheral bridge * Direct memory access (DMA) controller with multiplexer to increase available DMA requests. * External watchdog monitor * Watchdog Memories * Internal memories include: * Program flash memory * SRAM * External memory or peripheral bus interface: FlexBus * Serial programming interface: EzPort Clocks * Multiple clock generation options available from internally- and externallygenerated clocks * System oscillator to provide clock source for the MCU Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 45 Module Functional Categories Table 2-1. Module functional categories (continued) Module category Description Security * Cyclic Redundancy Check module for error detection Analog * * * * * High speed analog-to-digital converter Comparator Digital-to-analog converter Internal voltage reference Bandgap voltage reference Timers * * * * Programmable delay block FlexTimers Periodic interrupt timer Low power timer Communications * * * * Serial peripheral interface Inter-integrated circuit (I2C) UART Low-power UART (LPUART) Human-Machine Interfaces (HMI) * General purpose input/output controller Kinetis Motor Suite (KMS) * Kinetis Motor Suite (KMS) is a bundled hardware and software solution that enables rapid configuration of motor drive systems and accelerating application development. For more information refer to Kinetis Motor Suite API Reference Manual (KMS100RM)1 and Kinetis Motor Suite User's Guide (KMS100UG), 1 1. To find the associated resource, go to http://www.freescale.com and perform a search using Document ID. 2.2.1 ARM(R) Cortex(R)-M4 Core Modules The following core modules are available on this device. Table 2-2. Core modules Module Description ARM Cortex-M4 The ARM(R) Cortex(R)-M4 is the newest member of the Cortex M Series of processors targeting microcontroller cores focused on very cost sensitive, deterministic, interrupt driven environments. The Cortex M4 processor is based on the ARMv7 Architecture and Thumb(R)-2 ISA and is upward compatible with the Cortex M3, Cortex M1, and Cortex M0 architectures. Cortex M4 improvements include an ARMv7 Thumb-2 DSP (ported from the ARMv7-A/R profile architectures) providing 32-bit instructions with SIMD (single instruction multiple data) DSP style multiply-accumulates and saturating arithmetic. Floating point unit (FPU) A single-precision floating point unit (FPU) that is compliant to the IEEE Standard for Floating-Point Arithmetic (IEEE 754). NVIC The ARMv7-M exception model and nested-vectored interrupt controller (NVIC) implement a relocatable vector table supporting many external interrupts, a single non-maskable interrupt (NMI), and priority levels. The NVIC replaces shadow registers with equivalent system and simplified programmability. The NVIC contains the address of the function to execute for a particular handler. The address is fetched via the instruction port allowing parallel register stacking and look-up. The first sixteen entries are allocated to ARM internal sources with the others mapping to MCU-defined interrupts. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 46 Freescale Semiconductor, Inc. Chapter 2 Introduction Table 2-2. Core modules (continued) Module Description AWIC The primary function of the Asynchronous Wake-up Interrupt Controller (AWIC) is to detect asynchronous wake-up events in stop modes and signal to clock control logic to resume system clocking. After clock restart, the NVIC observes the pending interrupt and performs the normal interrupt or event processing. Debug interfaces Most of this device's debug is based on the ARM CoreSightTM architecture. Four debug interfaces are supported: * * * * IEEE 1149.1 JTAG IEEE 1149.7 JTAG (cJTAG) Serial Wire Debug (SWD) ARM Real-Time Trace Interface 2.2.2 System Modules The following system modules are available on this device. Table 2-3. System modules Module Description System integration module (SIM) The SIM includes integration logic and several module configuration settings. System mode controller The SMC provides control and protection on entry and exit to each power mode, control for the Power management controller (PMC), and reset entry and exit for the complete MCU. Power management controller (PMC) The PMC provides the user with multiple power options that allow the user to optimize power consumption for the level of functionality needed. Includes poweron-reset (POR) and integrated low voltage detect (LVD) with reset (brownout) capability and selectable LVD trip points. Low-leakage wakeup unit (LLWU) The LLWU module allows the device to wake from low leakage power modes (LLS and VLLS) through various internal peripheral and external pin sources. Miscellaneous control module (MCM) The MCM includes integration logic Crossbar switch (XBS) The XBS connects bus masters and bus slaves, allowing all bus masters to access different bus slaves simultaneously and providing arbitration among the bus masters when they access the same slave. Peripheral bridges The peripheral bridge converts the crossbar switch interface to an interface to access a majority of peripherals on the device. DMA multiplexer (DMAMUX) The DMA multiplexer selects from many DMA requests down to a smaller number for the DMA controller. Direct memory access (DMA) controller The DMA controller provides programmable channels with transfer control descriptors for data movement via dual-address transfers for 8-bit, 16-bit, 32-bit, 16-byte and 32-byte data values. External watchdog monitor (EWM) The EWM is a redundant mechanism to the software watchdog module that monitors both internal and external system operation for fail conditions. Software watchdog (WDOG) The WDOG monitors internal system operation and forces a reset in case of failure. It can run from an independent 1 KHz low power oscillator with a programmable refresh window to detect deviations in program flow or system frequency. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 47 Module Functional Categories 2.2.3 Memories and Memory Interfaces The following memories and memory interfaces are available on this device. Table 2-4. Memories and memory interfaces Module Description Flash memory * Program flash memory -- non-volatile flash memory that can execute program code Flash memory controller Manages the interface between the device and the on-chip flash memory. SRAM Internal system RAM. Partial SRAM kept powered in LLS2 and VLLS2 low leakage mode. System register file 32-byte register file that is accessible during all power modes and is powered by VDD. Serial programming interface (EzPort) Same serial interface as, and subset of, the command set used by industrystandard SPI flash memories. Provides the ability to read, erase, and program flash memory and reset command to boot the system after flash programming. FlexBus External bus interface with multiple independent, user-programmable chip-select signals that can interface with external SRAM, PROM, EPROM, EEPROM, flash, and other peripherals via 8-, 16- and 32-bit port sizes. Configurations include multiplexed or non-multiplexed address and data buses using 8-bit, 16-bit, 32-bit, and 16-byte line-sized transfers. 2.2.4 Clocks The following clock modules are available on this device. Table 2-5. Clock modules Module Description Multi-clock generator (MCG) The MCG provides several clock sources for the MCU that include: * Phase-locked loop (PLL) -- Voltage-controlled oscillator (VCO) * Frequency-locked loop (FLL) -- Digitally-controlled oscillator (DCO) * Internal reference clocks -- Can be used as a clock source for other on-chip peripherals 48 MHz Internal Reference Clock (IRC48M) The IRC48M provides an internally generated clock source. System oscillator The system oscillator, in conjunction with an external crystal or resonator, generates a reference clock for the MCU. 2.2.5 Security and Integrity modules The following security and integrity modules are available on this device: KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 48 Freescale Semiconductor, Inc. Chapter 2 Introduction Table 2-6. Security and integrity modules Module Description Random number generator (RNG) Supports the key generation algorithm defined in the Digital Signature Standard. Cyclic Redundancy Check (CRC) Hardware CRC generator circuit using 16/32-bit shift register. Error detection for all single, double, odd, and most multi-bit errors, programmable initial seed value, and optional feature to transpose input data and CRC result via transpose register. 2.2.6 Analog modules The following analog modules are available on this device: Table 2-7. Analog modules Module Description 16-bit analog-to-digital converters (ADC) 16-bit successive-approximation ADC Analog comparators Compares two analog input voltages across the full range of the supply voltage. 6-bit digital-to-analog converters (DAC) 64-tap resistor ladder network which provides a selectable voltage reference for applications where voltage reference is needed. 12-bit digital-to-analog converters (DAC) Low-power general-purpose DAC, whose output can be placed on an external pin or set as one of the inputs to the analog comparator or ADC. Voltage reference (VREF) Supplies an accurate voltage output that is trimmable in 0.5 mV steps. The VREF can be used in medical applications, such as glucose meters, to provide a reference voltage to biosensors or as a reference to analog peripherals, such as the ADC, DAC, or CMP. 2.2.7 Timer modules The following timer modules are available on this device: Table 2-8. Timer modules Module Description Programmable delay block (PDB) * * * * 16-bit resolution 3-bit prescaler Positive transition of trigger event signal initiates the counter Supports two triggered delay output signals, each with an independentlycontrolled delay from the trigger event * Outputs can be OR'd together to schedule two conversions from one input trigger event and can schedule precise edge placement for a pulsed output. This feature is used to generate the control signal for the CMP windowing feature and output to a package pin if needed for applications, such as critical conductive mode power factor correction. * Continuous-pulse output or single-shot mode supported, each output is independently enabled, with possible trigger events Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 49 Module Functional Categories Table 2-8. Timer modules (continued) Module Description * Supports bypass mode * Supports DMA Flexible timer modules (FTM) * Selectable FTM source clock, programmable prescaler * 16-bit counter supporting free-running or initial/final value, and counting is up or up-down * Input capture, output compare, and edge-aligned and center-aligned PWM modes * Operation of FTM channels as pairs with equal outputs, pairs with complimentary outputs, or independent channels with independent outputs * Deadtime insertion is available for each complementary pair * Generation of hardware triggers * Software control of PWM outputs * Up to 4 fault inputs for global fault control * Configurable channel polarity * Programmable interrupt on input capture, reference compare, overflowed counter, or detected fault condition * Quadrature decoder with input filters, relative position counting, and interrupt on position count or capture of position count on external event * DMA support for FTM events Periodic interrupt timers (PIT) * * * * Low-power timer (LPTimer) * Selectable clock for prescaler/glitch filter of 1 kHz (internal LPO), 32.768 kHz (external crystal), or internal reference clock * Configurable Glitch Filter or Prescaler with 16-bit counter * 16-bit time or pulse counter with compare * Interrupt generated on Timer Compare * Hardware trigger generated on Timer Compare Four general purpose interrupt timers Interrupt timers for triggering ADC conversions 32-bit counter resolution DMA support 2.2.8 Communication interfaces The following communication interfaces are available on this device: Table 2-9. Communication modules Module Description Serial peripheral interface (SPI) Synchronous serial bus for communication to an external device Inter-integrated circuit (I2C) Allows communication between a number of devices. Also supports the System Management Bus (SMBus) Specification, version 2. Universal asynchronous receiver/ transmitters (UART) Asynchronous serial bus communication interface with programmable 8- or 9-bit data format and support of ISO 7816 smart card interface LPUART Low power UART module that retains functionality in stop modes. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 50 Freescale Semiconductor, Inc. Chapter 2 Introduction 2.2.9 Human-machine interfaces The following human-machine interfaces (HMI) are available on this device: Table 2-10. HMI modules Module Description General purpose input/output (GPIO) All general purpose input or output (GPIO) pins are capable of interrupt and DMA request generation. 2.2.10 Kinetis Motor Suite A selection of KV3x devices are enabled with Kinetis Motor Suite (KMS). The supported devices are listed in Orderable Kinetis Motor Suite part numbers summary. KMS uses the top 8K of flash to store a KMS library file, and is protected using Flash Access Controls. This code space is execute only. For more information refer to Kinetis Motor Suite API Reference Manual (KMS100RM), 1 and Kinetis Motor Suite User's Guide (KMS100UG), 1. Table 2-11. KMS module Module Kinetis Motor Suite (KMS) Description KMS includes firmware preprogrammed on the Kinetis V3x series of microcontrollers and an intuitive PC-based graphical user interface. It supports field oriented control of three phase permanent magnet and brushless DC motors for sensorless velocity control and sensored position control. KMS part numbers for different motor types: * P suffix for sensorless or sensored FOC for velocity control of PMSM and BLDC motors 2.3 Orderable part numbers The following table summarizes the part numbers of the devices covered by this document. 1. To find the associated resource, go to http://www.freescale.com and perform a search using Document ID KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 51 Orderable part numbers Table 2-12. Orderable part numbers summary Part number CPU Pin count Package frequency Program flash SRAM GPIO MKV31F512VLL12 120 MHz 100 LQFP 512 KB 96 KB 70 MKV31F512VLH12 120 MHz 64 LQFP 512 KB 96 KB 46 Table 2-13. Orderable Kinetis Motor Suite part numbers summary Part number MKV31F512VLL12P Motor Type Pin count PMSM/BLDC 100 Package LQFP Flash available 504 KB 1 SRAM2 96 KB GPIO 70 1. Kinetis Motor Suite enabled devices have 8K bytes reserved flash space as execute only. See Kinetis Motor Suite Configuration section in Chapter 3 NOTE Do not do a mass erase of the flash since it will delete the entire flash contents including this KMS library KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 52 Freescale Semiconductor, Inc. Chapter 3 Chip Configuration 3.1 Introduction This chapter provides details on the individual modules of the microcontroller. It includes: * module block diagrams showing immediate connections within the device, * specific module-to-module interactions not necessarily discussed in the individual module chapters, and * links for more information. 3.2 Core modules 3.2.1 ARM Cortex-M4 Core Configuration This section summarizes how the module has been configured in the chip. Full documentation for this module is provided by ARM and can be found at arm.com. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 53 Core modules Debug Interrupts ARM Cortex-M4 Core Crossbar switch PPB PPB Modules Figure 3-1. Core configuration Table 3-1. Reference links to related information Topic Related module Reference Full description ARM Cortex-M4 core ARM Cortex-M4 Technical Reference Manual System memory map System memory map Clocking Clock distribution Power management Power management System/instruction/data bus module Crossbar switch Crossbar switch Debug IEEE 1149.1 JTAG Debug IEEE 1149.7 JTAG (cJTAG) Serial Wire Debug (SWD) ARM Real-Time Trace Interface Interrupts Nested Vectored Interrupt Controller (NVIC) NVIC Private Peripheral Bus (PPB) module Miscellaneous Control Module (MCM) MCM Private Peripheral Bus Single-precision floating (PPB) module point unit (FPU) FPU 3.2.1.1 Buses, interconnects, and interfaces The ARM Cortex-M4 core has four buses as described in the following table. Bus name Description Instruction code (ICODE) bus The ICODE and DCODE buses are muxed. This muxed bus is called the CODE bus and is connected to the crossbar switch via a single master port. Data code (DCODE) bus System bus The system bus is connected to a separate master port on the crossbar. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 54 Freescale Semiconductor, Inc. Chapter 3 Chip Configuration Bus name Private peripheral (PPB) bus Description The PPB provides access to these modules: * ARM modules such as the NVIC, ITM, DWT, FBP, and ROM table * Freescale Miscellaneous Control Module (MCM) 3.2.1.2 System Tick Timer The System Tick Timer's clock source is always the core clock, FCLK. This results in the following: * The CLKSOURCE bit in SysTick Control and Status register is always set to select the core clock. * Because the timing reference (FCLK) is a variable frequency, the TENMS bit in the SysTick Calibration Value Register is always zero. * The NOREF bit in SysTick Calibration Value Register is always set, implying that FCLK is the only available source of reference timing. 3.2.1.3 Debug facilities This device has extensive debug capabilities including run control and tracing capabilities. The standard ARM debug port that supports JTAG and SWD interfaces. Also the cJTAG interface is supported on this device. 3.2.1.4 Core privilege levels The ARM documentation uses different terms than this document to distinguish between privilege levels. If you see this term... it also means this term... Privileged Supervisor Unprivileged or user User 3.2.2 Nested Vectored Interrupt Controller (NVIC) Configuration This section summarizes how the module has been configured in the chip. Full documentation for this module is provided by ARM and can be found at arm.com. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 55 Core modules Interrupts ARM Cortex-M4 core Module Nested Vectored Interrupt Controller (NVIC) PPB Module Module Figure 3-2. NVIC configuration Table 3-2. Reference links to related information Topic Related module Reference Full description Nested Vectored Interrupt Controller (NVIC) ARM Cortex-M4 Technical Reference Manual System memory map System memory map Clocking Clock distribution Power management Power management Private Peripheral Bus (PPB) ARM Cortex-M4 core ARM Cortex-M4 core 3.2.2.1 Interrupt priority levels This device supports 16 priority levels for interrupts. Therefore, in the NVIC each source in the IPR registers contains 4 bits. For example, IPR0 is shown below: 31 R W 30 29 IRQ3 28 27 26 25 24 0 0 0 0 23 22 21 IRQ2 20 19 18 17 16 0 0 0 0 15 14 13 IRQ1 12 11 10 9 8 0 0 0 0 7 6 5 IRQ0 4 3 2 1 0 0 0 0 0 3.2.2.2 Non-maskable interrupt The non-maskable interrupt request to the NVIC is controlled by the external NMI signal. The pin the NMI signal is multiplexed on, must be configured for the NMI function to generate the non-maskable interrupt request. 3.2.2.3 Interrupt channel assignments The interrupt source assignments are defined in the following table. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 56 Freescale Semiconductor, Inc. Chapter 3 Chip Configuration * Vector number -- the value stored on the stack when an interrupt is serviced. * IRQ number -- non-core interrupt source count, which is the vector number minus 16. The IRQ number is used within ARM's NVIC documentation. Table 3-4. Interrupt vector assignments Address IRQ1 Vector NVIC NVIC non-IPR IPR register register number number 2 Source module Source description 3 ARM Core System Handler Vectors 0x0000_0000 0 - - - ARM core Initial Stack Pointer 0x0000_0004 1 - - - ARM core Initial Program Counter 0x0000_0008 2 - - - ARM core Non-maskable Interrupt (NMI) 0x0000_000C 3 - - - ARM core Hard Fault 0x0000_0010 4 - - - ARM core MemManage Fault 0x0000_0014 5 - - - ARM core Bus Fault 0x0000_0018 6 - - - ARM core Usage Fault 0x0000_001C 7 - - - -- -- 0x0000_0020 8 - - - -- -- 0x0000_0024 9 - - - -- -- 0x0000_0028 10 - - - -- -- 0x0000_002C 11 - - - ARM core Supervisor call (SVCall) 0x0000_0030 12 - - - ARM core Debug Monitor 0x0000_0034 13 - - - -- -- 0x0000_0038 14 - - - ARM core Pendable request for system service (PendableSrvReq) 0x0000_003C 15 - - - ARM core System tick timer (SysTick) 0x0000_0040 16 0 0 0 DMA DMA channel 0 transfer complete 0x0000_0044 17 1 0 0 DMA DMA channel 1 transfer complete 0x0000_0048 18 2 0 0 DMA DMA channel 2 transfer complete 0x0000_004C 19 3 0 0 DMA DMA channel 3 transfer complete 0x0000_0050 20 4 0 1 DMA DMA channel 4 transfer complete 0x0000_0054 21 5 0 1 DMA DMA channel 5 transfer complete 0x0000_0058 22 6 0 1 DMA DMA channel 6 transfer complete 0x0000_005C 23 7 0 1 DMA DMA channel 7 transfer complete 0x0000_0060 24 8 0 2 DMA DMA channel 8 transfer complete 0x0000_0064 25 9 0 2 DMA DMA channel 9 transfer complete 0x0000_0068 26 10 0 2 DMA DMA channel 10 transfer complete 0x0000_006C 27 11 0 2 DMA DMA channel 11 transfer complete Non-Core Vectors Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 57 Core modules Table 3-4. Interrupt vector assignments (continued) Address Vector IRQ1 NVIC NVIC non-IPR IPR register register number number 2 Source module Source description 3 0x0000_0070 28 12 0 3 DMA DMA channel 12 transfer complete 0x0000_0074 29 13 0 3 DMA DMA channel 13 transfer complete 0x0000_0078 30 14 0 3 DMA DMA channel 14 transfer complete 0x0000_007C 31 15 0 3 DMA DMA channel 15 transfer complete 0x0000_0080 32 16 0 4 DMA DMA error interrupt channels 0-15 0x0000_0084 33 17 0 4 MCM FPU sources 0x0000_0088 34 18 0 4 Flash memory Command complete 0x0000_008C 35 19 0 4 Flash memory Read collision 0x0000_0090 36 20 0 5 Mode Controller Low-voltage detect, low-voltage warning 0x0000_0094 37 21 0 5 LLWU Low Leakage Wakeup NOTE: The LLWU interrupt must not be masked by the interrupt controller to avoid a scenario where the system does not fully exit stop mode on an LLS recovery. 0x0000_0098 38 22 0 5 WDOG or EWM Both watchdog modules share this interrupt. 0x0000_009C 39 23 0 5 RNG Randon Number Generator -- 0x0000_00A0 40 24 0 6 I2C0 0x0000_00A4 41 25 0 6 I2C1 -- 0x0000_00A8 42 26 0 6 SPI0 Single interrupt vector for all sources 0x0000_00AC 43 27 0 6 SPI1 Single interrupt vector for all sources 0x0000_00B0 44 28 0 7 -- -- 0x0000_00B4 45 29 0 7 -- -- 0x0000_00B8 46 30 0 7 LPUART0 Status and error 0x0000_00BC 47 31 0 7 UART0 Single interrupt vector for UART status sources 0x0000_00C0 48 32 1 8 UART0 Single interrupt vector for UART error sources 0x0000_00C4 49 33 1 8 UART1 Single interrupt vector for UART status sources 0x0000_00C8 50 34 1 8 UART1 Single interrupt vector for UART error sources 0x0000_00CC 51 35 1 8 UART2 Single interrupt vector for UART status sources 0x0000_00D0 52 36 1 9 UART2 Single interrupt vector for UART error sources 0x0000_00D4 53 37 1 9 -- -- 0x0000_00D8 54 38 1 9 -- -- Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 58 Freescale Semiconductor, Inc. Chapter 3 Chip Configuration Table 3-4. Interrupt vector assignments (continued) Address Vector IRQ1 NVIC NVIC non-IPR IPR register register number number 2 Source module Source description 3 0x0000_00DC 55 39 1 9 ADC0 -- 0x0000_00E0 56 40 1 10 CMP0 -- 0x0000_00E4 57 41 1 10 CMP1 -- 0x0000_00E8 58 42 1 10 FTM0 Single interrupt vector for all sources 0x0000_00EC 59 43 1 10 FTM1 Single interrupt vector for all sources 0x0000_00F0 60 44 1 11 FTM2 Single interrupt vector for all sources 0x0000_00F4 61 45 1 11 -- -- 0x0000_00F8 62 46 1 11 Reserved -- 0x0000_00FC 63 47 1 11 Reserved -- 0x0000_0100 64 48 1 12 PIT Channel 0 0x0000_0104 65 49 1 12 PIT Channel 1 0x0000_0108 66 50 1 12 PIT Channel 2 0x0000_010C 67 51 1 12 PIT Channel 3 0x0000_0110 68 52 1 13 PDB -- 0x0000_0114 69 53 1 13 -- -- 0x0000_0118 70 54 1 13 -- -- 0x0000_011C 71 55 1 13 -- -- 0x0000_0120 72 56 1 14 DAC0 -- 0x0000_0124 73 57 1 14 MCG -- 0x0000_0128 74 58 1 14 Low Power Timer -- 0x0000_012C 75 59 1 14 Port control module Pin detect (Port A) 0x0000_0130 76 60 1 15 Port control module Pin detect (Port B) 0x0000_0134 77 61 1 15 Port control module Pin detect (Port C) 0x0000_0138 78 62 1 15 Port control module Pin detect (Port D) 0x0000_013C 79 63 1 15 Port control module Pin detect (Port E) 0x0000_0140 80 64 2 16 Software Software interrupt4 0x0000_0144 81 65 2 16 -- -- 0x0000_0148 82 66 2 16 -- -- 0x0000_014C 83 67 2 16 -- -- 0x0000_0150 84 68 2 17 -- -- 0x0000_0154 85 69 2 17 -- -- 0x0000_0158 86 70 2 17 -- -- 0x0000_015C 87 71 2 17 FTM3 Single interrupt vector for all sources 0x0000_0160 88 72 2 18 DAC1 -- 0x0000_0164 89 73 2 18 ADC1 -- 1. Indicates the NVIC's interrupt source number. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 59 Core modules 2. Indicates the NVIC's ISER, ICER, ISPR, ICPR, and IABR register number used for this IRQ. The equation to calculate this value is: IRQ div 32 3. Indicates the NVIC's IPR register number used for this IRQ. The equation to calculate this value is: IRQ div 4 4. This interrupt can only be pended or cleared via the NVIC registers. 3.2.2.3.1 Determining the bitfield and register location for configuring a particular interrupt Suppose you need to configure the low-power timer (LPTMR) interrupt. The following table is an excerpt of the LPTMR row from Interrupt channel assignments. Table 3-5. LPTMR interrupt vector assignment Address IRQ1 Vector NVIC NVIC non-IPR IPR register register number number 2 0x0000_0128 74 58 1 Source module Source description 3 14 Low Power Timer -- 1. Indicates the NVIC's interrupt source number. 2. Indicates the NVIC's ISER, ICER, ISPR, ICPR, and IABR register number used for this IRQ. The equation to calculate this value is: IRQ div 32 3. Indicates the NVIC's IPR register number used for this IRQ. The equation to calculate this value is: IRQ div 4 * The NVIC registers you would use to configure the interrupt are: * NVICISER1 * NVICICER1 * NVICISPR1 * NVICICPR1 * NVICIABR1 * NVICIPR14 * To determine the particular IRQ's bitfield location within these particular registers: * NVICISER1, NVICICER1, NVICISPR1, NVICICPR1, NVICIABR1 bit location = IRQ mod 32 = 26 * NVICIPR14 bitfield starting location = 8 * (IRQ mod 4) + 4 = 20 Since the NVICIPR bitfields are 4-bit wide (16 priority levels), the NVICIPR14 bitfield range is 20-23 Therefore, the following bitfield locations are used to configure the LPTMR interrupts: * * * * * * NVICISER1[26] NVICICER1[26] NVICISPR1[26] NVICICPR1[26] NVICIABR1[26] NVICIPR14[23:20] KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 60 Freescale Semiconductor, Inc. Chapter 3 Chip Configuration 3.2.3 Asynchronous Wake-up Interrupt Controller (AWIC) Configuration This section summarizes how the module has been configured in the chip. Full documentation for this module is provided by ARM and can be found at arm.com. Clock logic Wake-up requests Asynchronous Wake-up Interrupt Controller (AWIC) Nested vectored interrupt controller (NVIC) Module Module Figure 3-3. Asynchronous Wake-up Interrupt Controller configuration Table 3-6. Reference links to related information Topic Related module Reference System memory map System memory map Clocking Clock distribution Power management Power management Nested Vectored Interrupt Controller (NVIC) Wake-up requests NVIC AWIC wake-up sources 3.2.3.1 Wake-up sources The device uses the following internal and external inputs to the AWIC module. Table 3-7. AWIC Partial Stop, Stop and VLPS Wake-up Sources Wake-up source Description Available system resets RESET pin and WDOG when LPO is its clock source, and JTAG Low-voltage detect Power Mode Controller Low-voltage warning Power Mode Controller Pin interrupts Port Control Module - Any enabled pin interrupt is capable of waking the system ADCx The ADC is functional when using internal clock source Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 61 Core modules Table 3-7. AWIC Partial Stop, Stop and VLPS Wake-up Sources (continued) Wake-up source Description CMPx Since no system clocks are available, functionality is limited, trigger mode provides wakeup functionality with periodic sampling I2C Address match wakeup UART Active edge on RXD LPUART Functional when using clock source which is active in Stop and VLPS modes LPTMR Functional when using clock source which is active in Stop and VLPS modes NMI Non-maskable interrupt 3.2.4 FPU Configuration ARM Cortex M4 Core This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. PPB Transfers FPU Figure 3-4. FPU configuration Table 3-8. Reference links to related information Topic Related module Reference Full description FPU ARM Cortex-M4 Technical Reference Manual System memory map System memory map Clocking Clock Distribution Power Management Power Management Transfers ARM Cortex M4 core ARM Cortex-M4 core Private Peripheral Bus (PPB) 3.2.5 JTAG Controller Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 62 Freescale Semiconductor, Inc. Chapter 3 Chip Configuration JTAG controller cJTAG Signal multiplexing Figure 3-5. JTAGC Controller configuration Table 3-9. Reference links to related information Topic Related module Reference Full description JTAGC JTAGC Signal multiplexing Port control Signal multiplexing 3.3 System modules 3.3.1 SIM Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. Peripheral bridge Register access System integration module (SIM) Figure 3-6. SIM configuration Table 3-10. Reference links to related information Topic Related module Full description SIM Reference System memory map System memory map Clocking Clock distribution Power management Power management KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 63 System modules 3.3.2 System Mode Controller (SMC) Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. Peripheral bridge Register access Power Management Controller (PMC) System Mode Controller (SMC) Resets Figure 3-7. System Mode Controller configuration Table 3-11. Reference links to related information Topic Related module Reference Full description System Mode Controller (SMC) SMC System memory map System memory map Power management Power management Power management controller (PMC) PMC Low-Leakage Wakeup Unit (LLWU) LLWU Reset Control Module (RCM) Reset 3.3.3 PMC Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. Table 3-12. Reference links to related information Topic Related module Full description PMC Reference System memory map System memory map Power management Power management Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 64 Freescale Semiconductor, Inc. Chapter 3 Chip Configuration Table 3-12. Reference links to related information (continued) Topic Related module Reference Low-Leakage Wakeup Unit (LLWU) LLWU Full description 3.3.4 Low-Leakage Wake-up Unit (LLWU) Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. Peripheral bridge 0 Register access Wake-up requests Power Management Controller (PMC) Low-Leakage Wake-up Unit (LLWU) Module Module Figure 3-8. Low-Leakage Wake-up Unit configuration Table 3-13. Reference links to related information Topic Related module Full description LLWU System memory map Reference System memory map Clocking Clock distribution Power management Power management chapter Power Management Controller (PMC) Power Management Controller (PMC) Mode Controller Wake-up requests LLWU wake-up sources 3.3.4.1 Wake-up Sources The device uses the following internal peripheral and external pin inputs as wakeup sources to the LLWU module. LLWU_Px are external pin inputs, and LLWU_M0IFM7IF are connections to the internal peripheral interrupt flags. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 65 System modules NOTE In addition to the LLWU wakeup sources, the device also wakes from low power modes when NMI or RESET pins are enabled and the respective pin is asserted. Table 3-14. Wakeup sources for LLWU inputs Input Wakeup source LLWU_P0 PTE1/LLWU_P0 pin LLWU_P1 PTE2/LLWU_P1 pin LLWU_P2 PTE4/LLWU_P2 pin LLWU_P3 PTA4/LLWU_P3 pin1 LLWU_P4 PTA13/LLWU_P4 pin LLWU_P5 PTB0/LLWU_P5 pin LLWU_P6 PTC1/LLWU_P6 pin LLWU_P7 PTC3/LLWU_P7 pin LLWU_P8 PTC4/LLWU_P8 pin LLWU_P9 PTC5/LLWU_P9 pin LLWU_P10 PTC6/LLWU_P10 pin LLWU_P11 PTC11/LLWU_P11 pin LLWU_P12 PTD0/LLWU_P12 pin LLWU_P13 PTD2/LLWU_P13 pin LLWU_P14 PTD4/LLWU_P14 pin LLWU_P15 PTD6/LLWU_P15 pin LLWU_M0IF LPTMR2 LLWU_M1IF CMP02 LLWU_M2IF CMP12 LLWU_M3IF Reserved LLWU_M4IF Reserved LLWU_M5IF Reserved LLWU_M6IF Reserved LLWU_M7IF Reserved 1. The EZP_CS signal is checked only on Chip Reset not VLLS, so a VLLS wakeup via a non-reset source does not cause EzPort mode entry. If NMI was enabled on entry to LLS/VLLS, asserting the NMI pin generates an NMI interrupt on exit from the low power mode. NMI can also be disabled via the FOPT[NMI_DIS] bit. 2. Requires the peripheral and the peripheral interrupt to be enabled. The LLWU's WUME bit enables the internal module flag as a wakeup input. After wakeup, the flags are cleared based on the peripheral clearing mechanism. 3.3.5 MCM Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 66 Freescale Semiconductor, Inc. Chapter 3 Chip Configuration ARM Cortex-M4 core PPB Transfers Miscellaneous Control Module (MCM) Figure 3-9. MCM configuration Table 3-15. Reference links to related information Topic Related module Reference Full description Miscellaneous control module (MCM) MCM System memory map System memory map Clocking Clock distribution Power management Power management Transfers ARM Cortex-M4 core ARM Cortex-M4 core Private Peripheral Bus (PPB) 3.3.6 Crossbar-Light Switch Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 67 System modules Master Modules Slave Modules S0 SRAM controller_L S2 M2 Mux DMA EzPort Flash controller S1 ARM core system bus M1 ARM core code bus M0 Crossbar Switch SRAM controller_U Mux S3 Peripheral bridge 0 S4 GPIO controller FlexBus Figure 3-10. Crossbar-Light switch integration Table 3-16. Reference links to related information Topic Related module Reference Full description Crossbar switch Crossbar Switch System memory map System memory map Clocking Clock Distribution Crossbar switch master ARM Cortex-M4 core ARM Cortex-M4 core Crossbar switch master DMA controller DMA controller Crossbar switch master EzPort EzPort Crossbar switch slave Flash Flash Crossbar switch slave Peripheral bridges Peripheral bridge Crossbar switch slave GPIO controller GPIO controller Crossbar switch slave FlexBus/ FlexBus KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 68 Freescale Semiconductor, Inc. Chapter 3 Chip Configuration 3.3.6.1 Crossbar-Light Switch Master Assignments The masters connected to the crossbar switch are assigned as follows: Master module Master port number ARM core code bus 0 ARM core system bus 1 DMA /EzPort 2 NOTE The DMA and EzPort share a master port. Since these modules never operate at the same time, no configuration or arbitration explanations are necessary. 3.3.6.2 Crossbar-Light Switch Slave Assignments The slaves connected to the crossbar switch are assigned as follows: Slave module Slave port number Flash memory controller 0 SRAM controllers 1,2 Peripheral bridge 0/GPIO1 3 FlexBus 4 1. See System memory map for access restrictions. 3.3.7 Peripheral Bridge Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 69 System modules Crossbar switch Transfers AIPS-Lite peripheral bridge Transfers Peripherals Figure 3-11. Peripheral bridge configuration Table 3-17. Reference links to related information Topic Related module Reference Full description Peripheral bridge (AIPS-Lite) Peripheral bridge (AIPS-Lite) System memory map System memory map Clocking Clock Distribution Crossbar switch Crossbar switch Crossbar switch 3.3.7.1 Number of peripheral bridges This device contains one peripheral bridge. 3.3.7.2 Memory maps The peripheral bridges are used to access the registers of most of the modules on this device. See AIPS0 Memory Map for the memory slot assignment for each module. 3.3.8 DMA request multiplexer configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 70 Freescale Semiconductor, Inc. Chapter 3 Chip Configuration Peripheral bridge 0 Register access Requests DMA controller Channel request DMA Request Multiplexer Module Module Module Figure 3-12. DMA request multiplexer configuration Table 3-18. Reference links to related information Topic Related module Reference Full description DMA request multiplexer DMA Mux System memory map System memory map Clocking Clock distribution Power management Power management Channel request DMA controller DMA Controller Requests DMA request sources 3.3.8.1 DMA MUX request sources This device includes a DMA request mux that allows up to 63 DMA request signals to be mapped to any of the 16 DMA channels. Because of the mux there is not a hard correlation between any of the DMA request sources and a specific DMA channel. Some of the modules support Asynchronous DMA operation as indicated by the last column in the following DMA source assignment table. Table 3-19. DMA request sources - MUX 0 Source number Source module Source description 0 -- Channel disabled1 1 Reserved Not used 2 UART0 Receive 3 UART0 Transmit 4 UART1 Receive 5 UART1 Transmit 6 UART2 Receive 7 UART2 Transmit Async DMA capable Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 71 System modules Table 3-19. DMA request sources - MUX 0 (continued) Source number Source module Source description 8 Reserved -- 9 Reserved -- 10 Reserved -- 11 Reserved -- 12 -- -- Async DMA capable 13 -- -- 14 SPI0 Receive 15 SPI0 Transmit 16 SPI1 Transmit or Receive 17 Reserved -- 18 I2C0 -- 19 I2C1 -- 20 FTM0 Channel 0 21 FTM0 Channel 1 22 FTM0 Channel 2 23 FTM0 Channel 3 24 FTM0 Channel 4 25 FTM0 Channel 5 26 FTM0 Channel 6 27 FTM0 Channel 7 28 FTM1 Channel 0 29 FTM1 Channel 1 30 FTM2 Channel 0 31 FTM2 Channel 1 32 FTM3 Channel 0 33 FTM3 Channel 1 34 FTM3 Channel 2 35 FTM3 Channel 3 36 FTM3 Channel 4 37 FTM3 Channel 5 38 FTM3 Channel 6 39 FTM3 Channel 7 40 ADC0 -- Yes 41 ADC1 -- Yes 42 CMP0 -- Yes 43 CMP1 -- Yes 44 Reserved -- 45 DAC0 -- 46 DAC1 -- Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 72 Freescale Semiconductor, Inc. Chapter 3 Chip Configuration Table 3-19. DMA request sources - MUX 0 (continued) Source number Source module Source description Async DMA capable 47 Reserved -- 48 PDB -- 49 Port control module Port A Yes 50 Port control module Port B Yes 51 Port control module Port C Yes 52 Port control module Port D Yes 53 Port control module Port E Yes 54 Reserved -- 55 Reserved -- 56 Reserved -- 57 Reserved -- 58 LPUART0 Receive Yes 59 LPUART0 Transmit Yes 60 DMA MUX Always enabled 61 DMA MUX Always enabled 62 DMA MUX Always enabled 63 DMA MUX Always enabled 1. Configuring a DMA channel to select source 0 or any of the reserved sources disables that DMA channel. 3.3.8.2 DMA transfers via PIT trigger The PIT module can trigger a DMA transfer on the first four DMA channels. The assignments are detailed at PIT/DMA Periodic Trigger Assignments . 3.3.9 DMA Controller Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 73 System modules Peripheral bridge 0 Register access Crossbar switch Transfers DMA Controller Requests DMA Multiplexer Figure 3-13. DMA Controller configuration Table 3-20. Reference links to related information Topic Related module Reference Full description DMA Controller DMA Controller System memory map Register access System memory map Peripheral bridge (AIPS-Lite 0) AIPS-Lite 0 Clocking Clock distribution Power management Power management Transfers Crossbar switch Crossbar switch 3.3.10 External Watchdog Monitor (EWM) Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 74 Freescale Semiconductor, Inc. Chapter 3 Chip Configuration Peripheral bridge 0 Register access External Watchdog Monitor (EWM) Module signals Signal multiplexing Figure 3-14. External Watchdog Monitor configuration Table 3-21. Reference links to related information Topic Related module Reference Full description External Watchdog Monitor (EWM) EWM System memory map System memory map Clocking Clock distribution Power management Power management Signal multiplexing Port Control Module Signal multiplexing 3.3.10.1 EWM clocks This table shows the EWM clocks and the corresponding chip clocks. Table 3-22. EWM clock connections Module clock Low Power Clock Chip clock 1 kHz LPO Clock 3.3.10.2 EWM low-power modes This table shows the EWM low-power modes and the corresponding chip low-power modes. Table 3-23. EWM low-power modes Module mode Chip mode Wait Wait, VLPW Stop Stop, VLPS, LLS KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 75 System modules 3.3.10.3 EWM_OUT pin state in low power modes When the CPU enters a Run mode from Wait or Stop recovery, the pin resumes its previous state before entering Wait or Stop mode. When the CPU enters Run mode from Power Down, the pin returns to its reset state. 3.3.11 Watchdog Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. Peripheral bridge 0 Register access Mode Controller WDOG Figure 3-15. Watchdog configuration Table 3-24. Reference links to related information Topic Related module Reference Full description Watchdog Watchdog System memory map System memory map Clocking Clock distribution Power management Power management Mode Controller (MC) 3.3.11.1 WDOG clocks This table shows the WDOG module clocks and the corresponding chip clocks. Table 3-25. WDOG clock connections Module clock LPO Oscillator Chip clock 1 kHz LPO Clock Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 76 Freescale Semiconductor, Inc. Chapter 3 Chip Configuration Table 3-25. WDOG clock connections (continued) Module clock Chip clock Alt Clock Bus Clock Fast Test Clock Bus Clock System Bus Clock Bus Clock 3.3.11.2 WDOG low-power modes This table shows the WDOG low-power modes and the corresponding chip low-power modes. Table 3-26. WDOG low-power modes Module mode Chip mode Wait Wait, VLPW Stop Stop, VLPS Power Down LLS, VLLSx 3.4 Clock modules 3.4.1 MCG Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 77 Clock modules Peripheral bridge Register access System integration module (SIM) Multipurpose Clock Generator (MCG) System oscillator Figure 3-16. MCG configuration Table 3-27. Reference links to related information Topic Related module Reference Full description MCG MCG System memory map System memory map Clocking Clock distribution Power management Power management Signal multiplexing Port control Signal multiplexing 3.4.1.1 MCG oscillator clock input options The MCG has multiple oscillator input clock sources. Within the context of the MCG these are all referred to as the external reference clock and selection is determined by MCG_C7[OSCSEL] bitfield. The following table shows the chip-specific clock assignments for this bitfield. Table 3-28. MCG Oscillator Reference Options MCG_C7[OSCSEL] MCG defined selection Chip clock 00 OSCCLK0 - System Oscillator OSCCLK - Undivided system oscillator output. Derived from external crystal circuit or directly from EXTAL. 01 OSC2/RTC Oscillator Reserved 10 OSCCLK1 - Oscillator IRC48MCLK. Derived from internal 48 MHz oscillator. 11 Reserved -- See Clock Distribution for more details on these clocks. NOTE The MCG chapter has many references to the RTC oscillator source. On this device that clock source is not available and KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 78 Freescale Semiconductor, Inc. Chapter 3 Chip Configuration register MCG_C8 and other bit fields associated with this clock source should be treated as reserved. 3.4.2 OSC Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. Peripheral bridge Register access System oscillator MCG Module signals Signal multiplexing Figure 3-17. OSC configuration Table 3-29. Reference links to related information Topic Related module Reference Full description OSC OSC System memory map System memory map Clocking Clock distribution Power management Power management Signal multiplexing Port control Signal multiplexing Full description MCG MCG 3.4.2.1 OSC modes of operation with MCG The MCG's C2 register bits configure the oscillator frequency range. See the OSC and MCG chapters for more details. 3.5 Memories and memory interfaces KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 79 Memories and memory interfaces 3.5.1 Flash Memory Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. Peripheral bridge 0 Register access Flash memory controller Transfers Flash memory Figure 3-18. Flash memory configuration Table 3-30. Reference links to related information Topic Related module Full description Flash memory Reference System memory map System memory map Clocking Clock Distribution Transfers Flash memory controller Flash memory controller Register access Peripheral bridge Peripheral bridge 3.5.1.1 Flash memory types This device contains the following types of flash memory: * Program flash memory -- non-volatile flash memory that can execute program code 3.5.1.2 Flash Memory Sizes The devices covered in this document contain: * 2 blocks of program flash consisting of 2 KB sectors The amounts of flash memory for the devices covered in this document are: Device Program flash (KB) Block 0 address range Block 1 address range MKV31F512VLL12 512 0x0000_0000-0x0003_FFFF 0x0004_0000-0x0007_FFFF MKV31F512VLH12 512 0x0000_0000-0x0003_FFFF 0x0004_0000-0x0007_FFFF KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 80 Freescale Semiconductor, Inc. Chapter 3 Chip Configuration 3.5.1.3 Flash Memory Map The flash memory and the flash registers are located at different base addresses as shown in the following figure. The base address for each is specified in System memory map. Flash memory base address Registers Program flash base address Flash configuration field Program flash Figure 3-19. Flash memory map The on-chip Flash is implemented in a portion of the allocated Flash range to form a contiguous block in the memory map beginning at address 0x0000_0000. See Flash Memory Sizes for details of supported ranges. Accesses to the flash memory ranges outside the amount of Flash on the device causes the bus cycle to be terminated with an error followed by the appropriate response in the requesting bus master. Read collision events in which flash memory is accessed while a flash memory resource is being manipulated by a flash command also generates a bus error response. 3.5.1.4 Flash Security How flash security is implemented on this device is described in Chip Security. 3.5.1.5 Flash Program Restrictions The flash memory on this device should not be programmed or erased while operating in High Speed Run or VLPR power modes. 3.5.1.6 Flash Modes The flash memory operates in NVM normal and NVM special modes. The flash memory enters NVM special mode when the EzPort is enabled (EZP_CS asserted during reset). Otherwise, flash memory operates in NVM normal mode. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 81 Memories and memory interfaces 3.5.1.7 Erase All Flash Contents The flash of the MCU is protected from erasing all of the flash contents by the FTFA_FSEC[MEEN] bits. If the bits are set to 'b10 mass erase is disabled. An Erase All Flash Blocks operation can be launched by software through a series of peripheral bus writes to flash registers. In addition the entire flash memory may be erased external to the flash memory from the SWJ-DP debug port by setting DAP_CONTROL[0]. DAP_STATUS[0] is set to indicate the mass erase command has been accepted. DAP_STATUS[0] is cleared when the mass erase completes. The EzPort can also initiate an erase of flash contents by issuing a bulk erase (BE) command. See the EzPort chapter for more details. 3.5.1.8 FTF_FOPT Register The flash memory's FTF_FOPT register allows the user to customize the operation of the MCU at boot time. See FOPT boot options for details of its definition. 3.5.2 Flash Memory Controller Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. Peripheral bridge 0 Register access Crossbar switch Transfers Flash memory controller Transfers Flash memory Figure 3-20. Flash memory controller configuration Table 3-31. Reference links to related information Topic Related module Reference Full description Flash memory controller Flash memory controller System memory map System memory map Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 82 Freescale Semiconductor, Inc. Chapter 3 Chip Configuration Table 3-31. Reference links to related information (continued) Topic Related module Reference Clocking Clock Distribution Transfers Flash memory Flash memory Transfers Crossbar switch Crossbar Switch Register access Peripheral bridge Peripheral bridge 3.5.2.1 Number of masters The Flash Memory Controller supports up to eight crossbar switch masters. However, this device has a different number of crossbar switch masters. See Crossbar-Light Switch Configuration for details on the master port assignments. 3.5.3 SRAM Configuration This section summarizes how the module has been configured in the chip. Cortex-M4 core crossbar SRAM controller SRAM upper Transfers switch SRAM controller SRAM lower Figure 3-21. SRAM configuration Table 3-32. Reference links to related information Topic Related module Reference Full description SRAM SRAM System memory map System memory map Clocking Clock Distribution Transfers SRAM controller SRAM controller ARM Cortex-M4 core ARM Cortex-M4 core KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 83 Memories and memory interfaces 3.5.3.1 SRAM sizes This device contains SRAM accessed by bus masters through the cross-bar switch. The on-chip SRAM is split into SRAM_L and SRAM_U regions where the SRAM_L and SRAM_U ranges form a contiguous block in the memory map anchored at address 0x2000_0000. As such: * SRAM_L is anchored to 0x1FFF_FFFF and occupies the space before this ending address. * SRAM_U is anchored to 0x2000_0000 and occupies the space after this beginning address. NOTE Misaligned accesses across the 0x2000_0000 boundary are not supported in the ARM Cortex-M4 architecture. The amount of SRAM for the devices covered in this document is shown in the following table. Device SRAM_L size (KB) SRAM_U size (KB) Total SRAM (KB) Address Range MKV31F512VLL12 32 64 96 0x1FFF_8000-0x2000_FFFF MKV31F512VLH12 32 64 96 0x1FFF_8000-0x2000_FFFF 3.5.3.2 SRAM retention in low power modes The SRAM is retained down to LLS3 and VLLS3 mode. In LLS2 and VLLS2 the 32 KB region of SRAM_U from 0x2000_0000 is powered. In VLLS1 and VLLS0 no SRAM is retained; however, the 32-byte register file is available. 3.5.4 System Register File Configuration This section summarizes how the module has been configured in the chip. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 84 Freescale Semiconductor, Inc. Chapter 3 Chip Configuration Peripheral bridge 0 Register access Register file Figure 3-22. System Register file configuration Table 3-33. Reference links to related information Topic Related module Reference Full description Register file Register file System memory map System memory map Clocking Clock distribution Power management Power management 3.5.4.1 System Register file This device includes a 32-byte register file that is powered in all power modes. The System Register file is made up of eight 4-byte registers RFSYS_REGn, where n ranges from 0 to 7. Also, it retains contents during low-voltage detect (LVD) events and is only reset during a power-on reset. 3.5.5 EzPort Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 85 Memories and memory interfaces Transfers Crossbar switch EzPort Module signals Signal multiplexing Figure 3-23. EzPort configuration Table 3-34. Reference links to related information Topic Related module Reference Full description EzPort EzPort System memory map System memory map Clocking Clock Distribution Transfers Crossbar switch Crossbar switch Signal Multiplexing Port control Signal Multiplexing 3.5.5.1 JTAG instruction The system JTAG controller implements an EZPORT instruction. When executing this instruction, the JTAG controller resets the core logic and asserts the EzPort chip select signal to force the processor into EzPort mode. 3.5.5.2 Flash Option Register (FOPT) The FOPT[EZPORT_DIS] bit can be used to prevent entry into EzPort mode during reset. If the FOPT[EZPORT_DIS] bit is cleared, then the state of the chip select signal (EZP_CS) is ignored and the MCU always boots in normal mode. This option is useful for systems that use the EZP_CS/NMI signal configured for its NMI function. Disabling EzPort mode prevents possible unwanted entry into EzPort mode if the external circuit that drives the NMI signal asserts it during reset. The FOPT register is loaded from the flash option byte. If the flash option byte is modified the new value takes effect for any subsequent resets, until the value is changed again. 3.5.6 FlexBus Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 86 Freescale Semiconductor, Inc. Chapter 3 Chip Configuration Peripheral bridge 0 Register access Crossbar switch Transfers FlexBus Module signals Signal multiplexing Figure 3-24. FlexBus configuration Table 3-35. Reference links to related information Topic Related module Reference Full description FlexBus FlexBus System memory map System memory map Clocking Clock distribution Power management Power management Signal multiplexing Port control Signal multiplexing 3.5.6.1 FlexBus clocking The system provides a dedicated clock source to the FlexBus module's external CLKOUT. Its clock frequency is derived from a divider of the MCGOUTCLK. See Clock Distribution for more details. 3.5.6.2 FlexBus signal multiplexing The multiplexing of the FlexBus address and data signals is controlled by the port control module. However, the multiplexing of some of the FlexBus control signals are controlled by the port control and FlexBus modules. The port control module registers control whether the FlexBus or another module signals are available on the external pin, while the FlexBus's CSPMCR register configures which FlexBus signals are available from the modules. The control signals are grouped as illustrated: KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 87 Memories and memory interfaces CSPMCR FB_ALE FB_CS1 FB_TS Group1 Port Control Module To other modules FlexBus FB_CS4 FB_TSIZ0 FB_BE_31_24 Group2 To other modules Reserved External Pins FB_CS5 FB_TSIZ1 FB_BE_23_16 Group3 To other modules Reserved FB_TBST FB_CS2 FB_BE_15_8 Group4 To other modules Reserved FB_TA FB_CS3 FB_BE_7_0 Group5 To other modules Reserved Reserved Figure 3-25. FlexBus control signal multiplexing KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 88 Freescale Semiconductor, Inc. Chapter 3 Chip Configuration Therefore, use the CSPMCR and port control registers to configure which control signal is available on the external pin. All control signals, except for FB_TA, are assigned to the ALT5 function in the port control module. Since, unlike the other control signals, FB_TA is an input signal, it is assigned to the ALT6 function. 3.5.6.3 FlexBus CSCR0 reset value On this device the CSCR0 resets to 0x003F_FC00. Configure this register as needed before performing any FlexBus access. 3.5.6.4 FlexBus Security When security is enabled on the device, FlexBus accesses may be restricted by configuring SIM_SOPT2[]. See System Integration Module (SIM) for details. 3.5.6.5 FlexBus line transfers Line transfers are not possible from the ARM Cortex-M4 core. Ignore any references to line transfers in the FlexBus chapter. 3.6 Security 3.6.1 CRC Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 89 Security Peripheral bridge Register access CRC Figure 3-26. CRC configuration Table 3-36. Reference links to related information Topic Related module Reference Full description CRC CRC System memory map System memory map Power management Power management 3.6.2 RNG Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. Peripheral bridge Register access Random number generator (RNG) Figure 3-27. RNG configuration Table 3-37. Reference links to related information Topic Related module Reference Full description RNG RNG System memory map System memory map Clocking Clock distribution Power management Power management KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 90 Freescale Semiconductor, Inc. Chapter 3 Chip Configuration 3.7 Analog 3.7.1 16-bit SAR ADC Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. Peripheral bus controller 0 Register access Other peripherals Transfers 16-bit SAR ADC Module signals Signal multiplexing Figure 3-28. 16-bit SAR ADC configuration Table 3-38. Reference links to related information Topic Related module Reference Full description 16-bit SAR ADC 16-bit SAR ADC System memory map System memory map Clocking Clock distribution Power management Signal multiplexing Power management Port control Signal multiplexing 3.7.1.1 ADC instantiation information This device contains two ADCs. 3.7.1.1.1 Number of ADC channels The number of ADC channels present on the device is determined by the pinout of the specific device package. For details regarding the number of ADC channel available on a particular package, refer to the signal multiplexing chapter of this MCU. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 91 Analog 3.7.1.2 DMA Support on ADC Applications may require continuous sampling of the ADC (4K samples/sec) that may have considerable load on the CPU. Though using PDB to trigger ADC may reduce some CPU load, the ADC supports DMA request functionality for higher performance when the ADC is sampled at a very high rate or cases where PDB is bypassed. The ADC can trigger the DMA (via DMA req) on conversion completion. 3.7.1.3 ADCx Connections/Channel Assignment NOTE As indicated by the following sections, each ADCx_DPx input and certain ADCx_DMx inputs may operate as single-ended ADC channels in single-ended mode. 3.7.1.3.1 ADC0 channel assignment ADC Channel Table 3-39. ADC0 Assignments Channel Input signal (SC1n[DIFF]= 1) Input signal (SC1n[DIFF]= 0) 00000 DAD0 ADC0_DP0 and ADC0_DM0 ADC0_DP0 00001 DAD1 ADC0_DP1 and ADC0_DM1 ADC0_DP1 00010 DAD2 ADC0_DP2 and ADC0_DM2 ADC0_DP2 00011 DAD3 ADC0_DP3 and ADC0_DM3 ADC0_DP3 001001 AD4a Reserved ADC0_SE4a 001011 AD5a Reserved ADC0_SE5a 001101 AD6a Reserved ADC0_SE6a 001111 AD7a Reserved ADC0_SE7a 001001 AD4b Reserved ADC0_SE4b 001011 AD5b Reserved ADC0_SE5b 001101 AD6b Reserved ADC0_SE6b 001111 AD7b Reserved ADC0_SE7b 01000 AD8 Reserved ADC0_SE8 01001 AD9 Reserved ADC0_SE9 01010 AD10 Reserved Reserved 01011 AD11 Reserved Reserved 01100 AD12 Reserved ADC0_SE12 01101 AD13 Reserved ADC0_SE13 01110 AD14 Reserved ADC0_SE14 01111 AD15 Reserved ADC0_SE15 10000 AD16 Reserved ADC0_SE16 (SC1n[ADCH]) Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 92 Freescale Semiconductor, Inc. Chapter 3 Chip Configuration Table 3-39. ADC0 Assignments (continued) ADC Channel Channel Input signal (SC1n[DIFF]= 1) Input signal (SC1n[DIFF]= 0) 10001 AD17 Reserved ADC0_SE17 10010 AD18 Reserved ADC0_SE18 10011 AD19 Reserved ADC0_DM0 10100 AD20 Reserved ADC0_DM1 10101 AD21 Reserved ADC0_SE21 10110 AD22 Reserved ADC0_SE22 10111 AD23 Reserved 12-bit DAC0 Output/ADC0_SE23 11000 AD24 Reserved Reserved 11001 AD25 Reserved Reserved 11010 AD26 Temperature Sensor (Diff) Temperature Sensor (S.E) 11011 AD27 Bandgap (Diff) Bandgap (S.E)2 11100 AD28 Reserved Reserved 11101 AD29 -VREFH (Diff) VREFH (S.E) 11110 AD30 Reserved VREFL 11111 AD31 Module Disabled Module Disabled (SC1n[ADCH]) 1. ADCx_CFG2[MUXSEL] bit selects between ADCx_SEn channels a and b. Refer to MUXSEL description in ADC chapter for details. 2. This is the PMC bandgap 1V reference voltage and not the VREF module 1.2 V reference voltage. Prior to reading from this ADC channel, ensure that you enable the bandgap buffer by setting the PMC_REGSC[BGBE] bit. Refer to the device data sheet for the bandgap voltage (VBG) specification. 3.7.1.3.2 ADC1 channel assignment ADC Channel Table 3-40. ADC1 Assignments Channel Input signal (SC1n[DIFF]= 1) Input signal (SC1n[DIFF]= 0) 00000 DAD0 ADC1_DP0 and ADC1_DM0 ADC1_DP0 00001 DAD1 ADC1_DP1 and ADC1_DM1 ADC1_DP1 00010 DAD2 Reserved Reserved 00011 DAD3 ADC1_DP3 and ADC1_DM3 ADC1_DP3 001001 AD4a Reserved ADC1_SE4a 001011 AD5a Reserved ADC1_SE5a 001101 AD6a Reserved ADC1_SE6a 001111 AD7a Reserved ADC1_SE7a 001001 AD4b Reserved ADC1_SE4b 001011 AD5b Reserved ADC1_SE5b 001101 AD6b Reserved ADC1_SE6b 001111 AD7b Reserved ADC1_SE7b 01000 AD8 Reserved ADC1_SE8 (SC1n[ADCH]) Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 93 Analog Table 3-40. ADC1 Assignments (continued) ADC Channel Channel Input signal (SC1n[DIFF]= 1) Input signal (SC1n[DIFF]= 0) 01001 AD9 Reserved ADC1_SE9 01010 AD10 Reserved Reserved 01011 AD11 Reserved Reserved 01100 AD12 Reserved ADC1_SE12 01101 AD13 Reserved ADC1_SE13 01110 AD14 Reserved ADC1_SE14 01111 AD15 Reserved ADC1_SE15 10000 AD16 Reserved ADC1_SE16 10001 AD17 Reserved ADC1_SE17 10010 AD18 Reserved VREF Output/ADC1_SE18 10011 AD19 Reserved ADC1_DM0 10100 AD20 Reserved ADC1_DM1 10101 AD21 Reserved Reserved 10110 AD22 Reserved Reserved 10111 AD23 Reserved 12-bit DAC1 Output/ADC1_SE23 11000 AD24 Reserved Reserved 11001 AD25 Reserved Reserved 11010 AD26 Temperature Sensor (Diff) Temperature Sensor (S.E) 11011 AD27 Bandgap (Diff)2 Bandgap (S.E)2 11100 AD28 Reserved Reserved 11101 AD29 -VREFH (Diff) VREFH (S.E) 11110 AD30 Reserved VREFL 11111 AD31 Module Disabled Module Disabled (SC1n[ADCH]) 1. ADCx_CFG2[MUXSEL] bit selects between ADCx_SEn channels a and b. Refer to MUXSEL description in ADC chapter for details. 2. This is the PMC bandgap 1V reference voltage and not the VREF module 1.2 V reference voltage. Prior to reading from this ADC channel, ensure that you enable the bandgap buffer by setting the PMC_REGSC[BGBE] bit. Refer to the device data sheet for the bandgap voltage (VBG) specification. 3.7.1.4 ADC Channels MUX Selection The following figure shows the assignment of ADCx_SEn channels a and b through a MUX selection to ADC. To select between alternate set of channels, refer to ADCx_CFG2[MUXSEL] bit settings for more details. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 94 Freescale Semiconductor, Inc. Chapter 3 Chip Configuration ADCx_SE4a ADCx_SE5a ADCx_SE6a ADCx_SE7a ADCx_SE4b ADCx_SE5b ADCx_SE6b ADCx_SE7b AD4 [00100] AD5 [00101] ADC AD6 [00110] AD7 [00111] Figure 3-29. ADCx_SEn channels a and b selection 3.7.1.5 ADC Hardware Interleaved Channels The AD8 and AD9 channels on ADCx are interleaved in hardware using the following configuration. AD8 ADC0_SE8 /ADC1_SE8 ADC0 ADC0_SE9 /ADC1_SE9 AD9 AD8 ADC1 AD9 Figure 3-30. ADC hardware interleaved channels integration There are other pins on this device that have a similar interleave configuration, including the plus side of differential pair pins available (for example ADC0_DP0 and ADC1_DP3). Refer to the Signal Multiplexing and Pin Assignments table for this device. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 95 Analog 3.7.1.6 ADC Reference Options The ADC supports the following references: * VREFH/VREFL - connected as the primary reference option * 1.2 V VREF_OUT - connected as the VALT reference option ADCx_SC2[REFSEL] bit selects the voltage reference sources for ADC. Refer to REFSEL description in ADC chapter for more details. 3.7.1.7 ADC triggers The ADC supports both software and hardware triggers. The primary hardware mechanism for triggering the ADC is the PDB. The PDB itself can be triggered by other peripherals. For example: LPTMR Output signal is connected to the PDB. The PDB input trigger can receive the LPTMR Output trigger forcing ADC conversions in run mode (where PDB is enabled). On the other hand, the ADC can conduct conversions in low power modes, not triggered by PDB. This allows the ADC to do conversions in low power mode and store the output in the result register. The ADC generates interrupt when the data is ready in the result register that wakes the system from low power mode. The PDB can also be bypassed by using the ADCxTRGSEL bits in the SIM_SOPT7 register. Table 3-41. ADC Alternate trigger options SIM_SOPT7[ADCxTRGSEL] Selected source 0000 PDB external trigger pin input (PDB0_EXTRG) 0001 CMP0 output 0010 CMP1 output 0011 Reserved 0100 PIT trigger 0 0101 PIT trigger 1 0110 PIT trigger 2 0111 PIT trigger 3 1000 FTM0 trigger 1001 FTM1 trigger 1010 FTM2 trigger 1011 FTM3 trigger 1100 Reserved 1101 Reserved 1110 LPTMR trigger 1111 Reserved KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 96 Freescale Semiconductor, Inc. Chapter 3 Chip Configuration For operation of triggers in different modes, refer to Power Management chapter. 3.7.1.8 ADC conversion clock options The ADC has multiple input clock sources. Selection is determined by ADCx_CFG1[ADICLK] bitfield. The following table shows the chip-specific clock assignments for this bitfield. NOTE The ALTCLK option is only usable when OSCERCLK is in the MHz range. A system with OSCERCLK in the kHz range has the optional clock source below minimum ADC clock operating frequency. Table 3-42. ADC Conversion Clock Options ADCx_CFG1[ADICLK] ADC defined selection Chip clock Note 00 Bus Clock Bus Clock 01 ALTCLK2 IRC48MCLK Note 1 10 ALTCLK OSCERCLK Note 1 11 Asynchronous clock (ADACK) N/A - sourced from within ADC block Note1 1. For ADC operation in Compute only, PSTOP1, Stop and VLPS, ADACK and the alternate clock sources are allowed clock sources. Note however that ALTCLK2 is force disabled and therefore not available in VLPS. 3.7.1.9 ADC low-power modes This table shows the ADC low-power modes and the corresponding chip low-power modes. Table 3-43. ADC low-power modes Module mode Chip mode Wait Wait, VLPW Normal Stop Stop, VLPS Low Power Stop LLS, VLLS3, VLLS2, VLLS1, VLLS0 KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 97 Analog 3.7.2 CMP Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. Peripheral bridge 0 Register access CMP Other peripherals Module signals Signal multiplexing Figure 3-31. CMP configuration Table 3-44. Reference links to related information Topic Related module Reference Full description Comparator (CMP) Comparator System memory map System memory map Clocking Clock distribution Power management Power management Signal multiplexing Port control Signal multiplexing 3.7.2.1 CMP input connections The following table shows the fixed internal connections to the CMP. Table 3-45. CMP input connections CMP Inputs CMP0 CMP1 IN0 CMP0_IN0 CMP1_IN0 IN1 CMP0_IN1 CMP1_IN1 IN2 CMP0_IN2 CMP1_IN2 IN3 CMP0_IN3 12-bit DAC0_OUT/CMP1_IN3 IN4 12-bit DAC1 Output/CMP0_IN4 -- IN5 VREF Output/CMP0_IN5 VREF Output/CMP1_IN5 IN6 Bandgap Bandgap IN7 6b DAC0 Reference 6b DAC1 Reference KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 98 Freescale Semiconductor, Inc. Chapter 3 Chip Configuration 3.7.2.2 CMP external references The 6-bit DAC sub-block supports selection of two references. For this device, the references are connected as follows: * VREF_OUT - Vin1 input * VDD - Vin2 input 3.7.2.3 External window/sample input Individual PDB pulse-out signals control each CMP Sample/Window timing. 3.7.2.4 CMP trigger mode The CMP and 6-bit DAC sub-block supports trigger mode operation when the CMPx_CR1[TRIGM] is set. When trigger mode is enabled, the trigger event will initiate a compare sequence that must first enable the CMP and DAC prior to performing a CMP operation and capturing the output. In this device, control for this two staged sequencing is provided from the LPTMR. The LPTMR provides a single trigger output to all implemented comparators. Through configuration of the CMPx_CR1[TRIGM] bits the trigger can be used to trigger a single comparator or multiple comparators concurrently. The LPTMR triggering output is always enabled when the LPTMR is enabled. The first signal is supplied to enable the CMP and DAC and is asserted at the same time as the TCF flag is set. The delay to the second signal that triggers the CMP to capture the result of the compare operation is dependent on the LPTMR configuration. In Time Counter mode with prescaler enabled, the delay is 1/2 Prescaler output period. In Time Counter mode with prescaler bypassed, the delay is 1/2 Prescaler clock period. The delay between the first signal from LPTMR and the second signal from LPTMR must be greater than the Analog comparator initialization delay as defined in the device datasheet. 3.7.3 12-bit DAC Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 99 Analog Peripheral bus controller 0 Register access Other peripherals Transfers 12-bit DAC Module signals Signal multiplexing Figure 3-32. 12-bit DAC configuration Table 3-46. Reference links to related information Topic Related module Reference Full description 12-bit DAC 12-bit DAC System memory map System memory map Clocking Clock distribution Power management Power management Signal multiplexing Port control Signal multiplexing 3.7.3.1 12-bit DAC Overview This device contains two 12-bit digital-to-analog converters (DAC) with programmable reference generator output. The DAC includes a FIFO for DMA support. 3.7.3.2 12-bit DAC Output The output of the DAC can be placed on an external pin or set as one of the inputs to the analog comparator or ADC. 3.7.3.3 12-bit DAC Reference For this device VREF_OUT and VDDA are selectable as the DAC reference. VREF_OUT is connected to the DACREF_1 input and VDDA is connected to the DACREF_2 input. Use DACx_C0[DACRFS] control bit to select between these two options. Be aware that if the DAC and ADC use the VREF_OUT reference simultaneously, some degradation of ADC accuracy is to be expected due to DAC switching. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 100 Freescale Semiconductor, Inc. Chapter 3 Chip Configuration 3.7.4 VREF Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. Peripheral bus controller 0 Register access Transfers Other peripherals VREF Module signals Signal multiplexing Figure 3-33. VREF configuration Table 3-47. Reference links to related information Topic Related module Reference Full description VREF VREF System memory map System memory map Clocking Clock distribution Power management Power management Signal multiplexing Port control Signal multiplexing 3.7.4.1 VREF Overview This device includes a voltage reference (VREF) to supply an accurate 1.2 V voltage output. The voltage reference can provide a reference voltage to external peripherals or a reference to analog peripherals, such as the ADC, DAC, or CMP. NOTE PMC_REGSC[BGEN] bit must be set if the VREF regulator is required to remain operating in VLPx modes. NOTE For either an internal or external reference if the VREF_OUT functionality is being used, VREF_OUT signal must be KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 101 Timers connected to an output load capacitor. Refer the device data sheet for more details. 3.8 Timers 3.8.1 PDB Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. Peripheral bus controller 0 Register access Transfers Other peripherals PDB Module signals Signal multiplexing Figure 3-34. PDB configuration Table 3-48. Reference links to related information Topic Related module Reference Full description PDB PDB System memory map System memory map Clocking Clock distribution Power management Power management Signal multiplexing Port control Signal multiplexing 3.8.1.1 PDB Instantiation 3.8.1.1.1 PDB Output Triggers Table 3-49. PDB output triggers Number of PDB channels for ADC trigger 2 Number of pre-triggers per PDB channel 2 Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 102 Freescale Semiconductor, Inc. Chapter 3 Chip Configuration Table 3-49. PDB output triggers (continued) 3.8.1.1.2 Number of DAC triggers 2 Number of PulseOut 2 PDB Input Trigger Connections Table 3-50. PDB Input Trigger Options PDB Trigger PDB Input 0000 External Trigger 0001 CMP 0 0010 CMP 1 0011 Reserved 0100 PIT Ch 0 Output 0101 PIT Ch 1 Output 0110 PIT Ch 2 Output 0111 PIT Ch 3 Output 1000 FTM0 initialization trigger and channel triggers, as programmed in the FTM external trigger register (EXTTRIG) 1001 FTM1 initialization trigger and channel triggers, as programmed in the FTM external trigger register (EXTTRIG) 1010 FTM2 initialization trigger and channel triggers, as programmed in the FTM external trigger register (EXTTRIG) 1011 FTM3 initialization trigger and channel triggers, as programmed in the FTM external trigger register (EXTTRIG) 1100 Reserved 1101 Reserved 1110 LPTMR Output 1111 Software Trigger 3.8.1.2 PDB Module Interconnections PDB trigger outputs Connection Channel 0 triggers ADC0 trigger Channel 1 triggers ADC1 trigger and synchronous input 1 of FTM0 DAC triggers DAC0 and DAC1 trigger Pulse-out Pulse-out connected to each CMP module's sample/window input to control sample operation KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 103 Timers 3.8.1.3 Back-to-back acknowledgement connections Back-to-back operation enables the ADC conversions complete to trigger the next PDB channel pre-trigger and trigger output. In this MCU, PDB back-to-back operation acknowledgment connections are implemented as follows: * * * * PDB channel 0 trigger/pre-trigger 0 acknowledgement input: ADC1SC1B_COCO PDB channel 0 trigger/pre-trigger 1 acknowledgement input: ADC0SC1A_COCO PDB channel 1 trigger/pre-trigger 0 acknowledgement input: ADC0SC1B_COCO PDB channel 1 trigger/pre-trigger 1 acknowledgement input: ADC1SC1A_COCO So, the back-to-back chain is connected as a ring: Channel 0 pre-trigger 0 Channel 1 pre-trigger 1 Channel 0 pre-trigger 1 Channel 1 pre-trigger 0 Figure 3-35. PDB back-to-back chain The application code can set the PDBx_CHnC1[BB] bits to configure the PDB pretriggers as a single chain or several chains. 3.8.1.4 PDB Interval Trigger Connections to DAC In this MCU, PDB interval trigger connections to DAC are implemented as follows. * PDB interval trigger 0 connects to DAC0 hardware trigger input. * PDB interval trigger 1 connects to DAC1 hardware trigger input. 3.8.1.5 DAC External Trigger Input Connections In this MCU, the following DAC external trigger inputs are implemented. * DAC external trigger input 0: ADC0SC1A_COCO * DAC external trigger input 1: ADC1SC1A_COCO KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 104 Freescale Semiconductor, Inc. Chapter 3 Chip Configuration NOTE Application code can set the PDBx_DACINTCn[EXT] bit to allow DAC external trigger input when the corresponding ADC Conversion complete flag, ADCx_SC1n[COCO], is set. 3.8.1.6 Pulse-Out Connection Individual PDB Pulse-Out signals are connected to each CMP block and used for sample window. 3.8.1.7 Pulse-Out Enable Register Implementation The following table shows the comparison of pulse-out enable register at the module and chip level. Table 3-51. PDB pulse-out enable register Register Module implementation Chip implementation POnEN 7:0 - POEN 0 - POEN[0] for CMP0 31:8 - Reserved 1 - POEN[1] for CMP1 31:2 - Reserved 3.8.2 FlexTimer Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 105 Timers Peripheral bus controller 0 Register access Transfers Other peripherals FlexTimer Module signals Signal multiplexing Figure 3-36. FlexTimer configuration Table 3-52. Reference links to related information Topic Related module Reference Full description FlexTimer FlexTimer System memory map System memory map Clocking Clock distribution Power management Power management Signal multiplexing Port control Signal multiplexing 3.8.2.1 Instantiation Information This device contains four FlexTimer modules. The following table shows how these modules are configured. Table 3-53. FTM Instantiations FTM instance Number of channels Features/usage FTM0 8 3-phase motor + 2 general purpose or stepper motor FTM1 2 Quadrature decoder or general purpose FTM2 21 Quadrature decoder or general purpose FTM3 8 3-phase motor + 2 general purpose or stepper motor 1. Only channels 0 and 1 are available. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 106 Freescale Semiconductor, Inc. Chapter 3 Chip Configuration 3.8.2.2 External Clock Options By default each FTM is clocked by the internal bus clock (the FTM refers to it as system clock). Each module contains a register setting that allows the module to be clocked from an external clock instead. There are two external FTM_CLKINx pins that can be selected by any FTM module via the SIM_SOPT4 register. 3.8.2.3 Fixed frequency clock The fixed frequency clock for each FTM is MCGFFCLK. 3.8.2.4 FTM Interrupts The FlexTimer has multiple sources of interrupt. However, these sources are OR'd together to generate a single interrupt request per FTM module to the interrupt controller. When an FTM interrupt occurs, read the FTM status registers (FMS, SC, and STATUS) to determine the exact interrupt source. 3.8.2.5 FTM Fault Detection Inputs The following fault detection input options for the FTM modules are selected via the SIM_SOPT4 register. The external pin option is selected by default. * * * * FTM0 FAULT0 = FTM0_FLT0 pin or CMP0 output FTM0 FAULT1 = FTM0_FLT1 pin or CMP1 output FTM0 FAULT2 = FTM0_FLT2 pin FTM0 FAULT3 = FTM0_FLT3 pin * FTM1 FAULT0 = FTM1_FLT0 pin or CMP0 output * FTM1 FAULT1 = CMP1 output * FTM2 FAULT0 = FTM2_FLT0 pin or CMP0 output * FTM2 FAULT1 = CMP1 output * FTM3 FAULT0 = FTM3_FLT0 pin or CMP0 output 3.8.2.6 FTM Hardware Triggers The FTM synchronization hardware triggers are connected in the chip as follows: KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 107 Timers * FTM0 hardware trigger 0 = SIM_SOPT8[FTM0SYNCBIT] or CMP0 Output or FTM1 Match (when enabled in the FTM1 External Trigger (EXTTRIG) register) * FTM0 hardware trigger 1 = PDB channel 1 Trigger Output or FTM2 Match (when enabled in the FTM2 External Trigger (EXTTRIG) register) * FTM0 hardware trigger 2 = FTM0_FLT0 pin * FTM1 hardware trigger 0 = SIM_SOPT8[FTM1SYNCBIT] or CMP0 Output * FTM1 hardware trigger 1 = CMP1 Output * FTM1 hardware trigger 2 = FTM1_FLT0 pin * FTM2 hardware trigger 0 = SIM_SOPT8[FTM2SYNCBIT] or CMP0 Output * FTM2 hardware trigger 2 = FTM2_FLT0 pin * FTM3 hardware trigger 0 = SIM_SOPT8[FTM3SYNCBIT] or FTM1 Match (when enabled in the FTM1 External Trigger (EXTTRIG) register) * FTM3 hardware trigger 1 = FTM2 Match (when enabled in the FTM2 External Trigger (EXTTRIG) register) * FTM3 hardware trigger 2 = FTM3_FLT0 pin Having FTMxSYNCBIT fields in the same SOPTx register allows the user to synchronise all FTM timers via their respective TRIG0 input. For the triggers with more than one additional option, the SIM_SOPT4 register implements control fields for selecting the option. 3.8.2.7 Input capture options for FTM module instances The following channel 0 input capture source options are selected via SIM_SOPT4. The external pin option is selected by default. * FTM1 channel 0 input capture = FTM1_CH0 pin or CMP0 output or CMP1 output * FTM2 channel 0 input capture = FTM2_CH0 pin or CMP0 output or CMP1 output * FTM2 channel 1 input capture = FTM2_CH1 pin or exclusive OR of FTM2_CH0, FTM2_CH1, and FTM1_CH1. See FTM Hall sensor support. 3.8.2.8 FTM Hall sensor support For 3 phase motor control sensor-ed applications the use of Hall sensors, generally 3 sensors placed 120 degrees apart around the rotor, are deployed to detect position and speed. Each of the 3 sensors provides a pulse that applied to an input capture pin, can then be analyzed and both speed and position can be deduced. This device has two 2channel FTMs. (FTM1 and FTM2) and thus provides 4 input capture pins. To simplify KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 108 Freescale Semiconductor, Inc. Chapter 3 Chip Configuration the calculations required by the CPU on each hall sensor's input, if all 3 inputs are "exclusively OR'd " into one timer channel and the free running counter is refreshed on every edge then this can simplify the speed calculation. Via the SIM module and SIM_SOPT4 register the FTM2CH1SRC bit provides the choice of normal FTM2_CH1 input or the XOR of FTM2_CH0, FTM2_CH1 and FTM1_CH1 pins that will be applied to FTM2_CH1. Note: If the user utilizes FTM1_CH1 to be an input to FTM2_CH1, FTM1_CH0 can still be utilized for other functions. FTM2 FTM2_CH1 Ch0 Ch1 FTM2_CH0 X OR FTM1 FTM1_CH1 SIM_SOPT4[FTM2CH1SRC] Ch0 Ch1 Figure 3-37. FTM Hall Sensor Configuration 3.8.2.9 FTM modulation implementation FTM0 and FTM3 support a modulation function where the output channels when configured as PWM or Output Compare mode modulate another timer output when the channel signal is asserted. Any of the 8 channels of FTM0 and any of the 8 channels of FTM3 can be configured to support this modulation function. The SIM_SOPT8 register has eight control bits (FTM0CHySRC) that allow the user to select normal PWM/Output Compare mode on the corresponding FTM timer channel or modulate with FTM1_CH1. The diagram below shows the implementation for FTM0. FTM3 has similar implementation controlled by SIM_SOPT8[FTM3CHySRC] on each of its 8 channels with modulation possible via FTM2_CH1. See SIM Block Guide for further information. When FTM1_CH1 is used to modulate an FTM0 channel, then the user must configure FTM1_CH1 to provide a signal that has a higher frequency than the modulated FTM0 channel output. Also it limits the use of the FTM1_CH0 function, as the FTM1_CH1 will be programmed to provide a 50% duty PWM signal and limit the start and modulus values for the free running counter. FTM2 has a similar restriction when FTM2_CH1 is used for modulating an FTM3 channel. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 109 Timers SIM_SOPT8[FTM0CH7SRC] FTM0 & FTM0_CH7 CH7 SIM_SOPT8[FTM0CH0SRC] & FTM0_CH0 CH0 FTM1_CH1 Figure 3-38. FTM Output Modulation 3.8.2.10 FTM output triggers for other modules FTM output triggers can be selected as input triggers for the PDB and ADC modules. See PDB Instantiation and ADC triggers. 3.8.2.11 FTM Global Time Base This chip provides the optional FTM global time base feature (see Global time base (GTB)). FTM0 provides the only source for the FTM global time base. The other FTM modules can share the time base as shown in the following figure: KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 110 Freescale Semiconductor, Inc. Chapter 3 Chip Configuration FTM1 CONF Register GTBEOUT = 0 GTBEEN = 1 FTM0 CONF Register GTBEOUT = 1 GTBEEN = 1 gtb_in FTM Counter gtb_in FTM Counter gtb_out FTM2 CONF Register GTBEOUT = 0 GTBEEN = 1 FTM Counter gtb_in FTM3 CONF Register GTBEOUT = 0 GTBEEN = 1 FTM Counter gtb_in Figure 3-39. FTM Global Time Base Configuration 3.8.2.12 FTM BDM and debug halt mode In the FTM chapter, references to the chip being in "BDM" are the same as the chip being in "debug halt mode". 3.8.3 PIT Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 111 Timers Peripheral bridge Register access Periodic interrupt timer Figure 3-40. PIT configuration Table 3-54. Reference links to related information Topic Related module Reference Full description PIT PIT System memory map System memory map Clocking Clock Distribution Power management Power management 3.8.3.1 PIT/DMA Periodic Trigger Assignments The PIT generates periodic trigger events to the DMA Mux as shown in the table below. Table 3-55. PIT channel assignments for periodic DMA triggering DMA Channel Number PIT Channel DMA Channel 0 PIT Channel 0 DMA Channel 1 PIT Channel 1 DMA Channel 2 PIT Channel 2 DMA Channel 3 PIT Channel 3 3.8.3.2 PIT/ADC Triggers PIT triggers are selected as ADCx trigger sources using the SIM_SOPT7[ADCxTRGSEL] fields. For more details, refer to SIM chapter. 3.8.4 Low-power timer configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 112 Freescale Semiconductor, Inc. Chapter 3 Chip Configuration Peripheral bridge Register access Low-power timer Module signals Signal multiplexing Figure 3-41. LPTMR configuration Table 3-56. Reference links to related information Topic Related module Reference Full description Low-power timer Low-power timer System memory map System memory map Clocking Clock Distribution Power management Power management Signal Multiplexing Port control Signal Multiplexing 3.8.4.1 LPTMR prescaler/glitch filter clocking options The prescaler and glitch filter of the LPTMR module can be clocked from one of four sources determined by the LPTMR0_PSR[PCS] bitfield. The following table shows the chip-specific clock assignments for this bitfield. NOTE The chosen clock must remain enabled if the LPTMR is to continue operating in all required low-power modes. LPTMR0_PSR[PCS] Prescaler/glitch filter clock number Chip clock 00 0 MCGIRCLK -- internal reference clock (not available in VLPS/LLS/VLLS modes) 01 1 LPO -- 1 kHz clock (not available in VLLS0 mode) 10 2 ERCLK32K -- secondary external reference clock 11 3 OSCERCLK_UNDIV -- Undivided external reference clock (not available in VLLS0 mode) See Clock Distribution for more details on these clocks. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 113 Communication interfaces 3.8.4.2 LPTMR pulse counter input options The LPTMR_CSR[TPS] bitfield configures the input source used in pulse counter mode. The following table shows the chip-specific input assignments for this bitfield. LPTMR_CSR[TPS] Pulse counter input number Chip input 00 0 CMP0 output 01 1 LPTMR_ALT1 pin 10 2 LPTMR_ALT2 pin 11 3 LPTMR_ALT3 pin 3.9 Communication interfaces 3.9.1 SPI configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. Peripheral bridge Register access SPI Module signals Signal multiplexing Figure 3-42. SPI configuration Table 3-57. Reference links to related information Topic Related module Reference Full description SPI SPI System memory map System memory map Clocking Clock Distribution Signal Multiplexing Port control Signal Multiplexing KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 114 Freescale Semiconductor, Inc. Chapter 3 Chip Configuration 3.9.1.1 SPI Modules Configuration This device contains two SPI modules . 3.9.1.2 SPI clocking The SPI module is clocked by the internal bus clock (the DSPI refers to it as system clock). The module has an internal divider, with a minimum divide is two. So, the SPI can run at a maximum frequency of bus clock/2. 3.9.1.3 Number of CTARs SPI CTAR registers define different transfer attribute configurations. The SPI module supports up to eight CTAR registers. This device supports two CTARs on all instances of the SPI. In master mode, the CTAR registers define combinations of transfer attributes, such as frame size, clock phase, clock polarity, data bit ordering, baud rate, and various delays. In slave mode only CTAR0 is used, and a subset of its bitfields sets the slave transfer attributes. 3.9.1.4 TX FIFO size Table 3-58. SPI transmit FIFO size SPI Module Transmit FIFO size SPI0 4 SPI1 1 3.9.1.5 RX FIFO Size SPI supports up to 16-bit frame size during reception. Table 3-59. SPI receive FIFO size SPI Module Receive FIFO size SPI0 4 SPI1 1 KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 115 Communication interfaces 3.9.1.6 Number of PCS signals The following table shows the number of peripheral chip select signals available per SPI module. Table 3-60. SPI PCS signals SPI Module PCS Signals SPI0 For packages with greater than 64 pins: SPI_PCS[5:0] For packages with 64 pins: SPI_PCS[4:0] SPI1 For packages with greater than 64 pins: SPI_PCS[3:0] For packages with 64 pins: SPI_PCS[1:0] 3.9.1.7 SPI Operation in Low Power Modes In VLPR and VLPW modes the SPI is functional; however, the reduced system frequency also reduces the max frequency of operation for the SPI. In VLPR and VLPW modes the max SPI_CLK frequency is 2MHz. In stop and VLPS modes, the clocks to the SPI module are disabled. The module is not functional, but it is powered so that it retains state. There is one way to wake from stop mode via the SPI, which is explained in the following section. 3.9.1.7.1 Using GPIO Interrupt to Wake from stop mode Here are the steps to use a GPIO to create a wakeup upon reception of SPI data in slave mode: 1. Point the GPIO interrupt vector to the desired interrupt handler. 2. Enable the GPIO input to generate an interrupt on either the rising or falling edge (depending on the polarity of the chip select signal). 3. Enter Stop or VLPS mode and Wait for the GPIO interrupt. NOTE It is likely that in using this approach the first word of data from the SPI host might not be received correctly. This is dependent on the transfer rate used for the SPI, the delay between chip select assertion and presentation of data, and the system interrupt latency. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 116 Freescale Semiconductor, Inc. Chapter 3 Chip Configuration 3.9.1.8 SPI Doze Mode The Doze mode for the SPI module is the same as the Wait and VLPW modes for the chip. 3.9.1.9 SPI Interrupts The SPI has multiple sources of interrupt requests. However, these sources are OR'd together to generate a single interrupt request per SPI module to the interrupt controller. When an SPI interrupt occurs, read the SPI_SR to determine the exact interrupt source. 3.9.1.10 SPI clocks This table shows the SPI module clocks and the corresponding chip clocks. Table 3-61. SPI clock connections Module clock System Clock Chip clock Bus Clock 3.9.1.11 Writing SPI Transmit FIFO The SPI supports 8-bit or 16-bit writes to the PUSH TX FIFO, allowing a single write to the command word followed by multiple writes to the transmit word. The TX FIFO will save the last command word written, and convert a 8-bit/16-bit write to the transmit word into a 32-bit write that pushes both the command word and transmit word into the TX FIFO (PUSH TX FIFO Register In Master Mode) A 32-bit write to the SPI_PUSH register will push all 32-bits to the TX FIFO. An 8-bit or 16-bit write to the 16-bit transmit data field will push the data together with the last written command word. An 8-bit or 16-bit write to the command word does not push data onto the FIFO, but that command word is pushed to the TX FIFO on all subsequent 8-bit or 16-bit writes to the transmit data field. This allows a single 16-bit write to the command word to be used for all subsequent 8-bit or 16-bit writes to the transmit data word. Writing a different 16-bit command word will cause all subsequent 8-bit or 16-bit writes to the transmit data word to be pushed to the TX FIFO with the new command word. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 117 Communication interfaces 3.9.2 I2C Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. Peripheral bridge Register access I2 C Module signals Signal multiplexing Figure 3-43. I2C configuration Table 3-62. Reference links to related information Topic Related module Reference Full description I2C I2C System memory map System memory map Clocking Clock Distribution Power management Power management Signal Multiplexing Port control Signal Multiplexing 3.9.2.1 I2C Instantiation Information This device has two I2C modules. The I2C module includes SMBus support and DMA support. It also has optional address match wakeup in Stop/VLPS mode. The digital glitch filter implemented in the IIC module, controlled by the I2Cx_FLT[FLT] registers, is clocked from the bus clock and thus has filter granularity in bus clock cycle counts. 3.9.3 UART Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 118 Freescale Semiconductor, Inc. Chapter 3 Chip Configuration Peripheral bridge Register access Module signals UART Signal multiplexing Figure 3-44. UART configuration Table 3-63. Reference links to related information Topic Related module Reference Full description UART UART System memory map System memory map Clocking Clock Distribution Power management Power management Signal Multiplexing Port control Signal Multiplexing 3.9.3.1 UART configuration information This chip contains three UART modules. This section describes how each module is configured on this device. 1. Standard features of all UARTs: * RS-485 support * Hardware flow control (RTS/CTS) * 9-bit UART to support address mark with parity * MSB/LSB configuration on data 2. UART0 and UART1 are clocked from the core clock, the remaining UARTs are clocked on the bus clock. The maximum baud rate is 1/16 of related source clock frequency. 3. IrDA is available on all UARTs 4. UART0 contains the standard features plus ISO7816 5. UART0 contains 8-entry transmit and 8-entry receive FIFOs 6. All other UARTs contain a 1-entry transmit and receive FIFOs KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 119 Communication interfaces 3.9.3.2 UART wakeup The UART can be configured to generate an interrupt/wakeup on the first active edge that it receives. 3.9.3.3 UART interrupts The UART has multiple sources of interrupt requests. However, some of these sources are OR'd together to generate a single interrupt request. See below for the mapping of the individual interrupt sources to the interrupt request: The status interrupt combines the following interrupt sources: Source UART 0 UART 1 UART 2 Transmit data empty x x x Transmit complete x x x Idle line x x x Receive data full x x x LIN break detect x x x RxD pin active edge x x x Initial character detect x -- -- The error interrupt combines the following interrupt sources: Source UART 0 UART 1 UART 2 Receiver overrun x x x Noise flag x x x Framing error x x x Parity error x x x Transmitter buffer overflow x x x Receiver buffer overflow x x x Receiver buffer underflow x x x Transmit threshold (ISO7816) x -- -- Receiver threshold (ISO7816) x -- -- Wait timer (ISO7816) x -- -- Character wait timer (ISO7816) x -- -- Block wait timer (ISO7816) x -- -- Guard time violation (ISO7816) x -- -- ATR duration timer (ISO7816) x -- -- KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 120 Freescale Semiconductor, Inc. Chapter 3 Chip Configuration 3.9.4 LPUART configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. Peripheral bridge Register access Module signals LPUART Signal multiplexing Figure 3-45. LPUART configuration Table 3-64. Reference links to related information Topic Related module Reference Full description LPUART0 LPUART System memory map System memory map Clocking Clock distribution Power management Power management Signal multiplexing Port control Signal multiplexing 3.9.4.1 LPUART0 overview The LPUART0 module supports basic UART with DMA interface function and x4 to x32 oversampling of baud-rate. The module can remain functional in Stop and VLPS mode provided the clock it is using remains enabled. This module supports LIN slave operation. 3.10 Human-machine interfaces KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 121 Kinetis Motor Suite Configuration 3.10.1 GPIO configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module's dedicated chapter. Peripheral bridge Register access Crossbar switch Transfers GPIO controller Module signals Signal multiplexing Figure 3-46. GPIO configuration Table 3-65. Reference links to related information Topic Related module Reference Full description GPIO GPIO System memory map System memory map Clocking Clock Distribution Power management Power management Transfers Crossbar switch Clock Distribution Signal Multiplexing Port control Signal Multiplexing 3.10.1.1 Number of GPIO signals The number of GPIO signals available on the devices covered by this document are detailed in Orderable part numbers . Eight GPIO pins support a high drive capability - PTB0, PTB1, PTD4, PTD5, PTD6, PTD7, PTC3, and PTC4. All other GPIO support normal drive option only. PTA4 includes a passive input filter that is enabled or disabled by PORTA_PCR4[PFE] control. This reset default is to have this function disabled. 3.11 Kinetis Motor Suite Configuration KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 122 Freescale Semiconductor, Inc. Chapter 3 Chip Configuration 3.11.1 KMS configuration KMS is an integrated solution of hardware, factory programmed embedded firmware, and PC software that enables rapid development of applications driven by three phase permanent magnet or brushless DC motors. Figure 3-47. Kinetis Motor Suite MCU's enabled with KMS have only 504K of flash available since 8K of flash is used to store the KMS library routines. 3.11.2 KMS Library NOTE Do not mass erase the MCU Flash. Doing a mass erase will remove the factory programmed secured library from the MCU and render the KMS enabled part obsolete for KMS use. If the part is accidentally mass erased and KMS is desired, then a new KMS enabled MCU is needed to replace the erased MCU. To prevent mass erase set the MEEN bits in the FSEC config to KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 123 Kinetis Motor Suite Configuration (FSEC[MEEN] = 10). Regardless of the SEC bits values, setting (FSEC[MEEN] = 10) will keep the MCU from being mass erased from the MCU 'erase all' command, the debugger write to MDM-AP register or from an EzPort programmer. 3.11.3 Library Protection The KMS library is protected from reading through the flash access controller of the Flash module. The reserved address region is from 0x0007E000 to 0x0007FFFF on 512K Flash part. The Flash access controls are fully utilized by KMS for this protection and are not available to the user to protect any other code. If code protection is desired then use the other flash protection options available. 3.11.4 Flash protection The KMS library can be protected from sector erase with the FPROT config bits. Setting the highest order bits of (FPROT[31:30] = 01) on this 512K flash device protects the top 16K of Flash from erase by flash commands Erase all blocks and Erase All Execute-only Segments. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 124 Freescale Semiconductor, Inc. Chapter 4 Memory Map 4.1 Introduction This device contains various memories and memory-mapped peripherals which are located in one 32-bit contiguous memory space. This chapter describes the memory and peripheral locations within that memory space. 4.2 System memory map The following table shows the high-level device memory map. This map provides the complete architectural address space definition for the various sections. Based on the physical sizes of the memories and peripherals, the actual address regions used may be smaller. The system memory map includes address spaces that are intended for specific purposes. * The two ICode regions (address < 0x2000_0000) mapped to the FlexBus space allow code to be executed with maximum performance. * There is an aliased region that maps a system address space to the Program flash section. Flash region aliasing is specifically intended for references to read-only data coefficients in the flash while still preserving a full Harvard memory organization in the processor core supporting concurrent instruction fetches (for example, from RAM) and data accesses (from flash via the aliased space). * The bitbanding functionality supported by the processor core uses aliased regions that map to the basic RAM and peripheral address spaces. This functionality maps each 32-bit word of the aliased address space to a unique bit in the underlying RAM or peripheral address space to support single-bit insert and extract operations from the processor. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 125 System memory map Table 4-1. System memory map System 32-bit Address Range 0x0000_0000-0x07FF_FFFF 1 Destination Slave Access Program flash and read-only data All masters (Includes exception vectors in first 1024 bytes) 0x0800_0000-0x0FFF_FFFF FlexBus Cortex-M4 core (M0) only 0x1000_0000-0x17FF_FFFF Reserved -- 0x1800_0000-0x1BFF_FFFF FlexBus Cortex-M4 core (M0) only 0x1C00_0000-0x1FFF_FFFF 2 SRAM_L: Lower SRAM (ICODE/DCODE) All masters 0x2000_0000-0x200F_FFFF 2 SRAM_U: Upper SRAM bitband region All masters 0x2010_0000-0x21FF_FFFF Reserved - 0x2200_0000-0x23FF_FFFF Aliased to SRAM_U bitband Cortex-M4 core only Reserved - Program Flash and read-only data Cortex-M4 core only 0x3400_0000-0x3FFF_FFFF Reserved - 0x4000_0000-0x4007_FFFF Bitband region for peripheral bridge 0 (AIPS-Lite0) Cortex-M4 core & DMA/EzPort 0x4008_0000-0x400F_EFFF Reserved - 0x400F_F000-0x400F_FFFF Bitband region for general purpose input/output (GPIO) Cortex-M4 core & DMA/EzPort 0x4010_0000-0x41FF_FFFF Reserved - 0x4200_0000-0x42FF_FFFF Aliased to peripheral bridge (AIPS-Lite) bitband Cortex-M4 core only 0x4300_0000-0x43FD_FFFF Reserved - 0x43FE_0000-0x43FF_FFFF Aliased to general purpose input/output (GPIO) bitband Cortex-M4 core only 0x4400_0000-0x5FFF_FFFF Reserved - 0x6000_0000-0x9FFF_FFFF FlexBus (External Memory) All masters 0xA000_0000-0xDFFF_FFFF FlexBus (External Peripheral - Not executable) All masters 0xE000_0000-0xE00F_FFFF Private peripherals Cortex-M4 core only 0xE010_0000-0xFFFF_FFFF Reserved - 0x2400_0000-0x2FFF_FFFF 0x3000_0000-0x33FF_FFFF 1 1. This map provides the complete architectural address space definition for the flash. Based on the physical sizes of the memories implemented for a particular device, the actual address regions used may be smaller. See Flash Memory Sizes for details. 2. This range varies depending on amount of SRAM implemented for a particular device. See SRAM sizes for details. NOTE 1. EzPort master port is statically muxed with DMA master port. Access rights to AIPS-Lite peripheral bridge and general purpose input/output (GPIO) module address space is limited to the core, DMA and EzPort. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 126 Freescale Semiconductor, Inc. Chapter 4 Memory Map 2. ARM Cortex-M4 core access privileges also includes accesses via the debug interface. 4.2.1 Aliased bit-band regions The SRAM_U, AIPS-Lite, and general purpose input/output (GPIO) module resources reside in the Cortex-M4 processor bit-band regions. The processor also includes two 32 MB aliased bit-band regions associated with the two 1 MB bit-band spaces. Each 32-bit location in the 32 MB space maps to an individual bit in the bit-band region. A 32-bit write in the alias region has the same effect as a readmodify-write operation on the targeted bit in the bit-band region. Bit 0 of the value written to the alias region determines what value is written to the target bit: * Writing a value with bit 0 set writes a 1 to the target bit. * Writing a value with bit 0 clear writes a 0 to the target bit. A 32-bit read in the alias region returns either: * a value of 0x0000_0000 to indicate the target bit is clear * a value of 0x0000_0001 to indicate the target bit is set Bit-band region 31 0 0 32 MByte 1 MByte 31 Alias bit-band region Figure 4-1. Alias bit-band mapping KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 127 Flash Memory Map NOTE Each bit in bit-band region has an equivalent bit that can be manipulated through bit 0 in a corresponding long word in the alias bit-band region. 4.2.2 Flash Access Control Introduction The Flash Access Control (FAC) is a Freescale or third-party configurable memory protection scheme optimized to allow end users to utilize software libraries while offering programmable restrictions to these libraries. The flash memory is divided into equal size segments that provide protection to proprietary software libraries. The protection of these segments is controlled as the FAC provides a cycle-by-cycle evaluation of the access rights for each transaction routed to the on-chip flash memory. Configurability allows an increasing number of protected segments while supporting two levels of vendors adding their proprietary software to a device. Flash access control aligns to the three privilege levels supported by ARM Cortex-M family products where the most secure state - supervisor/privileged secure - aligns to the execute-only and supervisor-only access control. The unsecure state of user non-secure aligns to no access control states set, and the mid-level state where user secure aligns to using the access control of execute-only. Control for this protection scheme is implemented in Program Once NVM locations and is configurable through a Program Once flash command operations. The NVM locations controlling FAC are unaffected by Erase All Blocks flash command and debug interface initiated mass erase operations. NOTE The FAC protection scheme has eight XACC and eight SACC registers to control up to 64 segments. For program flash sizes 128KB or less, the memory is divided into 32 segments, controlled by the four lower-order XACC and SACC registers. To protect the NVM locations being used for execute only code from being mass erased FTFA_FSEC[MEEN] bits must be set to 'b10. 4.3 Flash Memory Map The flash memory and the flash registers are located at different base addresses as shown in the following figure. The base address for each is specified in System memory map. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 128 Freescale Semiconductor, Inc. Chapter 4 Memory Map Flash memory base address Registers Program flash base address Flash configuration field Program flash Figure 4-2. Flash memory map The on-chip Flash is implemented in a portion of the allocated Flash range to form a contiguous block in the memory map beginning at address 0x0000_0000. See Flash Memory Sizes for details of supported ranges. Accesses to the flash memory ranges outside the amount of Flash on the device causes the bus cycle to be terminated with an error followed by the appropriate response in the requesting bus master. Read collision events in which flash memory is accessed while a flash memory resource is being manipulated by a flash command also generates a bus error response. 4.3.1 Alternate Non-Volatile IRC User Trim Description The following non-volatile locations (4 bytes) are reserved for custom IRC user trim supported by some development tools. An alternate IRC trim to the factory loaded trim can be stored at this location. To override the factory trim, user software must load new values into the MCG trim registers. Non-Volatile Byte Address Alternate IRC Trim Value 0x0000_03FC Reserved 0x0000_03FD Reserved 0x0000_03FE (bit 0) SCFTRIM 0x0000_03FE (bit 4:1) FCTRIM 0x0000_03FE (bit 6) FCFTRIM 0x0000_03FF SCTRIM 4.4 SRAM memory map The on-chip RAM is split in two regions: SRAM_L and SRAM_U. The RAM is implemented such that the SRAM_L and SRAM_U ranges form a contiguous block in the memory map. See SRAM Configuration for details. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 129 Peripheral bridge (AIPS-Lite) memory map Accesses to the SRAM_L and SRAM_U memory ranges outside the amount of RAM on the device causes the bus cycle to be terminated with an error followed by the appropriate response in the requesting bus master. 4.5 Peripheral bridge (AIPS-Lite) memory map Modules that are disabled via their clock gate control bits in the SIM registers disable the associated AIPS slots. Access to any address within an unimplemented or disabled peripheral bridge slot results in a transfer error termination. For programming model accesses via the peripheral bridges, there is generally only a small range within the 4 KB slots that is implemented. Accessing an address that is not implemented in the peripheral results in a transfer error termination. 4.5.1 Read-after-write sequence and required serialization of memory operations In some situations, a write to a peripheral must be completed fully before a subsequent action can occur. Examples of such situations include: * Exiting an interrupt service routine (ISR) * Changing a mode * Configuring a function In these situations, the application software must perform a read-after-write sequence to guarantee the required serialization of the memory operations: 1. Write the peripheral register. 2. Read the written peripheral register to verify the write. 3. Continue with subsequent operations. NOTE One factor contributing to these situations is processor write buffering. The processor architecture has a programmable configuration bit to disable write buffering: ACTLR[DISDEFWBUF]. However, disabling buffered writes is likely to degrade system performance much more than simply performing the required memory serialization for the situations that truly require it. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 130 Freescale Semiconductor, Inc. Chapter 4 Memory Map 4.5.2 Peripheral Bridge 0 (AIPS-Lite 0) Memory Map Table 4-2. Peripheral bridge 0 slot assignments System 32-bit base address Slot number Module 0x4000_0000 0 -- 0x4000_1000 1 -- 0x4000_2000 2 -- 0x4000_3000 3 -- 0x4000_4000 4 -- 0x4000_5000 5 -- 0x4000_6000 6 -- 0x4000_7000 7 -- 0x4000_8000 8 DMA controller 0x4000_9000 9 DMA controller transfer control descriptors 0x4000_A000 10 -- 0x4000_B000 11 -- 0x4000_C000 12 FlexBus 0x4000_D000 13 -- 0x4000_E000 14 -- 0x4000_F000 15 -- 0x4001_0000 16 -- 0x4001_1000 17 -- 0x4001_2000 18 -- 0x4001_3000 19 -- 0x4001_4000 20 -- 0x4001_5000 21 -- 0x4001_6000 22 -- 0x4001_7000 23 -- 0x4001_8000 24 -- 0x4001_9000 25 -- 0x4001_A000 26 -- 0x4001_B000 27 -- 0x4001_C000 28 -- 0x4001_D000 29 -- 0x4001_E000 30 -- 0x4001_F000 31 Flash memory controller 0x4002_0000 32 Flash memory 0x4002_1000 33 DMA channel mutiplexer 0x4002_2000 34 -- 0x4002_3000 35 -- 0x4002_4000 36 -- Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 131 Peripheral bridge (AIPS-Lite) memory map Table 4-2. Peripheral bridge 0 slot assignments (continued) System 32-bit base address Slot number Module 0x4002_5000 37 -- 0x4002_6000 38 FlexTimer (FTM) 3 0x4002_7000 39 Analog-to-digital converter (ADC) 1 0x4002_8000 40 DAC1 0x4002_9000 41 Random Number Generator (RNGA) 0x4002_A000 42 LPUART0 0x4002_B000 43 -- 0x4002_C000 44 SPI 0 0x4002_D000 45 SPI 1 0x4002_E000 46 -- 0x4002_F000 47 -- 0x4003_0000 48 -- 0x4003_1000 49 -- 0x4003_2000 50 CRC 0x4003_3000 51 -- 0x4003_4000 52 -- 0x4003_5000 53 -- 0x4003_6000 54 Programmable delay block (PDB) 0x4003_7000 55 Periodic interrupt timers (PIT) 0x4003_8000 56 FlexTimer (FTM) 0 0x4003_9000 57 FlexTimer (FTM) 1 0x4003_A000 58 FlexTimer (FTM) 2 0x4003_B000 59 Analog-to-digital converter (ADC) 0 0x4003_C000 60 -- 0x4003_D000 61 -- 0x4003_E000 62 -- 0x4003_F000 63 DAC0 0x4004_0000 64 Low-power timer (LPTMR) 0x4004_1000 65 System register file 0x4004_2000 66 -- 0x4004_3000 67 -- 0x4004_4000 68 -- 0x4004_5000 69 -- 0x4004_6000 70 -- 0x4004_7000 71 SIM low-power logic 0x4004_8000 72 System integration module (SIM) 0x4004_9000 73 Port A multiplexing control 0x4004_A000 74 Port B multiplexing control 0x4004_B000 75 Port C multiplexing control Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 132 Freescale Semiconductor, Inc. Chapter 4 Memory Map Table 4-2. Peripheral bridge 0 slot assignments (continued) System 32-bit base address Slot number Module 0x4004_C000 76 Port D multiplexing control 0x4004_D000 77 Port E multiplexing control 0x4004_E000 78 -- 0x4004_F000 79 -- 0x4005_0000 80 -- 0x4005_1000 81 -- 0x4005_2000 82 Software watchdog 0x4005_3000 83 -- 0x4005_4000 84 -- 0x4005_5000 85 -- 0x4005_6000 86 -- 0x4005_7000 87 -- 0x4005_8000 88 -- 0x4005_9000 89 -- 0x4005_A000 90 -- 0x4005_B000 91 -- 0x4005_C000 92 -- 0x4005_D000 93 -- 0x4005_E000 94 -- 0x4005_F000 95 -- 0x4006_0000 96 -- 0x4006_1000 97 External watchdog 0x4006_2000 98 -- 0x4006_3000 99 -- 0x4006_4000 100 Multi-purpose Clock Generator (MCG) 0x4006_5000 101 System oscillator (OSC) 0x4006_6000 102 I2C 0 0x4006_7000 103 I2C 1 0x4006_8000 104 -- 0x4006_9000 105 -- 0x4006_A000 106 UART 0 0x4006_B000 107 UART 1 0x4006_C000 108 UART 2 0x4006_D000 109 -- 0x4006_E000 110 -- 0x4006_F000 111 -- 0x4007_0000 112 -- 0x4007_1000 113 -- 0x4007_2000 114 -- Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 133 Private Peripheral Bus (PPB) memory map Table 4-2. Peripheral bridge 0 slot assignments (continued) System 32-bit base address Slot number 0x4007_3000 115 Analog comparator (CMP) / 6-bit digital-to-analog converter (DAC) 0x4007_4000 116 Voltage reference (VREF) 0x4007_5000 117 -- 0x4007_6000 118 -- 0x4007_7000 119 -- 0x4007_8000 120 -- 0x4007_9000 121 -- 0x4007_A000 122 -- 0x4007_B000 123 -- 0x4007_C000 124 Low-leakage wakeup unit (LLWU) 0x4007_D000 125 Power management controller (PMC) 0x4007_E000 126 System Mode controller (SMC) 0x4007_F000 127 Reset Control Module (RCM) 0x400F_F000 Module GPIO controller 4.6 Private Peripheral Bus (PPB) memory map The PPB is part of the defined ARM bus architecture and provides access to select processor-local modules. These resources are only accessible from the core; other system masters do not have access to them. Table 4-3. PPB memory map System 32-bit Address Range Resource 0xE000_0000-0xE000_0FFF Instrumentation Trace Macrocell (ITM) 0xE000_1000-0xE000_1FFF Data Watchpoint and Trace (DWT) 0xE000_2000-0xE000_2FFF Flash Patch and Breakpoint (FPB) 0xE000_3000-0xE000_DFFF Reserved 0xE000_E000-0xE000_EFFF System Control Space (SCS) (for NVIC and FPU) 0xE000_F000-0xE003_FFFF Reserved 0xE004_0000-0xE004_0FFF Trace Port Interface Unit (TPIU) 0xE004_1000-0xE004_1FFF Reserved 0xE004_2000-0xE004_2FFF Reserved 0xE004_3000-0xE004_3FFF Reserved 0xE004_4000-0xE007_FFFF Reserved 0xE008_0000-0xE008_0FFF Miscellaneous Control Module (MCM) 0xE008_1000-0xE008_1FFF Reserved Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 134 Freescale Semiconductor, Inc. Chapter 4 Memory Map Table 4-3. PPB memory map (continued) System 32-bit Address Range Resource 0xE008_2000-0xE00F_EFFF Reserved 0xE00F_F000-0xE00F_FFFF ROM Table - allows auto-detection of debug components KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 135 Private Peripheral Bus (PPB) memory map KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 136 Freescale Semiconductor, Inc. Chapter 5 Clock Distribution 5.1 Introduction The MCG module controls which clock source is used to derive the system clocks. The clock generation logic divides the selected clock source into a variety of clock domains, including the clocks for the system bus masters, system bus slaves, and flash memory . The clock generation logic also implements module-specific clock gating to allow granular shutoff of modules. The primary clocks for the system are generated from the MCGOUTCLK clock. The clock generation circuitry provides several clock dividers that allow different portions of the device to be clocked at different frequencies. This allows for trade-offs between performance and power dissipation. Various modules have module-specific clocks that can be generated from the IRC48MCLK or MCGPLLCLK or MCGFLLCLK clock. In addition, there are various other module-specific clocks that have other alternate sources. Clock selection for most modules is controlled by the SOPT registers in the SIM module. 5.2 Programming model The selection and multiplexing of system clock sources is controlled and programmed via the MCG module. The setting of clock dividers and module clock gating for the system are programmed via the SIM module. Reference those sections for detailed register and bit descriptions. 5.3 High-Level device clocking diagram The following system oscillator, MCG, and SIM module registers control the multiplexers, dividers, and clock gates shown in the below figure: KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 137 Clock definitions OSC MCG SIM Multiplexers MCG_Cx MCG_Cx SIM_SOPT1, SIM_SOPT2 Dividers -- MCG_Cx SIM_CLKDIVx Clock gates OSC_CR MCG_C1 SIM_SCGCx SIM MCG 4 MHz IRC FCRDIV MCGIRCLK CG 32 kHz IRC MCGFFCLK FLL OUTDIV1 CG Core / system clocks OUTDIV2 CG Bus clock OUTDIV3 CG FlexBus clock OUTDIV4 CG Flash clock MCGOUTCLK PLL MCGFLLCLK FRDIV Clock options for some peripherals (see note) MCGPLLCLK System oscillator EXTAL0 IRC48MCLK OSCCLK OSCERCLK_UNDIV XTAL_CLK XTAL0 OSC logic OSCERCLK DIV OSC32KCLK ERCLK32K PMC IRC48M internal oscillator IRC48M logic IRC48MCLK PMC logic Clock options for some peripherals (see note) MCGPLLCLK/ MCGFLLCLK/ IRC48MCLK PRDIV LPO CG -- Clock gate Note: See subsequent sections for details on where these clocks are used. Figure 5-1. Clocking diagram 5.4 Clock definitions The following table describes the clocks in the previous block diagram. Clock name Core clock Description MCGOUTCLK divided by OUTDIV1 clocks the ARM CortexM4 core Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 138 Freescale Semiconductor, Inc. Chapter 5 Clock Distribution Clock name Description Platform clock MCGOUTCLK divided by OUTDIV1, clocks the crossbar switch and NVIC. System clock MCGOUTCLK divided by OUTDIV1, clocks the bus masters directly. In addition, this clock is used for UART0 and UART1. Bus clock MCGOUTCLK divided by OUTDIV2 clocks the bus slaves and peripheral (excluding memories) FlexBus clock MCGOUTCLK divided by OUTDIV3 clocks the external FlexBus interface Flash clock MCGOUTCLK divided by OUTDIV4 clocks the flash memory MCGIRCLK MCG output of the slow or fast internal reference clock MCGFFCLK MCG output of the slow internal reference clock or a divided MCG external reference clock. MCGOUTCLK MCG output of either IRC, MCGFLLCLK , MCGPLLCLK or MCG's external reference clock that sources the core, system, bus, FlexBus, and flash clock. It is also an option for the debug trace clock. MCGFLLCLK MCG output of the FLL. MCGFLLCLK may clock some modules. MCGPLLCLK MCG output of the PLL. MCGFLLCLK or MCGPLLCLK may clock some modules. IRC48MCLK Internal 48 MHz oscillator that can be used as a reference to the MCG and also may clock some on-chip modules. OSCCLK System oscillator output of the internal oscillator or sourced directly from EXTAL OSCERCLK System oscillator output sourced from OSCCLK that may clock some on-chip modules. Dividable by 1, 2, 4, or 8. OSC32KCLK System oscillator 32kHz output ERCLK32K Clock source for some modules that is chosen as OSC32KCLK. LPO PMC 1kHz output 5.4.1 Device clock summary The following table provides more information regarding the on-chip clocks. Table 5-1. Clock Summary Clock name High Speed Run mode Run mode VLPR mode clock frequency clock frequency Up to 120 MHz Up to 4 MHz Clock source Clock is disabled when... MCG In all stop modes except for partial stop modes and during PLL locking when clock frequency MCGOUTCLK Up to 120 MHz Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 139 Clock definitions Table 5-1. Clock Summary (continued) Clock name High Speed Run mode Run mode VLPR mode clock frequency clock frequency Clock source Clock is disabled when... clock frequency MCGOUTCLK derived from PLL. MCGFLLCLK Up to 100 MHz Up to 100 MHz N/A MCG MCG clock controls do not enable. Overriding forced disable in all low powers modes (including STOP and VLPx modes). MCGPLLCLK Up to 120 MHz Up to 120 MHz N/A MCG MCG clock controls do not enable, in Stop mode but PLLSTEN=0, or in VLPS, LLS and VLLSx modes Core clock Up to 120 MHz Up to 80 MHz Up to 4 MHz MCGOUTCLK clock divider In all wait and stop modes System clock Up to 120 MHz Up to 80 MHz Up to 4 MHz MCGOUTCLK clock divider In all stop modes and Compute Operation Bus clock Up to 60 MHz Up to 50 MHz Up to 4 MHz MCGOUTCLK clock divider In all stop modes except for partial STOP2 mode, and Compute Operation FlexBus clock Up to 30 MHz Up to 30 MHz Up to 4 MHz MCGOUTCLK clock divider In all stop modes or Up to 26.67 MHz Up to 26.67 MHz Up to 1 MHz in BLPE, Up to 800 kHz in BLPI MCGOUTCLK clock divider In all stop modes except for partial STOP2 mode 30-40 kHz or 4 MHz 4 MHz only MCG MCG_C1[IRCLKEN ] cleared, (FB_CLK) Flash clock Internal reference 30-40 kHz or 4 MHz (MCGIRCLK) FlexBus disabled Stop or VLPS mode and MCG_C1[IREFSTE N] cleared, or LLS/VLLS mode External reference Up to 50 MHz (bypass), (OSCERCLK) 30-40 kHz, or 3-32 MHz (crystal) Up to 50 MHz (bypass), Up to 16 MHz (bypass), 30-40 kHz, or 30-40 kHz (lowrange crystal) or 3-32 MHz (crystal) System OSC Stop mode and OSC_CR[EREFST EN] cleared Up to 16 MHz (high-range crystal) External reference 30-40 kHz 32kHz 30-40 kHz 30-40 kHz System OSC's OSC_CR[ERCLKE N] cleared, or System OSC or LPO System OSC's OSC_CR[ERCLKE N] cleared Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 140 Freescale Semiconductor, Inc. Chapter 5 Clock Distribution Table 5-1. Clock Summary (continued) Clock name High Speed Run mode Run mode VLPR mode clock frequency clock frequency 48 MHz N/A Clock source Clock is disabled when... IRC48M MCG or SIM control does not enable. clock frequency (ERCLK32K) Internal 48 MHz clock 48 MHz (IRC48MCLK) Overriding forced disable in VLPS, LLSx, VLLSx. CLKOUT32K 32 kHz 32 kHz 32 kHz ERCLK32K - which is system OSC or LPO depending on SIM_SOPT1[OSC3 2KSEL] SIM_SOPT1[OSC3 2KOUT] not configured to drive ERCLK32K out. LPO 1 kHz 1 kHz 1 kHz PMC in VLLS0 TRACE clock Up to 120 MHz Up to 120 MHz Up to 4 MHz System clock or Trace is disabled LPUART0 clock Up to 100 MHz Up to 100MHz Up to 16MHz MCGOUTCLK MCGFLLCLK or IRC48MCLK or LPUART0 is disabled MCGIRCLK or OSCERCLK 5.5 Internal clocking requirements The clock dividers are programmed via the SIM module's CLKDIV registers. Each divider is programmable from a divide-by-1 through divide-by-16 setting. The following requirements must be met when configuring the clocks for this device: 1. The core and system clock frequencies must be 120 MHz or slower in HSRUN, 80 MHz or slower in RUN. 2. The bus clock frequency must be programmed to 60 MHz or less in HSRUN, 50 MHz or less in RUN, and an integer divide of the core clock. The core clock to bus clock ratio is limited to a max value of 8. 3. The flash clock frequency must be programmed to 26.67 MHz or less, less than or equal to the bus clock, and an integer divide of the core clock. The core clock to flash clock ratio is limited to a max value of 8. 4. The FlexBus clock frequency must be programmed to be less than or equal to the bus clock frequency. The FlexBus also has pad interface restrictions that limits the maximum frequency. For this device the FlexBus maximum frequency is 30 MHz. The core clock to FlexBus clock ratio is limited to a max value of 8. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 141 Internal clocking requirements The following are a few of the more common clock configurations for this device: Option 1: Clock Frequency Core clock 50 MHz System clock 50 MHz Bus clock 50 MHz FlexBus clock 25 MHz Flash clock 25 MHz Option 2: Run Clock Frequency Core clock 80 MHz System clock 80 MHz Bus clock 40 MHz FlexBus clock 20 MHz Flash clock 26.67 MHz Option 3: High Speed Run Clock Frequency Core clock 120 MHz System clock 120 MHz Bus clock 60 MHz FlexBus clock 30 MHz Flash clock 24 MHz 5.5.1 Clock divider values after reset Each clock divider is programmed via the SIM module's CLKDIVn registers. The flash memory's FTF_FOPT[LPBOOT] bit controls the reset value of the core clock, system clock, bus clock, and flash clock dividers as shown below: FTF_FOPT [LPBOOT] Core/system clock Bus clock FlexBus clock Flash clock Description 0 0x7 (divide by 8) 0x7 (divide by 8) 0xF (divide by 16) 0xF (divide by 16) Low power boot 1 0x0 (divide by 1) 0x0 (divide by 1) 0x1 (divide by 2) 0x1 (divide by 2) Fast clock boot KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 142 Freescale Semiconductor, Inc. Chapter 5 Clock Distribution This gives the user flexibility for a lower frequency, low-power boot option. The flash erased state defaults to fast clocking mode, since where the low power boot (FTF_FOPT[LPBOOT]) bit resides in flash is logic 1 in the flash erased state. To enable the low power boot option program FTF_FOPT[LPBOOT] to zero. During the reset sequence, if LPBOOT is cleared, the system is in a slow clock configuration. Upon any system reset, the clock dividers return to this configurable reset state. 5.5.2 VLPR mode clocking The clock dividers cannot be changed while in VLPR mode. They must be programmed prior to entering VLPR mode to guarantee: * the core/system, FlexBus, and bus clocks are less than or equal to 4 MHz, and * the flash memory clock is less than or equal to 1 MHz NOTE When the MCG is in BLPI and clocking is derived from the Fast IRC, the clock divider controls, MCG_SC[FCRDIV] and SIM_CLKDIV1[OUTDIV4], must be programmed such that the resulting flash clock nominal frequency is 800 kHz or less. In this case, one example of correct configuration is MCG_SC[FCRDIV]=000b and SIM_CLKDIV1[OUTDIV4]=0100b, resulting in a divide by 5 setting. 5.6 Clock Gating The clock to each module can be individually gated on and off using the SIM module's SCGCx registers. These bits are cleared after any reset, which disables the clock to the corresponding module to conserve power. Prior to initializing a module, set the corresponding bit in SCGCx register to enable the clock. Before turning off the clock, make sure to disable the module. Any bus access to a peripheral that has its clock disabled generates an error termination. 5.7 Module clocks The following table summarizes the clocks associated with each module. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 143 Module clocks Table 5-2. Module clocks Module Bus interface clock Internal clocks I/O interface clocks Core modules ARM Cortex-M4 core System clock Core clock -- NVIC System clock -- -- DAP System clock -- -- ITM System clock -- -- cJTAG, JTAGC -- -- JTAG_CLK DMA System clock -- -- DMA Mux Bus clock -- -- Port control Bus clock LPO -- Crossbar Switch System clock -- -- Peripheral bridges System clock Bus clock, Flash clock -- LLWU, PMC, SIM, RCM Flash clock LPO -- Mode controller Flash clock -- -- System modules MCM System clock -- -- EWM Bus clock LPO -- Watchdog timer Bus clock LPO -- Clocks MCG Flash clock MCGOUTCLK, MCGPLLCLK, MCGFLLCLK, MCGIRCLK, OSCCLK, IRC48MCLK -- OSC Bus clock OSCERCLK, OSCCLK, OSCERCLK_UNDIV, OSC32KCLK -- IRC48M -- IRC48MCLK -- Memory and memory interfaces Flash Controller System clock Flash clock -- Flash memory Flash clock -- -- FlexBus System clock -- CLKOUT EzPort System clock -- EZP_CLK Security CRC Bus clock -- -- RNGA Bus clock -- -- Analog ADC Bus clock OSCERCLK , IRC48MCLK -- CMP Bus clock -- -- DAC Bus clock -- -- VREF Flash clock -- -- Timers PDB Bus clock -- -- FlexTimers Bus clock MCGFFCLK FTM_CLKINx Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 144 Freescale Semiconductor, Inc. Chapter 5 Clock Distribution Table 5-2. Module clocks (continued) Module Bus interface clock Internal clocks I/O interface clocks PIT Bus clock -- -- LPTMR Flash clock LPO, OSCERCLK_UNDIV, MCGIRCLK, ERCLK32K -- Communication interfaces DSPI Bus clock -- DSPI_SCK I2C Bus clock -- I2C_SCL UART0, UART1 System clock -- -- UART2 Bus clock -- -- LPUART0 Bus clock LPUART0 clock -- Human-machine interfaces GPIO Platform clock -- -- 5.7.1 PMC 1-kHz LPO clock The Power Management Controller (PMC) generates a 1-kHz clock that is enabled in all modes of operation, including all low power modes except VLLS0. This 1-kHz source is commonly referred to as LPO clock or 1-kHz LPO clock. 5.7.2 IRC 48MHz clock The integrated 48 MHz internal reference clock source (IRC48MCLK) is available in High Speed Run, Run, WAIT and Stop modes of operation. IRC48MCLK is also available in Compute Only, PSTOP2 and PSTOP1 modes of operation when entered from Run mode. IRC48MCLK is forced disabled when the MCU transitions into VLPS, LLSx, and VLLSx low power modes. NOTE IRC48MCLK is not forced disabled in Stop modes and should be disabled by software prior to Stop entry unless it is required. IRC48MCLK is not forced disabled in VLPR and should be disabled by software prior to VLPR entry. IRC48MCLK is enabled via any of the following control settings while operating in these modes: KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 145 Module clocks * MCG Control register selects IRC48 MHz clock (enabled when MCG_C7[OSCSEL]=10) and either MCG is configured in an external clocking mode (PBE, BLPE, PEE, FBE or FEE) or MCG_C5[PLLCLKEN0] = 1. * SIM Control register selects IRC48 MHz clock -- enabled when SIM_SOPT2[PLLFLLSEL]=11 The IRC48MCLK is available for use as: * an oscillator reference to the MCG - from which core, system, bus, and flash clock sources can be derived * an ADC alternate clock source * clock source for LPUART communications 5.7.3 WDOG clocking The WDOG may be clocked from two clock sources as shown in the following figure. LPO WDOG clock Bus clock WDOG_STCTRLH[CLKSRC] Figure 5-2. WDOG clock generation 5.7.4 Debug trace clock The debug trace clock source can be clocked as shown in the following figure. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 146 Freescale Semiconductor, Inc. Chapter 5 Clock Distribution MCGOUTCLK TRACECLKIN Debug Core / system clock SIM_SOPT2[TRACECLKSEL] Figure 5-3. Trace clock generation 5.7.5 PORT digital filter clocking The digital filters in the PORTD module can be clocked as shown in the following figure. NOTE In stop mode, the digital input filters are bypassed unless they are configured to run from the 1 kHz LPO clock source. Bus clock PORTx digital input filter clock LPO PORTx_DFCR[CS] Figure 5-4. PORTx digital input filter clock generation 5.7.6 LPTMR clocking The prescaler and glitch filters in each of the LPTMRx modules can be clocked as shown in the following figure. NOTE The chosen clock must remain enabled if the LPTMRx is to continue operating in all required low-power modes. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 147 Module clocks MCGIRCLK LPO LPTMRx prescaler/glitch filter clock ERCLK32K OSCERCLK_UNDIV LPTMRx_PSR[PCS] Figure 5-5. LPTMRx prescaler/glitch filter clock generation 5.7.7 CLKOUT32K clocking CLKOUT32K can be driven out on either PTE0 or PTE26 as controlled by SIM_SOPT1[OSC32KOUT], overriding the existing pin mux configuration for that pin. Except for VLLS0 mode, this function is available in all other modes of operation (including LLS3, LLS2, VLLS3, VLLS2, VLLS1 and System Reset). PTE0 is available in all packages for this device. PTE26 is not available in 64-pin packages for this device. SIM_SOPT1[OSC32KSEL] SIM_SOPT1[OSC32KOUT] 01 OSC32KCLK LPO Reserved 00 Pad interface ERCLK32K 11 10 Others PTE0/CLKOUT32K Other modules Pad interface PTE26/CLKOUT32K Other modules Figure 5-6. CLKOUT32K generation 5.7.8 UART clocking UART0 and UART1 modules operate from the core/system clock, which provides higher performance level for these modules. All other UART modules operate from the bus clock. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 148 Freescale Semiconductor, Inc. Chapter 5 Clock Distribution 5.7.9 LPUART0 clocking The LPUART0 module has a selectable clock as shown in the following figure. NOTE The chosen clock must remain enabled if the LPUART0 is to continue operating in all required low-power modes. MCGIRCLK OSCERCLK LPUART0 clock MCGFLLCLK MCGPLLCLK IRC48MCLK SIM_SOPT2[PLLFLLSEL] SIM_SOPT2[LPUARTSRC] Figure 5-7. LPUART0 clock generation KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 149 Module clocks KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 150 Freescale Semiconductor, Inc. Chapter 6 Reset and Boot 6.1 Introduction The following reset sources are supported in this MCU: Table 6-1. Reset sources Reset sources POR reset System resets Debug reset Description * Power-on reset (POR) * * * * * * * * * * * External pin reset (PIN) Low-voltage detect (LVD) Computer operating properly (COP) watchdog reset Low leakage wakeup (LLWU) reset Multipurpose clock generator loss of clock (LOC) reset Multipurpose clock generator loss of lock (LOL) reset Stop mode acknowledge error (SACKERR) Software reset (SW) Lockup reset (LOCKUP) EzPort reset MDM DAP system reset * JTAG reset * nTRST reset Each of the system reset sources has an associated bit in the system reset status (SRS) registers. See the Reset Control Module for register details. The MCU exits reset in functional mode that is controlled by EZP_CS pin to select between the single chip (default) or serial flash programming (EzPort) modes. See Boot options for more details. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 151 Reset 6.2 Reset This section discusses basic reset mechanisms and sources. Some modules that cause resets can be configured to cause interrupts instead. Consult the individual peripheral chapters for more information. 6.2.1 Power-on reset (POR) When power is initially applied to the MCU or when the supply voltage drops below the power-on reset re-arm voltage level (VPOR), the POR circuit causes a POR reset condition. As the supply voltage rises, the LVD circuit holds the MCU in reset until the supply has risen above the LVD low threshold (VLVDL). The POR and LVD bits in SRS0 register are set following a POR. 6.2.2 System reset sources Resetting the MCU provides a way to start processing from a known set of initial conditions. System reset begins with the on-chip regulator in full regulation and system clocking generation from an internal reference. When the processor exits reset, it performs the following: * Reads the start SP (SP_main) from vector-table offset 0 * Reads the start PC from vector-table offset 4 * LR is set to 0xFFFF_FFFF The on-chip peripheral modules are disabled and the non-analog I/O pins are initially configured as disabled. The pins with analog functions assigned to them default to their analog function after reset. During and following a reset, the JTAG pins have their associated input pins configured as: * TDI in pull-up (PU) * TCK in pull-down (PD) * TMS in PU and associated output pin configured as: * TDO with no pull-down or pull-up KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 152 Freescale Semiconductor, Inc. Chapter 6 Reset and Boot Note that the nTRST signal is initially configured as disabled, however once configured to its JTAG functionality its associated input pin is configured as: * nTRST in PU 6.2.2.1 External pin reset (PIN) On this device, RESET is a dedicated pin. This pin is open drain and has an internal pullup device. Asserting RESET wakes the device from any mode. During a pin reset, the RCM's SRS0[PIN] bit is set. 6.2.2.1.1 RESET pin filter The RESET pin filter supports filtering from both the 1 kHz LPO clock and the bus clock. RCM_RPFC[RSTFLTSS], RCM_RPFC[RSTFLTSRW], and RCM_RPFW[RSTFLTSEL] control this functionality; see the RCM chapter. The filters are asynchronously reset by Chip POR. The reset value for each filter assumes the RESET pin is negated. For all stop modes where LPO clock is still active (Stop, VLPS, LLS, VLLS3, VLLS2, and VLLS1), the only filtering option is the LPO-based digital filter. The filtering logic either switches to bypass operation or has continued filtering operation depending on the filtering mode selected. When entering VLLS0, the RESET pin filter is disabled and bypassed. The LPO filter has a fixed filter value of 3. Due to a synchronizer on the input data, there is also some associated latency (2 cycles). As a result, 5 cycles are required to complete a transition from low to high or high to low. 6.2.2.2 Low-voltage detect (LVD) The chip includes a system for managing low voltage conditions to protect memory contents and control MCU system states during supply voltage variations. The system consists of a power-on reset (POR) circuit and an LVD circuit with a user-selectable trip voltage. The LVD system is always enabled in hsrun, normal run, wait, or stop mode. The LVD system is disabled when entering VLPx, LLS, or VLLSx modes. The LVD can be configured to generate a reset upon detection of a low voltage condition by setting the PMC's LVDSC1[LVDRE] bit to 1. The low voltage detection threshold is determined by the PMC's LVDSC1[LVDV] field. After an LVD reset has occurred, the KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 153 Reset LVD system holds the MCU in reset until the supply voltage has risen above the low voltage detection threshold. The RCM's SRS0[LVD] bit is set following either an LVD reset or POR. 6.2.2.3 Computer operating properly (COP) watchdog timer The computer operating properly (COP) watchdog timer (WDOG) monitors the operation of the system by expecting periodic communication from the software. This communication is generally known as servicing (or refreshing) the COP watchdog. If this periodic refreshing does not occur, the watchdog issues a system reset. The COP reset causes the RCM's SRS0[WDOG] bit to set. 6.2.2.4 Low leakage wakeup (LLWU) The LLWU module provides the means for a number of external pins, the RESET pin, and a number of internal peripherals to wake the MCU from low leakage power modes. The LLWU module is functional only in low leakage power modes. * In LLS mode, only the RESET pin via the LLWU can generate a system reset. * In VLLSx modes, all enabled inputs to the LLWU can generate a system reset. After a system reset, the LLWU retains the flags indicating the input source of the last wakeup until the user clears them. NOTE Some flags are cleared in the LLWU and some flags are required to be cleared in the peripheral module. Refer to the individual peripheral chapters for more information. 6.2.2.5 Multipurpose clock generator loss-of-clock (LOC) The MCG module supports an external reference clock. If the C6[CME] bit in the MCG module is set, the clock monitor is enabled. If the external reference falls below floc_low or floc_high, as controlled by the C2[RANGE] field in the MCG module, the MCU resets. The RCM's SRS0[LOC] bit is set to indicate this reset source. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 154 Freescale Semiconductor, Inc. Chapter 6 Reset and Boot NOTE To prevent unexpected loss of clock reset events, all clock monitors should be disabled before entering any low power modes, including VLPR and VLPW. 6.2.2.6 MCG loss-of-lock (LOL) reset The MCG includes a PLL loss-of-lock detector. The detector is enabled when configured for PEE and lock has been achieved. If the MCG_C8[LOLRE] bit in the MCG module is set and the PLL lock status bit (MCG_S[LOLS0]) becomes set, the MCU resets. The RCM_SRS0[LOL] bit is set to indicate this reset source. NOTE This reset source does not cause a reset if the chip is in any stop mode. 6.2.2.7 Stop mode acknowledge error (SACKERR) This reset is generated if the core attempts to enter stop mode, but not all modules acknowledge stop mode within 1025 cycles of the 1 kHz LPO clock. A module might not acknowledge the entry to stop mode if an error condition occurs. The error can be caused by a failure of an external clock input to a module. 6.2.2.8 Software reset (SW) The SYSRESETREQ bit in the NVIC application interrupt and reset control register can be set to force a software reset on the device. (See ARM's NVIC documentation for the full description of the register fields, especially the VECTKEY field requirements.) Setting SYSRESETREQ generates a software reset request. This reset forces a system reset of all major components except for the debug module. A software reset causes the RCM's SRS1[SW] bit to set. 6.2.2.9 Lockup reset (LOCKUP) The LOCKUP gives immediate indication of seriously errant kernel software. This is the result of the core being locked because of an unrecoverable exception following the activation of the processor's built in system state protection hardware. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 155 Reset The LOCKUP condition causes a system reset and also causes the RCM's SRS1[LOCKUP] bit to set. 6.2.2.10 EzPort reset The EzPort supports a system reset request via EzPort signaling. The EzPort generates a system reset request following execution of a Reset Chip (RESET) command via the EzPort interface. This method of reset allows the chip to boot from flash memory after it has been programmed by an external source. The EzPort is enabled or disabled by the EZP_CS pin. An EzPort reset causes the RCM's SRS1[EZPT] bit to set. 6.2.2.11 MDM-AP system reset request Set the system reset request bit in the MDM-AP control register to initiate a system reset. This is the primary method for resets via the JTAG/SWD interface. The system reset is held until this bit is cleared. Set the core hold reset bit in the MDM-AP control register to hold the core in reset as the rest of the chip comes out of system reset. 6.2.3 MCU Resets A variety of resets are generated by the MCU to reset different modules. 6.2.3.1 POR Only The POR Only reset asserts on the POR reset source only. It resets the PMC and System Register File. The POR Only reset also causes all other reset types to occur. 6.2.3.2 Chip POR not VLLS The Chip POR not VLLS reset asserts on POR and LVD reset sources. It resets parts of the SMC and SIM. It also resets the LPTMR. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 156 Freescale Semiconductor, Inc. Chapter 6 Reset and Boot The Chip POR not VLLS reset also causes these resets to occur: Chip POR, Chip Reset not VLLS, and Chip Reset (including Early Chip Reset). 6.2.3.3 Chip POR The Chip POR asserts on POR, LVD, and VLLS Wakeup reset sources. It resets the Reset Pin Filter registers and parts of the SIM and MCG. The Chip POR also causes the Chip Reset (including Early Chip Reset) to occur. 6.2.3.4 Chip Reset not VLLS The Chip Reset not VLLS reset asserts on all reset sources except a VLLS Wakeup that does not occur via the RESET_b pin. It resets parts of the SMC, LLWU, and other modules that remain powered during VLLS mode. The Chip Reset not VLLS reset also causes the Chip Reset (including Early Chip Reset) to occur. 6.2.3.5 Early Chip Reset The Early Chip Reset asserts on all reset sources. It resets only the flash memory module. It negates before flash memory initialization begins ("earlier" than when the Chip Reset negates). 6.2.3.6 Chip Reset Chip Reset asserts on all reset sources and only negates after flash initialization has completed and the RESET_b pin has also negated. It resets the remaining modules (the modules not reset by other reset types). 6.2.4 Reset Pin For all reset sources except a VLLS Wakeup that does not occur via the RESET pin, the RESET pin is driven low by the MCU for at least 128 bus clock cycles and until flash initialization has completed. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 157 Reset After flash initialization has completed, the RESET pin is released, and the internal Chip Reset negates after the RESET pin is pulled high. Keeping the RESET pin asserted externally delays the negation of the internal Chip Reset. 6.2.5 Debug resets The following sections detail the debug resets available on the device. 6.2.5.1 JTAG reset The JTAG module generate a system reset when certain IR codes are selected. This functional reset is asserted when EzPort, EXTEST, HIGHZ and CLAMP instructions are active. The reset source from the JTAG module is released when any other IR code is selected. A JTAG reset causes the RCM's SRS1[JTAG] bit to set. 6.2.5.2 nTRST reset The nTRST pin causes a reset of the JTAG logic when asserted. Asserting the nTRST pin allows the debugger to gain control of the TAP controller state machine (after exiting LLS or VLLSx) without resetting the state of the debug modules. The nTRST pin does not cause a system reset. 6.2.5.3 Resetting the Debug subsystem Use the CDBGRSTREQ bit within the SWJ-DP CTRL/STAT register to reset the debug modules. However, as explained below, using the CDBGRSTREQ bit does not reset all debug-related registers. CDBGRSTREQ resets the debug-related registers within the following modules: * * * * SWJ-DP AHB-AP TPIU MDM-AP (MDM control and status registers) CDBGRSTREQ does not reset the debug-related registers within the following modules: * CM4 core (core debug registers: DHCSR, DCRSR, DCRDR, DEMCR) * FPB KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 158 Freescale Semiconductor, Inc. Chapter 6 Reset and Boot * * * * * * DWT ITM NVIC Crossbar bus switch1 AHB-AP1 Private peripheral bus1 6.3 Boot This section describes the boot sequence, including sources and options. 6.3.1 Boot sources This device only supports booting from internal flash. Any secondary boot must go through an initialization sequence in flash. 6.3.2 Boot options The device's functional mode is controlled by the state of the EzPort chip select (EZP_CS) pin during reset. The device can be in single chip (default) or serial flash programming mode (EzPort). While in single chip mode the device can be in run or various low power modes mentioned in Power mode transitions. Table 6-2. Mode select decoding EzPort chip select (EZP_CS) Description 0 Serial flash programming mode (EzPort) 1 Single chip (default) 1. CDBGRSTREQ does not affect AHB resources so that debug resources on the private peripheral bus are available during System Reset. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 159 Boot 6.3.3 FOPT boot options The flash option register (FOPT) in the flash memory module allows the user to customize the operation of the MCU at boot time. The register contains read-only bits that are loaded from the NVM's option byte in the flash configuration field. The user can reprogram the option byte in flash to change the FOPT values that are used for subsequent resets. For more details on programming the option byte, refer to the flash memory chapter. The MCU uses the FOPT register bits to configure the device at reset as shown in the following table. NOTE Reserved bits in the option byte should be left in their default erased state of logic 1. FOPT[7:0] = 0x00 is not a valid configuration. FOPT register is written to 0xFF if the contents of NVM's option byte in the flash configuration field is 0x00. Table 6-3. Flash Option Register Bit Definitions Bit Num Field Value Definition 7-6 Reserved Reserved for future expansion. 5 FAST_INIT Select initialization speed on POR, VLLSx, and any system reset. 0 Slower initialization. The Flash initialization will be slower with the benefit of reduced average current during this time. The duration of the recovery will be controlled by the clock divider selection determined by the LPBOOT setting. 1 Fast Initialization.The Flash has faster recoveries at the expense of higher current during these times. 4-3 Reserved Reserved for future expansion. 2 NMI_DIS Enable/disable control for the NMI function. 1 0 EZPORT_DIS LPBOOT 0 NMI interrupts are always blocked. The associated pin continues to default to NMI pin controls with internal pullup enabled. 1 NMI pin/interrupts reset default to enabled. Enable/disable EzPort function. 0 EzPort operation is disabled. The device always boots to normal CPU execution and the state of EZP_CS signal during reset is ignored. This option avoids inadvertent resets into EzPort mode if the EZP_CS/NMI pin is used for its NMI function. 1 EzPort operation is enabled. The state of EZP_CS pin during reset determines if device enters EzPort mode. Control the reset value of OUTDIVx values in SIM_CLKDIV1 register. Larger divide value selections produce lower average power consumption during POR, VLLSx recoveries and reset sequencing and after reset exit. The recovery times are also extended if the FAST_INIT option is not selected. 0 Low-power boot: OUTDIVx values in SIM_CLKDIV1 register are auto-configured at reset exit for higher divide values that produce lower power consumption at reset exit. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 160 Freescale Semiconductor, Inc. Chapter 6 Reset and Boot Table 6-3. Flash Option Register Bit Definitions (continued) Bit Num Field Value Definition * Core and system clock divider (OUTDIV1) and bus clock divider (OUTDIV2) are 0x7 (divide by 8) * Flash clock divider (OUTDIV4) and FlexBus clock divider (OUTDIV3) are 0xF (divide by 16) 1 Normal boot: OUTDIVx values in SIM_CLKDIV1 register are auto-configured at reset exit for higher frequency values that produce faster operating frequencies at reset exit. * Core and system clock divider (OUTDIV1) and bus clock divider (OUTDIV2) are 0x0 (divide by 1) * Flash clock divider (OUTDIV4) and FlexBus clock divider (OUTDIV3) are 0x1 (divide by 2) 6.3.4 Boot sequence At power up, the on-chip regulator holds the system in a POR state until the input supply is above the POR threshold. The system continues to be held in this static state until the internally regulated supplies have reached a safe operating voltage as determined by the LVD. The Mode Controller reset logic then controls a sequence to exit reset. 1. A system reset is held on internal logic, the RESET pin is driven out low, and the MCG is enabled in its default clocking mode. 2. Required clocks are enabled (Core Clock, System Clock, Flash Clock, and any Bus Clocks that do not have clock gate control reset to disabled). 3. The system reset on internal logic continues to be held, but the Flash Controller is released from reset and begins initialization operation while the Reset Control logic continues to drive the RESET pin out low. 4. Early in reset sequencing the NVM option byte is read and stored to the Flash Memory module's FOPT register. If the LPBOOT is programmed for an alternate clock divider reset value, the system/core clock is switched to a slower clock speed. If the FAST_INIT bit is programmed clear, the Flash initialization switches to slower clock resulting longer recovery times. 5. When Flash Initialization completes, the RESET pin is released. If RESET continues to be asserted (an indication of a slow rise time on the RESET pin or external drive in low), the system continues to be held in reset. Once the RESET pin is detected high, the Core clock is enabled and the system is released from reset. EzPort mode is selected instead of the normal CPU execution if EZP_CS is low when the internal reset is deasserted. EzPort mode can be disabled by programming the FOPT[EZPORT_DIS] field in the Flash Memory module. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 161 Boot 6. When the system exits reset, the processor sets up the stack, program counter (PC), and link register (LR). The processor reads the start SP (SP_main) from vector-table offset 0. The core reads the start PC from vector-table offset 4. LR is set to 0xFFFF_FFFF. What happens next depends on the NMI input and the FOPT[NMI_DIS] field in the Flash Memory module: * If the NMI input is high or the NMI function is disabled in the NMI_DIS field, the CPU begins execution at the PC location. * If the NMI input is low and the NMI function is enabled in the NMI_DIS field, this results in an NMI interrupt. The processor executes an Exception Entry and reads the NMI interrupt handler address from vector-table offset 8. The CPU begins execution at the NMI interrupt handler. Subsequent system resets follow this same reset flow. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 162 Freescale Semiconductor, Inc. Chapter 7 Power Management 7.1 Introduction This chapter describes the various chip power modes and functionality of the individual modules in these modes. 7.2 Clocking modes Information found here describes the various clocking modes supported on this device. 7.2.1 Partial Stop Partial Stop is a clocking option that can be taken instead of entering Stop mode and is configured in the SMC Stop Control Register (SMC_STOPCTRL). The Stop mode is only partially entered, which leaves some additional functionality alive at the expense of higher power consumption. Partial Stop can be entered from either Run mode or VLP Run mode. When configured for PSTOP2, only the core and system clocks are gated and the bus clock remains active. The bus masters and bus slaves clocked by the system clock enter Stop mode, but the bus slaves clocked by bus clock remain in Run (or VLP Run) mode. The clock generators in the MCG and the on-chip regulator in the PMC also remain in Run (or VLP Run) mode. Exit from PSTOP2 can be initiated by a reset, an asynchronous interrupt from a bus master or bus slave clocked by the system clock, or a synchronous interrupt from a bus slave clocked by the bus clock. If configured, a DMA request (using the asynchronous DMA wakeup) can also be used to exit Partial Stop for the duration of a DMA transfer before the device is transitioned back into PSTOP2. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 163 Clocking modes When configured for PSTOP1, both the system clock and bus clock are gated. All bus masters and bus slaves enter Stop mode, but the clock generators in the MCG and the onchip regulator in the PMC remain in Run (or VLP Run) mode. Exit from PSTOP1 can be initiated by a reset or an asynchronous interrupt from a bus master or bus slave. If configured, an asynchronous DMA request can also be used to exit Partial Stop for the duration of a DMA transfer before the device is transitioned back into PSTOP1. PSTOP1 is functionally similar to Stop mode, but offers faster wake-up at the expense of higher power consumption. Another benefit is that it keeps all of the MCG clocks enabled, which can be useful for some of the asynchronous peripherals that can remain functional in Stop modes. 7.2.2 DMA Wakeup The DMA can be configured to wake the device on a DMA request whenever it is placed in Stop mode. The wake-up is configured per DMA channel and is supported in Compute Operation, PSTOP, STOP, and VLPS low power modes. When a DMA wake-up is detected in PSTOP, STOP or VLPS then the device will initiate a normal exit from the low power mode. This can include restoring the on-chip regulator and internal power switches, enabling the clock generators in the MCG, enabling the system and bus clocks (but not the core clock) and negating the stop mode signal to the bus masters and bus slaves. The only difference is that the CPU will remain in the low power mode with the CPU clock disabled. During Compute Operation, a DMA wake-up will initiate a normal exit from Compute Operation. This includes enabling the clocks and negating the stop mode signal to the bus masters and bus slaves. The core clock always remains enabled during Compute Operation. Since the DMA wakeup will enable the clocks and negate the stop mode signals to all bus masters and slaves, software needs to ensure that bus masters and slaves that are not involved with the DMA wake-up and transfer remain in a known state. That can be accomplished by disabling the modules before entry into the low power mode or by setting the Doze enable bit in selected modules. Once the DMA request that initiated the wake-up negates and the DMA completes the current transfer, the device will transition back to the original low-power mode. This includes requesting all non-CPU bus masters to enter Stop mode and then requesting bus slaves to enter Stop mode. In STOP and VLPS modes, MCG and PMC would then also enter their appropriate modes. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 164 Freescale Semiconductor, Inc. Chapter 7 Power Management NOTE If the requested DMA transfer cannot cause the DMA request to negate, then the device will remain in a higher power state until the low power mode is fully exited. An enabled DMA wake-up can cause an aborted entry into the low power mode, if the DMA request asserts during the stop mode entry sequence (or reentry if the request asserts during a DMA wakeup) and can cause the SMC to assert its Stop Abort flag. Once the DMA wake-up completes, entry into the low power mode will restart. An interrupt that occurs during a DMA wake-up will cause an immediate exit from the low power mode (this is optional for Compute Operation) without impacting the DMA transfer. A DMA wake-up can be generated by either a synchronous DMA request or an asynchronous DMA request. Not all peripherals can generate an asynchronous DMA request in stop modes, although in general if a peripheral can generate synchronous DMA requests and also supports asynchronous interrupts in stop modes, then it can generate an asynchronous DMA request. 7.2.3 Compute Operation Compute Operation is an execution or compute-only mode of operation that keeps the CPU enabled with full access to the SRAM and Flash read port, but places all other bus masters and bus slaves into their stop mode. Compute Operation can be enabled in Run mode, HSRUN mode, or VLP Run mode. NOTE Do not enter any stop mode without first exiting Compute Operation. Because Compute Operation reuses the stop mode logic (including the staged entry with bus masters disabled before bus slaves), any bus master or bus slave that can remain functional in stop mode also remains functional in Compute Operation, including generation of asynchronous interrupts and DMA requests. When enabling Compute Operation in Run mode, module functionality for bus masters and slaves is the equivalent of STOP mode. When enabling Compute Operation in VLP Run mode, module functionality for bus masters and slaves is the equivalent of VLPS mode. The MCG, PMC, SRAM and Flash read port are not affected by Compute Operation, although the Flash register interface is disabled. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 165 Clocking modes During Compute Operation, the AIPS peripheral and external memory (FlexBus) space is disabled and attempted accesses generate bus errors. The private peripheral bus (PPB) remains accessible during Compute Operation, including the MCM, System Control Space (SCS) (for NVIC and FPU), and SysTick. Although access to the GPIO registers is supported, the GPIO port data input registers do not return valid data since clocks are disabled to the Port Control and Interrupt modules. By writing to the GPIO port data output registers, it is possible to control those GPIO ports that are configured as output pins. Compute Operation is controlled by the CPO register in the MCM, which is only accessible to the CPU. Setting or clearing the CPOREQ bit in the MCM initiates entry or exit into Compute Operation. Compute Operation can also be configured to exit automatically on detection of an interrupt, which is required in order to service most interrupts. Only the core system interrupts (exceptions, including NMI and SysTick) and any edge sensitive interrupts can be serviced without exiting Compute Operation. When entering Compute Operation, the CPOACK status bit indicates when entry has completed. When exiting Compute Operation in Run mode, the CPOACK status bit negates immediately. When exiting Compute Operation in VLP Run mode, the exit is delayed to allow the PMC to handle the change in power consumption. This delay means the CPOACK bit is polled to determine when the AIPS peripheral space can be accessed without generating a bus error. The DMA wakeup is also supported during Compute Operation and causes the CPOACK status bit to clear and the AIPS peripheral space to be accessible for the duration of the DMA wakeup. At the completion of the DMA wakeup, the device transitions back into Compute Operation. 7.2.4 Peripheral Doze Several peripherals support a Peripheral Doze mode, where a register bit can be used to disable the peripheral for the duration of a low-power mode. The flash memory can also be placed in a low-power state during Peripheral Doze via a register bit in the SIM. Peripheral Doze is defined to include all of the modes of operation listed below. * The CPU is in Wait mode. * The CPU is in Stop mode, including the entry sequence and for the duration of a DMA wakeup. * The CPU is in Compute Operation, including the entry sequence and for the duration of a DMA wakeup. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 166 Freescale Semiconductor, Inc. Chapter 7 Power Management Peripheral Doze can therefore be used to disable selected bus masters or slaves for the duration of WAIT or VLPW mode. It can also be used to disable selected bus slaves immediately on entry into any stop mode (or Compute Operation), instead of waiting for the bus masters to acknowledge the entry as part of the stop entry sequence. Finally, it can be used to disable selected bus masters or slaves that should remain inactive during a DMA wakeup. If the flash memory is not being accessed during WAIT and PSTOP modes, then the Flash Doze mode can be used to reduce power consumption, at the expense of a slightly longer wake-up when executing code and vectors from flash. It can also be used to reduce power consumption during Compute Operation when executing code and vectors from SRAM. 7.2.5 Clock Gating To conserve power, the clocks to most modules can be turned off using the SCGCx registers in the SIM module. These bits are cleared after any reset, which disables the clock to the corresponding module. Prior to initializing a module, set the corresponding bit in the SCGCx register to enable the clock. Before turning off the clock, make sure to disable the module. For more details, refer to the clock distribution and SIM chapters. 7.3 Power Modes Description The power management controller (PMC) provides multiple power options to allow the user to optimize power consumption for the level of functionality needed. Depending on the stop requirements of the user application, a variety of stop modes are available that provide state retention, partial power down or full power down of certain logic and/or memory. I/O states are held in all modes of operation. The following table compares the various power modes available. For Run and VLPR mode there is a corresponding wait and stop mode. Wait modes are similar to ARM sleep modes. Stop modes (VLPS, STOP) are similar to ARM sleep deep mode. The very low power run (VLPR) operating mode can drastically reduce runtime power when the maximum bus frequency is not required to handle the application needs. Stop mode entry is not supported directly from HSRUN and requires transition to Run prior to an attempt to enter a stop mode. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 167 Power Modes Description The three primary modes of operation are run, wait and stop. The WFI instruction invokes both wait and stop modes for the chip. The primary modes are augmented in a number of ways to provide lower power based on application needs. Table 7-1. Chip power modes Chip mode Description Normal run Default mode out of reset; on-chip voltage regulator is on. Core mode Normal recovery method Run - Run - High Speed run Allows maximum performance of chip. In this state, the MCU is able to operate at a faster frequency compared to normal run mode. Normal Wait via WFI Allows peripherals to function while the core is in sleep mode, reducing power. NVIC remains sensitive to interrupts; peripherals continue to be clocked. Sleep Interrupt Normal Stop via WFI Places chip in static state. Lowest power mode that retains all registers while maintaining LVD protection. NVIC is disabled; AWIC is used to wake up from interrupt; peripheral clocks are stopped. Sleep Deep Interrupt Run - Sleep Interrupt VLPS (Very Low Places chip in static state with LVD operation off. Lowest power mode Power Stop)-via with ADC and pin interrupts functional. Peripheral clocks are stopped, WFI but LPTimer, CMP, DAC can be used. NVIC is disabled (FCLK = OFF); AWIC is used to wake up from interrupt. On-chip voltage regulator is in a low power mode that supplies only enough power to run the chip at a reduced frequency. All SRAM is operating (content retained and I/O states held). Sleep Deep Interrupt LLS3 (Low State retention power mode. Most peripherals are in state retention Leakage Stop3) mode (with clocks stopped), but LLWU, LPTimer, CMP, DAC can be used. NVIC is disabled; LLWU is used to wake up. Sleep Deep Wakeup Interrupt1 Sleep Deep Wakeup Interrupt1 Sleep Deep Wakeup Reset2 VLPR (Very Low On-chip voltage regulator is in a low power mode that supplies only Power Run) enough power to run the chip at a reduced frequency. Reduced frequency Flash access mode (1 MHz); LVD off; internal oscillator provides a low power 4 MHz source for the core, the bus and the peripheral clocks. VLPW (Very Low Power Wait) -via WFI Same as VLPR but with the core in sleep mode to further reduce power; NVIC remains sensitive to interrupts (FCLK = ON). On-chip voltage regulator is in a low power mode that supplies only enough power to run the chip at a reduced frequency. NOTE: The LLWU interrupt must not be masked by the interrupt controller to avoid a scenario where the system does not fully exit stop mode on an LLS recovery. All SRAM is operating (content retained and I/O states held). LLS2 (Low State retention power mode. Most peripherals are in state retention Leakage Stop2) mode (with clocks stopped), but LLWU, LPTimer, CMP, DAC can be used. NVIC is disabled; LLWU is used to wake up. NOTE: The LLWU interrupt must not be masked by the interrupt controller to avoid a scenario where the system does not fully exit stop mode on an LLS recovery. A portion of SRAM_U remains powered on (content retained and I/O states held). VLLS3 (Very Low Leakage Stop3) Most peripherals are disabled (with clocks stopped), but LLWU, LPTimer, CMP, DAC can be used. NVIC is disabled; LLWU is used to wake up. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 168 Freescale Semiconductor, Inc. Chapter 7 Power Management Table 7-1. Chip power modes (continued) Chip mode Description Core mode Normal recovery method Sleep Deep Wakeup Reset2 Sleep Deep Wakeup Reset2 Sleep Deep Wakeup Reset2 SRAM_U and SRAM_L remain powered on (content retained and I/O states held). VLLS2 (Very Low Leakage Stop2) Most peripherals are disabled (with clocks stopped), but LLWU, LPTimer, CMP, DAC can be used. NVIC is disabled; LLWU is used to wake up. SRAM_L is powered off. A portion of SRAM_U remains powered on (content retained and I/O states held). VLLS1 (Very Low Leakage Stop1) Most peripherals are disabled (with clocks stopped), but LLWU, LPTimer, CMP, DAC can be used. NVIC is disabled; LLWU is used to wake up. All of SRAM_U and SRAM_L are powered off. The 32-byte system register file remain powered for customer-critical data. VLLS0 (Very Low Leakage Stop 0) Most peripherals are disabled (with clocks stopped), but LLWU can be used. NVIC is disabled; LLWU is used to wake up. All of SRAM_U and SRAM_L are powered off. The 32-byte system register file remain powered for customer-critical data. The POR detect circuit can be optionally powered off. 1. Resumes normal run mode operation by executing the LLWU interrupt service routine. 2. Follows the reset flow with the LLWU interrupt flag set for the NVIC. 7.4 Entering and exiting power modes The WFI instruction invokes wait and stop modes for the chip. The processor exits the low-power mode via an interrupt. The Nested Vectored Interrupt Controller (NVIC) describes interrupt operation and what peripherals can cause interrupts. NOTE The WFE instruction can have the side effect of entering a lowpower mode, but that is not its intended usage. See ARM documentation for more on the WFE instruction. Recovery from VLLSx is through the wake-up Reset event. The chip wake-ups from VLLSx by means of reset, an enabled pin or enabled module. See the table "LLWU inputs" in the LLWU configuration section for a list of the sources. The wake-up flow from VLLSx is through reset. The wakeup bit in the SRS registers in the RCM is set indicating that the chip is recovering from a low power mode. Code execution begins; however, the I/O pins are held in their pre low power mode entry KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 169 Power mode transitions states, and the system oscillator and MCG registers are reset (even if EREFSTEN had been set before entering VLLSx). Software must clear this hold by writing a 1 to the ACKISO bit in the Regulator Status and Control Register in the PMC module. NOTE To avoid unwanted transitions on the pins, software must reinitialize the I/O pins to their pre-low-power mode entry states before releasing the hold. If the oscillator was configured to continue running during VLLSx modes, it must be reconfigured before the ACKISO bit is cleared. The oscillator configuration within the MCG is cleared after VLLSx recovery and the oscillator will stop when ACKISO is cleared unless the register is re-configured. 7.5 Power mode transitions The following figure shows the power mode transitions. Any reset always brings the chip back to the normal run state. In run, wait, and stop modes active power regulation is enabled. The VLPx modes offer a lower power operating mode than normal modes. VLPR and VLPW are limited in frequency. The LLS and VLLSx mode(s) are the lowest power stop modes based on amount of logic or memory that is required to be retained by the application. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 170 Freescale Semiconductor, Inc. Chapter 7 Power Management Any RESET VLPW HSRUN 4 5 12 VLPR WAIT 1 3 RUN 7 2 STOP 6 VLPS 10 8 9 LLS VLLS 11 Figure 7-1. Power mode state transition diagram 7.6 Power modes shutdown sequencing When entering stop or other low-power modes, the clocks are shut off in an orderly sequence to safely place the chip in the targeted low-power state. All low-power entry sequences are initiated by the core executing an WFI instruction. The ARM core's outputs, SLEEPDEEP and SLEEPING, trigger entry to the various low-power modes: * System level wait and VLPW modes equate to: SLEEPING & SLEEPDEEP * All other low power modes equate to: SLEEPING & SLEEPDEEP When entering the non-wait modes, the chip performs the following sequence: KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 171 Flash Program Restrictions * Shuts off Core Clock and System Clock to the ARM Cortex-M4 core immediately. * Polls stop acknowledge indications from the non-core crossbar masters (DMA), supporting peripherals (SPI, PIT, RNG) and the Flash Controller for indications that System Clocks, Bus Clock and/or Flash Clock need to be left enabled to complete a previously initiated operation, effectively stalling entry to the targeted low power mode. When all acknowledges are detected, System Clock, Bus Clock and Flash Clock are turned off at the same time. * MCG and Mode Controller shut off clock sources and/or the internal supplies driven from the on-chip regulator as defined for the targeted low power mode. In wait modes, most of the system clocks are not affected by the low power mode entry. The Core Clock to the ARM Cortex-M4 core is shut off. Some modules support stop-inwait functionality and have their clocks disabled under these configurations. The debugger modules support a transition from stop, wait, VLPS, and VLPW back to a halted state when the debugger is enabled. This transition is initiated by setting the Debug Request bit in MDM-AP control register. As part of this transition, system clocking is reestablished and is equivalent to normal run/VLPR mode clocking configuration. 7.7 Flash Program Restrictions The flash memory on this device should not be programmed or erased while operating in High Speed Run or VLPR power modes. 7.8 Module Operation in Low Power Modes The following table illustrates the functionality of each module while the chip is in each of the low power modes. The standard behavior is shown with some exceptions for Compute Operation (CPO) and Partial Stop2 (PSTOP2). (Debug modules are discussed separately; see Debug in Low Power Modes.) Number ratings (such as 2 MHz and 1 Mbit/s) represent the maximum frequencies or maximum data rates per mode. Also, these terms are used: * FF = Full functionality. In VLPR and VLPW the system frequency is limited, but if a module does not have a limitation in its functionality, it is still listed as FF. * Async operation = Fully functional with alternate clock source, provided the selected clock source remains enabled * static = Module register states and associated memories are retained. * powered = Memory is powered to retain contents. * low power = Memory is powered to retain contents in a lower power state KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 172 Freescale Semiconductor, Inc. Chapter 7 Power Management * OFF = Modules are powered off; module is in reset state upon wakeup. For clocks, OFF means disabled. * wakeup = Modules can serve as a wakeup source for the chip. Table 7-2. Module operation in low power modes Modules VLPR VLPW Stop VLPS LLSx VLLSx static static OFF Core modules NVIC FF FF static Mode Controller FF FF FF FF FF FF static static static static FF FF2 low power low power ON low power low power low power in VLLS2/3, OFF in VLLS0/1 System modules LLWU1 Regulator LVD disabled disabled ON disabled disabled disabled Brown-out Detection ON ON ON ON ON ON in VLLS1/2/3, optionally disabled in VLLS03 DMA FF FF static OFF Async operation Async operation Async operation in CPO Watchdog FF FF FF FF static OFF EWM FF static static static static OFF ON ON ON in VLLS1/2/3, OFF in VLLS0 static in CPO FF in PSTOP2 Clocks 1kHz LPO ON ON ON OSCERCLK max of 16 MHz crystal OSCERCLK max of 16 MHz crystal OSCERCLK optional MCG 4 MHz IRC 4 MHz IRC Core clock 4 MHz max OFF OFF Platform clock 4 MHz max 4 MHz max System clock 4 MHz max System oscillator (OSC) OSCERCLK limited to low limited to low max of 16 MHz range/low power range/low power crystal in VLLS1/2/3, OFF in VLLS0 static static MCGIRCLK MCGIRCLK optional ; PLL optional (4 MHz optionally on but IRC only). gated static - no clock output OFF OFF OFF OFF OFF OFF OFF OFF 4 MHz max OFF OFF OFF OFF 4 MHz max OFF OFF OFF OFF OFF in CPO Bus clock 4 MHz max OFF in CPO 50 MHz max in PSTOP2 from RUN Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 173 Module Operation in Low Power Modes Table 7-2. Module operation in low power modes (continued) Modules VLPR VLPW Stop VLPS LLSx VLLSx OFF OFF 4 MHz max in PSTOP2 from VLPR Memory and memory interfaces Flash 1 MHz max access - no program/erase low power low power low power low power low power low power low power powered powered powered powered powered powered FF, disabled in CPO FF static static static OFF EzPort disabled disabled disabled disabled disabled disabled UART0, UART1 250 kbit/s 250 kbit/s static, wakeup on edge static, wakeup on edge static OFF 250 kbit/s static, wakeup on edge static, wakeup on edge static OFF static OFF static static OFF static, address match wakeup static OFF No register access in CPO System RAM (SRAM_U and SRAM_L) 4 System Register files FlexBus low power in low power in LLS3, partial in VLLS3, partial in LLS2 VLLS2; otherwise OFF Communication interfaces static, wakeup on edge in CPO UART2 250kbit/s static, wakeup on edge in CPO LPUART0 4 Mbps FF in PSTOP2 4 Mbps Async operation in CPO SPI Async operation Async operation FF in PSTOP2 1 Mbit/s (slave) 1 Mbit/s (slave) static 2 Mbit/s (master) 2 Mbit/s (master) FF in PSTOP2 200 kbit/s static, address match wakeup static in CPO I2C 200 kbit/s static, address match wakeup in CPO FF in PSTOP2 Security CRC FF FF static static static OFF FF FF static static static OFF static in CPO static in CPO static static OFF static in CPO RNG Timers FTM FF FF static in CPO static FF in PSTOP2 Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 174 Freescale Semiconductor, Inc. Chapter 7 Power Management Table 7-2. Module operation in low power modes (continued) Modules PIT VLPR VLPW Stop VLPS LLSx VLLSx FF FF static static static OFF static static OFF static in CPO PDB FF FF in PSTOP2 FF static in CPO LPTMR FF static FF in PSTOP2 FF Async operation Async operation Async operation FF in PSTOP2 Async operation5 Analog 16-bit ADC FF FF ADACK and ALTCLK clocks only in CPO ADACK, ADACK and ALTCLK, and ALTCLK clocks ALTCLK2 clocks only only static OFF HS or LS compare LS compare LS compare in VLLS1/2/3, OFF in VLLS0 static static static, OFF in VLLS0 FF in PSTOP2 CMP6 FF FF HS or LS compare in CPO 6-bit DAC FF HS or LS compare FF in PSTOP2 FF static in CPO static FF in PSTOP2 VREF FF FF FF FF static OFF 12-bit DAC FF FF static static static static static output, wakeup input static, pins latched OFF, pins latched static in CPO FF in PSTOP2 Human-machine interfaces GPIO FF FF GPIO write only in CPO static output, wakeup input FF in PSTOP2 1. Using the LLWU module, the external pins available for this chip do not require the associated peripheral function to be enabled. It only requires the function controlling the pin (GPIO or peripheral) to be configured as an input to allow a transition to occur to the LLWU. 2. Since LPO clock source is disabled, filters will be bypassed during VLLS0 3. The SMC_STOPCTRL[PORPO] bit in the SMC module controls this option. 4. A 32 KB portion of SRAM_U block is in low power when MCU is in low power modes LLS2 and VLLS2. The remaining System RAM is OFF in LLS2 and VLLS2. 5. System OSC and LPO clock sources are not available in VLLS0. Pulse counting is available in all modes. 6. CMP in stop or VLPS supports high speed or low speed external pin to pin or external pin to DAC compares. CMP in LLSx or VLLSx only supports low speed external pin to pin or external pin to DAC compares. Windowed, sampled & filtered modes of operation are not available while in stop, VLPS, LLSx, or VLLSx modes. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 175 Module Operation in Low Power Modes KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 176 Freescale Semiconductor, Inc. Chapter 8 Security 8.1 Introduction This device implements security based on the mode selected from the flash module. The following sections provide an overview of flash security and details the effects of security on non-flash modules. 8.2 Flash Security The flash module provides security information to the MCU based on the state held by the FSEC[SEC] bits. The MCU, in turn, confirms the security request and limits access to flash resources. During reset, the flash module initializes the FSEC register using data read from the security byte of the flash configuration field. NOTE The security features apply only to external accesses via debug and EzPort. CPU accesses to the flash are not affected by the status of FSEC. In the unsecured state all flash commands are available to the programming interfaces (JTAG and EzPort), as well as user code execution of Flash Controller commands. When the flash is secured (FSEC[SEC] = 00, 01, or 11), programmer interfaces are only allowed to launch mass erase operations and have no access to memory locations. Further information regarding the flash security options and enabling/disabling flash security is available in the Flash Memory Module. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 177 Security Interactions with other Modules 8.3 Security Interactions with other Modules The flash security settings are used by the SoC to determine what resources are available. The following sections describe the interactions between modules and the flash security settings or the impact that the flash security has on non-flash modules. 8.3.1 Security interactions with FlexBus When flash security is enabled, SIM_SOPT2[FBSL] enables/disables off-chip accesses through the FlexBus interface. The FBSL bitfield also has an option to allow opcode and operand accesses or only operand accesses. 8.3.2 Security Interactions with EzPort When flash security is active the MCU can still boot in EzPort mode. The EzPort holds the flash logic in NVM special mode and thus limits flash operation when flash security is active. While in EzPort mode and security is active, flash bulk erase (BE) can still be executed. The write FCCOB registers (WRFCCOB) command is limited to the mass erase (Erase All Blocks) and verify all 1s (Read 1s All Blocks) commands. Read accesses to internal memories via the EzPort are blocked when security is enabled. The mass erase can be used to disable flash security, but all of the flash contents are lost in the process. A mass erase via the EzPort is allowed even when some memory locations are protected. When mass erase has been disabled, mass erase via the EzPort is blocked and cannot be defeated. 8.3.3 Security Interactions with Debug When flash security is active the JTAG port cannot access the memory resources of the MCU. Boundary scan chain operations work, but debugging capabilities are disabled so that the debug port cannot read flash contents. Although most debug functions are disabled, the debugger can write to the Flash Mass Erase in Progress bit in the MDM-AP Control register to trigger a mass erase (Erase All Blocks) command. A mass erase via the debugger is allowed even when some memory locations are protected. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 178 Freescale Semiconductor, Inc. Chapter 8 Security When mass erase is disabled, mass erase via the debugger is blocked. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 179 Security Interactions with other Modules KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 180 Freescale Semiconductor, Inc. Chapter 9 Debug 9.1 Introduction This device's debug is based on the ARM coresight architecture and is configured in each device to provide the maximum flexibility as allowed by the restrictions of the pinout and other available resources. Four debug interfaces are supported: * * * * IEEE 1149.1 JTAG IEEE 1149.7 JTAG (cJTAG) Serial Wire Debug (SWD) ARM Real-Time Trace Interface(1-pin asynchronous mode only) The basic Cortex-M4 debug architecture is very flexible. The following diagram shows the topology of the core debug architecture and its components. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 181 Introduction INTNMI INTISR[239:0] SLEEPING Cortex-M4 Interrupts Sleep NVIC Core Debug SLEEPDEEP Instr. Data TPIU AWIC Trace port (serial wire or multi-pin) MCM FPB DWT ITM Private Peripheral Bus (internal) ROM Table APB i/f I-code bus Bus Matrix SW/ JTAG SWJ-DP D-code bus Code bus System bus AHB-AP MDM-AP Figure 9-1. Cortex-M4 Debug Topology The following table presents a brief description of each one of the debug components. Table 9-1. Debug Components Description Module Description SWJ-DP+ cJTAG Modified Debug Port with support for SWD, JTAG, cJTAG AHB-AP AHB Master Interface from JTAG to debug module and SOC system memory maps MDM-AP Provides centralized control and status registers for an external debugger to control the device. ROM Table Identifies which debug IP is available. Core Debug Singlestep, Register Access, Run, Core Status ITM S/W Instrumentation Messaging + Simple Data Trace Messaging + Watchpoint Messaging DWT (Data and Address Watchpoints) 4 data and address watchpoints FPB (Flash Patch and Breakpoints) The FPB implements hardware breakpoints and patches code and data from code space to system space. The FPB unit contains two literal comparators for matching against literal loads from Code space, and remapping to a corresponding area in System space. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 182 Freescale Semiconductor, Inc. Chapter 9 Debug Table 9-1. Debug Components Description (continued) Module Description The FPB also contains six instruction comparators for matching against instruction fetches from Code space, and remapping to a corresponding area in System space. Alternatively, the six instruction comparators can individually configure the comparators to return a Breakpoint Instruction (BKPT) to the processor core on a match, so providing hardware breakpoint capability. TPIU (Trace Port Inteface Unit) Asynchronous Mode (1-pin) = TRACE_SWO (available on JTAG_TDO) 9.1.1 References For more information on ARM debug components, see these documents: * ARMv7-M Architecture Reference Manual * ARM Debug Interface v5.1 * ARM CoreSight Architecture Specification 9.2 The Debug Port The configuration of the cJTAG module, JTAG controller, and debug port is illustrated in the following figure: KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 183 The Debug Port IR==BYPASSor IDCODE 4'b1111 or 4'b0000 jtag_updateinstr[3:0] A TDI nTRST TCK TMS TDO TRACESWO TDO TDI TDO TDI (1'b1 = 4-pin JTAG) (1'b0 = 2-pin cJTAG) To Test Resources CJTAG TDI TDO PEN TDO TDI nSYS_TDO nSYS_TDI nTRST 1'b1 SWCLKTCK TCK JTAGC nSYS_TRST TCK TMS_OUT TMS_OUT_OE SWDITMS nSYS_TCK nSYS_TMS AHB-AP JTAGir[3:0] TMS_IN IR==BYPASSor IDCODE JTAGNSW A DAP Bus 4'b1111 or 4'b1110 MDM-AP TMS SWDO SWDOEN SWDSEL JTAGSEL SWDITMS SWCLKTCK SWD/ JTAG SELECT Figure 9-2. Modified Debug Port The debug port comes out of reset in standard JTAG mode and is switched into either cJTAG or SWD mode by the following sequences. Once the mode has been changed, unused debug pins can be reassigned to any of their alternative muxed functions. 9.2.1 JTAG-to-SWD change sequence 1. Send more than 50 TCK cycles with TMS (SWDIO) =1 2. Send the 16-bit sequence on TMS (SWDIO) = 0111_1001_1110_0111 (MSB transmitted first) 3. Send more than 50 TCK cycles with TMS (SWDIO) =1 NOTE See the ARM documentation for the CoreSight DAP Lite for restrictions. 9.2.2 JTAG-to-cJTAG change sequence 1. Reset the debug port KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 184 Freescale Semiconductor, Inc. Chapter 9 Debug 2. Set the control level to 2 via zero-bit scans 3. Execute the Store Format (STFMT) command (00011) to set the scan format register to 1149.7 scan format 9.3 Debug Port Pin Descriptions The debug port pins default after POR to their JTAG functionality with the exception of JTAG_TRST_b and can be later reassigned to their alternate functionalities. In cJTAG and SWD modes JTAG_TDI and JTAG_TRST_b can be configured to alternate GPIO functions. Table 9-2. Debug port pins Pin Name JTAG Debug Port Type cJTAG Debug Port Description Type SWD Debug Port Description Type Internal Pullup\Down Description JTAG_TMS/ SWD_DIO I/O JTAG Test Mode Selection I/O cJTAG Data I/O Serial Wire Data Pull-up JTAG_TCLK/ SWD_CLK I JTAG Test Clock I cJTAG Clock I Serial Wire Clock Pull-down JTAG_TDI I JTAG Test Data Input - JTAG_TDO/ O TRACE_SWO JTAG Test Data Output O JTAG_TRST_ I b JTAG Reset I - - Trace output over a single pin cJTAG Reset O - - Pull-up Trace output over a single pin N/C - Pull-up 9.4 System TAP connection The system JTAG controller is connected in parallel to the ARM TAP controller. The system JTAG controller IR codes overlay the ARM JTAG controller IR codes without conflict. Refer to the IR codes table for a list of the available IR codes. The output of the TAPs (TDO) are muxed based on the IR code which is selected. This design is fully JTAG compliant and appears to the JTAG chain as a single TAP. At power on reset, ARM's IDCODE (IR=4'b1110) is selected. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 185 JTAG status and control registers 9.4.1 IR Codes Table 9-3. JTAG Instructions Instruction Code[3:0] Instruction Summary IDCODE 0000 Selects device identification register for shift SAMPLE/PRELOAD 0010 Selects boundary scan register for shifting, sampling, and preloading without disturbing functional operation SAMPLE 0011 Selects boundary scan register for shifting and sampling without disturbing functional operation EXTEST 0100 Selects boundary scan register while applying preloaded values to output pins and asserting functional reset HIGHZ 1001 Selects bypass register while three-stating all output pins and asserting functional reset CLAMP 1100 Selects bypass register while applying preloaded values to output pins and asserting functional reset EZPORT 1101 Enables the EZPORT function for the SoC and asserts functional reset. ARM_IDCODE 1110 ARM JTAG-DP Instruction BYPASS 1111 Selects bypass register for data operations Factory debug reserved ARM JTAG-DP Reserved Reserved 3 0101, 0110, 0111 Intended for factory debug only 1000, 1010, 1011, 1110 These instructions will go the ARM JTAG-DP controller. Please look at ARM JTAG-DP documentation for more information on these instructions. All other opcodes Decoded to select bypass register 3. The manufacturer reserves the right to change the decoding of reserved instruction codes in the future 9.5 JTAG status and control registers Through the ARM Debug Access Port (DAP), the debugger has access to the status and control elements, implemented as registers on the DAP bus as shown in the following figure. These registers provide additional control and status for low power mode recovery and typical run-control scenarios. The status register bits also provide a means for the debugger to get updated status of the core without having to initiate a bus transaction across the crossbar switch, thus remaining less intrusive during a debug session. It is important to note that these DAP control and status registers are not memory mapped within the system memory map and are only accessible via the Debug Access Port (DAP) using JTAG, cJTAG, or SWD. The MDM-AP is accessible as Debug Access Port 1 with the available registers shown in the table below. Table 9-4. MDM-AP Register Summary Address Register Description Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 186 Freescale Semiconductor, Inc. Chapter 9 Debug Table 9-4. MDM-AP Register Summary (continued) 0x0100_0000 Status See MDM-AP Status Register 0x0100_0004 Control See MDM-AP Control Register 0x0100_00FC ID Read-only identification register that always reads as 0x001C_0000 DPACC APACC A[3:2] RnW 0x0C 0x08 Data[31:0] Debug Port Read Buffer (REBUFF) 0x04 APSEL Decode AP Select (SELECT) Debug Port ID Register (DPIDR) A[3:2] RnW Control/Status (CTRL/STAT) DP Registers 0x00 Data[31:0] SWJ-DP See the ARM Debug Interface v5p1 Supplement. Generic Debug Port (DP) Data[31:0] A[7:4] A[3:2] RnW SELECT[31:24] (APSEL) selects the AP Internal SELECT[7:4] (APBANKSEL) selects the bank Bus MDM-AP 0x01 0x3F IDR (AHB-AP) Control AHB Access Port Status 0x00 A[3:2] from the APACC selects the register within the bank AHB-AP SELECT[31:24] = 0x00 selects the AHB-AP See ARM documentation for further details AccessMDM-AP Port SELECT[31:24] = 0x01 selects the MDM-AP SELECT[7:4] = 0x0 selects the bank with Status and Ctrl A[3:2] = 2'b00 selects the Status Register A[3:2] = 2'b01 selects the Control Register Bus Matrix See Control and Status Register Descriptions SELECT[7:4] = 0xF selects the bank with IDR A[3:2] = 2'b11 selects the IDR Register (IDR register reads 0x001C_0000) Figure 9-3. MDM AP Addressing KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 187 JTAG status and control registers 9.5.1 MDM-AP Control Register Table 9-5. MDM-AP Control register assignments Bit 0 Secure1 Name Flash Mass Erase in Progress Y Description Set to cause mass erase. Cleared by hardware after mass erase operation completes. When mass erase is disabled (via MEEN settings), the erase request does not occur and the Flash Mass Erase in Progress bit continues to assert until the next system reset. 1 Debug Disable N Set to disable debug. Clear to allow debug operation. When set it overrides the C_DEBUGEN bit within the DHCSR and force disables Debug logic. 2 Debug Request N Set to force the Core to halt. If the Core is in a stop or wait mode, this bit can be used to wakeup the core and transition to a halted state. 3 System Reset Request N Set to force a system reset. The system remains held in reset until this bit is cleared. 4 Core Hold Reset N Configuration bit to control Core operation at the end of system reset sequencing. 0 Normal operation - release the Core from reset along with the rest of the system at the end of system reset sequencing. 1 Suspend operation - hold the Core in reset at the end of reset sequencing. Once the system enters this suspended state, clearing this control bit immediately releases the Core from reset and CPU operation begins. 5 VLLSx Debug Request (VLLDBGREQ) N Set to configure the system to be held in reset after the next recovery from a VLLSx mode. This bit holds the in reset when VLLSx modes are exited to allow the debugger time to re-initialize debug IP before the debug session continues. The Mode Controller captures this bit logic on entry to VLLSx modes. Upon exit from VLLSx modes, the Mode Controller will hold the in reset until VLLDBGACK is asserted. The VLLDBGREQ bit clears automatically due to the POR reset generated as part of the VLLSx recovery. 6 VLLSx Debug Acknowledge (VLLDBGACK) N Set to release a being held in reset following a VLLSx recovery This bit is used by the debugger to release the system reset when it is being held on VLLSx mode exit. The debugger re-initializes all debug IP and then assert this control bit to allow the Mode Controller to release the from reset and allow CPU operation to begin. The VLLDBGACK bit is cleared by the debugger or can be left set because it clears automatically due to the POR reset generated as part of the next VLLSx recovery. 7 LLS, VLLSx Status Acknowledge N Set this bit to acknowledge the DAP LLS and VLLS Status bits have been read. This acknowledge automatically clears the status bits. This bit is used by the debugger to clear the sticky LLS and VLLSx mode entry status bits. This bit is asserted and cleared by the debugger. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 188 Freescale Semiconductor, Inc. Chapter 9 Debug Table 9-5. MDM-AP Control register assignments (continued) Bit 8 Secure1 Name Timestamp Disable N Description Set this bit to disable the 48-bit global trace timestamp counter during debug halt mode when the core is halted. 0 The timestamp counter continues to count assuming trace is enabled. (default) 1 The timestamp counter freezes when the core has halted (debug halt mode). 9- 31 Reserved for future use N 1. Command available in secure mode 9.5.2 MDM-AP Status Register Table 9-6. MDM-AP Status register assignments Bit 0 Name Flash Mass Erase Acknowledge Description The Flash Mass Erase Acknowledge bit is cleared after any system reset. The bit is also cleared at launch of a mass erase command due to write of Flash Mass Erase in Progress bit in MDM AP Control Register. The Flash Mass Erase Acknowledge is set after Flash control logic has started the mass erase operation. When mass erase is disabled (via MEEN settings), an erase request due to seting of Flash Mass Erase in Progress bit is not acknowledged. 1 Flash Ready Indicate Flash has been initialized and debugger can be configured even if system is continuing to be held in reset via the debugger. 2 System Security Indicates the security state. When secure, the debugger does not have access to the system bus or any memory mapped peripherals. This bit indicates when the part is locked and no system bus access is possible. 3 System Reset Indicates the system reset state. 0 System is in reset 1 System is not in reset 4 Reserved 5 Mass Erase Enable Indicates if the MCU can be mass erased or not 0 Mass erase is disabled 1 Mass erase is enabled 6 Backdoor Access Key Enable Indicates if the MCU has the backdoor access key enabled. 0 Disabled 1 Enabled 7 LP Enabled Decode of LPLLSM control bits to indicate that VLPS, LLS, or VLLSx are the selected power mode the next time the ARM Core enters Deep Sleep. 0 Low Power Stop Mode is not enabled 1 Low Power Stop Mode is enabled Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 189 Debug Resets Table 9-6. MDM-AP Status register assignments (continued) Bit Name Description Usage intended for debug operation in which Run to VLPS is attempted. Per debug definition, the system actually enters the Stop state. A debugger should interpret deep sleep indication (with SLEEPDEEP and SLEEPING asserted), in conjuntion with this bit asserted as the debuggerVLPS status indication. 8 Very Low Power Mode Indicates current power mode is VLPx. This bit is not `sticky' and should always represent whether VLPx is enabled or not. This bit is used to throttle JTAG TCK frequency up/down. 9 LLS Mode Exit This bit indicates an exit from LLS mode has occurred. The debugger will lose communication while the system is in LLS (including access to this register). Once communication is reestablished, this bit indicates that the system had been in LLS. Since the debug modules held their state during LLS, they do not need to be reconfigured. This bit is set during the LLS recovery sequence. The LLS Mode Exit bit is held until the debugger has had a chance to recognize that LLS was exited and is cleared by a write of 1 to the LLS, VLLSx Status Acknowledge bit in MDM AP Control register. 10 VLLSx Modes Exit This bit indicates an exit from VLLSx mode has occurred. The debugger will lose communication while the system is in VLLSx (including access to this register). Once communication is reestablished, this bit indicates that the system had been in VLLSx. Since the debug modules lose their state during VLLSx modes, they need to be reconfigured. This bit is set during the VLLSx recovery sequence. The VLLSx Mode Exit bit is held until the debugger has had a chance to recognize that a VLLS mode was exited and is cleared by a write of 1 to the LLS, VLLSx Status Acknowledge bit in MDM AP Control register. 11 - 15 Reserved for future use Always read 0. 16 Core Halted Indicates the Core has entered debug halt mode 17 Core SLEEPDEEP Indicates the Core has entered a low power mode 18 Core SLEEPING SLEEPING==1 and SLEEPDEEP==0 indicates wait or VLPW mode. SLEEPING==1 and SLEEPDEEP==1 indicates stop or VLPS mode. 19 - 31 Reserved for future use Always read 0. 9.6 Debug Resets The debug system receives the following sources of reset: * JTAG_TRST_b from an external signal. This signal is optional and may not be available in all packages. * Debug reset (CDBGRSTREQ bit within the SWJ-DP CTRL/STAT register) in the TCLK domain that allows the debugger to reset the debug logic. * TRST asserted via the cJTAG escape command. * System POR reset KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 190 Freescale Semiconductor, Inc. Chapter 9 Debug Conversely the debug system is capable of generating system reset using the following mechanism: * A system reset in the DAP control register which allows the debugger to hold the system in reset. * SYSRESETREQ bit in the NVIC application interrupt and reset control register * A system reset in the DAP control register which allows the debugger to hold the Core in reset. 9.7 AHB-AP AHB-AP provides the debugger access to all memory and registers in the system, including processor registers through the NVIC. System access is independent of the processor status. AHB-AP does not do back-to-back transactions on the bus, so all transactions are non-sequential. AHB-AP can perform unaligned and bit-band transactions. AHB-AP transactions bypass the FPB, so the FPB cannot remap AHB-AP transactions. SWJ/SW-DP-initiated transaction aborts drive an AHB-AP-supported sideband signal called HABORT. This signal is driven into the Bus Matrix, which resets the Bus Matrix state, so that AHB-AP can access the Private Peripheral Bus for last ditch debugging such as read/stop/reset the core. AHB-AP transactions are little endian. For a short period at the start of a system reset event the system security status is being determined and debugger access to all AHB-AP transactions is blocked. The MDM-AP Status register is accessible and can be monitored to determine when this initial period is completed. After this initial period, if system reset is held via assertion of the RESET pin, the debugger has access via the bus matrix to the private peripheral bus to configure the debug IP even while system reset is asserted. While in system reset, access to other memory and register resources, accessed over the Crossbar Switch, is blocked. 9.8 ITM The ITM is an application-driven trace source that supports printf style debugging to trace Operating System (OS) and application events, and emits diagnostic system information. The ITM emits trace information as packets. There are four sources that can generate packets. If multiple sources generate packets at the same time, the ITM arbitrates the order in which packets are output. The four sources in decreasing order of priority are: 1. Software trace -- Software can write directly to ITM stimulus registers. This emits packets. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 191 Core Trace Connectivity 2. Hardware trace -- The DWT generates these packets, and the ITM emits them. 3. Time stamping -- Timestamps are emitted relative to packets. The ITM contains a 21-bit counter to generate the timestamp. The Cortex-M4 clock or the bitclock rate of the Serial Wire Viewer (SWV) output clocks the counter. 4. Global system timestamping. Timestamps can optionally be generated using a system-wide 48-bit count value. 9.9 Core Trace Connectivity The ITM can route its data to the TPIU. (See the MCM (Miscellaneous Control Module) for controlling the routing to the TPIU.) This configuration enables the use of trace with low cost tools while maintaining the compatibility with trace probes. 9.10 TPIU The TPIU acts as a bridge between the on-chip trace data from the Instrumentation Trace Macrocell (ITM) to a data stream, encapsulating IDs where required, that is then captured by a Trace Port Analyzer (TPA). The TPIU is specially designed for low-cost debug. 9.11 DWT The DWT is a unit that performs the following debug functionality: * It contains four comparators that you can configure as a hardware watchpoint, a PC sampler event trigger, or a data address sampler event trigger. The first comparator, DWT_COMP0, can also compare against the clock cycle counter, CYCCNT. The second comparator, DWT_COMP1, can also be used as a data comparator. * The DWT contains counters for: * Clock cycles (CYCCNT) * Folded instructions * Load store unit (LSU) operations * Sleep cycles * CPI (all instruction cycles except for the first cycle) * Interrupt overhead KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 192 Freescale Semiconductor, Inc. Chapter 9 Debug NOTE An event is emitted each time a counter overflows. * The DWT can be configured to emit PC samples at defined intervals, and to emit interrupt event information. 9.12 Debug in Low Power Modes In low power modes in which the debug modules are kept static or powered off, the debugger cannot gather any debug data for the duration of the low power mode. In the case that the debugger is held static, the debug port returns to full functionality as soon as the low power mode exits and the system returns to a state with active debug. In the case that the debugger logic is powered off, the debugger is reset on recovery and must be reconfigured once the low power mode is exited. Power mode entry logic monitors Debug Power Up and System Power Up signals from the debug port as indications that a debugger is active. These signals can be changed in RUN, VLPR, WAIT and VLPW. If the debug signal is active and the system attempts to enter stop or VLPS, FCLK continues to run to support core register access. In these modes in which FCLK is left active the debug modules have access to core registers but not to system memory resources accessed via the crossbar. With debug enabled, transitions from Run directly to VLPS are not allowed and result in the system entering Stop mode instead. Status bits within the MDM-AP Status register can be evaluated to determine this pseudo-VLPS state. Note with the debug enabled, transitions from Run--> VLPR --> VLPS are still possible but also result in the system entering Stop mode instead. In VLLS mode all debug modules are powered off and reset at wakeup. In LLS mode, the debug modules retain their state but no debug activity is possible. NOTE When using cJTAG and entering LLS mode, the cJTAG controller must be reset on exit from LLS mode. Going into a VLLSx mode causes all the debug controls and settings to be reset. To give time to the debugger to sync up with the HW, the MDM-AP Control register can be configured hold the system in reset on recovery so that the debugger can regain control and reconfigure debug logic prior to the system exiting reset and resuming operation. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 193 Debug & Security 9.12.1 Debug Module State in Low Power Modes The following table shows the state of the debug modules in low power modes. These terms are used: * FF = Full functionality. In VLPR and VLPW the system frequency is limited, but if a module does not have a limitation in its functionality, it is still listed as FF. * static = Module register states and associated memories are retained. * OFF = Modules are powered off; module is in reset state upon wakeup. Table 9-7. Debug Module State in Low Power Modes Module STOP VLPR VLPW VLPS LLS VLLSx Debug Port FF FF FF OFF static OFF AHB-AP FF FF FF OFF static OFF ITM FF FF FF OFF static OFF TPIU FF FF FF OFF static OFF DWT FF FF FF OFF static OFF 9.13 Debug & Security When security is enabled (FSEC[SEC] != 10), the debug port capabilities are limited in order to prevent exploitation of secure data. In the secure state the debugger still has access to the MDM-AP Status Register and can determine the current security state of the device. In the case of a secure device, the debugger also has the capability of performing a mass erase operation via writes to the MDM-AP Control Register if mass erase is enabled. In the case of a secure device that has mass erase disabled (FSEC[MEEN] = 10), attempts to mass erase via the debug interface are blocked. When mass erase is disabled (FSEC[MEEN]= 10), the debugger does not have the capability of performing a mass erase operation via writes to MDM-AP Control Register KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 194 Freescale Semiconductor, Inc. Chapter 10 Signal Multiplexing and Signal Descriptions 10.1 Introduction To optimize functionality in small packages, pins have several functions available via signal multiplexing. This chapter illustrates which of this device's signals are multiplexed on which external pin. The Port Control block controls which signal is present on the external pin. Reference that chapter to find which register controls the operation of a specific pin. 10.2 Signal Multiplexing Integration This section summarizes how the module is integrated into the device. For a comprehensive description of the module itself, see the module's dedicated chapter. Peripheral bridge 0 Register access Module External Pins Transfers Signal Multiplexing/ Port Control Module Transfers Module Figure 10-1. Signal multiplexing integration Table 10-1. Reference links to related information Topic Related module Reference Full description Port control Port control System memory map System memory map Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 195 Signal Multiplexing Integration Table 10-1. Reference links to related information (continued) Topic Related module Reference Clocking Clock Distribution Register access Peripheral bus controller Peripheral bridge 10.2.1 Port control and interrupt module features * 32-pin ports NOTE Not all pins are available on the device. See the following section for details. * Each 32-pin port is assigned one interrupt. Table 10-2. Ports summary Feature Port A Port B Port C Port D Port E Yes Yes Yes Yes Pull select at reset PTA1/PTA2/PTA3/ Pull down PTA4/PTA5=Pull up, Others=Pull down Pull down Pull down Pull down Pull enable control Yes Yes Yes Yes Disabled Disabled Disabled Yes Yes Yes Yes Disabled Disabled Disabled Disabled Pull select control Yes Yes Pull enable at reset PTA0/PTA1/PTA2/ Disabled PTA3/ PTA4=Enabled; Others=Disabled Slew rate enable control Yes Slew rate enable at Disabled reset Passive filter enable control PTA4=Yes; Others=No No No No No Passive filter enable at reset Disabled Disabled Disabled Disabled Disabled Open drain enable Yes control Yes Yes Yes Yes Open drain enable Disabled at reset Disabled Disabled Disabled Disabled Drive strength enable control No PTB0/PTB1 only PTC3/PTC4 only PTD4/PTD5/PTD6/ No PTD7 only Drive strength enable at reset Disabled Disabled Disabled Disabled Disabled Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 196 Freescale Semiconductor, Inc. Chapter 10 Signal Multiplexing and Signal Descriptions Table 10-2. Ports summary (continued) Feature Port A Port B Port C Port D Port E Pin mux control Yes Yes Yes Yes Yes Pin mux at reset PTA0/PTA1/PTA2/ ALT0 PTA3/PTA4=ALT7; Others=ALT0 ALT0 ALT0 ALT0 Yes Yes Yes Yes Yes Interrupt and DMA Yes request Yes Yes Yes Yes No No Yes No Lock bit Digital glitch filter No 10.2.2 Clock gating The clock to the port control module can be gated on and off using the SCGC5[PORTx] bits in the SIM module. These bits are cleared after any reset, which disables the clock to the corresponding module to conserve power. Prior to initializing the corresponding module, set SCGC5[PORTx] in the SIM module to enable the clock. Before turning off the clock, make sure to disable the module. For more details, refer to the clock distribution chapter. 10.2.3 Signal multiplexing constraints 1. A given peripheral function must be assigned to a maximum of one package pin. Do not program the same function to more than one pin. 2. To ensure the best signal timing for a given peripheral's interface, choose the pins in closest proximity to each other. 10.3 Pinout 10.3.1 KV31F Signal Multiplexing and Pin Assignments The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 197 Pinout 100 64 LQFP LQFP Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 1 1 PTE0/ CLKOUT32K ADC1_SE4a ADC1_SE4a PTE0/ CLKOUT32K SPI1_PCS1 UART1_TX I2C1_SDA 2 2 PTE1/ LLWU_P0 ADC1_SE5a ADC1_SE5a PTE1/ LLWU_P0 SPI1_SOUT UART1_RX I2C1_SCL 3 -- PTE2/ LLWU_P1 ADC1_SE6a ADC1_SE6a PTE2/ LLWU_P1 SPI1_SCK UART1_ CTS_b 4 -- PTE3 ADC1_SE7a ADC1_SE7a PTE3 SPI1_SIN UART1_ RTS_b 5 -- PTE4/ LLWU_P2 DISABLED PTE4/ LLWU_P2 SPI1_PCS0 LPUART0_ TX 6 -- PTE5 DISABLED PTE5 SPI1_PCS2 LPUART0_ RX FTM3_CH0 7 -- PTE6 DISABLED PTE6 SPI1_PCS3 LPUART0_ CTS_b FTM3_CH1 8 3 VDD VDD VDD 9 4 VSS VSS VSS 10 5 PTE16 ADC0_SE4a ADC0_SE4a PTE16 SPI0_PCS0 UART2_TX FTM_CLKIN0 FTM0_FLT3 11 6 PTE17 ADC0_SE5a ADC0_SE5a PTE17 SPI0_SCK UART2_RX FTM_CLKIN1 LPTMR0_ ALT3 12 7 PTE18 ADC0_SE6a ADC0_SE6a PTE18 SPI0_SOUT UART2_ CTS_b I2C0_SDA 13 8 PTE19 ADC0_SE7a ADC0_SE7a PTE19 SPI0_SIN UART2_ RTS_b I2C0_SCL 14 -- ADC0_DP1 ADC0_DP1 ADC0_DP1 15 -- ADC0_DM1 ADC0_DM1 ADC0_DM1 16 -- ADC1_DP1/ ADC0_DP2 ADC1_DP1/ ADC0_DP2 ADC1_DP1/ ADC0_DP2 17 -- ADC1_DM1/ ADC0_DM2 ADC1_DM1/ ADC0_DM2 ADC1_DM1/ ADC0_DM2 18 9 ADC0_DP0/ ADC1_DP3 ADC0_DP0/ ADC1_DP3 ADC0_DP0/ ADC1_DP3 19 10 ADC0_DM0/ ADC1_DM3 ADC0_DM0/ ADC1_DM3 ADC0_DM0/ ADC1_DM3 20 11 ADC1_DP0/ ADC0_DP3 ADC1_DP0/ ADC0_DP3 ADC1_DP0/ ADC0_DP3 21 12 ADC1_DM0/ ADC0_DM3 ADC1_DM0/ ADC0_DM3 ADC1_DM0/ ADC0_DM3 22 13 VDDA VDDA VDDA 23 14 VREFH VREFH VREFH 24 15 VREFL VREFL VREFL 25 16 VSSA VSSA VSSA 26 17 VREF_OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_SE18 VREF_OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_SE18 VREF_OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_SE18 ALT7 EzPort SPI1_SIN SPI1_SOUT KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 198 Freescale Semiconductor, Inc. Chapter 10 Signal Multiplexing and Signal Descriptions 100 64 LQFP LQFP Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort 27 18 DAC0_OUT/ CMP1_IN3/ ADC0_SE23 DAC0_OUT/ CMP1_IN3/ ADC0_SE23 DAC0_OUT/ CMP1_IN3/ ADC0_SE23 28 19 DAC1_OUT/ CMP0_IN4/ ADC1_SE23 DAC1_OUT/ CMP0_IN4/ ADC1_SE23 DAC1_OUT/ CMP0_IN4/ ADC1_SE23 29 -- VSS VSS VSS 30 -- VDD VDD VDD 31 20 PTE24 ADC0_SE17 ADC0_SE17 PTE24 FTM0_CH0 I2C0_SCL EWM_OUT_b 32 21 PTE25 ADC0_SE18 ADC0_SE18 PTE25 FTM0_CH1 I2C0_SDA EWM_IN 33 -- PTE26/ CLKOUT32K DISABLED PTE26/ CLKOUT32K 34 22 PTA0 JTAG_TCLK/ SWD_CLK/ EZP_CLK PTA0 UART0_ CTS_b FTM0_CH5 EWM_IN 35 23 PTA1 JTAG_TDI/ EZP_DI PTA1 UART0_RX FTM0_CH6 CMP0_OUT FTM2_QD_ PHA FTM1_CH1 JTAG_TDI EZP_DI 36 24 PTA2 JTAG_TDO/ TRACE_ SWO/ EZP_DO PTA2 UART0_TX FTM0_CH7 CMP1_OUT FTM2_QD_ PHB FTM1_CH0 JTAG_TDO/ TRACE_ SWO EZP_DO 37 25 PTA3 JTAG_TMS/ SWD_DIO PTA3 UART0_ RTS_b FTM0_CH0 FTM2_FLT0 EWM_OUT_b JTAG_TMS/ SWD_DIO 38 26 PTA4/ LLWU_P3 NMI_b/ EZP_CS_b PTA4/ LLWU_P3 FTM0_CH1 FTM0_FLT3 NMI_b 39 27 PTA5 DISABLED PTA5 FTM0_CH2 JTAG_TRST_ b 40 -- VDD VDD VDD 41 -- VSS VSS VSS 42 28 PTA12 DISABLED PTA12 FTM1_CH0 FTM1_QD_ PHA 43 29 PTA13/ LLWU_P4 DISABLED PTA13/ LLWU_P4 FTM1_CH1 FTM1_QD_ PHB 44 -- PTA14 DISABLED PTA14 SPI0_PCS0 UART0_TX 45 -- PTA15 DISABLED PTA15 SPI0_SCK UART0_RX 46 -- PTA16 DISABLED PTA16 SPI0_SOUT UART0_ CTS_b 47 -- PTA17 ADC1_SE17 ADC1_SE17 PTA17 SPI0_SIN UART0_ RTS_b 48 30 VDD VDD VDD 49 31 VSS VSS VSS 50 32 PTA18 EXTAL0 EXTAL0 PTA18 51 33 PTA19 XTAL0 XTAL0 PTA19 52 34 RESET_b RESET_b RESET_b 53 35 PTB0/ LLWU_P5 ADC0_SE8/ ADC1_SE8 ADC0_SE8/ ADC1_SE8 PTB0/ LLWU_P5 FTM0_FLT2 FTM_CLKIN0 FTM0_FLT0 FTM1_FLT0 FTM_CLKIN1 I2C0_SCL FTM1_CH0 JTAG_TCLK/ EZP_CLK SWD_CLK EZP_CS_b LPTMR0_ ALT1 FTM1_QD_ PHA UART0_RX KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 199 Pinout 100 64 LQFP LQFP Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 EWM_IN ALT6 54 36 PTB1 ADC0_SE9/ ADC1_SE9 ADC0_SE9/ ADC1_SE9 PTB1 I2C0_SDA FTM1_CH1 FTM0_FLT2 FTM1_QD_ PHB 55 37 PTB2 ADC0_SE12 ADC0_SE12 PTB2 I2C0_SCL UART0_ RTS_b FTM0_FLT1 56 38 PTB3 ADC0_SE13 ADC0_SE13 PTB3 I2C0_SDA UART0_ CTS_b 57 -- PTB9 DISABLED PTB9 SPI1_PCS1 LPUART0_ CTS_b FB_AD20 58 -- PTB10 ADC1_SE14 ADC1_SE14 PTB10 SPI1_PCS0 LPUART0_ RX FB_AD19 FTM0_FLT1 59 -- PTB11 ADC1_SE15 ADC1_SE15 PTB11 SPI1_SCK LPUART0_ TX FB_AD18 FTM0_FLT2 60 -- VSS VSS VSS 61 -- VDD VDD VDD 62 39 PTB16 DISABLED PTB16 SPI1_SOUT UART0_RX FTM_CLKIN0 FB_AD17 EWM_IN 63 40 PTB17 DISABLED PTB17 SPI1_SIN UART0_TX FTM_CLKIN1 FB_AD16 EWM_OUT_b 64 41 PTB18 DISABLED PTB18 FTM2_CH0 FB_AD15 FTM2_QD_ PHA 65 42 PTB19 DISABLED PTB19 FTM2_CH1 FB_OE_b FTM2_QD_ PHB 66 -- PTB20 DISABLED PTB20 FB_AD31 CMP0_OUT 67 -- PTB21 DISABLED PTB21 FB_AD30 CMP1_OUT 68 -- PTB22 DISABLED PTB22 FB_AD29 69 -- PTB23 DISABLED PTB23 70 43 PTC0 ADC0_SE14 ADC0_SE14 PTC0 71 44 PTC1/ LLWU_P6 ADC0_SE15 ADC0_SE15 PTC1/ LLWU_P6 72 45 PTC2 73 46 74 ALT7 UART0_TX FTM0_FLT3 FTM0_FLT0 SPI0_PCS5 FB_AD28 SPI0_PCS4 PDB0_ EXTRG FB_AD14 SPI0_PCS3 UART1_ RTS_b FTM0_CH0 FB_AD13 LPUART0_ RTS_b ADC0_SE4b/ ADC0_SE4b/ PTC2 CMP1_IN0 CMP1_IN0 SPI0_PCS2 UART1_ CTS_b FTM0_CH1 FB_AD12 LPUART0_ CTS_b PTC3/ LLWU_P7 CMP1_IN1 CMP1_IN1 PTC3/ LLWU_P7 SPI0_PCS1 UART1_RX FTM0_CH2 CLKOUT LPUART0_ RX 47 VSS VSS VSS 75 48 VDD VDD VDD 76 49 PTC4/ LLWU_P8 DISABLED PTC4/ LLWU_P8 SPI0_PCS0 UART1_TX FTM0_CH3 FB_AD11 CMP1_OUT LPUART0_ TX 77 50 PTC5/ LLWU_P9 DISABLED PTC5/ LLWU_P9 SPI0_SCK LPTMR0_ ALT2 FB_AD10 CMP0_OUT FTM0_CH2 78 51 PTC6/ LLWU_P10 CMP0_IN0 CMP0_IN0 PTC6/ LLWU_P10 SPI0_SOUT PDB0_ EXTRG FB_AD9 I2C0_SCL 79 52 PTC7 CMP0_IN1 CMP0_IN1 PTC7 SPI0_SIN FB_AD8 I2C0_SDA 80 53 PTC8 ADC1_SE4b/ ADC1_SE4b/ PTC8 CMP0_IN2 CMP0_IN2 FTM3_CH4 FB_AD7 81 54 PTC9 ADC1_SE5b/ ADC1_SE5b/ PTC9 CMP0_IN3 CMP0_IN3 FTM3_CH5 FB_AD6 82 55 PTC10 ADC1_SE6b FTM3_CH6 FB_AD5 ADC1_SE6b PTC10 I2C1_SCL EzPort FTM0_FLT1 SPI0_PCS0 FTM2_FLT0 KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 200 Freescale Semiconductor, Inc. Chapter 10 Signal Multiplexing and Signal Descriptions 100 64 LQFP LQFP Pin Name Default ALT0 ADC1_SE7b ALT1 ALT4 FTM3_CH7 ALT5 ALT6 ALT7 56 PTC11/ LLWU_P11 ADC1_SE7b 84 -- PTC12 DISABLED PTC12 FB_AD27 85 -- PTC13 DISABLED PTC13 FB_AD26 86 -- PTC14 DISABLED PTC14 FB_AD25 87 -- PTC15 DISABLED PTC15 FB_AD24 88 -- VSS VSS VSS 89 -- VDD VDD VDD 90 -- PTC16 DISABLED PTC16 LPUART0_ RX FB_CS5_b/ FB_TSIZ1/ FB_BE23_ 16_BLS15_ 8_b 91 -- PTC17 DISABLED PTC17 LPUART0_ TX FB_CS4_b/ FB_TSIZ0/ FB_BE31_ 24_BLS7_0_ b 92 -- PTC18 DISABLED PTC18 LPUART0_ RTS_b FB_TBST_b/ FB_CS2_b/ FB_BE15_8_ BLS23_16_b 93 57 PTD0/ LLWU_P12 DISABLED PTD0/ LLWU_P12 SPI0_PCS0 UART2_ RTS_b FTM3_CH0 FB_ALE/ FB_CS1_b/ FB_TS_b LPUART0_ RTS_b 94 58 PTD1 ADC0_SE5b PTD1 SPI0_SCK UART2_ CTS_b FTM3_CH1 FB_CS0_b LPUART0_ CTS_b 95 59 PTD2/ LLWU_P13 DISABLED PTD2/ LLWU_P13 SPI0_SOUT UART2_RX FTM3_CH2 FB_AD4 LPUART0_ RX I2C0_SCL 96 60 PTD3 DISABLED PTD3 SPI0_SIN UART2_TX FTM3_CH3 FB_AD3 LPUART0_ TX I2C0_SDA 97 61 PTD4/ LLWU_P14 DISABLED PTD4/ LLWU_P14 SPI0_PCS1 UART0_ RTS_b FTM0_CH4 FB_AD2 EWM_IN SPI1_PCS0 98 62 PTD5 ADC0_SE6b ADC0_SE6b PTD5 SPI0_PCS2 UART0_ CTS_b FTM0_CH5 FB_AD1 EWM_OUT_b SPI1_SCK 99 63 PTD6/ LLWU_P15 ADC0_SE7b ADC0_SE7b PTD6/ LLWU_P15 SPI0_PCS3 UART0_RX FTM0_CH6 FB_AD0 FTM0_FLT0 SPI1_SOUT 100 64 PTD7 DISABLED UART0_TX FTM0_CH7 FTM0_FLT1 SPI1_SIN PTD7 I2C1_SDA ALT3 83 ADC0_SE5b PTC11/ LLWU_P11 ALT2 EzPort FB_RW_b FTM3_FLT0 10.3.2 KV31F Pinouts The following figure shows the pinout diagram for the devices supported by this document. Many signals may be multiplexed onto a single pin. To determine what signals can be used on which pin, see the previous section. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 201 PTD7 PTD6/LLWU_P15 PTD5 PTD4/LLWU_P14 PTD3 PTD2/LLWU_P13 PTD1 PTD0/LLWU_P12 PTC11/LLWU_P11 PTC10 PTC9 PTC8 PTC7 PTC6/LLWU_P10 PTC5/LLWU_P9 PTC4/LLWU_P8 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 Pinout ADC0_DP0/ADC1_DP3 9 40 PTB17 ADC0_DM0/ADC1_DM3 10 39 PTB16 ADC1_DP0/ADC0_DP3 11 38 PTB3 ADC1_DM0/ADC0_DM3 12 37 PTB2 VDDA 13 36 PTB1 VREFH 14 35 PTB0/LLWU_P5 VREFL 15 34 RESET_b VSSA 16 33 PTA19 32 PTB18 PTA18 41 31 8 VSS PTE19 30 PTB19 VDD 42 29 7 PTA13/LLWU_P4 PTE18 28 PTC0 PTA12 43 27 6 PTA5 PTE17 26 PTC1/LLWU_P6 PTA4/LLWU_P3 44 25 5 PTA3 PTE16 24 PTC2 PTA2 45 23 4 PTA1 VSS 22 PTC3/LLWU_P7 PTA0 46 21 3 PTE25 VDD 20 VSS PTE24 47 19 2 DAC1_OUT/CMP0_IN4/ADC1_SE23 PTE1/LLWU_P0 18 VDD DAC0_OUT/CMP1_IN3/ADC0_SE23 48 17 1 VREF_OUT/CMP1_IN5/CMP0_IN5/ADC1_SE18 PTE0/CLKOUT32K Figure 10-2. KV31F 64 LQFP Pinout Diagram (top view) KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 202 Freescale Semiconductor, Inc. PTC17 PTC16 VDD VSS PTC15 PTC14 PTC13 PTC12 PTC11/LLWU_P11 PTC10 PTC9 PTC8 90 89 88 87 86 85 84 83 82 81 80 PTC4/LLWU_P8 PTC18 92 91 76 PTD0/LLWU_P12 93 PTC5/LLWU_P9 PTD1 94 77 PTD2/LLWU_P13 95 PTC7 PTD3 96 PTC6/LLWU_P10 PTD4/LLWU_P14 97 78 PTD5 98 79 PTD6/LLWU_P15 99 100 PTD7 Chapter 10 Signal Multiplexing and Signal Descriptions PTE0/CLKOUT32K 1 75 VDD PTE1/LLWU_P0 2 74 VSS PTE2/LLWU_P1 3 73 PTC3/LLWU_P7 PTE3 4 72 PTC2 PTE4/LLWU_P2 5 71 PTC1/LLWU_P6 PTE5 6 70 PTC0 PTE6 7 69 PTB23 VDD 8 68 PTB22 9 67 PTB21 PTE16 10 66 PTB20 PTE17 11 65 PTB19 VSS PTE18 12 64 PTB18 PTE19 13 63 PTB17 ADC0_DP1 14 62 PTB16 ADC0_DM1 15 61 VDD ADC1_DP1/ADC0_DP2 16 60 VSS ADC1_DM1/ADC0_DM2 17 59 PTB11 ADC0_DP0/ADC1_DP3 18 58 PTB10 ADC0_DM0/ADC1_DM3 19 57 PTB9 ADC1_DP0/ADC0_DP3 20 56 PTB3 39 40 41 42 43 44 45 46 47 48 49 50 VDD VSS PTA12 PTA13/LLWU_P4 PTA14 PTA15 PTA16 PTA17 VDD VSS PTA18 PTA2 PTA5 36 PTA1 38 35 PTA0 37 34 PTE26/CLKOUT32K PTA3 33 PTA4/LLWU_P3 32 PTA19 31 RESET_b 51 PTE25 52 25 PTE24 24 VSSA VDD VREFL 30 PTB0/LLWU_P5 29 53 VSS 23 28 VREFH 27 PTB1 DAC1_OUT/CMP0_IN4/ADC1_SE23 PTB2 54 DAC0_OUT/CMP1_IN3/ADC0_SE23 55 22 26 21 VDDA VREF_OUT/CMP1_IN5/CMP0_IN5/ADC1_SE18 ADC1_DM0/ADC0_DM3 Figure 10-3. KV31F 100 LQFP Pinout Diagram (top view) KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 203 Module Signal Description Tables 10.4 Module Signal Description Tables The following sections correlate the chip-level signal name with the signal name used in the module's chapter. They also briefly describe the signal function and direction. 10.4.1 Core Modules Table 10-3. JTAG Signal Descriptions Chip signal name Module signal name Description I/O JTAG_TMS JTAG_TMS/ SWD_DIO JTAG Test Mode Selection I/O JTAG_TCLK JTAG_TCLK/ SWD_CLK JTAG Test Clock I JTAG_TDI JTAG_TDI JTAG Test Data Input I JTAG_TDO JTAG_TDO/ TRACE_SWO JTAG Test Data Output O JTAG_TRST JTAG_TRST_b JTAG Reset I Table 10-4. SWD Signal Descriptions Chip signal name Module signal name Description I/O SWD_DIO JTAG_TMS/ SWD_DIO Serial Wire Data I/O SWD_CLK JTAG_TCLK/ SWD_CLK Serial Wire Clock I Table 10-5. TPIU Signal Descriptions Chip signal name Module signal name Description I/O TRACE_SWO JTAG_TDO/ TRACE_SWO Trace output data from the ARM CoreSight debug block over a single pin O KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 204 Freescale Semiconductor, Inc. Chapter 10 Signal Multiplexing and Signal Descriptions 10.4.2 System Modules Table 10-6. EWM Signal Descriptions Chip signal name Module signal name EWM_IN EWM_in EWM_OUT EWM_out Description I/O EWM input for safety status of external safety circuits. The polarity of EWM_in is programmable using the EWM_CTRL[ASSIN] bit. The default polarity is active-low. I EWM reset out signal O 10.4.3 Clock Modules Table 10-7. OSC Signal Descriptions Chip signal name Module signal name EXTAL0 EXTAL XTAL0 XTAL Description I/O External clock/Oscillator input I Oscillator output O 10.4.4 Memories and Memory Interfaces Table 10-8. EzPort Signal Descriptions Chip signal name Module signal name Description I/O EZP_CLK EZP_CK EzPort Clock Input EZP_CS EZP_CS EzPort Chip Select Input EZP_DI EZP_D EzPort Serial Data In Input EZP_DO EZP_Q EzPort Serial Data Out Output Table 10-9. FlexBus Signal Descriptions Chip signal name Module signal name CLKOUT FB_CLK FB_AD[31:0] 1 Description I/O FlexBus Clock Output O FB_AD31 - FB_AD0 This is the address and data bus, FB_AD. I/O The number of byte lanes carrying the data is determined by the port size associated with the matching chip-select. The full 32-bit address is driven on the first clock of a bus cycle (address phase). After the first clock, the data is driven on the bus (data phase). During the data phase, the address is driven on the Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 205 Module Signal Description Tables Table 10-9. FlexBus Signal Descriptions (continued) Chip signal name Module signal name Description I/O pins not used for data. For example, in 16-bit mode, the lower address is driven on FB_AD15-FB_AD0, and in 8-bit mode, the lower address is driven on FB_AD23-FB_AD0. FB_CS[5:0] 2 FB_CS5-FB_CS0 General Purpose Chip-Selects--Indicate which external memory or peripheral is selected. A particular chip-select is asserted when the transfer address is within the external memory's or peripheral's address space, as defined in CSAR[BA] and CSMR[BAM]. O FB_BE31_24_BLS7_ 0, FB_BE23_16_BLS15 _8, FB_BE15_8_BLS23_ 16, FB_BE7_0_BLS31_2 43 FB_BE_31_24 Byte Enables--Indicate that data is to be latched or driven onto a specific byte lane of the data bus. CSCR[BEM] determines if these signals are asserted on reads and writes or on writes only. O FB_OE FB_OE Output Enable--Sent to the external memory or peripheral to enable a read transfer. This signal is asserted during read accesses only when a chip-select matches the current address decode. O FB_R W FB_R/W Read/Write--Indicates whether the current bus operation is a read operation (FB_R/W high) or a write operation (FB_R/W low). O FB_TS/ FB_ALE FB_TS Transfer Start--Indicates that the chip has begun a bus transaction and that the address and attributes are valid. O FB_BE_23_16 FB_BE_15_8 FB_BE_7_0 For external SRAM or flash devices, the FB_BE outputs should be connected to individual byte strobe signals. An inverted FB_TS is available as an address latch enable (FB_ALE), which indicates when the address is being driven on the FB_AD bus. FB_TS/FB_ALE is asserted for one bus clock cycle. The chip can extend this signal until the first positive clock edge after FB_CS asserts. See CSCR[EXTS] and Extended Transfer Start/Address Latch Enable. FB_TSIZ[1:0] FB_TSIZ1-FB_TSIZ0 Transfer Size--Indicates (along with FB_TBST) the data transfer size of the current bus operation. The interface supports 8-, 16-, and 32-bit operand transfers and allows accesses to 8-, 16-, and 32-bit data ports. O * 00b = 4 bytes * 01b = 1 byte * 10b = 2 bytes * 11b = 16 bytes (line) For misaligned transfers, FB_TSIZ1-FB_TSIZ0 indicate the size of each transfer. For example, if a 32-bit access through a 32-bit port device occurs at a misaligned offset of 1h, 8 bits are transferred first (FB_TSIZ1-FB_TSIZ0 = 01b), 16 bits are transferred next at offset 2h (FB_TSIZ1-FB_TSIZ0 = 10b), and the final 8 bits are transferred at offset 4h (FB_TSIZ1-FB_TSIZ0 = 01b). For aligned transfers larger than the port size, FB_TSIZ1- FB_TSIZ0 behave as follows: Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 206 Freescale Semiconductor, Inc. Chapter 10 Signal Multiplexing and Signal Descriptions Table 10-9. FlexBus Signal Descriptions (continued) Chip signal name Module signal name Description I/O * If bursting is used, FB_TSIZ1-FB_TSIZ0 are driven to the transfer size. * If bursting is inhibited, FB_TSIZ1-FB_TSIZ0 first show the entire transfer size and then show the port size. For burst-inhibited transfers, FB_TSIZ1-FB_TSIZ0 change with each FB_TS assertion to reflect the next transfer size. For transfers to port sizes smaller than the transfer size, FB_TSIZ1-FB_TSIZ0 indicate the size of the entire transfer on the first access and the size of the current port transfer on subsequent transfers. For example, for a 32-bit write to an 8-bit port, FB_TSIZ1-FB_TSIZ0 are 00b for the first transaction and 01b for the next three transactions. If bursting is used for a 32-bit write to an 8-bit port, FB_TSIZ1-FB_TSIZ0 are driven to 00b for the entire transfer. FB_TA4 FB_TA Transfer Acknowledge--Indicates that the external data transfer is complete. When FB_TA is asserted during a read transfer, FlexBus latches the data and then terminates the transfer. When FB_TA is asserted during a write transfer, the transfer is terminated. I If auto-acknowledge is disabled (CSCR[AA] = 0), the external memory or peripheral drives FB_TA to terminate the transfer. If auto-acknowledge is enabled (CSCR[AA] = 1), FB_TA is generated internally after a specified number of wait states, or the external memory or peripheral may assert external FB_TA before the waitstate countdown to terminate the transfer early. The chip deasserts FB_CS one cycle after the last FB_TA is asserted. During read transfers, the external memory or peripheral must continue to drive data until FB_TA is recognized. For write transfers, the chip continues driving data one clock cycle after FB_CS is deasserted. The number of wait states is determined by CSCR or the external FB_TA input. If the external FB_TA is used, the external memory or peripheral has complete control of the number of wait states. Note: External memory or peripherals should assert FB_TA only while the FB_CS signal to the external memory or peripheral is asserted. The CSPMCR register controls muxing of FB_TA with other signals. When the CSPMCR register does not allow fb_ta control, auto-acknowledge must be used (CSCR[AA] =1'b1); otherwise the bus may hang. FB_TBST FB_TBST Transfer Burst--Indicates that a burst transfer is in progress as driven by the chip. A burst transfer can be 2 to 16 beats depending on FB_TSIZ1-FB_TSIZ0 and the port size. O Note: When a burst transfer is in progress (FB_TBST = 0b), the transfer size is 16 bytes (FB_TSIZ1-FB_TSIZ0 = 11b), and the address is misaligned within the 16-byte boundary, the external memory or peripheral must be able to wrap around the address. 1. FB_AD[23:21] not available on 100-LQFP devices. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 207 Module Signal Description Tables 2. FB_CS3not available on 100-LQFP devices. 3. FB_BE7_0_BLS31_24not available on 100-LQFP devices. 4. FB_TAnotavailable on 100-LQFP devices. 10.4.5 Analog Table 10-10. ADC 0 Signal Descriptions Chip signal name Module signal name Description I/O ADC0_DP[3:0] DADP3-DADP0 Differential Analog Channel Inputs I ADC0_DM[3:0] DADM3-DADM0 Differential Analog Channel Inputs I ADC0_SEn ADn Single-Ended Analog Channel Inputs I VREFH VREFSH Voltage Reference Select High I VREFL VREFSL Voltage Reference Select Low I VDDA VDDA Analog Power Supply I VSSA VSSA Analog Ground I Table 10-11. ADC 1 Signal Descriptions Chip signal name Module signal name Description I/O ADC1_DP3, ADC1_DP[1:0] DADP3-DADP0 Differential Analog Channel Inputs I ADC1_DM3, ADC1_DM[1:0] DADM3-DADM0 Differential Analog Channel Inputs I ADC1_SEn ADn Single-Ended Analog Channel Inputs I VREFH VREFSH Voltage Reference Select High I VREFL VREFSL Voltage Reference Select Low I VDDA VDDA Analog Power Supply I VSSA VSSA Analog Ground I Table 10-12. CMP 0 Signal Descriptions Chip signal name Module signal name Description I/O CMP0_IN[5:0] IN[5:0] Analog voltage inputs I CMP0_OUT CMPO Comparator output O Table 10-13. CMP 1 Signal Descriptions Chip signal name Module signal name Description I/O CMP1_IN[5:0] IN[5:0] Analog voltage inputs I CMP1_OUT CMPO Comparator output O KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 208 Freescale Semiconductor, Inc. Chapter 10 Signal Multiplexing and Signal Descriptions Table 10-14. DAC 0 Signal Descriptions Chip signal name Module signal name DAC0_OUT -- Description I/O DAC output O Table 10-15. DAC 1 Signal Descriptions Chip signal name Module signal name DAC1_OUT -- Description I/O DAC output O Table 10-16. VREF Signal Descriptions Chip signal name Module signal name VREF_OUT VREF_OUT Description I/O Internally-generated Voltage Reference output O 10.4.6 Timer Modules Table 10-17. FTM 0 Signal Descriptions Chip signal name Module signal name FTM_CLKIN[1:0] EXTCLK FTM0_CH[7:0] CHn FTM0_FLT[3:0] FAULTj Description External clock. FTM external clock can be selected to drive the FTM counter. FTM channel (n), where n can be 7-0 Fault input (j), where j can be 3-0 I/O I I/O I Table 10-18. FTM 1 Signal Descriptions Chip signal name Module signal name FTM_CLKIN[1:0] EXTCLK FTM1_CH[1:0] CHn FTM1_FLT0 FAULTj FTM1_QD_PHA FTM1_QD_PHB Description External clock. FTM external clock can be selected to drive the FTM counter. FTM channel (n), where n can be 7-0 I/O I I/O Fault input (j), where j can be 3-0 I PHA Quadrature decoder phase A input. Input pin associated with quadrature decoder phase A. I PHB Quadrature decoder phase B input. Input pin associated with quadrature decoder phase B. I KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 209 Module Signal Description Tables Table 10-19. FTM 2 Signal Descriptions Chip signal name Module signal name FTM_CLKIN[1:0] EXTCLK FTM2_CH[1:0] CHn FTM2_FLT0 FAULTj FTM2_QD_PHA FTM2_QD_PHB Description I/O External clock. FTM external clock can be selected to drive the FTM counter. FTM channel (n), where n can be 7-0 I I/O Fault input (j), where j can be 3-0 I PHA Quadrature decoder phase A input. Input pin associated with quadrature decoder phase A. I PHB Quadrature decoder phase B input. Input pin associated with quadrature decoder phase B. I Table 10-20. FTM 3 Signal Descriptions Chip signal name Module signal name FTM_CLKIN[1:0] EXTCLK FTM3_CH[7:0] CHn FTM3_FLT0 FAULTj Description I/O External clock. FTM external clock can be selected to drive the FTM counter. FTM channel (n), where n can be 7-0 I I/O Fault input (j), where j can be 3-0 I Table 10-21. PDB 0 Signal Descriptions Chip signal name Module signal name PDB0_EXTRG EXTRG Description I/O External Trigger Input Source I If the PDB is enabled and external trigger input source is selected, a positive edge on the EXTRG signal resets and starts the counter. Table 10-22. LPTMR 0 Signal Descriptions Chip signal name Module signal name Description LPTMR0_ALT[:1] LPTMR0_ALTn Pulse Counter Input pin I/O I 10.4.7 Communication Interfaces Table 10-23. SPI 0 Signal Descriptions Chip signal name Module signal name Description I/O SPI0_PCS0 PCS0/SS Peripheral Chip Select 0 (O) I/O SPI0_PCS[3:1] PCS[1:3] Peripheral Chip Selects 1-3 O Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 210 Freescale Semiconductor, Inc. Chapter 10 Signal Multiplexing and Signal Descriptions Table 10-23. SPI 0 Signal Descriptions (continued) Chip signal name Module signal name Description I/O SPI0_PCS4 PCS4 Peripheral Chip Select 4 O SPI0_PCS5 PCS5/ PCSS Peripheral Chip Select 5 /Peripheral Chip Select Strobe O SPI0_SIN SIN Serial Data In I SPI0_SOUT SOUT Serial Data Out O SPI0_SCK SCK Serial Clock (O) I/O Table 10-24. SPI 1 Signal Descriptions Chip signal name Module signal name Description I/O SPI1_PCS0 PCS0/SS Peripheral Chip Select 0 (O) I/O SPI1_PCS[3:1] PCS[1:3] Peripheral Chip Selects 1-3 O SPI1_SIN SIN Serial Data In I SPI1_SOUT SOUT Serial Data Out O SPI1_SCK SCK Serial Clock (O) I/O Table 10-25. I2C 0 Signal Descriptions Chip signal name Module signal name I2C0_SCL SCL I2C0_SDA SDA Description I/O Bidirectional serial clock line of the I2C system. Bidirectional serial data line of the I2C system. I/O I/O Table 10-26. I2C 1 Signal Descriptions Chip signal name Module signal name I2C1_SCL SCL I2C1_SDA SDA Description I/O Bidirectional serial clock line of the I2C system. Bidirectional serial data line of the I2C system. I/O I/O Table 10-27. LPUART Signal Descriptions Chip signal name Module signal name Description I/O UART0_TX TxD Transmit Data O UART0_RX RxD Receive Data I KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 211 Module Signal Description Tables Table 10-28. UART 0 Signal Descriptions Chip signal name Module signal name Description I/O UART0_CTS CTS Clear to send I UART0_RTS RTS Request to send O UART0_TX TXD Transmit data O UART0_RX RXD Receive data I Table 10-29. UART 1 Signal Descriptions Chip signal name Module signal name Description I/O UART1_CTS CTS Clear to send I UART1_RTS RTS Request to send O UART1_TX TXD Transmit data O UART1_RX RXD Receive data I Table 10-30. UART 2 Signal Descriptions Chip signal name Module signal name Description I/O UART2_CTS CTS Clear to send I UART2_RTS RTS Request to send O UART2_TX TXD Transmit data O UART2_RX RXD Receive data I 10.4.8 Human-Machine Interfaces (HMI) Table 10-31. GPIO Signal Descriptions Chip signal name Module signal name Description I/O PTA[31:0]1 PORTA31-PORTA0 General-purpose input/output I/O PTB[31:0]1 PORTB31-PORTB0 General-purpose input/output I/O PTC[31:0]1 PORTC31-PORTC0 General-purpose input/output I/O PTD[31:0]1 PORTD31-PORTD0 General-purpose input/output I/O PTE[31:0]1 PORTE31-PORTE0 General-purpose input/output I/O 1. The available GPIO pins depends on the specific package. See the signal multiplexing section for which exact GPIO signals are available. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 212 Freescale Semiconductor, Inc. Chapter 11 Port Control and Interrupts (PORT) 11.1 Introduction NOTE For the chip-specific implementation details of this module's instances, see the chip configuration information. 11.2 Overview The Port Control and Interrupt (PORT) module provides support for port control, digital filtering, and external interrupt functions. Most functions can be configured independently for each pin in the 32-bit port and affect the pin regardless of its pin muxing state. There is one instance of the PORT module for each port. Not all pins within each port are implemented on a specific device. 11.2.1 Features The PORT module has the following features: * Pin interrupt * Interrupt flag and enable registers for each pin * Support for edge sensitive (rising, falling, both) or level sensitive (low, high) configured per pin * Support for interrupt or DMA request configured per pin * Asynchronous wake-up in low-power modes * Pin interrupt is functional in all digital pin muxing modes * Digital input filter on selected pins KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 213 Overview * Digital input filter for each pin, usable by any digital peripheral muxed onto the pin * Individual enable or bypass control field per pin * Selectable clock source for digital input filter with a five bit resolution on filter size * Functional in all digital pin multiplexing modes * Port control * Individual pull control fields with pullup, pulldown, and pull-disable support * Individual drive strength field supporting high and low drive strength * Individual slew rate field supporting fast and slow slew rates * Individual input passive filter field supporting enable and disable of the individual input passive filter * Individual open drain field supporting enable and disable of the individual open drain output * Individual mux control field supporting analog or pin disabled, GPIO, and up to six chip-specific digital functions * Pad configuration fields are functional in all digital pin muxing modes. 11.2.2 Modes of operation 11.2.2.1 Run mode In Run mode, the PORT operates normally. 11.2.2.2 Wait mode In Wait mode, PORT continues to operate normally and may be configured to exit the Low-Power mode if an enabled interrupt is detected. DMA requests are still generated during the Wait mode, but do not cause an exit from the Low-Power mode. 11.2.2.3 Stop mode In Stop mode, the PORT can be configured to exit the Low-Power mode via an asynchronous wake-up signal if an enabled interrupt is detected. In Stop mode, the digital input filters are bypassed unless they are configured to run from the LPO clock source. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 214 Freescale Semiconductor, Inc. Chapter 11 Port Control and Interrupts (PORT) 11.2.2.4 Debug mode In Debug mode, PORT operates normally. 11.3 External signal description The table found here describes the PORT external signal. Table 11-1. Signal properties Name Function I/O Reset Pull PORTx[31:0] External interrupt I/O 0 - NOTE Not all pins within each port are implemented on each device. 11.4 Detailed signal description The table found here contains the detailed signal description for the PORT interface. Table 11-2. PORT interface--detailed signal description Signal PORTx[31:0] I/O I/O Description External interrupt. State meaning Asserted--pin is logic 1. Negated--pin is logic 0. Timing Assertion--may occur at any time and can assert asynchronously to the system clock. Negation--may occur at any time and can assert asynchronously to the system clock. 11.5 Memory map and register definition Any read or write access to the PORT memory space that is outside the valid memory map results in a bus error. All register accesses complete with zero wait states. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 215 Memory map and register definition PORT memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4004_9000 Pin Control Register n (PORTA_PCR0) 32 R/W See section 11.5.1/222 4004_9004 Pin Control Register n (PORTA_PCR1) 32 R/W See section 11.5.1/222 4004_9008 Pin Control Register n (PORTA_PCR2) 32 R/W See section 11.5.1/222 4004_900C Pin Control Register n (PORTA_PCR3) 32 R/W See section 11.5.1/222 4004_9010 Pin Control Register n (PORTA_PCR4) 32 R/W See section 11.5.1/222 4004_9014 Pin Control Register n (PORTA_PCR5) 32 R/W See section 11.5.1/222 4004_9018 Pin Control Register n (PORTA_PCR6) 32 R/W See section 11.5.1/222 4004_901C Pin Control Register n (PORTA_PCR7) 32 R/W See section 11.5.1/222 4004_9020 Pin Control Register n (PORTA_PCR8) 32 R/W See section 11.5.1/222 4004_9024 Pin Control Register n (PORTA_PCR9) 32 R/W See section 11.5.1/222 4004_9028 Pin Control Register n (PORTA_PCR10) 32 R/W See section 11.5.1/222 4004_902C Pin Control Register n (PORTA_PCR11) 32 R/W See section 11.5.1/222 4004_9030 Pin Control Register n (PORTA_PCR12) 32 R/W See section 11.5.1/222 4004_9034 Pin Control Register n (PORTA_PCR13) 32 R/W See section 11.5.1/222 4004_9038 Pin Control Register n (PORTA_PCR14) 32 R/W See section 11.5.1/222 4004_903C Pin Control Register n (PORTA_PCR15) 32 R/W See section 11.5.1/222 4004_9040 Pin Control Register n (PORTA_PCR16) 32 R/W See section 11.5.1/222 4004_9044 Pin Control Register n (PORTA_PCR17) 32 R/W See section 11.5.1/222 4004_9048 Pin Control Register n (PORTA_PCR18) 32 R/W See section 11.5.1/222 4004_904C Pin Control Register n (PORTA_PCR19) 32 R/W See section 11.5.1/222 4004_9050 Pin Control Register n (PORTA_PCR20) 32 R/W See section 11.5.1/222 4004_9054 Pin Control Register n (PORTA_PCR21) 32 R/W See section 11.5.1/222 4004_9058 Pin Control Register n (PORTA_PCR22) 32 R/W See section 11.5.1/222 4004_905C Pin Control Register n (PORTA_PCR23) 32 R/W See section 11.5.1/222 4004_9060 Pin Control Register n (PORTA_PCR24) 32 R/W See section 11.5.1/222 4004_9064 Pin Control Register n (PORTA_PCR25) 32 R/W See section 11.5.1/222 4004_9068 Pin Control Register n (PORTA_PCR26) 32 R/W See section 11.5.1/222 4004_906C Pin Control Register n (PORTA_PCR27) 32 R/W See section 11.5.1/222 4004_9070 Pin Control Register n (PORTA_PCR28) 32 R/W See section 11.5.1/222 4004_9074 Pin Control Register n (PORTA_PCR29) 32 R/W See section 11.5.1/222 4004_9078 Pin Control Register n (PORTA_PCR30) 32 R/W See section 11.5.1/222 4004_907C Pin Control Register n (PORTA_PCR31) 32 R/W See section 11.5.1/222 4004_9080 Global Pin Control Low Register (PORTA_GPCLR) 32 W (always 0000_0000h reads 0) 11.5.2/225 4004_9084 Global Pin Control High Register (PORTA_GPCHR) 32 W (always 0000_0000h reads 0) 11.5.3/225 4004_90A0 Interrupt Status Flag Register (PORTA_ISFR) 32 w1c 0000_0000h 11.5.4/226 Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 216 Freescale Semiconductor, Inc. Chapter 11 Port Control and Interrupts (PORT) PORT memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4004_90C0 Digital Filter Enable Register (PORTA_DFER) 32 R/W 0000_0000h 11.5.5/226 4004_90C4 Digital Filter Clock Register (PORTA_DFCR) 32 R/W 0000_0000h 11.5.6/227 4004_90C8 Digital Filter Width Register (PORTA_DFWR) 32 R/W 0000_0000h 11.5.7/227 4004_A000 Pin Control Register n (PORTB_PCR0) 32 R/W See section 11.5.1/222 4004_A004 Pin Control Register n (PORTB_PCR1) 32 R/W See section 11.5.1/222 4004_A008 Pin Control Register n (PORTB_PCR2) 32 R/W See section 11.5.1/222 4004_A00C Pin Control Register n (PORTB_PCR3) 32 R/W See section 11.5.1/222 4004_A010 Pin Control Register n (PORTB_PCR4) 32 R/W See section 11.5.1/222 4004_A014 Pin Control Register n (PORTB_PCR5) 32 R/W See section 11.5.1/222 4004_A018 Pin Control Register n (PORTB_PCR6) 32 R/W See section 11.5.1/222 4004_A01C Pin Control Register n (PORTB_PCR7) 32 R/W See section 11.5.1/222 4004_A020 Pin Control Register n (PORTB_PCR8) 32 R/W See section 11.5.1/222 4004_A024 Pin Control Register n (PORTB_PCR9) 32 R/W See section 11.5.1/222 4004_A028 Pin Control Register n (PORTB_PCR10) 32 R/W See section 11.5.1/222 4004_A02C Pin Control Register n (PORTB_PCR11) 32 R/W See section 11.5.1/222 4004_A030 Pin Control Register n (PORTB_PCR12) 32 R/W See section 11.5.1/222 4004_A034 Pin Control Register n (PORTB_PCR13) 32 R/W See section 11.5.1/222 4004_A038 Pin Control Register n (PORTB_PCR14) 32 R/W See section 11.5.1/222 4004_A03C Pin Control Register n (PORTB_PCR15) 32 R/W See section 11.5.1/222 4004_A040 Pin Control Register n (PORTB_PCR16) 32 R/W See section 11.5.1/222 4004_A044 Pin Control Register n (PORTB_PCR17) 32 R/W See section 11.5.1/222 4004_A048 Pin Control Register n (PORTB_PCR18) 32 R/W See section 11.5.1/222 4004_A04C Pin Control Register n (PORTB_PCR19) 32 R/W See section 11.5.1/222 4004_A050 Pin Control Register n (PORTB_PCR20) 32 R/W See section 11.5.1/222 4004_A054 Pin Control Register n (PORTB_PCR21) 32 R/W See section 11.5.1/222 4004_A058 Pin Control Register n (PORTB_PCR22) 32 R/W See section 11.5.1/222 4004_A05C Pin Control Register n (PORTB_PCR23) 32 R/W See section 11.5.1/222 4004_A060 Pin Control Register n (PORTB_PCR24) 32 R/W See section 11.5.1/222 4004_A064 Pin Control Register n (PORTB_PCR25) 32 R/W See section 11.5.1/222 4004_A068 Pin Control Register n (PORTB_PCR26) 32 R/W See section 11.5.1/222 4004_A06C Pin Control Register n (PORTB_PCR27) 32 R/W See section 11.5.1/222 4004_A070 Pin Control Register n (PORTB_PCR28) 32 R/W See section 11.5.1/222 4004_A074 Pin Control Register n (PORTB_PCR29) 32 R/W See section 11.5.1/222 4004_A078 Pin Control Register n (PORTB_PCR30) 32 R/W See section 11.5.1/222 4004_A07C Pin Control Register n (PORTB_PCR31) 32 R/W See section 11.5.1/222 4004_A080 32 W (always 0000_0000h reads 0) 11.5.2/225 Global Pin Control Low Register (PORTB_GPCLR) Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 217 Memory map and register definition PORT memory map (continued) Absolute address (hex) 4004_A084 Register name Global Pin Control High Register (PORTB_GPCHR) Width Access (in bits) 32 Reset value W (always 0000_0000h reads 0) Section/ page 11.5.3/225 4004_A0A0 Interrupt Status Flag Register (PORTB_ISFR) 32 w1c 0000_0000h 11.5.4/226 4004_A0C0 Digital Filter Enable Register (PORTB_DFER) 32 R/W 0000_0000h 11.5.5/226 4004_A0C4 Digital Filter Clock Register (PORTB_DFCR) 32 R/W 0000_0000h 11.5.6/227 4004_A0C8 Digital Filter Width Register (PORTB_DFWR) 32 R/W 0000_0000h 11.5.7/227 4004_B000 Pin Control Register n (PORTC_PCR0) 32 R/W See section 11.5.1/222 4004_B004 Pin Control Register n (PORTC_PCR1) 32 R/W See section 11.5.1/222 4004_B008 Pin Control Register n (PORTC_PCR2) 32 R/W See section 11.5.1/222 4004_B00C Pin Control Register n (PORTC_PCR3) 32 R/W See section 11.5.1/222 4004_B010 Pin Control Register n (PORTC_PCR4) 32 R/W See section 11.5.1/222 4004_B014 Pin Control Register n (PORTC_PCR5) 32 R/W See section 11.5.1/222 4004_B018 Pin Control Register n (PORTC_PCR6) 32 R/W See section 11.5.1/222 4004_B01C Pin Control Register n (PORTC_PCR7) 32 R/W See section 11.5.1/222 4004_B020 Pin Control Register n (PORTC_PCR8) 32 R/W See section 11.5.1/222 4004_B024 Pin Control Register n (PORTC_PCR9) 32 R/W See section 11.5.1/222 4004_B028 Pin Control Register n (PORTC_PCR10) 32 R/W See section 11.5.1/222 4004_B02C Pin Control Register n (PORTC_PCR11) 32 R/W See section 11.5.1/222 4004_B030 Pin Control Register n (PORTC_PCR12) 32 R/W See section 11.5.1/222 4004_B034 Pin Control Register n (PORTC_PCR13) 32 R/W See section 11.5.1/222 4004_B038 Pin Control Register n (PORTC_PCR14) 32 R/W See section 11.5.1/222 4004_B03C Pin Control Register n (PORTC_PCR15) 32 R/W See section 11.5.1/222 4004_B040 Pin Control Register n (PORTC_PCR16) 32 R/W See section 11.5.1/222 4004_B044 Pin Control Register n (PORTC_PCR17) 32 R/W See section 11.5.1/222 4004_B048 Pin Control Register n (PORTC_PCR18) 32 R/W See section 11.5.1/222 4004_B04C Pin Control Register n (PORTC_PCR19) 32 R/W See section 11.5.1/222 4004_B050 Pin Control Register n (PORTC_PCR20) 32 R/W See section 11.5.1/222 4004_B054 Pin Control Register n (PORTC_PCR21) 32 R/W See section 11.5.1/222 4004_B058 Pin Control Register n (PORTC_PCR22) 32 R/W See section 11.5.1/222 4004_B05C Pin Control Register n (PORTC_PCR23) 32 R/W See section 11.5.1/222 4004_B060 Pin Control Register n (PORTC_PCR24) 32 R/W See section 11.5.1/222 4004_B064 Pin Control Register n (PORTC_PCR25) 32 R/W See section 11.5.1/222 4004_B068 Pin Control Register n (PORTC_PCR26) 32 R/W See section 11.5.1/222 4004_B06C Pin Control Register n (PORTC_PCR27) 32 R/W See section 11.5.1/222 4004_B070 Pin Control Register n (PORTC_PCR28) 32 R/W See section 11.5.1/222 4004_B074 Pin Control Register n (PORTC_PCR29) 32 R/W See section 11.5.1/222 4004_B078 Pin Control Register n (PORTC_PCR30) 32 R/W See section 11.5.1/222 Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 218 Freescale Semiconductor, Inc. Chapter 11 Port Control and Interrupts (PORT) PORT memory map (continued) Absolute address (hex) Register name Width Access (in bits) R/W Reset value Section/ page See section 11.5.1/222 4004_B07C Pin Control Register n (PORTC_PCR31) 32 4004_B080 Global Pin Control Low Register (PORTC_GPCLR) 32 W (always 0000_0000h reads 0) 11.5.2/225 4004_B084 Global Pin Control High Register (PORTC_GPCHR) 32 W (always 0000_0000h reads 0) 11.5.3/225 4004_B0A0 Interrupt Status Flag Register (PORTC_ISFR) 32 w1c 0000_0000h 11.5.4/226 4004_B0C0 Digital Filter Enable Register (PORTC_DFER) 32 R/W 0000_0000h 11.5.5/226 4004_B0C4 Digital Filter Clock Register (PORTC_DFCR) 32 R/W 0000_0000h 11.5.6/227 4004_B0C8 Digital Filter Width Register (PORTC_DFWR) 32 R/W 0000_0000h 11.5.7/227 4004_C000 Pin Control Register n (PORTD_PCR0) 32 R/W See section 11.5.1/222 4004_C004 Pin Control Register n (PORTD_PCR1) 32 R/W See section 11.5.1/222 4004_C008 Pin Control Register n (PORTD_PCR2) 32 R/W See section 11.5.1/222 4004_C00C Pin Control Register n (PORTD_PCR3) 32 R/W See section 11.5.1/222 4004_C010 Pin Control Register n (PORTD_PCR4) 32 R/W See section 11.5.1/222 4004_C014 Pin Control Register n (PORTD_PCR5) 32 R/W See section 11.5.1/222 4004_C018 Pin Control Register n (PORTD_PCR6) 32 R/W See section 11.5.1/222 4004_C01C Pin Control Register n (PORTD_PCR7) 32 R/W See section 11.5.1/222 4004_C020 Pin Control Register n (PORTD_PCR8) 32 R/W See section 11.5.1/222 4004_C024 Pin Control Register n (PORTD_PCR9) 32 R/W See section 11.5.1/222 4004_C028 Pin Control Register n (PORTD_PCR10) 32 R/W See section 11.5.1/222 4004_C02C Pin Control Register n (PORTD_PCR11) 32 R/W See section 11.5.1/222 4004_C030 Pin Control Register n (PORTD_PCR12) 32 R/W See section 11.5.1/222 4004_C034 Pin Control Register n (PORTD_PCR13) 32 R/W See section 11.5.1/222 4004_C038 Pin Control Register n (PORTD_PCR14) 32 R/W See section 11.5.1/222 4004_C03C Pin Control Register n (PORTD_PCR15) 32 R/W See section 11.5.1/222 4004_C040 Pin Control Register n (PORTD_PCR16) 32 R/W See section 11.5.1/222 4004_C044 Pin Control Register n (PORTD_PCR17) 32 R/W See section 11.5.1/222 4004_C048 Pin Control Register n (PORTD_PCR18) 32 R/W See section 11.5.1/222 4004_C04C Pin Control Register n (PORTD_PCR19) 32 R/W See section 11.5.1/222 4004_C050 Pin Control Register n (PORTD_PCR20) 32 R/W See section 11.5.1/222 4004_C054 Pin Control Register n (PORTD_PCR21) 32 R/W See section 11.5.1/222 4004_C058 Pin Control Register n (PORTD_PCR22) 32 R/W See section 11.5.1/222 4004_C05C Pin Control Register n (PORTD_PCR23) 32 R/W See section 11.5.1/222 4004_C060 Pin Control Register n (PORTD_PCR24) 32 R/W See section 11.5.1/222 4004_C064 Pin Control Register n (PORTD_PCR25) 32 R/W See section 11.5.1/222 4004_C068 Pin Control Register n (PORTD_PCR26) 32 R/W See section 11.5.1/222 4004_C06C Pin Control Register n (PORTD_PCR27) 32 R/W See section 11.5.1/222 Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 219 Memory map and register definition PORT memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4004_C070 Pin Control Register n (PORTD_PCR28) 32 R/W See section 11.5.1/222 4004_C074 Pin Control Register n (PORTD_PCR29) 32 R/W See section 11.5.1/222 4004_C078 Pin Control Register n (PORTD_PCR30) 32 R/W See section 11.5.1/222 4004_C07C Pin Control Register n (PORTD_PCR31) 32 R/W See section 11.5.1/222 11.5.2/225 11.5.3/225 4004_C080 Global Pin Control Low Register (PORTD_GPCLR) 32 W (always 0000_0000h reads 0) 4004_C084 Global Pin Control High Register (PORTD_GPCHR) 32 W (always 0000_0000h reads 0) 4004_C0A0 Interrupt Status Flag Register (PORTD_ISFR) 32 w1c 0000_0000h 11.5.4/226 4004_C0C0 Digital Filter Enable Register (PORTD_DFER) 32 R/W 0000_0000h 11.5.5/226 4004_C0C4 Digital Filter Clock Register (PORTD_DFCR) 32 R/W 0000_0000h 11.5.6/227 4004_C0C8 Digital Filter Width Register (PORTD_DFWR) 32 R/W 0000_0000h 11.5.7/227 4004_D000 Pin Control Register n (PORTE_PCR0) 32 R/W See section 11.5.1/222 4004_D004 Pin Control Register n (PORTE_PCR1) 32 R/W See section 11.5.1/222 4004_D008 Pin Control Register n (PORTE_PCR2) 32 R/W See section 11.5.1/222 4004_D00C Pin Control Register n (PORTE_PCR3) 32 R/W See section 11.5.1/222 4004_D010 Pin Control Register n (PORTE_PCR4) 32 R/W See section 11.5.1/222 4004_D014 Pin Control Register n (PORTE_PCR5) 32 R/W See section 11.5.1/222 4004_D018 Pin Control Register n (PORTE_PCR6) 32 R/W See section 11.5.1/222 4004_D01C Pin Control Register n (PORTE_PCR7) 32 R/W See section 11.5.1/222 4004_D020 Pin Control Register n (PORTE_PCR8) 32 R/W See section 11.5.1/222 4004_D024 Pin Control Register n (PORTE_PCR9) 32 R/W See section 11.5.1/222 4004_D028 Pin Control Register n (PORTE_PCR10) 32 R/W See section 11.5.1/222 4004_D02C Pin Control Register n (PORTE_PCR11) 32 R/W See section 11.5.1/222 4004_D030 Pin Control Register n (PORTE_PCR12) 32 R/W See section 11.5.1/222 4004_D034 Pin Control Register n (PORTE_PCR13) 32 R/W See section 11.5.1/222 4004_D038 Pin Control Register n (PORTE_PCR14) 32 R/W See section 11.5.1/222 4004_D03C Pin Control Register n (PORTE_PCR15) 32 R/W See section 11.5.1/222 4004_D040 Pin Control Register n (PORTE_PCR16) 32 R/W See section 11.5.1/222 4004_D044 Pin Control Register n (PORTE_PCR17) 32 R/W See section 11.5.1/222 4004_D048 Pin Control Register n (PORTE_PCR18) 32 R/W See section 11.5.1/222 4004_D04C Pin Control Register n (PORTE_PCR19) 32 R/W See section 11.5.1/222 4004_D050 Pin Control Register n (PORTE_PCR20) 32 R/W See section 11.5.1/222 4004_D054 Pin Control Register n (PORTE_PCR21) 32 R/W See section 11.5.1/222 4004_D058 Pin Control Register n (PORTE_PCR22) 32 R/W See section 11.5.1/222 4004_D05C Pin Control Register n (PORTE_PCR23) 32 R/W See section 11.5.1/222 4004_D060 32 R/W See section 11.5.1/222 Pin Control Register n (PORTE_PCR24) Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 220 Freescale Semiconductor, Inc. Chapter 11 Port Control and Interrupts (PORT) PORT memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4004_D064 Pin Control Register n (PORTE_PCR25) 32 R/W See section 11.5.1/222 4004_D068 Pin Control Register n (PORTE_PCR26) 32 R/W See section 11.5.1/222 4004_D06C Pin Control Register n (PORTE_PCR27) 32 R/W See section 11.5.1/222 4004_D070 Pin Control Register n (PORTE_PCR28) 32 R/W See section 11.5.1/222 4004_D074 Pin Control Register n (PORTE_PCR29) 32 R/W See section 11.5.1/222 4004_D078 Pin Control Register n (PORTE_PCR30) 32 R/W See section 11.5.1/222 4004_D07C Pin Control Register n (PORTE_PCR31) 32 R/W See section 11.5.1/222 4004_D080 Global Pin Control Low Register (PORTE_GPCLR) 32 W (always 0000_0000h reads 0) 11.5.2/225 4004_D084 Global Pin Control High Register (PORTE_GPCHR) 32 W (always 0000_0000h reads 0) 11.5.3/225 4004_D0A0 Interrupt Status Flag Register (PORTE_ISFR) 32 w1c 0000_0000h 11.5.4/226 4004_D0C0 Digital Filter Enable Register (PORTE_DFER) 32 R/W 0000_0000h 11.5.5/226 4004_D0C4 Digital Filter Clock Register (PORTE_DFCR) 32 R/W 0000_0000h 11.5.6/227 4004_D0C8 Digital Filter Width Register (PORTE_DFWR) 32 R/W 0000_0000h 11.5.7/227 KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 221 Memory map and register definition 11.5.1 Pin Control Register n (PORTx_PCRn) NOTE See the Signal Multiplexing and Pin Assignment chapter for the reset value of this device. See the GPIO Configuration section for details on the available functions for each pin. Do not modify pin configuration registers associated with pins not available in your selected package. All unbonded pins not available in your package will default to DISABLE state for lowest power consumption. Address: Base address + 0h offset + (4d x i), where i=0d to 31d Bit 31 30 29 28 27 26 25 0 R 24 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Reset 21 20 19 18 0 0 LK 0 0 0 MUX 0 * * 0 0 0 0 7 6 5 4 0 * * 0 17 16 IRQC w1c Reset W 22 ISF W R 23 DSE ODE PFE * 0 * 0 0 0 0 3 2 1 0 SRE PE PS * * * 0 0 * Notes: * MUX field: Varies by port. See Signal Multiplexing and Signal Descriptions chapter for reset values per port. * DSE field: Varies by port. See the Signal Multiplexing and Signal Descriptions chapter for reset values per port. * PFE field: Varies by port. See Signal Multiplexing and Signal Descriptions chapter for reset values per port. * SRE field: Varies by port. See Signal Multiplexing and Signal Descriptions chapter for reset values per port. * PE field: Varies by port. See Signal Multiplexing and Signal Descriptions chapter for reset values per port. * PS field: Varies by port. See Signal Multiplexing and Signal Descriptions chapter for reset values per port. PORTx_PCRn field descriptions Field 31-25 Reserved 24 ISF Description This field is reserved. This read-only field is reserved and always has the value 0. Interrupt Status Flag The pin interrupt configuration is valid in all digital pin muxing modes. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 222 Freescale Semiconductor, Inc. Chapter 11 Port Control and Interrupts (PORT) PORTx_PCRn field descriptions (continued) Field Description 0 1 23-20 Reserved 19-16 IRQC Configured interrupt is not detected. Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. This field is reserved. This read-only field is reserved and always has the value 0. Interrupt Configuration The pin interrupt configuration is valid in all digital pin muxing modes. The corresponding pin is configured to generate interrupt/DMA request as follows: 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 15 LK 14-12 Reserved 11-8 MUX Interrupt Status Flag (ISF) is disabled. ISF flag and DMA request on rising edge. ISF flag and DMA request on falling edge. ISF flag and DMA request on either edge. Reserved. Reserved. Reserved. Reserved. ISF flag and Interrupt when logic 0. ISF flag and Interrupt on rising-edge. ISF flag and Interrupt on falling-edge. ISF flag and Interrupt on either edge. ISF flag and Interrupt when logic 1. Reserved. Reserved. Reserved. Lock Register 0 1 Pin Control Register fields [15:0] are not locked. Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. This field is reserved. This read-only field is reserved and always has the value 0. Pin Mux Control Not all pins support all pin muxing slots. Unimplemented pin muxing slots are reserved and may result in configuring the pin for a different pin muxing slot. The corresponding pin is configured in the following pin muxing slot as follows: 0000 0001 0010 0011 0100 0101 0110 0111 Pin disabled. Alternative 1 (GPIO). Alternative 2 (chip-specific). Alternative 3 (chip-specific). Alternative 4 (chip-specific). Alternative 5 (chip-specific). Alternative 6 (chip-specific). Alternative 7 (chip-specific). Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 223 Memory map and register definition PORTx_PCRn field descriptions (continued) Field Description 1000 1001 1010 1011 1100 1101 1110 1111 7 Reserved 6 DSE This field is reserved. This read-only field is reserved and always has the value 0. Drive Strength Enable Drive strength configuration is valid in all digital pin muxing modes. 0 1 5 ODE Open drain configuration is valid in all digital pin muxing modes. 2 SRE Passive filter configuration is valid in all digital pin muxing modes. Slew Rate Enable Slew rate configuration is valid in all digital pin muxing modes. Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. Pull Enable Pull configuration is valid in all digital pin muxing modes. 0 1 0 PS Passive input filter is disabled on the corresponding pin. Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. This field is reserved. This read-only field is reserved and always has the value 0. 0 1 1 PE Open drain output is disabled on the corresponding pin. Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. Passive Filter Enable 0 1 3 Reserved Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. High drive strength is configured on the corresponding pin, if pin is configured as a digital output. Open Drain Enable 0 1 4 PFE Alternative 8 (chip-specific). Alternative 9 (chip-specific). Alternative 10 (chip-specific). Alternative 11 (chip-specific). Alternative 12 (chip-specific). Alternative 13 (chip-specific). Alternative 14 (chip-specific). Alternative 15 (chip-specific). Internal pullup or pulldown resistor is not enabled on the corresponding pin. Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. Pull Select Pull configuration is valid in all digital pin muxing modes. 0 1 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 224 Freescale Semiconductor, Inc. Chapter 11 Port Control and Interrupts (PORT) 11.5.2 Global Pin Control Low Register (PORTx_GPCLR) Only 32-bit writes are supported to this register. Address: Base address + 80h offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 R 0 0 W GPWE GPWD Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 5 4 3 2 1 0 0 0 0 0 0 0 0 PORTx_GPCLR field descriptions Field Description 31-16 GPWE Global Pin Write Enable Selects which Pin Control Registers (15 through 0) bits [15:0] update with the value in GPWD. If a selected Pin Control Register is locked then the write to that register is ignored. 0 1 GPWD Corresponding Pin Control Register is not updated with the value in GPWD. Corresponding Pin Control Register is updated with the value in GPWD. Global Pin Write Data Write value that is written to all Pin Control Registers bits [15:0] that are selected by GPWE. 11.5.3 Global Pin Control High Register (PORTx_GPCHR) Only 32-bit writes are supported to this register. Address: Base address + 84h offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 R 0 0 W GPWE GPWD Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 5 4 3 2 1 0 0 0 0 0 0 0 0 PORTx_GPCHR field descriptions Field 31-16 GPWE Description Global Pin Write Enable Selects which Pin Control Registers (31 through 16) bits [15:0] update with the value in GPWD. If a selected Pin Control Register is locked then the write to that register is ignored. 0 1 GPWD Corresponding Pin Control Register is not updated with the value in GPWD. Corresponding Pin Control Register is updated with the value in GPWD. Global Pin Write Data Write value that is written to all Pin Control Registers bits [15:0] that are selected by GPWE. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 225 Memory map and register definition 11.5.4 Interrupt Status Flag Register (PORTx_ISFR) The pin interrupt configuration is valid in all digital pin muxing modes. The Interrupt Status Flag for each pin is also visible in the corresponding Pin Control Register, and each flag can be cleared in either location. Address: Base address + A0h offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 R ISF W w1c Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORTx_ISFR field descriptions Field Description ISF Interrupt Status Flag Each bit in the field indicates the detection of the configured interrupt of the same number as the field. 0 1 Configured interrupt is not detected. Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. 11.5.5 Digital Filter Enable Register (PORTx_DFER) The corresponding bit is read only for pins that do not support a digital filter. Refer to the Chapter of Signal Multiplexing and Signal Descriptions for the pins that support digital filter. The digital filter configuration is valid in all digital pin muxing modes. Address: Base address + C0h offset Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DFE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORTx_DFER field descriptions Field DFE Description Digital Filter Enable KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 226 Freescale Semiconductor, Inc. Chapter 11 Port Control and Interrupts (PORT) PORTx_DFER field descriptions (continued) Field Description The digital filter configuration is valid in all digital pin muxing modes. The output of each digital filter is reset to zero at system reset and whenever the digital filter is disabled. Each bit in the field enables the digital filter of the same number as the field. 0 1 Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero. Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input. 11.5.6 Digital Filter Clock Register (PORTx_DFCR) This register is read only for ports that do not support a digital filter. The digital filter configuration is valid in all digital pin muxing modes. Address: Base address + C4h offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 R CS W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORTx_DFCR field descriptions Field 31-1 Reserved 0 CS Description This field is reserved. This read-only field is reserved and always has the value 0. Clock Source The digital filter configuration is valid in all digital pin muxing modes. Configures the clock source for the digital input filters. Changing the filter clock source must be done only when all digital filters are disabled. 0 1 Digital filters are clocked by the bus clock. Digital filters are clocked by the LPO clock. 11.5.7 Digital Filter Width Register (PORTx_DFWR) This register is read only for ports that do not support a digital filter. The digital filter configuration is valid in all digital pin muxing modes. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 227 Functional description Address: Base address + C8h offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 0 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 FILT W Reset 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORTx_DFWR field descriptions Field 31-5 Reserved FILT Description This field is reserved. This read-only field is reserved and always has the value 0. Filter Length The digital filter configuration is valid in all digital pin muxing modes. Configures the maximum size of the glitches, in clock cycles, that the digital filter absorbs for the enabled digital filters. Glitches that are longer than this register setting will pass through the digital filter, and glitches that are equal to or less than this register setting are filtered. Changing the filter length must be done only after all filters are disabled. 11.6 Functional description 11.6.1 Pin control Each port pin has a corresponding Pin Control register, PORT_PCRn, associated with it. The upper half of the Pin Control register configures the pin's capability to either interrupt the CPU or request a DMA transfer, on a rising/falling edge or both edges as well as a logic level occurring on the port pin. It also includes a flag to indicate that an interrupt has occurred. The lower half of the Pin Control register configures the following functions for each pin within the 32-bit port. * * * * * Pullup or pulldown enable Drive strength and slew rate configuration Open drain enable Passive input filter enable Pin Muxing mode The functions apply across all digital pin muxing modes and individual peripherals do not override the configuration in the Pin Control register. For example, if an I2C function is enabled on a pin, that does not override the pullup or open drain configuration for that pin. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 228 Freescale Semiconductor, Inc. Chapter 11 Port Control and Interrupts (PORT) When the Pin Muxing mode is configured for analog or is disabled, all the digital functions on that pin are disabled. This includes the pullup and pulldown enables, output buffer enable, input buffer enable, and passive filter enable. The LK bit (bit 15 of Pin Control Register PCRn) allows the configuration for each pin to be locked until the next system reset. When locked, writes to the lower half of that pin control register are ignored, although a bus error is not generated on an attempted write to a locked register. The configuration of each Pin Control register is retained when the PORT module is disabled. Whenever a pin is configured in any digital pin muxing mode, the input buffer for that pin is enabled allowing the pin state to be read via the corresponding GPIO Port Data Input Register (GPIO_PDIR) or allowing a pin interrupt or DMA request to be generated. If a pin is ever floating when its input buffer is enabled, then this can cause an increase in power consumption and must be avoided. A pin can be floating due to an input pin that is not connected or an output pin that has tri-stated (output buffer is disabled). Enabling the internal pull resistor (or implementing an external pull resistor) will ensure a pin does not float when its input buffer is enabled; note that the internal pull resistor is automatically disabled whenever the output buffer is enabled allowing the Pull Enable bit to remain set. Configuring the Pin Muxing mode to disabled or analog will disable the pin's input buffer and results in the lowest power consumption. 11.6.2 Global pin control The two global pin control registers allow a single register write to update the lower half of the pin control register on up to 16 pins, all with the same value. Registers that are locked cannot be written using the global pin control registers. The global pin control registers are designed to enable software to quickly configure multiple pins within the one port for the same peripheral function. However, the interrupt functions cannot be configured using the global pin control registers. The global pin control registers are write-only registers, that always read as 0. 11.6.3 External interrupts The external interrupt capability of the PORT module is available in all digital pin muxing modes provided the PORT module is enabled. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 229 Functional description Each pin can be individually configured for any of the following external interrupt modes: * * * * * * * * * Interrupt disabled, default out of reset Active high level sensitive interrupt Active low level sensitive interrupt Rising edge sensitive interrupt Falling edge sensitive interrupt Rising and falling edge sensitive interrupt Rising edge sensitive DMA request Falling edge sensitive DMA request Rising and falling edge sensitive DMA request The interrupt status flag is set when the configured edge or level is detected on the pin or at the output of the digital input filter, if the digital input digital filter is enabled. When not in Stop mode, the input is first synchronized to the bus clock to detect the configured level or edge transition. The PORT module generates a single interrupt that asserts when the interrupt status flag is set for any enabled interrupt for that port. The interrupt negates after the interrupt status flags for all enabled interrupts have been cleared by writing a logic 1 to the ISF flag in either the PORT_ISFR or PORT_PCRn registers. The PORT module generates a single DMA request that asserts when the interrupt status flag is set for any enabled DMA request in that port. The DMA request negates after the DMA transfer is completed, because that clears the interrupt status flags for all enabled DMA requests. During Stop mode, the interrupt status flag for any enabled interrupt is asynchronously set if the required level or edge is detected. This also generates an asynchronous wake-up signal to exit the Low-Power mode. 11.6.4 Digital filter The digital filter capabilities of the PORT module are available in all digital Pin Muxing modes if the PORT module is enabled. The clock used for all digital filters within one port can be configured between the bus clock or the LPO clock. This selection must be changed only when all digital filters for that port are disabled. If the digital filters for a port are configured to use the bus clock, then the digital filters are bypassed for the duration of Stop mode. While the digital filters KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 230 Freescale Semiconductor, Inc. Chapter 11 Port Control and Interrupts (PORT) are bypassed, the output of each digital filter always equals the input pin, but the internal state of the digital filters remains static and does not update due to any change on the input pin. The filter width in clock size is the same for all enabled digital filters within one port and must be changed only when all digital filters for that port are disabled. The output of each digital filter is logic zero after system reset and whenever a digital filter is disabled. After a digital filter is enabled, the input is synchronized to the filter clock, either the bus clock or the LPO clock. If the synchronized input and the output of the digital filter remain different for a number of filter clock cycles equal to the filter width register configuration, then the output of the digital filter updates to equal the synchronized filter input. The maximum latency through a digital filter equals three filter clock cycles plus the filter width configuration register. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 231 Functional description KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 232 Freescale Semiconductor, Inc. Chapter 12 System Integration Module (SIM) 12.1 Introduction NOTE For the chip-specific implementation details of this module's instances, see the chip configuration information. The System Integration Module (SIM) provides system control and chip configuration registers. 12.1.1 Features Features of the SIM include: * System clocking configuration * System clock divide values * Architectural clock gating control * Flash and system RAM size configuration * FlexTimer external clock, hardware trigger, and fault source selection * UART0 and UART1 receive/transmit source selection/configuration KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 233 Memory map and register definition 12.2 Memory map and register definition The SIM module contains many fields for selecting the clock source and dividers for various module clocks. See the Clock Distribution chapter for more information, including block diagrams and clock definitions. NOTE The SIM_SOPT1 and SIM_SOPT1CFG registers are located at a different base address than the other SIM registers. SIM memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4004_7000 System Options Register 1 (SIM_SOPT1) 32 R/W See section 12.2.1/235 4004_7004 SOPT1 Configuration Register (SIM_SOPT1CFG) 32 R/W 0000_0000h 12.2.2/236 4004_8004 System Options Register 2 (SIM_SOPT2) 32 R/W 0000_1000h 12.2.3/237 4004_800C System Options Register 4 (SIM_SOPT4) 32 R/W 0000_0000h 12.2.4/239 4004_8010 System Options Register 5 (SIM_SOPT5) 32 R/W 0000_0000h 12.2.5/242 4004_8018 System Options Register 7 (SIM_SOPT7) 32 R/W 0000_0000h 12.2.6/243 4004_801C System Options Register 8 (SIM_SOPT8) 32 R/W 0000_0000h 12.2.7/245 4004_8024 System Device Identification Register (SIM_SDID) 32 R See section 12.2.8/247 4004_8034 System Clock Gating Control Register 4 (SIM_SCGC4) 32 R/W F010_0030h 12.2.9/249 4004_8038 System Clock Gating Control Register 5 (SIM_SCGC5) 32 R/W 0004_0182h 12.2.10/251 4004_803C System Clock Gating Control Register 6 (SIM_SCGC6) 32 R/W 4000_0001h 12.2.11/253 4004_8040 System Clock Gating Control Register 7 (SIM_SCGC7) 32 R/W 0000_0002h 12.2.12/256 4004_8044 System Clock Divider Register 1 (SIM_CLKDIV1) 32 R/W See section 12.2.13/256 4004_804C Flash Configuration Register 1 (SIM_FCFG1) 32 R See section 12.2.14/259 4004_8050 Flash Configuration Register 2 (SIM_FCFG2) 32 R See section 12.2.15/261 4004_8054 Unique Identification Register High (SIM_UIDH) 32 R See section 12.2.16/261 4004_8058 Unique Identification Register Mid-High (SIM_UIDMH) 32 R See section 12.2.17/262 4004_805C Unique Identification Register Mid Low (SIM_UIDML) 32 R See section 12.2.18/262 4004_8060 Unique Identification Register Low (SIM_UIDL) 32 R See section 12.2.19/263 KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 234 Freescale Semiconductor, Inc. Chapter 12 System Integration Module (SIM) 12.2.1 System Options Register 1 (SIM_SOPT1) NOTE The SOPT1 register is only reset on POR or LVD. Address: 4004_7000h base + 0h offset = 4004_7000h Bit 31 R 30 29 28 27 26 25 24 22 21 20 0 Reserved W 23 19 18 17 16 OSC32KSEL OSC32KOUT Reset x* x* x* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x* x* RAMSIZE R 0 Reserved W Reset x* x* x* x* 0* 0* 0* 0* 0* 0* x* x* x* x* * Notes: * x = Undefined at reset. SIM_SOPT1 field descriptions Field Description 31-29 Reserved This field is reserved. 28-20 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 19-18 OSC32KSEL 32K oscillator clock select Selects the 32 kHz clock source (ERCLK32K) for LPTMR. This field is reset only on POR/LVD. 00 01 10 11 17-16 OSC32KOUT 32K Oscillator Clock Output Outputs the ERCLK32K on the selected pin in all modes of operation (including LLS/VLLS and System Reset), overriding the existing pin mux configuration for that pin. This field is reset only on POR/LVD. 00 01 10 11 15-12 RAMSIZE System oscillator (OSC32KCLK) Reserved Reserved LPO 1 kHz ERCLK32K is not output. ERCLK32K is output on PTE0. ERCLK32K is output on PTE26. Reserved. RAM size This field specifies the amount of system RAM available on the device. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 235 Memory map and register definition SIM_SOPT1 field descriptions (continued) Field Description 0001 0011 0100 0101 0110 0111 1000 1001 1011 8 KB 16 KB 24 KB 32 KB 48 KB 64 KB 96 KB 128 KB 256 KB 11-6 Reserved This field is reserved. This read-only field is reserved and always has the value 0. Reserved This field is reserved. 12.2.2 SOPT1 Configuration Register (SIM_SOPT1CFG) NOTE The SOPT1CFG register is reset on System Reset not VLLS. Address: 4004_7000h base + 4h offset = 4004_7004h Bit 31 30 29 28 27 26 0 R 25 24 23 22 21 20 19 18 17 0 16 15 14 13 12 11 10 9 0 8 7 6 5 4 0 3 2 1 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIM_SOPT1CFG field descriptions Field Description 31-27 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 26-24 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 23-10 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 9-8 Reserved This field is reserved. This read-only field is reserved and always has the value 0. Reserved This field is reserved. This read-only field is reserved and always has the value 0. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 236 Freescale Semiconductor, Inc. Chapter 12 System Integration Module (SIM) 12.2.3 System Options Register 2 (SIM_SOPT2) SOPT2 contains the controls for selecting many of the module clock source options on this device. See the Clock Distribution chapter for more information including clocking diagrams and definitions of device clocks. Address: 4004_7000h base + 1004h offset = 4004_8004h 31 30 29 0 R 28 27 26 25 LPUARTSRC Bit 0 W 24 23 0 22 21 0 20 19 0 18 17 16 0 PLLFLLSEL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 TRACECLKSE L Reset 0 R W Reset 0 0 0 1 0 FBSL 0 0 0 0 CLKOUTSEL 0 0 0 0 0 0 0 SIM_SOPT2 field descriptions Field Description 31-30 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 29-28 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 27-26 LPUARTSRC LPUART clock source select Selects the clock source for the LPUART transmit and receive clock. 00 01 10 11 Clock disabled MCGFLLCLK , or MCGPLLCLK, or IRC48M clock as selected by SOPT2[PLLFLLSEL]. OSCERCLK clock MCGIRCLK clock 25-24 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 23-22 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 21-19 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 18 Reserved This field is reserved. This read-only field is reserved and always has the value 0. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 237 Memory map and register definition SIM_SOPT2 field descriptions (continued) Field 17-16 PLLFLLSEL Description PLL/FLL clock select Selects the high frequency clock for various peripheral clocking options. 00 01 10 11 15-13 Reserved MCGFLLCLK clock MCGPLLCLK clock Reserved IRC48 MHz clock This field is reserved. This read-only field is reserved and always has the value 0. 12 Debug trace clock select TRACECLKSEL Selects the core/system clock, or MCG output clock (MCGOUTCLK) as the trace clock source. 0 1 MCGOUTCLK Core/system clock 11 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 10 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 9-8 FBSL FlexBus security level If flash security is enabled, then this field affects what CPU operations can access off-chip via the FlexBus interface. This field has no effect if flash security is not enabled. 00 01 10 11 7-5 CLKOUTSEL All off-chip accesses (instruction and data) via the FlexBus are disallowed. All off-chip accesses (instruction and data) via the FlexBus are disallowed. Off-chip instruction accesses are disallowed. Data accesses are allowed. Off-chip instruction accesses and data accesses are allowed. CLKOUT select Selects the clock to output on the CLKOUT pin. 000 001 010 011 100 101 110 111 FlexBus CLKOUT Reserved Flash clock LPO clock (1 kHz) MCGIRCLK Reserved OSCERCLK0 IRC 48 MHz clock 4 Reserved This field is reserved. This read-only field is reserved and always has the value 0. Reserved This field is reserved. This read-only field is reserved and always has the value 0. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 238 Freescale Semiconductor, Inc. Chapter 12 System Integration Module (SIM) 12.2.4 System Options Register 4 (SIM_SOPT4) Address: 4004_7000h base + 100Ch offset = 4004_800Ch 21 20 19 18 17 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 FTM0FLT1 FTM0FLT0 16 FTM1FLT0 FTM1CH0SRC 22 FTM2CH0SRC 23 FTM2CH1SRC 24 FTM0CLKSEL 25 FTM1CLKSEL 26 FTM2CLKSEL 27 FTM3CLKSEL 28 FTM0TRG0SR C 29 FTM0TRG1SR C 30 FTM3TRG0SR C 31 FTM3TRG1SR C Bit 0 0 0 0 0 0 R W Reset 0 0 0 0 0 0 0 0 0 FTM2FLT0 W FTM3FLT0 R 0 0 0 0 0 0 SIM_SOPT4 field descriptions Field Description 31 FlexTimer 3 Hardware Trigger 1 Source Select FTM3TRG1SRC Selects the source of FTM3 hardware trigger 1. 0 1 Reserved FTM2 channel match drives FTM3 hardware trigger 1 30 FlexTimer 3 Hardware Trigger 0 Source Select FTM3TRG0SRC Selects the source of FTM3 hardware trigger 0. 0 1 Reserved FTM1 channel match drives FTM3 hardware trigger 0 29 FlexTimer 0 Hardware Trigger 1 Source Select FTM0TRG1SRC Selects the source of FTM0 hardware trigger 1. 0 1 PDB output trigger 1 drives FTM0 hardware trigger 1 FTM2 channel match drives FTM0 hardware trigger 1 28 FlexTimer 0 Hardware Trigger 0 Source Select FTM0TRG0SRC Selects the source of FTM0 hardware trigger 0. 0 1 27 FTM3CLKSEL HSCMP0 output drives FTM0 hardware trigger 0 FTM1 channel match drives FTM0 hardware trigger 0 FlexTimer 3 External Clock Pin Select Selects the external pin used to drive the clock to the FTM3 module. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 239 Memory map and register definition SIM_SOPT4 field descriptions (continued) Field Description NOTE: The selected pin must also be configured for the FTM3 module external clock function through the appropriate pin control register in the port control module. 0 1 26 FTM2CLKSEL FTM3 external clock driven by FTM_CLK0 pin. FTM3 external clock driven by FTM_CLK1 pin. FlexTimer 2 External Clock Pin Select Selects the external pin used to drive the clock to the FTM2 module. NOTE: The selected pin must also be configured for the FTM2 module external clock function through the appropriate pin control register in the port control module. 0 1 25 FTM1CLKSEL FTM2 external clock driven by FTM_CLK0 pin. FTM2 external clock driven by FTM_CLK1 pin. FTM1 External Clock Pin Select Selects the external pin used to drive the clock to the FTM1 module. NOTE: The selected pin must also be configured for the FTM external clock function through the appropriate pin control register in the port control module. 0 1 24 FTM0CLKSEL FTM_CLK0 pin FTM_CLK1 pin FlexTimer 0 External Clock Pin Select Selects the external pin used to drive the clock to the FTM0 module. NOTE: The selected pin must also be configured for the FTM external clock function through the appropriate pin control register in the port control module. 0 1 23 Reserved FTM_CLK0 pin FTM_CLK1 pin This field is reserved. This read-only field is reserved and always has the value 0. 22 FTM2CH1SRC FTM2 channel 1 input capture source select 21-20 FTM2CH0SRC FTM2 channel 0 input capture source select 0 1 FTM2_CH1 signal Exclusive OR of FTM2_CH1, FTM2_CH0 and FTM1_CH1. Selects the source for FTM2 channel 0 input capture. NOTE: When the FTM is not in input capture mode, clear this field. 00 01 10 11 19-18 FTM1CH0SRC FTM2_CH0 signal CMP0 output CMP1 output Reserved FTM1 channel 0 input capture source select Selects the source for FTM1 channel 0 input capture. NOTE: When the FTM is not in input capture mode, clear this field. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 240 Freescale Semiconductor, Inc. Chapter 12 System Integration Module (SIM) SIM_SOPT4 field descriptions (continued) Field Description 00 01 10 11 17-13 Reserved 12 FTM3FLT0 FTM1_CH0 signal CMP0 output CMP1 output Reserved This field is reserved. This read-only field is reserved and always has the value 0. FTM3 Fault 0 Select Selects the source of FTM3 fault 0. NOTE: The pin source for fault 0 must be configured for the FTM module fault function through the appropriate PORTx pin control register. 0 1 11-9 Reserved 8 FTM2FLT0 FTM3_FLT0 pin CMP0 out This field is reserved. This read-only field is reserved and always has the value 0. FTM2 Fault 0 Select Selects the source of FTM2 fault 0. NOTE: The pin source for fault 0 must be configured for the FTM module fault function through the appropriate PORTx pin control register. 0 1 7-5 Reserved 4 FTM1FLT0 FTM2_FLT0 pin CMP0 out This field is reserved. This read-only field is reserved and always has the value 0. FTM1 Fault 0 Select Selects the source of FTM1 fault 0. NOTE: The pin source for fault 0 must be configured for the FTM module fault function through the appropriate pin control register in the port control module. 0 1 FTM1_FLT0 pin CMP0 out 3 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 2 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 1 FTM0FLT1 FTM0 Fault 1 Select Selects the source of FTM0 fault 1. NOTE: The pin source for fault 1 must be configured for the FTM module fault function through the appropriate pin control register in the port control module. 0 1 0 FTM0FLT0 FTM0_FLT1 pin CMP1 out FTM0 Fault 0 Select Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 241 Memory map and register definition SIM_SOPT4 field descriptions (continued) Field Description Selects the source of FTM0 fault 0. NOTE: The pin source for fault 0 must be configured for the FTM module fault function through the appropriate pin control register in the port control module. 0 1 FTM0_FLT0 pin CMP0 out 12.2.5 System Options Register 5 (SIM_SOPT5) Address: 4004_7000h base + 1010h offset = 4004_8010h 27 26 25 24 23 22 21 20 0 R W Reset 0 0 0 0 0 0 19 18 17 0 0 0 0 0 0 0 0 16 15 14 13 12 0 0 11 10 9 8 7 0 0 0 0 0 0 0 0 0 0 0 6 5 0 0 4 3 0 0 2 1 0 0 0 UART0TXSRC 28 UART0RXSRC 29 UART1TXSRC 30 UART1RXSRC 31 LPUART0RXS RC Bit 0 SIM_SOPT5 field descriptions Field 31-20 Reserved Description This field is reserved. This read-only field is reserved and always has the value 0. 19-18 LPUART0 receive data source select LPUART0RXSRC Selects the source for the LPUART0 receive data. 00 01 10 11 LPUART0_RX pin CMP0 output CMP1 output Reserved 17-16 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 15-8 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 7-6 UART1RXSRC UART 1 receive data source select Selects the source for the UART 1 receive data. 00 01 10 11 5-4 UART1TXSRC UART1_RX pin CMP0 CMP1 Reserved UART 1 transmit data source select Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 242 Freescale Semiconductor, Inc. Chapter 12 System Integration Module (SIM) SIM_SOPT5 field descriptions (continued) Field Description Selects the source for the UART 1 transmit data. 00 01 10 11 3-2 UART0RXSRC UART1_TX pin UART1_TX pin modulated with FTM1 channel 0 output UART1_TX pin modulated with FTM2 channel 0 output Reserved UART 0 receive data source select Selects the source for the UART 0 receive data. 00 01 10 11 UART0TXSRC UART0_RX pin CMP0 CMP1 Reserved UART 0 transmit data source select Selects the source for the UART 0 transmit data. 00 01 10 11 UART0_TX pin UART0_TX pin modulated with FTM1 channel 0 output UART0_TX pin modulated with FTM2 channel 0 output Reserved 12.2.6 System Options Register 7 (SIM_SOPT7) Address: 4004_7000h base + 1018h offset = 4004_8018h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 R W 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 ADC1TRGSEL 0 0 0 0 0 ADC0PRETRGS EL 0 ADC0ALTTRGE N 0 ADC1PRETRGS EL 0 ADC1ALTTRGE N Reset 0 0 0 0 ADC0TRGSEL 0 0 0 0 KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 243 Memory map and register definition SIM_SOPT7 field descriptions Field 31-16 Reserved Description This field is reserved. This read-only field is reserved and always has the value 0. 15 ADC1 alternate trigger enable ADC1ALTTRGEN Enable alternative conversion triggers for ADC1. 0 1 14-13 Reserved PDB trigger selected for ADC1 Alternate trigger selected for ADC1 as defined by ADC1TRGSEL. This field is reserved. This read-only field is reserved and always has the value 0. 12 ADC1 pre-trigger select ADC1PRETRGSEL Selects the ADC1 pre-trigger source when alternative triggers are enabled through ADC1ALTTRGEN. 0 1 11-8 ADC1TRGSEL Pre-trigger A selected for ADC1. Pre-trigger B selected for ADC1. ADC1 trigger select Selects the ADC1 trigger source when alternative triggers are functional in stop and VLPS modes. 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 PDB external trigger pin input (PDB0_EXTRG) High speed comparator 0 output High speed comparator 1 output Reserved PIT trigger 0 PIT trigger 1 PIT trigger 2 PIT trigger 3 FTM0 trigger FTM1 trigger FTM2 trigger FTM3 trigger Reserved Reserved Low-power timer (LPTMR) trigger Reserved 7 ADC0 alternate trigger enable ADC0ALTTRGEN Enable alternative conversion triggers for ADC0. 0 1 6-5 Reserved PDB trigger selected for ADC0. Alternate trigger selected for ADC0. This field is reserved. This read-only field is reserved and always has the value 0. 4 ADC0 pretrigger select ADC0PRETRGSEL Selects the ADC0 pre-trigger source when alternative triggers are enabled through ADC0ALTTRGEN. 0 1 Pre-trigger A Pre-trigger B Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 244 Freescale Semiconductor, Inc. Chapter 12 System Integration Module (SIM) SIM_SOPT7 field descriptions (continued) Field Description ADC0TRGSEL ADC0 trigger select Selects the ADC0 trigger source when alternative triggers are functional in stop and VLPS modes. . 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 PDB external trigger pin input (PDB0_EXTRG) High speed comparator 0 output High speed comparator 1 output Reserved PIT trigger 0 PIT trigger 1 PIT trigger 2 PIT trigger 3 FTM0 trigger FTM1 trigger FTM2 trigger FTM3 trigger Reserved Reserved Low-power timer (LPTMR) trigger Reserved 12.2.7 System Options Register 8 (SIM_SOPT8) Address: 4004_7000h base + 101Ch offset = 4004_801Ch FTM0OCH1SR C FTM0OCH0SR C Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FTM1SYNCBIT FTM0SYNCBIT 16 FTM0OCH2SR C 17 FTM2SYNCBIT 18 FTM0OCH3SR C 19 FTM3SYNCBIT 20 FTM0OCH4SR C 21 FTM0OCH5SR C 22 FTM0OCH6SR C 23 FTM0OCH7SR C 24 FTM3OCH0SR C 25 FTM3OCH1SR C 26 FTM3OCH2SR C 27 FTM3OCH3SR C 28 FTM3OCH4SR C 29 FTM3OCH5SR C 30 FTM3OCH6SR C 31 FTM3OCH7SR C Bit 0 0 0 0 0 0 0 0 0 0 R W 0 R W Reset 0 0 0 0 0 0 SIM_SOPT8 field descriptions Field Description 31 FTM3 channel 7 output source FTM3OCH7SRC Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 245 Memory map and register definition SIM_SOPT8 field descriptions (continued) Field Description 0 1 FTM3_CH7 pin is output of FTM3 channel 7 output FTM3_CH7 pin is output of FTM3 channel 7 output modulated by FTM2 channel 1 output. 30 FTM3 channel 6 output source FTM3OCH6SRC 0 FTM3_CH6 pin is output of FTM3 channel 6 output 1 FTM3_CH6 pin is output of FTM3 channel 6 output modulated by FTM2 channel 1 output. 29 FTM3 channel 5 output source FTM3OCH5SRC 0 FTM3_CH5 pin is output of FTM3 channel 5 output 1 FTM3_CH5 pin is output of FTM3 channel 5 output modulated by FTM2 channel 1 output. 28 FTM3 channel 4 output source FTM3OCH4SRC 0 FTM3_CH4 pin is output of FTM3 channel 4 output 1 FTM3_CH4 pin is output of FTM3 channel 4 output modulated by FTM2 channel 1 output. 27 FTM3 channel 3 output source FTM3OCH3SRC 0 FTM3_CH3 pin is output of FTM3 channel 3 output 1 FTM3_CH3 pin is output of FTM3 channel 3 output modulated by FTM2 channel 1 output. 26 FTM3 channel 2 output source FTM3OCH2SRC 0 FTM3_CH2 pin is output of FTM3 channel 2 output 1 FTM3_CH2 pin is output of FTM3 channel 2 output modulated by FTM2 channel 1 output. 25 FTM3 channel 1 output source FTM3OCH1SRC 0 FTM3_CH1 pin is output of FTM3 channel 1 output 1 FTM3_CH1 pin is output of FTM3 channel 1 output modulated by FTM2 channel 1 output. 24 FTM3 channel 0 output source FTM3OCH0SRC 0 FTM3_CH0 pin is output of FTM3 channel 0 output 1 FTM3_CH0 pin is output of FTM3 channel 0 output modulated by FTM2 channel 1 output. 23 FTM0 channel 7 output source FTM0OCH7SRC 0 FTM0_CH7 pin is output of FTM0 channel 7 output 1 FTM0_CH7 pin is output of FTM0 channel 7 output, modulated by FTM1 channel 1 output 22 FTM0 channel 6 output source FTM0OCH6SRC 0 FTM0_CH6 pin is output of FTM0 channel 6 output 1 FTM0_CH6 pin is output of FTM0 channel 6 output, modulated by FTM1 channel 1 output 21 FTM0 channel 5 output source FTM0OCH5SRC 0 FTM0_CH5 pin is output of FTM0 channel 5 output 1 FTM0_CH5 pin is output of FTM0 channel 5 output, modulated by FTM1 channel 1 output 20 FTM0 channel 4 output source FTM0OCH4SRC 0 FTM0_CH4 pin is output of FTM0 channel 4 output 1 FTM0_CH4 pin is output of FTM0 channel 4 output, modulated by FTM1 channel 1 output 19 FTM0 channel 3 output source FTM0OCH3SRC Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 246 Freescale Semiconductor, Inc. Chapter 12 System Integration Module (SIM) SIM_SOPT8 field descriptions (continued) Field Description 0 1 FTM0_CH3 pin is output of FTM0 channel 3 output FTM0_CH3 pin is output of FTM0 channel 3 output, modulated by FTM1 channel 1 output 18 FTM0 channel 2 output source FTM0OCH2SRC 0 FTM0_CH2 pin is output of FTM0 channel 2 output 1 FTM0_CH2 pin is output of FTM0 channel 2 output, modulated by FTM1 channel 1 output 17 FTM0 channel 1 output source FTM0OCH1SRC 0 FTM0_CH1 pin is output of FTM0 channel 1 output 1 FTM0_CH1 pin is output of FTM0 channel 1 output, modulated by FTM1 channel 1 output 16 FTM0 channel 0 output source FTM0OCH0SRC 0 FTM0_CH0 pin is output of FTM0 channel 0 output 1 FTM0_CH0 pin is output of FTM0 channel 0 output, modulated by FTM1 channel 1 output 15-4 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 3 FTM3SYNCBIT FTM3 Hardware Trigger 0 Software Synchronization 2 FTM2SYNCBIT FTM2 Hardware Trigger 0 Software Synchronization 1 FTM1SYNCBIT FTM1 Hardware Trigger 0 Software Synchronization 0 FTM0SYNCBIT FTM0 Hardware Trigger 0 Software Synchronization 0 1 0 1 0 1 0 1 No effect. Write 1 to assert the TRIG0 input to FTM3, software must clear this bit to allow other trigger sources to assert. No effect. Write 1 to assert the TRIG0 input to FTM2, software must clear this bit to allow other trigger sources to assert. No effect. Write 1 to assert the TRIG0 input to FTM1, software must clear this bit to allow other trigger sources to assert. No effect Write 1 to assert the TRIG0 input to FTM0, software must clear this bit to allow other trigger sources to assert. 12.2.8 System Device Identification Register (SIM_SDID) Address: 4004_7000h base + 1024h offset = 4004_8024h Bit R 31 30 29 28 FAMILYID 27 26 25 24 SUBFAMID 23 22 21 20 19 18 SERIESID 17 0 16 15 14 13 12 11 10 REVID 9 8 7 DIEID 6 5 4 Reserved 3 2 1 0 PINID W Reset x* x* x* x* x* x* x* x* x* x* x* x* 0 0 0 0 x* x* x* x* 1 1 1 0 1 1 1 1 x* x* x* x* * Notes: * x = Undefined at reset. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 247 Memory map and register definition SIM_SDID field descriptions Field 31-28 FAMILYID Description Kinetis Family ID Specifies the Kinetis family of the device. 0001 0010 0011 0100 0110 0111 27-24 SUBFAMID Kinetis Sub-Family ID Specifies the Kinetis sub-family of the device. 0000 0001 0010 0011 0100 0101 0110 23-20 SERIESID KVx0 Subfamily KVx1 Subfamily KVx2 Subfamily KVx3 Subfamily KVx4 Subfamily KVx5 Subfamily KVx6 Subfamily Kinetis Series ID Specifies the Kinetis series of the device. 0000 0001 0101 0110 19-16 Reserved KV1x Family KV2x Family KV3x Family KV4x Family KV6x Family KV7x Family Kinetis K series Kinetis L series Kinetis W series Kinetis V series This field is reserved. This read-only field is reserved and always has the value 0. 15-12 REVID Device revision number 11-7 DIEID Device die number Specifies the silicon implementation number for the device. Specifies the silicon implementation number for the device. 6-4 Reserved This field is reserved. PINID Pincount identification Specifies the pincount of the device. 0000 0001 0010 0011 0100 0101 0110 Reserved Reserved 32-pin Reserved 48-pin 64-pin 80-pin Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 248 Freescale Semiconductor, Inc. Chapter 12 System Integration Module (SIM) SIM_SDID field descriptions (continued) Field Description 0111 1000 1001 1010 1011 1100 1101 1110 1111 81-pin or 121-pin 100-pin 121-pin 144-pin Custom pinout (WLCSP) 169-pin Reserved 256-pin Reserved 12.2.9 System Clock Gating Control Register 4 (SIM_SCGC4) Address: 4004_7000h base + 1034h offset = 4004_8034h Bit 31 30 29 28 27 26 25 24 1 R 23 22 21 20 19 0 18 17 0 16 0 VREF CMP W 1 1 0 0 0 0 0 0 0 1 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 R 0 W Reset 0 0 0 UART0 1 UART1 1 UART2 Reset 0 0 0 0 0 1 0 I2C1 I2C0 0 0 0 EWM 1 1 0 0 0 0 SIM_SCGC4 field descriptions Field Description 31-28 Reserved This field is reserved. This read-only field is reserved and always has the value 1. 27-21 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 20 VREF VREF Clock Gate Control This bit controls the clock gate to the VREF module. 0 1 19 CMP Clock disabled Clock enabled Comparator Clock Gate Control This bit controls the clock gate to the comparator module. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 249 Memory map and register definition SIM_SCGC4 field descriptions (continued) Field Description 0 1 Clock disabled Clock enabled 18 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 17-14 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 13 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 12 UART2 UART2 Clock Gate Control This bit controls the clock gate to the UART2 module. 0 1 11 UART1 UART1 Clock Gate Control This bit controls the clock gate to the UART1 module. 0 1 10 UART0 7 I2C1 This bit controls the clock gate to the UART0 module. Clock disabled Clock enabled This field is reserved. This read-only field is reserved and always has the value 0. I2C1 Clock Gate Control This bit controls the clock gate to the I 2 C1 module. 0 1 6 I2C0 Clock disabled Clock enabled UART0 Clock Gate Control 0 1 9-8 Reserved Clock disabled Clock enabled Clock disabled Clock enabled I2C0 Clock Gate Control This bit controls the clock gate to the I 2 C0 module. 0 1 Clock disabled Clock enabled 5-4 Reserved This field is reserved. This read-only field is reserved and always has the value 1. 3 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 2 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 1 EWM EWM Clock Gate Control This bit controls the clock gate to the EWM module. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 250 Freescale Semiconductor, Inc. Chapter 12 System Integration Module (SIM) SIM_SCGC4 field descriptions (continued) Field Description 0 1 0 Reserved Clock disabled Clock enabled This field is reserved. This read-only field is reserved and always has the value 0. 12.2.10 System Clock Gating Control Register 5 (SIM_SCGC5) Address: 4004_7000h base + 1038h offset = 4004_8038h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 0 R 17 1 16 0 W 0 0 0 0 0 0 0 0 1 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 R W Reset 0 0 0 0 0 0 0 1 1 1 0 0 1 0 1 LPTMR 0 PORTA 0 PORTB 0 PORTC 0 PORTD 0 PORTE Reset 0 SIM_SCGC5 field descriptions Field Description 31-19 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 18 Reserved This field is reserved. This read-only field is reserved and always has the value 1. 17-14 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 13 PORTE Port E Clock Gate Control This bit controls the clock gate to the Port E module. 0 1 12 PORTD Port D Clock Gate Control This bit controls the clock gate to the Port D module. 0 1 11 PORTC Clock disabled Clock enabled Clock disabled Clock enabled Port C Clock Gate Control Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 251 Memory map and register definition SIM_SCGC5 field descriptions (continued) Field Description This bit controls the clock gate to the Port C module. 0 1 10 PORTB Port B Clock Gate Control This bit controls the clock gate to the Port B module. 0 1 9 PORTA Clock disabled Clock enabled Clock disabled Clock enabled Port A Clock Gate Control This bit controls the clock gate to the Port A module. 0 1 Clock disabled Clock enabled 8-7 Reserved This field is reserved. This read-only field is reserved and always has the value 1. 6 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 5 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 4 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 3-2 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 1 Reserved This field is reserved. This read-only field is reserved and always has the value 1. 0 LPTMR Low Power Timer Access Control This bit controls software access to the Low Power Timer module. 0 1 Access disabled Access enabled KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 252 Freescale Semiconductor, Inc. Chapter 12 System Integration Module (SIM) 12.2.11 System Clock Gating Control Register 6 (SIM_SCGC6) Address: 4004_7000h base + 103Ch offset = 4004_803Ch Bit 31 24 23 22 PDB 21 20 0 19 18 17 0 16 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 FTF 0 1 0 SPI1 SPI0 0 0 W Reset 0 0 0 FTM3 0 ADC1 0 DAC1 1 RNGA 0 LPUART0 Reset DMAMUX 0 25 FTM0 0 26 FTM1 1 27 FTM2 28 ADC0 29 PIT W DAC0 R 30 0 0 0 0 0 CRC 0 0 0 0 0 SIM_SCGC6 field descriptions Field 31 DAC0 Description DAC0 Clock Gate Control This bit controls the clock gate to the DAC0 module. 0 1 Clock disabled Clock enabled 30 Reserved This field is reserved. This read-only field is reserved and always has the value 1. 29 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 28 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 27 ADC0 ADC0 Clock Gate Control This bit controls the clock gate to the ADC0 module. 0 1 26 FTM2 FTM2 Clock Gate Control This bit controls the clock gate to the FTM2 module. 0 1 25 FTM1 Clock disabled Clock enabled Clock disabled Clock enabled FTM1 Clock Gate Control This bit controls the clock gate to the FTM1 module. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 253 Memory map and register definition SIM_SCGC6 field descriptions (continued) Field Description 0 1 24 FTM0 FTM0 Clock Gate Control This bit controls the clock gate to the FTM0 module. 0 1 23 PIT Clock disabled Clock enabled PIT Clock Gate Control This bit controls the clock gate to the PIT module. 0 1 22 PDB Clock disabled Clock enabled Clock disabled Clock enabled PDB Clock Gate Control This bit controls the clock gate to the PDB module. 0 1 Clock disabled Clock enabled 21 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 20-19 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 18 CRC CRC Clock Gate Control This bit controls the clock gate to the CRC module. 0 1 Clock disabled Clock enabled 17-16 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 15 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 14 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 13 SPI1 SPI1 Clock Gate Control This bit controls the clock gate to the SPI1 module. 0 1 12 SPI0 SPI0 Clock Gate Control This bit controls the clock gate to the SPI0 module. 0 1 11 Reserved Clock disabled Clock enabled Clock disabled Clock enabled This field is reserved. This read-only field is reserved and always has the value 0. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 254 Freescale Semiconductor, Inc. Chapter 12 System Integration Module (SIM) SIM_SCGC6 field descriptions (continued) Field 10 LPUART0 Description LPUART0 Clock Gate Control This bit controls the clock gate to the LPUART0 module. 0 1 Clock disabled Clock enabled 9 RNGA RNGA Clock Gate Control 8 DAC1 DAC1 Clock Gate Control This bit controls the clock gate to the RNGA module. This bit controls the clock gate to the DAC1 module. 0 1 7 ADC1 ADC1 Clock Gate Control This bit controls the clock gate to the ADC1 module. 0 1 6 FTM3 Clock disabled Clock enabled Clock disabled Clock enabled FTM3 Clock Gate Control This bit controls the clock gate to the FTM3 module. 0 1 Clock disabled Clock enabled 5 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 4 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 3-2 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 1 DMAMUX DMA Mux Clock Gate Control This bit controls the clock gate to the DMA Mux module. 0 1 0 FTF Clock disabled Clock enabled Flash Memory Clock Gate Control This bit controls the clock gate to the flash memory. Flash reads are still supported while the flash memory is clock gated, but entry into low power modes and HSRUN mode is blocked. 0 1 Clock disabled Clock enabled KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 255 Memory map and register definition 12.2.12 System Clock Gating Control Register 7 (SIM_SCGC7) Address: 4004_7000h base + 1040h offset = 4004_8040h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 DMA FLEXBUS W 1 0 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIM_SCGC7 field descriptions Field Description 31-4 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 3 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 2 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 1 DMA DMA Clock Gate Control This bit controls the clock gate to the DMA module. 0 1 0 FLEXBUS Clock disabled Clock enabled FlexBus Clock Gate Control This bit controls the clock gate to the FlexBus module. 0 1 Clock disabled Clock enabled 12.2.13 System Clock Divider Register 1 (SIM_CLKDIV1) When updating CLKDIV1, update all fields using the one write command. Attempting to write an invalid clock ratio to the CLKDIV1 register will cause the write to be ignored. The maximum divide ratio that can be programmed between core/system clock and the other divided clocks is divide by 8. When OUTDIV1 equals 0000 (divide by 1), the other dividers cannot be set higher than 0111 (divide by 8). KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 256 Freescale Semiconductor, Inc. Chapter 12 System Integration Module (SIM) NOTE The CLKDIV1 register cannot be written to when the device is in VLPR mode. Address: 4004_7000h base + 1044h offset = 4004_8044h Bit R W Reset 31 30 29 28 OUTDIV1 27 26 25 24 OUTDIV2 23 22 21 20 OUTDIV3 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 OUTDIV4 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 1* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* SIM_CLKDIV1 field descriptions Field 31-28 OUTDIV1 Description Clock 1 output divider value This field sets the divide value for the core/system clock from MCGOUTCLK. At the end of reset, it is loaded with either 0000 or 0111 depending on FTF_FOPT[LPBOOT]. 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 27-24 OUTDIV2 Divide-by-1. Divide-by-2. Divide-by-3. Divide-by-4. Divide-by-5. Divide-by-6. Divide-by-7. Divide-by-8. Divide-by-9. Divide-by-10. Divide-by-11. Divide-by-12. Divide-by-13. Divide-by-14. Divide-by-15. Divide-by-16. Clock 2 output divider value This field sets the divide value for the bus clock from MCGOUTCLK. At the end of reset, it is loaded with either 0000 or 0111 depending on FTF_FOPT[LPBOOT]. The bus clock frequency must be an integer divide of the core/system clock frequency. 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 Divide-by-1. Divide-by-2. Divide-by-3. Divide-by-4. Divide-by-5. Divide-by-6. Divide-by-7. Divide-by-8. Divide-by-9. Divide-by-10. Divide-by-11. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 257 Memory map and register definition SIM_CLKDIV1 field descriptions (continued) Field Description 1011 1100 1101 1110 1111 23-20 OUTDIV3 Clock 3 output divider value This field sets the divide value for the FlexBus clock (external pin FB_CLK) from MCGOUTCLK. At the end of reset, it is loaded with either 0001 or 1111 depending on FTF_FOPT[LPBOOT]. The FlexBus clock frequency must be an integer divide of the system clock frequency. 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 19-16 OUTDIV4 Divide-by-12. Divide-by-13. Divide-by-14. Divide-by-15. Divide-by-16. Divide-by-1. Divide-by-2. Divide-by-3. Divide-by-4. Divide-by-5. Divide-by-6. Divide-by-7. Divide-by-8. Divide-by-9. Divide-by-10. Divide-by-11. Divide-by-12. Divide-by-13. Divide-by-14. Divide-by-15. Divide-by-16. Clock 4 output divider value This field sets the divide value for the flash clock from MCGOUTCLK. At the end of reset, it is loaded with either 0001 or 1111 depending on FTF_FOPT[LPBOOT]. The flash clock frequency must be an integer divide of the system clock frequency. 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 Divide-by-1. Divide-by-2. Divide-by-3. Divide-by-4. Divide-by-5. Divide-by-6. Divide-by-7. Divide-by-8. Divide-by-9. Divide-by-10. Divide-by-11. Divide-by-12. Divide-by-13. Divide-by-14. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 258 Freescale Semiconductor, Inc. Chapter 12 System Integration Module (SIM) SIM_CLKDIV1 field descriptions (continued) Field Description 1110 1111 Reserved Divide-by-15. Divide-by-16. This field is reserved. This read-only field is reserved and always has the value 0. 12.2.14 Flash Configuration Register 1 (SIM_FCFG1) Address: 4004_7000h base + 104Ch offset = 4004_804Ch Bit 31 30 29 28 27 26 0 R 25 24 23 22 PFSIZE 21 20 19 18 0 17 16 1 Reset 0* 0* 0* 0* 1* 1* 1* 1* 0* 0* 0* 0* 1* 1* 1* 1* Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FLASHDOZE FLASHDIS W 0* 0* 0* 0* 0* 0 R 1 0 W Reset 0* 0* 0* 0* 1* 1* 1* 1* 0* 0* 0* SIM_FCFG1 field descriptions Field 31-28 Reserved 27-24 PFSIZE Description This field is reserved. This read-only field is reserved and always has the value 0. Program flash size This field specifies the amount of program flash memory available on the device . Undefined values are reserved. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 259 Memory map and register definition SIM_FCFG1 field descriptions (continued) Field Description 0011 0101 0111 1001 1011 1101 1111 32 KB of program flash memory 64 KB of program flash memory 128 KB of program flash memory 256 KB of program flash memory 512 KB of program flash memory 1024 KB of program flash memory 512 KB of program flash memory 23-20 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 19-16 Reserved This field is reserved. This read-only field is reserved and always has the value 1. 15-12 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 11-8 Reserved This field is reserved. This read-only field is reserved and always has the value 1. 7-2 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 1 FLASHDOZE Flash Doze When set, Flash memory is disabled for the duration of Wait mode. An attempt by the DMA or other bus master to access the Flash when the Flash is disabled will result in a bus error. This bit should be clear during VLP modes. The Flash will be automatically enabled again at the end of Wait mode so interrupt vectors do not need to be relocated out of Flash memory. The wakeup time from Wait mode is extended when this bit is set. 0 1 0 FLASHDIS Flash remains enabled during Wait mode Flash is disabled for the duration of Wait mode Flash Disable Flash accesses are disabled (and generate a bus error) and the Flash memory is placed in a low power state. This bit should not be changed during VLP modes. Relocate the interrupt vectors out of Flash memory before disabling the Flash. 0 1 Flash is enabled Flash is disabled KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 260 Freescale Semiconductor, Inc. Chapter 12 System Integration Module (SIM) 12.2.15 Flash Configuration Register 2 (SIM_FCFG2) Address: 4004_7000h base + 1050h offset = 4004_8050h Bit 31 R 0 30 29 28 27 26 25 24 23 MAXADDR0 22 21 20 1 19 18 17 16 MAXADDR1 W Reset 0* 1* 1* 1* 1* 1* 1* 1* 1* 1* 1* 1* 1* 1* 1* 1* Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0* 0* 0* 0* 0* 0* 0* 0* 0 R W Reset 0* 0* 0* 0* 0* 0* 0* 0* SIM_FCFG2 field descriptions Field Description 31 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 30-24 MAXADDR0 Max address block 0 This field concatenated with 13 trailing zeros indicates the first invalid address of each program flash block. For example, if MAXADDR0 = 0x20 the first invalid address of flash block 0 is 0x0004_0000. This would be the MAXADDR0 value for a device with 256 KB program flash in flash block 0. 23 Reserved This field is reserved. This read-only field is reserved and always has the value 1. 22-16 MAXADDR1 Max address block 1 This field equals zero if there is only one program flash block, otherwise it equals the value of the MAXADDR0 field. For example, with MAXADDR0 = MAXADDR1 = 0x20 the first invalid address of flash block 1 is 0x4_0000 + 0x4_0000. This would be the MAXADDR1 value for a device with 512 KB program flash memory across two flash blocks and no FlexNVM. Reserved This field is reserved. This read-only field is reserved and always has the value 0. 12.2.16 Unique Identification Register High (SIM_UIDH) Address: 4004_7000h base + 1054h offset = 4004_8054h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 UID R W Reset 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 261 Memory map and register definition SIM_UIDH field descriptions Field Description UID Unique Identification Unique identification for the device. 12.2.17 Unique Identification Register Mid-High (SIM_UIDMH) Address: 4004_7000h base + 1058h offset = 4004_8058h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 UID R W Reset 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* SIM_UIDMH field descriptions Field Description UID Unique Identification Unique identification for the device. 12.2.18 Unique Identification Register Mid Low (SIM_UIDML) Address: 4004_7000h base + 105Ch offset = 4004_805Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 UID R W Reset 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* SIM_UIDML field descriptions Field UID Description Unique Identification Unique identification for the device. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 262 Freescale Semiconductor, Inc. Chapter 12 System Integration Module (SIM) 12.2.19 Unique Identification Register Low (SIM_UIDL) Address: 4004_7000h base + 1060h offset = 4004_8060h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 UID R W Reset 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* SIM_UIDL field descriptions Field UID Description Unique Identification Unique identification for the device. 12.3 Functional description For more information about the functions of SIM, see the Introduction section. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 263 Functional description KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 264 Freescale Semiconductor, Inc. Chapter 13 Kinetis Flashloader 13.1 Chip-Specific Information This device has various peripherals (UART, I2C, SPI) supported by the Kinetis Flashloader. The next table shows the pads used by the Kinetis Flashloader. Table 13-1. Kinetis Flashloader Peripheral Pinmux Port Signal PTE0 UART1_TX PTE1 UART1_RX PTC10 I2C0_SCL PTC11 I2C0_SDA PTD4 SPI0_PCS PTD5 SPI0_SCK PTD6 SPI0_SOUT PTD7 SPI0_SIN 13.2 Introduction The Kinetis devices that do not have an on-chip ROM are shipped with the preprogrammed Kinetis Flashloader in the on-chip flash memory, for one-time, in-system factory programming. The Kinetis Flashloader's main task is to load a customer firmware image into the flash memory. The image on the flash has 2 programs: flashloader_loader and flashloader. After a device reset, the flashloader_loader program starts its execution first. The flashloader_loader program copies the contents of flashloader image from the flash to the on-chip RAM; the device then switches execution to the flashloader program to execute from RAM. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 265 Introduction For this device, the Kinetis Flashloader can interface with UART, I2C, and SPI peripherals in slave mode and respond to the commands sent by a master (or host) communicating on one of those ports. The host/master can be a firmware-download application running on a PC or an embedded host communicating with the Kinetis Flashloader. Regardless of the host/master (PC or embedded host), the Kinetis Flashloader always uses a command protocol to communicate with that host/master. Commands are provided to write to memory (flash or RAM), erase flash, and get/set flashloader options and property values. The host application can query the set of available commands. This chapter describes Kinetis Flashloader features, functionality, command structure and which peripherals are supported. Features supported by the Kinetis Flashloader : * * * * * * * Supports UART, I2C, and SPI peripheral interfaces Automatic detection of the active peripheral UART peripheral with autobaud Common packet-based protocol for all peripherals Packet error detection and retransmission Protection of RAM used by the flashloader while it is running Provides command to read properties of the device, such as flash and RAM size Table 13-2. Commands supported by the Kinetis Flashloader Command Description When flash security is enabled, then this command is Call Runs user application code and returns control to bootloader Not supported Execute Run user application code that never returns control to Not supported the flashloader FillMemory Fill a range of bytes in flash with a word pattern Not supported FlashEraseAll Erase the entire flash array Not supported FlashEraseRegion Erase a range of sectors in flash Not supported FlashProgramOnce Writes data provided in a command packet to a specified range of bytes in the program once field Not supported FlashReadOnce Returns the contents of the program once field by given index and byte count Not supported FlashReadResource Returns the contents of the IFR field or Flash firmware Not supported ID, by given offset, byte count and option WriteMemory Write data to memory Not supported ReadMemory Read data from memory Not supported GetProperty Get the current value of a property Supported Reset Reset the chip Supported SetProperty Attempt to modify a writable property Supported KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 266 Freescale Semiconductor, Inc. Chapter 13 Kinetis Flashloader 13.3 Functional Description The following sub-sections describe the Kinetis Flashloader functionality. 13.3.1 Memory Maps While executing, the Kinetis Flashloader uses RAM memory. Available 0x1FFF_F000 Flashloader use 0x1FFF_8000 RAM 512R Figure 13-1. Kinetis Flashloader RAM Memory Map NOTE The Kinetis Flashloader requires a minimum memory space of 16 KB of RAM. For Kinetis devices with less than this amount of on-chip RAM, the Kinetis Flashloader is not available. 13.3.2 Start-up Process As the Kinetis Flashloader begins executing, flashloader operations begin: 1. The flashloader's temporary working area in RAM is initialized. 2. All supported peripherals are initialized. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 267 Functional Description 3. The flashloader waits for communication to begin on a peripheral. * There is no timeout for the active peripheral detection process. * If communication is detected, then all inactive peripherals are shut down, and the command phase is entered. Enter flashloader Init hardware Init Flash, Property and Memory interfaces Init UARTn, SPIn, and I2Cn Was a Ping packet received on UARTn? Yes No Was Start byte (0x5A) received on I2Cn? Yes Shutdown unused Peripherals Enter flashloader state machine No Was Start byte (0x5A) received on SPIn? Yes No Figure 13-2. Kinetis Flashloader Start-up Flowchart 13.3.3 Clock Configuration The core runs on the default reset clock (20.9 MHz). The Kinetis Flashloader does not modify any clocks, and after a reset, the core uses the clock configuration of the chip. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 268 Freescale Semiconductor, Inc. Chapter 13 Kinetis Flashloader 13.3.4 Flashloader Protocol This section explains the general protocol for the packet transfers between the host and the Kinetis Flashloader. The description includes the transfer of packets for different transactions, such as commands with no data phase and commands with incoming or outgoing data phase. The next section describes various packet types used in a transaction. Each command sent from the host is replied to with a response command. Commands may include an optional data phase: * If the data phase is incoming (from host to flashloader ), then the data phase is part of the original command. * If the data phase is outgoing (from flashloader to host), then the data phase is part of the response command. NOTE In all protocols (described in the next subsections), the Ack sent in response to a Command or Data packet can arrive at any time before, during, or after the Command/Data packet has processed. 13.3.4.1 Command with no data phase The protocol for a command with no data phase contains: * Command packet (from host) * Generic response command packet (to host) Target Host Command ACK Process command Response ACK Figure 13-3. Command with No Data Phase KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 269 Functional Description 13.3.4.2 Command with incoming data phase The protocol for a command with an incoming data phase contains: * Command packet (from host) * Generic response command packet (to host) * Incoming data packets (from host) * Generic response command packet (to host) Target Host Command ACK Process command Initial Response ACK Data packet Process data ACK Final data packet ACK Process data Final Response ACK Figure 13-4. Command with incoming data phase KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 270 Freescale Semiconductor, Inc. Chapter 13 Kinetis Flashloader * * * * NOTE The host may not send any further packets while it (the host) is waiting for the response to a command. If the Generic Response packet prior to the start of the data phase does not have a status of kStatus_Success, then the data phase is aborted. Data phases may be aborted by the receiving side by sending the final Generic Response early with a status of kStatus_AbortDataPhase. The host may abort the data phase early by sending a zero-length data packet. The final Generic Response packet sent after the data phase includes the status for the entire operation. 13.3.4.3 Command with outgoing data phase The protocol for a command with an outgoing data phase contains: * Command packet (from host) * ReadMemory Response command packet (to host) (kCommandFlag_HasDataPhase set) * Outgoing data packets (to host) * Generic response command packet (to host) KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 271 Functional Description Target Host Command ACK Process command Initial Response ACK Data packet Process data ACK Final data packet Process data ACK Final Response ACK Figure 13-5. Command with outgoing data phase NOTE * For the outgoing data phase sequence above, the data phase is really considered part of the response command. * The host may not send any further packets while it (the host) is waiting for the response to a command. * If the ReadMemory Response command packet prior to the start of the data phase does not contain the kCommandFlag_HasDataPhase flag, then the data phase is aborted. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 272 Freescale Semiconductor, Inc. Chapter 13 Kinetis Flashloader * Data phases may be aborted by the host sending the final Generic Response early with a status of kStatus_AbortDataPhase. The sending side may abort the data phase early by sending a zero-length data packet. * The final Generic Response packet sent after the data phase includes the status for the entire operation. 13.3.5 Flashloader Packet Types The Kinetis Flashloader device works in slave mode. All data communication is initiated by a host, which is either a PC or an embedded host . The Kinetis Flashloader device is the target, which receives a command or data packet. All data communication between host and target is packetized. NOTE The term "target" refers to the "Kinetis Flashloader device." There are 6 types of packets used in the device: * Ping packet * Ping Response packet * Framing packet * Command packet * Data packet * Response packet All fields in the packets are in little-endian byte order. 13.3.5.1 Ping packet The Ping packet is the first packet sent from a host to the target (Kinetis Flashloader), to establish a connection on a selected peripheral. For a UART peripheral, the Ping packet is used to determine the baudrate. A Ping packet must be sent before any other communications. In response to a Ping packet, the target sends a Ping Response packet. Table 13-3. Ping Packet Format Byte # Value Name 0 0x5A start byte 1 0xA6 ping KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 273 Functional Description Target Host Ping Packet 0x5a 0xa6 Target executes UART autobaud if necessary PingResponse Packet: 0x5a 0xa7 0x00 0x02 0x01 0x50 0x00 0x00 0xaa 0xea Figure 13-6. Ping Packet Protocol Sequence 13.3.5.2 Ping Response Packet The target (Kinetis Flashloader) sends a Ping Response packet back to the host after receiving a Ping packet. If communication is over a UART peripheral, the target uses the incoming Ping packet to determine the baud rate before replying with the Ping Response packet. Once the Ping Response packet is received by the host, the connection is established, and the host starts sending commands to the target (Kinetis Flashloader). Table 13-4. Ping Response Packet Format Byte # Value Parameter 0 0x5A start byte 1 0xA7 Ping response code 2 Protocol bugfix 3 Protocol minor 4 Protocol major 5 Protocol name = 'P' (0x50) 6 Options low 7 Options high 8 CRC16 low 9 CRC16 high KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 274 Freescale Semiconductor, Inc. Chapter 13 Kinetis Flashloader 13.3.5.3 Framing Packet The framing packet is used for flow control and error detection, and it (the framing packet) wraps command and data packets as well. Table 13-5. Framing Packet Format Byte # Value 0 0x5A Parameter start byte 1 packetType 2 length_low 3 length_high 4 crc16_low 5 crc16_high 6 . . .n Length is a 16-bit field that specifies the entire command or data packet size in bytes. This is a 16-bit field. The CRC16 value covers entire framing packet, including the start byte and command or data packets, but does not include the CRC bytes. See the CRC16 algorithm after this table. Command or Data packet payload A special framing packet that contains only a start byte and a packet type is used for synchronization between the host and target. Table 13-6. Special Framing Packet Format Byte # Value Parameter 0 0x5A start byte 1 0xAn packetType The Packet Type field specifies the type of the packet from one of the defined types (below): Table 13-7. packetType Field packetType Name Description 0xA1 kFramingPacketType_Ack The previous packet was received successfully; the sending of more packets is allowed. 0xA2 kFramingPacketType_Nak The previous packet was corrupted and must be re-sent. 0xA3 kFramingPacketType_AckAbort Data phase is being aborted. 0xA4 kFramingPacketType_Command The framing packet contains a command packet payload. 0xA5 kFramingPacketType_Data The framing packet contains a data packet payload. 0xA6 kFramingPacketType_Ping Sent to verify the other side is alive. Also used for UART autobaud. 0xA7 kFramingPacketType_PingResponse A response to Ping; contains the framing protocol version number and options. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 275 Functional Description 13.3.5.4 Command packet The command packet carries a 32-bit command header and a list of 32-bit parameters. Table 13-8. Command Packet Format Command Packet Format (32 bytes) Command Header (4 bytes) 28 bytes for Parameters (Max 7 parameters) Tag Flags Rsvd Param Param1 Count (32-bit) byte 0 byte 1 byte 2 byte 3 Param2 (32-bit) Param3 (32-bit) Param4 (32-bit) Param5 (32-bit) Param6 (32-bit) Param7 (32-bit) Table 13-9. Command Header Format Byte # Command Header Field 0 Command or Response tag 1 Flags 2 Reserved. Should be 0x00. 3 ParameterCount The command header is 4 bytes long, with these fields. The header is followed by 32-bit parameters up to the value of the ParameterCount field specified in the header. Because a command packet is 32 bytes long, only 7 parameters can fit into the command packet. Command packets are also used by the target to send responses back to the host. As mentioned earlier, command packets and data packets are embedded into framing packets for all of the transfers. Table 13-10. Commands that are supported Command Name 0x01 FlashEraseAll 0x02 FlashEraseRegion 0x03 ReadMemory 0x04 WriteMemory 0x05 FillMemory 0x06 Reserved 0x07 GetProperty 0x08 Reserved 0x09 Execute 0x0A Call 0x0B Reset Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 276 Freescale Semiconductor, Inc. Chapter 13 Kinetis Flashloader Table 13-10. Commands that are supported (continued) Command Name 0x0C SetProperty 0x0D Reserved 0x0E FlashProgramOnce 0x0F FlashReadOnce 0x10 FlashReadResource 0x11 Reserved Table 13-11. Responses that are supported Response Name 0xA0 GenericResponse 0xA3 ReadMemoryResponse (used for sending responses to ReadMemory command only) 0xA7 GetPropertyResponse (used for sending responses to GetProperty command only) 0xAF FlashReadOnceResponse (used for sending responses to FlashReadOnce command only) 0xB0 FlashReadResourceResponse (used for sending responses to FlashReadResource command only) Flags: Each command packet contains a Flag byte. Only bit 0 of the flag byte is used. If bit 0 of the flag byte is set to 1, then data packets will follow in the command sequence. The number of bytes that will be transferred in the data phase is determined by a command-specific parameter in the parameters array. ParameterCount: The number of parameters included in the command packet. Parameters: The parameters are word-length (32 bits). With the default maximum packet size of 32 bytes, a command packet can contain up to 7 parameters. 13.3.5.5 Data packet The data packet carries just the data, either host sending data to target, or target sending data to host. The data transfer direction is determined by the last command sent from the host. The data packet is also wrapped within a framing packet, to ensure the correct packet data is received. The contents of a data packet are simply the data itself. There are no other fields, so that the most data per packet can be transferred. Framing packets are responsible for ensuring that the correct packet data is received. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 277 Functional Description 13.3.5.6 Response packet The responses are carried using the same command packet format wrapped with framing packet data. Types of responses include: * GenericResponse * GetPropertyResponse * ReadMemoryResponse * FlashReadOnceResponse * FlashReadResourceResponse GenericResponse: After the Kinetis Flashloader has processed a command, the flashloader will send a generic response with status and command tag information to the host. The generic response is the last packet in the command protocol sequence. The generic response packet contains the framing packet data and the command packet data (with generic response tag = 0xA0) and a list of parameters (defined in the next section). The parameter count field in the header is always set to 2, for status code and command tag parameters. Table 13-12. GenericResponse Parameters Byte # Parameter Descripton 0-3 Status code The Status codes are errors encountered during the execution of a command by the target (Kinetis Flashloader). If a command succeeds, then a kStatus_Success code is returned. Table 13-47, Kinetis Flashloader Status Error Codes, lists the status codes returned to the host by the Kinetis Flashloader. 4-7 Command tag The Command tag parameter identifies the response to the command sent by the host. GetPropertyResponse: The GetPropertyResponse packet is sent by the target in response to the host query that uses the GetProperty command. The GetPropertyResponse packet contains the framing packet data and the command packet data, with the command/response tag set to a GetPropertyResponse tag value (0xA7). The parameter count field in the header is set to greater than 1, to always include the status code and one or many property values. Table 13-13. GetPropertyResponse Parameters Byte # Value Parameter 0-3 Status code 4-7 Property value Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 278 Freescale Semiconductor, Inc. Chapter 13 Kinetis Flashloader Table 13-13. GetPropertyResponse Parameters (continued) Byte # Value ... Parameter ... Can be up to maximum 6 property values, limited to the size of the 32-bit command packet and property type. ReadMemoryResponse: The ReadMemoryResponse packet is sent by the target in response to the host sending a ReadMemory command. The ReadMemoryResponse packet contains the framing packet data and the command packet data, with the command/response tag set to a ReadMemoryResponse tag value (0xA3), the flags field set to kCommandFlag_HasDataPhase (1). The parameter count set to 2 for the status code and the data byte count parameters shown below. Table 13-14. ReadMemoryResponse Parameters Byte # Parameter Descripton 0-3 Status code The status of the associated Read Memory command. 4-7 Data byte count The number of bytes sent in the data phase. FlashReadOnceResponse:The FlashReadOnceResponse packet is sent by the target in response to the host sending a FlashReadOnce command. The FlashReadOnceResponse packet contains the framing packet data and the command packet data, with the command/response tag set to a FlashReadOnceResponse tag value (0xAF), and the flags field set to 0. The parameter count is set to 2 plus the number of words requested to be read in the FlashReadOnceCommand. Table 13-15. FlashReadOnceResponse Parameters Byte # Value Parameter 0-3 Status Code 4-7 Byte count to read ... ... Can be up to 20 bytes of requested read data. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 279 Functional Description The FlashReadResourceResponse packet is sent by the target in response to the host sending a FlashReadResource command. The FlashReadResourceResponse packet contains the framing packet data and command packet data, with the command/response tag set to a FlashReadResourceResponse tag value (0xB0), and the flags field set to kCommandFlag_HasDataPhase (1). Table 13-16. FlashReadResourceResponse Parameters Byte # Value Parameter 0-3 Status Code 4-7 Data byte count 13.3.6 Flashloader Command API All Kinetis Flashloader command APIs follow the command packet format that is wrapped by the framing packet, as explained in previous sections. * For a list of commands supported by the Flashloader, see Table 13-2, Commands supported. * For a list of status codes returned by the Kinetis Flashloader, see Table 13-47, Kinetis Flashloader Status Error Codes. 13.3.6.1 Call command The Call command will execute a function that is written in memory at the address sent in the command. The address needs to be a valid memory location residing in accessible flash (internal or external) or in RAM. The command supports the passing of one 32-bit argument. Although the command supports a stack address, at this time the call will still take place using the current stack pointer. After execution of the function, a 32-bit return value will be returned in the generic response message. Table 13-17. Parameters for Call Command Byte # Command 0-3 Call address 4-7 Argument word 8 - 11 Stack pointer KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 280 Freescale Semiconductor, Inc. Chapter 13 Kinetis Flashloader Target Host Call: Address=0x00000cd9, arg=0 0x5a a4 0c 00 16 5c 0a 00 00 02 d9 0c 00 00 00 000 000 00 ACK: 0x5a a1 Generic Response: 0x5a a4 0c 00 79 d0 a0 00 00 02 00 00 00 00 0a 00 00 00 ACK: 0x5a a1 Figure 13-7. Protocol Sequence for Call Command Response: The target (Kinetis Flashloader) will return a GenericResponse packet with a status code either set to the return value of the function called or set to kStatus_InvalidArgument (105). 13.3.6.2 GetProperty command The GetProperty command is used to query the flashloader about various properties and settings. Each supported property has a unique 32-bit tag associated with it. The tag occupies the first parameter of the command packet. The target returns a GetPropertyResponse packet with the property values for the property identified with the tag in the GetProperty command. Properties are the defined units of data that can be accessed with the GetProperty or SetProperty commands. Properties may be read-only or read-write. All read-write properties are 32-bit integers, so they can easily be carried in a command parameter. For a list of properties and their associated 32-bit property tags supported by the Kinetis Flashloader, see Table 13-43. The 32-bit property tag is the only parameter required for GetProperty command. Table 13-18. Parameters for GetProperty Command Byte # 0-3 Command Property tag KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 281 Functional Description Target Host GetProperty: Property tag = 0x01 0x5a a4 08 00 73 d4 07 00 00 01 01 00 00 00 ACK: 0x5a a1 Process command Generic Response: 0x5a a4 0c 00 07 7a a7 00 00 02 00 00 00 00 00 00 01 4b ACK: 0x5a a1 Figure 13-8. Protocol Sequence for GetProperty Command Table 13-19. GetProperty Command Packet Format (Example) GetProperty Framing packet Command packet Parameter Value start byte 0x5A packetType 0xA4, kFramingPacketType_Command length 0x08 0x00 crc16 0x73 0xD4 commandTag 0x07 - GetProperty flags 0x00 reserved 0x00 parameterCount 0x01 propertyTag 0x00000001 - CurrentVersion The GetProperty command has no data phase. Response: In response to a GetProperty command, the target will send a GetPropertyResponse packet with the response tag set to 0xA7. The parameter count indicates the number of parameters sent for the property values, with the first parameter showing status code 0, followed by the property value(s). The next table shows an example of a GetPropertyResponse packet. Table 13-20. GetProperty Response Packet Format (Example) GetPropertyResponse Framing packet Parameter Value start byte 0x5A packetType 0xA4, kFramingPacketType_Command length 0x0c 0x00 (12 bytes) Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 282 Freescale Semiconductor, Inc. Chapter 13 Kinetis Flashloader Table 13-20. GetProperty Response Packet Format (Example) (continued) GetPropertyResponse Command packet Parameter Value crc16 0x07 0x7a responseTag 0xA7 flags 0x00 reserved 0x00 parameterCount 0x02 status 0x00000000 propertyValue 0x0000014b - CurrentVersion 13.3.6.3 SetProperty command The SetProperty command is used to change or alter the values of the properties or options in the Kinetis Flashloader. However, the SetProperty command can only change the value of properties that are writable--see Table 13-43, Properties used by Get/ SetProperty Commands. If you try to set a value for a read-only property, then the Kinetis Flashloader will return an error. The property tag and the new value to set are the 2 parameters required for the SetProperty command. Table 13-21. Parameters for SetProperty Command Byte # Command 0-3 Property tag 4-7 Property value KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 283 Functional Description Target Host SetProperty: Property tag = 10, Property Value = 1 0x5a a4 0c 00 67 8d 0c 00 00 02 0a 00 00 00 01 00 00 00 ACK : 0x5a a1 Process command GenericResponse: 0x5a a4 00 9e 10 a0 00 0c 02 00 00 00 00 0c 00 00 00 ACK: 0x5a a1 Figure 13-9. Protocol Sequence for SetProperty Command Table 13-22. SetProperty Command Packet Format (Example) SetProperty Framing packet Command packet Parameter Value start byte 0x5A packetType 0xA4, kFramingPacketType_Command length 0x0C 0x00 crc16 0x67 0x8D commandTag 0x0C - SetProperty with property tag 10 flags 0x00 reserved 0x00 parameterCount 0x02 propertyTag 0x0000000A - VerifyWrites propertyValue 0x00000001 The SetProperty command has no data phase. Response: The target (Kinetis Flashloader) will return a GenericResponse packet with one of following status codes: Table 13-23. SetProperty Response Status Codes Status Code kStatus_Success kStatus_ReadOnly kStatus_UnknownProperty kStatus_InvalidArgument KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 284 Freescale Semiconductor, Inc. Chapter 13 Kinetis Flashloader 13.3.6.4 FlashEraseAll command The FlashEraseAll command performs an erase of the entire flash memory. If any flash regions are protected, then the FlashEraseAll command will fail and return an error status code. Executing the FlashEraseAll command will release flash security if it (flash security) was enabled, by setting the FTFA_FSEC register. However, the FSEC field of the flash configuration field is erased, so unless it is reprogrammed, the flash security will be re-enabled after the next system reset. The Command tag for FlashEraseAll command is 0x01 set in the commandTag field of the command packet. The FlashEraseAll command requires no parameters. Target Host FlashEraseAll 0x5a a4 04 00 c4 2e 01 00 00 00 ACK: 0x5a a1 Process command Generic Response: 0x5a a4 0c 00 53 63 a0 00 04 02 00 00 00 00 01 00 00 00 ACK: 0x5a a1 Figure 13-10. Protocol Sequence for FlashEraseAll Command Table 13-24. FlashEraseAll Command Packet Format (Example) FlashEraseAll Parameter Value Framing packet start byte 0x5A packetType 0xA4, kFramingPacketType_Command length 0x04 0x00 crc16 0xC4 0x2E commandTag 0x01 - FlashEraseAll flags 0x00 reserved 0x00 parameterCount 0x00 Command packet The FlashEraseAll command has no data phase. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 285 Functional Description Response: The target (Kinetis Flashloader ) will return a GenericResponse packet with status code either set to kStatus_Success for successful execution of the command, or set to an appropriate error status code. 13.3.6.5 FlashEraseRegion command The FlashEraseRegion command performs an erase of one or more sectors of the flash memory or a specified range of flash within the connected SPI flash devices. The start address and number of bytes are the 2 parameters required for the FlashEraseRegion command. The start and byte count parameters must be , or the FlashEraseRegion command will fail and return kStatus_FlashAlignmentError (0x101). If the region specified does not fit in the flash memory space, the FlashEraseRegion command will fail and return kStatus_FlashAddressError (0x102). If any part of the region specified is protected, the FlashEraseRegion command will fail and return kStatus_MemoryRangeInvalid (0x10200). Table 13-25. Parameters for FlashEraseRegion Command Byte # Parameter 0-3 Start address 4-7 Byte count Target Host FlashEraseRegion: startAddress=0, byteCount=1024 0x5a a4 0c 00 f9 a6 02 00 00 00 00 00 00 00 00 04 00 00 ACK: 0x5a a1 Process command Generic Response: 0x5a a4 0c 00 ba 55 a0 00 00 02 00 00 00 00 02 00 00 00 ACK: 0x5a a1 Figure 13-11. Protocol Sequence for FlashEraseRegion Command KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 286 Freescale Semiconductor, Inc. Chapter 13 Kinetis Flashloader Table 13-26. FlashEraseRegion Command Packet Format (Example) FlashEraseRegion Framing packet Command packet Parameter Value start byte 0x5A packetType 0xA4, kFramingPacketType_Command length 0x0C 0x00 crc16 0xF9 0x A6 commandTag 0x02, kCommandTag_FlashEraseRegion flags 0x00 reserved 0x00 parameterCount 0x02 startAddress 0x00 0x00 0x00 0x00 (0x0000_0000) byte count 0x00 0x04 0x00 0x00 (0x400) The FlashEraseRegion command has no data phase. Response: The target (Kinetis Flashloader ) will return a GenericResponse packet with one of following error status codes. Table 13-27. FlashEraseRegion Response Status Codes Status Code kStatus_Success (0x0) kStatus_MemoryRangeInvalid (0x10200) kStatus_FlashAlignmentError (0x101) kStatus_FlashAddressError (0x102) kStatus_FlashAccessError (0x103) kStatus_FlashProtectionViolation (0x104) kStatus_FlashCommandFailure (0x105) 13.3.6.6 FillMemory command The FillMemory command fills a range of bytes in memory with a data pattern. It follows the same rules as the WriteMemory command. The difference between FillMemory and WriteMemory is that a data pattern is included in FillMemory command parameter, and there is no data phase for the FillMemory command, while WriteMemory does have a data phase. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 287 Functional Description Table 13-28. Parameters for FillMemory Command Byte # Command 0-3 Start address of memory to fill 4-7 Number of bytes to write with the pattern * The start address should be 32-bit aligned. * The number of bytes must be evenly divisible by 4. 8 - 11 32-bit pattern * To fill with a byte pattern (8-bit), the byte must be replicated 4 times in the 32-bit pattern. * To fill with a short pattern (16-bit), the short value must be replicated 2 times in the 32-bit pattern. For example, to fill a byte value with 0xFE, the word pattern would be 0xFEFEFEFE; to fill a short value 0x5AFE, the word pattern would be 0x5AFE5AFE. Special care must be taken when writing to flash. * First, any flash sector written to must have been previously erased with a FlashEraseAll or FlashEraseRegion command. * Writing to flash requires the start address to be . * If the VerifyWrites property is set to true, then writes to flash will also perform a flash verify program operation. When writing to RAM, the start address need not be aligned, and the data will not be padded. Target Host FillMemory, with word pattern 0x12345678 0x5a a4 10 00 e4 57 05 00 00 03 00 70 00 00 00 08 00 00 78 56 34 12 ACK: 0x5a a1 Process command Generic Response: 0x5a a4 0c 00 97 04 a0 00 00 02 00 00 00 00 05 00 00 00 ACK: 0x5a a1 Figure 13-12. Protocol Sequence for FillMemory Command KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 288 Freescale Semiconductor, Inc. Chapter 13 Kinetis Flashloader Table 13-29. FillMemory Command Packet Format (Example) FillMemory Framing packet Command packet Parameter Value start byte 0x5A packetType 0xA4, kFramingPacketType_Command length 0x10 0x00 crc16 0xE4 0x57 commandTag 0x05 - FillMemory flags 0x00 Reserved 0x00 parameterCount 0x03 startAddress 0x00007000 byteCount 0x00000800 patternWord 0x12345678 The FillMemory command has no data phase. Response: upon successful execution of the command, the target (Kinetis Flashloader) will return a GenericResponse packet with a status code set to kStatus_Success, or to an appropriate error status code. 13.3.6.7 FlashProgramOnce command The FlashProgramOnce command writes data (that is provided in a command packet) to a specified range of bytes in the program once field. Special care must be taken when writing to the program once field. * The program once field only supports programming once, so any attempted to reprogram a program once field will get an error response. * Writing to the program once field requires the byte count to be 4-byte aligned or 8byte aligned. The FlashProgramOnce command uses 3 parameters: index, byteCount, data. Table 13-30. Parameters for FlashProgramOnce Command Byte # Command 0-3 Index of program once field 4-7 Byte count (must be evenly divisible by 4) 8 - 11 Data 12 - 16 Data KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 289 Functional Description Target Host FlashProgramOnce: index=0, byteCount=4, data=0x12345678 0x5a a4 10 00 7e 89 0e 00 00 03 00 00 00 00 04 00 00 00 78 56 34 12 ACK: 0x5a a1 Process command Generic Response: 0x5a a4 0c 00 88 1a a0 00 00 02 00 00 00 00 0e 00 00 00 ACK: 0x5a a1 Figure 13-13. Protocol Sequence for FlashProgramOnce Command Table 13-31. FlashProgramOnce Command Packet Format (Example) FlashProgramOnce Framing packet Command packet Parameter Value start byte 0x5A packetType 0xA4, kFramingPacketType_Command length 0x10 0x00 crc16 0x7E4 0x89 commandTag 0x0E - FlashProgramOnce flags 0 reserved 0 parameterCount 3 index 0x0000_0000 byteCount 0x0000_0004 data 0x1234_5678 Response: upon successful execution of the command, the target (Kinetis Flashloader) will return a GenericResponse packet with a status code set to kStatus_Success, or to an appropriate error status code. 13.3.6.8 FlashReadOnce command The FlashReadOnce command returns the contents of the program once field by given index and byte count. The FlashReadOnce command uses 2 parameters: index and byteCount. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 290 Freescale Semiconductor, Inc. Chapter 13 Kinetis Flashloader Table 13-32. Parameters for FlashReadOnce Command Byte # Parameter Description 0-3 index Index of the program once field (to read from) 4-7 byteCount Number of bytes to read and return to the caller Target Host FlashReadOnce: index=0, byteCount=4 0x5a a4 0c 00 c1 a5 0f 00 00 02 00 00 00 00 04 00 00 00 ACK: 0x5a a1 Process command Generic Response: 0x5a a4 10 00 3f 6f af 00 00 03 00 00 00 00 04 00 00 00 78 56 34 12 ACK: 0x5a a1 Figure 13-14. Protocol Sequence for FlashReadOnce Command Table 13-33. FlashReadOnce Command Packet Format (Example) FlashReadOnce Parameter Value Framing packet start byte 0x5A packetType 0xA4 length 0x0C 0x00 crc 0xC1 0xA5 commandTag 0x0F - FlashReadOnce flags 0x00 reserved 0x00 parameterCount 0x02 index 0x0000_0000 byteCount 0x0000_0004 Command packet Table 13-34. FlashReadOnce Response Format (Example) FlashReadOnce Response Parameter Value Framing packet start byte 0x5A packetType 0xA4 Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 291 Functional Description Table 13-34. FlashReadOnce Response Format (Example) (continued) FlashReadOnce Response Command packet Parameter Value length 0x10 0x00 crc 0x3F 0x6F commandTag 0xAF flags 0x00 reserved 0x00 parameterCount 0x03 status 0x0000_0000 byteCount 0x0000_0004 data 0x1234_5678 Response: upon successful execution of the command, the target (Kinetis Flashloader) will return a FlashReadOnceResponse packet with a status code set to kStatus_Success, a byte count and corresponding data read from Program Once Field upon successful execution of the command, or will return with a status code set to an appropriate error status code and a byte count set to 0. 13.3.6.9 FlashReadResource command The FlashReadResource command returns the contents of the IFR field or Flash firmware ID, by given offset, byte count, and option. The FlashReadResource command uses 3 parameters: start address, byteCount, option. Table 13-35. Parameters for FlashReadResource Command Byte # Parameter Command 0-3 start address Start address of specific non-volatile memory to be read 4-7 byteCount Byte count to be read 8 - 11 option 0: IFR 1: Flash firmware ID KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 292 Freescale Semiconductor, Inc. Chapter 13 Kinetis Flashloader Target Host FlashReadResource: start address=0, byteCount=8, option=1 5a a4 10 00 b3 cc 10 00 00 03 00 00 00 00 08 00 00 00 01 00 00 00 ACK: 0x5a a1 Process command FlashReadResource Response 5a a4 0c 00 08 d2 b0 01 00 02 00 00 00 00 08 00 00 00 ACK: 0x5a a1 Data packet 5a a5 08 00 9c d3 00 08 00 00 00 01 00 06 Process Data ACK: 0x5a a1 Generic Response 5a a4 0c 00 75 a3 a0 00 00 02 00 00 00 00 10 00 00 00 ACK: 0x5a a1 Figure 13-15. Protocol Sequence for FlashReadResource Command Table 13-36. FlashReadResource Command Packet Format (Example) FlashReadResource Framing packet Command packet Parameter Value start byte 0x5A packetType 0xA4 length 0x10 0x00 crc 0xB3 0xCC commandTag 0x10 - FlashReadResource flags 0x00 reserved 0x00 parameterCount 0x03 startAddress 0x0000_0000 byteCount 0x0000_0008 option 0x0000_0001 KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 293 Functional Description Table 13-37. FlashReadResource Response Format (Example) FlashReadResource Response Framing packet Command packet Parameter Value start byte 0x5A packetType 0xA4 length 0x0C 0x00 crc 0xD2 0xB0 commandTag 0xB0 flags 0x01 reserved 0x00 parameterCount 0x02 status 0x0000_0000 byteCount 0x0000_0008 Data phase: The FlashReadResource command has a data phase. Because the target (Kinetis Flashloader ) works in slave mode, the host must pull data packets until the number of bytes of data specified in the byteCount parameter of FlashReadResource command are received by the host. 13.3.6.10 WriteMemory command The WriteMemory command writes data provided in the data phase to a specified range of bytes in memory (flash or RAM). However, if flash protection is enabled, then writes to protected sectors will fail. Special care must be taken when writing to flash. * First, any flash sector written to must have been previously erased with a FlashEraseAll or FlashEraseRegion command. * Writing to flash requires the start address to be . * If the VerifyWrites property is set to true, then writes to flash will also perform a flash verify program operation. When writing to RAM, the start address need not be aligned, and the data will not be padded. The start address and number of bytes are the 2 parameters required for WriteMemory command. Table 13-38. Parameters for WriteMemory Command Byte # Command 0-3 Start address 4-7 Byte count KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 294 Freescale Semiconductor, Inc. Chapter 13 Kinetis Flashloader Target Host WriteMemory : startAddress = 0x20000400, byteCount = 0x64 0x5a a4 0c 00 06 5a 04 00 00 02 00 04 00 20 64 00 00 00 ACK: 0x5a a1 Process command Generic Response: 0x5a a4 0c 00 a0 0e 04 01 00 02 00 04 00 20 40 00 00 00 ACK: 0x5a a1 Data packet : 0x5a a5 20 00 CRC16 32 bytes data Process Data ACK: 0x5a a1 Final Data packet 0x5a a5 length16 CRC16 32 bytes data Process Data ACK Generic Response 0x5a a4 0c 00 23 72 a0 00 00 02 00 00 00 00 04 00 00 00 ACK: 0x5a a1 Figure 13-16. Protocol Sequence for WriteMemory Command Table 13-39. WriteMemory Command Packet Format (Example) WriteMemory Framing packet Command packet Parameter Value start byte 0x5A packetType 0xA4, kFramingPacketType_Command length 0x0C 0x00 crc16 0x06 0x5A commandTag 0x04 - writeMemory flags 0x00 reserved 0x00 parameterCount 0x02 Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 295 Functional Description Table 13-39. WriteMemory Command Packet Format (Example) (continued) WriteMemory Parameter Value startAddress 0x20000400 byteCount 0x00000064 Data Phase: The WriteMemory command has a data phase; the host will send data packets until the number of bytes of data specified in the byteCount parameter of the WriteMemory command are received by the target. Response: The target (Kinetis Flashloader ) will return a GenericResponse packet with a status code set to kStatus_Success upon successful execution of the command, or to an appropriate error status code. 13.3.6.11 Read memory command The ReadMemory command returns the contents of memory at the given address, for a specified number of bytes. This command can read any region of memory accessible by the CPU and not protected by security. The start address and number of bytes are the 2 parameters required for ReadMemory command. Table 13-40. Parameters for read memory command Byte Parameter 0-3 Start address 4-7 Byte count Description Start address of memory to read from Number of bytes to read and return to caller KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 296 Freescale Semiconductor, Inc. Chapter 13 Kinetis Flashloader Target Host readMemory : startAddress = 0x20000400, byteCount = 100 0x5a a4 0c 00 1d 23 03 00 00 02 00 04 00 20 64 00 00 00 ACK: 0x5a a1 Process command Generic response for command: 0x5a a4 0c 00 27 f6 a3 01 00 02 00 00 00 00 64 00 00 00 ACK: 0x5a a1 Data packet : 0x5a a5 20 00 CRC 16 32 bytes data Process Data ACK: 0x5a a1 Final Data packet 0x5a a5 length 16 CRC 16 32 bytes data ACK: 0x5a a1 Process Data Final Generic Response 0x5a a4 0c 00 23 72 a 0 00 00 02 00 00 00 00 04 00 00 00 0x5a a4 0c 00 0e 23 a0 00 00 02 00 00 00 00 03 00 00 00 ACK: 0x5a a1 Figure 13-17. Command sequence for read memory ReadMemory Parameter Framing packet Start byte packetType Command packet Value 0x5A0xA4, kFramingPacketType_Command length 0x0C 0x00 crc16 0x1D 0x23 commandTag 0x03 - readMemory flags 0x00 reserved 0x00 parameterCount 0x02 startAddress 0x20000400 byteCount 0x00000064 KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 297 Functional Description Data Phase: The ReadMemory command has a data phase. Since the target (Kinetis Flashloader) works in slave mode, the host need pull data packets until the number of bytes of data specified in the byteCount parameter of ReadMemory command are received by host. Response: The target (Kinetis Flashloader) will return a GenericResponse packet with a status code either set to kStatus_Success upon successful execution of the command, or set to an appropriate error status code. 13.3.6.12 Execute command The execute command results in the flashloader setting the program counter to the code at the provided jump address, R0 to the provided argument, and a Stack pointer to the provided stack pointer address. Prior to the jump, the system is returned to the reset state. The Jump address, function argument pointer, and stack pointer are the parameters required for the Execute command. Table 13-41. Parameters for Execute Command Byte # Command 0-3 Jump address 4-7 Argument word 8 - 11 Stack pointer address The Execute command has no data phase. Response: Before executing the Execute command, the target (Kinetis Flashloader) will validate the parameters and return a GenericResponse packet with a status code either set to kStatus_Success or an appropriate error status code. 13.3.6.13 Reset command The Reset command will result in flashloader resetting the chip. The Reset command requires no parameters. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 298 Freescale Semiconductor, Inc. Chapter 13 Kinetis Flashloader Target Host Reset 0x5a a4 04 00 6f 46 0b 00 00 00 ACK : 0x5a a1 Process command GenericResponse: 0x5a a4 0c 00 f8 0b a 0 00 04 02 00 00 00 00 0b 00 00 00 ACK: 0x5a a1 Figure 13-18. Protocol Sequence for Reset Command Table 13-42. Reset Command Packet Format (Example) Reset Framing packet Command packet Parameter Value start byte 0x5A packetType 0xA4, kFramingPacketType_Command length 0x04 0x00 crc16 0x6F 0x46 commandTag 0x0B - reset flags 0x00 reserved 0x00 parameterCount 0x00 The Reset command has no data phase. Response: The target (Kinetis Flashloader) will return a GenericResponse packet with status code set to kStatus_Success, before resetting the chip. 13.4 Peripherals Supported This section describes the peripherals supported by the Kinetis Flashloader. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 299 Peripherals Supported 13.4.1 I2C Peripheral The Kinetis Flashloader supports loading data into flash via the I2C peripheral, where the I2C peripheral serves as the I2C slave. A 7-bit slave address is used during the transfer. The Kinetis Flashloader uses 0x10 as the I2C slave address, and supports 400 kbps as the I2C baud rate. Because the I2C peripheral serves as an I2C slave device, each transfer should be started by the host, and each outgoing packet should be fetched by the host. * An incoming packet is sent by the host with a selected I2C slave address and the direction bit is set as write. * An outgoing packet is read by the host with a selected I2C slave address and the direction bit is set as read. * 0x00 will be sent as the response to host if the target is busy with processing or preparing data. The following flow charts demonstrate the communication flow of how the host reads ping packet, ACK and response from the target. Fetch Ping response End Read 1 byte from target Read leftover bytes of ping response packet No Yes 0x5A received? Yes Read 1 byte from target 0x7A received? No Report Error Figure 13-19. Host reads ping response from target via I2C KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 300 Freescale Semiconductor, Inc. Chapter 13 Kinetis Flashloader Fetch ACK Report an error No Read 1 byte from target No Process NAK 0xA2 received? Yes No Reached maximum retries? 0x5A received? No Yes Read 1 byte from target 0xA1 received? Yes Yes Report a timeout error End Figure 13-20. Host reads ACK packet from target via I2C Fetch Response Read 1 byte from target No Reached maximum retries? End No Read payload data from target 0x5A received? Yes Yes Payload length less than supported length? Read 1 byte from target Yes Report a timeout error (End) 0xA4 received? Yes Read payload length part from target (2 bytes) No Set payload length to maximum supported length Read CRC checksum from target (2 bytes) No Figure 13-21. Host reads response from target via I2C 13.4.2 SPI Peripheral The Kinetis Flashloader supports loading data into flash via the SPI peripheral, where the SPI peripheral serves as a SPI slave. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 301 Peripherals Supported The Kinetis Flashloader supports 400 kbps as the SPI baud rate. The SPI peripheral uses the following bus attributes: * Clock Phase = 1 (Second Edge) * Clock Polarity = 1 (Active Low) Because the SPI peripheral serves as a SPI slave device, each transfer should be started by the host, and each outgoing packet should be fetched by the host. The transfer on SPI is slightly different from I2C: * Host will receive 1 byte after it sends out any byte. * Received bytes should be ignored when host is sending out bytes to target * Host starts reading bytes by sending 0x00s to target * The byte 0x00 will be sent as response to host if target is under the following conditions: * Processing incoming packet * Preparing outgoing data * Received invalid data The SPI bus configuration is: * Phase = 1; data is sampled on rising edges * Polarity = 1; idle is high * MSB is transmitted first For any transfer where the target does not have actual data to send, the target (slave) is responsible for ensuring that 0x00 bytes will be returned to the host (master). The host uses framing packets to identify real data and not "dummy" 0x00 bytes (which do not have framing packets). The following flowcharts demonstrate how the host reads a ping response, an ACK and a command response from target via SPI. Fetch Ping response End Send 0x00 to shift out 1 byte from target Send 0x00s to shift out leftover bytes of ping response No Yes 0x5A received? Yes Send 0x00 to shift out 1 byte from target 0xA7 received? No Report Error Figure 13-22. Host reads ping packet from target via SPI KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 302 Freescale Semiconductor, Inc. Chapter 13 Kinetis Flashloader Report an error Fetch ACK No Send 0x00 to shift out 1 byte from target No Process NAK 0xA2 received? Yes No Reached maximum retries? No 0x5A received? Yes Yes Report a timeout error Send 0x00 to shift out 1 byte from target 0xA1 received? Yes Next action Figure 13-23. Host reads ACK from target via SPI Fetch Response Send 0x00 to shift out 1 byte from target No Reached maximum retries? End No Write 0x00s to shift out payload data from target 0x5A received? Yes Yes Payload length less than supported length? Send 0x00 to shift out 1 byte from target Yes Report a timeout error (End) 0xA4 received? Yes Write 0x00s to shift out payload length part from target (2 bytes) No Set payload length to maximum supported length Write 0x00s to shift out CRC checksum from target (2 bytes) No Figure 13-24. Host reads response from target via SPI 13.4.3 UART Peripheral The Kinetis Flashloader integrates an autobaud detection algorithm for the UART peripheral, thereby providing flexible baud rate choices. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 303 Peripherals Supported Autobaud feature: If UARTn is used to connect to the flashloader, then the UARTn_RX pin must be kept high and not left floating during the detection phase in order to comply with the autobaud detection algorithm. After the flashloader detects the ping packet (0x5A 0xA6) on UARTn_RX, the flashloader firmware executes the autobaud sequence. If the baudrate is successfully detected, then the flashloader will send a ping packet response [(0x5A 0xA7), protocol version (4 bytes), protocol version options (2 bytes) and crc16 (2 bytes)] at the detected baudrate. The Kinetis Flashloader then enters a loop, waiting for flashloader commands via the UART peripheral. NOTE The data bytes of the ping packet must be sent continuously (with no more than 80 ms between bytes) in a fixed UART transmission mode (8-bit data, no parity bit and 1 stop bit). If the bytes of the ping packet are sent one-by-one with more than 80 ms delay between them, then the autobaud detection algorithm may calculate an incorrect baud rate. In this case, the autobaud detection state machine should be reset. Supported baud rates: The baud rate is closely related to the MCU core and system clock frequencies. Typical baud rates supported are 9600, 19200, 38400, 57600, and 115200. Packet transfer: After autobaud detection succeeds, flashloader communications can take place over the UART peripheral. The following flow charts show: * How the host detects an ACK from the target * How the host detects a ping response from the target * How the host detects a command response from the target KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 304 Freescale Semiconductor, Inc. Chapter 13 Kinetis Flashloader Wait for ACK Report an error No Wait for 1 byte from target No Yes Process NAK 0xA2 received? No Reached maximum retries? 0x5A received? No Yes Wait for 1 byte from target 0xA1 received? Yes Yes End Report a timeout error Figure 13-25. Host reads an ACK from target via UART Wait for ping response End Wait for remaining bytes of ping response packet Wait for 1 byte from target No Yes 0x5A received? Yes Wait for 1 byte from target 0xA7 received? No Report Error Figure 13-26. Host reads a ping response from target via UART KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 305 Get/SetProperty Command Properties Wait for response Wait for 1 byte from target No Reached maximum retries? End No Wait for payload data from target 0x5A received? Yes Yes Yes Wait for 1 byte from target Report a timeout error (End) 0xA4 received? Payload length less than supported length? Yes Wait for payload length part from target (2 bytes) No Set payload length to maximum supported length Wait for CRC checksum from target (2 bytes) No Figure 13-27. Host reads a command response from target via UART 13.5 Get/SetProperty Command Properties This section lists the properties of the GetProperty and SetProperty commands. Table 13-43. Properties used by Get/SetProperty Commands, sorted by Value Property Writable Tag Value Size Descripion CurrentVersion No 01h 4 Current flashloader version. AvailablePeripherals No 02h 4 The set of peripherals supported on this chip. FlashStartAddress No 03h 4 Start address of program flash. FlashSizeInBytes No 04h 4 Size in bytes of program flash. FlashSectorSize No 05h 4 The size in bytes of one sector of program flash. This is the minimum erase size. FlashBlockCount No 06h 4 Number of blocks in the flash array. AvailableCommands No 07h 4 The set of commands supported by the flashloader. VerifyWrites Yes 0Ah 4 Controls whether the flashloader will verify writes to flash. VerifyWrites feature is enabled by default. 0 - No verification is done. 1 - Enable verification. MaxPacketSize No 0Bh 4 Maximum supported packet size for the currently active peripheral interface. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 306 Freescale Semiconductor, Inc. Chapter 13 Kinetis Flashloader Table 13-43. Properties used by Get/SetProperty Commands, sorted by Value (continued) Property ReservedRegions Writable Tag Value Size No 0Ch 16 Descripion List of memory regions reserved by the flashloader. Returned as value pairs (<start-address-of-region>, <end-address-of-region>). * If HasDataPhase flag is not set, then the Response packet parameter count indicates the number of pairs. * If HasDataPhase flag is set, then the second parameter is the number of bytes in the data phase. RAMStartAddress No 0Eh 4 Start address of RAM RAMSizeInBytes No 0Fh 4 Size in bytes of RAM SystemDeviceId No 10h 4 Value of the Kinetis System Device Identification register. FlashSecurityState No 11h 4 Indicates whether Flash security is enabled 0 - Flash security is disabled 1 - Flash security is enabled UniqueDeviceId No 12h 16 Unique device identification, value of Kinetis Unique Identification registers (16 for K series devices, 12 for KL series devices) FacSupport No 13h 4 FAC (Flash Access Control) support flag 0 - FAC not supported 1 - FAC supported FlashAcessSegmentSize No 14h 4 The size in bytes of 1 segment of flash FlashAcessSegmentCount No 15h 4 FAC segment count (The count of flash access segments within the flash model.) 13.5.1 Property Definitions Get/Set property definitions are provided in this section. 13.5.1.1 CurrentVersion Property The value of this property is a 4-byte structure containing the current version of the flashloader. Table 13-44. Fields of CurrentVersion property: Bits [31:24] [23:16] [15:8] [7:0] Field Name = 'K' (0x4B) Major version Minor version Bugfix version KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 307 Get/SetProperty Command Properties 13.5.1.2 AvailablePeripherals Property The value of this property is a bitfield that lists the peripherals supported by the flashloader and the hardware on which it is running. Table 13-45. Peripheral bits: Bit [31:7] [6] [5] [4] [3] [2] [1] [0] Peripheral Reserved Reserved Reserved Reserved Reserved SPI Slave I2C Slave UART If the peripheral is available, then the corresponding bit will be set in the property value. All reserved bits must be set to 0. 13.5.1.3 AvailableCommands Property This property value is a bitfield with set bits indicating the commands enabled in the flashloader. Only commands that can be sent from the host to the target are listed in the bitfield. Response commands such as GenericResponse are excluded. The bit number that identifies whether a command is present is the command's tag value minus 1. 1 is subtracted from the command tag because the lowest command tag value is 0x01. To get the bit mask for a given command, use this expression: mask = 1 << (tag - 1) Table 13-46. Command bits: [0] FlashEraseAll [1] FlashEraseRegion [2] ReadMemory [3] WriteMemory [4] FillMemory [5] Reserved [6] GetProperty [7] Reserved [8] Execute [9] Call Reset SetProperty Reserved FlashProgramOnce FlashReadOnce [15] [14] [13] [12] [11] [10] FlashReadResource Reserved Command [31: [16] 17] Reserved Bit KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 308 Freescale Semiconductor, Inc. Chapter 13 Kinetis Flashloader 13.6 Kinetis Flashloader Status Error Codes This section describes the status error codes that the Kinetis Flashloader returns to the host. Table 13-47. Kinetis Flashloader Status Error Codes, sorted by Value Error Code Value Description kStatus_Success 0 Operation succeeded without error. kStatus_Fail 1 Operation failed with a generic error. kStatus_ReadOnly 2 Requested value cannot be changed because it is read-only. kStatus_OutOfRange 3 Requested value is out of range. kStatus_InvalidArgument 4 The requested command's argument is undefined. kStatus_Timeout 5 A timeout occurred. kStatus_FlashSizeError 100 Not used. kStatus_FlashAlignmentError 101 Address or length does not meet required alignment. kStatus_FlashAddressError 102 Address or length is outside addressable memory. kStatus_FlashAccessError 103 The FTFA_FSTAT[ACCERR] bit is set. kStatus_FlashProtectionViolation 104 The FTFA_FSTAT[FPVIOL] bit is set. kStatus_FlashCommandFailure 105 The FTFA_FSTAT[MGSTAT0] bit is set. kStatus_FlashUnknownProperty 106 Unknown Flash property. kStatus_FlashEraseKeyError 107 The key provided does not match the programmed flash key. kStatus_FlashRegionExecuteOnly 108 The area of flash is protected as execute only. kStatus_I2C_SlaveTxUnderrun 200 I2C Slave TX Underrun error. kStatus_I2C_SlaveRxOverrun 201 I2C Slave RX Overrun error. kStatus_I2C_AribtrationLost 202 I2C Arbitration Lost error. kStatus_SPI_SlaveTxUnderrun 300 SPI Slave TX Underrun error. kStatus_SPI_SlaveRxOverrun 301 SPI Slave RX Overrun error. kStatus_SPI_Timeout 302 SPI tranfser timed out. kStatus_SPI_Busy 303 SPI instance is already busy performing a transfer. 304 Attempt to abort a transfer when no transfer was in progress. kStatus_SPI_NoTransferInProgress kStatus_UnknownCommand 10000 The requested command value is undefined. kStatus_SecurityViolation 10001 Command is disallowed because flash security is enabled. kStatus_AbortDataPhase 10002 Abort the data phase early. kStatusMemoryRangeInvalid 10200 Memory range conflicts with a protected region. kStatus_UnknownProperty 10300 The requested property value is undefined. kStatus_ReadOnlyProperty 10301 The requested property value cannot be written. kStatus_InvalidPropertyValue 10302 The specified property value is invalid. kStatus_AppCrcCheckPassed 10400 CRC check is valid and passed. kStatus_AppCrcCheckFailed 10401 CRC check is valid but failed. kStatus_AppCrcCheckInactive 10402 CRC check is inactive. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 309 Kinetis Flashloader Status Error Codes Table 13-47. Kinetis Flashloader Status Error Codes, sorted by Value (continued) Error Code Value Description kStatus_AppCrcCheckInvalid 10403 CRC check is invalid, because the BCA is invalid or the CRC parameters are unset (all 0xFF bytes). kStatus_AppCrcCheckOutOfRange 10404 CRC check is valid but addresses are out of range. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 310 Freescale Semiconductor, Inc. Chapter 14 Reset Control Module (RCM) 14.1 Introduction Information found here describes the registers of the Reset Control Module (RCM). The RCM implements many of the reset functions for the chip. See the chip's reset chapter for more information. See AN4503: Power Management for Kinetis MCUs for further details on using the RCM. 14.2 Reset memory map and register descriptions The RCM Memory Map/Register Definition can be found here. The Reset Control Module (RCM) registers provide reset status information and reset filter control. NOTE The RCM registers can be written only in supervisor mode. Write accesses in user mode are blocked and will result in a bus error. RCM memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4007_F000 System Reset Status Register 0 (RCM_SRS0) 8 R 82h 14.2.1/312 4007_F001 System Reset Status Register 1 (RCM_SRS1) 8 R 00h 14.2.2/313 4007_F004 Reset Pin Filter Control register (RCM_RPFC) 8 R/W 00h 14.2.3/315 4007_F005 Reset Pin Filter Width register (RCM_RPFW) 8 R/W 00h 14.2.4/316 Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 311 Reset memory map and register descriptions RCM memory map (continued) Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 4007_F007 Mode Register (RCM_MR) 8 R 00h 14.2.5/317 4007_F008 Sticky System Reset Status Register 0 (RCM_SSRS0) 8 R/W 82h 14.2.6/318 4007_F009 Sticky System Reset Status Register 1 (RCM_SSRS1) 8 R/W 00h 14.2.7/319 14.2.1 System Reset Status Register 0 (RCM_SRS0) This register includes read-only status flags to indicate the source of the most recent reset. The reset state of these bits depends on what caused the MCU to reset. NOTE The reset value of this register depends on the reset source: * POR (including LVD) -- 0x82 * LVD (without POR) -- 0x02 * VLLS mode wakeup due to RESET pin assertion -- 0x41 * VLLS mode wakeup due to other wakeup sources -- 0x01 * Other reset -- a bit is set if its corresponding reset source caused the reset Address: 4007_F000h base + 0h offset = 4007_F000h Bit Read 7 6 5 4 3 2 1 0 POR PIN WDOG 0 LOL LOC LVD WAKEUP 1 0 0 0 0 0 1 0 Write Reset RCM_SRS0 field descriptions Field 7 POR Description Power-On Reset Indicates a reset has been caused by the power-on detection logic. Because the internal supply voltage was ramping up at the time, the low-voltage reset (LVD) status bit is also set to indicate that the reset occurred while the internal supply was below the LVD threshold. 0 1 6 PIN Reset not caused by POR Reset caused by POR External Reset Pin Indicates a reset has been caused by an active-low level on the external RESET pin. 0 1 Reset not caused by external reset pin Reset caused by external reset pin Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 312 Freescale Semiconductor, Inc. Chapter 14 Reset Control Module (RCM) RCM_SRS0 field descriptions (continued) Field 5 WDOG Description Watchdog Indicates a reset has been caused by the watchdog timer timing out. This reset source can be blocked by disabling the watchdog. 0 1 4 Reserved 3 LOL This field is reserved. This read-only field is reserved and always has the value 0. Loss-of-Lock Reset Indicates a reset has been caused by a loss of lock in the MCG PLL. See the MCG description for information on the loss-of-clock event. 0 1 2 LOC Indicates a reset has been caused by a loss of external clock. The MCG clock monitor must be enabled for a loss of clock to be detected. Refer to the detailed MCG description for information on enabling the clock monitor. Reset not caused by a loss of external clock. Reset caused by a loss of external clock. Low-Voltage Detect Reset If PMC_LVDSC1[LVDRE] is set and the supply drops below the LVD trip voltage, an LVD reset occurs. This field is also set by POR. 0 1 0 WAKEUP Reset not caused by a loss of lock in the PLL Reset caused by a loss of lock in the PLL Loss-of-Clock Reset 0 1 1 LVD Reset not caused by watchdog timeout Reset caused by watchdog timeout Reset not caused by LVD trip or POR Reset caused by LVD trip or POR Low Leakage Wakeup Reset Indicates a reset has been caused by an enabled LLWU module wakeup source while the chip was in a low leakage mode. In LLS mode, the RESET pin is the only wakeup source that can cause this reset. Any enabled wakeup source in a VLLSx mode causes a reset. This bit is cleared by any reset except WAKEUP. 0 1 Reset not caused by LLWU module wakeup source Reset caused by LLWU module wakeup source 14.2.2 System Reset Status Register 1 (RCM_SRS1) This register includes read-only status flags to indicate the source of the most recent reset. The reset state of these bits depends on what caused the MCU to reset. NOTE The reset value of this register depends on the reset source: * POR (including LVD) -- 0x00 KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 313 Reset memory map and register descriptions * LVD (without POR) -- 0x00 * VLLS mode wakeup -- 0x00 * Other reset -- a bit is set if its corresponding reset source caused the reset Address: 4007_F000h base + 1h offset = 4007_F001h Bit 7 6 5 4 3 2 1 0 Read 0 0 SACKERR EZPT MDM_AP SW LOCKUP JTAG 0 0 0 0 0 0 0 0 Write Reset RCM_SRS1 field descriptions Field Description 7 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 6 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 5 SACKERR Stop Mode Acknowledge Error Reset Indicates that after an attempt to enter Stop mode, a reset has been caused by a failure of one or more peripherals to acknowledge within approximately one second to enter stop mode. 0 1 4 EZPT EzPort Reset Indicates a reset has been caused by EzPort receiving the RESET command while the device is in EzPort mode. 0 1 3 MDM_AP Indicates a reset has been caused by the host debugger system setting of the System Reset Request bit in the MDM-AP Control Register. Reset not caused by host debugger system setting of the System Reset Request bit Reset caused by host debugger system setting of the System Reset Request bit Software Indicates a reset has been caused by software setting of SYSRESETREQ bit in Application Interrupt and Reset Control Register in the ARM core. 0 1 1 LOCKUP Reset not caused by EzPort receiving the RESET command while the device is in EzPort mode Reset caused by EzPort receiving the RESET command while the device is in EzPort mode MDM-AP System Reset Request 0 1 2 SW Reset not caused by peripheral failure to acknowledge attempt to enter stop mode Reset caused by peripheral failure to acknowledge attempt to enter stop mode Reset not caused by software setting of SYSRESETREQ bit Reset caused by software setting of SYSRESETREQ bit Core Lockup Indicates a reset has been caused by the ARM core indication of a LOCKUP event. 0 1 Reset not caused by core LOCKUP event Reset caused by core LOCKUP event Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 314 Freescale Semiconductor, Inc. Chapter 14 Reset Control Module (RCM) RCM_SRS1 field descriptions (continued) Field 0 JTAG Description JTAG Generated Reset Indicates a reset has been caused by JTAG selection of certain IR codes: EZPORT, EXTEST, HIGHZ, and CLAMP. 0 1 Reset not caused by JTAG Reset caused by JTAG 14.2.3 Reset Pin Filter Control register (RCM_RPFC) NOTE The reset values of bits 2-0 are for Chip POR only. They are unaffected by other reset types. NOTE The bus clock filter is reset when disabled or when entering stop mode. The LPO filter is reset when disabled . Address: 4007_F000h base + 4h offset = 4007_F004h Bit Read Write Reset 7 6 5 4 3 0 0 0 0 2 RSTFLTSS 0 0 0 1 0 RSTFLTSRW 0 0 RCM_RPFC field descriptions Field 7-3 Reserved 2 RSTFLTSS Description This field is reserved. This read-only field is reserved and always has the value 0. Reset Pin Filter Select in Stop Mode Selects how the reset pin filter is enabled in Stop and VLPS modes , and also during LLS and VLLS modes. On exit from VLLS mode, this bit should be reconfigured before clearing PMC_REGSC[ACKISO]. 0 1 RSTFLTSRW All filtering disabled LPO clock filter enabled Reset Pin Filter Select in Run and Wait Modes Selects how the reset pin filter is enabled in run and wait modes. 00 01 10 11 All filtering disabled Bus clock filter enabled for normal operation LPO clock filter enabled for normal operation Reserved KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 315 Reset memory map and register descriptions 14.2.4 Reset Pin Filter Width register (RCM_RPFW) NOTE The reset values of the bits in the RSTFLTSEL field are for Chip POR only. They are unaffected by other reset types. Address: 4007_F000h base + 5h offset = 4007_F005h Bit Read Write Reset 7 6 5 4 3 0 0 0 2 1 0 0 0 RSTFLTSEL 0 0 0 0 RCM_RPFW field descriptions Field 7-5 Reserved RSTFLTSEL Description This field is reserved. This read-only field is reserved and always has the value 0. Reset Pin Filter Bus Clock Select Selects the reset pin bus clock filter width. 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 Bus clock filter count is 1 Bus clock filter count is 2 Bus clock filter count is 3 Bus clock filter count is 4 Bus clock filter count is 5 Bus clock filter count is 6 Bus clock filter count is 7 Bus clock filter count is 8 Bus clock filter count is 9 Bus clock filter count is 10 Bus clock filter count is 11 Bus clock filter count is 12 Bus clock filter count is 13 Bus clock filter count is 14 Bus clock filter count is 15 Bus clock filter count is 16 Bus clock filter count is 17 Bus clock filter count is 18 Bus clock filter count is 19 Bus clock filter count is 20 Bus clock filter count is 21 Bus clock filter count is 22 Bus clock filter count is 23 Bus clock filter count is 24 Bus clock filter count is 25 Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 316 Freescale Semiconductor, Inc. Chapter 14 Reset Control Module (RCM) RCM_RPFW field descriptions (continued) Field Description 11001 11010 11011 11100 11101 11110 11111 Bus clock filter count is 26 Bus clock filter count is 27 Bus clock filter count is 28 Bus clock filter count is 29 Bus clock filter count is 30 Bus clock filter count is 31 Bus clock filter count is 32 14.2.5 Mode Register (RCM_MR) This register includes read-only status flags to indicate the state of the mode pins during the last Chip Reset. Address: 4007_F000h base + 7h offset = 4007_F007h Bit 7 6 5 Read 4 3 2 0 1 0 EZP_MS 0 0 0 Write Reset 0 0 0 0 0 0 RCM_MR field descriptions Field Description 7-2 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 1 EZP_MS EZP_MS_B pin state Reflects the state of the EZP_MS pin during the last Chip Reset 0 1 0 Reserved Pin deasserted (logic 1) Pin asserted (logic 0) This field is reserved. This read-only field is reserved and always has the value 0. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 317 Reset memory map and register descriptions 14.2.6 Sticky System Reset Status Register 0 (RCM_SSRS0) This register includes status flags to indicate all reset sources since the last POR, LVD or VLLS Wakeup that have not been cleared by software. Software can clear the status flags by writing a logic one to a flag. Address: 4007_F000h base + 8h offset = 4007_F008h Bit 7 6 5 4 3 2 1 0 Read SPOR SPIN SWDOG 0 SLOL SLOC SLVD SWAKEUP Write w1c w1c w1c w1c w1c w1c w1c Reset 1 0 0 0 0 1 0 0 RCM_SSRS0 field descriptions Field 7 SPOR Description Sticky Power-On Reset Indicates a reset has been caused by the power-on detection logic. Because the internal supply voltage was ramping up at the time, the low-voltage reset (LVD) status bit is also set to indicate that the reset occurred while the internal supply was below the LVD threshold. 0 1 6 SPIN Sticky External Reset Pin Indicates a reset has been caused by an active-low level on the external RESET pin. 0 1 5 SWDOG 3 SLOL Indicates a reset has been caused by the watchdog timer timing out.This reset source can be blocked by disabling the watchdog. Reset not caused by watchdog timeout Reset caused by watchdog timeout This field is reserved. This read-only field is reserved and always has the value 0. Sticky Loss-of-Lock Reset Indicates a reset has been caused by a loss of lock in the MCG PLL. See the MCG description for information on the loss-of-clock event. 0 1 2 SLOC Reset not caused by external reset pin Reset caused by external reset pin Sticky Watchdog 0 1 4 Reserved Reset not caused by POR Reset caused by POR Reset not caused by a loss of lock in the PLL Reset caused by a loss of lock in the PLL Sticky Loss-of-Clock Reset Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 318 Freescale Semiconductor, Inc. Chapter 14 Reset Control Module (RCM) RCM_SSRS0 field descriptions (continued) Field Description Indicates a reset has been caused by a loss of external clock. The MCG clock monitor must be enabled for a loss of clock to be detected. Refer to the detailed MCG description for information on enabling the clock monitor. 0 1 1 SLVD Sticky Low-Voltage Detect Reset If PMC_LVDSC1[LVDRE] is set and the supply drops below the LVD trip voltage, an LVD reset occurs. This field is also set by POR. 0 1 0 SWAKEUP Reset not caused by a loss of external clock. Reset caused by a loss of external clock. Reset not caused by LVD trip or POR Reset caused by LVD trip or POR Sticky Low Leakage Wakeup Reset Indicates a reset has been caused by an enabled LLWU modulewakeup source while the chip was in a low leakage mode. In LLS mode, the RESET pin is the only wakeup source that can cause this reset. Any enabled wakeup source in a VLLSx mode causes a reset. 0 1 Reset not caused by LLWU module wakeup source Reset caused by LLWU module wakeup source 14.2.7 Sticky System Reset Status Register 1 (RCM_SSRS1) This register includes status flags to indicate all reset sources since the last POR, LVD or VLLS Wakeup that have not been cleared by software. Software can clear the status flags by writing a logic one to a flag. Address: 4007_F000h base + 9h offset = 4007_F009h Bit 7 6 5 4 3 2 1 0 Read 0 0 SSACKERR SEZPT SMDM_AP SSW SLOCKUP SJTAG w1c w1c w1c w1c w1c w1c 0 0 0 0 0 0 Write Reset 0 0 RCM_SSRS1 field descriptions Field Description 7 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 6 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 5 SSACKERR Sticky Stop Mode Acknowledge Error Reset Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 319 Reset memory map and register descriptions RCM_SSRS1 field descriptions (continued) Field Description Indicates that after an attempt to enter Stop mode, a reset has been caused by a failure of one or more peripherals to acknowledge within approximately one second to enter stop mode. 0 1 4 SEZPT Sticky EzPort Reset Indicates a reset has been caused by EzPort receiving the RESET command while the device is in EzPort mode. 0 1 3 SMDM_AP Indicates a reset has been caused by the host debugger system setting of the System Reset Request bit in the MDM-AP Control Register. Indicates a reset has been caused by software setting of SYSRESETREQ bit in Application Interrupt and Reset Control Register in the ARM core. Reset not caused by software setting of SYSRESETREQ bit Reset caused by software setting of SYSRESETREQ bit Sticky Core Lockup Indicates a reset has been caused by the ARM core indication of a LOCKUP event. 0 1 0 SJTAG Reset not caused by host debugger system setting of the System Reset Request bit Reset caused by host debugger system setting of the System Reset Request bit Sticky Software 0 1 1 SLOCKUP Reset not caused by EzPort receiving the RESET command while the device is in EzPort mode Reset caused by EzPort receiving the RESET command while the device is in EzPort mode Sticky MDM-AP System Reset Request 0 1 2 SSW Reset not caused by peripheral failure to acknowledge attempt to enter stop mode Reset caused by peripheral failure to acknowledge attempt to enter stop mode Reset not caused by core LOCKUP event Reset caused by core LOCKUP event Sticky JTAG Generated Reset Indicates a reset has been caused by JTAG selection of certain IR codes: EZPORT, EXTEST, HIGHZ, and CLAMP. 0 1 Reset not caused by JTAG Reset caused by JTAG KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 320 Freescale Semiconductor, Inc. Chapter 15 System Mode Controller (SMC) 15.1 Introduction NOTE For the chip-specific implementation details of this module's instances, see the chip configuration information. The System Mode Controller (SMC) is responsible for sequencing the system into and out of all low-power Stop and Run modes. Specifically, it monitors events to trigger transitions between power modes while controlling the power, clocks, and memories of the system to achieve the power consumption and functionality of that mode. This chapter describes all the available low-power modes, the sequence followed to enter/ exit each mode, and the functionality available while in each of the modes. The SMC is able to function during even the deepest low power modes. See AN4503: Power Management for Kinetis MCUs for further details on using the SMC. 15.2 Modes of operation The ARM CPU has three primary modes of operation: * Run * Sleep * Deep Sleep The WFI or WFE instruction is used to invoke Sleep and Deep Sleep modes. Run, Wait, and Stop are the common terms used for the primary operating modes of Freescale microcontrollers. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 321 Modes of operation The following table shows the translation between the ARM CPU modes and the Freescale MCU power modes. ARM CPU mode MCU mode Sleep Wait Deep Sleep Stop Accordingly, the ARM CPU documentation refers to sleep and deep sleep, while the Freescale MCU documentation normally uses wait and stop. In addition, Freescale MCUs also augment Stop, Wait, and Run modes in a number of ways. The power management controller (PMC) contains a run and a stop mode regulator. Run regulation is used in normal run, wait and stop modes. Stop mode regulation is used during all very low power and low leakage modes. During stop mode regulation, the bus frequencies are limited in the very low power modes. The SMC provides the user with multiple power options. The Very Low Power Run (VLPR) mode can drastically reduce run time power when maximum bus frequency is not required to handle the application needs. From Normal Run mode, the Run Mode (RUNM) field can be modified to change the MCU into VLPR mode when limited frequency is sufficient for the application. From VLPR mode, a corresponding wait (VLPW) and stop (VLPS) mode can be entered. Depending on the needs of the user application, a variety of stop modes are available that allow the state retention, partial power down or full power down of certain logic and/or memory. I/O states are held in all modes of operation. Several registers are used to configure the various modes of operation for the device. The following table describes the power modes available for the device. Table 15-1. Power modes Mode Description RUN The MCU can be run at full speed and the internal supply is fully regulated, that is, in run regulation. This mode is also referred to as Normal Run mode. HSRUN The MCU can be run at a faster frequency compared with RUN mode and the internal supply is fully regulated. See the Power Management chapter for details about the maximum allowable frequencies. WAIT The core clock is gated off. The system clock continues to operate. Bus clocks, if enabled, continue to operate. Run regulation is maintained. STOP The core clock is gated off. System clocks to other masters and bus clocks are gated off after all stop acknowledge signals from supporting peripherals are valid. VLPR The core, system, bus, and flash clock maximum frequencies are restricted in this mode. See the Power Management chapter for details about the maximum allowable frequencies. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 322 Freescale Semiconductor, Inc. Chapter 15 System Mode Controller (SMC) Table 15-1. Power modes (continued) Mode Description VLPW The core clock is gated off. The system, bus, and flash clocks continue to operate, although their maximum frequency is restricted. See the Power Management chapter for details on the maximum allowable frequencies. VLPS The core clock is gated off. System clocks to other masters and bus clocks are gated off after all stop acknowledge signals from supporting peripherals are valid. LLS3 The core clock is gated off. System clocks to other masters and bus clocks are gated off after all stop acknowledge signals from supporting peripherals are valid. The MCU is placed in a low leakage mode by reducing the voltage to internal logic. All system RAM contents, internal logic and I/O states are retained. LLS2 The core clock is gated off. System clocks to other masters and bus clocks are gated off after all stop acknowledge signals from supporting peripherals are valid. The MCU is placed in a low leakage mode by reducing voltage to internal logicand powering down the system RAM2 partition. The system RAM1 partition, internal logic and I/O states are retained.1 VLLS3 The core clock is gated off. System clocks to other masters and bus clocks are gated off after all stop acknowledge signals from supporting peripherals are valid. The MCU is placed in a low leakage mode by powering down the internal logic. All system RAM contents are retained and I/O states are held. Internal logic states are not retained. VLLS2 The core clock is gated off. System clocks to other masters and bus clocks are gated off after all stop acknowledge signals from supporting peripherals are valid. The MCU is placed in a low leakage mode by powering down the internal logic and the system RAM2 partition. The system RAM1 partition contents are retained in this mode. Internal logic states are not retained. 1 VLLS1 The core clock is gated off. System clocks to other masters and bus clocks are gated off after all stop acknowledge signals from supporting peripherals are valid. The MCU is placed in a low leakage mode by powering down the internal logic and all system RAM. I/O states are held. Internal logic states are not retained. VLLS0 The core clock is gated off. System clocks to other masters and bus clocks are gated off after all stop acknowledge signals from supporting peripherals are valid. The MCU is placed in a low leakage mode by powering down the internal logic and all system RAM. I/O states are held. Internal logic states are not retained. The 1kHz LPO clock is disabled and the power on reset (POR) circuit can be optionally enabled using STOPCTRL[PORPO]. 1. See the devices' chip configuration details for the size and location of the system RAM partitions. 15.3 Memory map and register descriptions Information about the registers related to the system mode controller can be found here. Different SMC registers reset on different reset types. Each register's description provides details. For more information about the types of reset on this chip, refer to the Reset section details. NOTE The SMC registers can be written only in supervisor mode. Write accesses in user mode are blocked and will result in a bus error. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 323 Memory map and register descriptions NOTE Before executing the WFI instruction, the last register written to must be read back. This ensures that all register writes associated with setting up the low power mode being entered have completed before the MCU enters the low power mode. Failure to do this may result in the low power mode not being entered correctly. SMC memory map Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 4007_E000 Power Mode Protection register (SMC_PMPROT) 8 R/W 00h 15.3.1/324 4007_E001 Power Mode Control register (SMC_PMCTRL) 8 R/W 00h 15.3.2/325 4007_E002 Stop Control Register (SMC_STOPCTRL) 8 R/W 03h 15.3.3/327 4007_E003 Power Mode Status register (SMC_PMSTAT) 8 R 01h 15.3.4/328 15.3.1 Power Mode Protection register (SMC_PMPROT) This register provides protection for entry into any low-power run or stop mode. The enabling of the low-power run or stop mode occurs by configuring the Power Mode Control register (PMCTRL). The PMPROT register can be written only once after any system reset. If the MCU is configured for a disallowed or reserved power mode, the MCU remains in its current power mode. For example, if the MCU is in normal RUN mode and AVLP is 0, an attempt to enter VLPR mode using PMCTRL[RUNM] is blocked and PMCTRL[RUNM] remains 00b, indicating the MCU is still in Normal Run mode. NOTE This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See the Reset section details for more information. Address: 4007_E000h base + 0h offset = 4007_E000h Bit Read Write Reset 7 6 5 4 3 2 1 0 AHSRUN 0 AVLP 0 ALLS 0 AVLLS 0 0 0 0 0 0 0 0 0 KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 324 Freescale Semiconductor, Inc. Chapter 15 System Mode Controller (SMC) SMC_PMPROT field descriptions Field 7 AHSRUN Description Allow High Speed Run mode Provided the appropriate control bits are set up in PMCTRL, this write-once field allows the MCU to enter High Speed Run mode (HSRUN). 0 1 6 Reserved 5 AVLP This field is reserved. This read-only field is reserved and always has the value 0. Allow Very-Low-Power Modes Provided the appropriate control bits are set up in PMCTRL, this write-once field allows the MCU to enter any very-low-power mode (VLPR, VLPW, and VLPS). 0 1 4 Reserved 3 ALLS 1 AVLLS Allow Low-Leakage Stop Mode Provided the appropriate control bits are set up in PMCTRL, this write-once field allows the MCU to enter any low-leakage stop mode (LLS). Any LLSx mode is not allowed Any LLSx mode is allowed This field is reserved. This read-only field is reserved and always has the value 0. Allow Very-Low-Leakage Stop Mode Provided the appropriate control bits are set up in PMCTRL, this write once bit allows the MCU to enter any very-low-leakage stop mode (VLLSx). 0 1 0 Reserved VLPR, VLPW, and VLPS are not allowed. VLPR, VLPW, and VLPS are allowed. This field is reserved. This read-only field is reserved and always has the value 0. 0 1 2 Reserved HSRUN is not allowed HSRUN is allowed Any VLLSx mode is not allowed Any VLLSx mode is allowed This field is reserved. This read-only field is reserved and always has the value 0. 15.3.2 Power Mode Control register (SMC_PMCTRL) The PMCTRL register controls entry into low-power Run and Stop modes, provided that the selected power mode is allowed via an appropriate setting of the protection (PMPROT) register. NOTE This register is reset on Chip POR not VLLS and by reset types that trigger Chip POR not VLLS. It is unaffected by reset types KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 325 Memory map and register descriptions that do not trigger Chip POR not VLLS. See the Reset section details for more information. Address: 4007_E000h base + 1h offset = 4007_E001h Bit Read Write Reset 7 6 Reserved 5 RUNM 0 0 0 4 3 0 STOPA 0 0 2 1 0 STOPM 0 0 0 SMC_PMCTRL field descriptions Field 7 Reserved 6-5 RUNM Description This field is reserved. This bit is reserved for future expansion and should always be written zero. Run Mode Control When written, causes entry into the selected run mode. Writes to this field are blocked if the protection level has not been enabled using the PMPROT register. NOTE: RUNM may be set to VLPR only when PMSTAT=RUN. After being written to VLPR, RUNM should not be written back to RUN until PMSTAT=VLPR. NOTE: RUNM may be set to HSRUN only when PMSTAT=RUN. After being programmed to HSRUN, RUNM should not be programmed back to RUN until PMSTAT=HSRUN. Also, stop mode entry should not be attempted while RUNM=HSRUN or PMSTAT=HSRUN. 00 01 10 11 4 Reserved 3 STOPA This field is reserved. This read-only field is reserved and always has the value 0. Stop Aborted When set, this read-only status bit indicates an interrupt occured during the previous stop mode entry sequence, preventing the system from entering that mode. This field is cleared by reset or by hardware at the beginning of any stop mode entry sequence and is set if the sequence was aborted. 0 1 STOPM Normal Run mode (RUN) Reserved Very-Low-Power Run mode (VLPR) High Speed Run mode (HSRUN) The previous stop mode entry was successful. The previous stop mode entry was aborted. Stop Mode Control When written, controls entry into the selected stop mode when Sleep-Now or Sleep-On-Exit mode is entered with SLEEPDEEP=1 . Writes to this field are blocked if the protection level has not been enabled using the PMPROT register. After any system reset, this field is cleared by hardware on any successful write to the PMPROT register. NOTE: When set to VLLSxor LLSx, the LLSM in the STOPCTRL register is used to further select the particular VLLSor LLS submode which will be entered. NOTE: When set to STOP, the PSTOPO bits in the STOPCTRL register can be used to select a Partial Stop mode if desired. 000 Normal Stop (STOP) Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 326 Freescale Semiconductor, Inc. Chapter 15 System Mode Controller (SMC) SMC_PMCTRL field descriptions (continued) Field Description 001 010 011 100 101 110 111 Reserved Very-Low-Power Stop (VLPS) Low-Leakage Stop (LLSx) Very-Low-Leakage Stop (VLLSx) Reserved Reseved Reserved 15.3.3 Stop Control Register (SMC_STOPCTRL) The STOPCTRL register provides various control bits allowing the user to fine tune power consumption during the stop mode selected by the STOPM field. NOTE This register is reset on Chip POR not VLLS and by reset types that trigger Chip POR not VLLS. It is unaffected by reset types that do not trigger Chip POR not VLLS. See the Reset section details for more information. Address: 4007_E000h base + 2h offset = 4007_E002h Bit Read Write Reset 7 6 5 PSTOPO 0 0 4 3 PORPO 0 Reserved 0 0 0 2 1 0 LLSM 0 1 1 SMC_STOPCTRL field descriptions Field 7-6 PSTOPO Description Partial Stop Option These bits control whether a Partial Stop mode is entered when STOPM=STOP. When entering a Partial Stop mode from RUN (or VLPR) mode, the PMC, MCG and flash remain fully powered, allowing the device to wakeup almost instantaneously at the expense of higher power consumption. In PSTOP2, only system clocks are gated allowing peripherals running on bus clock to remain fully functional. In PSTOP1, both system and bus clocks are gated. 00 01 10 11 5 PORPO STOP - Normal Stop mode PSTOP1 - Partial Stop with both system and bus clocks disabled PSTOP2 - Partial Stop with system clock disabled and bus clock enabled Reserved POR Power Option This bit controls whether the POR detect circuit is enabled in VLLS0 mode. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 327 Memory map and register descriptions SMC_STOPCTRL field descriptions (continued) Field Description 0 1 POR detect circuit is enabled in VLLS0 POR detect circuit is disabled in VLLS0 4 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 3 Reserved This field is reserved. This bit is reserved for future expansion and should always be written zero. LLSM LLS or VLLS Mode Control This field controls which LLS orVLLS sub-mode to enter if STOPM = LLSx orVLLSx. 000 001 010 011 100 101 110 111 VLLS0 if PMCTRL[STOPM]=VLLSx, reserved if PMCTRL[STOPM]=LLSx VLLS1 if PMCTRL[STOPM]=VLLSx, reserved if PMCTRL[STOPM]=LLSx VLLS2 if PMCTRL[STOPM]=VLLSx, LLS2 if PMCTRL[STOPM]=LLSx VLLS3 if PMCTRL[STOPM]=VLLSx, LLS3 if PMCTRL[STOPM]=LLSx Reserved Reserved Reserved Reserved 15.3.4 Power Mode Status register (SMC_PMSTAT) PMSTAT is a read-only, one-hot register which indicates the current power mode of the system. NOTE This register is reset on Chip POR not VLLS and by reset types that trigger Chip POR not VLLS. It is unaffected by reset types that do not trigger Chip POR not VLLS. See the Reset section details for more information. Address: 4007_E000h base + 3h offset = 4007_E003h Bit 7 6 5 4 Read 3 2 1 0 0 0 0 1 PMSTAT Write Reset 0 0 0 0 SMC_PMSTAT field descriptions Field PMSTAT Description Power Mode Status NOTE: When debug is enabled, the PMSTAT will not update to STOP or VLPS KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 328 Freescale Semiconductor, Inc. Chapter 15 System Mode Controller (SMC) SMC_PMSTAT field descriptions (continued) Field Description NOTE: When a PSTOP mode is enabled, the PMSTAT will not update to STOP or VLPS 0000_0001 0000_0010 0000_0100 0000_1000 0001_0000 0010_0000 0100_0000 1000_0000 Current power mode is RUN. Current power mode is STOP. Current power mode is VLPR. Current power mode is VLPW. Current power mode is VLPS. Current power mode is LLS. Current power mode is VLLS. Current power mode is HSRUN 15.4 Functional description 15.4.1 Power mode transitions The following figure shows the power mode state transitions available on the chip. Any reset always brings the MCU back to the normal RUN state. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 329 Functional description Any RESET VLPW HSRUN 4 5 12 VLPR WAIT 1 3 RUN 7 2 STOP 6 VLPS 10 8 9 LLS VLLS 11 Figure 15-1. Power mode state diagram The following table defines triggers for the various state transitions shown in the previous figure. Table 15-2. Power mode transition triggers Transition # From To 1 RUN WAIT Trigger conditions Sleep-now or sleep-on-exit modes entered with SLEEPDEEP clear, controlled in System Control Register in ARM core. See note.1 2 WAIT RUN Interrupt or Reset RUN STOP PMCTRL[RUNM]=00, PMCTRL[STOPM]=0002 Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 330 Freescale Semiconductor, Inc. Chapter 15 System Mode Controller (SMC) Table 15-2. Power mode transition triggers (continued) Transition # From To Trigger conditions Sleep-now or sleep-on-exit modes entered with SLEEPDEEP set, which is controlled in System Control Register in ARM core. See note.1 3 STOP RUN Interrupt or Reset RUN VLPR The core, system, bus and flash clock frequencies and MCG clocking mode are restricted in this mode. See the Power Management chapter for the maximum allowable frequencies and MCG modes supported. VLPR RUN VLPR VLPW Set PMPROT[AVLP]=1, PMCTRL[RUNM]=10. Set PMCTRL[RUNM]=00 or Reset. 4 Sleep-now or sleep-on-exit modes entered with SLEEPDEEP clear, which is controlled in System Control Register in ARM core. See note.1 VLPW VLPR Interrupt 5 VLPW RUN Reset 6 VLPR VLPS PMCTRL[STOPM]=0003 or 010, Sleep-now or sleep-on-exit modes entered with SLEEPDEEP set, which is controlled in System Control Register in ARM core. See note.1 VLPS VLPR Interrupt NOTE: If VLPS was entered directly from RUN (transition #7), hardware forces exit back to RUN and does not allow a transition to VLPR. 7 RUN VLPS PMPROT[AVLP]=1, PMCTRL[STOPM]=010, Sleep-now or sleep-on-exit modes entered with SLEEPDEEP set, which is controlled in System Control Register in ARM core. See note.1 VLPS RUN Interrupt and VLPS mode was entered directly from RUN or Reset 8 9 RUN VLLSx VLLSx RUN VLPR VLLSx PMPROT[AVLLS]=1, PMCTRL[STOPM]=100, STOPCTRL[LLSM]=x (VLLSx), Sleep-now or sleep-on-exit modes entered with SLEEPDEEP set, which is controlled in System Control Register in ARM core. Wakeup from enabled LLWU input source or RESET pin PMPROT[AVLLS]=1, PMCTRL[STOPM]=100, STOPCTRL[LLSM]=x (VLLSx), Sleep-now or sleep-on-exit modes entered with SLEEPDEEP set, which is controlled in System Control Register in ARM core. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 331 Functional description Table 15-2. Power mode transition triggers (continued) Transition # From To Trigger conditions 10 RUN LLSx PMPROT[ALLS]=1, PMCTRL[STOPM]=011, STOPCTRL[LLSM]=x (LLSx), Sleep-now or sleep-on-exit modes entered with SLEEPDEEP set, which is controlled in System Control Register in ARM core. LLSx RUN Wakeup from enabled LLWU input source and LLSx mode was entered directly from RUN or RESET pin. 11 VLPR LLSx PMPROT[ALLS]=1, PMCTRL[STOPM]=011, Sleep-now or sleep-on-exit modes entered with SLEEPDEEP set, which is controlled in System Control Register in ARM core. LLSx VLPR Wakeup from enabled LLWU input source and LLSx mode was entered directly from VLPR NOTE: If LLSx was entered directly from RUN, hardware will not allow this transition and will force exit back to RUN 12 RUN HSRUN HSRUN RUN Set PMPROT[AHSRUN]=1, PMCTRL[RUNM]=11. Set PMCTRL[RUNM]=00 or Reset 1. If debug is enabled, the core clock remains to support debug. 2. If PMCTRL[STOPM]=000 and STOPCTRL[PSTOPO]=01 or 10, then only a Partial Stop mode is entered instead of STOP 3. If PMCTRL[STOPM]=000 and STOPCTRL[PSTOPO]=00, then VLPS mode is entered instead of STOP. If PMCTRL[STOPM]=000 and STOPCTRL[PSTOPO]=01 or 10, then only a Partial Stop mode is entered instead of VLPS 15.4.2 Power mode entry/exit sequencing When entering or exiting low-power modes, the system must conform to an orderly sequence to manage transitions safely. The SMC manages the system's entry into and exit from all power modes. This diagram illustrates the connections of the SMC with other system components in the chip that are necessary to sequence the system through all power modes. Figure 15-2. Low-power system components and connections 15.4.2.1 Stop mode entry sequence Entry into a low-power stop mode (Stop, VLPS, LLS, VLLSx) is initiated by a CPU executing the WFI instruction. After the instruction is executed, the following sequence occurs: 1. The CPU clock is gated off immediately. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 332 Freescale Semiconductor, Inc. Chapter 15 System Mode Controller (SMC) 2. Requests are made to all non-CPU bus masters to enter Stop mode. 3. After all masters have acknowledged they are ready to enter Stop mode, requests are made to all bus slaves to enter Stop mode. 4. After all slaves have acknowledged they are ready to enter Stop mode, all system and bus clocks are gated off. 5. Clock generators are disabled in the MCG. 6. The on-chip regulator in the PMC and internal power switches are configured to meet the power consumption goals for the targeted low-power mode. 15.4.2.2 Stop mode exit sequence Exit from a low-power stop mode is initiated either by a reset or an interrupt event. The following sequence then executes to restore the system to a run mode (RUN or VLPR): 1. The on-chip regulator in the PMC and internal power switches are restored. 2. Clock generators are enabled in the MCG. 3. System and bus clocks are enabled to all masters and slaves. 4. The CPU clock is enabled and the CPU begins servicing the reset or interrupt that initiated the exit from the low-power stop mode. 15.4.2.3 Aborted stop mode entry If an interrupt occurs during a stop entry sequence, the SMC can abort the transition early and return to RUN mode without completely entering the stop mode. An aborted entry is possible only if the interrupt occurs before the PMC begins the transition to stop mode regulation. After this point, the interrupt is ignored until the PMC has completed its transition to stop mode regulation. When an aborted stop mode entry sequence occurs, SMC_PMCTRL[STOPA] is set to 1. 15.4.2.4 Transition to wait modes For wait modes (WAIT and VLPW), the CPU clock is gated off while all other clocking continues, as in RUN and VLPR mode operation. Some modules that support stop-inwait functionality have their clocks disabled in these configurations. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 333 Functional description 15.4.2.5 Transition from stop modes to Debug mode The debugger module supports a transition from STOP, WAIT, VLPS, and VLPW back to a Halted state when the debugger has been enabled. As part of this transition, system clocking is re-established and is equivalent to the normal RUN and VLPR mode clocking configuration. 15.4.3 Run modes The run modes supported by this device can be found here. * Run (RUN) * Very Low-Power Run (VLPR) * High Speed Run (HSRUN) 15.4.3.1 RUN mode This is the normal operating mode for the device. This mode is selected after any reset. When the ARM processor exits reset, it sets up the stack, program counter (PC), and link register (LR): * The processor reads the start SP (SP_main) from vector-table offset 0x000 * The processor reads the start PC from vector-table offset 0x004 * LR is set to 0xFFFF_FFFF. To reduce power in this mode, disable the clocks to unused modules using their corresponding clock gating control bits in the SIM's (or PCC's) registers. 15.4.3.2 Very-Low Power Run (VLPR) mode In VLPR mode, the on-chip voltage regulator is put into a stop mode regulation state. In this state, the regulator is designed to supply enough current to the MCU over a reduced frequency. To further reduce power in this mode, disable the clocks to unused modules using their corresponding clock gating control bits in the SIM's registers. Before entering this mode, the following conditions must be met: * The MCG must be configured in a mode which is supported during VLPR. See the Power Management details for information about these MCG modes. * All clock monitors in the MCG must be disabled. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 334 Freescale Semiconductor, Inc. Chapter 15 System Mode Controller (SMC) * The maximum frequencies of the system, bus, flash, and core are restricted. See the Power Management details about which frequencies are supported. * Mode protection must be set to allow VLP modes, that is, PMPROT[AVLP] is 1. * PMCTRL[RUNM] must be set to 10b to enter VLPR. * Flash programming/erasing is not allowed. NOTE Do not increase the clock frequency while in VLPR mode, because the regulator is slow in responding and cannot manage fast load transitions. In addition, do not modify the clock source in the MCG module or any clock divider registers. Module clock enables in the SIM can be set, but not cleared. To reenter Normal Run mode, clear PMCTRL[RUNM]. PMSTAT is a read-only status register that can be used to determine when the system has completed an exit to RUN mode. When PMSTAT=RUN, the system is in run regulation and the MCU can run at full speed in any clock mode. If a higher execution frequency is desired, poll PMSTAT until it is set to RUN when returning from VLPR mode. Any reset always causes an exit from VLPR and returns the device to RUN mode after the MCU exits its reset flow. 15.4.3.3 High Speed Run (HSRUN) mode In HSRUN mode, the on-chip voltage regulator remains in a run regulation state, but with a slightly elevated voltage output. In this state, the MCU is able to operate at a faster frequency compared to normal RUN mode. For the maximum allowable frequencies, see the Power Management chapter. While in this mode, the following restrictions must be adhered to: * The maximum allowable change in frequency of the system, bus, flash or core clocks is restricted to 2x (double the frequency). * Before exiting HSRUN mode, clock frequencies should be reduced back down to those acceptable in RUN mode. * Stop mode entry is not supported from HSRUN. * Modifications to clock gating control bits are prohibited. * Flash programming/erasing is not allowed. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 335 Functional description To enter HSRUN mode, set PMPORT[AHSRUN]=HSRUN and set PMCTRL[RUNM]=HSRUN. Before increasing clock frequencies, the PMSTAT register should be polled to determine when the system has completed entry into HSRUN mode. To reenter normal RUN mode, clear RUNM. Any reset will also clear RUNM and cause the system to exit to normal RUN mode after the MCU exits its reset flow. 15.4.4 Wait modes This device contains two different wait modes which are listed here. * Wait * Very-Low Power Wait (VLPW) 15.4.4.1 WAIT mode WAIT mode is entered when the ARM core enters the Sleep-Now or Sleep-On-Exit modes while SLEEPDEEP is cleared. The ARM CPU enters a low-power state in which it is not clocked, but peripherals continue to be clocked provided they are enabled. Clock gating to the peripheral is enabled via the SIM module. When an interrupt request occurs, the CPU exits WAIT mode and resumes processing in RUN mode, beginning with the stacking operations leading to the interrupt service routine. A system reset will cause an exit from WAIT mode, returning the device to normal RUN mode. 15.4.4.2 Very-Low-Power Wait (VLPW) mode VLPW is entered by the entering the Sleep-Now or Sleep-On-Exit mode while SLEEPDEEP is cleared and the MCU is in VLPR mode. In VLPW, the on-chip voltage regulator remains in its stop regulation state. In this state, the regulator is designed to supply enough current to the MCU over a reduced frequency. To further reduce power in this mode, disable the clocks to unused modules by clearing the peripherals' corresponding clock gating control bits in the SIM (or PCC). VLPR mode restrictions also apply to VLPW. When an interrupt from VLPW occurs, the device returns to VLPR mode to execute the interrupt service routine. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 336 Freescale Semiconductor, Inc. Chapter 15 System Mode Controller (SMC) A system reset will cause an exit from VLPW mode, returning the device to normal RUN mode. 15.4.5 Stop modes This device contains a variety of stop modes to meet your application needs. The stop modes range from: * a stopped CPU, with all I/O, logic, and memory states retained, and certain asynchronous mode peripherals operating to: * a powered down CPU, with only I/O and a small register file retained, very few asynchronous mode peripherals operating, while the remainder of the MCU is powered down. The choice of stop mode depends upon the user's application, and how power usage and state retention versus functional needs and recovery time may be traded off. NOTE All clock monitors must be disabled before entering these lowpower modes: Stop, VLPS, VLPR, VLPW, LLSand VLLSx. The various stop modes are selected by setting the appropriate fields in PMPROT and PMCTRL. The selected stop mode is entered during the sleep-now or sleep-on-exit entry with the SLEEPDEEP bit set in the System Control Register in the ARM core. The available stop modes are: * * * * Normal Stop (STOP) Very-Low Power Stop (VLPS) Low-Leakage Stop (LLS) Very-Low-Leakage Stop (VLLSx) 15.4.5.1 STOP mode STOP mode is entered via the sleep-now or sleep-on-exit with the SLEEPDEEP bit set in the System Control Register in the ARM core. The MCG module can be configured to leave the reference clocks running. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 337 Functional description A module capable of providing an asynchronous interrupt to the device takes the device out of STOP mode and returns the device to normal RUN mode. Refer to the device's Power Management chapter for peripheral, I/O, and memory operation in STOP mode. When an interrupt request occurs, the CPU exits STOP mode and resumes processing, beginning with the stacking operations leading to the interrupt service routine. A system reset will cause an exit from STOP mode, returning the device to normal RUN mode via an MCU reset. 15.4.5.2 Very-Low-Power Stop (VLPS) mode The two ways in which VLPS mode can be entered are listed here. * Entry into stop via the sleep-now or sleep-on-exit with the SLEEPDEEP bit set in the System Control Register in the ARM core while the MCU is in VLPR mode and PMCTRL[STOPM] = 010 or 000. * Entry into stop via the sleep-now or sleep-on-exit with the SLEEPDEEP bit set in the System Control Register in the ARM core while the MCU is in normal RUN mode and PMCTRL[STOPM] = 010. When VLPS is entered directly from RUN mode, exit to VLPR is disabled by hardware and the system will always exit back to RUN. In VLPS, the on-chip voltage regulator remains in its stop regulation state as in VLPR. A module capable of providing an asynchronous interrupt to the device takes the device out of VLPS and returns the device to VLPR mode. A system reset will also cause a VLPS exit, returning the device to normal RUN mode. 15.4.5.3 Low-Leakage Stop (LLSx) modes This device contains two Low-Leakage Stop modes: LLS3 and LLS2. LLS or LLSx is often used in this document to refer to both modes. All LLS modes can be entered from normal RUN or VLPR modes. The MCU enters LLS mode if: * In Sleep-Now or Sleep-On-Exit mode, SLEEPDEEP is set in the System Control Register in the ARM core, and * The device is configured as shown in Table 15-2. In LLS, the on-chip voltage regulator is in stop regulation. Most of the peripherals are put in a state-retention mode that does not allow them to operate while in LLS. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 338 Freescale Semiconductor, Inc. Chapter 15 System Mode Controller (SMC) Before entering LLS mode, the user should configure the Low-Leakage Wake-up (LLWU) module to enable the desired wake-up sources. The available wake-up sources in LLS are detailed in the chip configuration details for this device. After wakeup from LLS, the device returns to the run mode from which LLS was entered (either normal RUN or VLPR) with a pending LLWU module interrupt. In the LLWU interrupt service routine (ISR), the user can poll the LLWU module wake-up flags to determine the source of the wakeup. NOTE The LLWU interrupt must not be masked by the interrupt controller to avoid a scenario where the system does not fully exit Stop mode on an LLS recovery. An asserted RESET pin will cause an exit from LLS mode, returning the device to normal RUN mode. When LLS is exiting via the RESET pin, RCM_SRS[PIN] and RCM_SRS[WAKEUP] are set. 15.4.5.4 Very-Low-Leakage Stop (VLLSx) modes This device contains these very low leakage modes: * * * * VLLS3 VLLS2 VLLS1 VLLS0 VLLSx is often used in this document to refer to all of these modes. All VLLSx modes can be entered from normal RUN or VLPR modes. The MCU enters the configured VLLS mode if: * In Sleep-Now or Sleep-On-Exit mode, the SLEEPDEEP bit is set in the System Control Register in the ARM core, and * The device is configured as shown in Table 15-2. In VLLS, the on-chip voltage regulator is in its stop-regulation state while most digital logic is powered off. Before entering VLLS mode, the user should configure the Low-Leakage Wake-up (LLWU) module to enable the desired wakeup sources. The available wake-up sources in VLLS are detailed in the chip configuration details for this device. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 339 Functional description After wakeup from VLLS, the device returns to normal RUN mode with a pending LLWU interrupt. In the LLWU interrupt service routine (ISR), the user can poll the LLWU module wake-up flags to determine the source of the wake-up. When entering VLLS, each I/O pin is latched as configured before executing VLLS. Because all digital logic in the MCU is powered off, all port and peripheral data is lost during VLLS. This information must be restored before PMC_REGSC[ACKISO] is set. An asserted RESET pin will cause an exit from any VLLS mode, returning the device to normal RUN mode. When exiting VLLS via the RESET pin, RCM_SRS[PIN] and RCM_SRS[WAKEUP] are set. 15.4.6 Debug in low power modes When the MCU is secure, the device disables/limits debugger operation. When the MCU is unsecure, the ARM debugger can assert two power-up request signals: * System power up, via SYSPWR in the Debug Port Control/Stat register * Debug power up, via CDBGPWRUPREQ in the Debug Port Control/Stat register When asserted while in RUN, WAIT, VLPR, or VLPW, the mode controller drives a corresponding acknowledge for each signal, that is, both CDBGPWRUPACK and CSYSPWRUPACK. When both requests are asserted, the mode controller handles attempts to enter STOP and VLPS by entering an emulated stop state. In this emulated stop state: * * * * * the regulator is in run regulation, the MCG-generated clock source is enabled, all system clocks, except the core clock, are disabled, the debug module has access to core registers, and access to the on-chip peripherals is blocked. No debug is available while the MCU is in LLS or VLLS modes. LLS is a state-retention mode and all debug operation can continue after waking from LLS, even in cases where system wakeup is due to a system reset event. Entering into a VLLS mode causes all of the debug controls and settings to be powered off. To give time to the debugger to sync with the MCU, the MDM AP Control Register includes a Very-Low-Leakage Debug Request (VLLDBGREQ) bit that is set to configure the Reset Controller logic to hold the system in reset after the next recovery from a VLLS mode. This bit allows the debugger time to reinitialize the debug module before the debug session continues. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 340 Freescale Semiconductor, Inc. Chapter 15 System Mode Controller (SMC) The MDM AP Control Register also includes a Very Low Leakage Debug Acknowledge (VLLDBGACK) bit that is set to release the ARM core being held in reset following a VLLS recovery. The debugger reinitializes all debug IP, and then asserts the VLLDBGACK control bit to allow the RCM to release the ARM core from reset and allow CPU operation to begin. The VLLDBGACK bit is cleared by the debugger (or can be left set as is) or clears automatically due to the reset generated as part of the next VLLS recovery. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 341 Functional description KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 342 Freescale Semiconductor, Inc. Chapter 16 Power Management Controller (PMC) 16.1 Introduction NOTE For the chip-specific implementation details of this module's instances, see the chip configuration information. The power management controller (PMC) contains the internal voltage regulator, power on reset (POR), and low voltage detect system (LVD). See AN4503: Power Management for Kinetis MCUs for further details on using the PMC. 16.2 Features A list of included PMC features can be found here. * Internal voltage regulator * Active POR providing brown-out detect * Low-voltage detect supporting two low-voltage trip points with four warning levels per trip point 16.3 Low-voltage detect (LVD) system This device includes a system to guard against low-voltage conditions. This protects memory contents and controls MCU system states during supply voltage variations. The system is comprised of a power-on reset (POR) circuit and a LVD circuit with a user-selectable trip voltage: high (VLVDH) or low (VLVDL). The trip voltage is selected by LVDSC1[LVDV]. The LVD is disabled upon entering VLPx, LLS, and VLLSx modes. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 343 Low-voltage detect (LVD) system Two flags are available to indicate the status of the low-voltage detect system: * The Low Voltage Detect Flag in the Low Voltage Status and Control 1 Register (LVDSC1[LVDF]) operates in a level sensitive manner. LVDSC1[LVDF] is set when the supply voltage falls below the selected trip point (VLVD). LVDSC1[LVDF] is cleared by writing 1 to LVDSC1[LVDACK], but only if the internal supply has returned above the trip point; otherwise, LVDSC1[LVDF] remains set. * The Low Voltage Warning Flag (LVWF) in the Low Voltage Status and Control 2 Register (LVDSC2[LVWF]) operates in a level sensitive manner. LVDSC2[LVWF] is set when the supply voltage falls below the selected monitor trip point (VLVW). LVDSC2[LVWF] is cleared by writing one to LVDSC2[LVWACK], but only if the internal supply has returned above the trip point; otherwise, LVDSC2[LVWF] remains set. 16.3.1 LVD reset operation By setting LVDSC1[LVDRE], the LVD generates a reset upon detection of a low-voltage condition. The low-voltage detection threshold is determined by LVDSC1[LVDV]. After an LVD reset occurs, the LVD system holds the MCU in reset until the supply voltage rises above this threshold. The LVD field in the SRS register of the RCM module (RCM_SRS[LVD]) is set following an LVD or power-on reset. 16.3.2 LVD interrupt operation By configuring the LVD circuit for interrupt operation (LVDSC1[LVDIE] set and LVDSC1[LVDRE] clear), LVDSC1[LVDF] is set and an LVD interrupt request occurs upon detection of a low voltage condition. LVDSC1[LVDF] is cleared by writing 1 to LVDSC1[LVDACK]. 16.3.3 Low-voltage warning (LVW) interrupt operation The LVD system contains a Low-Voltage Warning Flag (LVWF) in the Low Voltage Detect Status and Control 2 Register to indicate that the supply voltage is approaching, but is above, the LVD voltage. The LVW also has an interrupt, which is enabled by setting LVDSC2[LVWIE]. If enabled, an LVW interrupt request occurs when LVDSC2[LVWF] is set. LVDSC2[LVWF] is cleared by writing 1 to LVDSC2[LVWACK]. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 344 Freescale Semiconductor, Inc. Chapter 16 Power Management Controller (PMC) LVDSC2[LVWV] selects one of the four trip voltages: * Highest: VLVW4 * Two mid-levels: VLVW3 and VLVW2 * Lowest: VLVW1 16.4 I/O retention When in LLS mode, the I/O pins are held in their input or output state. Upon wakeup, the PMC is re-enabled, goes through a power up sequence to full regulation, and releases the logic from state retention mode. The I/O are released immediately after a wake-up or reset event. In the case of LLS exit via a RESET pin, the I/O default to their reset state. When in VLLS modes, the I/O states are held on a wake-up event (with the exception of wake-up by reset event) until the wake-up has been acknowledged via a write to REGSC[ACKISO]. In the case of VLLS exit via a RESET pin, the I/O are released and default to their reset state. In this case, no write to REGSC[ACKISO] is needed. 16.5 Memory map and register descriptions Details about the PMC registers can be found here. NOTE Different portions of PMC registers are reset only by particular reset types. Each register's description provides details. For more information about the types of reset on this chip, refer to the Reset section details. The PMC registers can be written only in supervisor mode. Write accesses in user mode are blocked and will result in a bus error. PMC memory map Absolute address (hex) 4007_D000 Register name Width Access (in bits) Low Voltage Detect Status And Control 1 register (PMC_LVDSC1) 8 R/W Reset value Section/ page 10h 16.5.1/346 Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 345 Memory map and register descriptions PMC memory map (continued) Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 4007_D001 Low Voltage Detect Status And Control 2 register (PMC_LVDSC2) 8 R/W 00h 16.5.2/347 4007_D002 Regulator Status And Control register (PMC_REGSC) 8 R/W 04h 16.5.3/348 16.5.1 Low Voltage Detect Status And Control 1 register (PMC_LVDSC1) This register contains status and control bits to support the low voltage detect function. This register should be written during the reset initialization program to set the desired controls even if the desired settings are the same as the reset settings. While the device is in the very low power or low leakage modes, the LVD system is disabled regardless of LVDSC1 settings. To protect systems that must have LVD always on, configure the Power Mode Protection (PMPROT) register of the SMC module (SMC_PMPROT) to disallow any very low power or low leakage modes from being enabled. See the device's data sheet for the exact LVD trip voltages. NOTE The LVDV bits are reset solely on a POR Only event. The register's other bits are reset on Chip Reset Not VLLS. For more information about these reset types, refer to the Reset section details. Address: 4007_D000h base + 0h offset = 4007_D000h Bit Read 7 6 LVDF 0 Write Reset 5 LVDACK 0 0 4 3 LVDIE LVDRE 0 1 2 1 0 0 0 LVDV 0 0 0 PMC_LVDSC1 field descriptions Field 7 LVDF Description Low-Voltage Detect Flag This read-only status field indicates a low-voltage detect event. 0 1 Low-voltage event not detected Low-voltage event detected Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 346 Freescale Semiconductor, Inc. Chapter 16 Power Management Controller (PMC) PMC_LVDSC1 field descriptions (continued) Field 6 LVDACK 5 LVDIE Description Low-Voltage Detect Acknowledge This write-only field is used to acknowledge low voltage detection errors. Write 1 to clear LVDF. Reads always return 0. Low-Voltage Detect Interrupt Enable Enables hardware interrupt requests for LVDF. 0 1 4 LVDRE Low-Voltage Detect Reset Enable This write-once bit enables LVDF events to generate a hardware reset. Additional writes are ignored. 0 1 3-2 Reserved LVDV Hardware interrupt disabled (use polling) Request a hardware interrupt when LVDF = 1 LVDF does not generate hardware resets Force an MCU reset when LVDF = 1 This field is reserved. This read-only field is reserved and always has the value 0. Low-Voltage Detect Voltage Select Selects the LVD trip point voltage (V LVD ). 00 01 10 11 Low trip point selected (V LVD = V LVDL ) High trip point selected (V LVD = V LVDH ) Reserved Reserved 16.5.2 Low Voltage Detect Status And Control 2 register (PMC_LVDSC2) This register contains status and control bits to support the low voltage warning function. While the device is in the very low power or low leakage modes, the LVD system is disabled regardless of LVDSC2 settings. See the device's data sheet for the exact LVD trip voltages. NOTE The LVW trip voltages depend on LVWV and LVDV. NOTE LVWV is reset solely on a POR Only event. The other fields of the register are reset on Chip Reset Not VLLS. For more information about these reset types, refer to the Reset section details. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 347 Memory map and register descriptions Address: 4007_D000h base + 1h offset = 4007_D001h Bit Read 7 6 LVWF 0 Write Reset LVWACK 0 5 4 3 LVWIE 0 0 2 1 0 0 0 0 LVWV 0 0 0 PMC_LVDSC2 field descriptions Field 7 LVWF Description Low-Voltage Warning Flag This read-only status field indicates a low-voltage warning event. LVWF is set when VSupply transitions below the trip point, or after reset and VSupply is already below VLVW. LVWF may be 1 after power-on reset, therefore, to use LVW interrupt function, before enabling LVWIE, LVWF must be cleared by writing LVWACK first. 0 1 6 LVWACK 5 LVWIE Low-Voltage Warning Acknowledge This write-only field is used to acknowledge low voltage warning errors. Write 1 to clear LVWF. Reads always return 0. Low-Voltage Warning Interrupt Enable Enables hardware interrupt requests for LVWF. 0 1 4-2 Reserved LVWV Low-voltage warning event not detected Low-voltage warning event detected Hardware interrupt disabled (use polling) Request a hardware interrupt when LVWF = 1 This field is reserved. This read-only field is reserved and always has the value 0. Low-Voltage Warning Voltage Select Selects the LVW trip point voltage (VLVW). The actual voltage for the warning depends on LVDSC1[LVDV]. 00 01 10 11 Low trip point selected (VLVW = VLVW1) Mid 1 trip point selected (VLVW = VLVW2) Mid 2 trip point selected (VLVW = VLVW3) High trip point selected (VLVW = VLVW4) 16.5.3 Regulator Status And Control register (PMC_REGSC) The PMC contains an internal voltage regulator. The voltage regulator design uses a bandgap reference that is also available through a buffer as input to certain internal peripherals, such as the CMP and ADC. The internal regulator provides a status bit (REGONS) indicating the regulator is in run regulation. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 348 Freescale Semiconductor, Inc. Chapter 16 Power Management Controller (PMC) NOTE This register is reset on Chip Reset Not VLLS and by reset types that trigger Chip Reset not VLLS. See the Reset section details for more information. Address: 4007_D000h base + 2h offset = 4007_D002h Bit 7 6 Read 0 0 5 Write Reset 0 0 4 Reserved BGEN 0 0 3 2 ACKISO REGONS w1c 0 1 1 0 Reserved BGBE 0 0 PMC_REGSC field descriptions Field Description 7 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 6 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 5 Reserved This field is reserved. 4 BGEN Bandgap Enable In VLPx Operation BGEN controls whether the bandgap is enabled in lower power modes of operation (VLPx, LLS, and VLLSx). When on-chip peripherals require the bandgap voltage reference in low power modes of operation, set BGEN to continue to enable the bandgap operation. NOTE: When the bandgap voltage reference is not needed in low power modes, clear BGEN to avoid excess power consumption. 0 1 3 ACKISO Bandgap voltage reference is disabled in VLPx , LLS , and VLLSx modes. Bandgap voltage reference is enabled in VLPx , LLS , and VLLSx modes. Acknowledge Isolation Reading this field indicates whether certain peripherals and the I/O pads are in a latched state as a result of having been in a VLLS mode. Writing 1 to this field when it is set releases the I/O pads and certain peripherals to their normal run mode state. NOTE: After recovering from a VLLS mode, user should restore chip configuration before clearing ACKISO. In particular, pin configuration for enabled LLWU wakeup pins should be restored to avoid any LLWU flag from being falsely set when ACKISO is cleared. 0 1 2 REGONS Regulator In Run Regulation Status This read-only field provides the current status of the internal voltage regulator. 0 1 1 Reserved Peripherals and I/O pads are in normal run state. Certain peripherals and I/O pads are in an isolated and latched state. Regulator is in stop regulation or in transition to/from it Regulator is in run regulation This field is reserved. NOTE: This reserved bit must remain cleared (set to 0). Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 349 Memory map and register descriptions PMC_REGSC field descriptions (continued) Field 0 BGBE Description Bandgap Buffer Enable Enables the bandgap buffer. 0 1 Bandgap buffer not enabled Bandgap buffer enabled KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 350 Freescale Semiconductor, Inc. Chapter 17 Low-Leakage Wakeup Unit (LLWU) 17.1 Introduction NOTE For the chip-specific implementation details of this module's instances, see the chip configuration information. The LLWU module allows the user to select up to 16 external pins and up to 8 internal modules as interrupt wake-up sources from low-leakage power modes. The input sources are described in the device's chip configuration details. Each of the available wake-up sources can be individually enabled. The RESET pin is an additional source for triggering an exit from low-leakage power modes, and causes the MCU to exit both LLS and VLLS through a reset flow. The LLWU module also includes two optional digital pin filters for the external wakeup pins. See AN4503: Power Management for Kinetis MCUs for further details on using the LLWU. 17.1.1 Features The LLWU module features include: * Support for up to 16 external input pins and up to 8 internal modules with individual enable bits for MCU interrupt from low leakage modes * Input sources may be external pins or from internal peripherals capable of running in LLS or VLLS. See the chip configuration information for wakeup input sources for this device. * External pin wake-up inputs, each of which is programmable as falling-edge, risingedge, or any change KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 351 Introduction * Wake-up inputs that are activated after MCU enters a low-leakage power mode * Optional digital filters provided to qualify an external pin detect. Note that when the LPO clock is disabled, the filters are disabled and bypassed. 17.1.2 Modes of operation The LLWU module becomes functional on entry into a low-leakage power mode. After recovery from LLS, the LLWU is immediately disabled. After recovery from VLLS, the LLWU continues to detect wake-up events until the user has acknowledged the wake-up via a write to PMC_REGSC[ACKISO]. 17.1.2.1 LLS mode Wake-up events due to external pin inputs (LLWU_Px) and internal module interrupt inputs (LLWU_MxIF) result in an interrupt flow when exiting LLS. NOTE The LLWU interrupt must not be masked by the interrupt controller to avoid a scenario where the system does not fully exit Stop mode on an LLS recovery. 17.1.2.2 VLLS modes All wakeup and reset events result in VLLS exit via a reset flow. 17.1.2.3 Non-low leakage modes The LLWU is not active in all non-low leakage modes where detection and control logic are in a static state. The LLWU registers are accessible in non-low leakage modes and are available for configuring and reading status when bus transactions are possible. When the wake-up pin filters are enabled, filter operation begins immediately. If a low leakage mode is entered within five LPO clock cycles of an active edge, the edge event will be detected by the LLWU. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 352 Freescale Semiconductor, Inc. Chapter 17 Low-Leakage Wakeup Unit (LLWU) 17.1.2.4 Debug mode When the chip is in Debug mode and then enters LLS or a VLLSx mode, no debug logic works in the fully-functional low-leakage mode. Upon an exit from the LLS or VLLSx mode, the LLWU becomes inactive. 17.1.3 Block diagram The following figure is the block diagram for the LLWU module. enter low leakge mode WUME7 Module7 interrupt flag (LLWU_M7IF) Module0 interrupt flag (LLWU_M0IF) Interrupt module flag detect LLWU_MWUF7 occurred Interrupt module flag detect LLWU_MWUF0 occurred FILT1[FILTSEL] Internal module sources WUME0 LPO LLWU_P15 Synchronizer LLWU_P0 Pin filter 1 LPO Synchronizer Pin filter 2 FILT1[FILTE] Edge detect Pin filter 1 wakeup occurred LLWU controller FILT2[FILTE] Edge detect exit low leakge mode Pin filter 2 wakeup occurred interrupt flow reset flow WUPE15 2 FILT2[FILTSEL] Edge detect Edge detect LLWU_P15 wakeup occurred LLWU_P0 wakeup occurred External pin sources 2 WUPE0 Figure 17-1. LLWU block diagram KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 353 LLWU signal descriptions 17.2 LLWU signal descriptions The signal properties of LLWU are shown in the table found here. The external wakeup input pins can be enabled to detect either rising-edge, falling-edge, or on any change. Table 17-1. LLWU signal descriptions Signal LLWU_Pn Description I/O Wakeup inputs (n = 0-15 ) I 17.3 Memory map/register definition The LLWU includes the following registers: * Wake-up source enable registers * Enable external pin input sources * Enable internal peripheral interrupt sources * Wake-up flag registers * Indication of wakeup source that caused exit from a low-leakage power mode includes external pin or internal module interrupt * Wake-up pin filter enable registers NOTE The LLWU registers can be written only in supervisor mode. Write accesses in user mode are blocked and will result in a bus error. All LLWU registers are reset by Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. Each register's displayed reset value represents this subset of reset types. LLWU registers are unaffected by reset types that do not trigger Chip Reset not VLLS. For more information about the types of reset on this chip, refer to the Introduction details. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 354 Freescale Semiconductor, Inc. Chapter 17 Low-Leakage Wakeup Unit (LLWU) LLWU memory map Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 4007_C000 LLWU Pin Enable 1 register (LLWU_PE1) 8 R/W 00h 17.3.1/355 4007_C001 LLWU Pin Enable 2 register (LLWU_PE2) 8 R/W 00h 17.3.2/356 4007_C002 LLWU Pin Enable 3 register (LLWU_PE3) 8 R/W 00h 17.3.3/357 4007_C003 LLWU Pin Enable 4 register (LLWU_PE4) 8 R/W 00h 17.3.4/358 4007_C004 LLWU Module Enable register (LLWU_ME) 8 R/W 00h 17.3.5/359 4007_C005 LLWU Flag 1 register (LLWU_F1) 8 R/W 00h 17.3.6/361 4007_C006 LLWU Flag 2 register (LLWU_F2) 8 R/W 00h 17.3.7/363 4007_C007 LLWU Flag 3 register (LLWU_F3) 8 R 00h 17.3.8/364 4007_C008 LLWU Pin Filter 1 register (LLWU_FILT1) 8 R/W 00h 17.3.9/366 4007_C009 LLWU Pin Filter 2 register (LLWU_FILT2) 8 R/W 00h 17.3.10/367 17.3.1 LLWU Pin Enable 1 register (LLWU_PE1) LLWU_PE1 contains the field to enable and select the edge detect type for the external wakeup input pins LLWU_P3-LLWU_P0. NOTE This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See the Introduction details for more information. Address: 4007_C000h base + 0h offset = 4007_C000h Bit Read Write Reset 7 6 5 WUPE3 0 4 3 WUPE2 0 0 2 1 WUPE1 0 0 0 WUPE0 0 0 0 LLWU_PE1 field descriptions Field 7-6 WUPE3 Description Wakeup Pin Enable For LLWU_P3 Enables and configures the edge detection for the wakeup pin. 00 01 10 11 5-4 WUPE2 External input pin disabled as wakeup input External input pin enabled with rising edge detection External input pin enabled with falling edge detection External input pin enabled with any change detection Wakeup Pin Enable For LLWU_P2 Enables and configures the edge detection for the wakeup pin. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 355 Memory map/register definition LLWU_PE1 field descriptions (continued) Field Description 00 01 10 11 3-2 WUPE1 Wakeup Pin Enable For LLWU_P1 Enables and configures the edge detection for the wakeup pin. 00 01 10 11 WUPE0 External input pin disabled as wakeup input External input pin enabled with rising edge detection External input pin enabled with falling edge detection External input pin enabled with any change detection External input pin disabled as wakeup input External input pin enabled with rising edge detection External input pin enabled with falling edge detection External input pin enabled with any change detection Wakeup Pin Enable For LLWU_P0 Enables and configures the edge detection for the wakeup pin. 00 01 10 11 External input pin disabled as wakeup input External input pin enabled with rising edge detection External input pin enabled with falling edge detection External input pin enabled with any change detection 17.3.2 LLWU Pin Enable 2 register (LLWU_PE2) LLWU_PE2 contains the field to enable and select the edge detect type for the external wakeup input pins LLWU_P7-LLWU_P4. NOTE This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See the Introduction details for more information. Address: 4007_C000h base + 1h offset = 4007_C001h Bit Read Write Reset 7 6 5 WUPE7 0 4 3 WUPE6 0 0 2 1 WUPE5 0 0 0 WUPE4 0 0 0 LLWU_PE2 field descriptions Field 7-6 WUPE7 Description Wakeup Pin Enable For LLWU_P7 Enables and configures the edge detection for the wakeup pin. 00 01 External input pin disabled as wakeup input External input pin enabled with rising edge detection Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 356 Freescale Semiconductor, Inc. Chapter 17 Low-Leakage Wakeup Unit (LLWU) LLWU_PE2 field descriptions (continued) Field Description 10 11 5-4 WUPE6 Wakeup Pin Enable For LLWU_P6 Enables and configures the edge detection for the wakeup pin. 00 01 10 11 3-2 WUPE5 External input pin disabled as wakeup input External input pin enabled with rising edge detection External input pin enabled with falling edge detection External input pin enabled with any change detection Wakeup Pin Enable For LLWU_P5 Enables and configures the edge detection for the wakeup pin. 00 01 10 11 WUPE4 External input pin enabled with falling edge detection External input pin enabled with any change detection External input pin disabled as wakeup input External input pin enabled with rising edge detection External input pin enabled with falling edge detection External input pin enabled with any change detection Wakeup Pin Enable For LLWU_P4 Enables and configures the edge detection for the wakeup pin. 00 01 10 11 External input pin disabled as wakeup input External input pin enabled with rising edge detection External input pin enabled with falling edge detection External input pin enabled with any change detection 17.3.3 LLWU Pin Enable 3 register (LLWU_PE3) LLWU_PE3 contains the field to enable and select the edge detect type for the external wakeup input pins LLWU_P11-LLWU_P8. NOTE This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See the Introduction details for more information. Address: 4007_C000h base + 2h offset = 4007_C002h Bit Read Write Reset 7 6 5 WUPE11 0 4 3 WUPE10 0 0 2 1 WUPE9 0 0 0 WUPE8 0 0 0 KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 357 Memory map/register definition LLWU_PE3 field descriptions Field 7-6 WUPE11 Description Wakeup Pin Enable For LLWU_P11 Enables and configures the edge detection for the wakeup pin. 00 01 10 11 5-4 WUPE10 Wakeup Pin Enable For LLWU_P10 Enables and configures the edge detection for the wakeup pin. 00 01 10 11 3-2 WUPE9 External input pin disabled as wakeup input External input pin enabled with rising edge detection External input pin enabled with falling edge detection External input pin enabled with any change detection Wakeup Pin Enable For LLWU_P9 Enables and configures the edge detection for the wakeup pin. 00 01 10 11 WUPE8 External input pin disabled as wakeup input External input pin enabled with rising edge detection External input pin enabled with falling edge detection External input pin enabled with any change detection External input pin disabled as wakeup input External input pin enabled with rising edge detection External input pin enabled with falling edge detection External input pin enabled with any change detection Wakeup Pin Enable For LLWU_P8 Enables and configures the edge detection for the wakeup pin. 00 01 10 11 External input pin disabled as wakeup input External input pin enabled with rising edge detection External input pin enabled with falling edge detection External input pin enabled with any change detection 17.3.4 LLWU Pin Enable 4 register (LLWU_PE4) LLWU_PE4 contains the field to enable and select the edge detect type for the external wakeup input pins LLWU_P15-LLWU_P12. NOTE This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See the Introduction details for more information. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 358 Freescale Semiconductor, Inc. Chapter 17 Low-Leakage Wakeup Unit (LLWU) Address: 4007_C000h base + 3h offset = 4007_C003h Bit Read Write Reset 7 6 5 WUPE15 0 4 3 WUPE14 0 0 2 1 WUPE13 0 0 0 WUPE12 0 0 0 LLWU_PE4 field descriptions Field 7-6 WUPE15 Description Wakeup Pin Enable For LLWU_P15 Enables and configures the edge detection for the wakeup pin. 00 01 10 11 5-4 WUPE14 Wakeup Pin Enable For LLWU_P14 Enables and configures the edge detection for the wakeup pin. 00 01 10 11 3-2 WUPE13 External input pin disabled as wakeup input External input pin enabled with rising edge detection External input pin enabled with falling edge detection External input pin enabled with any change detection Wakeup Pin Enable For LLWU_P13 Enables and configures the edge detection for the wakeup pin. 00 01 10 11 WUPE12 External input pin disabled as wakeup input External input pin enabled with rising edge detection External input pin enabled with falling edge detection External input pin enabled with any change detection External input pin disabled as wakeup input External input pin enabled with rising edge detection External input pin enabled with falling edge detection External input pin enabled with any change detection Wakeup Pin Enable For LLWU_P12 Enables and configures the edge detection for the wakeup pin. 00 01 10 11 External input pin disabled as wakeup input External input pin enabled with rising edge detection External input pin enabled with falling edge detection External input pin enabled with any change detection 17.3.5 LLWU Module Enable register (LLWU_ME) LLWU_ME contains the bits to enable the internal module flag as a wakeup input source for inputs MWUF7-MWUF0. NOTE This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 359 Memory map/register definition types that do not trigger Chip Reset not VLLS. See the Introduction details for more information. Address: 4007_C000h base + 4h offset = 4007_C004h Bit Read Write Reset 7 6 5 4 3 2 1 0 WUME7 WUME6 WUME5 WUME4 WUME3 WUME2 WUME1 WUME0 0 0 0 0 0 0 0 0 LLWU_ME field descriptions Field 7 WUME7 Description Wakeup Module Enable For Module 7 Enables an internal module as a wakeup source input. 0 1 6 WUME6 Wakeup Module Enable For Module 6 Enables an internal module as a wakeup source input. 0 1 5 WUME5 Enables an internal module as a wakeup source input. Enables an internal module as a wakeup source input. Enables an internal module as a wakeup source input. Internal module flag not used as wakeup source Internal module flag used as wakeup source Wakeup Module Enable For Module 2 Enables an internal module as a wakeup source input. 0 1 1 WUME1 Internal module flag not used as wakeup source Internal module flag used as wakeup source Wakeup Module Enable For Module 3 0 1 2 WUME2 Internal module flag not used as wakeup source Internal module flag used as wakeup source Wakeup Module Enable For Module 4 0 1 3 WUME3 Internal module flag not used as wakeup source Internal module flag used as wakeup source Wakeup Module Enable For Module 5 0 1 4 WUME4 Internal module flag not used as wakeup source Internal module flag used as wakeup source Internal module flag not used as wakeup source Internal module flag used as wakeup source Wakeup Module Enable for Module 1 Enables an internal module as a wakeup source input. 0 1 Internal module flag not used as wakeup source Internal module flag used as wakeup source Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 360 Freescale Semiconductor, Inc. Chapter 17 Low-Leakage Wakeup Unit (LLWU) LLWU_ME field descriptions (continued) Field 0 WUME0 Description Wakeup Module Enable For Module 0 Enables an internal module as a wakeup source input. 0 1 Internal module flag not used as wakeup source Internal module flag used as wakeup source 17.3.6 LLWU Flag 1 register (LLWU_F1) LLWU_F1 contains the wakeup flags indicating which wakeup source caused the MCU to exit LLS or VLLS mode. For LLS, this is the source causing the CPU interrupt flow. For VLLS, this is the source causing the MCU reset flow. The external wakeup flags are read-only and clearing a flag is accomplished by a write of a 1 to the corresponding WUFx bit. The wakeup flag (WUFx), if set, will remain set if the associated WUPEx bit is cleared. NOTE This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See the Introduction details for more information. Address: 4007_C000h base + 5h offset = 4007_C005h Bit 7 6 5 4 3 2 1 0 Read WUF7 WUF6 WUF5 WUF4 WUF3 WUF2 WUF1 WUF0 Write w1c w1c w1c w1c w1c w1c w1c w1c Reset 0 0 0 0 0 0 0 0 LLWU_F1 field descriptions Field 7 WUF7 Description Wakeup Flag For LLWU_P7 Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag, write a 1 to WUF7. 0 1 6 WUF6 LLWU_P7 input was not a wakeup source LLWU_P7 input was a wakeup source Wakeup Flag For LLWU_P6 Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag, write a 1 to WUF6. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 361 Memory map/register definition LLWU_F1 field descriptions (continued) Field Description 0 1 5 WUF5 Wakeup Flag For LLWU_P5 Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag, write a 1 to WUF5. 0 1 4 WUF4 Indicates that an enabled external wake-up pin was a source of exiting a low-leakage power mode. To clear the flag, write a 1 to WUF4. Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag, write a 1 to WUF3. Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag, write a 1 to WUF2. LLWU_P2 input was not a wakeup source LLWU_P2 input was a wakeup source Wakeup Flag For LLWU_P1 Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag, write a 1 to WUF1. 0 1 0 WUF0 LLWU_P3 input was not a wake-up source LLWU_P3 input was a wake-up source Wakeup Flag For LLWU_P2 0 1 1 WUF1 LLWU_P4 input was not a wakeup source LLWU_P4 input was a wakeup source Wakeup Flag For LLWU_P3 0 1 2 WUF2 LLWU_P5 input was not a wakeup source LLWU_P5 input was a wakeup source Wakeup Flag For LLWU_P4 0 1 3 WUF3 LLWU_P6 input was not a wakeup source LLWU_P6 input was a wakeup source LLWU_P1 input was not a wakeup source LLWU_P1 input was a wakeup source Wakeup Flag For LLWU_P0 Indicates that an enabled external wake-up pin was a source of exiting a low-leakage power mode. To clear the flag, write a 1 to WUF0. 0 1 LLWU_P0 input was not a wakeup source LLWU_P0 input was a wakeup source KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 362 Freescale Semiconductor, Inc. Chapter 17 Low-Leakage Wakeup Unit (LLWU) 17.3.7 LLWU Flag 2 register (LLWU_F2) LLWU_F2 contains the wakeup flags indicating which wakeup source caused the MCU to exit LLS or VLLS mode. For LLS, this is the source causing the CPU interrupt flow. For VLLS, this is the source causing the MCU reset flow. The external wakeup flags are read-only and clearing a flag is accomplished by a write of a 1 to the corresponding WUFx bit. The wakeup flag (WUFx), if set, will remain set if the associated WUPEx bit is cleared. NOTE This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See the Introduction details for more information. Address: 4007_C000h base + 6h offset = 4007_C006h Bit 7 6 5 4 3 2 1 0 Read WUF15 WUF14 WUF13 WUF12 WUF11 WUF10 WUF9 WUF8 Write w1c w1c w1c w1c w1c w1c w1c w1c Reset 0 0 0 0 0 0 0 0 LLWU_F2 field descriptions Field 7 WUF15 Description Wakeup Flag For LLWU_P15 Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag, write a 1 to WUF15. 0 1 6 WUF14 Wakeup Flag For LLWU_P14 Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag, write a 1 to WUF14. 0 1 5 WUF13 LLWU_P15 input was not a wakeup source LLWU_P15 input was a wakeup source LLWU_P14 input was not a wakeup source LLWU_P14 input was a wakeup source Wakeup Flag For LLWU_P13 Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag, write a 1 to WUF13. 0 1 LLWU_P13 input was not a wakeup source LLWU_P13 input was a wakeup source Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 363 Memory map/register definition LLWU_F2 field descriptions (continued) Field 4 WUF12 Description Wakeup Flag For LLWU_P12 Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag, write a 1 to WUF12. 0 1 3 WUF11 Wakeup Flag For LLWU_P11 Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag, write a 1 to WUF11. 0 1 2 WUF10 Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag, write a 1 to WUF10. LLWU_P10 input was not a wakeup source LLWU_P10 input was a wakeup source Wakeup Flag For LLWU_P9 Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag, write a 1 to WUF9. 0 1 0 WUF8 LLWU_P11 input was not a wakeup source LLWU_P11 input was a wakeup source Wakeup Flag For LLWU_P10 0 1 1 WUF9 LLWU_P12 input was not a wakeup source LLWU_P12 input was a wakeup source LLWU_P9 input was not a wakeup source LLWU_P9 input was a wakeup source Wakeup Flag For LLWU_P8 Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag, write a 1 to WUF8. 0 1 LLWU_P8 input was not a wakeup source LLWU_P8 input was a wakeup source 17.3.8 LLWU Flag 3 register (LLWU_F3) LLWU_F3 contains the wakeup flags indicating which internal wakeup source caused the MCU to exit LLS or VLLS mode. For LLS, this is the source causing the CPU interrupt flow. For VLLS, this is the source causing the MCU reset flow. For internal peripherals that are capable of running in a low-leakage power mode, such as a real time clock module or CMP module, the flag from the associated peripheral is accessible as the MWUFx bit. The flag will need to be cleared in the peripheral instead of writing a 1 to the MWUFx bit. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 364 Freescale Semiconductor, Inc. Chapter 17 Low-Leakage Wakeup Unit (LLWU) NOTE This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See the Introduction details for more information. Address: 4007_C000h base + 7h offset = 4007_C007h Bit Read 7 6 5 4 3 2 1 0 MWUF7 MWUF6 MWUF5 MWUF4 MWUF3 MWUF2 MWUF1 MWUF0 0 0 0 0 0 0 0 0 Write Reset LLWU_F3 field descriptions Field 7 MWUF7 Description Wakeup flag For module 7 Indicates that an enabled internal peripheral was a source of exiting a low-leakage power mode. To clear the flag, follow the internal peripheral flag clearing mechanism. 0 1 6 MWUF6 Wakeup flag For module 6 Indicates that an enabled internal peripheral was a source of exiting a low-leakage power mode. To clear the flag, follow the internal peripheral flag clearing mechanism. 0 1 5 MWUF5 Indicates that an enabled internal peripheral was a source of exiting a low-leakage power mode. To clear the flag, follow the internal peripheral flag clearing mechanism. Indicates that an enabled internal peripheral was a source of exiting a low-leakage power mode. To clear the flag, follow the internal peripheral flag clearing mechanism. Module 4 input was not a wakeup source Module 4 input was a wakeup source Wakeup flag For module 3 Indicates that an enabled internal peripheral was a source of exiting a low-leakage power mode. To clear the flag, follow the internal peripheral flag clearing mechanism. 0 1 2 MWUF2 Module 5 input was not a wakeup source Module 5 input was a wakeup source Wakeup flag For module 4 0 1 3 MWUF3 Module 6 input was not a wakeup source Module 6 input was a wakeup source Wakeup flag For module 5 0 1 4 MWUF4 Module 7 input was not a wakeup source Module 7 input was a wakeup source Module 3 input was not a wakeup source Module 3 input was a wakeup source Wakeup flag For module 2 Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 365 Memory map/register definition LLWU_F3 field descriptions (continued) Field Description Indicates that an enabled internal peripheral was a source of exiting a low-leakage power mode. To clear the flag, follow the internal peripheral flag clearing mechanism. 0 1 1 MWUF1 Wakeup flag For module 1 Indicates that an enabled internal peripheral was a source of exiting a low-leakage power mode. To clear the flag, follow the internal peripheral flag clearing mechanism. 0 1 0 MWUF0 Module 2 input was not a wakeup source Module 2 input was a wakeup source Module 1 input was not a wakeup source Module 1 input was a wakeup source Wakeup flag For module 0 Indicates that an enabled internal peripheral was a source of exiting a low-leakage power mode. To clear the flag, follow the internal peripheral flag clearing mechanism. 0 1 Module 0 input was not a wakeup source Module 0 input was a wakeup source 17.3.9 LLWU Pin Filter 1 register (LLWU_FILT1) LLWU_FILT1 is a control and status register that is used to enable/disable the digital filter 1 features for an external pin. NOTE This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See the Introduction details for more information. Address: 4007_C000h base + 8h offset = 4007_C008h Bit 7 Read FILTF Write w1c Reset 0 6 5 3 2 0 FILTE 0 4 0 0 1 0 0 0 FILTSEL 0 0 LLWU_FILT1 field descriptions Field 7 FILTF Description Filter Detect Flag Indicates that the filtered external wakeup pin, selected by FILTSEL, was a source of exiting a low-leakage power mode. To clear the flag write a one to FILTF. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 366 Freescale Semiconductor, Inc. Chapter 17 Low-Leakage Wakeup Unit (LLWU) LLWU_FILT1 field descriptions (continued) Field Description 0 1 6-5 FILTE Pin Filter 1 was not a wakeup source Pin Filter 1 was a wakeup source Digital Filter On External Pin Controls the digital filter options for the external pin detect. 00 01 10 11 Filter disabled Filter posedge detect enabled Filter negedge detect enabled Filter any edge detect enabled 4 Reserved This field is reserved. This read-only field is reserved and always has the value 0. FILTSEL Filter Pin Select Selects 1 out of the 16 wakeup pins to be muxed into the filter. 0000 ... 1111 Select LLWU_P0 for filter ... Select LLWU_P15 for filter 17.3.10 LLWU Pin Filter 2 register (LLWU_FILT2) LLWU_FILT2 is a control and status register that is used to enable/disable the digital filter 2 features for an external pin. NOTE This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See the Introduction details for more information. Address: 4007_C000h base + 9h offset = 4007_C009h Bit 7 Read FILTF Write w1c Reset 0 6 5 FILTE 0 4 3 2 0 0 0 1 0 0 0 FILTSEL 0 0 LLWU_FILT2 field descriptions Field 7 FILTF Description Filter Detect Flag Indicates that the filtered external wakeup pin, selected by FILTSEL, was a source of exiting a low-leakage power mode. To clear the flag write a one to FILTF. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 367 Functional description LLWU_FILT2 field descriptions (continued) Field Description 0 1 6-5 FILTE Pin Filter 2 was not a wakeup source Pin Filter 2 was a wakeup source Digital Filter On External Pin Controls the digital filter options for the external pin detect. 00 01 10 11 Filter disabled Filter posedge detect enabled Filter negedge detect enabled Filter any edge detect enabled 4 Reserved This field is reserved. This read-only field is reserved and always has the value 0. FILTSEL Filter Pin Select Selects 1 out of the 16 wakeup pins to be muxed into the filter. 0000 ... 1111 Select LLWU_P0 for filter ... Select LLWU_P15 for filter 17.4 Functional description Thie low-leakage wakeup unit (LLWU) module allows internal peripherals and external input pins as a source of wakeup from low-leakage modes. It is operational only in LLS and VLLSx modes. The LLWU module contains pin enables for each external pin and internal module. For each external pin, the user can disable or select the edge type for the wakeup with the following options: * Falling-edge * Rising-edge * Either-edge When an external pin is enabled as a wakeup source, the pin must be configured as an input pin. The LLWU implements optional 3-cycle glitch filters, based on the LPO clock. A detected external pin is required to remain asserted until the enabled glitch filter times out. Additional latency of up to 2 cycles is due to synchronization, which results in a total of up to 5 cycles of delay before the detect circuit alerts the system to the wakeup or reset event when the filter function is enabled. Two wakeup detect filters are available for selected external pins. Glitch filtering is not provided on the internal modules. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 368 Freescale Semiconductor, Inc. Chapter 17 Low-Leakage Wakeup Unit (LLWU) For internal module interrupts, the WUMEx bit enables the associated module interrupt as a wakeup source. 17.4.1 LLS mode Wakeup events triggered from either an external pin input or an internal module interrupt, result in a CPU interrupt flow to begin user code execution. 17.4.2 VLLS modes For any wakeup from VLLS, recovery is always via a reset flow and RCM_SRS[WAKEUP] is set indicating the low-leakage mode was active. State retention data is lost and I/O will be restored after PMC_REGSC[ACKISO] has been written. A VLLS exit event due to RESET pin assertion causes an exit via a system reset. State retention data is lost and the I/O states immediately return to their reset state. The RCM_SRS[WAKEUP] and RCM_SRS[PIN] bits are set and the system executes a reset flow before CPU operation begins with a reset vector fetch. 17.4.3 Initialization For an enabled peripheral wakeup input, the peripheral flag must be cleared by software before entering LLS or VLLSx mode to avoid an immediate exit from the mode. Flags associated with external input pins, filtered and unfiltered, must also be cleared by software prior to entry to LLS or VLLSx mode. After enabling an external pin filter or changing the source pin, wait at least five LPO clock cycles before entering LLS or VLLSx mode to allow the filter to initialize. NOTE After recovering from a VLLS mode, user must restore chip configuration before clearing PMC_REGSC[ACKISO]. In particular, pin configuration for enabled LLWU wake-up pins must be restored to avoid any LLWU flag from being falsely set when PMC_REGSC[ACKISO] is cleared. The signal selected as a wake-up source pin must be a digital pin, as selected in the pin mux control. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 369 Functional description KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 370 Freescale Semiconductor, Inc. Chapter 18 Miscellaneous Control Module (MCM) 18.1 Introduction NOTE For the chip-specific implementation details of this module's instances, see the chip configuration information. The Miscellaneous Control Module (MCM) provides a myriad of miscellaneous control functions. 18.1.1 Features The MCM includes the following features: * Program-visible information on the platform configuration and revision 18.2 Memory map/register descriptions The memory map and register descriptions below describe the registers using byte addresses. MCM memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page E008_0008 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC) 16 R 001Fh 18.2.1/372 E008_000A Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC) 16 R 0017h 18.2.2/372 32 R/W 0000_0000h 18.2.3/373 E008_000C Crossbar Switch (AXBS) Control Register (MCM_PLACR) Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 371 Memory map/register descriptions MCM memory map (continued) Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page E008_0010 Interrupt Status and Control Register (MCM_ISCR) 32 R 0002_0000h 18.2.4/373 E008_0040 Compute Operation Control Register (MCM_CPO) 32 R/W 0000_0000h 18.2.5/376 18.2.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC) PLASC is a 16-bit read-only register identifying the presence/absence of bus slave connections to the device's crossbar switch. Address: E008_0000h base + 8h offset = E008_0008h Bit 15 14 13 12 Read 11 10 9 8 7 6 5 4 0 3 2 1 0 1 1 1 1 ASC Write Reset 0 0 0 0 0 0 0 0 0 0 0 1 MCM_PLASC field descriptions Field Description 15-8 Reserved This field is reserved. This read-only field is reserved and always has the value 0. ASC Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's slave input port. 0 1 A bus slave connection to AXBS input port n is absent A bus slave connection to AXBS input port n is present 18.2.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC) PLAMC is a 16-bit read-only register identifying the presence/absence of bus master connections to the device's crossbar switch. Address: E008_0000h base + Ah offset = E008_000Ah Bit 15 14 13 12 Read 11 10 9 8 7 6 5 4 0 3 2 1 0 0 1 1 1 AMC Write Reset 0 0 0 0 0 0 0 0 0 0 0 1 KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 372 Freescale Semiconductor, Inc. Chapter 18 Miscellaneous Control Module (MCM) MCM_PLAMC field descriptions Field Description 15-8 Reserved This field is reserved. This read-only field is reserved and always has the value 0. AMC Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port. 0 1 A bus master connection to AXBS input port n is absent A bus master connection to AXBS input port n is present 18.2.3 Crossbar Switch (AXBS) Control Register (MCM_PLACR) The PLACR register selects the arbitration policy for the crossbar masters. Address: E008_0000h base + Ch offset = E008_000Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 4 3 2 1 0 0 0 0 0 0 R W Reset 0 0 0 Bit 15 14 13 0 0 0 0 0 0 0 0 12 11 10 9 8 7 6 5 0 R ARB W Reset 0 0 0 Reserved 0 0 0 0 0 0 0 0 0 MCM_PLACR field descriptions Field 31-10 Reserved 9 ARB Reserved Description This field is reserved. This read-only field is reserved and always has the value 0. Arbitration select 0 1 Fixed-priority arbitration for the crossbar masters Round-robin arbitration for the crossbar masters This field is reserved. 18.2.4 Interrupt Status and Control Register (MCM_ISCR) The MCM_ISCR register includes the enable and status bits associated with the core's floating-point exceptions. The individual event indicators are first qualified with their exception enables and then logically summed to form an interrupt request sent to the core's NVIC. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 373 Memory map/register descriptions Bits 15-8 are read-only indicator flags based on the processor's FPSCR register. Attempted writes to these bits are ignored. Once set, the flags remain asserted until software clears the corresponding FPSCR bit. Address: E008_0000h base + 10h offset = E008_0010h Bit 31 30 29 28 27 26 25 24 23 22 21 0 19 18 17 16 FIXCE FUFCE FOFCE FDZCE FIOCE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R FUFC FOFC FDZC FIOC 0 0 0 0 0 0 0 0 0 FIDCE Reset FIXC Reserved FIDC R 20 W 0 0 W Reset 0 0 0 0 0 0 0 MCM_ISCR field descriptions Field 31 FIDCE 30-29 Reserved Description FPU input denormal interrupt enable 0 1 Disable interrupt Enable interrupt This field is reserved. This read-only field is reserved and always has the value 0. 28 FIXCE FPU inexact interrupt enable 27 FUFCE FPU underflow interrupt enable 0 1 0 1 Disable interrupt Enable interrupt Disable interrupt Enable interrupt Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 374 Freescale Semiconductor, Inc. Chapter 18 Miscellaneous Control Module (MCM) MCM_ISCR field descriptions (continued) Field Description 26 FOFCE FPU overflow interrupt enable 25 FDZCE FPU divide-by-zero interrupt enable 24 FIOCE FPU invalid operation interrupt enable 23-16 Reserved 15 FIDC 0 1 0 1 0 1 12 FIXC This read-only bit is a copy of the core's FPSCR[IDC] bit and signals input denormalized number has been detected in the processor's FPU. Once set, this bit remains set until software clears the FPSCR[IDC] bit. FPU inexact interrupt status This read-only bit is a copy of the core's FPSCR[IXC] bit and signals an inexact number has been detected in the processor's FPU. Once set, this bit remains set until software clears the FPSCR[IXC] bit. No interrupt Interrupt occurred FPU underflow interrupt status This read-only bit is a copy of the core's FPSCR[UFC] bit and signals an underflow has been detected in the processor's FPU. Once set, this bit remains set until software clears the FPSCR[UFC] bit. No interrupt Interrupt occurred FPU overflow interrupt status This read-only bit is a copy of the core's FPSCR[OFC] bit and signals an overflow has been detected in the processor's FPU. Once set, this bit remains set until software clears the FPSCR[OFC] bit. 0 1 9 FDZC No interrupt Interrupt occurred This field is reserved. This read-only field is reserved and always has the value 0. 0 1 10 FOFC Disable interrupt Enable interrupt FPU input denormal interrupt status 0 1 11 FUFC Disable interrupt Enable interrupt This field is reserved. 0 1 14-13 Reserved Disable interrupt Enable interrupt No interrupt Interrupt occurred FPU divide-by-zero interrupt status This read-only bit is a copy of the core's FPSCR[DZC] bit and signals a divide by zero has been detected in the processor's FPU. Once set, this bit remains set until software clears the FPSCR[DZC] bit. 0 1 No interrupt Interrupt occurred Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 375 Memory map/register descriptions MCM_ISCR field descriptions (continued) Field Description 8 FIOC FPU invalid operation interrupt status This read-only bit is a copy of the core's FPSCR[IOC] bit and signals an illegal operation has been detected in the processor's FPU. Once set, this bit remains set until software clears the FPSCR[IOC] bit. 0 1 Reserved No interrupt Interrupt occurred This field is reserved. This read-only field is reserved and always has the value 0. 18.2.5 Compute Operation Control Register (MCM_CPO) This register controls the Compute Operation. Address: E008_0000h base + 40h offset = E008_0040h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 CPOWOI R CPOREQ 0 CPOACK Reset W Reset 0 0 0 0 0 0 0 0 0 0 KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 376 Freescale Semiconductor, Inc. Chapter 18 Miscellaneous Control Module (MCM) MCM_CPO field descriptions Field Description 31-3 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 2 CPOWOI Compute Operation wakeup on interrupt 1 CPOACK Compute Operation acknowledge 0 CPOREQ Compute Operation request 0 1 0 1 No effect. When set, the CPOREQ is cleared on any interrupt or exception vector fetch. Compute operation entry has not completed or compute operation exit has completed. Compute operation entry has completed or compute operation exit has not completed. This bit is auto-cleared by vector fetching if CPOWOI = 1. 0 1 Request is cleared. Request Compute Operation. 18.3 Functional description This section describes the functional description of MCM module. 18.3.1 Interrupts The MCM's interrupt is generated if any of the following is true: * FPU input denormal interrupt is enabled (FIDCE) and an input is denormalized (FIDC) * FPU inexact interrupt is enabled (FIXCE) and a number is inexact (FIXC) * FPU underflow interrupt is enabled (FUFCE) and an underflow occurs (FUFC) * FPU overflow interrupt is enabled (FOFCE) and an overflow occurs (FOFC) * FPU divide-by-zero interrupt is enabled (FDZCE) and a divide-by-zero occurs (FDZC) * FPU invalid operation interrupt is enabled (FDZCE) and an invalid occurs (FDZC) 18.3.1.1 Determining source of the interrupt To determine the exact source of the interrupt qualify the interrupt status flags with the corresponding interrupt enable bits. 1. From MCM_ISCR[31:16] && MCM_ISCR[15:0] KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 377 Functional description 2. Search the result for asserted flags, which indicate the exact interrupt sources KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 378 Freescale Semiconductor, Inc. Chapter 19 Crossbar Switch Lite (AXBS-Lite) 19.1 Introduction NOTE For the chip-specific implementation details of this module's instances, see the chip configuration information. The information found here provides information on the layout, configuration, and programming of the crossbar switch. The crossbar switch connects bus masters and bus slaves using a crossbar switch structure. This structure allows up to four bus masters to access different bus slaves simultaneously, while providing arbitration among the bus masters when they access the same slave. 19.1.1 Features The crossbar switch includes these features: * Symmetric crossbar bus switch implementation * Allows concurrent accesses from different masters to different slaves * Up to single-clock 32-bit transfer * Programmable configuration for fixed-priority or round-robin slave port arbitration (see the chip-specific information). KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 379 Memory Map / Register Definition 19.2 Memory Map / Register Definition This crossbar switch is designed for minimal gate count. It, therefore, has no memorymapped configuration registers. Please see the chip-specific information for information on whether the arbitration method in the crossbar switch is programmable, and by which module. 19.3 Functional Description 19.3.1 General operation When a master accesses the crossbar switch, the access is immediately taken. If the targeted slave port of the access is available, then the access is immediately presented on the slave port. Single-clock or zero-wait-state accesses are possible through the crossbar. If the targeted slave port of the access is busy or parked on a different master port, the requesting master simply sees wait states inserted until the targeted slave port can service the master's request. The latency in servicing the request depends on each master's priority level and the responding slave's access time. Because the crossbar switch appears to be just another slave to the master device, the master device has no knowledge of whether it actually owns the slave port it is targeting. While the master does not have control of the slave port it is targeting, it simply waits. After the master has control of the slave port it is targeting, the master remains in control of the slave port until it relinquishes the slave port by running an IDLE cycle or by targeting a different slave port for its next access. The master can also lose control of the slave port if another higher-priority master makes a request to the slave port. The crossbar terminates all master IDLE transfers, as opposed to allowing the termination to come from one of the slave buses. Additionally, when no master is requesting access to a slave port, the crossbar drives IDLE transfers onto the slave bus, even though a default master may be granted access to the slave port. When a slave bus is being idled by the crossbar, it remains parked with the last master to use the slave port. This is done to save the initial clock of arbitration delay that otherwise would be seen if the same master had to arbitrate to gain control of the slave port. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 380 Freescale Semiconductor, Inc. Chapter 19 Crossbar Switch Lite (AXBS-Lite) 19.3.2 Arbitration The crossbar switch supports two arbitration algorithms: * Fixed priority * Round-robin The selection of the global slave port arbitration is controlled in the MCM module. For fixed priority, set MCM_PLACR[ARB] to 0. For round robin, set MCM_PLACR[ARB] to 1. This arbitration setting applies to all slave ports. 19.3.2.1 Fixed-priority operation When operating in fixed-priority mode, each master is assigned a unique priority level with the highest numbered master having the highest priority (for example, in a system with 5 masters, master 1 has lower priority than master 3). If two masters request access to the same slave port, the master with the highest priority gains control over the slave port. NOTE In this arbitration mode, a higher-priority master can monopolize a slave port, preventing accesses from any lowerpriority master to the port. When a master makes a request to a slave port, the slave port checks whether the new requesting master's priority level is higher than that of the master that currently has control over the slave port, unless the slave port is in a parked state. The slave port performs an arbitration check at every clock edge to ensure that the proper master, if any, has control of the slave port. The following table describes possible scenarios based on the requesting master port: Table 19-1. How the Crossbar Switch grants control of a slave port to a master When Then the Crossbar Switch grants control to the requesting master Both of the following are true: At the next clock edge * The current master is not running a transfer. * The new requesting master's priority level is higher than that of the current master. Both of the following are true: At the next arbitration point for the undefined length burst transfer Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 381 Initialization/application information Table 19-1. How the Crossbar Switch grants control of a slave port to a master (continued) When Then the Crossbar Switch grants control to the requesting master * The current master is running an undefined length burst transfer. * The requesting master's priority level is higher than that of the current master. The requesting master's priority level is lower than the current At the conclusion of one of the following cycles: master. * An IDLE cycle * A non-IDLE cycle to a location other than the current slave port 19.3.2.2 Round-robin priority operation When operating in round-robin mode, each master is assigned a relative priority based on the master port number. This relative priority is compared to the master port number (ID) of the last master to perform a transfer on the slave bus. The highest priority requesting master becomes owner of the slave bus at the next transfer boundary. Priority is based on how far ahead the ID of the requesting master is to the ID of the last master. After granted access to a slave port, a master may perform as many transfers as desired to that port until another master makes a request to the same slave port. The next master in line is granted access to the slave port at the next transfer boundary, or possibly on the next clock cycle if the current master has no pending access request. As an example of arbitration in round-robin mode, assume the crossbar is implemented with master ports 0, 1, 4, and 5. If the last master of the slave port was master 1, and master 0, 4, and 5 make simultaneous requests, they are serviced in the order: 4 then 5 then 0. The round-robin arbitration mode generally provides a more fair allocation of the available slave-port bandwidth (compared to fixed priority) as the fixed master priority does not affect the master selection. 19.4 Initialization/application information No initialization is required for the crossbar switch. See the AXBS section of the configuration chapter for the reset state of the arbitration scheme. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 382 Freescale Semiconductor, Inc. Chapter 20 Peripheral Bridge (AIPS-Lite) 20.1 Introduction NOTE For the chip-specific implementation details of this module's instances, see the chip configuration information. The peripheral bridge converts the crossbar switch interface to an interface that can access most of the slave peripherals on this chip. The peripheral bridge occupies 64 MB of the address space, which is divided into peripheral slots of 4 KB. (It might be possible that all the peripheral slots are not used. See the memory map chapter for details on slot assignments.) The bridge includes separate clock enable inputs for each of the slots to accommodate slower peripherals. 20.1.1 Features Key features of the peripheral bridge are: * Supports peripheral slots with 8-, 16-, and 32-bit datapath width 20.1.2 General operation The slave devices connected to the peripheral bridge are modules which contain a programming model of control and status registers. The system masters read and write these registers through the peripheral bridge. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 383 Memory map/register definition The register maps of the peripherals are located on 4-KB boundaries. Each peripheral is allocated one or more 4-KB block(s) of the memory map. Two global external module enables are available for the remaining address space to allow for customization and expansion of addressed peripheral devices. 20.2 Memory map/register definition The AIPS module(s) on this device do(es) not contain any user-programmable registers. 20.3 Functional description The peripheral bridge functions as a bus protocol translator between the crossbar switch and the slave peripheral bus. The peripheral bridge manages all transactions destined for the attached slave devices and generates select signals for modules on the peripheral bus by decoding accesses within the attached address space. 20.3.1 Access support Aligned and misaligned 32-bit, 16-bit, and byte accesses are supported for 32-bit peripherals. Misaligned accesses are supported to allow memory to be placed on the slave peripheral bus. Peripheral registers must not be misaligned, although no explicit checking is performed by the peripheral bridge. All accesses are performed with a single transfer. All accesses to the peripheral slots must be sized less than or equal to the designated peripheral slot size. If an access is attempted that is larger than the targeted port, an error response is generated. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 384 Freescale Semiconductor, Inc. Chapter 21 Direct Memory Access Multiplexer (DMAMUX) 21.1 Introduction NOTE For the chip-specific implementation details of this module's instances, see the chip configuration information. 21.1.1 Overview The Direct Memory Access Multiplexer (DMAMUX) routes DMA sources, called slots, to any of the 16 DMA channels. This process is illustrated in the following figure. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 385 Introduction DMAMUX Source #1 DMA channel #0 DMA channel #1 Source #2 Source #3 Source #x Always #1 Always #y Trigger #1 DMA channel #n Trigger #z Figure 21-1. DMAMUX block diagram 21.1.2 Features The DMAMUX module provides these features: * Up to 59 peripheral slots and up to four always-on slots can be routed to 16 channels. * 16 independently selectable DMA channel routers. * The first four channels additionally provide a trigger functionality. * Each channel router can be assigned to one of the possible peripheral DMA slots or to one of the always-on slots. 21.1.3 Modes of operation The following operating modes are available: * Disabled mode KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 386 Freescale Semiconductor, Inc. Chapter 21 Direct Memory Access Multiplexer (DMAMUX) In this mode, the DMA channel is disabled. Because disabling and enabling of DMA channels is done primarily via the DMA configuration registers, this mode is used mainly as the reset state for a DMA channel in the DMA channel MUX. It may also be used to temporarily suspend a DMA channel while reconfiguration of the system takes place, for example, changing the period of a DMA trigger. * Normal mode In this mode, a DMA source is routed directly to the specified DMA channel. The operation of the DMAMUX in this mode is completely transparent to the system. * Periodic Trigger mode In this mode, a DMA source may only request a DMA transfer, such as when a transmit buffer becomes empty or a receive buffer becomes full, periodically. Configuration of the period is done in the registers of the periodic interrupt timer (PIT). This mode is available only for channels 0-3. 21.2 External signal description The DMAMUX has no external pins. 21.3 Memory map/register definition This section provides a detailed description of all memory-mapped registers in the DMAMUX. DMAMUX memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4002_1000 Channel Configuration register (DMAMUX_CHCFG3) 8 R/W 00h 21.3.1/388 4002_1001 Channel Configuration register (DMAMUX_CHCFG2) 8 R/W 00h 21.3.1/388 4002_1002 Channel Configuration register (DMAMUX_CHCFG1) 8 R/W 00h 21.3.1/388 4002_1003 Channel Configuration register (DMAMUX_CHCFG0) 8 R/W 00h 21.3.1/388 4002_1004 Channel Configuration register (DMAMUX_CHCFG7) 8 R/W 00h 21.3.1/388 4002_1005 Channel Configuration register (DMAMUX_CHCFG6) 8 R/W 00h 21.3.1/388 4002_1006 Channel Configuration register (DMAMUX_CHCFG5) 8 R/W 00h 21.3.1/388 4002_1007 Channel Configuration register (DMAMUX_CHCFG4) 8 R/W 00h 21.3.1/388 4002_1008 Channel Configuration register (DMAMUX_CHCFG11) 8 R/W 00h 21.3.1/388 Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 387 Memory map/register definition DMAMUX memory map (continued) Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 4002_1009 Channel Configuration register (DMAMUX_CHCFG10) 8 R/W 00h 21.3.1/388 4002_100A Channel Configuration register (DMAMUX_CHCFG9) 8 R/W 00h 21.3.1/388 4002_100B Channel Configuration register (DMAMUX_CHCFG8) 8 R/W 00h 21.3.1/388 4002_100C Channel Configuration register (DMAMUX_CHCFG15) 8 R/W 00h 21.3.1/388 4002_100D Channel Configuration register (DMAMUX_CHCFG14) 8 R/W 00h 21.3.1/388 4002_100E Channel Configuration register (DMAMUX_CHCFG13) 8 R/W 00h 21.3.1/388 4002_100F Channel Configuration register (DMAMUX_CHCFG12) 8 R/W 00h 21.3.1/388 21.3.1 Channel Configuration register (DMAMUX_CHCFGn) Each of the DMA channels can be independently enabled/disabled and associated with one of the DMA slots (peripheral slots or always-on slots) in the system. NOTE Setting multiple CHCFG registers with the same source value will result in unpredictable behavior. This is true, even if a channel is disabled (ENBL==0). Before changing the trigger or source settings, a DMA channel must be disabled via CHCFGn[ENBL]. Address: 4002_1000h base + 0h offset + (1d x i), where i=0d to 15d Bit Read Write Reset 7 6 5 ENBL TRIG 0 0 4 3 2 1 0 0 0 0 SOURCE 0 0 0 DMAMUX_CHCFGn field descriptions Field 7 ENBL Description DMA Channel Enable Enables the DMA channel. 0 1 6 TRIG DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. DMA channel is enabled DMA Channel Trigger Enable Enables the periodic trigger capability for the triggered DMA channel. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 388 Freescale Semiconductor, Inc. Chapter 21 Direct Memory Access Multiplexer (DMAMUX) DMAMUX_CHCFGn field descriptions (continued) Field Description 0 1 SOURCE Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. DMA Channel Source (Slot) Specifies which DMA source, if any, is routed to a particular DMA channel. See the chip-specific DMAMUX information for details about the peripherals and their slot numbers. 21.4 Functional description The primary purpose of the DMAMUX is to provide flexibility in the system's use of the available DMA channels. As such, configuration of the DMAMUX is intended to be a static procedure done during execution of the system boot code. However, if the procedure outlined in Enabling and configuring sources is followed, the configuration of the DMAMUX may be changed during the normal operation of the system. Functionally, the DMAMUX channels may be divided into two classes: * Channels that implement the normal routing functionality plus periodic triggering capability * Channels that implement only the normal routing functionality 21.4.1 DMA channels with periodic triggering capability Besides the normal routing functionality, the first 4 channels of the DMAMUX provide a special periodic triggering capability that can be used to provide an automatic mechanism to transmit bytes, frames, or packets at fixed intervals without the need for processor intervention. The trigger is generated by the periodic interrupt timer (PIT); as such, the configuration of the periodic triggering interval is done via configuration registers in the PIT. See the section on periodic interrupt timer for more information on this topic. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 389 Functional description Note Because of the dynamic nature of the system (due to DMA channel priorities, bus arbitration, interrupt service routine lengths, etc.), the number of clock cycles between a trigger and the actual DMA transfer cannot be guaranteed. Source #1 Source #2 Source #3 Trigger #1 Source #x Always #1 Trigger #m DMA channel #0 DMA channel #m-1 Always #y Figure 21-2. DMAMUX triggered channels The DMA channel triggering capability allows the system to schedule regular DMA transfers, usually on the transmit side of certain peripherals, without the intervention of the processor. This trigger works by gating the request from the peripheral to the DMA until a trigger event has been seen. This is illustrated in the following figure. Peripheral request Trigger DMA request Figure 21-3. DMAMUX channel triggering: normal operation KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 390 Freescale Semiconductor, Inc. Chapter 21 Direct Memory Access Multiplexer (DMAMUX) After the DMA request has been serviced, the peripheral will negate its request, effectively resetting the gating mechanism until the peripheral reasserts its request and the next trigger event is seen. This means that if a trigger is seen, but the peripheral is not requesting a transfer, then that trigger will be ignored. This situation is illustrated in the following figure. Peripheral request Trigger DMA request Figure 21-4. DMAMUX channel triggering: ignored trigger This triggering capability may be used with any peripheral that supports DMA transfers, and is most useful for two types of situations: * Periodically polling external devices on a particular bus As an example, the transmit side of an SPI is assigned to a DMA channel with a trigger, as described above. After it has been set up, the SPI will request DMA transfers, presumably from memory, as long as its transmit buffer is empty. By using a trigger on this channel, the SPI transfers can be automatically performed every 5 s (as an example). On the receive side of the SPI, the SPI and DMA can be configured to transfer receive data into memory, effectively implementing a method to periodically read data from external devices and transfer the results into memory without processor intervention. * Using the GPIO ports to drive or sample waveforms By configuring the DMA to transfer data to one or more GPIO ports, it is possible to create complex waveforms using tabular data stored in on-chip memory. Conversely, using the DMA to periodically transfer data from one or more GPIO ports, it is possible to sample complex waveforms and store the results in tabular form in onchip memory. A more detailed description of the capability of each trigger, including resolution, range of values, and so on, may be found in the periodic interrupt timer section. 21.4.2 DMA channels with no triggering capability The other channels of the DMAMUX provide the normal routing functionality as described in Modes of operation. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 391 Functional description 21.4.3 Always-enabled DMA sources In addition to the peripherals that can be used as DMA sources, there are four additional DMA sources that are always enabled. Unlike the peripheral DMA sources, where the peripheral controls the flow of data during DMA transfers, the sources that are always enabled provide no such "throttling" of the data transfers. These sources are most useful in the following cases: * Performing DMA transfers to/from GPIO--Moving data from/to one or more GPIO pins, either unthrottled (that is, as fast as possible), or periodically (using the DMA triggering capability). * Performing DMA transfers from memory to memory--Moving data from memory to memory, typically as fast as possible, sometimes with software activation. * Performing DMA transfers from memory to the external bus, or vice-versa--Similar to memory to memory transfers, this is typically done as quickly as possible. * Any DMA transfer that requires software activation--Any DMA transfer that should be explicitly started by software. In cases where software should initiate the start of a DMA transfer, an always-enabled DMA source can be used to provide maximum flexibility. When activating a DMA channel via software, subsequent executions of the minor loop require that a new start event be sent. This can either be a new software activation, or a transfer request from the DMA channel MUX. The options for doing this are: * Transfer all data in a single minor loop. By configuring the DMA to transfer all of the data in a single minor loop (that is, major loop counter = 1), no reactivation of the channel is necessary. The disadvantage to this option is the reduced granularity in determining the load that the DMA transfer will impose on the system. For this option, the DMA channel must be disabled in the DMA channel MUX. * Use explicit software reactivation. In this option, the DMA is configured to transfer the data using both minor and major loops, but the processor is required to reactivate the channel by writing to the DMA registers after every minor loop. For this option, the DMA channel must be disabled in the DMA channel MUX. * Use an always-enabled DMA source. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 392 Freescale Semiconductor, Inc. Chapter 21 Direct Memory Access Multiplexer (DMAMUX) In this option, the DMA is configured to transfer the data using both minor and major loops, and the DMA channel MUX does the channel reactivation. For this option, the DMA channel should be enabled and pointing to an "always enabled" source. Note that the reactivation of the channel can be continuous (DMA triggering is disabled) or can use the DMA triggering capability. In this manner, it is possible to execute periodic transfers of packets of data from one source to another, without processor intervention. 21.5 Initialization/application information This section provides instructions for initializing the DMA channel MUX. 21.5.1 Reset The reset state of each individual bit is shown in Memory map/register definition. In summary, after reset, all channels are disabled and must be explicitly enabled before use. 21.5.2 Enabling and configuring sources To enable a source with periodic triggering: 1. Determine with which DMA channel the source will be associated. Note that only the first 4 DMA channels have periodic triggering capability. 2. Clear the CHCFG[ENBL] and CHCFG[TRIG] fields of the DMA channel. 3. Ensure that the DMA channel is properly configured in the DMA. The DMA channel may be enabled at this point. 4. Configure the corresponding timer. 5. Select the source to be routed to the DMA channel. Write to the corresponding CHCFG register, ensuring that the CHCFG[ENBL] and CHCFG[TRIG] fields are set. NOTE The following is an example. See the chip configuration details for the number of this device's DMA channels that have triggering capability. To configure source #5 transmit for use with DMA channel 1, with periodic triggering capability: 1. Write 0x00 to CHCFG1. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 393 Initialization/application information 2. Configure channel 1 in the DMA, including enabling the channel. 3. Configure a timer for the desired trigger interval. 4. Write 0xC5 to CHCFG1. The following code example illustrates steps 1 and 4 above: void DMAMUX_Init(uint8_t DMA_CH, uint8_t DMAMUX_SOURCE) { DMAMUX_0.CHCFG[DMA_CH].B.SOURCE = DMAMUX_SOURCE; DMAMUX_0.CHCFG[DMA_CH].B.ENBL = 1; DMAMUX_0.CHCFG[DMA_CH].B.TRIG = 1; } To enable a source, without periodic triggering: 1. Determine with which DMA channel the source will be associated. Note that only the first 4 DMA channels have periodic triggering capability. 2. Clear the CHCFG[ENBL] and CHCFG[TRIG] fields of the DMA channel. 3. Ensure that the DMA channel is properly configured in the DMA. The DMA channel may be enabled at this point. 4. Select the source to be routed to the DMA channel. Write to the corresponding CHCFG register, ensuring that CHCFG[ENBL] is set while CHCFG[TRIG] is cleared. NOTE The following is an example. See the chip configuration details for the number of this device's DMA channels that have triggering capability. To configure source #5 transmit for use with DMA channel 1, with no periodic triggering capability: 1. Write 0x00 to CHCFG1. 2. Configure channel 1 in the DMA, including enabling the channel. 3. Write 0x85 to CHCFG1. The following code example illustrates steps 1 and 3 above: In File registers.h: #define DMAMUX_BASE_ADDR 0x40021000/* Example only ! /* Following example assumes char is 8-bits */ volatile unsigned char *CHCFG0 = (volatile unsigned char volatile unsigned char *CHCFG1 = (volatile unsigned char volatile unsigned char *CHCFG2 = (volatile unsigned char volatile unsigned char *CHCFG3 = (volatile unsigned char volatile unsigned char *CHCFG4 = (volatile unsigned char volatile unsigned char *CHCFG5 = (volatile unsigned char volatile unsigned char *CHCFG6 = (volatile unsigned char volatile unsigned char *CHCFG7 = (volatile unsigned char volatile unsigned char *CHCFG8 = (volatile unsigned char volatile unsigned char *CHCFG9 = (volatile unsigned char volatile unsigned char *CHCFG10= (volatile unsigned char volatile unsigned char *CHCFG11= (volatile unsigned char volatile unsigned char *CHCFG12= (volatile unsigned char volatile unsigned char *CHCFG13= (volatile unsigned char */ *) *) *) *) *) *) *) *) *) *) *) *) *) *) (DMAMUX_BASE_ADDR+0x0003); (DMAMUX_BASE_ADDR+0x0002); (DMAMUX_BASE_ADDR+0x0001); (DMAMUX_BASE_ADDR+0x0000); (DMAMUX_BASE_ADDR+0x0007); (DMAMUX_BASE_ADDR+0x0006); (DMAMUX_BASE_ADDR+0x0005); (DMAMUX_BASE_ADDR+0x0004); (DMAMUX_BASE_ADDR+0x000B); (DMAMUX_BASE_ADDR+0x000A); (DMAMUX_BASE_ADDR+0x0009); (DMAMUX_BASE_ADDR+0x0008); (DMAMUX_BASE_ADDR+0x000F); (DMAMUX_BASE_ADDR+0x000E); KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 394 Freescale Semiconductor, Inc. Chapter 21 Direct Memory Access Multiplexer (DMAMUX) volatile unsigned char *CHCFG14= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000D); volatile unsigned char *CHCFG15= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000C); In File main.c: #include "registers.h" : : *CHCFG1 = 0x00; *CHCFG1 = 0x85; To disable a source: A particular DMA source may be disabled by not writing the corresponding source value into any of the CHCFG registers. Additionally, some module-specific configuration may be necessary. See the appropriate section for more details. To switch the source of a DMA channel: 1. Disable the DMA channel in the DMA and reconfigure the channel for the new source. 2. Clear the CHCFG[ENBL] and CHCFG[TRIG] bits of the DMA channel. 3. Select the source to be routed to the DMA channel. Write to the corresponding CHCFG register, ensuring that the CHCFG[ENBL] and CHCFG[TRIG] fields are set. To switch DMA channel 8 from source #5 transmit to source #7 transmit: 1. In the DMA configuration registers, disable DMA channel 8 and reconfigure it to handle the transfers to peripheral slot 7. This example assumes channel 8 doesn't have triggering capability. 2. Write 0x00 to CHCFG8. 3. Write 0x87 to CHCFG8. (In this example, setting CHCFG[TRIG] would have no effect due to the assumption that channel 8 does not support the periodic triggering functionality.) The following code example illustrates steps 2 and 3 above: In File registers.h: #define DMAMUX_BASE_ADDR 0x40021000/* Example only ! /* Following example assumes char is 8-bits */ volatile unsigned char *CHCFG0 = (volatile unsigned char volatile unsigned char *CHCFG1 = (volatile unsigned char volatile unsigned char *CHCFG2 = (volatile unsigned char volatile unsigned char *CHCFG3 = (volatile unsigned char volatile unsigned char *CHCFG4 = (volatile unsigned char volatile unsigned char *CHCFG5 = (volatile unsigned char volatile unsigned char *CHCFG6 = (volatile unsigned char volatile unsigned char *CHCFG7 = (volatile unsigned char volatile unsigned char *CHCFG8 = (volatile unsigned char volatile unsigned char *CHCFG9 = (volatile unsigned char volatile unsigned char *CHCFG10= (volatile unsigned char volatile unsigned char *CHCFG11= (volatile unsigned char volatile unsigned char *CHCFG12= (volatile unsigned char volatile unsigned char *CHCFG13= (volatile unsigned char volatile unsigned char *CHCFG14= (volatile unsigned char volatile unsigned char *CHCFG15= (volatile unsigned char */ *) *) *) *) *) *) *) *) *) *) *) *) *) *) *) *) (DMAMUX_BASE_ADDR+0x0003); (DMAMUX_BASE_ADDR+0x0002); (DMAMUX_BASE_ADDR+0x0001); (DMAMUX_BASE_ADDR+0x0000); (DMAMUX_BASE_ADDR+0x0007); (DMAMUX_BASE_ADDR+0x0006); (DMAMUX_BASE_ADDR+0x0005); (DMAMUX_BASE_ADDR+0x0004); (DMAMUX_BASE_ADDR+0x000B); (DMAMUX_BASE_ADDR+0x000A); (DMAMUX_BASE_ADDR+0x0009); (DMAMUX_BASE_ADDR+0x0008); (DMAMUX_BASE_ADDR+0x000F); (DMAMUX_BASE_ADDR+0x000E); (DMAMUX_BASE_ADDR+0x000D); (DMAMUX_BASE_ADDR+0x000C); KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 395 Initialization/application information In File main.c: #include "registers.h" : : *CHCFG8 = 0x00; *CHCFG8 = 0x87; KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 396 Freescale Semiconductor, Inc. Chapter 22 Enhanced Direct Memory Access (eDMA) 22.1 Introduction NOTE For the chip-specific implementation details of this module's instances, see the chip configuration information. The enhanced direct memory access (eDMA) controller is a second-generation module capable of performing complex data transfers with minimal intervention from a host processor. The hardware microarchitecture includes: * A DMA engine that performs: * Source address and destination address calculations * Data-movement operations * Local memory containing transfer control descriptors for each of the 16 channels 22.1.1 eDMA system block diagram Figure 22-1 illustrates the components of the eDMA system, including the eDMA module ("engine"). KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 397 Introduction eDMA system Write Address Write Data 0 Transfer Control Descriptor (TCD) n-1 64 eDMA e ngine Program Model/ Channel Arbitration Read Data Read Data Internal Peripheral Bus To/From Crossbar Switch 1 2 Address Path Control Data Path Write Data Address eDMA Peripheral Request eDMA Done Figure 22-1. eDMA system block diagram 22.1.2 Block parts The eDMA module is partitioned into two major modules: the eDMA engine and the transfer-control descriptor local memory. The eDMA engine is further partitioned into four submodules: Table 22-1. eDMA engine submodules Submodule Address path Function This block implements registered versions of two channel transfer control descriptors, channel x and channel y, and manages all master bus-address calculations. All the channels provide the same functionality. This structure allows data transfers associated with one channel to be preempted after the completion of a read/write sequence if a higher priority channel activation is asserted while the first channel is active. After a channel is activated, it runs until the minor loop is completed, unless preempted by a higher priority channel. This provides a mechanism (enabled by DCHPRIn[ECP]) where a large data move operation can be preempted to minimize the time another channel is blocked from execution. When any channel is selected to execute, the contents of its TCD are read from local memory and loaded into the address path channel x registers for a normal start and into channel y registers for a preemption start. After the minor loop completes execution, the address path hardware writes Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 398 Freescale Semiconductor, Inc. Chapter 22 Enhanced Direct Memory Access (eDMA) Table 22-1. eDMA engine submodules (continued) Submodule Function the new values for the TCDn_{SADDR, DADDR, CITER} back to local memory. If the major iteration count is exhausted, additional processing is performed, including the final address pointer updates, reloading the TCDn_CITER field, and a possible fetch of the next TCDn from memory as part of a scatter/gather operation. Data path This block implements the bus master read/write datapath. It includes a data buffer and the necessary multiplex logic to support any required data alignment. The internal read data bus is the primary input, and the internal write data bus is the primary output. The address and data path modules directly support the 2-stage pipelined internal bus. The address path module represents the 1st stage of the bus pipeline (address phase), while the data path module implements the 2nd stage of the pipeline (data phase). Program model/channel arbitration This block implements the first section of the eDMA programming model as well as the channel arbitration logic. The programming model registers are connected to the internal peripheral bus. The eDMA peripheral request inputs and interrupt request outputs are also connected to this block (via control logic). Control This block provides all the control functions for the eDMA engine. For data transfers where the source and destination sizes are equal, the eDMA engine performs a series of source read/ destination write operations until the number of bytes specified in the minor loop byte count has moved. For descriptors where the sizes are not equal, multiple accesses of the smaller size data are required for each reference of the larger size. As an example, if the source size references 16bit data and the destination is 32-bit data, two reads are performed, then one 32-bit write. The transfer-control descriptor local memory is further partitioned into: Table 22-2. Transfer control descriptor memory Submodule Description Memory controller This logic implements the required dual-ported controller, managing accesses from the eDMA engine as well as references from the internal peripheral bus. As noted earlier, in the event of simultaneous accesses, the eDMA engine is given priority and the peripheral transaction is stalled. Memory array TCD storage for each channel's transfer profile. 22.1.3 Features The eDMA is a highly programmable data-transfer engine optimized to minimize any required intervention from the host processor. It is intended for use in applications where the data size to be transferred is statically known and not defined within the transferred data itself. The eDMA module features: * All data movement via dual-address transfers: read from source, write to destination * Programmable source and destination addresses and transfer size * Support for enhanced addressing modes KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 399 Modes of operation * 16-channel implementation that performs complex data transfers with minimal intervention from a host processor * Internal data buffer, used as temporary storage to support 16- and 32-byte transfers * Connections to the crossbar switch for bus mastering the data movement * Transfer control descriptor (TCD) organized to support two-deep, nested transfer operations * 32-byte TCD stored in local memory for each channel * An inner data transfer loop defined by a minor byte transfer count * An outer data transfer loop defined by a major iteration count * Channel activation via one of three methods: * Explicit software initiation * Initiation via a channel-to-channel linking mechanism for continuous transfers * Peripheral-paced hardware requests, one per channel * Fixed-priority and round-robin channel arbitration * Channel completion reported via programmable interrupt requests * One interrupt per channel, which can be asserted at completion of major iteration count * Programmable error terminations per channel and logically summed together to form one error interrupt to the interrupt controller * Programmable support for scatter/gather DMA processing * Support for complex data structures In the discussion of this module, n is used to reference the channel number. 22.2 Modes of operation The eDMA operates in the following modes: KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 400 Freescale Semiconductor, Inc. Chapter 22 Enhanced Direct Memory Access (eDMA) Table 22-3. Modes of operation Mode Normal Description In Normal mode, the eDMA transfers data between a source and a destination. The source and destination can be a memory block or an I/O block capable of operation with the eDMA. A service request initiates a transfer of a specific number of bytes (NBYTES) as specified in the transfer control descriptor (TCD). The minor loop is the sequence of read-write operations that transfers these NBYTES per service request. Each service request executes one iteration of the major loop, which transfers NBYTES of data. Debug DMA operation is configurable in Debug mode via the control register: * If CR[EDBG] is cleared, the DMA continues to operate. * If CR[EDBG] is set, the eDMA stops transferring data. If Debug mode is entered while a channel is active, the eDMA continues operation until the channel retires. Wait Before entering Wait mode, the DMA attempts to complete its current transfer. After the transfer completes, the device enters Wait mode. 22.3 Memory map/register definition The eDMA's programming model is partitioned into two regions: * The first region defines a number of registers providing control functions * The second region corresponds to the local transfer control descriptor (TCD) memory 22.3.1 TCD memory Each channel requires a 32-byte transfer control descriptor for defining the desired data movement operation. The channel descriptors are stored in the local memory in sequential order: channel 0, channel 1, ... channel 15. Each TCDn definition is presented as 11 registers of 16 or 32 bits. 22.3.2 TCD initialization Prior to activating a channel, you must initialize its TCD with the appropriate transfer profile. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 401 Memory map/register definition 22.3.3 TCD structure 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 0000h SMOD SSIZE DSIZE DMOD 3 4 1 2 0 { SMLOE MLOFF or NBYTES DADDR CITER.E_LINK 0010h CITER or CITER.LINKCH { NBYTES SLAST CITER DMA_CR[EMLM] disabled DMA_CR[EMLM] enabled DOFF INT_MAJ START 5 INT_HALF 6 E_SG 7 D_REQ 8 MAJOR.E_LINK 9 DONE 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 ACTIVE BWC BITER MAJOR.LINKCH BITER.E_LINK BITER or BITER.LINKCH Reserved DLAST_SGA 0018h 001Ch 5 SOFF 000Ch 0014h 6 NBYTES DMLOE { 7 SADDR 0004h 0008h 8 9 4 3 2 1 0 22.3.4 Reserved memory and bit fields * Reading reserved bits in a register returns the value of zero. * Writes to reserved bits in a register are ignored. * Reading or writing a reserved memory location generates a bus error. DMA memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4000_8000 Control Register (DMA_CR) 32 R/W 0000_0000h 22.3.1/413 4000_8004 Error Status Register (DMA_ES) 32 R 0000_0000h 22.3.2/416 4000_800C Enable Request Register (DMA_ERQ) 32 R/W 0000_0000h 22.3.3/418 4000_8014 Enable Error Interrupt Register (DMA_EEI) 32 R/W 0000_0000h 22.3.4/420 4000_8018 Clear Enable Error Interrupt Register (DMA_CEEI) 8 W (always reads 0) 00h 22.3.5/422 4000_8019 Set Enable Error Interrupt Register (DMA_SEEI) 8 W (always reads 0) 00h 22.3.6/423 Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 402 Freescale Semiconductor, Inc. Chapter 22 Enhanced Direct Memory Access (eDMA) DMA memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4000_801A Clear Enable Request Register (DMA_CERQ) 8 W (always reads 0) 00h 22.3.7/424 4000_801B Set Enable Request Register (DMA_SERQ) 8 W (always reads 0) 00h 22.3.8/425 4000_801C Clear DONE Status Bit Register (DMA_CDNE) 8 W (always reads 0) 00h 22.3.9/426 4000_801D Set START Bit Register (DMA_SSRT) 8 W (always reads 0) 00h 22.3.10/427 4000_801E Clear Error Register (DMA_CERR) 8 W (always reads 0) 00h 22.3.11/428 4000_801F Clear Interrupt Request Register (DMA_CINT) 8 W (always reads 0) 00h 22.3.12/429 4000_8024 Interrupt Request Register (DMA_INT) 32 R/W 0000_0000h 22.3.13/430 4000_802C Error Register (DMA_ERR) 32 R/W 0000_0000h 22.3.14/432 4000_8034 Hardware Request Status Register (DMA_HRS) 32 R 0000_0000h 22.3.15/435 4000_8044 Enable Asynchronous Request in Stop Register (DMA_EARS) 32 R/W 0000_0000h 22.3.16/438 4000_8100 Channel n Priority Register (DMA_DCHPRI3) 8 R/W See section 22.3.17/440 4000_8101 Channel n Priority Register (DMA_DCHPRI2) 8 R/W See section 22.3.17/440 4000_8102 Channel n Priority Register (DMA_DCHPRI1) 8 R/W See section 22.3.17/440 4000_8103 Channel n Priority Register (DMA_DCHPRI0) 8 R/W See section 22.3.17/440 4000_8104 Channel n Priority Register (DMA_DCHPRI7) 8 R/W See section 22.3.17/440 4000_8105 Channel n Priority Register (DMA_DCHPRI6) 8 R/W See section 22.3.17/440 4000_8106 Channel n Priority Register (DMA_DCHPRI5) 8 R/W See section 22.3.17/440 4000_8107 Channel n Priority Register (DMA_DCHPRI4) 8 R/W See section 22.3.17/440 4000_8108 Channel n Priority Register (DMA_DCHPRI11) 8 R/W See section 22.3.17/440 4000_8109 Channel n Priority Register (DMA_DCHPRI10) 8 R/W See section 22.3.17/440 4000_810A Channel n Priority Register (DMA_DCHPRI9) 8 R/W See section 22.3.17/440 4000_810B Channel n Priority Register (DMA_DCHPRI8) 8 R/W See section 22.3.17/440 4000_810C Channel n Priority Register (DMA_DCHPRI15) 8 R/W See section 22.3.17/440 4000_810D Channel n Priority Register (DMA_DCHPRI14) 8 R/W See section 22.3.17/440 4000_810E Channel n Priority Register (DMA_DCHPRI13) 8 R/W See section 22.3.17/440 4000_810F Channel n Priority Register (DMA_DCHPRI12) 8 R/W See section 22.3.17/440 4000_9000 TCD Source Address (DMA_TCD0_SADDR) 32 R/W Undefined 22.3.18/441 4000_9004 TCD Signed Source Address Offset (DMA_TCD0_SOFF) 16 R/W Undefined 22.3.19/441 4000_9006 TCD Transfer Attributes (DMA_TCD0_ATTR) 16 R/W Undefined 22.3.20/442 Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 403 Memory map/register definition DMA memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4000_9008 TCD Minor Byte Count (Minor Loop Mapping Disabled) (DMA_TCD0_NBYTES_MLNO) 32 R/W Undefined 22.3.21/443 4000_9008 TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) (DMA_TCD0_NBYTES_MLOFFNO) 32 R/W Undefined 22.3.22/444 4000_9008 TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) (DMA_TCD0_NBYTES_MLOFFYES) 32 R/W Undefined 22.3.23/445 4000_900C TCD Last Source Address Adjustment (DMA_TCD0_SLAST) 32 R/W Undefined 22.3.24/446 4000_9010 TCD Destination Address (DMA_TCD0_DADDR) 32 R/W Undefined 22.3.25/447 4000_9014 TCD Signed Destination Address Offset (DMA_TCD0_DOFF) 16 R/W Undefined 22.3.26/447 4000_9016 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD0_CITER_ELINKYES) 16 R/W Undefined 22.3.27/448 4000_9016 DMA_TCD0_CITER_ELINKNO 16 R/W Undefined 22.3.28/449 4000_9018 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCD0_DLASTSGA) 32 R/W Undefined 22.3.29/450 4000_901C TCD Control and Status (DMA_TCD0_CSR) 16 R/W Undefined 22.3.30/451 4000_901E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD0_BITER_ELINKYES) 16 R/W Undefined 22.3.31/453 4000_901E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCD0_BITER_ELINKNO) 16 R/W Undefined 22.3.32/454 4000_9020 TCD Source Address (DMA_TCD1_SADDR) 32 R/W Undefined 22.3.18/441 4000_9024 TCD Signed Source Address Offset (DMA_TCD1_SOFF) 16 R/W Undefined 22.3.19/441 4000_9026 TCD Transfer Attributes (DMA_TCD1_ATTR) 16 R/W Undefined 22.3.20/442 4000_9028 TCD Minor Byte Count (Minor Loop Mapping Disabled) (DMA_TCD1_NBYTES_MLNO) 32 R/W Undefined 22.3.21/443 4000_9028 TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) (DMA_TCD1_NBYTES_MLOFFNO) 32 R/W Undefined 22.3.22/444 4000_9028 TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) (DMA_TCD1_NBYTES_MLOFFYES) 32 R/W Undefined 22.3.23/445 4000_902C TCD Last Source Address Adjustment (DMA_TCD1_SLAST) 32 R/W Undefined 22.3.24/446 4000_9030 TCD Destination Address (DMA_TCD1_DADDR) 32 R/W Undefined 22.3.25/447 4000_9034 TCD Signed Destination Address Offset (DMA_TCD1_DOFF) 16 R/W Undefined 22.3.26/447 4000_9036 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD1_CITER_ELINKYES) 16 R/W Undefined 22.3.27/448 4000_9036 DMA_TCD1_CITER_ELINKNO 16 R/W Undefined 22.3.28/449 4000_9038 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCD1_DLASTSGA) 32 R/W Undefined 22.3.29/450 Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 404 Freescale Semiconductor, Inc. Chapter 22 Enhanced Direct Memory Access (eDMA) DMA memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4000_903C TCD Control and Status (DMA_TCD1_CSR) 16 R/W Undefined 22.3.30/451 4000_903E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD1_BITER_ELINKYES) 16 R/W Undefined 22.3.31/453 4000_903E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCD1_BITER_ELINKNO) 16 R/W Undefined 22.3.32/454 4000_9040 TCD Source Address (DMA_TCD2_SADDR) 32 R/W Undefined 22.3.18/441 4000_9044 TCD Signed Source Address Offset (DMA_TCD2_SOFF) 16 R/W Undefined 22.3.19/441 4000_9046 TCD Transfer Attributes (DMA_TCD2_ATTR) 16 R/W Undefined 22.3.20/442 4000_9048 TCD Minor Byte Count (Minor Loop Mapping Disabled) (DMA_TCD2_NBYTES_MLNO) 32 R/W Undefined 22.3.21/443 4000_9048 TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) (DMA_TCD2_NBYTES_MLOFFNO) 32 R/W Undefined 22.3.22/444 4000_9048 TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) (DMA_TCD2_NBYTES_MLOFFYES) 32 R/W Undefined 22.3.23/445 4000_904C TCD Last Source Address Adjustment (DMA_TCD2_SLAST) 32 R/W Undefined 22.3.24/446 4000_9050 TCD Destination Address (DMA_TCD2_DADDR) 32 R/W Undefined 22.3.25/447 4000_9054 TCD Signed Destination Address Offset (DMA_TCD2_DOFF) 16 R/W Undefined 22.3.26/447 4000_9056 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD2_CITER_ELINKYES) 16 R/W Undefined 22.3.27/448 4000_9056 DMA_TCD2_CITER_ELINKNO 16 R/W Undefined 22.3.28/449 4000_9058 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCD2_DLASTSGA) 32 R/W Undefined 22.3.29/450 4000_905C TCD Control and Status (DMA_TCD2_CSR) 16 R/W Undefined 22.3.30/451 4000_905E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD2_BITER_ELINKYES) 16 R/W Undefined 22.3.31/453 4000_905E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCD2_BITER_ELINKNO) 16 R/W Undefined 22.3.32/454 4000_9060 TCD Source Address (DMA_TCD3_SADDR) 32 R/W Undefined 22.3.18/441 4000_9064 TCD Signed Source Address Offset (DMA_TCD3_SOFF) 16 R/W Undefined 22.3.19/441 4000_9066 TCD Transfer Attributes (DMA_TCD3_ATTR) 16 R/W Undefined 22.3.20/442 4000_9068 TCD Minor Byte Count (Minor Loop Mapping Disabled) (DMA_TCD3_NBYTES_MLNO) 32 R/W Undefined 22.3.21/443 4000_9068 TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) (DMA_TCD3_NBYTES_MLOFFNO) 32 R/W Undefined 22.3.22/444 4000_9068 TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) (DMA_TCD3_NBYTES_MLOFFYES) 32 R/W Undefined 22.3.23/445 Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 405 Memory map/register definition DMA memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4000_906C TCD Last Source Address Adjustment (DMA_TCD3_SLAST) 32 R/W Undefined 22.3.24/446 4000_9070 TCD Destination Address (DMA_TCD3_DADDR) 32 R/W Undefined 22.3.25/447 4000_9074 TCD Signed Destination Address Offset (DMA_TCD3_DOFF) 16 R/W Undefined 22.3.26/447 4000_9076 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD3_CITER_ELINKYES) 16 R/W Undefined 22.3.27/448 4000_9076 DMA_TCD3_CITER_ELINKNO 16 R/W Undefined 22.3.28/449 4000_9078 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCD3_DLASTSGA) 32 R/W Undefined 22.3.29/450 4000_907C TCD Control and Status (DMA_TCD3_CSR) 16 R/W Undefined 22.3.30/451 4000_907E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD3_BITER_ELINKYES) 16 R/W Undefined 22.3.31/453 4000_907E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCD3_BITER_ELINKNO) 16 R/W Undefined 22.3.32/454 4000_9080 TCD Source Address (DMA_TCD4_SADDR) 32 R/W Undefined 22.3.18/441 4000_9084 TCD Signed Source Address Offset (DMA_TCD4_SOFF) 16 R/W Undefined 22.3.19/441 4000_9086 TCD Transfer Attributes (DMA_TCD4_ATTR) 16 R/W Undefined 22.3.20/442 4000_9088 TCD Minor Byte Count (Minor Loop Mapping Disabled) (DMA_TCD4_NBYTES_MLNO) 32 R/W Undefined 22.3.21/443 4000_9088 TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) (DMA_TCD4_NBYTES_MLOFFNO) 32 R/W Undefined 22.3.22/444 4000_9088 TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) (DMA_TCD4_NBYTES_MLOFFYES) 32 R/W Undefined 22.3.23/445 4000_908C TCD Last Source Address Adjustment (DMA_TCD4_SLAST) 32 R/W Undefined 22.3.24/446 4000_9090 TCD Destination Address (DMA_TCD4_DADDR) 32 R/W Undefined 22.3.25/447 4000_9094 TCD Signed Destination Address Offset (DMA_TCD4_DOFF) 16 R/W Undefined 22.3.26/447 4000_9096 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD4_CITER_ELINKYES) 16 R/W Undefined 22.3.27/448 4000_9096 DMA_TCD4_CITER_ELINKNO 16 R/W Undefined 22.3.28/449 4000_9098 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCD4_DLASTSGA) 32 R/W Undefined 22.3.29/450 4000_909C TCD Control and Status (DMA_TCD4_CSR) 16 R/W Undefined 22.3.30/451 4000_909E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD4_BITER_ELINKYES) 16 R/W Undefined 22.3.31/453 4000_909E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCD4_BITER_ELINKNO) 16 R/W Undefined 22.3.32/454 4000_90A0 TCD Source Address (DMA_TCD5_SADDR) 32 R/W Undefined 22.3.18/441 Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 406 Freescale Semiconductor, Inc. Chapter 22 Enhanced Direct Memory Access (eDMA) DMA memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4000_90A4 TCD Signed Source Address Offset (DMA_TCD5_SOFF) 16 R/W Undefined 22.3.19/441 4000_90A6 TCD Transfer Attributes (DMA_TCD5_ATTR) 16 R/W Undefined 22.3.20/442 4000_90A8 TCD Minor Byte Count (Minor Loop Mapping Disabled) (DMA_TCD5_NBYTES_MLNO) 32 R/W Undefined 22.3.21/443 4000_90A8 TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) (DMA_TCD5_NBYTES_MLOFFNO) 32 R/W Undefined 22.3.22/444 4000_90A8 TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) (DMA_TCD5_NBYTES_MLOFFYES) 32 R/W Undefined 22.3.23/445 4000_90AC TCD Last Source Address Adjustment (DMA_TCD5_SLAST) 32 R/W Undefined 22.3.24/446 4000_90B0 TCD Destination Address (DMA_TCD5_DADDR) 32 R/W Undefined 22.3.25/447 4000_90B4 TCD Signed Destination Address Offset (DMA_TCD5_DOFF) 16 R/W Undefined 22.3.26/447 4000_90B6 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD5_CITER_ELINKYES) 16 R/W Undefined 22.3.27/448 4000_90B6 DMA_TCD5_CITER_ELINKNO 16 R/W Undefined 22.3.28/449 4000_90B8 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCD5_DLASTSGA) 32 R/W Undefined 22.3.29/450 4000_90BC TCD Control and Status (DMA_TCD5_CSR) 16 R/W Undefined 22.3.30/451 TCD Beginning Minor Loop Link, Major Loop Count 4000_90BE (Channel Linking Enabled) (DMA_TCD5_BITER_ELINKYES) 16 R/W Undefined 22.3.31/453 4000_90BE TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCD5_BITER_ELINKNO) 16 R/W Undefined 22.3.32/454 4000_90C0 TCD Source Address (DMA_TCD6_SADDR) 32 R/W Undefined 22.3.18/441 4000_90C4 TCD Signed Source Address Offset (DMA_TCD6_SOFF) 16 R/W Undefined 22.3.19/441 4000_90C6 TCD Transfer Attributes (DMA_TCD6_ATTR) 16 R/W Undefined 22.3.20/442 4000_90C8 TCD Minor Byte Count (Minor Loop Mapping Disabled) (DMA_TCD6_NBYTES_MLNO) 32 R/W Undefined 22.3.21/443 4000_90C8 TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) (DMA_TCD6_NBYTES_MLOFFNO) 32 R/W Undefined 22.3.22/444 4000_90C8 TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) (DMA_TCD6_NBYTES_MLOFFYES) 32 R/W Undefined 22.3.23/445 4000_90CC TCD Last Source Address Adjustment (DMA_TCD6_SLAST) 32 R/W Undefined 22.3.24/446 4000_90D0 TCD Destination Address (DMA_TCD6_DADDR) 32 R/W Undefined 22.3.25/447 4000_90D4 TCD Signed Destination Address Offset (DMA_TCD6_DOFF) 16 R/W Undefined 22.3.26/447 4000_90D6 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD6_CITER_ELINKYES) 16 R/W Undefined 22.3.27/448 4000_90D6 DMA_TCD6_CITER_ELINKNO 16 R/W Undefined 22.3.28/449 Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 407 Memory map/register definition DMA memory map (continued) Absolute address (hex) 4000_90D8 Register name TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCD6_DLASTSGA) Width Access (in bits) Reset value Section/ page 32 R/W Undefined 22.3.29/450 4000_90DC TCD Control and Status (DMA_TCD6_CSR) 16 R/W Undefined 22.3.30/451 TCD Beginning Minor Loop Link, Major Loop Count 4000_90DE (Channel Linking Enabled) (DMA_TCD6_BITER_ELINKYES) 16 R/W Undefined 22.3.31/453 4000_90DE TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCD6_BITER_ELINKNO) 16 R/W Undefined 22.3.32/454 4000_90E0 TCD Source Address (DMA_TCD7_SADDR) 32 R/W Undefined 22.3.18/441 4000_90E4 TCD Signed Source Address Offset (DMA_TCD7_SOFF) 16 R/W Undefined 22.3.19/441 4000_90E6 TCD Transfer Attributes (DMA_TCD7_ATTR) 16 R/W Undefined 22.3.20/442 4000_90E8 TCD Minor Byte Count (Minor Loop Mapping Disabled) (DMA_TCD7_NBYTES_MLNO) 32 R/W Undefined 22.3.21/443 4000_90E8 TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) (DMA_TCD7_NBYTES_MLOFFNO) 32 R/W Undefined 22.3.22/444 4000_90E8 TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) (DMA_TCD7_NBYTES_MLOFFYES) 32 R/W Undefined 22.3.23/445 4000_90EC TCD Last Source Address Adjustment (DMA_TCD7_SLAST) 32 R/W Undefined 22.3.24/446 4000_90F0 TCD Destination Address (DMA_TCD7_DADDR) 32 R/W Undefined 22.3.25/447 4000_90F4 TCD Signed Destination Address Offset (DMA_TCD7_DOFF) 16 R/W Undefined 22.3.26/447 4000_90F6 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD7_CITER_ELINKYES) 16 R/W Undefined 22.3.27/448 4000_90F6 DMA_TCD7_CITER_ELINKNO 16 R/W Undefined 22.3.28/449 4000_90F8 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCD7_DLASTSGA) 32 R/W Undefined 22.3.29/450 16 R/W Undefined 22.3.30/451 4000_90FC TCD Control and Status (DMA_TCD7_CSR) 4000_90FE TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD7_BITER_ELINKYES) 16 R/W Undefined 22.3.31/453 4000_90FE TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCD7_BITER_ELINKNO) 16 R/W Undefined 22.3.32/454 4000_9100 TCD Source Address (DMA_TCD8_SADDR) 32 R/W Undefined 22.3.18/441 4000_9104 TCD Signed Source Address Offset (DMA_TCD8_SOFF) 16 R/W Undefined 22.3.19/441 4000_9106 TCD Transfer Attributes (DMA_TCD8_ATTR) 16 R/W Undefined 22.3.20/442 4000_9108 TCD Minor Byte Count (Minor Loop Mapping Disabled) (DMA_TCD8_NBYTES_MLNO) 32 R/W Undefined 22.3.21/443 4000_9108 TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) (DMA_TCD8_NBYTES_MLOFFNO) 32 R/W Undefined 22.3.22/444 Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 408 Freescale Semiconductor, Inc. Chapter 22 Enhanced Direct Memory Access (eDMA) DMA memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4000_9108 TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) (DMA_TCD8_NBYTES_MLOFFYES) 32 R/W Undefined 22.3.23/445 4000_910C TCD Last Source Address Adjustment (DMA_TCD8_SLAST) 32 R/W Undefined 22.3.24/446 4000_9110 TCD Destination Address (DMA_TCD8_DADDR) 32 R/W Undefined 22.3.25/447 4000_9114 TCD Signed Destination Address Offset (DMA_TCD8_DOFF) 16 R/W Undefined 22.3.26/447 4000_9116 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD8_CITER_ELINKYES) 16 R/W Undefined 22.3.27/448 4000_9116 DMA_TCD8_CITER_ELINKNO 16 R/W Undefined 22.3.28/449 4000_9118 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCD8_DLASTSGA) 32 R/W Undefined 22.3.29/450 4000_911C TCD Control and Status (DMA_TCD8_CSR) 16 R/W Undefined 22.3.30/451 4000_911E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD8_BITER_ELINKYES) 16 R/W Undefined 22.3.31/453 4000_911E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCD8_BITER_ELINKNO) 16 R/W Undefined 22.3.32/454 4000_9120 TCD Source Address (DMA_TCD9_SADDR) 32 R/W Undefined 22.3.18/441 4000_9124 TCD Signed Source Address Offset (DMA_TCD9_SOFF) 16 R/W Undefined 22.3.19/441 4000_9126 TCD Transfer Attributes (DMA_TCD9_ATTR) 16 R/W Undefined 22.3.20/442 4000_9128 TCD Minor Byte Count (Minor Loop Mapping Disabled) (DMA_TCD9_NBYTES_MLNO) 32 R/W Undefined 22.3.21/443 4000_9128 TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) (DMA_TCD9_NBYTES_MLOFFNO) 32 R/W Undefined 22.3.22/444 4000_9128 TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) (DMA_TCD9_NBYTES_MLOFFYES) 32 R/W Undefined 22.3.23/445 4000_912C TCD Last Source Address Adjustment (DMA_TCD9_SLAST) 32 R/W Undefined 22.3.24/446 4000_9130 TCD Destination Address (DMA_TCD9_DADDR) 32 R/W Undefined 22.3.25/447 4000_9134 TCD Signed Destination Address Offset (DMA_TCD9_DOFF) 16 R/W Undefined 22.3.26/447 4000_9136 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD9_CITER_ELINKYES) 16 R/W Undefined 22.3.27/448 4000_9136 DMA_TCD9_CITER_ELINKNO 16 R/W Undefined 22.3.28/449 4000_9138 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCD9_DLASTSGA) 32 R/W Undefined 22.3.29/450 4000_913C TCD Control and Status (DMA_TCD9_CSR) 16 R/W Undefined 22.3.30/451 4000_913E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD9_BITER_ELINKYES) 16 R/W Undefined 22.3.31/453 Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 409 Memory map/register definition DMA memory map (continued) Absolute address (hex) Register name 4000_913E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCD9_BITER_ELINKNO) 16 4000_9140 TCD Source Address (DMA_TCD10_SADDR) 4000_9144 TCD Signed Source Address Offset (DMA_TCD10_SOFF) 4000_9146 Width Access (in bits) Reset value Section/ page R/W Undefined 22.3.32/454 32 R/W Undefined 22.3.18/441 16 R/W Undefined 22.3.19/441 TCD Transfer Attributes (DMA_TCD10_ATTR) 16 R/W Undefined 22.3.20/442 4000_9148 TCD Minor Byte Count (Minor Loop Mapping Disabled) (DMA_TCD10_NBYTES_MLNO) 32 R/W Undefined 22.3.21/443 4000_9148 TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) (DMA_TCD10_NBYTES_MLOFFNO) 32 R/W Undefined 22.3.22/444 4000_9148 TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) (DMA_TCD10_NBYTES_MLOFFYES) 32 R/W Undefined 22.3.23/445 4000_914C TCD Last Source Address Adjustment (DMA_TCD10_SLAST) 32 R/W Undefined 22.3.24/446 4000_9150 TCD Destination Address (DMA_TCD10_DADDR) 32 R/W Undefined 22.3.25/447 4000_9154 TCD Signed Destination Address Offset (DMA_TCD10_DOFF) 16 R/W Undefined 22.3.26/447 4000_9156 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD10_CITER_ELINKYES) 16 R/W Undefined 22.3.27/448 4000_9156 DMA_TCD10_CITER_ELINKNO 16 R/W Undefined 22.3.28/449 4000_9158 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCD10_DLASTSGA) 32 R/W Undefined 22.3.29/450 4000_915C TCD Control and Status (DMA_TCD10_CSR) 16 R/W Undefined 22.3.30/451 4000_915E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD10_BITER_ELINKYES) 16 R/W Undefined 22.3.31/453 4000_915E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCD10_BITER_ELINKNO) 16 R/W Undefined 22.3.32/454 4000_9160 TCD Source Address (DMA_TCD11_SADDR) 32 R/W Undefined 22.3.18/441 4000_9164 TCD Signed Source Address Offset (DMA_TCD11_SOFF) 16 R/W Undefined 22.3.19/441 4000_9166 TCD Transfer Attributes (DMA_TCD11_ATTR) 16 R/W Undefined 22.3.20/442 4000_9168 TCD Minor Byte Count (Minor Loop Mapping Disabled) (DMA_TCD11_NBYTES_MLNO) 32 R/W Undefined 22.3.21/443 4000_9168 TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) (DMA_TCD11_NBYTES_MLOFFNO) 32 R/W Undefined 22.3.22/444 4000_9168 TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) (DMA_TCD11_NBYTES_MLOFFYES) 32 R/W Undefined 22.3.23/445 4000_916C TCD Last Source Address Adjustment (DMA_TCD11_SLAST) 32 R/W Undefined 22.3.24/446 4000_9170 TCD Destination Address (DMA_TCD11_DADDR) 32 R/W Undefined 22.3.25/447 Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 410 Freescale Semiconductor, Inc. Chapter 22 Enhanced Direct Memory Access (eDMA) DMA memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4000_9174 TCD Signed Destination Address Offset (DMA_TCD11_DOFF) 16 R/W Undefined 22.3.26/447 4000_9176 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD11_CITER_ELINKYES) 16 R/W Undefined 22.3.27/448 4000_9176 DMA_TCD11_CITER_ELINKNO 16 R/W Undefined 22.3.28/449 4000_9178 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCD11_DLASTSGA) 32 R/W Undefined 22.3.29/450 4000_917C TCD Control and Status (DMA_TCD11_CSR) 16 R/W Undefined 22.3.30/451 4000_917E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD11_BITER_ELINKYES) 16 R/W Undefined 22.3.31/453 4000_917E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCD11_BITER_ELINKNO) 16 R/W Undefined 22.3.32/454 4000_9180 TCD Source Address (DMA_TCD12_SADDR) 32 R/W Undefined 22.3.18/441 4000_9184 TCD Signed Source Address Offset (DMA_TCD12_SOFF) 16 R/W Undefined 22.3.19/441 4000_9186 TCD Transfer Attributes (DMA_TCD12_ATTR) 16 R/W Undefined 22.3.20/442 4000_9188 TCD Minor Byte Count (Minor Loop Mapping Disabled) (DMA_TCD12_NBYTES_MLNO) 32 R/W Undefined 22.3.21/443 4000_9188 TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) (DMA_TCD12_NBYTES_MLOFFNO) 32 R/W Undefined 22.3.22/444 4000_9188 TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) (DMA_TCD12_NBYTES_MLOFFYES) 32 R/W Undefined 22.3.23/445 4000_918C TCD Last Source Address Adjustment (DMA_TCD12_SLAST) 32 R/W Undefined 22.3.24/446 4000_9190 TCD Destination Address (DMA_TCD12_DADDR) 32 R/W Undefined 22.3.25/447 4000_9194 TCD Signed Destination Address Offset (DMA_TCD12_DOFF) 16 R/W Undefined 22.3.26/447 4000_9196 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD12_CITER_ELINKYES) 16 R/W Undefined 22.3.27/448 4000_9196 DMA_TCD12_CITER_ELINKNO 16 R/W Undefined 22.3.28/449 4000_9198 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCD12_DLASTSGA) 32 R/W Undefined 22.3.29/450 4000_919C TCD Control and Status (DMA_TCD12_CSR) 16 R/W Undefined 22.3.30/451 4000_919E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD12_BITER_ELINKYES) 16 R/W Undefined 22.3.31/453 4000_919E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCD12_BITER_ELINKNO) 16 R/W Undefined 22.3.32/454 4000_91A0 TCD Source Address (DMA_TCD13_SADDR) 32 R/W Undefined 22.3.18/441 4000_91A4 TCD Signed Source Address Offset (DMA_TCD13_SOFF) 16 R/W Undefined 22.3.19/441 Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 411 Memory map/register definition DMA memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4000_91A6 TCD Transfer Attributes (DMA_TCD13_ATTR) 16 R/W Undefined 22.3.20/442 4000_91A8 TCD Minor Byte Count (Minor Loop Mapping Disabled) (DMA_TCD13_NBYTES_MLNO) 32 R/W Undefined 22.3.21/443 4000_91A8 TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) (DMA_TCD13_NBYTES_MLOFFNO) 32 R/W Undefined 22.3.22/444 4000_91A8 TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) (DMA_TCD13_NBYTES_MLOFFYES) 32 R/W Undefined 22.3.23/445 4000_91AC TCD Last Source Address Adjustment (DMA_TCD13_SLAST) 32 R/W Undefined 22.3.24/446 4000_91B0 TCD Destination Address (DMA_TCD13_DADDR) 32 R/W Undefined 22.3.25/447 4000_91B4 TCD Signed Destination Address Offset (DMA_TCD13_DOFF) 16 R/W Undefined 22.3.26/447 4000_91B6 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD13_CITER_ELINKYES) 16 R/W Undefined 22.3.27/448 4000_91B6 DMA_TCD13_CITER_ELINKNO 16 R/W Undefined 22.3.28/449 4000_91B8 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCD13_DLASTSGA) 32 R/W Undefined 22.3.29/450 4000_91BC TCD Control and Status (DMA_TCD13_CSR) 16 R/W Undefined 22.3.30/451 TCD Beginning Minor Loop Link, Major Loop Count 4000_91BE (Channel Linking Enabled) (DMA_TCD13_BITER_ELINKYES) 16 R/W Undefined 22.3.31/453 TCD Beginning Minor Loop Link, Major Loop Count 4000_91BE (Channel Linking Disabled) (DMA_TCD13_BITER_ELINKNO) 16 R/W Undefined 22.3.32/454 4000_91C0 TCD Source Address (DMA_TCD14_SADDR) 32 R/W Undefined 22.3.18/441 4000_91C4 TCD Signed Source Address Offset (DMA_TCD14_SOFF) 16 R/W Undefined 22.3.19/441 4000_91C6 TCD Transfer Attributes (DMA_TCD14_ATTR) 16 R/W Undefined 22.3.20/442 4000_91C8 TCD Minor Byte Count (Minor Loop Mapping Disabled) (DMA_TCD14_NBYTES_MLNO) 32 R/W Undefined 22.3.21/443 4000_91C8 TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) (DMA_TCD14_NBYTES_MLOFFNO) 32 R/W Undefined 22.3.22/444 4000_91C8 TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) (DMA_TCD14_NBYTES_MLOFFYES) 32 R/W Undefined 22.3.23/445 4000_91CC TCD Last Source Address Adjustment (DMA_TCD14_SLAST) 32 R/W Undefined 22.3.24/446 4000_91D0 TCD Destination Address (DMA_TCD14_DADDR) 32 R/W Undefined 22.3.25/447 4000_91D4 TCD Signed Destination Address Offset (DMA_TCD14_DOFF) 16 R/W Undefined 22.3.26/447 4000_91D6 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD14_CITER_ELINKYES) 16 R/W Undefined 22.3.27/448 4000_91D6 DMA_TCD14_CITER_ELINKNO 16 R/W Undefined 22.3.28/449 Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 412 Freescale Semiconductor, Inc. Chapter 22 Enhanced Direct Memory Access (eDMA) DMA memory map (continued) Absolute address (hex) 4000_91D8 Register name TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCD14_DLASTSGA) Width Access (in bits) Reset value Section/ page 32 R/W Undefined 22.3.29/450 4000_91DC TCD Control and Status (DMA_TCD14_CSR) 16 R/W Undefined 22.3.30/451 TCD Beginning Minor Loop Link, Major Loop Count 4000_91DE (Channel Linking Enabled) (DMA_TCD14_BITER_ELINKYES) 16 R/W Undefined 22.3.31/453 TCD Beginning Minor Loop Link, Major Loop Count 4000_91DE (Channel Linking Disabled) (DMA_TCD14_BITER_ELINKNO) 16 R/W Undefined 22.3.32/454 4000_91E0 TCD Source Address (DMA_TCD15_SADDR) 32 R/W Undefined 22.3.18/441 4000_91E4 TCD Signed Source Address Offset (DMA_TCD15_SOFF) 16 R/W Undefined 22.3.19/441 4000_91E6 TCD Transfer Attributes (DMA_TCD15_ATTR) 16 R/W Undefined 22.3.20/442 4000_91E8 TCD Minor Byte Count (Minor Loop Mapping Disabled) (DMA_TCD15_NBYTES_MLNO) 32 R/W Undefined 22.3.21/443 4000_91E8 TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) (DMA_TCD15_NBYTES_MLOFFNO) 32 R/W Undefined 22.3.22/444 4000_91E8 TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) (DMA_TCD15_NBYTES_MLOFFYES) 32 R/W Undefined 22.3.23/445 4000_91EC TCD Last Source Address Adjustment (DMA_TCD15_SLAST) 32 R/W Undefined 22.3.24/446 4000_91F0 TCD Destination Address (DMA_TCD15_DADDR) 32 R/W Undefined 22.3.25/447 4000_91F4 TCD Signed Destination Address Offset (DMA_TCD15_DOFF) 16 R/W Undefined 22.3.26/447 4000_91F6 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD15_CITER_ELINKYES) 16 R/W Undefined 22.3.27/448 4000_91F6 DMA_TCD15_CITER_ELINKNO 16 R/W Undefined 22.3.28/449 4000_91F8 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCD15_DLASTSGA) 32 R/W Undefined 22.3.29/450 16 R/W Undefined 22.3.30/451 4000_91FC TCD Control and Status (DMA_TCD15_CSR) 4000_91FE TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD15_BITER_ELINKYES) 16 R/W Undefined 22.3.31/453 4000_91FE TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCD15_BITER_ELINKNO) 16 R/W Undefined 22.3.32/454 22.3.1 Control Register (DMA_CR) The CR defines the basic operating configuration of the DMA. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 413 Memory map/register definition Arbitration can be configured to use either a fixed-priority or a round-robin scheme. For fixed-priority arbitration, the highest priority channel requesting service is selected to execute. The channel priority registers assign the priorities; see the DCHPRIn registers. For round-robin arbitration, the channel priorities are ignored and channels are cycled through (from high to low channel number) without regard to priority. NOTE For correct operation, writes to the CR register must be performed only when the DMA channels are inactive; that is, when TCDn_CSR[ACTIVE] bits are cleared. Minor loop offsets are address offset values added to the final source address (TCDn_SADDR) or destination address (TCDn_DADDR) upon minor loop completion. When minor loop offsets are enabled, the minor loop offset (MLOFF) is added to the final source address (TCDn_SADDR), to the final destination address (TCDn_DADDR), or to both prior to the addresses being written back into the TCD. If the major loop is complete, the minor loop offset is ignored and the major loop address offsets (TCDn_SLAST and TCDn_DLAST_SGA) are used to compute the next TCDn_SADDR and TCDn_DADDR values. When minor loop mapping is enabled (EMLM is 1), TCDn word2 is redefined. A portion of TCDn word2 is used to specify multiple fields: a source enable bit (SMLOE) to specify the minor loop offset should be applied to the source address (TCDn_SADDR) upon minor loop completion, a destination enable bit (DMLOE) to specify the minor loop offset should be applied to the destination address (TCDn_DADDR) upon minor loop completion, and the sign extended minor loop offset value (MLOFF). The same offset value (MLOFF) is used for both source and destination minor loop offsets. When either minor loop offset is enabled (SMLOE set or DMLOE set), the NBYTES field is reduced to 10 bits. When both minor loop offsets are disabled (SMLOE cleared and DMLOE cleared), the NBYTES field is a 30-bit vector. When minor loop mapping is disabled (EMLM is 0), all 32 bits of TCDn word2 are assigned to the NBYTES field. Address: 4000_8000h base + 0h offset = 4000_8000h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CX ECX 0 0 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 414 Freescale Semiconductor, Inc. 11 10 9 8 0 R W Reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 CLM HOE Reserved 12 EDBG 13 ERCA 14 Reserved 15 HALT Bit EMLM Chapter 22 Enhanced Direct Memory Access (eDMA) 0 0 0 0 0 0 0 0 DMA_CR field descriptions Field 31-18 Reserved 17 CX 16 ECX 15-8 Reserved 7 EMLM 6 CLM Description This field is reserved. This read-only field is reserved and always has the value 0. Cancel Transfer 0 1 Normal operation Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed. Error Cancel Transfer 0 1 Normal operation Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX treats the cancel as an error condition, thus updating the Error Status register (DMAx_ES) and generating an optional error interrupt. This field is reserved. This read-only field is reserved and always has the value 0. Enable Minor Loop Mapping 0 1 Disabled. TCDn.word2 is defined as a 32-bit NBYTES field. Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES field. The individual enable fields allow the minor loop offset to be applied to the source address, the destination address, or both. The NBYTES field is reduced when either offset is enabled. Continuous Link Mode NOTE: Do not use continuous link mode with a channel linking to itself if there is only one minor loop iteration per service request, e.g., if the channel's NBYTES value is the same as either the source or destination size. The same data transfer profile can be achieved by simply increasing the NBYTES value, which provides more efficient, faster processing. 0 1 5 HALT A minor loop channel link made to itself goes through channel arbitration before being activated again. A minor loop channel link made to itself does not go through channel arbitration before being activated again. Upon minor loop completion, the channel activates again if that channel has a minor loop channel link enabled and the link channel is itself. This effectively applies the minor loop offsets and restarts the next minor loop. Halt DMA Operations 0 1 Normal operation Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 415 Memory map/register definition DMA_CR field descriptions (continued) Field Description 4 HOE Halt On Error 0 1 3 Reserved Normal operation Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared. This field is reserved. Reserved 2 ERCA Enable Round Robin Channel Arbitration 1 EDBG Enable Debug 0 1 0 1 0 Reserved Fixed priority arbitration is used for channel selection . Round robin arbitration is used for channel selection . When in debug mode, the DMA continues to operate. When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared. This field is reserved. Reserved 22.3.2 Error Status Register (DMA_ES) The ES provides information concerning the last recorded channel error. Channel errors can be caused by: * A configuration error, that is: * An illegal setting in the transfer-control descriptor, or * An illegal priority register setting in fixed-arbitration * An error termination to a bus master read or write cycle * A cancel transfer with error bit that will be set when a transfer is canceled via the corresponding cancel transfer control bit See the Error Reporting and Handling section for more details. Address: 4000_8000h base + 4h offset = 4000_8004h Bit 31 R VLD 30 29 28 27 26 25 24 23 22 21 20 19 18 17 0 16 ECX W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 CPE SAE SOE DAE DOE NCE SGE SBE DBE 0 0 0 0 0 0 0 0 0 0 0 ERRCHN W Reset 0 0 0 0 0 0 KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 416 Freescale Semiconductor, Inc. Chapter 22 Enhanced Direct Memory Access (eDMA) DMA_ES field descriptions Field 31 VLD 30-17 Reserved 16 ECX 15 Reserved 14 CPE Description Logical OR of all ERR status bits 0 1 No ERR bits are set. At least one ERR bit is set indicating a valid error exists that has not been cleared. This field is reserved. This read-only field is reserved and always has the value 0. Transfer Canceled 0 1 No canceled transfers The last recorded entry was a canceled transfer by the error cancel transfer input This field is reserved. This read-only field is reserved and always has the value 0. Channel Priority Error 0 1 No channel priority error The last recorded error was a configuration error in the channel priorities . Channel priorities are not unique. 13-12 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 11-8 ERRCHN Error Channel Number or Canceled Channel Number The channel number of the last recorded error, excluding CPE errors, or last recorded error canceled transfer. 7 SAE Source Address Error 6 SOE Source Offset Error 5 DAE Destination Address Error 4 DOE Destination Offset Error 3 NCE NBYTES/CITER Configuration Error 0 1 0 1 0 1 0 1 0 1 No source address configuration error. The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE]. No source offset configuration error The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE]. No destination address configuration error The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE]. No destination offset configuration error The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE]. No NBYTES/CITER configuration error The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields. * TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 417 Memory map/register definition DMA_ES field descriptions (continued) Field Description * TCDn_CITER[CITER] is equal to zero, or * TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK] 2 SGE Scatter/Gather Configuration Error 1 SBE Source Bus Error 0 DBE Destination Bus Error 0 1 0 1 0 1 No scatter/gather configuration error The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is enabled. TCDn_DLASTSGA is not on a 32 byte boundary. No source bus error The last recorded error was a bus error on a source read No destination bus error The last recorded error was a bus error on a destination write 22.3.3 Enable Request Register (DMA_ERQ) The ERQ register provides a bit map for the 16 channels to enable the request signal for each channel. The state of any given channel enable is directly affected by writes to this register; it is also affected by writes to the SERQ and CERQ registers. These registers are provided so the request enable for a single channel can easily be modified without needing to perform a read-modify-write sequence to the ERQ. DMA request input signals and this enable request flag must be asserted before a channel's hardware service request is accepted. The state of the DMA enable request flag does not affect a channel service request made explicitly through software or a linked channel request. Address: 4000_8000h base + Ch offset = 4000_800Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 W ERQ15 ERQ14 ERQ13 ERQ12 ERQ11 ERQ10 W Reset 0 0 0 0 0 0 R ERQ9 ERQ8 ERQ7 ERQ6 ERQ5 ERQ4 ERQ3 ERQ2 ERQ1 ERQ0 0 0 0 0 0 0 0 0 0 0 KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 418 Freescale Semiconductor, Inc. Chapter 22 Enhanced Direct Memory Access (eDMA) DMA_ERQ field descriptions Field 31-16 Reserved Description This field is reserved. This read-only field is reserved and always has the value 0. 15 ERQ15 Enable DMA Request 15 14 ERQ14 Enable DMA Request 14 13 ERQ13 Enable DMA Request 13 12 ERQ12 Enable DMA Request 12 11 ERQ11 Enable DMA Request 11 10 ERQ10 Enable DMA Request 10 9 ERQ9 Enable DMA Request 9 8 ERQ8 Enable DMA Request 8 7 ERQ7 Enable DMA Request 7 6 ERQ6 Enable DMA Request 6 5 ERQ5 Enable DMA Request 5 4 ERQ4 Enable DMA Request 4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 The DMA request signal for the corresponding channel is disabled The DMA request signal for the corresponding channel is enabled The DMA request signal for the corresponding channel is disabled The DMA request signal for the corresponding channel is enabled The DMA request signal for the corresponding channel is disabled The DMA request signal for the corresponding channel is enabled The DMA request signal for the corresponding channel is disabled The DMA request signal for the corresponding channel is enabled The DMA request signal for the corresponding channel is disabled The DMA request signal for the corresponding channel is enabled The DMA request signal for the corresponding channel is disabled The DMA request signal for the corresponding channel is enabled The DMA request signal for the corresponding channel is disabled The DMA request signal for the corresponding channel is enabled The DMA request signal for the corresponding channel is disabled The DMA request signal for the corresponding channel is enabled The DMA request signal for the corresponding channel is disabled The DMA request signal for the corresponding channel is enabled The DMA request signal for the corresponding channel is disabled The DMA request signal for the corresponding channel is enabled The DMA request signal for the corresponding channel is disabled The DMA request signal for the corresponding channel is enabled Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 419 Memory map/register definition DMA_ERQ field descriptions (continued) Field Description 0 1 The DMA request signal for the corresponding channel is disabled The DMA request signal for the corresponding channel is enabled 3 ERQ3 Enable DMA Request 3 2 ERQ2 Enable DMA Request 2 1 ERQ1 Enable DMA Request 1 0 ERQ0 Enable DMA Request 0 0 1 0 1 0 1 0 1 The DMA request signal for the corresponding channel is disabled The DMA request signal for the corresponding channel is enabled The DMA request signal for the corresponding channel is disabled The DMA request signal for the corresponding channel is enabled The DMA request signal for the corresponding channel is disabled The DMA request signal for the corresponding channel is enabled The DMA request signal for the corresponding channel is disabled The DMA request signal for the corresponding channel is enabled 22.3.4 Enable Error Interrupt Register (DMA_EEI) The EEI register provides a bit map for the 16 channels to enable the error interrupt signal for each channel. The state of any given channel's error interrupt enable is directly affected by writes to this register; it is also affected by writes to the SEEI and CEEI. These registers are provided so that the error interrupt enable for a single channel can easily be modified without the need to perform a read-modify-write sequence to the EEI register. The DMA error indicator and the error interrupt enable flag must be asserted before an error interrupt request for a given channel is asserted to the interrupt controller. Address: 4000_8000h base + 14h offset = 4000_8014h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 R W Reset 0 0 0 0 0 0 0 0 KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 420 Freescale Semiconductor, Inc. 12 11 10 9 8 7 6 5 4 3 2 1 0 EEI11 EEI10 Reset 13 EEI12 W 14 EEI13 R 15 EEI14 Bit EEI15 Chapter 22 Enhanced Direct Memory Access (eDMA) EEI9 EEI8 EEI7 EEI6 EEI5 EEI4 EEI3 EEI2 EEI1 EEI0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_EEI field descriptions Field 31-16 Reserved Description This field is reserved. This read-only field is reserved and always has the value 0. 15 EEI15 Enable Error Interrupt 15 14 EEI14 Enable Error Interrupt 14 13 EEI13 Enable Error Interrupt 13 12 EEI12 Enable Error Interrupt 12 11 EEI11 Enable Error Interrupt 11 10 EEI10 Enable Error Interrupt 10 9 EEI9 Enable Error Interrupt 9 8 EEI8 Enable Error Interrupt 8 7 EEI7 Enable Error Interrupt 7 6 EEI6 Enable Error Interrupt 6 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 The error signal for corresponding channel does not generate an error interrupt The assertion of the error signal for corresponding channel generates an error interrupt request The error signal for corresponding channel does not generate an error interrupt The assertion of the error signal for corresponding channel generates an error interrupt request The error signal for corresponding channel does not generate an error interrupt The assertion of the error signal for corresponding channel generates an error interrupt request The error signal for corresponding channel does not generate an error interrupt The assertion of the error signal for corresponding channel generates an error interrupt request The error signal for corresponding channel does not generate an error interrupt The assertion of the error signal for corresponding channel generates an error interrupt request The error signal for corresponding channel does not generate an error interrupt The assertion of the error signal for corresponding channel generates an error interrupt request The error signal for corresponding channel does not generate an error interrupt The assertion of the error signal for corresponding channel generates an error interrupt request The error signal for corresponding channel does not generate an error interrupt The assertion of the error signal for corresponding channel generates an error interrupt request The error signal for corresponding channel does not generate an error interrupt The assertion of the error signal for corresponding channel generates an error interrupt request Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 421 Memory map/register definition DMA_EEI field descriptions (continued) Field Description 0 1 The error signal for corresponding channel does not generate an error interrupt The assertion of the error signal for corresponding channel generates an error interrupt request 5 EEI5 Enable Error Interrupt 5 4 EEI4 Enable Error Interrupt 4 3 EEI3 Enable Error Interrupt 3 2 EEI2 Enable Error Interrupt 2 1 EEI1 Enable Error Interrupt 1 0 EEI0 Enable Error Interrupt 0 0 1 0 1 0 1 0 1 0 1 0 1 The error signal for corresponding channel does not generate an error interrupt The assertion of the error signal for corresponding channel generates an error interrupt request The error signal for corresponding channel does not generate an error interrupt The assertion of the error signal for corresponding channel generates an error interrupt request The error signal for corresponding channel does not generate an error interrupt The assertion of the error signal for corresponding channel generates an error interrupt request The error signal for corresponding channel does not generate an error interrupt The assertion of the error signal for corresponding channel generates an error interrupt request The error signal for corresponding channel does not generate an error interrupt The assertion of the error signal for corresponding channel generates an error interrupt request The error signal for corresponding channel does not generate an error interrupt The assertion of the error signal for corresponding channel generates an error interrupt request 22.3.5 Clear Enable Error Interrupt Register (DMA_CEEI) The CEEI provides a simple memory-mapped mechanism to clear a given bit in the EEI to disable the error interrupt for a given channel. The data value on a register write causes the corresponding bit in the EEI to be cleared. Setting the CAEE bit provides a global clear function, forcing the EEI contents to be cleared, disabling all DMA request inputs. If the NOP bit is set, the command is ignored. This allows you to write multiple-byte registers as a 32-bit word. Reads of this register return all zeroes. Address: 4000_8000h base + 18h offset = 4000_8018h Bit 7 6 Read 0 0 Write NOP CAEE Reset 0 0 5 4 3 2 1 0 0 0 0 0 0 CEEI 0 0 0 KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 422 Freescale Semiconductor, Inc. Chapter 22 Enhanced Direct Memory Access (eDMA) DMA_CEEI field descriptions Field Description 7 NOP No Op enable 6 CAEE Clear All Enable Error Interrupts 5-4 Reserved CEEI 0 1 0 1 Normal operation No operation, ignore the other bits in this register Clear only the EEI bit specified in the CEEI field Clear all bits in EEI This field is reserved. Clear Enable Error Interrupt Clears the corresponding bit in EEI 22.3.6 Set Enable Error Interrupt Register (DMA_SEEI) The SEEI provides a simple memory-mapped mechanism to set a given bit in the EEI to enable the error interrupt for a given channel. The data value on a register write causes the corresponding bit in the EEI to be set. Setting the SAEE bit provides a global set function, forcing the entire EEI contents to be set. If the NOP bit is set, the command is ignored. This allows you to write multiple-byte registers as a 32-bit word. Reads of this register return all zeroes. Address: 4000_8000h base + 19h offset = 4000_8019h Bit 7 6 Read 0 0 Write NOP SAEE Reset 0 0 5 4 3 2 1 0 0 0 0 0 0 SEEI 0 0 0 DMA_SEEI field descriptions Field Description 7 NOP No Op enable 6 SAEE Sets All Enable Error Interrupts 5-4 Reserved 0 1 0 1 Normal operation No operation, ignore the other bits in this register Set only the EEI bit specified in the SEEI field. Sets all bits in EEI This field is reserved. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 423 Memory map/register definition DMA_SEEI field descriptions (continued) Field SEEI Description Set Enable Error Interrupt Sets the corresponding bit in EEI 22.3.7 Clear Enable Request Register (DMA_CERQ) The CERQ provides a simple memory-mapped mechanism to clear a given bit in the ERQ to disable the DMA request for a given channel. The data value on a register write causes the corresponding bit in the ERQ to be cleared. Setting the CAER bit provides a global clear function, forcing the entire contents of the ERQ to be cleared, disabling all DMA request inputs. If NOP is set, the command is ignored. This allows you to write multiple-byte registers as a 32-bit word. Reads of this register return all zeroes. Address: 4000_8000h base + 1Ah offset = 4000_801Ah Bit 7 6 Read 0 0 Write NOP CAER Reset 0 0 5 4 3 2 1 0 0 0 0 0 0 CERQ 0 0 0 DMA_CERQ field descriptions Field 7 NOP 6 CAER Description No Op enable 0 1 Normal operation No operation, ignore the other bits in this register Clear All Enable Requests 0 1 Clear only the ERQ bit specified in the CERQ field Clear all bits in ERQ 5-4 Reserved This field is reserved. CERQ Clear Enable Request Clears the corresponding bit in ERQ. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 424 Freescale Semiconductor, Inc. Chapter 22 Enhanced Direct Memory Access (eDMA) 22.3.8 Set Enable Request Register (DMA_SERQ) The SERQ provides a simple memory-mapped mechanism to set a given bit in the ERQ to enable the DMA request for a given channel. The data value on a register write causes the corresponding bit in the ERQ to be set. Setting the SAER bit provides a global set function, forcing the entire contents of ERQ to be set. If the NOP bit is set, the command is ignored. This allows you to write multiple-byte registers as a 32-bit word. Reads of this register return all zeroes. Address: 4000_8000h base + 1Bh offset = 4000_801Bh Bit 7 6 Read 0 0 Write NOP SAER Reset 0 0 5 4 3 2 1 0 0 0 0 0 0 SERQ 0 0 0 DMA_SERQ field descriptions Field Description 7 NOP No Op enable 6 SAER Set All Enable Requests 0 1 0 1 Normal operation No operation, ignore the other bits in this register Set only the ERQ bit specified in the SERQ field Set all bits in ERQ 5-4 Reserved This field is reserved. SERQ Set Enable Request Sets the corresponding bit in ERQ. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 425 Memory map/register definition 22.3.9 Clear DONE Status Bit Register (DMA_CDNE) The CDNE provides a simple memory-mapped mechanism to clear the DONE bit in the TCD of the given channel. The data value on a register write causes the DONE bit in the corresponding transfer control descriptor to be cleared. Setting the CADN bit provides a global clear function, forcing all DONE bits to be cleared. If the NOP bit is set, the command is ignored. This allows you to write multiple-byte registers as a 32-bit word. Reads of this register return all zeroes. Address: 4000_8000h base + 1Ch offset = 4000_801Ch Bit 7 6 Read 0 0 Write NOP CADN Reset 0 0 5 4 3 2 1 0 0 0 0 0 0 CDNE 0 0 0 DMA_CDNE field descriptions Field 7 NOP Description No Op enable 0 1 Normal operation No operation, ignore the other bits in this register 6 CADN Clears All DONE Bits 5-4 Reserved This field is reserved. CDNE 0 1 Clears only the TCDn_CSR[DONE] bit specified in the CDNE field Clears all bits in TCDn_CSR[DONE] Clear DONE Bit Clears the corresponding bit in TCDn_CSR[DONE] KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 426 Freescale Semiconductor, Inc. Chapter 22 Enhanced Direct Memory Access (eDMA) 22.3.10 Set START Bit Register (DMA_SSRT) The SSRT provides a simple memory-mapped mechanism to set the START bit in the TCD of the given channel. The data value on a register write causes the START bit in the corresponding transfer control descriptor to be set. Setting the SAST bit provides a global set function, forcing all START bits to be set. If the NOP bit is set, the command is ignored. This allows you to write multiple-byte registers as a 32-bit word. Reads of this register return all zeroes. Address: 4000_8000h base + 1Dh offset = 4000_801Dh Bit 7 6 Read 0 0 Write NOP SAST Reset 0 0 5 4 3 2 1 0 0 0 0 0 0 SSRT 0 0 0 DMA_SSRT field descriptions Field Description 7 NOP No Op enable 6 SAST Set All START Bits (activates all channels) 5-4 Reserved SSRT 0 1 0 1 Normal operation No operation, ignore the other bits in this register Set only the TCDn_CSR[START] bit specified in the SSRT field Set all bits in TCDn_CSR[START] This field is reserved. Set START Bit Sets the corresponding bit in TCDn_CSR[START] KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 427 Memory map/register definition 22.3.11 Clear Error Register (DMA_CERR) The CERR provides a simple memory-mapped mechanism to clear a given bit in the ERR to disable the error condition flag for a given channel. The given value on a register write causes the corresponding bit in the ERR to be cleared. Setting the CAEI bit provides a global clear function, forcing the ERR contents to be cleared, clearing all channel error indicators. If the NOP bit is set, the command is ignored. This allows you to write multiple-byte registers as a 32-bit word. Reads of this register return all zeroes. Address: 4000_8000h base + 1Eh offset = 4000_801Eh Bit 7 6 Read 0 0 Write NOP CAEI Reset 0 0 5 4 3 2 1 0 0 0 0 0 0 CERR 0 0 0 DMA_CERR field descriptions Field Description 7 NOP No Op enable 6 CAEI Clear All Error Indicators 0 1 0 1 Normal operation No operation, ignore the other bits in this register Clear only the ERR bit specified in the CERR field Clear all bits in ERR 5-4 Reserved This field is reserved. CERR Clear Error Indicator Clears the corresponding bit in ERR KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 428 Freescale Semiconductor, Inc. Chapter 22 Enhanced Direct Memory Access (eDMA) 22.3.12 Clear Interrupt Request Register (DMA_CINT) The CINT provides a simple, memory-mapped mechanism to clear a given bit in the INT to disable the interrupt request for a given channel. The given value on a register write causes the corresponding bit in the INT to be cleared. Setting the CAIR bit provides a global clear function, forcing the entire contents of the INT to be cleared, disabling all DMA interrupt requests. If the NOP bit is set, the command is ignored. This allows you to write multiple-byte registers as a 32-bit word. Reads of this register return all zeroes. Address: 4000_8000h base + 1Fh offset = 4000_801Fh Bit 7 6 Read 0 0 Write NOP CAIR Reset 0 0 5 4 3 2 1 0 0 0 0 0 0 CINT 0 0 0 DMA_CINT field descriptions Field Description 7 NOP No Op enable 6 CAIR Clear All Interrupt Requests 5-4 Reserved CINT 0 1 0 1 Normal operation No operation, ignore the other bits in this register Clear only the INT bit specified in the CINT field Clear all bits in INT This field is reserved. Clear Interrupt Request Clears the corresponding bit in INT KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 429 Memory map/register definition 22.3.13 Interrupt Request Register (DMA_INT) The INT register provides a bit map for the 16 channels signaling the presence of an interrupt request for each channel. Depending on the appropriate bit setting in the transfer-control descriptors, the eDMA engine generates an interrupt on data transfer completion. The outputs of this register are directly routed to the interrupt controller. During the interrupt-service routine associated with any given channel, it is the software's responsibility to clear the appropriate bit, negating the interrupt request. Typically, a write to the CINT register in the interrupt service routine is used for this purpose. The state of any given channel's interrupt request is directly affected by writes to this register; it is also affected by writes to the CINT register. On writes to INT, a 1 in any bit position clears the corresponding channel's interrupt request. A zero in any bit position has no affect on the corresponding channel's current interrupt status. The CINT register is provided so the interrupt request for a single channel can easily be cleared without the need to perform a read-modify-write sequence to the INT register. Address: 4000_8000h base + 24h offset = 4000_8024h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 R W 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R INT0 0 INT1 0 INT2 0 INT3 0 INT4 0 INT5 0 INT6 0 INT7 0 INT8 0 INT9 0 INT10 0 INT11 0 INT12 0 INT13 0 INT14 0 INT15 Reset W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset DMA_INT field descriptions Field 31-16 Reserved Description This field is reserved. This read-only field is reserved and always has the value 0. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 430 Freescale Semiconductor, Inc. Chapter 22 Enhanced Direct Memory Access (eDMA) DMA_INT field descriptions (continued) Field Description 15 INT15 Interrupt Request 15 14 INT14 Interrupt Request 14 13 INT13 Interrupt Request 13 12 INT12 Interrupt Request 12 11 INT11 Interrupt Request 11 10 INT10 Interrupt Request 10 9 INT9 Interrupt Request 9 8 INT8 Interrupt Request 8 7 INT7 Interrupt Request 7 6 INT6 Interrupt Request 6 5 INT5 Interrupt Request 5 4 INT4 Interrupt Request 4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 The interrupt request for corresponding channel is cleared The interrupt request for corresponding channel is active The interrupt request for corresponding channel is cleared The interrupt request for corresponding channel is active The interrupt request for corresponding channel is cleared The interrupt request for corresponding channel is active The interrupt request for corresponding channel is cleared The interrupt request for corresponding channel is active The interrupt request for corresponding channel is cleared The interrupt request for corresponding channel is active The interrupt request for corresponding channel is cleared The interrupt request for corresponding channel is active The interrupt request for corresponding channel is cleared The interrupt request for corresponding channel is active The interrupt request for corresponding channel is cleared The interrupt request for corresponding channel is active The interrupt request for corresponding channel is cleared The interrupt request for corresponding channel is active The interrupt request for corresponding channel is cleared The interrupt request for corresponding channel is active The interrupt request for corresponding channel is cleared The interrupt request for corresponding channel is active The interrupt request for corresponding channel is cleared The interrupt request for corresponding channel is active Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 431 Memory map/register definition DMA_INT field descriptions (continued) Field Description 3 INT3 Interrupt Request 3 2 INT2 Interrupt Request 2 1 INT1 Interrupt Request 1 0 INT0 Interrupt Request 0 0 1 0 1 0 1 0 1 The interrupt request for corresponding channel is cleared The interrupt request for corresponding channel is active The interrupt request for corresponding channel is cleared The interrupt request for corresponding channel is active The interrupt request for corresponding channel is cleared The interrupt request for corresponding channel is active The interrupt request for corresponding channel is cleared The interrupt request for corresponding channel is active 22.3.14 Error Register (DMA_ERR) The ERR provides a bit map for the 16 channels, signaling the presence of an error for each channel. The eDMA engine signals the occurrence of an error condition by setting the appropriate bit in this register. The outputs of this register are enabled by the contents of the EEI, and then routed to the interrupt controller. During the execution of the interrupt-service routine associated with any DMA errors, it is software's responsibility to clear the appropriate bit, negating the error-interrupt request. Typically, a write to the CERR in the interrupt-service routine is used for this purpose. The normal DMA channel completion indicators (setting the transfer control descriptor DONE flag and the possible assertion of an interrupt request) are not affected when an error is detected. The contents of this register can also be polled because a non-zero value indicates the presence of a channel error regardless of the state of the EEI. The state of any given channel's error indicators is affected by writes to this register; it is also affected by writes to the CERR. On writes to the ERR, a one in any bit position clears the corresponding channel's error status. A zero in any bit position has no affect on the corresponding channel's current error status. The CERR is provided so the error indicator for a single channel can easily be cleared. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 432 Freescale Semiconductor, Inc. Chapter 22 Enhanced Direct Memory Access (eDMA) Address: 4000_8000h base + 2Ch offset = 4000_802Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 R W 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R ERR0 0 ERR1 0 ERR2 0 ERR3 0 ERR4 0 ERR5 0 ERR6 0 ERR7 0 ERR8 0 ERR9 0 ERR10 0 ERR11 0 ERR12 0 ERR13 0 ERR14 0 ERR15 Reset W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset DMA_ERR field descriptions Field 31-16 Reserved Description This field is reserved. This read-only field is reserved and always has the value 0. 15 ERR15 Error In Channel 15 14 ERR14 Error In Channel 14 13 ERR13 Error In Channel 13 12 ERR12 Error In Channel 12 11 ERR11 Error In Channel 11 10 ERR10 Error In Channel 10 0 1 0 1 0 1 0 1 0 1 0 1 An error in this channel has not occurred An error in this channel has occurred An error in this channel has not occurred An error in this channel has occurred An error in this channel has not occurred An error in this channel has occurred An error in this channel has not occurred An error in this channel has occurred An error in this channel has not occurred An error in this channel has occurred An error in this channel has not occurred An error in this channel has occurred Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 433 Memory map/register definition DMA_ERR field descriptions (continued) Field Description 9 ERR9 Error In Channel 9 8 ERR8 Error In Channel 8 7 ERR7 Error In Channel 7 6 ERR6 Error In Channel 6 5 ERR5 Error In Channel 5 4 ERR4 Error In Channel 4 3 ERR3 Error In Channel 3 2 ERR2 Error In Channel 2 1 ERR1 Error In Channel 1 0 ERR0 Error In Channel 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 An error in this channel has not occurred An error in this channel has occurred An error in this channel has not occurred An error in this channel has occurred An error in this channel has not occurred An error in this channel has occurred An error in this channel has not occurred An error in this channel has occurred An error in this channel has not occurred An error in this channel has occurred An error in this channel has not occurred An error in this channel has occurred An error in this channel has not occurred An error in this channel has occurred An error in this channel has not occurred An error in this channel has occurred An error in this channel has not occurred An error in this channel has occurred An error in this channel has not occurred An error in this channel has occurred KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 434 Freescale Semiconductor, Inc. Chapter 22 Enhanced Direct Memory Access (eDMA) 22.3.15 Hardware Request Status Register (DMA_HRS) The HRS register provides a bit map for the DMA channels, signaling the presence of a hardware request for each channel. The hardware request status bits reflect the current state of the register and qualified (via the ERQ fields) DMA request signals as seen by the DMA's arbitration logic. This view into the hardware request signals may be used for debug purposes. NOTE These bits reflect the state of the request as seen by the arbitration logic. Therefore, this status is affected by the ERQ bits. Address: 4000_8000h base + 34h offset = 4000_8034h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R HRS15 HRS14 HRS13 HRS12 HRS11 HRS10 HRS9 HRS8 HRS7 HRS6 HRS5 HRS4 HRS3 HRS2 HRS1 HRS0 W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset DMA_HRS field descriptions Field 31-16 Reserved 15 HRS15 Description This field is reserved. This read-only field is reserved and always has the value 0. Hardware Request Status Channel 15 Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 435 Memory map/register definition DMA_HRS field descriptions (continued) Field Description The HRS bit for its respective channel remains asserted for the period when a Hardware Request is Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically cleared by hardware. 0 1 14 HRS14 Hardware Request Status Channel 14 The HRS bit for its respective channel remains asserted for the period when a Hardware Request is Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically cleared by hardware. 0 1 13 HRS13 The HRS bit for its respective channel remains asserted for the period when a Hardware Request is Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically cleared by hardware. The HRS bit for its respective channel remains asserted for the period when a Hardware Request is Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically cleared by hardware. The HRS bit for its respective channel remains asserted for the period when a Hardware Request is Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically cleared by hardware. A hardware service request for channel 11 is not present A hardware service request for channel 11 is present Hardware Request Status Channel 10 The HRS bit for its respective channel remains asserted for the period when a Hardware Request is Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically cleared by hardware. 0 1 9 HRS9 A hardware service request for channel 12 is not present A hardware service request for channel 12 is present Hardware Request Status Channel 11 0 1 10 HRS10 A hardware service request for channel 13 is not present A hardware service request for channel 13 is present Hardware Request Status Channel 12 0 1 11 HRS11 A hardware service request for channel 14 is not present A hardware service request for channel 14 is present Hardware Request Status Channel 13 0 1 12 HRS12 A hardware service request for channel 15 is not present A hardware service request for channel 15 is present A hardware service request for channel 10 is not present A hardware service request for channel 10 is present Hardware Request Status Channel 9 The HRS bit for its respective channel remains asserted for the period when a Hardware Request is Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically cleared by hardware. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 436 Freescale Semiconductor, Inc. Chapter 22 Enhanced Direct Memory Access (eDMA) DMA_HRS field descriptions (continued) Field Description 0 1 8 HRS8 Hardware Request Status Channel 8 The HRS bit for its respective channel remains asserted for the period when a Hardware Request is Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically cleared by hardware. 0 1 7 HRS7 The HRS bit for its respective channel remains asserted for the period when a Hardware Request is Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically cleared by hardware. The HRS bit for its respective channel remains asserted for the period when a Hardware Request is Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically cleared by hardware. The HRS bit for its respective channel remains asserted for the period when a Hardware Request is Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically cleared by hardware. The HRS bit for its respective channel remains asserted for the period when a Hardware Request is Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically cleared by hardware. A hardware service request for channel 4 is not present A hardware service request for channel 4 is present Hardware Request Status Channel 3 The HRS bit for its respective channel remains asserted for the period when a Hardware Request is Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically cleared by hardware. 0 1 2 HRS2 A hardware service request for channel 5 is not present A hardware service request for channel 5 is present Hardware Request Status Channel 4 0 1 3 HRS3 A hardware service request for channel 6 is not present A hardware service request for channel 6 is present Hardware Request Status Channel 5 0 1 4 HRS4 A hardware service request for channel 7 is not present A hardware service request for channel 7 is present Hardware Request Status Channel 6 0 1 5 HRS5 A hardware service request for channel 8 is not present A hardware service request for channel 8 is present Hardware Request Status Channel 7 0 1 6 HRS6 A hardware service request for channel 9 is not present A hardware service request for channel 9 is present A hardware service request for channel 3 is not present A hardware service request for channel 3 is present Hardware Request Status Channel 2 Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 437 Memory map/register definition DMA_HRS field descriptions (continued) Field Description The HRS bit for its respective channel remains asserted for the period when a Hardware Request is Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically cleared by hardware. 0 1 1 HRS1 A hardware service request for channel 2 is not present A hardware service request for channel 2 is present Hardware Request Status Channel 1 The HRS bit for its respective channel remains asserted for the period when a Hardware Request is Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically cleared by hardware. 0 1 0 HRS0 A hardware service request for channel 1 is not present A hardware service request for channel 1 is present Hardware Request Status Channel 0 The HRS bit for its respective channel remains asserted for the period when a Hardware Request is Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically cleared by hardware. 0 1 A hardware service request for channel 0 is not present A hardware service request for channel 0 is present 22.3.16 Enable Asynchronous Request in Stop Register (DMA_EARS) Address: 4000_8000h base + 44h offset = 4000_8044h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R EDREQ_15 EDREQ_14 EDREQ_13 EDREQ_12 EDREQ_11 EDREQ_10 EDREQ_9 EDREQ_8 EDREQ_7 EDREQ_6 EDREQ_5 EDREQ_4 EDREQ_3 EDREQ_2 EDREQ_1 EDREQ_0 W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset DMA_EARS field descriptions Field 31-16 Reserved Description This field is reserved. This read-only field is reserved and always has the value 0. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 438 Freescale Semiconductor, Inc. Chapter 22 Enhanced Direct Memory Access (eDMA) DMA_EARS field descriptions (continued) Field Description 15 EDREQ_15 Enable asynchronous DMA request in stop mode for channel 15 14 EDREQ_14 Enable asynchronous DMA request in stop mode for channel 14 13 EDREQ_13 Enable asynchronous DMA request in stop mode for channel 13 12 EDREQ_12 Enable asynchronous DMA request in stop mode for channel 12 11 EDREQ_11 Enable asynchronous DMA request in stop mode for channel 11 10 EDREQ_10 Enable asynchronous DMA request in stop mode for channel 10 9 EDREQ_9 Enable asynchronous DMA request in stop mode for channel 9 8 EDREQ_8 Enable asynchronous DMA request in stop mode for channel 8 7 EDREQ_7 Enable asynchronous DMA request in stop mode for channel 7 6 EDREQ_6 Enable asynchronous DMA request in stop mode for channel 6 5 EDREQ_5 Enable asynchronous DMA request in stop mode for channel 5 4 EDREQ_4 Enable asynchronous DMA request in stop mode for channel 4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Disable asynchronous DMA request for channel 15. Enable asynchronous DMA request for channel 15. Disable asynchronous DMA request for channel 14. Enable asynchronous DMA request for channel 14. Disable asynchronous DMA request for channel 13. Enable asynchronous DMA request for channel 13. Disable asynchronous DMA request for channel 12. Enable asynchronous DMA request for channel 12. Disable asynchronous DMA request for channel 11. Enable asynchronous DMA request for channel 11. Disable asynchronous DMA request for channel 10. Enable asynchronous DMA request for channel 10. Disable asynchronous DMA request for channel 9. Enable asynchronous DMA request for channel 9. Disable asynchronous DMA request for channel 8. Enable asynchronous DMA request for channel 8. Disable asynchronous DMA request for channel 7. Enable asynchronous DMA request for channel 7. Disable asynchronous DMA request for channel 6. Enable asynchronous DMA request for channel 6. Disable asynchronous DMA request for channel 5. Enable asynchronous DMA request for channel 5. Disable asynchronous DMA request for channel 4. Enable asynchronous DMA request for channel 4. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 439 Memory map/register definition DMA_EARS field descriptions (continued) Field Description 3 EDREQ_3 Enable asynchronous DMA request in stop mode for channel 3. 2 EDREQ_2 Enable asynchronous DMA request in stop mode for channel 2. 1 EDREQ_1 Enable asynchronous DMA request in stop mode for channel 1. 0 EDREQ_0 Enable asynchronous DMA request in stop mode for channel 0. 0 1 0 1 0 1 0 1 Disable asynchronous DMA request for channel 3. Enable asynchronous DMA request for channel 3. Disable asynchronous DMA request for channel 2. Enable asynchronous DMA request for channel 2. Disable asynchronous DMA request for channel 1 Enable asynchronous DMA request for channel 1. Disable asynchronous DMA request for channel 0. Enable asynchronous DMA request for channel 0. 22.3.17 Channel n Priority Register (DMA_DCHPRIn) When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the contents of these registers define the unique priorities associated with each channel. The channel priorities are evaluated by numeric value; for example, 0 is the lowest priority, 1 is the next higher priority, then 2, 3, etc. Software must program the channel priorities with unique values; otherwise, a configuration error is reported. The range of the priority value is limited to the values of 0 through 15. Address: 4000_8000h base + 100h offset + (1d x i), where i=0d to 15d Bit Read Write Reset 7 6 ECP DPA 0 0 5 4 3 2 0 0 1 0 * * CHPRI 0 * * * Notes: * CHPRI field: See bit field description. DMA_DCHPRIn field descriptions Field 7 ECP Description Enable Channel Preemption. 0 1 Channel n cannot be suspended by a higher priority channel's service request. Channel n can be temporarily suspended by the service request of a higher priority channel. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 440 Freescale Semiconductor, Inc. Chapter 22 Enhanced Direct Memory Access (eDMA) DMA_DCHPRIn field descriptions (continued) Field Description 6 DPA Disable Preempt Ability. 0 1 5-4 Reserved Channel n can suspend a lower priority channel. Channel n cannot suspend any channel, regardless of channel priority. This field is reserved. This read-only field is reserved and always has the value 0. CHPRI Channel n Arbitration Priority Channel priority when fixed-priority arbitration is enabled NOTE: Reset value for the channel priority field, CHPRI, is equal to the corresponding channel number for each priority register, that is, DCHPRI15[CHPRI] = 0b1111. 22.3.18 TCD Source Address (DMA_TCDn_SADDR) Address: 4000_8000h base + 1000h offset + (32d x i), where i=0d to 15d Bit R W Reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SADDR x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* * Notes: * x = Undefined at reset. DMA_TCDn_SADDR field descriptions Field SADDR Description Source Address Memory address pointing to the source data. 22.3.19 TCD Signed Source Address Offset (DMA_TCDn_SOFF) Address: 4000_8000h base + 1004h offset + (32d x i), where i=0d to 15d Bit Read Write Reset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x* x* x* x* x* x* x* x* SOFF x* x* x* x* x* x* x* x* * Notes: * x = Undefined at reset. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 441 Memory map/register definition DMA_TCDn_SOFF field descriptions Field SOFF Description Source address signed offset Sign-extended offset applied to the current source address to form the next-state value as each source read is completed. 22.3.20 TCD Transfer Attributes (DMA_TCDn_ATTR) Address: 4000_8000h base + 1006h offset + (32d x i), where i=0d to 15d Bit Read Write Reset 15 14 13 12 11 10 SMOD x* x* x* 9 8 7 6 SSIZE x* x* x* x* 5 4 3 2 DMOD x* x* x* x* 1 0 DSIZE x* x* x* x* x* * Notes: * x = Undefined at reset. DMA_TCDn_ATTR field descriptions Field Description 15-11 SMOD Source Address Modulo 10-8 SSIZE Source data transfer size 0 0 Source address modulo feature is disabled This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. NOTE: Using a Reserved value causes a configuration error. 000 001 010 011 100 101 110 111 8-bit 16-bit 32-bit Reserved 16-byte burst 32-byte burst Reserved Reserved 7-3 DMOD Destination Address Modulo DSIZE Destination data transfer size See the SMOD definition Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 442 Freescale Semiconductor, Inc. Chapter 22 Enhanced Direct Memory Access (eDMA) DMA_TCDn_ATTR field descriptions (continued) Field Description See the SSIZE definition 22.3.21 TCD Minor Byte Count (Minor Loop Mapping Disabled) (DMA_TCDn_NBYTES_MLNO) This register, or one of the next two registers (TCD_NBYTES_MLOFFNO, TCD_NBYTES_MLOFFYES), defines the number of bytes to transfer per request. Which register to use depends on whether minor loop mapping is disabled, enabled but not used for this channel, or enabled and used. TCD word 2 is defined as follows if: * Minor loop mapping is disabled (CR[EMLM] = 0) If minor loop mapping is enabled, see the TCD_NBYTES_MLOFFNO and TCD_NBYTES_MLOFFYES register descriptions for the definition of TCD word 2. Address: 4000_8000h base + 1008h offset + (32d x i), where i=0d to 15d Bit R W Reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NBYTES x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* * Notes: * x = Undefined at reset. DMA_TCDn_NBYTES_MLNO field descriptions Field NBYTES Description Minor Byte Transfer Count Number of bytes to be transferred in each service request of the channel. As a channel activates, the appropriate TCD contents load into the eDMA engine, and the appropriate reads and writes perform until the minor byte transfer count has transferred. This is an indivisible operation and cannot be halted. It can, however, be stalled by using the bandwidth control field, or via preemption. After the minor count is exhausted, the SADDR and DADDR values are written back into the TCD memory, the major iteration count is decremented and restored to the TCD memory. If the major iteration count is completed, additional processing is performed. NOTE: An NBYTES value of 0x0000_0000 is interpreted as a 4 GB transfer. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 443 Memory map/register definition 22.3.22 TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) (DMA_TCDn_NBYTES_MLOFFNO) One of three registers (this register, TCD_NBYTES_MLNO, or TCD_NBYTES_MLOFFYES), defines the number of bytes to transfer per request. Which register to use depends on whether minor loop mapping is disabled, enabled but not used for this channel, or enabled and used. TCD word 2 is defined as follows if: * Minor loop mapping is enabled (CR[EMLM] = 1) and * SMLOE = 0 and DMLOE = 0 If minor loop mapping is enabled and SMLOE or DMLOE is set, then refer to the TCD_NBYTES_MLOFFYES register description. If minor loop mapping is disabled, then refer to the TCD_NBYTES_MLNO register description. 31 30 W SMLOE DMLOE Address: 4000_8000h base + 1008h offset + (32d x i), where i=0d to 15d Bit Reset x* x* x* x* x* x* x* x* x* Bit 15 14 13 12 11 10 9 8 7 R 29 28 27 26 25 24 23 22 21 20 19 18 17 16 x* x* x* x* x* x* x* 6 5 4 3 2 1 0 x* x* x* x* x* x* x* NBYTES R NBYTES W Reset x* x* x* x* x* x* x* x* x* * Notes: * x = Undefined at reset. DMA_TCDn_NBYTES_MLOFFNO field descriptions Field 31 SMLOE Description Source Minor Loop Offset Enable Selects whether the minor loop offset is applied to the source address upon minor loop completion. 0 1 30 DMLOE The minor loop offset is not applied to the SADDR The minor loop offset is applied to the SADDR Destination Minor Loop Offset enable Selects whether the minor loop offset is applied to the destination address upon minor loop completion. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 444 Freescale Semiconductor, Inc. Chapter 22 Enhanced Direct Memory Access (eDMA) DMA_TCDn_NBYTES_MLOFFNO field descriptions (continued) Field Description 0 1 NBYTES The minor loop offset is not applied to the DADDR The minor loop offset is applied to the DADDR Minor Byte Transfer Count Number of bytes to be transferred in each service request of the channel. As a channel activates, the appropriate TCD contents load into the eDMA engine, and the appropriate reads and writes perform until the minor byte transfer count has transferred. This is an indivisible operation and cannot be halted. It can, however, be stalled by using the bandwidth control field, or via preemption. After the minor count is exhausted, the SADDR and DADDR values are written back into the TCD memory, the major iteration count is decremented and restored to the TCD memory. If the major iteration count is completed, additional processing is performed. 22.3.23 TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) (DMA_TCDn_NBYTES_MLOFFYES) One of three registers (this register, TCD_NBYTES_MLNO, or TCD_NBYTES_MLOFFNO), defines the number of bytes to transfer per request. Which register to use depends on whether minor loop mapping is disabled, enabled but not used for this channel, or enabled and used. TCD word 2 is defined as follows if: * Minor loop mapping is enabled (CR[EMLM] = 1) and * Minor loop offset is enabled (SMLOE or DMLOE = 1) If minor loop mapping is enabled and SMLOE and DMLOE are cleared, then refer to the TCD_NBYTES_MLOFFNO register description. If minor loop mapping is disabled, then refer to the TCD_NBYTES_MLNO register description. 31 30 W SMLOE DMLOE Address: 4000_8000h base + 1008h offset + (32d x i), where i=0d to 15d Bit Reset x* x* x* x* x* x* x* x* x* Bit 15 14 13 12 11 10 9 8 7 R 29 28 27 26 25 24 23 22 21 20 19 18 17 16 x* x* x* x* x* x* x* 6 5 4 3 2 1 0 x* x* x* x* MLOFF R MLOFF NBYTES W Reset x* x* x* x* x* x* x* x* x* x* x* x* * Notes: KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 445 Memory map/register definition * x = Undefined at reset. DMA_TCDn_NBYTES_MLOFFYES field descriptions Field Description 31 SMLOE Source Minor Loop Offset Enable Selects whether the minor loop offset is applied to the source address upon minor loop completion. 0 1 30 DMLOE The minor loop offset is not applied to the SADDR The minor loop offset is applied to the SADDR Destination Minor Loop Offset enable Selects whether the minor loop offset is applied to the destination address upon minor loop completion. 0 1 29-10 MLOFF The minor loop offset is not applied to the DADDR The minor loop offset is applied to the DADDR If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. NBYTES Minor Byte Transfer Count Number of bytes to be transferred in each service request of the channel. As a channel activates, the appropriate TCD contents load into the eDMA engine, and the appropriate reads and writes perform until the minor byte transfer count has transferred. This is an indivisible operation and cannot be halted. It can, however, be stalled by using the bandwidth control field, or via preemption. After the minor count is exhausted, the SADDR and DADDR values are written back into the TCD memory, the major iteration count is decremented and restored to the TCD memory. If the major iteration count is completed, additional processing is performed. 22.3.24 TCD Last Source Address Adjustment (DMA_TCDn_SLAST) Address: 4000_8000h base + 100Ch offset + (32d x i), where i=0d to 15d Bit R W Reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SLAST x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* * Notes: * x = Undefined at reset. DMA_TCDn_SLAST field descriptions Field SLAST Description Last Source Address Adjustment Adjustment value added to the source address at the completion of the major iteration count. This value can be applied to restore the source address to the initial value, or adjust the address to reference the next data structure. This register uses two's complement notation; the overflow bit is discarded. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 446 Freescale Semiconductor, Inc. Chapter 22 Enhanced Direct Memory Access (eDMA) 22.3.25 TCD Destination Address (DMA_TCDn_DADDR) Address: 4000_8000h base + 1010h offset + (32d x i), where i=0d to 15d Bit R W Reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DADDR x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* * Notes: * x = Undefined at reset. DMA_TCDn_DADDR field descriptions Field DADDR Description Destination Address Memory address pointing to the destination data. 22.3.26 TCD Signed Destination Address Offset (DMA_TCDn_DOFF) Address: 4000_8000h base + 1014h offset + (32d x i), where i=0d to 15d Bit Read Write Reset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x* x* x* x* x* x* x* x* DOFF x* x* x* x* x* x* x* x* * Notes: * x = Undefined at reset. DMA_TCDn_DOFF field descriptions Field DOFF Description Destination Address Signed Offset Sign-extended offset applied to the current destination address to form the next-state value as each destination write is completed. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 447 Memory map/register definition 22.3.27 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCDn_CITER_ELINKYES) If TCDn_CITER[ELINK] is set, the TCDn_CITER register is defined as follows. Address: 4000_8000h base + 1016h offset + (32d x i), where i=0d to 15d Bit Read Write Reset Bit Read Write Reset 15 14 ELINK 13 12 11 10 9 LINKCH 0 8 CITER x* x* x* x* x* x* x* x* 7 6 5 4 3 2 1 0 x* x* x* x* CITER x* x* x* x* * Notes: * x = Undefined at reset. DMA_TCDn_CITER_ELINKYES field descriptions Field 15 ELINK Description Enable channel-to-channel linking on minor-loop complete As the channel completes the minor loop, this flag enables linking to another channel, defined by the LINKCH field. The link target channel initiates a channel service request via an internal mechanism that sets the TCDn_CSR[START] bit of the specified channel. If channel linking is disabled, the CITER value is extended to 15 bits in place of a link channel number. If the major loop is exhausted, this link mechanism is suppressed in favor of the MAJORELINK channel linking. NOTE: This bit must be equal to the BITER[ELINK] bit; otherwise, a configuration error is reported. 0 1 14-13 Reserved 12-9 LINKCH CITER The channel-to-channel linking is disabled The channel-to-channel linking is enabled This field is reserved. Minor Loop Link Channel Number If channel-to-channel linking is enabled (ELINK = 1), then after the minor loop is exhausted, the eDMA engine initiates a channel service request to the channel defined by this field by setting that channel's TCDn_CSR[START] bit. Current Major Iteration Count This 9-bit (ELINK = 1) or 15-bit (ELINK = 0) count represents the current major loop count for the channel. It is decremented each time the minor loop is completed and updated in the transfer control descriptor memory. After the major iteration count is exhausted, the channel performs a number of operations, for example, final source and destination address calculations, optionally generating an interrupt to signal channel completion before reloading the CITER field from the Beginning Iteration Count (BITER) field. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 448 Freescale Semiconductor, Inc. Chapter 22 Enhanced Direct Memory Access (eDMA) DMA_TCDn_CITER_ELINKYES field descriptions (continued) Field Description NOTE: When the CITER field is initially loaded by software, it must be set to the same value as that contained in the BITER field. NOTE: If the channel is configured to execute a single service request, the initial values of BITER and CITER should be 0x0001. 22.3.28 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCDn_CITER_ELINKNO) If TCDn_CITER[ELINK] is cleared, the TCDn_CITER register is defined as follows. Address: 4000_8000h base + 1016h offset + (32d x i), where i=0d to 15d Bit Read Write Reset Bit Read Write Reset 15 14 13 12 11 ELINK 10 9 8 CITER x* x* x* x* x* x* x* x* 7 6 5 4 3 2 1 0 x* x* x* x* CITER x* x* x* x* * Notes: * x = Undefined at reset. DMA_TCDn_CITER_ELINKNO field descriptions Field 15 ELINK Description Enable channel-to-channel linking on minor-loop complete As the channel completes the minor loop, this flag enables linking to another channel, defined by the LINKCH field. The link target channel initiates a channel service request via an internal mechanism that sets the TCDn_CSR[START] bit of the specified channel. If channel linking is disabled, the CITER value is extended to 15 bits in place of a link channel number. If the major loop is exhausted, this link mechanism is suppressed in favor of the MAJORELINK channel linking. NOTE: This bit must be equal to the BITER[ELINK] bit; otherwise, a configuration error is reported. 0 1 CITER The channel-to-channel linking is disabled The channel-to-channel linking is enabled Current Major Iteration Count This 9-bit (ELINK = 1) or 15-bit (ELINK = 0) count represents the current major loop count for the channel. It is decremented each time the minor loop is completed and updated in the transfer control descriptor memory. After the major iteration count is exhausted, the channel performs a number of operations, for Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 449 Memory map/register definition DMA_TCDn_CITER_ELINKNO field descriptions (continued) Field Description example, final source and destination address calculations, optionally generating an interrupt to signal channel completion before reloading the CITER field from the Beginning Iteration Count (BITER) field. NOTE: When the CITER field is initially loaded by software, it must be set to the same value as that contained in the BITER field. NOTE: If the channel is configured to execute a single service request, the initial values of BITER and CITER should be 0x0001. 22.3.29 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCDn_DLASTSGA) Address: 4000_8000h base + 1018h offset + (32d x i), where i=0d to 15d Bit R W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DLASTSGA Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* * Notes: * x = Undefined at reset. DMA_TCDn_DLASTSGA field descriptions Field DLASTSGA Description Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather). If (TCDn_CSR[ESG] = 0) then: * Adjustment value added to the destination address at the completion of the major iteration count. This value can apply to restore the destination address to the initial value or adjust the address to reference the next data structure. * This field uses two's complement notation for the final destination address adjustment. Otherwise: * This address points to the beginning of a 0-modulo-32-byte region containing the next transfer control descriptor to be loaded into this channel. This channel reload is performed as the major iteration count completes. The scatter/gather address must be 0-modulo-32-byte, otherwise a configuration error is reported. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 450 Freescale Semiconductor, Inc. Chapter 22 Enhanced Direct Memory Access (eDMA) 22.3.30 TCD Control and Status (DMA_TCDn_CSR) Address: 4000_8000h base + 101Ch offset + (32d x i), where i=0d to 15d Bit 15 14 Read 13 BWC Write 12 11 10 9 8 MAJORLINKCH 0 Reset x* x* x* x* x* x* x* x* Bit 7 6 5 4 3 2 1 0 ACTIVE MAJORELI NK ESG DREQ INTHALF INTMAJOR START x* x* x* x* x* x* x* Read Write Reset DONE x* * Notes: * x = Undefined at reset. DMA_TCDn_CSR field descriptions Field 15-14 BWC Description Bandwidth Control Throttles the amount of bus bandwidth consumed by the eDMA. Generally, as the eDMA processes the minor loop, it continuously generates read/write sequences until the minor count is exhausted. This field forces the eDMA to stall after the completion of each read/write access to control the bus request bandwidth seen by the crossbar switch. NOTE: If the source and destination sizes are equal, this field is ignored between the first and second transfers and after the last write of each minor loop. This behavior is a side effect of reducing start-up latency. 00 01 10 11 13-12 Reserved No eDMA engine stalls. Reserved eDMA engine stalls for 4 cycles after each R/W. eDMA engine stalls for 8 cycles after each R/W. This field is reserved. 11-8 Major Loop Link Channel Number MAJORLINKCH If (MAJORELINK = 0) then: * No channel-to-channel linking, or chaining, is performed after the major loop counter is exhausted. Otherwise: * After the major loop counter is exhausted, the eDMA engine initiates a channel service request at the channel defined by this field by setting that channel's TCDn_CSR[START] bit. 7 DONE Channel Done This flag indicates the eDMA has completed the major loop. The eDMA engine sets it as the CITER count reaches zero. The software clears it, or the hardware when the channel is activated. NOTE: This bit must be cleared to write the MAJORELINK or ESG bits. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 451 Memory map/register definition DMA_TCDn_CSR field descriptions (continued) Field 6 ACTIVE 5 MAJORELINK Description Channel Active This flag signals the channel is currently in execution. It is set when channel service begins, and is cleared by the eDMA as the minor loop completes or when any error condition is detected. Enable channel-to-channel linking on major loop complete As the channel completes the major loop, this flag enables the linking to another channel, defined by MAJORLINKCH. The link target channel initiates a channel service request via an internal mechanism that sets the TCDn_CSR[START] bit of the specified channel. NOTE: To support the dynamic linking coherency model, this field is forced to zero when written to while the TCDn_CSR[DONE] bit is set. 0 1 4 ESG The channel-to-channel linking is disabled. The channel-to-channel linking is enabled. Enable Scatter/Gather Processing As the channel completes the major loop, this flag enables scatter/gather processing in the current channel. If enabled, the eDMA engine uses DLASTSGA as a memory pointer to a 0-modulo-32 address containing a 32-byte data structure loaded as the transfer control descriptor into the local memory. NOTE: To support the dynamic scatter/gather coherency model, this field is forced to zero when written to while the TCDn_CSR[DONE] bit is set. 0 1 3 DREQ Disable Request If this flag is set, the eDMA hardware automatically clears the corresponding ERQ bit when the current major iteration count reaches zero. 0 1 2 INTHALF The current channel's TCD is normal format. The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. The channel's ERQ bit is not affected. The channel's ERQ bit is cleared when the major loop is complete. Enable an interrupt when major counter is half complete. If this flag is set, the channel generates an interrupt request by setting the appropriate bit in the INT register when the current major iteration count reaches the halfway point. Specifically, the comparison performed by the eDMA engine is (CITER == (BITER >> 1)). This halfway point interrupt request is provided to support double-buffered, also known as ping-pong, schemes or other types of data movement where the processor needs an early indication of the transfer's progress. NOTE: If BITER = 1, do not use INTHALF. Use INTMAJOR instead. 0 1 1 INTMAJOR The half-point interrupt is disabled. The half-point interrupt is enabled. Enable an interrupt when major iteration count completes. If this flag is set, the channel generates an interrupt request by setting the appropriate bit in the INT when the current major iteration count reaches zero. 0 1 The end-of-major loop interrupt is disabled. The end-of-major loop interrupt is enabled. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 452 Freescale Semiconductor, Inc. Chapter 22 Enhanced Direct Memory Access (eDMA) DMA_TCDn_CSR field descriptions (continued) Field 0 START Description Channel Start If this flag is set, the channel is requesting service. The eDMA hardware automatically clears this flag after the channel begins execution. 0 1 The channel is not explicitly started. The channel is explicitly started via a software initiated service request. 22.3.31 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCDn_BITER_ELINKYES) If the TCDn_BITER[ELINK] bit is set, the TCDn_BITER register is defined as follows. Address: 4000_8000h base + 101Eh offset + (32d x i), where i=0d to 15d Bit Read Write Reset Bit Read Write Reset 15 14 ELINK 13 12 11 10 9 LINKCH 0 8 BITER x* x* x* x* x* x* x* x* 7 6 5 4 3 2 1 0 x* x* x* x* BITER x* x* x* x* * Notes: * x = Undefined at reset. DMA_TCDn_BITER_ELINKYES field descriptions Field Description 15 ELINK Enables channel-to-channel linking on minor loop complete As the channel completes the minor loop, this flag enables the linking to another channel, defined by BITER[LINKCH]. The link target channel initiates a channel service request via an internal mechanism that sets the TCDn_CSR[START] bit of the specified channel. If channel linking disables, the BITER value extends to 15 bits in place of a link channel number. If the major loop is exhausted, this link mechanism is suppressed in favor of the MAJORELINK channel linking. NOTE: When the software loads the TCD, this field must be set equal to the corresponding CITER field; otherwise, a configuration error is reported. As the major iteration count is exhausted, the contents of this field are reloaded into the CITER field. 0 1 The channel-to-channel linking is disabled The channel-to-channel linking is enabled 14-13 Reserved This field is reserved. 12-9 LINKCH Link Channel Number Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 453 Memory map/register definition DMA_TCDn_BITER_ELINKYES field descriptions (continued) Field Description If channel-to-channel linking is enabled (ELINK = 1), then after the minor loop is exhausted, the eDMA engine initiates a channel service request at the channel defined by this field by setting that channel's TCDn_CSR[START] bit. NOTE: When the software loads the TCD, this field must be set equal to the corresponding CITER field; otherwise, a configuration error is reported. As the major iteration count is exhausted, the contents of this field are reloaded into the CITER field. BITER Starting major iteration count As the transfer control descriptor is first loaded by software, this 9-bit (ELINK = 1) or 15-bit (ELINK = 0) field must be equal to the value in the CITER field. As the major iteration count is exhausted, the contents of this field are reloaded into the CITER field. NOTE: When the software loads the TCD, this field must be set equal to the corresponding CITER field; otherwise, a configuration error is reported. As the major iteration count is exhausted, the contents of this field are reloaded into the CITER field. If the channel is configured to execute a single service request, the initial values of BITER and CITER should be 0x0001. 22.3.32 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCDn_BITER_ELINKNO) If the TCDn_BITER[ELINK] bit is cleared, the TCDn_BITER register is defined as follows. Address: 4000_8000h base + 101Eh offset + (32d x i), where i=0d to 15d Bit Read Write Reset Bit Read Write Reset 15 14 13 12 11 ELINK 10 9 8 x* x* x* x* 3 2 1 0 x* x* x* x* BITER x* x* x* x* 7 6 5 4 BITER x* x* x* x* * Notes: * x = Undefined at reset. DMA_TCDn_BITER_ELINKNO field descriptions Field Description 15 ELINK Enables channel-to-channel linking on minor loop complete As the channel completes the minor loop, this flag enables the linking to another channel, defined by BITER[LINKCH]. The link target channel initiates a channel service request via an internal mechanism that sets the TCDn_CSR[START] bit of the specified channel. If channel linking is disabled, the BITER value extends to 15 bits in place of a link channel number. If the major loop is exhausted, this link mechanism is suppressed in favor of the MAJORELINK channel linking. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 454 Freescale Semiconductor, Inc. Chapter 22 Enhanced Direct Memory Access (eDMA) DMA_TCDn_BITER_ELINKNO field descriptions (continued) Field Description NOTE: When the software loads the TCD, this field must be set equal to the corresponding CITER field; otherwise, a configuration error is reported. As the major iteration count is exhausted, the contents of this field are reloaded into the CITER field. 0 1 BITER The channel-to-channel linking is disabled The channel-to-channel linking is enabled Starting Major Iteration Count As the transfer control descriptor is first loaded by software, this 9-bit (ELINK = 1) or 15-bit (ELINK = 0) field must be equal to the value in the CITER field. As the major iteration count is exhausted, the contents of this field are reloaded into the CITER field. NOTE: When the software loads the TCD, this field must be set equal to the corresponding CITER field; otherwise, a configuration error is reported. As the major iteration count is exhausted, the contents of this field is reloaded into the CITER field. If the channel is configured to execute a single service request, the initial values of BITER and CITER should be 0x0001. 22.4 Functional description The operation of the eDMA is described in the following subsections. 22.4.1 eDMA basic data flow The basic flow of a data transfer can be partitioned into three segments. As shown in the following diagram, the first segment involves the channel activation: KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 455 Functional description eDMA Write Address Write Data 0 Transfer Control Descriptor (TCD) n-1 64 eDMA Engine Program Model/ Channel Arbitration Read Data Internal Peripheral Bus To/From Crossbar Switch 1 2 Read Data Address Path Control Data Path Write Data Address eDMA Peripheral Request eDMA Done Figure 22-2. eDMA operation, part 1 This example uses the assertion of the eDMA peripheral request signal to request service for channel n. Channel activation via software and the TCDn_CSR[START] bit follows the same basic flow as peripheral requests. The eDMA request input signal is registered internally and then routed through the eDMA engine: first through the control module, then into the program model and channel arbitration. In the next cycle, the channel arbitration performs, using the fixed-priority or round-robin algorithm. After arbitration is complete, the activated channel number is sent through the address path and converted into the required address to access the local memory for TCDn. Next, the TCD memory is accessed and the required descriptor read from the local memory and loaded into the eDMA engine address path channel x or y registers. The TCD memory is 64 bits wide to minimize the time needed to fetch the activated channel descriptor and load it into the address path channel x or y registers. The following diagram illustrates the second part of the basic data flow: KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 456 Freescale Semiconductor, Inc. Chapter 22 Enhanced Direct Memory Access (eDMA) eDMA Write Address Write Data To/From Crossbar Switch Transfer Control Descriptor (TCD) n-1 64 eDMA Engine Program Model/ Channel Arbitration Read Data Internal Peripheral Bus 0 1 2 Read Data Address Path Control Data Path Write Data Address eDMA Peripheral Request eDMA Done Figure 22-3. eDMA operation, part 2 The modules associated with the data transfer (address path, data path, and control) sequence through the required source reads and destination writes to perform the actual data movement. The source reads are initiated and the fetched data is temporarily stored in the data path block until it is gated onto the internal bus during the destination write. This source read/destination write processing continues until the minor byte count has transferred. After the minor byte count has moved, the final phase of the basic data flow is performed. In this segment, the address path logic performs the required updates to certain fields in the appropriate TCD, for example, SADDR, DADDR, CITER. If the major iteration count is exhausted, additional operations are performed. These include the final address adjustments and reloading of the BITER field into the CITER. Assertion of an optional interrupt request also occurs at this time, as does a possible fetch of a new TCD from memory using the scatter/gather address pointer included in the descriptor (if scatter/ gather is enabled). The updates to the TCD memory and the assertion of an interrupt request are shown in the following diagram. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 457 Functional description eDMA Write Address Write Data To/From Crossbar Switch Transfer Control Descriptor (TCD) n-1 64 Internal Peripheral Bus 0 1 2 eDMA En g in e Program Model/ Channel Arbitration Read Data Read Data Address Path Control Data Path Write Data Address eDMA Peripheral Request eDMA Done Figure 22-4. eDMA operation, part 3 22.4.2 Fault reporting and handling Channel errors are reported in the Error Status register (DMAx_ES) and can be caused by: * A configuration error, which is an illegal setting in the transfer-control descriptor or an illegal priority register setting in Fixed-Arbitration mode, or * An error termination to a bus master read or write cycle A configuration error is reported when the starting source or destination address, source or destination offsets, minor loop byte count, or the transfer size represent an inconsistent state. Each of these possible causes are detailed below: * The addresses and offsets must be aligned on 0-modulo-transfer-size boundaries. * The minor loop byte count must be a multiple of the source and destination transfer sizes. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 458 Freescale Semiconductor, Inc. Chapter 22 Enhanced Direct Memory Access (eDMA) * All source reads and destination writes must be configured to the natural boundary of the programmed transfer size respectively. * In fixed arbitration mode, a configuration error is caused by any two channel priorities being equal. All channel priority levels must be unique when fixed arbitration mode is enabled. NOTE When two channels have the same priority, a channel priority error exists and will be reported in the Error Status register. However, the channel number will not be reported in the Error Status register. When all of the channel priorities within a group are not unique, the channel number selected by arbitration is undetermined. To aid in Channel Priority Error (CPE) debug, set the Halt On Error bit in the DMA's Control Register. If all of the channel priorities within a group are not unique, the DMA will be halted after the CPE error is recorded. The DMA will remain halted and will not process any channel service requests. Once all of the channel priorities are set to unique numbers, the DMA may be enabled again by clearing the Halt bit. * If a scatter/gather operation is enabled upon channel completion, a configuration error is reported if the scatter/gather address (DLAST_SGA) is not aligned on a 32byte boundary. * If minor loop channel linking is enabled upon channel completion, a configuration error is reported when the link is attempted if the TCDn_CITER[E_LINK] bit does not equal the TCDn_BITER[E_LINK] bit. If enabled, all configuration error conditions, except the scatter/gather and minor-loop link errors, report as the channel activates and asserts an error interrupt request. A scatter/ gather configuration error is reported when the scatter/gather operation begins at major loop completion when properly enabled. A minor loop channel link configuration error is reported when the link operation is serviced at minor loop completion. If a system bus read or write is terminated with an error, the data transfer is stopped and the appropriate bus error flag set. In this case, the state of the channel's transfer control descriptor is updated by the eDMA engine with the current source address, destination address, and current iteration count at the point of the fault. When a system bus error occurs, the channel terminates after the next transfer. Due to pipeline effect, the next transfer is already in progress when the bus error is received by the eDMA. If a bus error KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 459 Functional description occurs on the last read prior to beginning the write sequence, the write executes using the data captured during the bus error. If a bus error occurs on the last write prior to switching to the next read sequence, the read sequence executes before the channel terminates due to the destination bus error. A transfer may be cancelled by software with the CR[CX] bit. When a cancel transfer request is recognized, the DMA engine stops processing the channel. The current readwrite sequence is allowed to finish. If the cancel occurs on the last read-write sequence of a major or minor loop, the cancel request is discarded and the channel retires normally. The error cancel transfer is the same as a cancel transfer except the Error Status register (DMAx_ES) is updated with the cancelled channel number and ECX is set. The TCD of a cancelled channel contains the source and destination addresses of the last transfer saved in the TCD. If the channel needs to be restarted, you must re-initialize the TCD because the aforementioned fields no longer represent the original parameters. When a transfer is cancelled by the error cancel transfer mechanism, the channel number is loaded into DMA_ES[ERRCHN] and ECX and VLD are set. In addition, an error interrupt may be generated if enabled. NOTE The cancel transfer request allows the user to stop a large data transfer in the event the full data transfer is no longer needed. The cancel transfer bit does not abort the channel. It simply stops the transferring of data and then retires the channel through its normal shutdown sequence. The application software must handle the context of the cancel. If an interrupt is desired (or not), then the interrupt should be enabled (or disabled) before the cancel request. The application software must clean up the transfer control descriptor since the full transfer did not occur. The occurrence of any error causes the eDMA engine to stop normal processing of the active channel immediately (it goes to its error processing states and the transaction to the system bus still has pipeline effect), and the appropriate channel bit in the eDMA error register is asserted. At the same time, the details of the error condition are loaded into the Error Status register (DMAx_ES). The major loop complete indicators, setting the transfer control descriptor DONE flag and the possible assertion of an interrupt request, are not affected when an error is detected. After the error status has been updated, the eDMA engine continues operating by servicing the next appropriate channel. A channel that experiences an error condition is not automatically disabled. If a channel is terminated by an error and then issues another service request before the error is fixed, that channel executes and terminates with the same error condition. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 460 Freescale Semiconductor, Inc. Chapter 22 Enhanced Direct Memory Access (eDMA) 22.4.3 Channel preemption Channel preemption is enabled on a per-channel basis by setting the DCHPRIn[ECP] bit. Channel preemption allows the executing channel's data transfers to temporarily suspend in favor of starting a higher priority channel. After the preempting channel has completed all its minor loop data transfers, the preempted channel is restored and resumes execution. After the restored channel completes one read/write sequence, it is again eligible for preemption. If any higher priority channel is requesting service, the restored channel is suspended and the higher priority channel is serviced. Nested preemption, that is, attempting to preempt a preempting channel, is not supported. After a preempting channel begins execution, it cannot be preempted. Preemption is available only when fixed arbitration is selected. A channel's ability to preempt another channel can be disabled by setting DCHPRIn[DPA]. When a channel's preempt ability is disabled, that channel cannot suspend a lower priority channel's data transfer, regardless of the lower priority channel's ECP setting. This allows for a pool of low priority, large data-moving channels to be defined. These low priority channels can be configured to not preempt each other, thus preventing a low priority channel from consuming the preempt slot normally available to a true, high priority channel. 22.4.4 Performance This section addresses the performance of the eDMA module, focusing on two separate metrics: * In the traditional data movement context, performance is best expressed as the peak data transfer rates achieved using the eDMA. In most implementations, this transfer rate is limited by the speed of the source and destination address spaces. * In a second context where device-paced movement of single data values to/from peripherals is dominant, a measure of the requests that can be serviced in a fixed time is a more relevant metric. In this environment, the speed of the source and destination address spaces remains important. However, the microarchitecture of the eDMA also factors significantly into the resulting metric. 22.4.4.1 Peak transfer rates The peak transfer rates for several different source and destination transfers are shown in the following tables. These tables assume: KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 461 Functional description * Internal SRAM can be accessed with zero wait-states when viewed from the system bus data phase * All internal peripheral bus reads require two wait-states, and internal peripheral bus writes three wait-states, when viewed from the system bus data phase * All internal peripheral bus accesses are 32-bits in size NOTE All architectures will not meet the assumptions listed above. See the SRAM configuration section for more information. This table compares peak transfer rates based on different possible system speeds. Specific chips/devices may not support all system speeds listed. Table 22-4. eDMA peak transfer rates (Mbytes/sec) Internal SRAM-to- Internal SRAM-to-32 bit Internal SRAM 32 bit internal peripheral bus-to-Internal SRAM internal peripheral bus 66.7 MHz, 32 bit 133.3 66.7 53.3 83.3 MHz, 32 bit 166.7 83.3 66.7 100.0 MHz, 32 bit 200.0 100.0 80.0 133.3 MHz, 32 bit 266.7 133.3 106.7 150.0 MHz, 32 bit 300.0 150.0 120.0 System Speed, Width Internal-SRAM-to-internal-SRAM transfers occur at the core's datapath width. For all transfers involving the internal peripheral bus, 32-bit transfer sizes are used. In all cases, the transfer rate includes the time to read the source plus the time to write the destination. 22.4.4.2 Peak request rates The second performance metric is a measure of the number of DMA requests that can be serviced in a given amount of time. For this metric, assume that the peripheral request causes the channel to move a single internal peripheral bus-mapped operand to/from internal SRAM. The same timing assumptions used in the previous example apply to this calculation. In particular, this metric also reflects the time required to activate the channel. The eDMA design supports the following hardware service request sequence. Note that the exact timing from Cycle 7 is a function of the response times for the channel's read and write accesses. In the case of an internal peripheral bus read and internal SRAM write, the combined data phase time is 4 cycles. For an SRAM read and internal peripheral bus write, it is 5 cycles. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 462 Freescale Semiconductor, Inc. Chapter 22 Enhanced Direct Memory Access (eDMA) Table 22-5. Hardware service request process Cycle With internal peripheral bus read and internal SRAM write Description With SRAM read and internal peripheral bus write 1 eDMA peripheral request is asserted. 2 The eDMA peripheral request is registered locally in the eDMA module and qualified. TCDn_CSR[START] bit initiated requests start at this point with the registering of the user write to TCDn word 7. 3 Channel arbitration begins. 4 Channel arbitration completes. The transfer control descriptor local memory read is initiated. 5-6 The first two parts of the activated channel's TCD is read from the local memory. The memory width to the eDMA engine is 64 bits, so the entire descriptor can be accessed in four cycles 7 The first system bus read cycle is initiated, as the third part of the channel's TCD is read from the local memory. Depending on the state of the crossbar switch, arbitration at the system bus may insert an additional cycle of delay here. 8-11 8-12 The last part of the TCD is read in. This cycle represents the first data phase for the read, and the address phase for the destination write. 12 13 This cycle represents the data phase of the last destination write. 13 14 The eDMA engine completes the execution of the inner minor loop and prepares to write back the required TCDn fields into the local memory. The TCDn word 7 is read and checked for channel linking or scatter/gather requests. 14 15 The appropriate fields in the first part of the TCDn are written back into the local memory. 15 16 The fields in the second part of the TCDn are written back into the local memory. This cycle coincides with the next channel arbitration cycle start. 16 17 The next channel to be activated performs the read of the first part of its TCD from the local memory. This is equivalent to Cycle 4 for the first channel's service request. Assuming zero wait states on the system bus, DMA requests can be processed every 9 cycles. Assuming an average of the access times associated with internal peripheral busto-SRAM (4 cycles) and SRAM-to-internal peripheral bus (5 cycles), DMA requests can be processed every 11.5 cycles (4 + (4+5)/2 + 3). This is the time from Cycle 4 to Cycle x +5. The resulting peak request rate, as a function of the system frequency, is shown in the following table. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 463 Functional description Table 22-6. eDMA peak request rate (MReq/sec) System frequency (MHz) Request rate Request rate with zero wait states with wait states 66.6 7.4 5.8 83.3 9.2 7.2 100.0 11.1 8.7 133.3 14.8 11.6 150.0 16.6 13.0 A general formula to compute the peak request rate with overlapping requests is: PEAKreq = freq / [ entry + (1 + read_ws) + (1 + write_ws) + exit ] where: Table 22-7. Peak request formula operands Operand Description PEAKreq Peak request rate freq System frequency entry Channel startup (4 cycles) read_ws Wait states seen during the system bus read data phase write_ws Wait states seen during the system bus write data phase exit Channel shutdown (3 cycles) 22.4.4.3 eDMA performance example Consider a system with the following characteristics: * Internal SRAM can be accessed with one wait-state when viewed from the system bus data phase * All internal peripheral bus reads require two wait-states, and internal peripheral bus writes three wait-states viewed from the system bus data phase * System operates at 150 MHz For an SRAM to internal peripheral bus transfer, PEAKreq = 150 MHz / [ 4 + (1 + 1) + (1 + 3) + 3 ] cycles = 11.5 Mreq/sec For an internal peripheral bus to SRAM transfer, KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 464 Freescale Semiconductor, Inc. Chapter 22 Enhanced Direct Memory Access (eDMA) PEAKreq = 150 MHz / [ 4 + (1 + 2) + (1 + 1) + 3 ] cycles = 12.5 Mreq/sec Assuming an even distribution of the two transfer types, the average peak request rate would be: PEAKreq = (11.5 Mreq/sec + 12.5 Mreq/sec) / 2 = 12.0 Mreq/sec The minimum number of cycles to perform a single read/write, zero wait states on the system bus, from a cold start where no channel is executing and eDMA is idle are: * 11 cycles for a software, that is, a TCDn_CSR[START] bit, request * 12 cycles for a hardware, that is, an eDMA peripheral request signal, request Two cycles account for the arbitration pipeline and one extra cycle on the hardware request resulting from the internal registering of the eDMA peripheral request signals. For the peak request rate calculations above, the arbitration and request registering is absorbed in or overlaps the previous executing channel. Note When channel linking or scatter/gather is enabled, a two cycle delay is imposed on the next channel selection and startup. This allows the link channel or the scatter/gather channel to be eligible and considered in the arbitration pool for next channel selection. 22.5 Initialization/application information The following sections discuss initialization of the eDMA and programming considerations. 22.5.1 eDMA initialization To initialize the eDMA: 1. Write to the CR if a configuration other than the default is desired. 2. Write the channel priority levels to the DCHPRIn registers if a configuration other than the default is desired. 3. Enable error interrupts in the EEI register if so desired. 4. Write the 32-byte TCD for each channel that may request service. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 465 Initialization/application information 5. Enable any hardware service requests via the ERQH and ERQL registers. 6. Request channel service via either: * Software: setting the TCDn_CSR[START] * Hardware: slave device asserting its eDMA peripheral request signal After any channel requests service, a channel is selected for execution based on the arbitration and priority levels written into the programmer's model. The eDMA engine reads the entire TCD, including the TCD control and status fields, as shown in the following table, for the selected channel into its internal address path module. As the TCD is read, the first transfer is initiated on the internal bus, unless a configuration error is detected. Transfers from the source, as defined by TCDn_SADDR, to the destination, as defined by TCDn_DADDR, continue until the number of bytes specified by TCDn_NBYTES are transferred. When the transfer is complete, the eDMA engine's local TCDn_SADDR, TCDn_DADDR, and TCDn_CITER are written back to the main TCD memory and any minor loop channel linking is performed, if enabled. If the major loop is exhausted, further post processing executes, such as interrupts, major loop channel linking, and scatter/gather operations, if enabled. Table 22-8. TCD Control and Status fields TCDn_CSR field name Description START Control bit to start channel explicitly when using a software initiated DMA service (Automatically cleared by hardware) ACTIVE Status bit indicating the channel is currently in execution DONE Status bit indicating major loop completion (cleared by software when using a software initiated DMA service) D_REQ Control bit to disable DMA request at end of major loop completion when using a hardware initiated DMA service BWC Control bits for throttling bandwidth control of a channel E_SG Control bit to enable scatter-gather feature INT_HALF Control bit to enable interrupt when major loop is half complete INT_MAJ Control bit to enable interrupt when major loop completes The following figure shows how each DMA request initiates one minor-loop transfer, or iteration, without CPU intervention. DMA arbitration can occur after each minor loop, and one level of minor loop DMA preemption is allowed. The number of minor loops in a major loop is specified by the beginning iteration count (BITER). KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 466 Freescale Semiconductor, Inc. Chapter 22 Enhanced Direct Memory Access (eDMA) Current major loop iteration count (CITER) Source or destination memory Minor loop DMA request 3 Major loop Minor loop DMA request 2 Minor loop DMA request 1 Figure 22-5. Example of multiple loop iterations The following figure lists the memory array terms and how the TCD settings interrelate. xADDR: (Starting address) xSIZE: (size of one data transfer) Minor loop (NBYTES in minor loop, often the same value as xSIZE) Minor loop Offset (xOFF): number of bytes added to current address after each transfer (often the same value as xSIZE) Each DMA source (S) and destination (D) has its own: Address (xADDR) Size (xSIZE) Offset (xOFF) Modulo (xMOD) Last Address Adjustment (xLAST) where x = S or D Last minor loop Peripheral queues typically have size and offset equal to NBYTES. xLAST: Number of bytes added to current address after major loop (typically used to loop back) Figure 22-6. Memory array terms 22.5.2 Programming errors The eDMA performs various tests on the transfer control descriptor to verify consistency in the descriptor data. Most programming errors are reported on a per channel basis with the exception of channel priority error (ES[CPE]). KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 467 Initialization/application information For all error types other than channel priority error, the channel number causing the error is recorded in the Error Status register (DMAx_ES). If the error source is not removed before the next activation of the problem channel, the error is detected and recorded again. If priority levels are not unique, when any channel requests service, a channel priority error is reported. The highest channel priority with an active request is selected, but the lowest numbered channel with that priority is selected by arbitration and executed by the eDMA engine. The hardware service request handshake signals, error interrupts, and error reporting is associated with the selected channel. 22.5.3 Arbitration mode considerations This section discusses arbitration considerations for the eDMA. 22.5.3.1 Fixed channel arbitration In this mode, the channel service request from the highest priority channel is selected to execute. 22.5.3.2 Round-robin channel arbitration Channels are serviced starting with the highest channel number and rotating through to the lowest channel number without regard to the channel priority levels. 22.5.4 Performing DMA transfers This section presents examples on how to perform DMA transfers with the eDMA. 22.5.4.1 Single request To perform a simple transfer of n bytes of data with one activation, set the major loop to one (TCDn_CITER = TCDn_BITER = 1). The data transfer begins after the channel service request is acknowledged and the channel is selected to execute. After the transfer is complete, the TCDn_CSR[DONE] bit is set and an interrupt generates if properly enabled. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 468 Freescale Semiconductor, Inc. Chapter 22 Enhanced Direct Memory Access (eDMA) For example, the following TCD entry is configured to transfer 16 bytes of data. The eDMA is programmed for one iteration of the major loop transferring 16 bytes per iteration. The source memory has a byte wide memory port located at 0x1000. The destination memory has a 32-bit port located at 0x2000. The address offsets are programmed in increments to match the transfer size: one byte for the source and four bytes for the destination. The final source and destination addresses are adjusted to return to their beginning values. TCDn_CITER = TCDn_BITER = 1 TCDn_NBYTES = 16 TCDn_SADDR = 0x1000 TCDn_SOFF = 1 TCDn_ATTR[SSIZE] = 0 TCDn_SLAST = -16 TCDn_DADDR = 0x2000 TCDn_DOFF = 4 TCDn_ATTR[DSIZE] = 2 TCDn_DLAST_SGA= -16 TCDn_CSR[INT_MAJ] = 1 TCDn_CSR[START] = 1 (Should be written last after all other fields have been initialized) All other TCDn fields = 0 This generates the following event sequence: 1. User write to the TCDn_CSR[START] bit requests channel service. 2. The channel is selected by arbitration for servicing. 3. eDMA engine writes: TCDn_CSR[DONE] = 0, TCDn_CSR[START] = 0, TCDn_CSR[ACTIVE] = 1. 4. eDMA engine reads: channel TCD data from local memory to internal register file. 5. The source-to-destination transfers are executed as follows: a. Read byte from location 0x1000, read byte from location 0x1001, read byte from 0x1002, read byte from 0x1003. b. Write 32-bits to location 0x2000 first iteration of the minor loop. c. Read byte from location 0x1004, read byte from location 0x1005, read byte from 0x1006, read byte from 0x1007. d. Write 32-bits to location 0x2004 second iteration of the minor loop. e. Read byte from location 0x1008, read byte from location 0x1009, read byte from 0x100A, read byte from 0x100B. f. Write 32-bits to location 0x2008 third iteration of the minor loop. g. Read byte from location 0x100C, read byte from location 0x100D, read byte from 0x100E, read byte from 0x100F. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 469 Initialization/application information h. Write 32-bits to location 0x200C last iteration of the minor loop major loop complete. 6. The eDMA engine writes: TCDn_SADDR = 0x1000, TCDn_DADDR = 0x2000, TCDn_CITER = 1 (TCDn_BITER). 7. The eDMA engine writes: TCDn_CSR[ACTIVE] = 0, TCDn_CSR[DONE] = 1, INT[n] = 1. 8. The channel retires and the eDMA goes idle or services the next channel. 22.5.4.2 Multiple requests The following example transfers 32 bytes via two hardware requests, but is otherwise the same as the previous example. The only fields that change are the major loop iteration count and the final address offsets. The eDMA is programmed for two iterations of the major loop transferring 16 bytes per iteration. After the channel's hardware requests are enabled in the ERQ register, the slave device initiates channel service requests. TCDn_CITER = TCDn_BITER = 2 TCDn_SLAST = -32 TCDn_DLAST_SGA = -32 This would generate the following sequence of events: 1. First hardware, that is, eDMA peripheral, request for channel service. 2. The channel is selected by arbitration for servicing. 3. eDMA engine writes: TCDn_CSR[DONE] = 0, TCDn_CSR[START] = 0, TCDn_CSR[ACTIVE] = 1. 4. eDMA engine reads: channel TCDn data from local memory to internal register file. 5. The source to destination transfers are executed as follows: a. Read byte from location 0x1000, read byte from location 0x1001, read byte from 0x1002, read byte from 0x1003. b. Write 32-bits to location 0x2000 first iteration of the minor loop. c. Read byte from location 0x1004, read byte from location 0x1005, read byte from 0x1006, read byte from 0x1007. d. Write 32-bits to location 0x2004 second iteration of the minor loop. e. Read byte from location 0x1008, read byte from location 0x1009, read byte from 0x100A, read byte from 0x100B. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 470 Freescale Semiconductor, Inc. Chapter 22 Enhanced Direct Memory Access (eDMA) f. Write 32-bits to location 0x2008 third iteration of the minor loop. g. Read byte from location 0x100C, read byte from location 0x100D, read byte from 0x100E, read byte from 0x100F. h. Write 32-bits to location 0x200C last iteration of the minor loop. 6. eDMA engine writes: TCDn_SADDR = 0x1010, TCDn_DADDR = 0x2010, TCDn_CITER = 1. 7. eDMA engine writes: TCDn_CSR[ACTIVE] = 0. 8. The channel retires one iteration of the major loop. The eDMA goes idle or services the next channel. 9. Second hardware, that is, eDMA peripheral, requests channel service. 10. The channel is selected by arbitration for servicing. 11. eDMA engine writes: TCDn_CSR[DONE] = 0, TCDn_CSR[START] = 0, TCDn_CSR[ACTIVE] = 1. 12. eDMA engine reads: channel TCD data from local memory to internal register file. 13. The source to destination transfers are executed as follows: a. Read byte from location 0x1010, read byte from location 0x1011, read byte from 0x1012, read byte from 0x1013. b. Write 32-bits to location 0x2010 first iteration of the minor loop. c. Read byte from location 0x1014, read byte from location 0x1015, read byte from 0x1016, read byte from 0x1017. d. Write 32-bits to location 0x2014 second iteration of the minor loop. e. Read byte from location 0x1018, read byte from location 0x1019, read byte from 0x101A, read byte from 0x101B. f. Write 32-bits to location 0x2018 third iteration of the minor loop. g. Read byte from location 0x101C, read byte from location 0x101D, read byte from 0x101E, read byte from 0x101F. h. Write 32-bits to location 0x201C last iteration of the minor loop major loop complete. 14. eDMA engine writes: TCDn_SADDR = 0x1000, TCDn_DADDR = 0x2000, TCDn_CITER = 2 (TCDn_BITER). KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 471 Initialization/application information 15. eDMA engine writes: TCDn_CSR[ACTIVE] = 0, TCDn_CSR[DONE] = 1, INT[n] = 1. 16. The channel retires major loop complete. The eDMA goes idle or services the next channel. 22.5.4.3 Using the modulo feature The modulo feature of the eDMA provides the ability to implement a circular data queue in which the size of the queue is a power of 2. MOD is a 5-bit field for the source and destination in the TCD, and it specifies which lower address bits increment from their original value after the address+offset calculation. All upper address bits remain the same as in the original value. A setting of 0 for this field disables the modulo feature. The following table shows how the transfer addresses are specified based on the setting of the MOD field. Here a circular buffer is created where the address wraps to the original value while the 28 upper address bits (0x1234567x) retain their original value. In this example the source address is set to 0x12345670, the offset is set to 4 bytes and the MOD field is set to 4, allowing for a 24 byte (16-byte) size queue. Table 22-9. Modulo example Transfer Number Address 1 0x12345670 2 0x12345674 3 0x12345678 4 0x1234567C 5 0x12345670 6 0x12345674 22.5.5 Monitoring transfer descriptor status This section discusses how to monitor eDMA status. 22.5.5.1 Testing for minor loop completion There are two methods to test for minor loop completion when using software initiated service requests. The first is to read the TCDn_CITER field and test for a change. Another method may be extracted from the sequence shown below. The second method is KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 472 Freescale Semiconductor, Inc. Chapter 22 Enhanced Direct Memory Access (eDMA) to test the TCDn_CSR[START] bit and the TCDn_CSR[ACTIVE] bit. The minor-loopcomplete condition is indicated by both bits reading zero after the TCDn_CSR[START] was set. Polling the TCDn_CSR[ACTIVE] bit may be inconclusive, because the active status may be missed if the channel execution is short in duration. The TCD status bits execute the following sequence for a software activated channel: Stage TCDn_CSR bits State START ACTIVE DONE 1 1 0 0 Channel service request via software 2 0 1 0 Channel is executing 3a 0 0 0 Channel has completed the minor loop and is idle 3b 0 0 1 Channel has completed the major loop and is idle The best method to test for minor-loop completion when using hardware, that is, peripheral, initiated service requests is to read the TCDn_CITER field and test for a change. The hardware request and acknowledge handshake signals are not visible in the programmer's model. The TCD status bits execute the following sequence for a hardware-activated channel: Stage TCDn_CSR bits State START ACTIVE DONE 1 0 0 0 Channel service request via hardware (peripheral request asserted) 2 0 1 0 Channel is executing 3a 0 0 0 Channel has completed the minor loop and is idle 3b 0 0 1 Channel has completed the major loop and is idle For both activation types, the major-loop-complete status is explicitly indicated via the TCDn_CSR[DONE] bit. The TCDn_CSR[START] bit is cleared automatically when the channel begins execution regardless of how the channel activates. 22.5.5.2 Reading the transfer descriptors of active channels The eDMA reads back the true TCDn_SADDR, TCDn_DADDR, and TCDn_NBYTES values if read while a channel executes. The true values of the SADDR, DADDR, and NBYTES are the values the eDMA engine currently uses in its internal register file and not the values in the TCD local memory for that channel. The addresses, SADDR and KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 473 Initialization/application information DADDR, and NBYTES, which decrement to zero as the transfer progresses, can give an indication of the progress of the transfer. All other values are read back from the TCD local memory. 22.5.5.3 Checking channel preemption status Preemption is available only when fixed arbitration is selected as the channel arbitration mode. A preemptive situation is one in which a preempt-enabled channel runs and a higher priority request becomes active. When the eDMA engine is not operating in fixed channel arbitration mode, the determination of the actively running relative priority outstanding requests become undefined. Channel priorities are treated as equal, that is, constantly rotating, when Round-Robin Arbitration mode is selected. The TCDn_CSR[ACTIVE] bit for the preempted channel remains asserted throughout the preemption. The preempted channel is temporarily suspended while the preempting channel executes one major loop iteration. If two TCDn_CSR[ACTIVE] bits are set simultaneously in the global TCD map, a higher priority channel is actively preempting a lower priority channel. 22.5.6 Channel Linking Channel linking (or chaining) is a mechanism where one channel sets the TCDn_CSR[START] bit of another channel (or itself), therefore initiating a service request for that channel. When properly enabled, the EDMA engine automatically performs this operation at the major or minor loop completion. The minor loop channel linking occurs at the completion of the minor loop (or one iteration of the major loop). The TCDn_CITER[E_LINK] field determines whether a minor loop link is requested. When enabled, the channel link is made after each iteration of the major loop except for the last. When the major loop is exhausted, only the major loop channel link fields are used to determine if a channel link should be made. For example, the initial fields of: TCDn_CITER[E_LINK] = 1 TCDn_CITER[LINKCH] = 0xC TCDn_CITER[CITER] value = 0x4 TCDn_CSR[MAJOR_E_LINK] = 1 TCDn_CSR[MAJOR_LINKCH] = 0x7 executes as: 1. Minor loop done set TCD12_CSR[START] bit KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 474 Freescale Semiconductor, Inc. Chapter 22 Enhanced Direct Memory Access (eDMA) 2. Minor loop done set TCD12_CSR[START] bit 3. Minor loop done set TCD12_CSR[START] bit 4. Minor loop done, major loop done set TCD7_CSR[START] bit When minor loop linking is enabled (TCDn_CITER[E_LINK] = 1), the TCDn_CITER[CITER] field uses a nine bit vector to form the current iteration count. When minor loop linking is disabled (TCDn_CITER[E_LINK] = 0), the TCDn_CITER[CITER] field uses a 15-bit vector to form the current iteration count. The bits associated with the TCDn_CITER[LINKCH] field are concatenated onto the CITER value to increase the range of the CITER. Note The TCDn_CITER[E_LINK] bit and the TCDn_BITER[E_LINK] bit must equal or a configuration error is reported. The CITER and BITER vector widths must be equal to calculate the major loop, half-way done interrupt point. The following table summarizes how a DMA channel can link to another DMA channel, i.e, use another channel's TCD, at the end of a loop. Table 22-10. Channel Linking Parameters Desired Link Behavior Link at end of Minor Loop Link at end of Major Loop TCD Control Field Name Description CITER[E_LINK] Enable channel-to-channel linking on minor loop completion (current iteration) CITER[LINKCH] Link channel number when linking at end of minor loop (current iteration) CSR[MAJOR_E_LINK] Enable channel-to-channel linking on major loop completion CSR[MAJOR_LINKCH] Link channel number when linking at end of major loop 22.5.7 Dynamic programming This section provides recommended methods to change the programming model during channel execution. 22.5.7.1 Dynamically changing the channel priority The following two options are recommended for dynamically changing channel priority levels: KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 475 Initialization/application information 1. Switch to Round-Robin Channel Arbitration mode, change the channel priorities, then switch back to Fixed Arbitration mode, 2. Disable all the channels, change the channel priorities, then enable the appropriate channels. 22.5.7.2 Dynamic channel linking Dynamic channel linking is the process of setting the TCD.major.e_link bit during channel execution (see the diagram in TCD structure). This bit is read from the TCD local memory at the end of channel execution, thus allowing the user to enable the feature during channel execution. Because the user is allowed to change the configuration during execution, a coherency model is needed. Consider the scenario where the user attempts to execute a dynamic channel link by enabling the TCD.major.e_link bit at the same time the eDMA engine is retiring the channel. The TCD.major.e_link would be set in the programmer's model, but it would be unclear whether the actual link was made before the channel retired. The following coherency model is recommended when executing a dynamic channel link request. 1. Write 1 to the TCD.major.e_link bit. 2. Read back the TCD.major.e_link bit. 3. Test the TCD.major.e_link request status: * If TCD.major.e_link = 1, the dynamic link attempt was successful. * If TCD.major.e_link = 0, the attempted dynamic link did not succeed (the channel was already retiring). For this request, the TCD local memory controller forces the TCD.major.e_link bit to zero on any writes to a channel's TCD.word7 after that channel's TCD.done bit is set, indicating the major loop is complete. NOTE The user must clear the TCD.done bit before writing the TCD.major.e_link bit. The TCD.done bit is cleared automatically by the eDMA engine after a channel begins execution. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 476 Freescale Semiconductor, Inc. Chapter 22 Enhanced Direct Memory Access (eDMA) 22.5.7.3 Dynamic scatter/gather Scatter/gather is the process of automatically loading a new TCD into a channel. It allows a DMA channel to use multiple TCDs; this enables a DMA channel to scatter the DMA data to multiple destinations or gather it from multiple sources.When scatter/gather is enabled and the channel has finished its major loop, a new TCD is fetched from system memory and loaded into that channel's descriptor location in eDMA programmer's model, thus replacing the current descriptor. Because the user is allowed to change the configuration during execution, a coherency model is needed. Consider the scenario where the user attempts to execute a dynamic scatter/gather operation by enabling the TCD.e_sg bit at the same time the eDMA engine is retiring the channel. The TCD.e_sg would be set in the programmer's model, but it would be unclear whether the actual scatter/gather request was honored before the channel retired. Two methods for this coherency model are shown in the following subsections. Method 1 has the advantage of reading the major.linkch field and the e_sg bit with a single read. For both dynamic channel linking and scatter/gather requests, the TCD local memory controller forces the TCD.major.e_link and TCD.e_sg bits to zero on any writes to a channel's TCD.word7 if that channel's TCD.done bit is set indicating the major loop is complete. NOTE The user must clear the TCD.done bit before writing the TCD.major.e_link or TCD.e_sg bits. The TCD.done bit is cleared automatically by the eDMA engine after a channel begins execution. 22.5.7.3.1 Method 1 (channel not using major loop channel linking) For a channel not using major loop channel linking, the coherency model described here may be used for a dynamic scatter/gather request. When the TCD.major.e_link bit is zero, the TCD.major.linkch field is not used by the eDMA. In this case, the TCD.major.linkch bits may be used for other purposes. This method uses the TCD.major.linkch field as a TCD indentification (ID). 1. When the descriptors are built, write a unique TCD ID in the TCD.major.linkch field for each TCD associated with a channel using dynamic scatter/gather. 2. Write 1b to the TCD.d_req bit. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 477 Initialization/application information Should a dynamic scatter/gather attempt fail, setting the TCD.d_req bit will prevent a future hardware activation of this channel. This stops the channel from executing with a destination address (daddr) that was calculated using a scatter/gather address (written in the next step) instead of a dlast final offest value. 3. 4. 5. 6. Write the TCD.dlast_sga field with the scatter/gather address. Write 1b to the TCD.e_sg bit. Read back the 16 bit TCD control/status field. Test the TCD.e_sg request status and TCD.major.linkch value: If e_sg = 1b, the dynamic link attempt was successful. If e_sg = 0b and the major.linkch (ID) did not change, the attempted dynamic link did not succeed (the channel was already retiring). If e_sg = 0b and the major.linkch (ID) changed, the dynamic link attempt was successful (the new TCD's e_sg value cleared the e_sg bit). 22.5.7.3.2 Method 2 (channel using major loop channel linking) For a channel using major loop channel linking, the coherency model described here may be used for a dynamic scatter/gather request. This method uses the TCD.dlast_sga field as a TCD indentification (ID). 1. Write 1b to the TCD.d_req bit. Should a dynamic scatter/gather attempt fail, setting the d_req bit will prevent a future hardware activation of this channel. This stops the channel from executing with a destination address (daddr) that was calculated using a scatter/gather address (written in the next step) instead of a dlast final offest value. 2. 3. 4. 5. Write theTCD.dlast_sga field with the scatter/gather address. Write 1b to the TCD.e_sg bit. Read back the TCD.e_sg bit. Test the TCD.e_sg request status: If e_sg = 1b, the dynamic link attempt was successful. If e_sg = 0b, read the 32 bit TCD dlast_sga field. If e_sg = 0b and the dlast_sga did not change, the attempted dynamic link did not succeed (the channel was already retiring). KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 478 Freescale Semiconductor, Inc. Chapter 22 Enhanced Direct Memory Access (eDMA) If e_sg = 0b and the dlast_sga changed, the dynamic link attempt was successful (the new TCD's e_sg value cleared the e_sg bit). KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 479 Initialization/application information KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 480 Freescale Semiconductor, Inc. Chapter 23 External Watchdog Monitor (EWM) 23.1 Introduction NOTE For the chip-specific implementation details of this module's instances, see the chip configuration information. For safety, a redundant watchdog system, External Watchdog Monitor (EWM), is designed to monitor external circuits, as well as the MCU software flow. This provides a back-up mechanism to the internal watchdog that resets the MCU's CPU and peripherals. The watchdog is generally used to monitor the flow and execution of embedded software within an MCU. The watchdog consists of a counter that if allowed to overflow, forces an internal reset (asynchronous) to all on-chip peripherals and optionally assert the RESET pin to reset external devices/circuits. The overflow of the watchdog counter must not occur if the software code works well and services the watchdog to re-start the actual counter. The EWM differs from the internal watchdog in that it does not reset the MCU's CPU and peripherals. The EWM provides an independent EWM_out signal that when asserted resets or places an external circuit into a safe mode. The EWM_out signal is asserted upon the EWM counter time-out. An optional external input EWM_in is provided to allow additional control of the assertion of EWM_out signal. 23.1.1 Features Features of EWM module include: * Independent LPO_CLK clock source * Programmable time-out period specified in terms of number of EWM LPO_CLK clock cycles. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 481 Introduction * Windowed refresh option * Provides robust check that program flow is faster than expected. * Programmable window. * Refresh outside window leads to assertion of EWM_out. * Robust refresh mechanism * Write values of 0xB4 and 0x2C to EWM Refresh Register within 15 (EWM_refresh_time) peripheral bus clock cycles. * One output port, EWM_out, when asserted is used to reset or place the external circuit into safe mode. * One Input port, EWM_in, allows an external circuit to control the assertion of the EWM_out signal. 23.1.2 Modes of Operation This section describes the module's operating modes. 23.1.2.1 Stop Mode When the EWM is in stop mode, the CPU refreshes to the EWM cannot occur. On entry to stop mode, the EWM's counter freezes. There are two possible ways to exit from Stop mode: * On exit from stop mode through a reset, the EWM remains disabled. * On exit from stop mode by an interrupt, the EWM is re-enabled, and the counter continues to be clocked from the same value prior to entry to stop mode. Note the following if the EWM enters the stop mode during CPU refresh mechanism: At the exit from stop mode by an interrupt, refresh mechanism state machine starts from the previous state which means, if first refresh command is written correctly and EWM enters the stop mode immediately, the next command has to be written within the next 15 (EWM_refresh_time) peripheral bus clocks after exiting from stop mode. User must mask all interrupts prior to executing EWM refresh instructions. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 482 Freescale Semiconductor, Inc. Chapter 23 External Watchdog Monitor (EWM) 23.1.2.2 Wait Mode The EWM module treats the stop and wait modes as the same. EWM functionality remains the same in both of these modes. 23.1.2.3 Debug Mode Entry to debug mode has no effect on the EWM. * If the EWM is enabled prior to entry of debug mode, it remains enabled. * If the EWM is disabled prior to entry of debug mode, it remains disabled. 23.1.3 Block Diagram This figure shows the EWM block diagram. LPO_CLK Clock Divider Logic Low Power Clock Clock Gating Cell Counter Value 8-bit Counter Reset to Counter Enable EWM_CLKPRESCALER[CLK_DIV] AND OR CPU Reset EWM_CTRL[EWMEN] EWM Refreshed Counter overflow EWM_out EWM Refresh And /EWM_out Output Control Mechanism EWM_CMPH[COMPAREH] EWM_CMPL[COMPAREL] EWM_in EWM Service Register Figure 23-1. EWM Block Diagram KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 483 EWM Signal Descriptions 23.2 EWM Signal Descriptions The EWM has two external signals, as shown in the following table. Table 23-1. EWM Signal Descriptions Signal Description EWM_in EWM_out I/O EWM input for safety status of external safety circuits. The polarity of EWM_in is programmable using the EWM_CTRL[ASSIN] bit. The default polarity is active-low. I EWM reset out signal O 23.3 Memory Map/Register Definition This section contains the module memory map and registers. EWM memory map Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 4006_1000 Control Register (EWM_CTRL) 8 R/W 00h 23.3.1/484 4006_1001 Service Register (EWM_SERV) 8 W (always reads 0) 00h 23.3.2/485 4006_1002 Compare Low Register (EWM_CMPL) 8 R/W 00h 23.3.3/485 4006_1003 Compare High Register (EWM_CMPH) 8 R/W FFh 23.3.4/486 4006_1005 Clock Prescaler Register (EWM_CLKPRESCALER) 8 R/W 00h 23.3.5/487 23.3.1 Control Register (EWM_CTRL) The CTRL register is cleared by any reset. NOTE INEN, ASSIN and EWMEN bits can be written once after a CPU reset. Modifying these bits more than once, generates a bus transfer error. Address: 4006_1000h base + 0h offset = 4006_1000h Bit Read Write Reset 7 6 5 4 0 0 0 0 0 3 2 1 0 INTEN INEN ASSIN EWMEN 0 0 0 0 KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 484 Freescale Semiconductor, Inc. Chapter 23 External Watchdog Monitor (EWM) EWM_CTRL field descriptions Field 7-4 Reserved 3 INTEN 2 INEN 1 ASSIN 0 EWMEN Description This field is reserved. This read-only field is reserved and always has the value 0. Interrupt Enable. This bit when set and EWM_out is asserted, an interrupt request is generated. To de-assert interrupt request, user should clear this bit by writing 0. Input Enable. This bit when set, enables the EWM_in port. EWM_in's Assertion State Select. Default assert state of the EWM_in signal is logic zero. Setting the ASSIN bit inverts the assert state of EWM_in signal to a logic one. EWM enable. This bit when set, enables the EWM module. This resets the EWM counter to zero and deasserts the EWM_out signal. This bit when unset, keeps the EWM module disabled. It cannot be re-enabled until a next reset, due to the write-once nature of this bit. 23.3.2 Service Register (EWM_SERV) The SERV register provides the interface from the CPU to the EWM module. It is writeonly and reads of this register return zero. Address: 4006_1000h base + 1h offset = 4006_1001h Bit 7 6 5 4 Read 0 Write SERVICE Reset 0 0 0 0 3 2 1 0 0 0 0 0 EWM_SERV field descriptions Field SERVICE Description The EWM refresh mechanism requires the CPU to write two values to the SERV register: a first data byte of 0xB4, followed by a second data byte of 0x2C. The EWM refresh is invalid if either of the following conditions is true. * The first or second data byte is not written correctly. * The second data byte is not written within a fixed number of peripheral bus cycles of the first data byte. This fixed number of cycles is called EWM_refresh_time. 23.3.3 Compare Low Register (EWM_CMPL) The CMPL register is reset to zero after a CPU reset. This provides no minimum time for the CPU to refresh the EWM counter. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 485 Memory Map/Register Definition NOTE This register can be written only once after a CPU reset. Writing this register more than once generates a bus transfer error. Address: 4006_1000h base + 2h offset = 4006_1002h Bit Read Write Reset 7 6 5 4 3 2 1 0 0 0 0 0 COMPAREL 0 0 0 0 EWM_CMPL field descriptions Field COMPAREL Description To prevent runaway code from changing this field, software should write to this field after a CPU reset even if the (default) minimum refresh time is required. 23.3.4 Compare High Register (EWM_CMPH) The CMPH register is reset to 0xFF after a CPU reset. This provides a maximum of 256 clocks time, for the CPU to refresh the EWM counter. NOTE This register can be written only once after a CPU reset. Writing this register more than once generates a bus transfer error. NOTE The valid values for CMPH are up to 0xFE because the EWM counter never expires when CMPH = 0xFF. The expiration happens only if EWM counter is greater than CMPH. Address: 4006_1000h base + 3h offset = 4006_1003h Bit Read Write Reset 7 6 5 4 3 2 1 0 1 1 1 1 COMPAREH 1 1 1 1 EWM_CMPH field descriptions Field COMPAREH Description To prevent runaway code from changing this field, software should write to this field after a CPU reset even if the (default) maximum refresh time is required. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 486 Freescale Semiconductor, Inc. Chapter 23 External Watchdog Monitor (EWM) 23.3.5 Clock Prescaler Register (EWM_CLKPRESCALER) This CLKPRESCALER register is reset to 0x00 after a CPU reset. NOTE This register can be written only once after a CPU reset. Writing this register more than once generates a bus transfer error. NOTE Write the required prescaler value before enabling the EWM. NOTE The implementation of this register is chip-specific. See the Chip Configuration details. Address: 4006_1000h base + 5h offset = 4006_1005h Bit Read Write Reset 7 6 5 4 3 2 1 0 0 0 0 0 CLK_DIV 0 0 0 0 EWM_CLKPRESCALER field descriptions Field CLK_DIV Description Selected low power clock source for running the EWM counter can be prescaled as below. * Prescaled clock frequency = low power clock source frequency / ( 1 + CLK_DIV ) 23.4 Functional Description The following sections describe functional details of the EWM module. NOTE When the BUS_CLK is lost, then EWM module doesn't generate the EWM_out signal and no refresh operation is possible 23.4.1 The EWM_out Signal The EWM_out is a digital output signal used to gate an external circuit (application specific) that controls critical safety functions. For example, the EWM_out could be connected to the high voltage transistors circuits that control an AC motor in a large appliance. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 487 Functional Description The EWM_out signal remains deasserted when the EWM is being regularly refreshed by the CPU within the programmable refresh window, indicating that the application code is executed as expected. The EWM_out signal is asserted in any of the following conditions: * The EWM refresh occurs when the counter value is less than CMPL value. * The EWM counter value reaches the CMPH value, and no EWM refresh has occurred. * If functionality of EWM_in pin is enabled and EWM_in pin is asserted while refreshing the EWM. * After any reset (by the virtue of the external pull-down mechanism on the EWM_out pin) The EWM_out is asserted after any reset by the virtue of the external pull-down mechanism on the EWM_out signal. Then, to deassert the EWM_out signal, set EWMEN bit in the CTRL register to enable the EWM. If the EWM_out signal shares its pad with a digital I/O pin, on reset this actual pad defers to being an input signal. The pad state is controlled by the EWM_out signal only after the EWM is enabled by the EWMEN bit in the CTRL register. Note EWM_out pad must be in pull down state when EWM functionality is used and when EWM is under Reset. 23.4.2 The EWM_in Signal The EWM_in is a digital input signal for safety status of external safety circuits, that allows an external circuit to control the assertion of the EWM_out signal. For example, in the application, an external circuit monitors a critical safety function, and if there is fault with safety function, the external circuit can then actively initiate the EWM_out signal that controls the gating circuit. The EWM_in signal is ignored if the EWM is disabled, or if INEN bit of CTRL register is cleared, as after any reset. On enabling the EWM (setting the CTRL[EWMEN] bit) and enabling EWM_in functionality (setting the CTRL[INEN] bit), the EWM_in signal must be in the deasserted state prior to the CPU start refreshing the EWM. This ensures that the EWM_out stays in the deasserted state; otherwise, the EWM_out output signal is asserted. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 488 Freescale Semiconductor, Inc. Chapter 23 External Watchdog Monitor (EWM) Note The user must update the CMPH and CMPL registers prior to enabling the EWM. After enabling the EWM, the counter resets to zero, therefore the user shall provide a reasonable time after a power-on reset for the external monitoring circuit to stabilize. The user shall also ensure that the EWM_in pin is deasserted. 23.4.3 EWM Counter It is an 8-bit ripple counter fed from a clock source that is independent of the peripheral bus clock source. As the preferred time-out is between 1 ms and 100 ms the actual clock source should be in the kHz range. The counter is reset to zero after the CPU reset, or when EWM refresh action completes, or at counter overflow. The counter value is not accessible to the CPU. 23.4.4 EWM Compare Registers The compare registers CMPL and CMPH are write-once after a CPU reset and cannot be modified until another CPU reset occurs. The EWM compare registers are used to create a refresh window to refresh the EWM module. It is illegal to program CMPL and CMPH with same value. In this case, as soon as counter reaches (CMPL + 1), EWM_out is asserted. 23.4.5 EWM Refresh Mechanism Other than the initial configuration of the EWM, the CPU can only access the EWM by the EWM Service Register. The CPU must access the EWM service register with correct write of unique data within the windowed time frame as determined by the CMPL and CMPH registers for correct EWM refresh operation. Therefore, three possible conditions can occur: KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 489 Functional Description Table 23-2. EWM Refresh Mechanisms Condition Mechanism An EWM refresh action completes when: The software behaves as expected and the EWM counter is reset to zero. The EWM_out output signal remains in the deasserted state if, during the EWM refresh action, the EWM_in input has been in deasserted state.. CMPL < Counter < CMPH. An EWM refresh action completes when Counter < CMPL The software refreshes the EWM before the windowed time frame, the counter is reset to zero and the EWM_out output signal is asserted irrespective of the input EWM_in. Counter value reaches CMPH prior to completion of EWM refresh action. Software has not refreshed the EWM. The EWM counter is reset to zero and the EWM_out output signal is asserted irrespective of the input EWM_in. 23.4.6 EWM Interrupt When EWM_out is asserted, an interrupt request is generated to indicate the assertion of the EWM reset out signal. This interrupt is enabled when CTRL[INTEN] is set. Clearing this bit clears the interrupt request but does not affect EWM_out. The EWM_out signal can be deasserted only by forcing a system reset. 23.4.7 Counter clock prescaler The EWM counter clock source can be prescaled by a clock divider, by programming CLKPRESCALER[CLK_DIV]. This divided clock is used to run the EWM counter. NOTE The divided clock used to run the EWM counter must be no more than half the frequency of the bus clock. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 490 Freescale Semiconductor, Inc. Chapter 24 Watchdog Timer (WDOG) 24.1 Introduction NOTE For the chip-specific implementation details of this module's instances, see the chip configuration information. The Watchdog Timer (WDOG) keeps a watch on the system functioning and resets it in case of its failure. Reasons for failure include run-away software code and the stoppage of the system clock that in a safety critical system can lead to serious consequences. In such cases, the watchdog brings the system into a safe state of operation. The watchdog monitors the operation of the system by expecting periodic communication from the software, generally known as servicing or refreshing the watchdog. If this periodic refreshing does not occur, the watchdog resets the system. 24.2 Features The features of the Watchdog Timer (WDOG) include: * Clock source input independent from CPU/bus clock. Choice between two clock sources: * Low-power oscillator (LPO) * External system clock * Unlock sequence for allowing updates to write-once WDOG control/configuration bits. * All WDOG control/configuration bits are writable once only within 256 bus clock cycles of being unlocked. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 491 Functional overview * You need to always update these bits after unlocking within 256 bus clock cycles. Failure to update these bits resets the system. * Programmable time-out period specified in terms of number of WDOG clock cycles. * Ability to test WDOG timer and reset with a flag indicating watchdog test. * Quick test--Small time-out value programmed for quick test. * Byte test--Individual bytes of timer tested one at a time. * Read-only access to the WDOG timer--Allows dynamic check that WDOG timer is operational. NOTE Reading the watchdog timer counter while running the watchdog on the bus clock might not give the accurate counter value. * Windowed refresh option * Provides robust check that program flow is faster than expected. * Programmable window. * Refresh outside window leads to reset. * Robust refresh mechanism * Write values of 0xA602 and 0xB480 to WDOG Refresh Register within 20 bus clock cycles. * Count of WDOG resets as they occur. * Configurable interrupt on time-out to provide debug breadcrumbs. This is followed by a reset after 256 bus clock cycles. 24.3 Functional overview KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 492 Freescale Semiconductor, Inc. Chapter 24 Watchdog Timer (WDOG) WDOG Unlock Sequence 2 Writes of data within K bus clock cycles of each other Disable Control/Configuration bit changes N bus clk cycles after unlocking Refresh Sequence 2 writes of data within K bus clock cycles of each other 0xC520 N bus clk cycles 0xD928 0xA602 0xB480 Allow update for N bus clk cycles WDOGEN WAITEN STOPEN Window_begin No unlock after reset WINEN DebugEN System Bus Clock WDOG CLKSRC 32-bit Modulus Reg (Time-out Value) 32-bit Timer Y Invalid Refresh Seq IRQ_RST_ EN = = 1? Refresh Outside Window N Timer Time-out WDOGTEST N bus clk cycles R WDOGT Interrupt No config after unlocking System reset and SRS register Invalid Unlock Seq LPO WDOG reset count Osc Alt Clock Fast Fn Test Clock WDOG Clock Selection WDOG CLK WDOGEN = WDOG Enable WINEN = Windowed Mode Enable WDOGT = WDOG Time-out Value WDOGCLKSRC = WDOG Clock Source WDOG Test = WDOG Test Mode WAIT EN = Enable in wait mode STOP EN = Enable in stop mode Debug EN = Enable in debug mode SRS = System Reset Status Register R = Timer Reload Figure 24-1. WDOG operation The preceding figure shows the operation of the watchdog. The values for N and K are: * N = 256 * K = 20 The watchdog is a fail safe mechanism that brings the system into a known initial state in case of its failure due to CPU clock stopping or a run-away condition in code execution. In its simplest form, the watchdog timer runs continuously off a clock source and expects to be serviced periodically, failing which it resets the system. This ensures that the software is executing correctly and has not run away in an unintended direction. Software can adjust the period of servicing or the time-out value for the watchdog timer to meet the needs of the application. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 493 Functional overview You can select a windowed mode of operation that expects the servicing to be done only in a particular window of the time-out period. An attempted servicing of the watchdog outside this window results in a reset. By operating in this mode, you can get an indication of whether the code is running faster than expected. The window length is also user programmable. If a system fails to update/refresh the watchdog due to an unknown and persistent cause, it will be caught in an endless cycle of resets from the watchdog. To analyze the cause of such conditions, you can program the watchdog to first issue an interrupt, followed by a reset. In the interrupt service routine, the software can analyze the system stack to aid debugging. To enhance the independence of watchdog from the system, it runs off an independent LPO oscillator clock. You can also switch over to an alternate clock source if required, through a control register bit. 24.3.1 Unlocking and updating the watchdog As long as ALLOW_UPDATE in the watchdog control register is set, you can unlock and modify the write-once-only control and configuration registers: 1. Write 0xC520 followed by 0xD928 within 20 bus clock cycles to a specific unlock register (WDOG_UNLOCK). 2. Wait one bus clock cycle. You cannot update registers on the bus clock cycle immediately following the write of the unlock sequence. 3. An update window equal in length to the watchdog configuration time (WCT) opens. Within this window, you can update the configuration and control register bits. These register bits can be modified only once after unlocking. If none of the configuration and control registers is updated within the update window, the watchdog issues a reset, that is, interrupt-then-reset, to the system. Trying to unlock the watchdog within the WCT after an initial unlock has no effect. During the update operation, the watchdog timer is not paused and continues running in the background. After the update window closes, the watchdog timer restarts and the watchdog functions according to the new configuration. The update feature is useful for applications that have an initial, non-safety critical part, where the watchdog is kept disabled or with a conveniently long time-out period. This means the application coder does not have to frequently service the watchdog. After the critical part of the application begins, the watchdog can be reconfigured as needed. The watchdog issues a reset, that is, interrupt-then-reset if enabled, to the system for any of these invalid unlock sequences: KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 494 Freescale Semiconductor, Inc. Chapter 24 Watchdog Timer (WDOG) * Write any value other than 0xC520 or 0xD928 to the unlock register. * ALLOW_UPDATE is set and a gap of more than 20 bus clock cycles is inserted between the writing of the unlock sequence values. An attempted refresh operation between the two writes of the unlock sequence and in the WCT time following a successful unlock, goes undetected. Also, see Watchdog Operation with 8-bit access for guidelines related to 8-bit accesses to the unlock register. Note A context switch during unlocking and refreshing may lead to a watchdog reset. 24.3.2 Watchdog configuration time (WCT) To prevent unintended modification of the watchdog's control and configuration register bits, you are allowed to update them only within a period of 256 bus clock cycles after unlocking. This period is known as the watchdog configuration time (WCT). In addition, these register bits can be modified only once after unlocking them for editing, even after reset. You must unlock the registers within WCT after system reset, failing which the WDOG issues a reset to the system. In other words, you must write at least the first word of the unlocking sequence within the WCT after reset. After this is done, you have a further 20 bus clock cycles, the maximum allowed gap between the words of the unlock sequence, to complete the unlocking operation. Thereafter, to make sure that you do not forget to configure the watchdog, the watchdog issues a reset if none of the WDOG control and configuration registers is updated in the WCT after unlock. After the close of this window or after the first write, these register bits are locked out from any further changes. The watchdog timer keeps running according to its default configuration through unlocking and update operations that can extend up to a maximum total of 2xWCT + 20 bus clock cycles. Therefore, it must be ensured that the time-out value for the watchdog is always greater than 2xWCT time + 20 bus clock cycles. Updates in the write-once registers take effect only after the WCT window closes with the following exceptions for which changes take effect immediately: * Stop, Wait, and Debug mode enable * IRQ_RST_EN The operations of refreshing the watchdog goes undetected during the WCT. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 495 Functional overview 24.3.3 Refreshing the watchdog A robust refreshing mechanism has been chosen for the watchdog. A valid refresh is a write of 0xA602 followed by 0xB480 within 20 bus clock cycles to watchdog refresh register. If these two values are written more than 20 bus cycles apart or if something other than these two values is written to the register, a watchdog reset, or interrupt-thenreset if enabled, is issued to the system. A valid refresh makes the watchdog timer restart on the next bus clock. Also, an attempted unlock operation in between the two writes of the refresh sequence goes undetected. See Watchdog Operation with 8-bit access for guidelines related to 8-bit accesses to the refresh register. 24.3.4 Windowed mode of operation In this mode of operation, a restriction is placed on the point in time within the time-out period at which the watchdog can be refreshed. The refresh is considered valid only when the watchdog timer increments beyond a certain count as specified by the watchdog window register. This is known as refreshing the watchdog within a window of the total time-out period. If a refresh is attempted before the timer reaches the window value, the watchdog generates a reset, or interrupt-then-reset if enabled. If there is no refresh at all, the watchdog times out and generates a reset or interrupt-then-reset if enabled. 24.3.5 Watchdog disabled mode of operation When the watchdog is disabled through the WDOG_EN bit in the watchdog status and control register, the watchdog timer is reset to zero and is disabled from counting until you enable it or it is enabled again by the system reset. In this mode, the watchdog timer cannot be refreshed-there is no requirement to do so while the timer is disabled. However, the watchdog still generates a reset, or interrupt-then-reset if enabled, on a nontime-out exception. See Generated Resets and Interrupts. You need to unlock the watchdog before enabling it. A system reset brings the watchdog out of the disabled mode. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 496 Freescale Semiconductor, Inc. Chapter 24 Watchdog Timer (WDOG) 24.3.6 Debug modes of operation You can program the watchdog to disable in debug modes through DBG_EN in the watchdog control register. This results in the watchdog timer pausing for the duration of the mode. Register read/writes are still allowed, which means that operations like refresh, unlock, and so on are allowed. Upon exit from the mode, the timer resumes its operation from the point of pausing. The entry of the system into the mode does not excuse it from compulsorily configuring the watchdog in the WCT time after unlock, unless the system bus clock is gated off, in which case the internal state machine pauses too. Failing to do so still results in a reset, or interrupt-then-reset, if enabled, to the system. Also, all of the exception conditions that result in a reset to the system, as described in Generated Resets and Interrupts, are still valid in mode. So, if an exception condition occurs and the system bus clock is on, a reset occurs, or interrupt-then-reset, if enabled. The entry into Debug mode within WCT after reset is treated differently. The WDOG timer is kept reset to zero and there is no need to unlock and configure it within WCT. You must not try to refresh or unlock the WDOG in this state or unknown behavior may result. Upon exit from mode, the WDOG timer restarts and the WDOG has to be unlocked and configured within WCT. 24.4 Testing the watchdog For IEC 60730 and other safety standards, the expectation is that anything that monitors a safety function must be tested, and this test is required to be fault tolerant. To test the watchdog, its main timer and its associated compare and reset logic must be tested. To this end, two tests are implemented for the watchdog, as described in Quick Test and Byte Test. A control bit is provided to put the watchdog into functional test mode. There is also an overriding test-disable control bit which allows the functional test mode to be disabled permanently. After it is set, this test-disable bit can only be cleared by a reset. These two tests achieve the overall aim of testing the counter functioning and the compare and reset logic. Note Do not enable the watchdog interrupt during these tests. If required, you must ensure that the effective time-out value is greater than WCT time. See Generated Resets and Interrupts for more details. To run a particular test: KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 497 Testing the watchdog 1. Select either quick test or byte test.. 2. Set a certain test mode bit to put the watchdog in the functional test mode. Setting this bit automatically switches the watchdog timer to a fast clock source. The switching of the clock source is done to achieve a faster time-out and hence a faster test. In a successful test, the timer times out after reaching the programmed time-out value and generates a system reset. Note After emerging from a reset due to a watchdog test, unlock and configure the watchdog. The refresh and unlock operations and interrupt are not automatically disabled in the test mode. 24.4.1 Quick test In this test, the time-out value of watchdog timer is programmed to a very low value to achieve quick time-out. The only difference between the quick test and the normal mode of the watchdog is that TESTWDOG is set for the quick test. This allows for a faster test of the watchdog reset mechanism. 24.4.2 Byte test The byte test is a more thorough a test of the watchdog timer. In this test, the timer is split up into its constituent byte-wide stages that are run independently and tested for time-out against the corresponding byte of the time-out value register. The following figure explains the splitting concept: KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 498 Freescale Semiconductor, Inc. Chapter 24 Watchdog Timer (WDOG) Reset Value (Hardwired) Modulus Register (Time-out Value) Byte 3 Byte 2 Byte 1 Byte 4 WDOG Reset WDOG Test Equality Comparison Mod = = Timer? 32-bit Timer Byte Stage 1 en Byte Stage 2 en Byte Stage 3 en Byte Stage 4 CLK Nth Stage Overflow Enables N + 1th Stage Figure 24-2. Watchdog timer byte splitting Each stage is an 8-bit synchronous counter followed by combinational logic that generates an overflow signal. The overflow signal acts as an enable to the N + 1th stage. In the test mode, when an individual byte, N, is tested, byte N - 1 is loaded forcefully with 0xFF, and both these bytes are allowed to run off the clock source. By doing so, the overflow signal from stage N - 1 is generated immediately, enabling counter stage N. The Nth stage runs and compares with the Nth byte of the time-out value register. In this way, the byte N is also tested along with the link between it and the preceding stage. No other stages, N - 2, N - 3... and N + 1, N + 2... are enabled for the test on byte N. These disabled stages, except the most significant stage of the counter, are loaded with a value of 0xFF. 24.5 Backup reset generator The backup reset generator generates the final reset which goes out to the system. It has a backup mechanism which ensures that in case the bus clock stops and prevents the main state machine from generating a reset exception/interrupt, the watchdog timer's time-out is separately routed out as a reset to the system. Two successive timer time-outs without an intervening system reset result in the backup reset generator routing out the time-out signal as a reset to the system. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 499 Generated resets and interrupts 24.6 Generated resets and interrupts The watchdog generates a reset in the following events, also referred to as exceptions: * A watchdog time-out * Failure to unlock the watchdog within WCT time after system reset deassertion * No update of the control and configuration registers within the WCT window after unlocking. At least one of the following registers must be written to within the WCT window to avoid reset: * WDOG_ST_CTRL_H, WDOG_ST_CTRL_L * WDOG_TO_VAL_H, WDOG_TO_VAL_L * WDOG_WIN_H, WDOG_WIN_L * WDOG_PRESCALER * A value other than the unlock sequence or the refresh sequence is written to the unlock and/or refresh registers, respectively. * A gap of more than 20 bus cycles exists between the writes of two values of the unlock sequence. * A gap of more than 20 bus cycles exists between the writes of two values of the refresh sequence. The watchdog can also generate an interrupt. If IRQ_RST_EN is set, then on the above mentioned events WDOG_ST_CTRL_L[INT_FLG] is set, generating an interrupt. A watchdog reset is also generated WCT time later to ensure the watchdog is fault tolerant. The interrupt can be cleared by writing 1 to INT_FLG. The gap of WCT between interrupt and reset means that the WDOG time-out value must be greater than WCT. Otherwise, if the interrupt was generated due to a time-out, a second consecutive time-out will occur in that WCT gap. This will trigger the backup reset generator to generate a reset to the system, prematurely ending the interrupt service routine execution. Also, jobs such as counting the number of watchdog resets would not be done. 24.7 Memory map and register definition This section consists of the memory map and register descriptions. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 500 Freescale Semiconductor, Inc. Chapter 24 Watchdog Timer (WDOG) WDOG memory map Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 4005_2000 Watchdog Status and Control Register High (WDOG_STCTRLH) 16 R/W 01D3h 24.7.1/501 4005_2002 Watchdog Status and Control Register Low (WDOG_STCTRLL) 16 R/W 0001h 24.7.2/503 4005_2004 Watchdog Time-out Value Register High (WDOG_TOVALH) 16 R/W 004Ch 24.7.3/503 4005_2006 Watchdog Time-out Value Register Low (WDOG_TOVALL) 16 R/W 4B4Ch 24.7.4/504 4005_2008 Watchdog Window Register High (WDOG_WINH) 16 R/W 0000h 24.7.5/504 4005_200A Watchdog Window Register Low (WDOG_WINL) 16 R/W 0010h 24.7.6/505 4005_200C Watchdog Refresh register (WDOG_REFRESH) 16 R/W B480h 24.7.7/505 4005_200E Watchdog Unlock register (WDOG_UNLOCK) 16 R/W D928h 24.7.8/505 4005_2010 Watchdog Timer Output Register High (WDOG_TMROUTH) 16 R/W 0000h 24.7.9/506 4005_2012 Watchdog Timer Output Register Low (WDOG_TMROUTL) 16 R/W 0000h 24.7.10/ 506 4005_2014 Watchdog Reset Count register (WDOG_RSTCNT) 16 R/W 0000h 24.7.11/ 507 4005_2016 Watchdog Prescaler register (WDOG_PRESC) 16 R/W 0400h 24.7.12/ 507 24.7.1 Watchdog Status and Control Register High (WDOG_STCTRLH) 0 4 3 2 1 0 WDOGEN 0 5 CLKSRC 0 6 IRQRSTEN 0 7 WINEN 0 0 8 ALLOWUPDAT E 0 9 DBGEN 0 10 STOPEN Reset 11 WAITEN Write 12 Reserved 0 13 TESTWDOG Read 14 BYTESEL[1:0] 15 DISTESTWDO G Bit TESTSEL Address: 4005_2000h base + 0h offset = 4005_2000h 1 1 1 0 1 0 0 1 1 WDOG_STCTRLH field descriptions Field 15 Reserved Description This field is reserved. This read-only field is reserved and always has the value 0. 14 Allows the WDOG's functional test mode to be disabled permanently. After it is set, it can only be cleared DISTESTWDOG by a reset. It cannot be unlocked for editing after it is set. 0 1 13-12 BYTESEL[1:0] WDOG functional test mode is not disabled. WDOG functional test mode is disabled permanently until reset. This 2-bit field selects the byte to be tested when the watchdog is in the byte test mode. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 501 Memory map and register definition WDOG_STCTRLH field descriptions (continued) Field Description 00 01 10 11 11 TESTSEL 10 TESTWDOG Byte 0 selected Byte 1 selected Byte 2 selected Byte 3 selected Effective only if TESTWDOG is set. Selects the test to be run on the watchdog timer. 0 1 Quick test. The timer runs in normal operation. You can load a small time-out value to do a quick test. Byte test. Puts the timer in the byte test mode where individual bytes of the timer are enabled for operation and are compared for time-out against the corresponding byte of the programmed time-out value. Select the byte through BYTESEL[1:0] for testing. Puts the watchdog in the functional test mode. In this mode, the watchdog timer and the associated compare and reset generation logic is tested for correct operation. The clock for the timer is switched from the main watchdog clock to the fast clock input for watchdog functional test. The TESTSEL bit selects the test to be run. 9 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 8 Reserved This field is reserved. 7 WAITEN Enables or disables WDOG in Wait mode. 6 STOPEN Enables or disables WDOG in Stop mode. 5 DBGEN Enables or disables WDOG in Debug mode. 0 1 0 1 0 1 WDOG is disabled in CPU Wait mode. WDOG is enabled in CPU Wait mode. WDOG is disabled in CPU Stop mode. WDOG is enabled in CPU Stop mode. WDOG is disabled in CPU Debug mode. WDOG is enabled in CPU Debug mode. 4 Enables updates to watchdog write-once registers, after the reset-triggered initial configuration window ALLOWUPDATE (WCT) closes, through unlock sequence. 0 1 3 WINEN 2 IRQRSTEN Enables Windowing mode. 0 1 Windowing mode is disabled. Windowing mode is enabled. Used to enable the debug breadcrumbs feature. A change in this bit is updated immediately, as opposed to updating after WCT. 0 1 1 CLKSRC No further updates allowed to WDOG write-once registers. WDOG write-once registers can be unlocked for updating. WDOG time-out generates reset only. WDOG time-out initially generates an interrupt. After WCT, it generates a reset. Selects clock source for the WDOG timer and other internal timing operations. 0 1 WDOG clock sourced from LPO . WDOG clock sourced from alternate clock source. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 502 Freescale Semiconductor, Inc. Chapter 24 Watchdog Timer (WDOG) WDOG_STCTRLH field descriptions (continued) Field Description 0 WDOGEN Enables or disables the WDOG's operation. In the disabled state, the watchdog timer is kept in the reset state, but the other exception conditions can still trigger a reset/interrupt. A change in the value of this bit must be held for more than one WDOG_CLK cycle for the WDOG to be enabled or disabled. 0 1 WDOG is disabled. WDOG is enabled. 24.7.2 Watchdog Status and Control Register Low (WDOG_STCTRLL) Address: 4005_2000h base + 2h offset = 4005_2002h Bit Read Write Reset 15 14 13 12 11 INTFLG Bit Read Write Reset 10 9 8 Reserved 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 1 Reserved 0 0 0 0 WDOG_STCTRLL field descriptions Field Description 15 INTFLG Interrupt flag. It is set when an exception occurs. IRQRSTEN = 1 is a precondition to set this flag. INTFLG = 1 results in an interrupt being issued followed by a reset, WCT later. The interrupt can be cleared by writing 1 to this bit. It also gets cleared on a system reset. Reserved This field is reserved. NOTE: Do not modify this field value. 24.7.3 Watchdog Time-out Value Register High (WDOG_TOVALH) Address: 4005_2000h base + 4h offset = 4005_2004h Bit Read Write Reset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 0 1 1 0 0 TOVALHIGH 0 0 0 0 0 0 0 0 0 WDOG_TOVALH field descriptions Field Description TOVALHIGH Defines the upper 16 bits of the 32-bit time-out value for the watchdog timer. It is defined in terms of cycles of the watchdog clock. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 503 Memory map and register definition 24.7.4 Watchdog Time-out Value Register Low (WDOG_TOVALL) The time-out value of the watchdog must be set to a minimum of four watchdog clock cycles. This is to take into account the delay in new settings taking effect in the watchdog clock domain. Address: 4005_2000h base + 6h offset = 4005_2006h Bit Read Write Reset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 0 1 1 0 0 TOVALLOW 0 1 0 0 1 0 1 1 0 WDOG_TOVALL field descriptions Field Description TOVALLOW Defines the lower 16 bits of the 32-bit time-out value for the watchdog timer. It is defined in terms of cycles of the watchdog clock. 24.7.5 Watchdog Window Register High (WDOG_WINH) NOTE You must set the Window Register value lower than the Timeout Value Register. Address: 4005_2000h base + 8h offset = 4005_2008h Bit Read Write Reset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 WINHIGH 0 0 0 0 0 0 0 0 0 WDOG_WINH field descriptions Field WINHIGH Description Defines the upper 16 bits of the 32-bit window for the windowed mode of operation of the watchdog. It is defined in terms of cycles of the watchdog clock. In this mode, the watchdog can be refreshed only when the timer has reached a value greater than or equal to this window length. A refresh outside this window resets the system or if IRQRSTEN is set, it interrupts and then resets the system. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 504 Freescale Semiconductor, Inc. Chapter 24 Watchdog Timer (WDOG) 24.7.6 Watchdog Window Register Low (WDOG_WINL) NOTE You must set the Window Register value lower than the Timeout Value Register. Address: 4005_2000h base + Ah offset = 4005_200Ah Bit Read Write Reset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 0 0 0 WINLOW 0 0 0 0 0 0 0 0 0 WDOG_WINL field descriptions Field Description WINLOW Defines the lower 16 bits of the 32-bit window for the windowed mode of operation of the watchdog. It is defined in terms of cycles of the pre-scaled watchdog clock. In this mode, the watchdog can be refreshed only when the timer reaches a value greater than or equal to this window length value. A refresh outside of this window resets the system or if IRQRSTEN is set, it interrupts and then resets the system. 24.7.7 Watchdog Refresh register (WDOG_REFRESH) Address: 4005_2000h base + Ch offset = 4005_200Ch Bit Read Write Reset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 WDOGREFRESH 1 0 1 1 0 1 0 0 1 WDOG_REFRESH field descriptions Field Description WDOGREFRESH Watchdog refresh register. A sequence of 0xA602 followed by 0xB480 within 20 bus clock cycles written to this register refreshes the WDOG and prevents it from resetting the system. Writing a value other than the above mentioned sequence or if the sequence is longer than 20 bus cycles, resets the system, or if IRQRSTEN is set, it interrupts and then resets the system. 24.7.8 Watchdog Unlock register (WDOG_UNLOCK) Address: 4005_2000h base + Eh offset = 4005_200Eh Bit Read Write Reset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 1 0 0 0 WDOGUNLOCK 1 1 0 1 1 0 0 1 0 KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 505 Memory map and register definition WDOG_UNLOCK field descriptions Field Description WDOGUNLOCK Writing the unlock sequence values to this register to makes the watchdog write-once registers writable again. The required unlock sequence is 0xC520 followed by 0xD928 within 20 bus clock cycles. A valid unlock sequence opens a window equal in length to the WCT within which you can update the registers. Writing a value other than the above mentioned sequence or if the sequence is longer than 20 bus cycles, resets the system or if IRQRSTEN is set, it interrupts and then resets the system. The unlock sequence is effective only if ALLOWUPDATE is set. 24.7.9 Watchdog Timer Output Register High (WDOG_TMROUTH) Address: 4005_2000h base + 10h offset = 4005_2010h Bit Read Write Reset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 TIMEROUTHIGH 0 0 0 0 0 0 0 0 0 WDOG_TMROUTH field descriptions Field Description TIMEROUTHIGH Shows the value of the upper 16 bits of the watchdog timer. 24.7.10 Watchdog Timer Output Register Low (WDOG_TMROUTL) During Stop mode, the WDOG_TIMER_OUT will be caught at the pre-stop value of the watchdog timer. After exiting Stop mode, a maximum delay of 1 WDOG_CLK cycle + 3 bus clock cycles will occur before the WDOG_TIMER_OUT starts following the watchdog timer. Address: 4005_2000h base + 12h offset = 4005_2012h Bit Read Write Reset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 TIMEROUTLOW 0 0 0 0 0 0 0 0 0 WDOG_TMROUTL field descriptions Field Description TIMEROUTLOW Shows the value of the lower 16 bits of the watchdog timer. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 506 Freescale Semiconductor, Inc. Chapter 24 Watchdog Timer (WDOG) 24.7.11 Watchdog Reset Count register (WDOG_RSTCNT) Address: 4005_2000h base + 14h offset = 4005_2014h Bit Read Write Reset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 RSTCNT 0 0 0 0 0 0 0 0 0 WDOG_RSTCNT field descriptions Field Description RSTCNT Counts the number of times the watchdog resets the system. This register is reset only on a POR. Writing 1 to the bit to be cleared enables you to clear the contents of this register. 24.7.12 Watchdog Prescaler register (WDOG_PRESC) Address: 4005_2000h base + 16h offset = 4005_2016h Bit Read Write Reset 15 14 13 12 11 10 0 0 0 0 9 8 7 6 5 4 PRESCVAL 0 0 1 0 3 2 1 0 0 0 0 0 0 0 0 0 0 0 WDOG_PRESC field descriptions Field 15-11 Reserved 10-8 PRESCVAL Reserved Description This field is reserved. This read-only field is reserved and always has the value 0. 3-bit prescaler for the watchdog clock source. A value of zero indicates no division of the input WDOG clock. The watchdog clock is divided by (PRESCVAL + 1) to provide the prescaled WDOG_CLK. This field is reserved. This read-only field is reserved and always has the value 0. 24.8 Watchdog operation with 8-bit access 24.8.1 General guideline When performing 8-bit accesses to the watchdog's 16-bit registers where the intention is to access both the bytes of a register, place the two 8-bit accesses one after the other in your code. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 507 Watchdog operation with 8-bit access 24.8.2 Refresh and unlock operations with 8-bit access One exception condition that generates a reset to the system is the write of any value other than those required for a legal refresh/update sequence to the respective refresh and unlock registers. For an 8-bit access to these registers, writing a correct value requires at least two bus clock cycles, resulting in an invalid value in the registers for one cycle. Therefore, the system is reset even if the intention is to write a correct value to the refresh/unlock register. Keeping this in mind, the exception condition for 8-bit accesses is slightly modified. Whereas the match for a correct value for a refresh/unlock sequence is as according to the original definition, the match for an incorrect value is done byte-wise on the refresh/ unlock rather than for the whole 16-bit value. This means that if the high byte of the refresh/unlock register contains any value other than high bytes of the two values that make up the sequence, it is treated as an exception condition, leading to a reset or interrupt-then-reset. The same holds true for the lower byte of the refresh or unlock register. Take the refresh operation that expects a write of 0xA602 followed by 0xB480 to the refresh register, as an example. Table 24-1. Refresh for 8-bit access WDOG_REFRESH[15:8] WDOG_REFRESH[7:0] Sequence value1 or value2 match Mismatch exception Current Value 0xB4 0x80 Value2 match No Write 1 0xB4 0x02 No match No Write 2 0xA6 0x02 Value1 match No Write 3 0xB4 0x02 No match No Write 4 0xB4 0x80 Value2 match. Sequence complete. No Write 5 0x02 0x80 No match Yes As shown in the preceding table, the refresh register holds its reset value initially. Thereafter, two 8-bit accesses are performed on the register to write the first value of the refresh sequence. No mismatch exception is registered on the intermediate write, Write1. The sequence is completed by performing two more 8-bit accesses, writing in the second value of the sequence for a successful refresh. It must be noted that the match of value2 takes place only when the complete 16-bit value is correctly written, write4. Hence, the requirement of writing value2 of the sequence within 20 bus clock cycles of value1 is checked by measuring the gap between write2 and write4. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 508 Freescale Semiconductor, Inc. Chapter 24 Watchdog Timer (WDOG) It is reiterated that the condition for matching values 1 and 2 of the refresh or unlock sequence remains unchanged. The difference for 8-bit accesses is that the criterion for detecting a mismatch is less strict. Any 16-bit access still needs to adhere to the original guidelines, mentioned in the sections Refreshing the Watchdog. 24.9 Restrictions on watchdog operation This section mentions some exceptions to the watchdog operation that may not be apparent to you. * Restriction on unlock/refresh operations--In the period between the closure of the WCT window after unlock and the actual reload of the watchdog timer, unlock and refresh operations need not be attempted. * The update and reload of the watchdog timer happens two to three watchdog clocks after WCT window closes, following a successful configuration on unlock. * Clock Switching Delay--The watchdog uses glitch-free multiplexers at two places - one to choose between the LPO oscillator input and alternate clock input, and the other to choose between the watchdog functional clock and fast clock input for watchdog functional test. A maximum time period of ~2 clock A cycles plus ~2 clock B cycles elapses from the time a switch is requested to the occurrence of the actual clock switch, where clock A and B are the two input clocks to the clock mux. * For the windowed mode, there is a two to three bus clock latency between the watchdog counter going past the window value and the same registering in the bus clock domain. * For proper operation of the watchdog, the watchdog clock must be at least five times slower than the system bus clock at all times. An exception is when the watchdog clock is synchronous to the bus clock wherein the watchdog clock can be as fast as the bus clock. * WCT must be equivalent to at least three watchdog clock cycles. If not ensured, this means that even after the close of the WCT window, you have to wait for the synchronized system reset to deassert in the watchdog clock domain, before expecting the configuration updates to take effect. * The time-out value of the watchdog should be set to a minimum of four watchdog clock cycles. This is to take into account the delay in new settings taking effect in the watchdog clock domain. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 509 Restrictions on watchdog operation * You must take care not only to refresh the watchdog within the watchdog timer's actual time-out period, but also provide enough allowance for the time it takes for the refresh sequence to be detected by the watchdog timer, on the watchdog clock. * Updates cannot be made in the bus clock cycle immediately following the write of the unlock sequence, but one bus clock cycle later. * It should be ensured that the time-out value for the watchdog is always greater than 2xWCT time + 20 bus clock cycles. * An attempted refresh operation, in between the two writes of the unlock sequence and in the WCT time following a successful unlock, will go undetected. * Trying to unlock the watchdog within the WCT time after an initial unlock has no effect. * The refresh and unlock operations and interrupt are not automatically disabled in the watchdog functional test mode. * After emerging from a reset due to a watchdog functional test, you are still expected to go through the mandatory steps of unlocking and configuring the watchdog. The watchdog continues to be in its functional test mode and therefore you should pull the watchdog out of the functional test mode within WCT time of reset. * After emerging from a reset due to a watchdog functional test, you still need to go through the mandatory steps of unlocking and configuring the watchdog. * You must ensure that both the clock inputs to the glitchless clock multiplexers are alive during the switching of clocks. Failure to do so results in a loss of clock at their outputs. * There is a gap of two to three watchdog clock cycles from the point that stop mode is entered to the watchdog timer actually pausing, due to synchronization. The same holds true for an exit from the stop mode, this time resulting in a two to three watchdog clock cycle delay in the timer restarting. In case the duration of the stop mode is less than one watchdog clock cycle, the watchdog timer is not guaranteed to pause. * Consider the case when the first refresh value is written, following which the system enters stop mode with system bus clk still on. If the second refresh value is not written within 20 bus cycles of the first value, the system is reset, or interrupt-thenreset if enabled. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 510 Freescale Semiconductor, Inc. Chapter 25 Multipurpose Clock Generator (MCG) 25.1 Introduction NOTE For the chip-specific implementation details of this module's instances, see the chip configuration information. The multipurpose clock generator (MCG) module provides several clock source choices for the MCU. The module contains a frequency-locked loop (FLL) and a phase-locked loop (PLL). The FLL is controllable by either an internal or an external reference clock. The PLL is controllable by the external reference clock. The module can select either an FLL or PLL output clock, or a reference clock (internal or external) as a source for the MCU system clock. The MCG operates in conjuction with a crystal oscillator, which allows an external crystal, ceramic resonator, or another external clock source to produce the external reference clock. 25.1.1 Features Key features of the MCG module are: * Frequency-locked loop (FLL): * Digitally-controlled oscillator (DCO) * DCO frequency range is programmable for up to four different frequency ranges. * Option to program and maximize DCO output frequency for a low frequency external reference clock source. * Option to prevent FLL from resetting its current locked frequency when switching clock modes if FLL reference frequency is not changed. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 511 Introduction * Internal or external reference clock can be used as the FLL source. * Can be used as a clock source for other on-chip peripherals. * Phase-locked loop (PLL): * Voltage-controlled oscillator (VCO) * External reference clock is used as the PLL source. * Modulo VCO frequency divider * Phase/Frequency detector * Integrated loop filter * Can be used as a clock source for other on-chip peripherals. * Internal reference clock generator: * Slow clock with nine trim bits for accuracy * Fast clock with four trim bits * Can be used as source clock for the FLL. In FEI mode, only the slow Internal Reference Clock (IRC) can be used as the FLL source. * Either the slow or the fast clock can be selected as the clock source for the MCU. * Can be used as a clock source for other on-chip peripherals. * Control signals for the MCG external reference low power oscillator clock generators are provided: * HGO, RANGE, EREFS * External clock from the Crystal Oscillator : * Can be used as a source for the FLL and/or the PLL. * Can be selected as the clock source for the MCU. * External clock from the Real Time Counter (RTC): * Can be used as a source for the FLL only. * Can be selected as the clock source for the MCU. * External clock monitor with reset and interrupt request capability to check for external clock failure when running in FBE, PEE, BLPE, or FEE modes * Lock detector with interrupt request capability for use with the PLL KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 512 Freescale Semiconductor, Inc. Chapter 25 Multipurpose Clock Generator (MCG) * Internal Reference Clocks Auto Trim Machine (ATM) capability using an external clock as a reference * Reference dividers for both the FLL and the PLL are provided * Reference dividers for the Fast Internal Reference Clock are provided * MCG PLL Clock (MCGPLLCLK) is provided as a clock source for other on-chip peripherals * MCG FLL Clock (MCGFLLCLK) is provided as a clock source for other on-chip peripherals * MCG Fixed Frequency Clock (MCGFFCLK) is provided as a clock source for other on-chip peripherals * MCG Internal Reference Clock (MCGIRCLK) is provided as a clock source for other on-chip peripherals This figure presents the block diagram of the MCG module. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 513 Introduction Oscillator (OSC0) Oscillator (OSC2) Oscillator (OSC1) CLKS OSCINIT EREFS OSCSEL HGO PLLCLKEN MCG Crystal Oscillator Enable Detect IREFS OSCSELCLK RANGE PLLS ATMF SCTRIM Internal Reference SCFTRIM LOCRE1 MCGIRCLK IRCLKEN n /2 n=0-7 n /2 DRS IREFS DMX32 Filter PLL DCO FLTPRSRV 5 DCOOUT MCGFLLCLK FLL MCGFFCLK /2 Sync LP PLLCLKEN PRDIV MCGOUTCLK PLLS LOCS1 RANGE /(1,2,3...25) IRCSCLK LOCS0 FRDIV Peripheral BUSCLK CLKS IRCS /2 n=0-7 External Clock Monitor LOCRE0 ATMS Slow Clock Fast Clock Clock Generator FCTRIM CME0 CME1 Auto Trim Machine STOP IREFSTEN Phase Detector Charge Pump VDIV Internal Filter LOLIE Clock Valid Lock Detector VCO MCGPLLCLK VCOOUT LOLS LOCK /(24,25,26....55) Multipurpose Clock Generator (MCG) Figure 25-1. Multipurpose Clock Generator (MCG) block diagram NOTE Refer to the chip configuration chapter to identify the oscillator used in this MCU. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 514 Freescale Semiconductor, Inc. Chapter 25 Multipurpose Clock Generator (MCG) 25.1.2 Modes of Operation The MCG has the following modes of operation: FEI, FEE, FBI, FBE, PBE, PEE, BLPI, BLPE, and Stop. For details, see MCG modes of operation. 25.2 External Signal Description There are no MCG signals that connect off chip. 25.3 Memory Map/Register Definition This section includes the memory map and register definition. The MCG registers can only be written when in supervisor mode. Write accesses when in user mode will result in a bus error. Read accesses may be performed in both supervisor and user mode. MCG memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4006_4000 MCG Control 1 Register (MCG_C1) 8 R/W 04h 25.3.1/516 4006_4001 MCG Control 2 Register (MCG_C2) 8 R/W See section 25.3.2/517 4006_4002 MCG Control 3 Register (MCG_C3) 8 R/W Undefined 25.3.3/518 4006_4003 MCG Control 4 Register (MCG_C4) 8 R/W See section 25.3.4/519 4006_4004 MCG Control 5 Register (MCG_C5) 8 R/W 00h 25.3.5/520 4006_4005 MCG Control 6 Register (MCG_C6) 8 R/W 00h 25.3.6/521 4006_4006 MCG Status Register (MCG_S) 8 R 10h 25.3.7/523 4006_4008 MCG Status and Control Register (MCG_SC) 8 R/W 02h 25.3.8/524 4006_400A MCG Auto Trim Compare Value High Register (MCG_ATCVH) 8 R/W 00h 25.3.9/526 4006_400B MCG Auto Trim Compare Value Low Register (MCG_ATCVL) 8 R/W 00h 25.3.10/ 526 4006_400C MCG Control 7 Register (MCG_C7) 8 R/W 00h 25.3.11/ 526 4006_400D MCG Control 8 Register (MCG_C8) 8 R/W 80h 25.3.12/ 527 4006_4011 MCG Control 12 Register (MCG_C12) 8 R/W 00h 25.3.13/ 528 Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 515 Memory Map/Register Definition MCG memory map (continued) Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 4006_4012 MCG Status 2 Register (MCG_S2) 8 R/W 00h 25.3.13/ 528 4006_4013 MCG Test 3 Register (MCG_T3) 8 R/W 00h 25.3.13/ 529 2 1 0 IREFS IRCLKEN IREFSTEN 1 0 0 25.3.1 MCG Control 1 Register (MCG_C1) Address: 4006_4000h base + 0h offset = 4006_4000h Bit Read Write Reset 7 6 5 CLKS 0 4 3 FRDIV 0 0 0 0 MCG_C1 field descriptions Field 7-6 CLKS Description Clock Source Select Selects the clock source for MCGOUTCLK . 00 01 10 11 5-3 FRDIV FLL External Reference Divider Selects the amount to divide down the external reference clock for the FLL. The resulting frequency must be in the range 31.25 kHz to 39.0625 kHz (This is required when FLL/DCO is the clock source for MCGOUTCLK . In FBE mode, it is not required to meet this range, but it is recommended in the cases when trying to enter a FLL mode from FBE). 000 001 010 011 100 101 110 111 2 IREFS Encoding 0 -- Output of FLL or PLL is selected (depends on PLLS control bit). Encoding 1 -- Internal reference clock is selected. Encoding 2 -- External reference clock is selected. Encoding 3 -- Reserved. If RANGE = 0 or OSCSEL=1 , Divide Factor is 1; for all other RANGE values, Divide Factor is 32. If RANGE = 0 or OSCSEL=1 , Divide Factor is 2; for all other RANGE values, Divide Factor is 64. If RANGE = 0 or OSCSEL=1 , Divide Factor is 4; for all other RANGE values, Divide Factor is 128. If RANGE = 0 or OSCSEL=1 , Divide Factor is 8; for all other RANGE values, Divide Factor is 256. If RANGE = 0 or OSCSEL=1 , Divide Factor is 16; for all other RANGE values, Divide Factor is 512. If RANGE = 0 or OSCSEL=1 , Divide Factor is 32; for all other RANGE values, Divide Factor is 1024. If RANGE = 0 or OSCSEL=1 , Divide Factor is 64; for all other RANGE values, Divide Factor is 1280 . If RANGE = 0 or OSCSEL=1 , Divide Factor is 128; for all other RANGE values, Divide Factor is 1536 . Internal Reference Select Selects the reference clock source for the FLL. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 516 Freescale Semiconductor, Inc. Chapter 25 Multipurpose Clock Generator (MCG) MCG_C1 field descriptions (continued) Field Description 0 1 1 IRCLKEN Internal Reference Clock Enable Enables the internal reference clock for use as MCGIRCLK. 0 1 0 IREFSTEN External reference clock is selected. The slow internal reference clock is selected. MCGIRCLK inactive. MCGIRCLK active. Internal Reference Stop Enable Controls whether or not the internal reference clock remains enabled when the MCG enters Stop mode. 0 1 Internal reference clock is disabled in Stop mode. Internal reference clock is enabled in Stop mode if IRCLKEN is set or if MCG is in FEI, FBI, or BLPI modes before entering Stop mode. 25.3.2 MCG Control 2 Register (MCG_C2) Address: 4006_4000h base + 1h offset = 4006_4001h Bit Read Write Reset 7 6 LOCRE0 FCFTRIM 1 x* 5 4 RANGE 0 0 3 2 1 0 HGO EREFS LP IRCS 0 0 0 0 * Notes: * x = Undefined at reset. MCG_C2 field descriptions Field 7 LOCRE0 Description Loss of Clock Reset Enable Determines whether an interrupt or a reset request is made following a loss of OSC0 external reference clock. The LOCRE0 only has an affect when CME0 is set. 0 1 6 FCFTRIM Interrupt request is generated on a loss of OSC0 external reference clock. Generate a reset request on a loss of OSC0 external reference clock. Fast Internal Reference Clock Fine Trim FCFTRIM1 controls the smallest adjustment of the fast internal reference clock frequency. Setting FCFTRIM increases the period and clearing FCFTRIM decreases the period by the smallest amount possible. If an FCFTRIM value stored in nonvolatile memory is to be used, it is your responsibility to copy that value from the nonvolatile memory location to this bit. 5-4 RANGE Frequency Range Select Selects the frequency range for the crystal oscillator or external clock source. See the Oscillator (OSC) chapter for more details and the device data sheet for the frequency ranges used. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 517 Memory Map/Register Definition MCG_C2 field descriptions (continued) Field Description 00 01 1X 3 HGO High Gain Oscillator Select Controls the crystal oscillator mode of operation. See the Oscillator (OSC) chapter for more details. 0 1 2 EREFS Configure crystal oscillator for low-power operation. Configure crystal oscillator for high-gain operation. External Reference Select Selects the source for the external reference clock. See the Oscillator (OSC) chapter for more details. 0 1 1 LP Encoding 0 -- Low frequency range selected for the crystal oscillator . Encoding 1 -- High frequency range selected for the crystal oscillator . Encoding 2 -- Very high frequency range selected for the crystal oscillator . External reference clock requested. Oscillator requested. Low Power Select Controls whether the FLL or PLL is disabled in BLPI and BLPE modes. In FBE or PBE modes, setting this bit to 1 will transition the MCG into BLPE mode; in FBI mode, setting this bit to 1 will transition the MCG into BLPI mode. In any other MCG mode, LP bit has no affect. 0 1 0 IRCS FLL or PLL is not disabled in bypass modes. FLL or PLL is disabled in bypass modes (lower power) Internal Reference Clock Select Selects between the fast or slow internal reference clock source. 0 1 Slow internal reference clock selected. Fast internal reference clock selected. 1. A value for FCFTRIM is loaded during reset from a factory programmed location. 25.3.3 MCG Control 3 Register (MCG_C3) Address: 4006_4000h base + 2h offset = 4006_4002h Bit Read Write Reset 7 6 5 4 3 2 1 0 x* x* x* x* SCTRIM x* x* x* x* * Notes: * x = Undefined at reset. MCG_C3 field descriptions Field SCTRIM Description Slow Internal Reference Clock Trim Setting SCTRIM 1 controls the slow internal reference clock frequency by controlling the slow internal reference clock period. The SCTRIM bits are binary weighted, that is, bit 1 adjusts twice as much as bit 0. Increasing the binary value increases the period, and decreasing the value decreases the period. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 518 Freescale Semiconductor, Inc. Chapter 25 Multipurpose Clock Generator (MCG) MCG_C3 field descriptions (continued) Field Description An additional fine trim bit is available in C4 register as the SCFTRIM bit. Upon reset, this value is loaded with a factory trim value. If an SCTRIM value stored in nonvolatile memory is to be used, it is your responsibility to copy that value from the nonvolatile memory location to this register. 1. A value for SCTRIM is loaded during reset from a factory programmed location. 25.3.4 MCG Control 4 Register (MCG_C4) Address: 4006_4000h base + 3h offset = 4006_4003h Bit Read Write Reset 7 6 DMX32 5 4 3 DRST_DRS 0 0 2 1 FCTRIM 0 x* x* 0 SCFTRIM x* x* x* * Notes: * x = Undefined at reset. MCG_C4 field descriptions Field 7 DMX32 Description DCO Maximum Frequency with 32.768 kHz Reference The DMX32 bit controls whether the DCO frequency range is narrowed to its maximum frequency with a 32.768 kHz reference. The following table identifies settings for the DCO frequency range. NOTE: The system clocks derived from this source should not exceed their specified maximums. DRST_DRS DMX32 Reference Range FLL Factor DCO Range 00 0 31.25-39.0625 kHz 640 20-25 MHz 1 32.768 kHz 732 24 MHz 0 31.25-39.0625 kHz 1280 40-50 MHz 1 32.768 kHz 1464 48 MHz 0 31.25-39.0625 kHz 1920 60-75 MHz 1 32.768 kHz 2197 72 MHz 0 31.25-39.0625 kHz 2560 80-100 MHz 1 32.768 kHz 2929 96 MHz 01 10 11 0 1 6-5 DRST_DRS DCO has a default range of 25%. DCO is fine-tuned for maximum frequency with 32.768 kHz reference. DCO Range Select The DRS bits select the frequency range for the FLL output, DCOOUT. When the LP bit is set, writes to the DRS bits are ignored. The DRST read field indicates the current frequency range for DCOOUT. The Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 519 Memory Map/Register Definition MCG_C4 field descriptions (continued) Field Description DRST field does not update immediately after a write to the DRS field due to internal synchronization between clock domains. See the DCO Frequency Range table for more details. 00 01 10 11 4-1 FCTRIM Encoding 0 -- Low range (reset default). Encoding 1 -- Mid range. Encoding 2 -- Mid-high range. Encoding 3 -- High range. Fast Internal Reference Clock Trim Setting FCTRIM 1 controls the fast internal reference clock frequency by controlling the fast internal reference clock period. The FCTRIM bits are binary weighted, that is, bit 1 adjusts twice as much as bit 0. Increasing the binary value increases the period, and decreasing the value decreases the period. If an FCTRIM[3:0] value stored in nonvolatile memory is to be used, it is your responsibility to copy that value from the nonvolatile memory location to this register. 0 SCFTRIM Slow Internal Reference Clock Fine Trim SCFTRIM 2 controls the smallest adjustment of the slow internal reference clock frequency. Setting SCFTRIM increases the period and clearing SCFTRIM decreases the period by the smallest amount possible. If an SCFTRIM value stored in nonvolatile memory is to be used, it is your responsibility to copy that value from the nonvolatile memory location to this bit. 1. A value for FCTRIM is loaded during reset from a factory programmed location. 2. A value for SCFTRIM is loaded during reset from a factory programmed location. 25.3.5 MCG Control 5 Register (MCG_C5) Address: 4006_4000h base + 4h offset = 4006_4004h Bit 7 Read Write Reset 0 0 6 5 4 3 PLLCLKEN0 PLLSTEN0 0 0 2 1 0 0 0 PRDIV0 0 0 0 MCG_C5 field descriptions Field 7 Reserved 6 PLLCLKEN0 Description This field is reserved. This read-only field is reserved and always has the value 0. PLL Clock Enable Enables the PLL independent of PLLS and enables the PLL clock for use as MCGPLLCLK. (PRDIV 0 needs to be programmed to the correct divider to generate a PLL reference clock in the range of 2 - 4 MHz range prior to setting the PLLCLKEN 0 bit). Setting PLLCLKEN 0 will enable the external oscillator if not already enabled. Whenever the PLL is being enabled by means of the PLLCLKEN 0 bit, and the external oscillator is being used as the reference clock, the OSCINIT 0 bit should be checked to make sure it is set. 0 1 MCGPLLCLK is inactive. MCGPLLCLK is active. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 520 Freescale Semiconductor, Inc. Chapter 25 Multipurpose Clock Generator (MCG) MCG_C5 field descriptions (continued) Field 5 PLLSTEN0 Description PLL Stop Enable Enables the PLL Clock during Normal Stop. In Low Power Stop mode, the PLL clock gets disabled even if PLLSTEN 0 =1. All other power modes, PLLSTEN 0 bit has no affect and does not enable the PLL Clock to run if it is written to 1. 0 1 PRDIV0 MCGPLLCLK is disabled in any of the Stop modes. MCGPLLCLK is enabled if system is in Normal Stop mode. PLL External Reference Divider Selects the amount to divide down the external reference clock for the PLL. The resulting frequency must be in the range of 2 MHz to 4 MHz. After the PLL is enabled (by setting either PLLCLKEN 0 or PLLS), the PRDIV 0 value must not be changed when LOCK0 is zero. Table 25-1. PLL External Reference Divide Factor PRDIV 0 Divide Factor PRDIV 0 Divide Factor PRDIV 0 Divide Factor PRDIV 0 Divide Factor 00000 1 01000 9 10000 17 11000 25 00001 2 01001 10 10001 18 11001 Reserve d 00010 3 01010 11 10010 19 11010 Reserve d 00011 4 01011 12 10011 20 11011 Reserve d 00100 5 01100 13 10100 21 11100 Reserve d 00101 6 01101 14 10101 22 11101 Reserve d 00110 7 01110 15 10110 23 11110 Reserve d 00111 8 01111 16 10111 24 11111 Reserve d 25.3.6 MCG Control 6 Register (MCG_C6) Address: 4006_4000h base + 5h offset = 4006_4005h Bit Read Write Reset 7 6 5 LOLIE0 PLLS CME0 0 0 0 4 3 2 1 0 0 0 VDIV0 0 0 0 KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 521 Memory Map/Register Definition MCG_C6 field descriptions Field 7 LOLIE0 Description Loss of Lock Interrrupt Enable Determines if an interrupt request is made following a loss of lock indication. This bit only has an effect when LOLS 0 is set. 0 1 6 PLLS PLL Select Controls whether the PLL or FLL output is selected as the MCG source when CLKS[1:0]=00. If the PLLS bit is cleared and PLLCLKEN 0 is not set, the PLL is disabled in all modes. If the PLLS is set, the FLL is disabled in all modes. 0 1 5 CME0 FLL is selected. PLL is selected (PRDIV 0 need to be programmed to the correct divider to generate a PLL reference clock in the range of 2-4 MHz prior to setting the PLLS bit). Clock Monitor Enable Enables the loss of clock monitoring circuit for the OSC0 external reference mux select. The LOCRE0 bit will determine if a interrupt or a reset request is generated following a loss of OSC0 indication. The CME0 bit must only be set to a logic 1 when the MCG is in an operational mode that uses the external clock (FEE, FBE, PEE, PBE, or BLPE) . Whenever the CME0 bit is set to a logic 1, the value of the RANGE0 bits in the C2 register should not be changed. CME0 bit should be set to a logic 0 before the MCG enters any Stop mode. Otherwise, a reset request may occur while in Stop mode. CME0 should also be set to a logic 0 before entering VLPR or VLPW power modes if the MCG is in BLPE mode. 0 1 VDIV0 No interrupt request is generated on loss of lock. Generate an interrupt request on loss of lock. External clock monitor is disabled for OSC0. External clock monitor is enabled for OSC0. VCO 0 Divider Selects the amount to divide the VCO output of the PLL. The VDIV 0 bits establish the multiplication factor (M) applied to the reference clock frequency. After the PLL is enabled (by setting either PLLCLKEN 0 or PLLS), the VDIV 0 value must not be changed when LOCK 0 is zero. Table 25-2. PLL VCO Divide Factor VDIV 0 Multiply Factor VDIV 0 Multiply Factor VDIV 0 Multiply Factor VDIV 0 Multiply Factor 00000 24 01000 32 10000 40 11000 48 00001 25 01001 33 10001 41 11001 49 00010 26 01010 34 10010 42 11010 50 00011 27 01011 35 10011 43 11011 51 00100 28 01100 36 10100 44 11100 52 00101 29 01101 37 10101 45 11101 53 00110 30 01110 38 10110 46 11110 54 00111 31 01111 39 10111 47 11111 55 KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 522 Freescale Semiconductor, Inc. Chapter 25 Multipurpose Clock Generator (MCG) 25.3.7 MCG Status Register (MCG_S) Address: 4006_4000h base + 6h offset = 4006_4006h Bit Read 7 6 5 4 LOLS0 LOCK0 PLLST IREFST 3 0 0 0 1 2 CLKST 1 0 OSCINIT0 IRCST 0 0 Write Reset 0 0 MCG_S field descriptions Field 7 LOLS0 Description Loss of Lock Status This bit is a sticky bit indicating the lock status for the PLL. LOLS is set if after acquiring lock, the PLL output frequency has fallen outside the lock exit frequency tolerance, D unl . LOLIE determines whether an interrupt request is made when LOLS is set. LOLRE determines whether a reset request is made when LOLS is set. This bit is cleared by reset or by writing a logic 1 to it when set. Writing a logic 0 to this bit has no effect. 0 1 6 LOCK0 Lock Status This bit indicates whether the PLL has acquired lock. Lock detection is only enabled when the PLL is enabled (either through clock mode selection or PLLCLKEN0=1 setting). While the PLL clock is locking to the desired frequency, the MCG PLL clock (MCGPLLCLK) will be gated off until the LOCK bit gets asserted. If the lock status bit is set, changing the value of the PRDIV0 [4:0] bits in the C5 register or the VDIV0[4:0] bits in the C6 register causes the lock status bit to clear and stay cleared until the PLL has reacquired lock. Loss of PLL reference clock will also cause the LOCK0 bit to clear until the PLL has reacquired lock. Entry into LLS, VLPS, or regular Stop with PLLSTEN=0 also causes the lock status bit to clear and stay cleared until the Stop mode is exited and the PLL has reacquired lock. Any time the PLL is enabled and the LOCK0 bit is cleared, the MCGPLLCLK will be gated off until the LOCK0 bit is asserted again. 0 1 5 PLLST PLL is currently unlocked. PLL is currently locked. PLL Select Status This bit indicates the clock source selected by PLLS . The PLLST bit does not update immediately after a write to the PLLS bit due to internal synchronization between clock domains. 0 1 4 IREFST PLL has not lost lock since LOLS 0 was last cleared. PLL has lost lock since LOLS 0 was last cleared. Source of PLLS clock is FLL clock. Source of PLLS clock is PLL output clock. Internal Reference Status This bit indicates the current source for the FLL reference clock. The IREFST bit does not update immediately after a write to the IREFS bit due to internal synchronization between clock domains. 0 1 Source of FLL reference clock is the external reference clock. Source of FLL reference clock is the internal reference clock. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 523 Memory Map/Register Definition MCG_S field descriptions (continued) Field 3-2 CLKST Description Clock Mode Status These bits indicate the current clock mode. The CLKST bits do not update immediately after a write to the CLKS bits due to internal synchronization between clock domains. 00 01 10 11 1 OSCINIT0 0 IRCST Encoding 0 -- Output of the FLL is selected (reset default). Encoding 1 -- Internal reference clock is selected. Encoding 2 -- External reference clock is selected. Encoding 3 -- Output of the PLL is selected. OSC Initialization This bit, which resets to 0, is set to 1 after the initialization cycles of the crystal oscillator clock have completed. After being set, the bit is cleared to 0 if the OSC is subsequently disabled. See the OSC module's detailed description for more information. Internal Reference Clock Status The IRCST bit indicates the current source for the internal reference clock select clock (IRCSCLK). The IRCST bit does not update immediately after a write to the IRCS bit due to internal synchronization between clock domains. The IRCST bit will only be updated if the internal reference clock is enabled, either by the MCG being in a mode that uses the IRC or by setting the C1[IRCLKEN] bit . 0 1 Source of internal reference clock is the slow clock (32 kHz IRC). Source of internal reference clock is the fast clock (4 MHz IRC). 25.3.8 MCG Status and Control Register (MCG_SC) Address: 4006_4000h base + 8h offset = 4006_4008h Bit Read Write Reset 7 6 ATME ATMS 0 0 5 ATMF w1c 0 4 3 FLTPRSRV 0 2 1 FCRDIV 0 0 0 LOCS0 w1c 1 0 MCG_SC field descriptions Field 7 ATME Description Automatic Trim Machine Enable Enables the Auto Trim Machine to start automatically trimming the selected Internal Reference Clock. NOTE: ATME deasserts after the Auto Trim Machine has completed trimming all trim bits of the IRCS clock selected by the ATMS bit. Writing to C1, C3, C4, and SC registers or entering Stop mode aborts the auto trim operation and clears this bit. 0 1 Auto Trim Machine disabled. Auto Trim Machine enabled. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 524 Freescale Semiconductor, Inc. Chapter 25 Multipurpose Clock Generator (MCG) MCG_SC field descriptions (continued) Field 6 ATMS Description Automatic Trim Machine Select Selects the IRCS clock for Auto Trim Test. 0 1 5 ATMF Automatic Trim Machine Fail Flag Fail flag for the Automatic Trim Machine (ATM). This bit asserts when the Automatic Trim Machine is enabled, ATME=1, and a write to the C1, C3, C4, and SC registers is detected or the MCG enters into any Stop mode. A write to ATMF clears the flag. 0 1 4 FLTPRSRV This bit will prevent the FLL filter values from resetting allowing the FLL output frequency to remain the same during clock mode changes where the FLL/DCO output is still valid. (Note: This requires that the FLL reference frequency to remain the same as what it was prior to the new clock mode switch. Otherwise FLL filter and frequency values will change.) FLL filter and FLL frequency will reset on changes to currect clock mode. Fll filter and FLL frequency retain their previous values during new clock mode change. Fast Clock Internal Reference Divider Selects the amount to divide down the fast internal reference clock. The resulting frequency will be in the range 31.25 kHz to 4 MHz (Note: Changing the divider when the Fast IRC is enabled is not supported). 000 001 010 011 100 101 110 111 0 LOCS0 Automatic Trim Machine completed normally. Automatic Trim Machine failed. FLL Filter Preserve Enable 0 1 3-1 FCRDIV 32 kHz Internal Reference Clock selected. 4 MHz Internal Reference Clock selected. Divide Factor is 1 Divide Factor is 2. Divide Factor is 4. Divide Factor is 8. Divide Factor is 16 Divide Factor is 32 Divide Factor is 64 Divide Factor is 128. OSC0 Loss of Clock Status The LOCS0 indicates when a loss of OSC0 reference clock has occurred. The LOCS0 bit only has an effect when CME0 is set. This bit is cleared by writing a logic 1 to it when set. 0 1 Loss of OSC0 has not occurred. Loss of OSC0 has occurred. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 525 Memory Map/Register Definition 25.3.9 MCG Auto Trim Compare Value High Register (MCG_ATCVH) Address: 4006_4000h base + Ah offset = 4006_400Ah Bit Read Write Reset 7 6 5 4 3 2 1 0 0 0 0 0 ATCVH 0 0 0 0 MCG_ATCVH field descriptions Field ATCVH Description ATM Compare Value High Values are used by Auto Trim Machine to compare and adjust Internal Reference trim values during ATM SAR conversion. 25.3.10 MCG Auto Trim Compare Value Low Register (MCG_ATCVL) Address: 4006_4000h base + Bh offset = 4006_400Bh Bit Read Write Reset 7 6 5 4 3 2 1 0 0 0 0 0 ATCVL 0 0 0 0 MCG_ATCVL field descriptions Field ATCVL Description ATM Compare Value Low Values are used by Auto Trim Machine to compare and adjust Internal Reference trim values during ATM SAR conversion. 25.3.11 MCG Control 7 Register (MCG_C7) Address: 4006_4000h base + Ch offset = 4006_400Ch Bit Read Write Reset 7 6 5 4 0 0 3 2 1 0 0 0 0 0 OSCSEL 0 0 0 0 KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 526 Freescale Semiconductor, Inc. Chapter 25 Multipurpose Clock Generator (MCG) MCG_C7 field descriptions Field Description 7-6 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 5-2 Reserved Reserved OSCSEL MCG OSC Clock Select This field is reserved. This read-only field is reserved and always has the value 0. Selects the MCG FLL external reference clock NOTE: The OSCSEL field can't be changed during MCG modes (like PBE), when external clock is serving as the clock source for MCG. 00 01 10 11 Selects Oscillator (OSCCLK0). Selects 32 kHz RTC Oscillator. Selects Oscillator (OSCCLK1). RESERVED 25.3.12 MCG Control 8 Register (MCG_C8) Address: 4006_4000h base + Dh offset = 4006_400Dh Bit Read Write Reset 7 6 5 LOCRE1 LOLRE CME1 1 0 0 4 3 2 1 0 0 LOCS1 w1c 0 0 0 0 0 MCG_C8 field descriptions Field 7 LOCRE1 Description Loss of Clock Reset Enable Determines if a interrupt or a reset request is made following a loss of RTC external reference clock. The LOCRE1 only has an affect when CME1 is set. 0 1 6 LOLRE PLL Loss of Lock Reset Enable Determines if an interrupt or a reset request is made following a PLL loss of lock. 0 1 5 CME1 Interrupt request is generated on a loss of RTC external reference clock. Generate a reset request on a loss of RTC external reference clock Interrupt request is generated on a PLL loss of lock indication. The PLL loss of lock interrupt enable bit must also be set to generate the interrupt request. Generate a reset request on a PLL loss of lock indication. Clock Monitor Enable1 Enables the loss of clock monitoring circuit for the output of the RTC external reference clock. The LOCRE1 bit will determine whether an interrupt or a reset request is generated following a loss of RTC Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 527 Memory Map/Register Definition MCG_C8 field descriptions (continued) Field Description clock indication. The CME1 bit should be set to a logic 1 when the MCG is in an operational mode that uses the RTC as its external reference clock or if the RTC is operational. CME1 bit must be set to a logic 0 before the MCG enters any Stop mode. Otherwise, a reset request may occur when in Stop mode. CME1 should also be set to a logic 0 before entering VLPR or VLPW power modes. 0 1 4-1 Reserved 0 LOCS1 External clock monitor is disabled for RTC clock. External clock monitor is enabled for RTC clock. This field is reserved. This read-only field is reserved and always has the value 0. RTC Loss of Clock Status This bit indicates when a loss of clock has occurred. This bit is cleared by writing a logic 1 to it when set. 0 1 Loss of RTC has not occur. Loss of RTC has occur 25.3.13 MCG Control 12 Register (MCG_C12) Address: 4006_4000h base + 11h offset = 4006_4011h Bit Read Write Reset 7 6 5 4 3 2 1 0 0 0 0 0 3 2 1 0 0 0 0 0 0 0 0 0 0 MCG_C12 field descriptions Field Reserved Description This field is reserved. This read-only field is reserved and always has the value 0. 25.3.13 MCG Status 2 Register (MCG_S2) Address: 4006_4000h base + 12h offset = 4006_4012h Bit Read Write Reset 7 6 5 4 0 0 0 0 0 MCG_S2 field descriptions Field Reserved Description This field is reserved. This read-only field is reserved and always has the value 0. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 528 Freescale Semiconductor, Inc. Chapter 25 Multipurpose Clock Generator (MCG) 25.3.13 MCG Test 3 Register (MCG_T3) Address: 4006_4000h base + 13h offset = 4006_4013h Bit Read Write Reset 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 MCG_T3 field descriptions Field Reserved Description This field is reserved. This read-only field is reserved and always has the value 0. 25.4 Functional description 25.4.1 MCG mode state diagram The nine states of the MCG are shown in the following figure and are described in Table 25-3. The arrows indicate the permitted MCG mode transitions. Reset FEI FEE FBI FBE BLPE BLPI PBE PEE Entered from any state when the MCU enters Stop mode Stop Returns to the state that was active before the MCU entered Stop mode, unless a reset occurs while in Stop mode. Figure 25-2. MCG mode state diagram KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 529 Functional description NOTE * During exits from LLS or VLPS when the MCG is in PEE mode, the MCG will reset to PBE clock mode and the C1[CLKS] and S[CLKST] will automatically be set to 2'b10. * If entering Normal Stop mode when the MCG is in PEE mode with PLLSTEN=0, the MCG will reset to PBE clock mode and C1[CLKS] and S[CLKST] will automatically be set to 2'b10. 25.4.1.1 MCG modes of operation The MCG operates in one of the following modes. Note The MCG restricts transitions between modes. For the permitted transitions, see Figure 25-2. Table 25-3. MCG modes of operation Mode Description FLL Engaged Internal (FEI) FLL engaged internal (FEI) is the default mode of operation and is entered when all the following condtions occur: * 00 is written to C1[CLKS]. * 1 is written to C1[IREFS]. * 0 is written to C6[PLLS]. In FEI mode, MCGOUTCLK is derived from the FLL clock (DCOCLK) that is controlled by the 32 kHz Internal Reference Clock (IRC). The FLL loop will lock the DCO frequency to the FLL factor, as selected by C4[DRST_DRS] and C4[DMX32] bits, times the internal reference frequency. See the C4[DMX32] bit description for more details. In FEI mode, the PLL is disabled in a low-power state unless C5[PLLCLKEN] is set . FLL Engaged External (FEE) FLL engaged external (FEE) mode is entered when all the following conditions occur: * 00 is written to C1[CLKS]. * 0 is written to C1[IREFS]. * C1[FRDIV] must be written to divide external reference clock to be within the range of 31.25 kHz to 39.0625 kHz * 0 is written to C6[PLLS]. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 530 Freescale Semiconductor, Inc. Chapter 25 Multipurpose Clock Generator (MCG) Table 25-3. MCG modes of operation (continued) Mode Description In FEE mode, MCGOUTCLK is derived from the FLL clock (DCOCLK) that is controlled by the external reference clock. The FLL loop will lock the DCO frequency to the FLL factor, as selected by C4[DRST_DRS] and C4[DMX32] bits, times the external reference frequency, as specified by C1[FRDIV] and C2[RANGE]. See the C4[DMX32] bit description for more details. In FEE mode, the PLL is disabled in a low-power state unless C5[PLLCLKEN] is set . FLL Bypassed Internal (FBI) FLL bypassed internal (FBI) mode is entered when all the following conditions occur: * 01 is written to C1[CLKS]. * 1 is written to C1[IREFS]. * 0 is written to C6[PLLS] * 0 is written to C2[LP]. In FBI mode, the MCGOUTCLK is derived either from the slow (32 kHz IRC) or fast (4 MHz IRC) internal reference clock, as selected by the C2[IRCS] bit. The FLL is operational but its output is not used. This mode is useful to allow the FLL to acquire its target frequency while the MCGOUTCLK is driven from the C2[IRCS] selected internal reference clock. The FLL clock (DCOCLK) is controlled by the slow internal reference clock, and the DCO clock frequency locks to a multiplication factor, as selected by C4[DRST_DRS] and C4[DMX32] bits, times the internal reference frequency. See the C4[DMX32] bit description for more details. In FBI mode, the PLL is disabled in a low-power state unless C5[PLLCLKEN] is set . FLL Bypassed External FLL bypassed external (FBE) mode is entered when all the following conditions occur: (FBE) * 10 is written to C1[CLKS]. * 0 is written to C1[IREFS]. * C1[FRDIV] must be written to divide external reference clock to be within the range of 31.25 kHz to 39.0625 kHz. * 0 is written to C6[PLLS]. * 0 is written to C2[LP]. In FBE mode, the MCGOUTCLK is derived from the OSCSEL external reference clock. The FLL is operational but its output is not used. This mode is useful to allow the FLL to acquire its target frequency while the MCGOUTCLK is driven from the external reference clock. The FLL clock (DCOCLK) is controlled by the external reference clock, and the DCO clock frequency locks to a multiplication factor, as selected by C4[DRST_DRS] and C4[DMX32] bits, times the divided external reference frequency. See the C4[DMX32] bit description for more details. In FBE mode, the PLL is disabled in a low-power state unless C5[PLLCLKEN] is set . PLL Engaged External (PEE) PLL Engaged External (PEE) mode is entered when all the following conditions occur: * 00 is written to C1[CLKS]. * 0 is written to C1[IREFS]. * 1 is written to C6[PLLS]. In PEE mode, the MCGOUTCLK is derived from the output of PLL which is controlled by a external reference clock. The PLL clock frequency locks to a multiplication factor, as specified by its corresponding VDIV, times the selected PLL reference frequency, as specified by its corresponding PRDIV. The PLL's programmable reference divider must be configured to produce a valid PLL reference clock. The FLL is disabled in a low-power state. PLL Bypassed External PLL Bypassed External (PBE) mode is entered when all the following conditions occur: (PBE) * 10 is written to C1[CLKS]. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 531 Functional description Table 25-3. MCG modes of operation (continued) Mode Description * 0 is written to C1[IREFS]. * 1 is written to C6[PLLS]. * 0 is written to C2[LP]. In PBE mode, MCGOUTCLK is derived from the OSCSEL external reference clock; the PLL is operational, but its output clock is not used. This mode is useful to allow the PLL to acquire its target frequency while MCGOUTCLK is driven from the external reference clock. The PLL clock frequency locks to a multiplication factor, as specified by its [VDIV], times the PLL reference frequency, as specified by its [PRDIV]. In preparation for transition to PEE, the PLL's programmable reference divider must be configured to produce a valid PLL reference clock. The FLL is disabled in a lowpower state. Bypassed Low Power Internal (BLPI) 1 Bypassed Low Power Internal (BLPI) mode is entered when all the following conditions occur: * 01 is written to C1[CLKS]. * 1 is written to C1[IREFS]. * 0 is written to C6[PLLS]. * 1 is written to C2[LP]. In BLPI mode, MCGOUTCLK is derived from the internal reference clock. The FLL is disabled and PLL is disabled even if C5[PLLCLKEN] is set to 1. Bypassed Low Power External (BLPE) 1 Bypassed Low Power External (BLPE) mode is entered when all the following conditions occur: * 10 is written to C1[CLKS]. * 0 is written to C1[IREFS]. * 1 is written to C2[LP]. In BLPE mode, MCGOUTCLK is derived from the OSCSEL external reference clock. The FLL is disabled and PLL is disabled even if the C5[PLLCLKEN] is set to 1. Stop Entered whenever the MCU enters a Stop state. The power modes are chip specific. For power mode assignments, see the chapter that describes how modules are configured and MCG behavior during Stop recovery. Entering Stop mode, the FLL is disabled, and all MCG clock signals are static except in the following case: MCGPLLCLK is active in Normal Stop mode when PLLSTEN=1 MCGIRCLK is active in Normal Stop mode when all the following conditions become true: * C1[IRCLKEN] = 1 * C1[IREFSTEN] = 1 NOTE: * When entering Low Power Stop modes (LLS or VLPS) from PEE mode, on exit the MCG clock mode is forced to PBE clock mode. C1[CLKS] and S[CLKST] will be configured to 2'b10 and S[LOCK] bit will be cleared without setting S[LOLS]. * When entering Normal Stop mode from PEE mode and if C5[PLLSTEN]=0, on exit the MCG clock mode is forced to PBE mode, the C1[CLKS] and S[CLKST] will be configured to 2'b10 and S[LOCK] bit will clear without setting S[LOLS]. If C5[PLLSTEN]=1, the S[LOCK] bit will not get cleared and on exit the MCG will continue to run in PEE mode. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 532 Freescale Semiconductor, Inc. Chapter 25 Multipurpose Clock Generator (MCG) 1. Caution: If entering VLPR mode, MCG has to be configured and enter BLPE mode or BLPI mode with the Fast IRC clock selected (C2[IRCS]=1). After it enters VLPR mode, writes to any of the MCG control registers that can cause an MCG clock mode switch to a non low power clock mode must be avoided. NOTE For the chip-specific modes of operation, see the power management chapter of this MCU. 25.4.1.2 MCG mode switching C1[IREFS] can be changed at any time, but the actual switch to the newly selected reference clocks is shown by S[IREFST]. When switching between engaged internal and engaged external modes, the FLL will begin locking again after the switch is completed. C1[CLKS] can also be changed at any time, but the actual switch to the newly selected clock is shown by S[CLKST]. If the newly selected clock is not available, the previous clock will remain selected. The C4[DRST_DRS] write bits can be changed at any time except when C2[LP] bit is 1. If C4[DRST_DRS] write bits are changed while in FLL engaged internal (FEI) or FLL engaged external (FEE) mode, the MCGOUTCLK switches to the new selected DCO range within three clocks of the selected DCO clock. After switching to the new DCO (indicated by the updated C4[DRST_DRS] read bits), the FLL remains unlocked for several reference cycles. The FLL lock time is provided in the device data sheet as tfll_acquire. 25.4.2 Low-power bit usage C2[LP] is provided to allow the FLL or PLL to be disabled and thus conserve power when these systems are not being used. C4[DRST_DRS] can not be written while C2[LP] is 1. However, in some applications, it may be desirable to enable the FLL or PLL and allow it to lock for maximum accuracy before switching to an engaged mode. Do this by writing 0 to C2[LP]. 25.4.3 MCG Internal Reference Clocks This module supports two internal reference clocks with nominal frequencies of 32 kHz (slow IRC) and 4 MHz (fast IRC). The fast IRC frequency can be divided down by programming of the FCRDIV to produce a frequency range of 32 kHz to 4 MHz. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 533 Functional description 25.4.3.1 MCG Internal Reference Clock The MCG Internal Reference Clock (MCGIRCLK) provides a clock source for other onchip peripherals and is enabled when C1[IRCLKEN]=1. When enabled, MCGIRCLK is driven by either the fast internal reference clock (4 MHz IRC which can be divided down by the FRDIV factors) or the slow internal reference clock (32 kHz IRC). The IRCS clock frequency can be re-targeted by trimming the period of its IRCS selected internal reference clock. This can be done by writing a new trim value to the C3[SCTRIM]:C4[SCFTRIM] bits when the slow IRC clock is selected or by writing a new trim value to C4[FCTRIM]:C2[FCFTRIM] when the fast IRC clock is selected. The internal reference clock period is proportional to the trim value written. C3[SCTRIM]:C4[SCFTRIM] (if C2[IRCS]=0) and C4[FCTRIM]:C2[FCFTRIM] (if C2[IRCS]=1) bits affect the MCGOUTCLK frequency if the MCG is in FBI or BLPI modes. C3[SCTRIM]:C4[SCFTRIM] (if C2[IRCS]=0) bits also affect the MCGOUTCLK frequency if the MCG is in FEI mode. Additionally, this clock can be enabled in Stop mode by setting C1[IRCLKEN] and C1[IREFSTEN], otherwise this clock is disabled in Stop mode. 25.4.4 External Reference Clock The MCG module can support an external reference clock in all modes. See the device datasheet for external reference frequency range. When C1[IREFS] is set, the external reference clock will not be used by the FLL or PLL. In these modes, the frequency can be equal to the maximum frequency the chip-level timing specifications will support. If any of the CME bits are asserted the slow internal reference clock is enabled along with the enabled external clock monitor. For the case when C6[CME0]=1, a loss of clock is detected if the OSC0 external reference falls below a minimum frequency (floc_high or floc_low depending on C2[RANGE0]). For the case when C8[CME1]=1, a loss of clock is detected if the RTC external reference falls below a minimum frequency (floc_low). NOTE All clock monitors must be disabled before entering these lowpower modes: Stop, VLPS, VLPR, VLPW, LLS, and VLLSx. On detecting a loss-of-clock event, the MCU generates a system reset if the respective LOCRE bit is set. Otherwise the MCG sets the respective LOCS bit and the MCG generates a LOCS interrupt request. In the case where a OSC loss of clock is detected, the PLL LOCK status bit is cleared. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 534 Freescale Semiconductor, Inc. Chapter 25 Multipurpose Clock Generator (MCG) 25.4.5 MCG Fixed Frequency Clock The MCG Fixed Frequency Clock (MCGFFCLK) provides a fixed frequency clock source for other on-chip peripherals; see the block diagram. This clock is driven by either the slow clock from the internal reference clock generator or the external reference clock from the Crystal Oscillator, divided by the FLL reference clock divider. The source of MCGFFCLK is selected by C1[IREFS]. This clock is synchronized to the peripheral bus clock and is valid only when its frequency is not more than 1/8 of the MCGOUTCLK frequency. When it is not valid, it is disabled and held high. The MCGFFCLK is not available when the MCG is in BLPI mode. This clock is also disabled in Stop mode. The FLL reference clock must be set within the valid frequency range for the MCGFFCLK. 25.4.6 MCG PLL clock The MCG PLL Clock (MCGPLLCLK) is available depending on the device's configuration of the MCG module. For more details, see the clock distribution chapter of this MCU. The MCGPLLCLK is prevented from coming out of the MCG until it is enabled and S[LOCK0] is set. 25.4.7 MCG Auto TRIM (ATM) The MCG Auto Trim (ATM) is a MCG feature that when enabled, it configures the MCG hardware to automatically trim the MCG Internal Reference Clocks using an external clock as a reference. The selection between which MCG IRC clock gets tested and enabled is controlled by the ATC[ATMS] control bit (ATC[ATMS]=0 selects the 32 kHz IRC and ATC[ATMS]=1 selects the 4 MHz IRC). If 4 MHz IRC is selected for the ATM, a divide by 128 is enabled to divide down the 4 MHz IRC to a range of 31.250 kHz. When MCG ATM is enabled by writing ATC[ATME] bit to 1, The ATM machine will start auto trimming the selected IRC clock. During the autotrim process, ATC[ATME] will remain asserted and will deassert after ATM is completed or an abort occurs. The MCG ATM is aborted if a write to any of the following control registers is detected : C1, C3, C4, or ATC or if Stop mode is entered. If an abort occurs, ATC[ATMF] fail flag is asserted. The ATM machine uses the bus clock as the external reference clock to perform the IRC auto-trim. Therefore, it is required that the MCG is configured in a clock mode where the reference clock used to generate the system clock is the external reference clock such as KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 535 Initialization / Application information FBE clock mode. The MCG must not be configured in a clock mode where selected IRC ATM clock is used to generate the system clock. The bus clock is also required to be running with in the range of 8-16 MHz. To perform the ATM on the selected IRC, the ATM machine uses the successive approximation technique to adjust the IRC trim bits to generate the desired IRC trimmed frequency. The ATM SARs each of the ATM IRC trim bits starting with the MSB. For each trim bit test, the ATM uses a pulse that is generated by the ATM selected IRC clock to enable a counter that counts number of ATM external clocks. At end of each trim bit, the ATM external counter value is compared to the ATCV[15:0] register value. Based on the comparison result, the ATM trim bit under test will get cleared or stay asserted. This is done until all trim bits have been tested by ATM SAR machine. Before the ATM can be enabled, the ATM expected count needs to be derived and stored into the ATCV register. The ATCV expected count is derived based on the required target Internal Reference Clock (IRC) frequency, and the frequency of the external reference clock using the following formula: ATCV * Fr = Target Internal Reference Clock (IRC) Trimmed Frequency * Fe = External Clock Frequency If the auto trim is being performed on the 4 MHz IRC, the calculated expected count value must be multiplied by 128 before storing it in the ATCV register. Therefore, the ATCV Expected Count Value for trimming the 4 MHz IRC is calculated using the following formula. (128) 25.5 Initialization / Application information This section describes how to initialize and configure the MCG module in an application. The following sections include examples on how to initialize the MCG and properly switch between the various available modes. 25.5.1 MCG module initialization sequence The MCG comes out of reset configured for FEI mode. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 536 Freescale Semiconductor, Inc. Chapter 25 Multipurpose Clock Generator (MCG) The internal reference will stabilize in tirefsts microseconds before the FLL can acquire lock. As soon as the internal reference is stable, the FLL will acquire lock in tfll_acquire milliseconds. 25.5.1.1 Initializing the MCG Because the MCG comes out of reset in FEI mode, the only MCG modes that can be directly switched to upon reset are FEE, FBE, and FBI modes (see Figure 25-2). Reaching any of the other modes requires first configuring the MCG for one of these three intermediate modes. Care must be taken to check relevant status bits in the MCG status register reflecting all configuration changes within each mode. To change from FEI mode to FEE or FBE modes, follow this procedure: 1. Enable the external clock source by setting the appropriate bits in C2 register. 2. Write to C1 register to select the clock mode. * If entering FEE mode, set C1[FRDIV] appropriately, clear C1[IREFS] bit to switch to the external reference, and leave C1[CLKS] at 2'b00 so that the output of the FLL is selected as the system clock source. * If entering FBE, clear C1[IREFS] to switch to the external reference and change C1[CLKS] to 2'b10 so that the external reference clock is selected as the system clock source. The C1[FRDIV] bits should also be set appropriately here according to the external reference frequency to keep the FLL reference clock in the range of 31.25 kHz to 39.0625 kHz. Although the FLL is bypassed, it is still on in FBE mode. * The internal reference can optionally be kept running by setting C1[IRCLKEN]. This is useful if the application will switch back and forth between internal and external modes. For minimum power consumption, leave the internal reference disabled while in an external clock mode. 3. Once the proper configuration bits have been set, wait for the affected bits in the MCG status register to be changed appropriately, reflecting that the MCG has moved into the proper mode. * If the MCG is in FEE, FBE, PEE, PBE, or BLPE mode, and C2[EREFS] was also set in step 1, wait here for S[OSCINIT0] bit to become set indicating that the external clock source has finished its initialization cycles and stabilized. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 537 Initialization / Application information * If in FEE mode, check to make sure S[IREFST] is cleared before moving on. * If in FBE mode, check to make sure S[IREFST] is cleared and S[CLKST] bits have changed to 2'b10 indicating the external reference clock has been appropriately selected. Although the FLL is bypassed, it is still on in FBE mode. 4. Write to the C4 register to determine the DCO output (MCGFLLCLK) frequency range. * By default, with C4[DMX32] cleared to 0, the FLL multiplier for the DCO output is 640. For greater flexibility, if a mid-low-range FLL multiplier of 1280 is desired instead, set C4[DRST_DRS] bits to 2'b01 for a DCO output frequency of 40 MHz. If a mid high-range FLL multiplier of 1920 is desired instead, set the C4[DRST_DRS] bits to 2'b10 for a DCO output frequency of 60 MHz. If a highrange FLL multiplier of 2560 is desired instead, set the C4[DRST_DRS] bits to 2'b11 for a DCO output frequency of 80 MHz. * When using a 32.768 kHz external reference, if the maximum low-range DCO frequency that can be achieved with a 32.768 kHz reference is desired, set C4[DRST_DRS] bits to 2'b00 and set C4[DMX32] bit to 1. The resulting DCO output (MCGOUTCLK) frequency with the new multiplier of 732 will be 24 MHz. * When using a 32.768 kHz external reference, if the maximum mid-range DCO frequency that can be achieved with a 32.768 kHz reference is desired, set C4[DRST_DRS] bits to 2'b01 and set C4[DMX32] bit to 1. The resulting DCO output (MCGOUTCLK) frequency with the new multiplier of 1464 will be 48 MHz. * When using a 32.768 kHz external reference, if the maximum mid high-range DCO frequency that can be achieved with a 32.768 kHz reference is desired, set C4[DRST_DRS] bits to 2'b10 and set C4[DMX32] bit to 1. The resulting DCO output (MCGOUTCLK) frequency with the new multiplier of 2197 will be 72 MHz. * When using a 32.768 kHz external reference, if the maximum high-range DCO frequency that can be achieved with a 32.768 kHz reference is desired, set C4[DRST_DRS] bits to 2'b11 and set C4[DMX32] bit to 1. The resulting DCO output (MCGOUTCLK) frequency with the new multiplier of 2929 will be 96 MHz. 5. Wait for the FLL lock time to guarantee FLL is running at new C4[DRST_DRS] and C4[DMX32] programmed frequency. To change from FEI clock mode to FBI clock mode, follow this procedure: KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 538 Freescale Semiconductor, Inc. Chapter 25 Multipurpose Clock Generator (MCG) 1. Change C1[CLKS] bits in C1 register to 2'b01 so that the internal reference clock is selected as the system clock source. 2. Wait for S[CLKST] bits in the MCG status register to change to 2'b01, indicating that the internal reference clock has been appropriately selected. 3. Write to the C2 register to determine the IRCS output (IRCSCLK) frequency range. * By default, with C2[IRCS] cleared to 0, the IRCS selected output clock is the slow internal reference clock (32 kHz IRC). If the faster IRC is desired, set C2[IRCS] to 1 for a IRCS clock derived from the 4 MHz IRC source. 25.5.2 Using a 32.768 kHz reference In FEE and FBE modes, if using a 32.768 kHz external reference, at the default FLL multiplication factor of 640, the DCO output (MCGFLLCLK) frequency is 20.97 MHz at low-range. If C4[DRST_DRS] bits are set to 2'b01, the multiplication factor is doubled to 1280, and the resulting DCO output frequency is 41.94 MHz at mid-low-range. If C4[DRST_DRS] bits are set to 2'b10, the multiplication factor is set to 1920, and the resulting DCO output frequency is 62.91 MHz at mid high-range. If C4[DRST_DRS] bits are set to 2'b11, the multiplication factor is set to 2560, and the resulting DCO output frequency is 83.89 MHz at high-range. In FBI and FEI modes, setting C4[DMX32] bit is not recommended. If the internal reference is trimmed to a frequency above 32.768 kHz, the greater FLL multiplication factor could potentially push the microcontroller system clock out of specification and damage the part. 25.5.3 MCG mode switching When switching between operational modes of the MCG, certain configuration bits must be changed in order to properly move from one mode to another. Each time any of these bits are changed (C6[PLLS], C1[IREFS], C1[CLKS], C2[IRCS], or C2[EREFS], the corresponding bits in the MCG status register (PLLST, IREFST, CLKST, IRCST, or OSCINIT) must be checked before moving on in the application software. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 539 Initialization / Application information Additionally, care must be taken to ensure that the reference clock divider (C1[FRDIV] and C5[PRDIV0]) is set properly for the mode being switched to. For instance, in PEE mode, if using a 4 MHz crystal, C5[PRDIV0] must be set to 5'b000 (divide-by-1) or 5'b001 (divide-by-2) to divide the external reference down to the required frequency between 2 and 4 MHz In FBE, FEE, FBI, and FEI modes, at any time, the application can switch the FLL multiplication factor between 640, 1280, 1920, and 2560 with C4[DRST_DRS] bits. Writes to C4[DRST_DRS] bits will be ignored if C2[LP]=1. The table below shows MCGOUTCLK frequency calculations using C1[FRDIV], C5[PRDIV0], and C6[VDIV0] settings for each clock mode. Table 25-4. MCGOUTCLK Frequency Calculation Options Clock Mode fMCGOUTCLK1 Note FEI (FLL engaged internal) fint x F Typical fMCGOUTCLK = 21 MHz immediately after reset. FEE (FLL engaged external) (fext / FLL_R) x F fext / FLL_R must be in the range of 31.25 kHz to 39.0625 kHz FBE (FLL bypassed external) OSCCLK OSCCLK / FLL_R must be in the range of 31.25 kHz to 39.0625 kHz FBI (FLL bypassed internal) MCGIRCLK Selectable between slow and fast IRC PEE (PLL engaged external) (OSCCLK / PLL_R) x M OSCCLK / PLL_R must be in the range of 2 - 4 MHz PBE (PLL bypassed external) OSCCLK OSCCLK / PLL_R must be in the range of 2 - 4 MHz BLPI (Bypassed low power internal) MCGIRCLK Selectable between slow and fast IRC BLPE (Bypassed low power external) OSCCLK 1. FLL_R is the reference divider selected by the C1[FRDIV] bits, F is the FLL factor selected by C4[DRST_DRS] and C4[DMX32] bits , PLL_R is the reference divider selected by C5[PRDIV0] bits, and M is the multiplier selected by C6[VDIV0] bits. This section will include several mode switching examples, using an 4 MHz external crystal. If using an external clock source less than 2 MHz, the MCG must not be configured for any of the PLL modes (PEE and PBE). KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 540 Freescale Semiconductor, Inc. Chapter 25 Multipurpose Clock Generator (MCG) 25.5.3.1 Example 1: Moving from FEI to PEE mode: External Crystal = 4 MHz, MCGOUTCLK frequency = 48 MHz In this example, the MCG will move through the proper operational modes from FEI to PEE to achieve 48 MHz MCGOUTCLK frequency from 4 MHz external crystal reference. First, the code sequence will be described. Then there is a flowchart that illustrates the sequence. 1. First, FEI must transition to FBE mode: a. C2 = 0x2C * C2[RANGE] set to 2'b01 because the frequency of 4 MHz is within the high frequency range. * C2[HGO] set to 1 to configure the crystal oscillator for high gain operation. * C2[EREFS] set to 1, because a crystal is being used. b. C1 = 0x90 * C1[CLKS] set to 2'b10 to select external reference clock as system clock source * C1[FRDIV] set to 3'b010, or divide-by-128 because 4 MHz / 128 = 31.25 kHz which is in the 31.25 kHz to 39.0625 kHz range required by the FLL * C1[IREFS] cleared to 0, selecting the external reference clock and enabling the external oscillator. c. Loop until S[OSCINIT0] is 1, indicating the crystal selected by C2[EREFS0] has been initialized. d. Loop until S[IREFST] is 0, indicating the external reference is the current source for the reference clock. e. Loop until S[CLKST] is 2'b10, indicating that the external reference clock is selected to feed MCGOUTCLK. 2. Then configure C5[PRDIV0] to generate correct PLL reference frequency. a. C5 = 0x01 * C5[PRDIV] set to 5'b00001, or divide-by-2 resulting in a pll reference frequency of 4MHz/2 = 2 MHz. 3. Then, FBE must transition either directly to PBE mode or first through BLPE mode and then to PBE mode: KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 541 Initialization / Application information a. BLPE: If a transition through BLPE mode is desired, first set C2[LP] to 1. b. BLPE/PBE: C6 = 0x40 * C6[PLLS] set to 1, selects the PLL. At this time, with a C1[PRDIV] value of 2'b001, the PLL reference divider is 2 (see PLL External Reference Divide Factor table), resulting in a reference frequency of 4 MHz/ 2 = 2 MHz. In BLPE mode, changing the C6[PLLS] bit only prepares the MCG for PLL usage in PBE mode. * C6[VDIV] set to 5'b00000, or multiply-by-24 because 2 MHz reference * 24 = 48 MHz. In BLPE mode, the configuration of the VDIV bits does not matter because the PLL is disabled. Changing them only sets up the multiply value for PLL usage in PBE mode. c. BLPE: If transitioning through BLPE mode, clear C2[LP] to 0 here to switch to PBE mode. d. PBE: Loop until S[PLLST] is set, indicating that the current source for the PLLS clock is the PLL. e. PBE: Then loop until S[LOCK0] is set, indicating that the PLL has acquired lock. 4. Lastly, PBE mode transitions into PEE mode: a. C1 = 0x10 * C1[CLKS] set to 2'b00 to select the output of the PLL as the system clock source. b. Loop until S[CLKST] are 2'b11, indicating that the PLL output is selected to feed MCGOUTCLK in the current clock mode. * Now, with PRDIV of divide-by-2, and C6[VDIV] of multiply-by-24, MCGOUTCLK = [(4 MHz / 2) * 24] = 48 MHz. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 542 Freescale Semiconductor, Inc. Chapter 25 Multipurpose Clock Generator (MCG) START IN FEI MODE C6 = 0x40 C2 = 0x1C IN BLPE MODE ? (S[LP]=1) C1 = 0x90 NO YES C2 = 0x1C (S[LP]=0) NO CHECK S[OSCINIT] = 1? CHECK S[PLLST] = 1? YES CHECK S[IREFST] = 0? NO YES CHECK S[LOCK] = 1? YES CHECK NO S[CLKST] = %10? NO NO YES C1 = 0x10 YES C5 = 0x01 (C5[VDIV] = 1) ENTER BLPE MODE ? YES CHECK S[CLKST] = %11? NO NO YES CONTINUE IN PEE MODE C2 = 0x1E (C2[LP] = 1) Figure 25-3. Flowchart of FEI to PEE mode transition using an 4 MHz crystal KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 543 Initialization / Application information 25.5.3.2 Example 2: Moving from PEE to BLPI mode: MCGOUTCLK frequency =32 kHz In this example, the MCG will move through the proper operational modes from PEE mode with a 4 MHz crystal configured for a 48 MHz MCGOUTCLK frequency (see previous example) to BLPI mode with a 32 kHz MCGOUTCLK frequency. First, the code sequence will be described. Then there is a flowchart that illustrates the sequence. 1. First, PEE must transition to PBE mode: a. C1 = 0x90 * C1[CLKS] set to 2'b10 to switch the system clock source to the external reference clock. b. Loop until S[CLKST] are 2'b10, indicating that the external reference clock is selected to feed MCGOUTCLK. 2. Then, PBE must transition either directly to FBE mode or first through BLPE mode and then to FBE mode: a. BLPE: If a transition through BLPE mode is desired, first set C2[LP] to 1. b. BLPE/FBE: C6 = 0x00 * C6[PLLS] clear to 0 to select the FLL. At this time, with C1[FRDIV] value of 3'b010, the FLL divider is set to 128, resulting in a reference frequency of 4 MHz / 128 = 31.25 kHz. If C1[FRDIV] was not previously set to 3'b010 (necessary to achieve required 31.25-39.06 kHz FLL reference frequency with an 4 MHz external source frequency), it must be changed prior to clearing C6[PLLS] bit. In BLPE mode,changing this bit only prepares the MCG for FLL usage in FBE mode. With C6[PLLS] = 0, the C6[VDIV] value does not matter. c. BLPE: If transitioning through BLPE mode, clear C2[LP] to 0 here to switch to FBE mode. d. FBE: Loop until S[PLLST] is cleared, indicating that the current source for the PLLS clock is the FLL. 3. Next, FBE mode transitions into FBI mode: a. C1 = 0x54 * C1[CLKS] set to 2'b01 to switch the system clock to the internal reference clock. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 544 Freescale Semiconductor, Inc. Chapter 25 Multipurpose Clock Generator (MCG) * C1[IREFS] set to 1 to select the internal reference clock as the reference clock source. * C1[FRDIV] remain unchanged because the reference divider does not affect the internal reference. b. Loop until S[IREFST] is 1, indicating the internal reference clock has been selected as the reference clock source. c. Loop until S[CLKST] are 2'b01, indicating that the internal reference clock is selected to feed MCGOUTCLK. 4. Lastly, FBI transitions into BLPI mode. a. C2 = 0x02 * C2[LP] is 1 * C2[RANGE], C2[HGO], C2[EREFS], C1[IRCLKEN], and C1[IREFSTEN] bits are ignored when the C1[IREFS] bit is set. They can remain set, or be cleared at this point. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 545 Initialization / Application information START IN PEE MODE C1 = 0x90 CHECK S[PLLST] = 0? NO CHECK S[CLKST] = %10 ? YES C1 = 0x54 YES ENTER NO NO BLPE MODE ? YES CHECK S[IREFST] = 0? NO YES C2 = 0x1E (C2[LP] = 1) CHECK S[CLKST] = %01? C6 = 0x00 IN BLPE MODE ? (C2[LP]=1) NO YES C2 = 0x02 NO CONTINUE YES IN BLPI MODE C2 = 0x1C (C2[LP] = 0) Figure 25-4. Flowchart of PEE to BLPI mode transition using an 4 MHz crystal KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 546 Freescale Semiconductor, Inc. Chapter 25 Multipurpose Clock Generator (MCG) 25.5.3.3 Example 3: Moving from BLPI to FEE mode In this example, the MCG will move through the proper operational modes from BLPI mode at a 32 kHz MCGOUTCLK frequency running off the internal reference clock (see previous example) to FEE mode using a 4 MHz crystal configured for a 20 MHz MCGOUTCLK frequency. First, the code sequence will be described. Then there is a flowchart that illustrates the sequence. 1. First, BLPI must transition to FBI mode. a. C2 = 0x00 * C2[LP] is 0 2. Next, FBI will transition to FEE mode. a. C2 = 0x1C * C2[RANGE] set to 2'b01 because the frequency of 4 MHz is within the high frequency range. * C2[HGO] set to 1 to configure the crystal oscillator for high gain operation. * C2[EREFS] set to 1, because a crystal is being used. b. C1 = 0x10 * C1[CLKS] set to 2'b00 to select the output of the FLL as system clock source. * C1[FRDIV] remain at 3'b010, or divide-by-128 for a reference of 4 MHz / 128 = 31.25 kHz. * C1[IREFS] cleared to 0, selecting the external reference clock. c. Loop until S[OSCINIT] is 1, indicating the crystal selected by the C2[EREFS] bit has been initialized. d. Loop until S[IREFST] is 0, indicating the external reference clock is the current source for the reference clock. e. Loop until S[CLKST] are 2'b00, indicating that the output of the FLL is selected to feed MCGOUTCLK. f. Now, with a 31.25 kHz reference frequency, a fixed DCO multiplier of 640, MCGOUTCLK = 31.25 kHz * 640 / 1 = 20 MHz. g. At this point, by default, the C4[DRST_DRS] bits are set to 2'b00 and C4[DMX32] is cleared to 0. If the MCGOUTCLK frequency of 40 MHz is desired instead, set the C4[DRST_DRS] bits to 0x01 to switch the FLL KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 547 Initialization / Application information multiplication factor from 640 to 1280. To return the MCGOUTCLK frequency to 20 MHz, set C4[DRST_DRS] bits to 2'b00 again, and the FLL multiplication factor will switch back to 640. START IN BLPI MODE CHECK NO S[IREFST] = 0? C2 = 0x00 YES C2 = 0x1C NO CHECK S[CLKST] = %00? C1 = 0x10 YES CONTINUE CHECK S[OSCINIT] = 1 ? NO IN FEE MODE YES Figure 25-5. Flowchart of BLPI to FEE mode transition using an 4 MHz crystal KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 548 Freescale Semiconductor, Inc. Chapter 26 Oscillator (OSC) 26.1 Introduction NOTE For the chip-specific implementation details of this module's instances, see the chip configuration information. The OSC module is a crystal oscillator. The module, in conjunction with an external crystal or resonator, generates a reference clock for the MCU. 26.2 Features and Modes Key features of the module are listed here. * Supports 32 kHz crystals (Low Range mode) * Supports 3-8 MHz, 8-32 MHz crystals and resonators (High Range mode) * Automatic Gain Control (AGC) to optimize power consumption in high frequency ranges 3-8 MHz, 8-32 MHz using low-power mode * High gain option in frequency ranges: 32 kHz, 3-8 MHz, and 8-32 MHz * Voltage and frequency filtering to guarantee clock frequency and stability * Optionally external input bypass clock from EXTAL signal directly * One clock for MCU clock system * Two clocks for on-chip peripherals that can work in Stop modes Functional Description describes the module's operation in more detail. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 549 Block Diagram 26.3 Block Diagram The OSC module uses a crystal or resonator to generate three filtered oscillator clock signals.Three clocks are output from OSC module: OSCCLK for MCU system, OSCERCLK for on-chip peripherals, and OSC32KCLK. The OSCCLK can only work in run mode. OSCERCLK and OSC32KCLK can work in low power modes. For the clock source assignments, refer to the clock distribution information of this MCU. Refer to the chip configuration details for the external reference clock source in this MCU. The figure found here shows the block diagram of the OSC module. EXTAL XTAL Mux OSC Clock Enable OSC_CLK_OUT OSCERCLK_UNDIV ERCLKEN Range selections Low Power config XTL_CLK Oscillator Circuits ERPS EN DIV OSCERCLK OSC32KCLK ERCLKEN OSC clock selection EREFSTEN OSC_EN 4096 Counter Control and Decoding logic CNT_DONE_4096 OSCCLK STOP Figure 26-1. OSC Module Block Diagram 26.4 OSC Signal Descriptions The table found here shows the user-accessible signals available for the OSC module. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 550 Freescale Semiconductor, Inc. Chapter 26 Oscillator (OSC) Refer to signal multiplexing information for this MCU for more details. Table 26-1. OSC Signal Descriptions Signal Description EXTAL External clock/Oscillator input I Oscillator output O XTAL I/O 26.5 External Crystal / Resonator Connections The connections for a crystal/resonator frequency reference are shown in the figures found here. When using low-frequency, low-power mode, the only external component is the crystal or ceramic resonator itself. In the other oscillator modes, load capacitors (Cx, Cy) and feedback resistor (RF) are required. The following table shows all possible connections. Table 26-2. External Caystal/Resonator Connections Oscillator Mode Connections Low-frequency (32 kHz), low-power Connection 1 Low-frequency (32 kHz), high-gain Connection 2/Connection 31 High-frequency (3~32 MHz), low-power Connection 1/Connection 32,2 High-frequency (3~32 MHz), high-gain Connection 2/Connection 32 1. When the load capacitors (Cx, Cy) are greater than 30 pF, use Connection 3. 2. With the low-power mode, the oscillator has the internal feedback resistor RF. Therefore, the feedback resistor must not be externally with the Connection 3. OSC XTAL VSS EXTAL Crystal or Resonator Figure 26-2. Crystal/Ceramic Resonator Connections - Connection 1 KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 551 External Clock Connections OSC EXTAL XTAL VSS RF Crystal or Resonator Figure 26-3. Crystal/Ceramic Resonator Connections - Connection 2 NOTE Connection 1 and Connection 2 should use internal capacitors as the load of the oscillator by configuring the CR[SCxP] bits. OSC EXTAL XTAL VSS Cx Cy RF Crystal or Resonator Figure 26-4. Crystal/Ceramic Resonator Connections - Connection 3 26.6 External Clock Connections In external clock mode, the pins can be connected as shown in the figure found here. NOTE XTAL can be used as a GPIO when the GPIO alternate function is configured for it. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 552 Freescale Semiconductor, Inc. Chapter 26 Oscillator (OSC) OSC XTAL VSS EXTAL Clock Input I/O Figure 26-5. External Clock Connections 26.7 Memory Map/Register Definitions Some oscillator module register bits are typically incorporated into other peripherals such as MCG or SIM. 26.7.1 OSC Memory Map/Register Definition OSC memory map Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 4006_5000 OSC Control Register (OSC_CR) 8 R/W 00h 26.7.1.1/ 553 4006_5002 OSC_DIV (OSC_OSC_DIV) 8 R/W 00h 26.7.1.2/ 555 26.7.1.1 OSC Control Register (OSC_CR) NOTE After OSC is enabled and starts generating the clocks, the configurations such as low power and frequency range, must not be changed. Address: 4006_5000h base + 0h offset = 4006_5000h Bit Read Write Reset 7 6 5 4 3 2 1 0 ERCLKEN 0 EREFSTEN 0 SC2P SC4P SC8P SC16P 0 0 0 0 0 0 0 0 KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 553 OSC Memory Map/Register Definition OSC_CR field descriptions Field 7 ERCLKEN Description External Reference Enable Enables external reference clock (OSCERCLK) . 0 1 6 Reserved 5 EREFSTEN This field is reserved. This read-only field is reserved and always has the value 0. External Reference Stop Enable Controls whether or not the external reference clock (OSCERCLK) remains enabled when MCU enters Stop mode. 0 1 4 Reserved 3 SC2P Oscillator 2 pF Capacitor Load Configure Configures the oscillator load. Configures the oscillator load. Disable the selection. Add 4 pF capacitor to the oscillator load. Oscillator 8 pF Capacitor Load Configure Configures the oscillator load. 0 1 0 SC16P Disable the selection. Add 2 pF capacitor to the oscillator load. Oscillator 4 pF Capacitor Load Configure 0 1 1 SC8P External reference clock is disabled in Stop mode. External reference clock stays enabled in Stop mode if ERCLKEN is set before entering Stop mode. This field is reserved. This read-only field is reserved and always has the value 0. 0 1 2 SC4P External reference clock is inactive. External reference clock is enabled. Disable the selection. Add 8 pF capacitor to the oscillator load. Oscillator 16 pF Capacitor Load Configure Configures the oscillator load. 0 1 Disable the selection. Add 16 pF capacitor to the oscillator load. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 554 Freescale Semiconductor, Inc. Chapter 26 Oscillator (OSC) 26.7.1.2 OSC_DIV (OSC_OSC_DIV) OSC Clock divider register. Address: 4006_5000h base + 2h offset = 4006_5002h Bit Read Write Reset 7 6 ERPS 0 0 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 OSC_OSC_DIV field descriptions Field 7-6 ERPS Description ERCLK prescaler. These two bits are used to divide the ERCLK output. The un-divided ERCLK output is not affected by these two bits. 00 01 10 11 The divisor ratio is 1. The divisor ratio is 2. The divisor ratio is 4. The divisor ratio is 8. 5 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 4 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 3 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 2 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 1 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 0 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 26.8 Functional Description Functional details of the module can be found here. 26.8.1 OSC module states The states of the OSC module are shown in the following figure. The states and their transitions between each other are described in this section. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 555 Functional Description Off Oscillator OFF OSC_CLK_OUT = Static OSCCLK not requested OSCCLK requested OSCCLK requested && && Select OSC internal clock Select clock from EXTAL signal Start-Up External Clock Mode Oscillator ON, not yet stable OSC_CLK_OUT = Static Oscillator ON OSC_CLK_OUT = EXTAL CNT_DONE_4096 Stable Oscillator ON, Stable OSC_CLK_OUT = XTL_CLK Figure 26-6. OSC Module state diagram NOTE XTL_CLK is the clock generated internally from OSC circuits. 26.8.1.1 Off The OSC enters the Off state when the system does not require OSC clocks. Upon entering this state, XTL_CLK is static unless OSC is configured to select the clock from the EXTAL pad by clearing the external reference clock selection bit. For details regarding the external reference clock source in this MCU, refer to the chip configuration details. The EXTAL and XTAL pins are also decoupled from all other oscillator circuitry in this state. The OSC module circuitry is configured to draw minimal current. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 556 Freescale Semiconductor, Inc. Chapter 26 Oscillator (OSC) 26.8.1.2 Oscillator startup The OSC enters startup state when it is configured to generate clocks (internally the OSC_EN transitions high) using the internal oscillator circuits by setting the external reference clock selection bit. In this state, the OSC module is enabled and oscillations are starting up, but have not yet stabilized. When the oscillation amplitude becomes large enough to pass through the input buffer, XTL_CLK begins clocking the counter. When the counter reaches 4096 cycles of XTL_CLK, the oscillator is considered stable and XTL_CLK is passed to the output clock OSC_CLK_OUT. 26.8.1.3 Oscillator Stable The OSC enters stable state when it is configured to generate clocks (internally the OSC_EN transitions high) using the internal oscillator circuits by setting the external reference clock selection bit and the counter reaches 4096 cycles of XTL_CLK (when CNT_DONE_4096 is high). In this state, the OSC module is producing a stable output clock on OSC_CLK_OUT. Its frequency is determined by the external components being used. 26.8.1.4 External Clock mode The OSC enters external clock state when it is enabled and external reference clock selection bit is cleared. For details regarding external reference clock source in this MCU, see the chip configuration details. In this state, the OSC module is set to buffer (with hysteresis) a clock from EXTAL onto the OSC_CLK_OUT. Its frequency is determined by the external clock being supplied. 26.8.2 OSC module modes The OSC is a pierce-type oscillator that supports external crystals or resonators operating over the frequency ranges shown in Table 26-3. These modes assume the following conditions: OSC is enabled to generate clocks (OSC_EN=1), configured to generate clocks internally (MCG_C2[EREFS] = 1), and some or one of the other peripherals (MCG, Timer, and so on) is configured to use the oscillator output clock (OSC_CLK_OUT). Table 26-3. Oscillator modes Mode Frequency Range Low-frequency, high-gain fosc_lo (32.768 kHz) up to fosc_lo (39.0625 kHz) Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 557 Functional Description Table 26-3. Oscillator modes (continued) Mode Frequency Range High-frequency mode1, high-gain fosc_hi_1 (3 MHz) up to fosc_hi_1 (8 MHz) High-frequency mode1, low-power High-frequency mode2, high-gain fosc_hi_2 (8 MHz) up to fosc_hi_2 (32 MHz) High-frequency mode2, low-power NOTE For information about low power modes of operation used in this chip and their alignment with some OSC modes, see the chip's Power Management details. 26.8.2.1 Low-Frequency, High-Gain Mode In Low-frequency, high-gain mode, the oscillator uses a simple inverter-style amplifier. The gain is set to achieve rail-to-rail oscillation amplitudes. The oscillator input buffer in this mode is single-ended. It provides low pass frequency filtering as well as hysteresis for voltage filtering and converts the output to logic levels. In this mode, the internal capacitors could be used. 26.8.2.2 Low-Frequency, Low-Power Mode In low-frequency, low-power mode, the oscillator uses a gain control loop to minimize power consumption. As the oscillation amplitude increases, the amplifier current is reduced. This continues until a desired amplitude is achieved at steady-state. This mode provides low pass frequency filtering as well as hysteresis for voltage filtering and converts the output to logic levels. In this mode, the internal capacitors could be used, the internal feedback resistor is connected, and no external resistor should be used. In this mode, the amplifier inputs, gain-control input, and input buffer input are all capacitively coupled for leakage tolerance (not sensitive to the DC level of EXTAL). Also in this mode, all external components except for the resonator itself are integrated, which includes the load capacitors and feeback resistor that biases EXTAL. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 558 Freescale Semiconductor, Inc. Chapter 26 Oscillator (OSC) 26.8.2.3 High-Frequency, High-Gain Mode In high-frequency, high-gain mode, the oscillator uses a simple inverter-style amplifier. The gain is set to achieve rail-to-rail oscillation amplitudes. This mode provides low pass frequency filtering as well as hysteresis for voltage filtering and converts the output to logic levels. In this mode, the internal capacitors could be used. 26.8.2.4 High-Frequency, Low-Power Mode In high-frequency, low-power mode, the oscillator uses a gain control loop to minimize power consumption. As the oscillation amplitude increases, the amplifier current is reduced. This continues until a desired amplitude is achieved at steady-state. In this mode, the internal capacitors could be used, the internal feedback resistor is connected, and no external resistor should be used. The oscillator input buffer in this mode is differential. It provides low pass frequency filtering as well as hysteresis for voltage filtering and converts the output to logic levels. 26.8.3 Counter The oscillator output clock (OSC_CLK_OUT) is gated off until the counter has detected 4096 cycles of its input clock (XTL_CLK). After 4096 cycles are completed, the counter passes XTL_CLK onto OSC_CLK_OUT. This counting timeout is used to guarantee output clock stability. 26.8.4 Reference clock pin requirements The OSC module requires use of both the EXTAL and XTAL pins to generate an output clock in Oscillator mode, but requires only the EXTAL pin in External clock mode. The EXTAL and XTAL pins are available for I/O. For the implementation of these pins on this device, refer to the Signal Multiplexing chapter. 26.9 Reset There is no reset state associated with the OSC module. The counter logic is reset when the OSC is not configured to generate clocks. There are no sources of reset requests for the OSC module. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 559 Low power modes operation 26.10 Low power modes operation When the MCU enters Stop modes, the OSC is functional depending on CR[ERCLKEN] and CR[EREFSETN] bit settings. If both these bits are set, the OSC is in operation. In Low Leakage Stop (LLS) modes, the OSC holds all register settings. If CR[ERCLKEN] and CR[EREFSTEN] are set before entry to Low Leakage Stop modes, the OSC is still functional in these modes. After waking up from Very Low Leakage Stop (VLLSx) modes, all OSC register bits are reset and initialization is required through software. 26.11 Interrupts The OSC module does not generate any interrupts. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 560 Freescale Semiconductor, Inc. Chapter 27 Flash Memory Controller (FMC) 27.1 Introduction NOTE For the chip-specific implementation details of this module's instances, see the chip configuration information. The Flash Memory Controller (FMC) is a memory acceleration unit that provides: * an interface between the device and the nonvolatile memory. * buffers that can accelerate flash memory transfers. 27.1.1 Overview The Flash Memory Controller manages the interface between the device and the flash memory. The FMC receives status information detailing the configuration of the memory and uses this information to ensure a proper interface. The following table shows the supported read/write operations. Flash memory type Program flash memory Read 8-bit, 16-bit, and 32-bit reads Write --1 1. A write operation to program flash memory results in a bus error. In addition, for bank 0 and bank 1, the FMC provides three separate mechanisms for accelerating the interface between the device and the flash memory. A 64-bit speculation buffer can prefetch the next 64-bit flash memory location, and both a 4-way, 8-set cache and a single-entry 64-bit buffer can store previously accessed flash memory data for quick access times. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 561 Modes of operation 27.1.2 Features The FMC's features include: * Interface between the device and the flash memory: * 8-bit, 16-bit, and 32-bit read operations to program flash memory. * For bank 0 and bank 1: Read accesses to consecutive 32-bit spaces in memory return the second read data with no wait states. The memory returns 64 bits via the 32-bit bus access. * Crossbar master access protection for setting no access, read-only access, writeonly access, or read/write access for each crossbar master. * For bank 0 and bank 1: Acceleration of data transfer from program flash memory to the device: * 64-bit prefetch speculation buffer with controls for instruction/data access per master and bank * 4-way, 8-set, 64-bit line size cache for a total of thirty-two 64-bit entries with controls for replacement algorithm and lock per way for each bank * Single-entry buffer per bank * Invalidation control for the speculation buffer and the single-entry buffer 27.2 Modes of operation The FMC only operates when a bus master accesses the flash memory. For any device power mode where the flash memory cannot be accessed, the FMC is disabled. 27.3 External signal description The FMC has no external signals. 27.4 Memory map and register descriptions The programming model consists of the FMC control registers and the program visible cache (data and tag/valid entries). NOTE Program the registers only while the flash controller is idle (for example, execute from RAM). Changing configuration settings KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 562 Freescale Semiconductor, Inc. Chapter 27 Flash Memory Controller (FMC) while a flash access is in progress can lead to non-deterministic behavior. Table 27-1. FMC register access Registers Read access Mode Write access Length Mode Length Control registers: PFAPR, PFB0CR, PFB1CR Supervisor (privileged) mode or user mode 32 bits Supervisor (privileged) mode only 32 bits Cache registers Supervisor (privileged) mode or user mode 32 bits Supervisor (privileged) mode only 32 bits NOTE Accesses to unimplemented registers within the FMC's 4 KB address space return a bus error. The cache entries, both data and tag/valid, can be read at any time. NOTE System software is required to maintain memory coherence when any segment of the flash cache is programmed. For example, all buffer data associated with the reprogrammed flash should be invalidated. Accordingly, cache program visible writes must occur after a programming or erase event is completed and before the new memory image is accessed. The cache is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and the sets are numbered 0-7. The following table elaborates on the tag/valid and data entries. Table 27-2. Program visible cache registers Cache storage Based at offset Contents of 32-bit read Nomenclature Nomenclature example Tag 100h 13'h0, tag[18:5], 4'h0, valid In TAGVDWxSy, x denotes the way and y denotes the set. TAGVDW2S0 is the 14-bit tag and 1-bit valid for cache entry way 2, set 0. Data 200h Upper or lower longword of data In DATAWxSyU and DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and lower word, respectively. DATAW1S0U represents bits [63:32] of data entry way 1, set 0, and DATAW1S0L represents bits [31:0] of data entry way 1, set 0. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 563 Memory map and register descriptions FMC memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4001_F000 Flash Access Protection Register (FMC_PFAPR) 32 R/W 00F8_003Fh 27.4.1/568 4001_F004 Flash Bank 0 Control Register (FMC_PFB0CR) 32 R/W 3002_001Fh 27.4.2/570 4001_F008 Flash Bank 1 Control Register (FMC_PFB1CR) 32 R/W 3002_001Fh 27.4.3/573 4001_F100 Cache Tag Storage (FMC_TAGVDW0S0) 32 R/W 0000_0000h 27.4.4/575 4001_F104 Cache Tag Storage (FMC_TAGVDW0S1) 32 R/W 0000_0000h 27.4.4/575 4001_F108 Cache Tag Storage (FMC_TAGVDW0S2) 32 R/W 0000_0000h 27.4.4/575 4001_F10C Cache Tag Storage (FMC_TAGVDW0S3) 32 R/W 0000_0000h 27.4.4/575 4001_F110 Cache Tag Storage (FMC_TAGVDW0S4) 32 R/W 0000_0000h 27.4.4/575 4001_F114 Cache Tag Storage (FMC_TAGVDW0S5) 32 R/W 0000_0000h 27.4.4/575 4001_F118 Cache Tag Storage (FMC_TAGVDW0S6) 32 R/W 0000_0000h 27.4.4/575 4001_F11C Cache Tag Storage (FMC_TAGVDW0S7) 32 R/W 0000_0000h 27.4.4/575 4001_F120 Cache Tag Storage (FMC_TAGVDW1S0) 32 R/W 0000_0000h 27.4.5/576 4001_F124 Cache Tag Storage (FMC_TAGVDW1S1) 32 R/W 0000_0000h 27.4.5/576 4001_F128 Cache Tag Storage (FMC_TAGVDW1S2) 32 R/W 0000_0000h 27.4.5/576 4001_F12C Cache Tag Storage (FMC_TAGVDW1S3) 32 R/W 0000_0000h 27.4.5/576 4001_F130 Cache Tag Storage (FMC_TAGVDW1S4) 32 R/W 0000_0000h 27.4.5/576 4001_F134 Cache Tag Storage (FMC_TAGVDW1S5) 32 R/W 0000_0000h 27.4.5/576 4001_F138 Cache Tag Storage (FMC_TAGVDW1S6) 32 R/W 0000_0000h 27.4.5/576 4001_F13C Cache Tag Storage (FMC_TAGVDW1S7) 32 R/W 0000_0000h 27.4.5/576 4001_F140 Cache Tag Storage (FMC_TAGVDW2S0) 32 R/W 0000_0000h 27.4.6/577 4001_F144 Cache Tag Storage (FMC_TAGVDW2S1) 32 R/W 0000_0000h 27.4.6/577 4001_F148 Cache Tag Storage (FMC_TAGVDW2S2) 32 R/W 0000_0000h 27.4.6/577 4001_F14C Cache Tag Storage (FMC_TAGVDW2S3) 32 R/W 0000_0000h 27.4.6/577 4001_F150 Cache Tag Storage (FMC_TAGVDW2S4) 32 R/W 0000_0000h 27.4.6/577 4001_F154 Cache Tag Storage (FMC_TAGVDW2S5) 32 R/W 0000_0000h 27.4.6/577 4001_F158 Cache Tag Storage (FMC_TAGVDW2S6) 32 R/W 0000_0000h 27.4.6/577 4001_F15C Cache Tag Storage (FMC_TAGVDW2S7) 32 R/W 0000_0000h 27.4.6/577 4001_F160 Cache Tag Storage (FMC_TAGVDW3S0) 32 R/W 0000_0000h 27.4.7/578 4001_F164 Cache Tag Storage (FMC_TAGVDW3S1) 32 R/W 0000_0000h 27.4.7/578 4001_F168 Cache Tag Storage (FMC_TAGVDW3S2) 32 R/W 0000_0000h 27.4.7/578 4001_F16C Cache Tag Storage (FMC_TAGVDW3S3) 32 R/W 0000_0000h 27.4.7/578 4001_F170 Cache Tag Storage (FMC_TAGVDW3S4) 32 R/W 0000_0000h 27.4.7/578 4001_F174 Cache Tag Storage (FMC_TAGVDW3S5) 32 R/W 0000_0000h 27.4.7/578 4001_F178 Cache Tag Storage (FMC_TAGVDW3S6) 32 R/W 0000_0000h 27.4.7/578 4001_F17C Cache Tag Storage (FMC_TAGVDW3S7) 32 R/W 0000_0000h 27.4.7/578 4001_F200 Cache Data Storage (upper word) (FMC_DATAW0S0U) 32 R/W 0000_0000h 27.4.8/578 4001_F204 Cache Data Storage (lower word) (FMC_DATAW0S0L) 32 R/W 0000_0000h 27.4.9/579 4001_F208 Cache Data Storage (upper word) (FMC_DATAW0S1U) 32 R/W 0000_0000h 27.4.8/578 Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 564 Freescale Semiconductor, Inc. Chapter 27 Flash Memory Controller (FMC) FMC memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4001_F20C Cache Data Storage (lower word) (FMC_DATAW0S1L) 32 R/W 0000_0000h 27.4.9/579 4001_F210 Cache Data Storage (upper word) (FMC_DATAW0S2U) 32 R/W 0000_0000h 27.4.8/578 4001_F214 Cache Data Storage (lower word) (FMC_DATAW0S2L) 32 R/W 0000_0000h 27.4.9/579 4001_F218 Cache Data Storage (upper word) (FMC_DATAW0S3U) 32 R/W 0000_0000h 27.4.8/578 4001_F21C Cache Data Storage (lower word) (FMC_DATAW0S3L) 32 R/W 0000_0000h 27.4.9/579 4001_F220 Cache Data Storage (upper word) (FMC_DATAW0S4U) 32 R/W 0000_0000h 27.4.8/578 4001_F224 Cache Data Storage (lower word) (FMC_DATAW0S4L) 32 R/W 0000_0000h 27.4.9/579 4001_F228 Cache Data Storage (upper word) (FMC_DATAW0S5U) 32 R/W 0000_0000h 27.4.8/578 4001_F22C Cache Data Storage (lower word) (FMC_DATAW0S5L) 32 R/W 0000_0000h 27.4.9/579 4001_F230 Cache Data Storage (upper word) (FMC_DATAW0S6U) 32 R/W 0000_0000h 27.4.8/578 4001_F234 Cache Data Storage (lower word) (FMC_DATAW0S6L) 32 R/W 0000_0000h 27.4.9/579 4001_F238 Cache Data Storage (upper word) (FMC_DATAW0S7U) 32 R/W 0000_0000h 27.4.8/578 4001_F23C Cache Data Storage (lower word) (FMC_DATAW0S7L) 32 R/W 0000_0000h 27.4.9/579 4001_F240 Cache Data Storage (upper word) (FMC_DATAW1S0U) 32 R/W 0000_0000h 27.4.10/ 579 4001_F244 Cache Data Storage (lower word) (FMC_DATAW1S0L) 32 R/W 0000_0000h 27.4.11/ 580 4001_F248 Cache Data Storage (upper word) (FMC_DATAW1S1U) 32 R/W 0000_0000h 27.4.10/ 579 4001_F24C Cache Data Storage (lower word) (FMC_DATAW1S1L) 32 R/W 0000_0000h 27.4.11/ 580 4001_F250 Cache Data Storage (upper word) (FMC_DATAW1S2U) 32 R/W 0000_0000h 27.4.10/ 579 4001_F254 Cache Data Storage (lower word) (FMC_DATAW1S2L) 32 R/W 0000_0000h 27.4.11/ 580 4001_F258 Cache Data Storage (upper word) (FMC_DATAW1S3U) 32 R/W 0000_0000h 27.4.10/ 579 4001_F25C Cache Data Storage (lower word) (FMC_DATAW1S3L) 32 R/W 0000_0000h 27.4.11/ 580 4001_F260 Cache Data Storage (upper word) (FMC_DATAW1S4U) 32 R/W 0000_0000h 27.4.10/ 579 4001_F264 Cache Data Storage (lower word) (FMC_DATAW1S4L) 32 R/W 0000_0000h 27.4.11/ 580 4001_F268 Cache Data Storage (upper word) (FMC_DATAW1S5U) 32 R/W 0000_0000h 27.4.10/ 579 4001_F26C Cache Data Storage (lower word) (FMC_DATAW1S5L) 32 R/W 0000_0000h 27.4.11/ 580 4001_F270 Cache Data Storage (upper word) (FMC_DATAW1S6U) 32 R/W 0000_0000h 27.4.10/ 579 4001_F274 Cache Data Storage (lower word) (FMC_DATAW1S6L) 32 R/W 0000_0000h 27.4.11/ 580 Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 565 Memory map and register descriptions FMC memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 32 R/W 0000_0000h 27.4.10/ 579 4001_F27C Cache Data Storage (lower word) (FMC_DATAW1S7L) 32 R/W 0000_0000h 27.4.11/ 580 4001_F280 Cache Data Storage (upper word) (FMC_DATAW2S0U) 32 R/W 0000_0000h 27.4.12/ 580 4001_F284 Cache Data Storage (lower word) (FMC_DATAW2S0L) 32 R/W 0000_0000h 27.4.13/ 581 4001_F288 Cache Data Storage (upper word) (FMC_DATAW2S1U) 32 R/W 0000_0000h 27.4.12/ 580 4001_F28C Cache Data Storage (lower word) (FMC_DATAW2S1L) 32 R/W 0000_0000h 27.4.13/ 581 4001_F290 Cache Data Storage (upper word) (FMC_DATAW2S2U) 32 R/W 0000_0000h 27.4.12/ 580 4001_F294 Cache Data Storage (lower word) (FMC_DATAW2S2L) 32 R/W 0000_0000h 27.4.13/ 581 4001_F298 Cache Data Storage (upper word) (FMC_DATAW2S3U) 32 R/W 0000_0000h 27.4.12/ 580 4001_F29C Cache Data Storage (lower word) (FMC_DATAW2S3L) 32 R/W 0000_0000h 27.4.13/ 581 4001_F2A0 Cache Data Storage (upper word) (FMC_DATAW2S4U) 32 R/W 0000_0000h 27.4.12/ 580 4001_F2A4 Cache Data Storage (lower word) (FMC_DATAW2S4L) 32 R/W 0000_0000h 27.4.13/ 581 4001_F2A8 Cache Data Storage (upper word) (FMC_DATAW2S5U) 32 R/W 0000_0000h 27.4.12/ 580 4001_F2AC Cache Data Storage (lower word) (FMC_DATAW2S5L) 32 R/W 0000_0000h 27.4.13/ 581 4001_F2B0 Cache Data Storage (upper word) (FMC_DATAW2S6U) 32 R/W 0000_0000h 27.4.12/ 580 4001_F2B4 Cache Data Storage (lower word) (FMC_DATAW2S6L) 32 R/W 0000_0000h 27.4.13/ 581 4001_F2B8 Cache Data Storage (upper word) (FMC_DATAW2S7U) 32 R/W 0000_0000h 27.4.12/ 580 4001_F2BC Cache Data Storage (lower word) (FMC_DATAW2S7L) 32 R/W 0000_0000h 27.4.13/ 581 4001_F2C0 Cache Data Storage (upper word) (FMC_DATAW3S0U) 32 R/W 0000_0000h 27.4.14/ 581 4001_F2C4 Cache Data Storage (lower word) (FMC_DATAW3S0L) 32 R/W 0000_0000h 27.4.15/ 582 4001_F2C8 Cache Data Storage (upper word) (FMC_DATAW3S1U) 32 R/W 0000_0000h 27.4.14/ 581 4001_F2CC Cache Data Storage (lower word) (FMC_DATAW3S1L) 32 R/W 0000_0000h 27.4.15/ 582 4001_F278 Cache Data Storage (upper word) (FMC_DATAW1S7U) Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 566 Freescale Semiconductor, Inc. Chapter 27 Flash Memory Controller (FMC) FMC memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 4001_F2D0 Cache Data Storage (upper word) (FMC_DATAW3S2U) 32 R/W 0000_0000h 27.4.14/ 581 4001_F2D4 Cache Data Storage (lower word) (FMC_DATAW3S2L) 32 R/W 0000_0000h 27.4.15/ 582 4001_F2D8 Cache Data Storage (upper word) (FMC_DATAW3S3U) 32 R/W 0000_0000h 27.4.14/ 581 4001_F2DC Cache Data Storage (lower word) (FMC_DATAW3S3L) 32 R/W 0000_0000h 27.4.15/ 582 4001_F2E0 Cache Data Storage (upper word) (FMC_DATAW3S4U) 32 R/W 0000_0000h 27.4.14/ 581 4001_F2E4 Cache Data Storage (lower word) (FMC_DATAW3S4L) 32 R/W 0000_0000h 27.4.15/ 582 4001_F2E8 Cache Data Storage (upper word) (FMC_DATAW3S5U) 32 R/W 0000_0000h 27.4.14/ 581 4001_F2EC Cache Data Storage (lower word) (FMC_DATAW3S5L) 32 R/W 0000_0000h 27.4.15/ 582 4001_F2F0 Cache Data Storage (upper word) (FMC_DATAW3S6U) 32 R/W 0000_0000h 27.4.14/ 581 4001_F2F4 Cache Data Storage (lower word) (FMC_DATAW3S6L) 32 R/W 0000_0000h 27.4.15/ 582 4001_F2F8 Cache Data Storage (upper word) (FMC_DATAW3S7U) 32 R/W 0000_0000h 27.4.14/ 581 32 R/W 0000_0000h 27.4.15/ 582 4001_F2FC Cache Data Storage (lower word) (FMC_DATAW3S7L) KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 567 Memory map and register descriptions 27.4.1 Flash Access Protection Register (FMC_PFAPR) Address: 4001_F000h base + 0h offset = 4001_F000h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved M2PFD M1PFD M0PFD R Reset 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Reserved W R Reserved Reserved Reserved 0 0 M2AP[1:0] M1AP[1:0] M0AP[1:0] W Reset 0 0 0 0 0 0 0 0 1 1 1 1 1 1 FMC_PFAPR field descriptions Field Description 31-24 Reserved This field is reserved. 23-20 Reserved This field is reserved. This read-only bitfield is reserved. Do not write to this bitfield or indeterminate results will occur. 19 Reserved This field is reserved. 18 M2PFD Master 2 Prefetch Disable These bits control whether prefetching is enabled, based on the logical number of the requesting crossbar switch master. This field is further qualified by the PFBnCR[BxDPE,BxIPE] bits. 0 1 17 M1PFD Prefetching for this master is enabled. Prefetching for this master is disabled. Master 1 Prefetch Disable These bits control whether prefetching is enabled, based on the logical number of the requesting crossbar switch master. This field is further qualified by the PFBnCR[BxDPE,BxIPE] bits. 0 1 Prefetching for this master is enabled. Prefetching for this master is disabled. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 568 Freescale Semiconductor, Inc. Chapter 27 Flash Memory Controller (FMC) FMC_PFAPR field descriptions (continued) Field 16 M0PFD Description Master 0 Prefetch Disable These bits control whether prefetching is enabled, based on the logical number of the requesting crossbar switch master. This field is further qualified by the PFBnCR[BxDPE,BxIPE] bits. 0 1 Prefetching for this master is enabled. Prefetching for this master is disabled. 15-10 Reserved This field is reserved. This read-only bitfield is reserved and is reset to zero. Do not write to this bitfield or indeterminate results will occur. 9-8 Reserved This field is reserved. 7-6 Reserved This field is reserved. 5-4 M2AP[1:0] Master 2 Access Protection This field controls whether read and write access to the flash is allowed, based on the logical master number of the requesting crossbar switch master. 00 01 10 11 3-2 M1AP[1:0] Master 1 Access Protection This field controls whether read and write access to the flash is allowed, based on the logical master number of the requesting crossbar switch master. 00 01 10 11 M0AP[1:0] No access may be performed by this master Only read accesses may be performed by this master Only write accesses may be performed by this master Both read and write accesses may be performed by this master No access may be performed by this master Only read accesses may be performed by this master Only write accesses may be performed by this master Both read and write accesses may be performed by this master Master 0 Access Protection This field controls whether read and write access to the flash is allowed, based on the logical master number of the requesting crossbar switch master. 00 01 10 11 No access may be performed by this master Only read accesses may be performed by this master Only write accesses may be performed by this master Both read and write accesses may be performed by this master KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 569 Memory map and register descriptions 27.4.2 Flash Bank 0 Control Register (FMC_PFB0CR) Address: 4001_F000h base + 4h offset = 4001_F004h Bit 31 30 29 28 27 26 25 24 23 22 B0RWSC[3:0] R 21 20 19 0 0 CINV_WAY[3:0] S_B_ INV 18 17 B0MW[1:0] 16 0 CLCK_WAY[3:0] Reset 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 B0DCE B0ICE B0DPE B0IPE B0SEBE W 1 1 1 1 1 0 R CRC[2:0] W Reset 0 0 0 0 0 0 0 0 0 0 0 FMC_PFB0CR field descriptions Field 31-28 B0RWSC[3:0] Description Bank 0 Read Wait State Control This read-only field defines the number of wait states required to access the bank 0 flash memory. The relationship between the read access time of the flash array (expressed in system clock cycles) and RWSC is defined as: Access time of flash array [system clocks] = RWSC + 1 The FMC automatically calculates this value based on the ratio of the system clock speed to the flash clock speed. For example, when this ratio is 4:1, the field's value is 3h. 27-24 Cache Lock Way x CLCK_WAY[3:0] These bits determine if the given cache way is locked such that its contents will not be displaced by future misses. The bit setting definitions are for each bit in the field. 0 1 Cache way is unlocked and may be displaced Cache way is locked and its contents are not displaced 23-20 Cache Invalidate Way x CINV_WAY[3:0] Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 570 Freescale Semiconductor, Inc. Chapter 27 Flash Memory Controller (FMC) FMC_PFB0CR field descriptions (continued) Field Description These bits determine if the given cache way is to be invalidated (cleared). When a bit within this field is written, the corresponding cache way is immediately invalidated: the way's tag, data, and valid contents are cleared. This field always reads as zero. Cache invalidation takes precedence over locking. The cache is invalidated by system reset. System software is required to maintain memory coherency when any segment of the flash memory is programmed or erased. Accordingly, cache invalidations must occur after a programming or erase event is completed and before the new memory image is accessed. The bit setting definitions are for each bit in the field. 0 1 19 S_B_INV Invalidate Prefetch Speculation Buffer This bit determines if the FMC's prefetch speculation buffer and the single entry page buffer are to be invalidated (cleared). When this bit is written, the speculation buffer and single entry buffer are immediately cleared. This bit always reads as zero. 0 1 18-17 B0MW[1:0] No cache way invalidation for the corresponding cache Invalidate cache way for the corresponding cache: clear the tag, data, and vld bits of ways selected Speculation buffer and single entry buffer are not affected. Invalidate (clear) speculation buffer and single entry buffer. Bank 0 Memory Width This read-only field defines the width of the bank 0 memory. 00 01 10 11 32 bits 64 bits Reserved Reserved 16 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 15-8 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 7-5 CRC[2:0] Cache Replacement Control This 3-bit field defines the replacement algorithm for accesses that are cached. 000 001 010 011 1xx 4 B0DCE Bank 0 Data Cache Enable This bit controls whether data references are loaded into the cache. 0 1 3 B0ICE LRU replacement algorithm per set across all four ways Reserved Independent LRU with ways [0-1] for ifetches, [2-3] for data Independent LRU with ways [0-2] for ifetches, [3] for data Reserved Do not cache data references. Cache data references. Bank 0 Instruction Cache Enable This bit controls whether instruction fetches are loaded into the cache. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 571 Memory map and register descriptions FMC_PFB0CR field descriptions (continued) Field Description 0 1 2 B0DPE Bank 0 Data Prefetch Enable This bit controls whether prefetches (or speculative accesses) are initiated in response to data references. 0 1 1 B0IPE Do not prefetch in response to data references. Enable prefetches in response to data references. Bank 0 Instruction Prefetch Enable This bit controls whether prefetches (or speculative accesses) are initiated in response to instruction fetches. 0 1 0 B0SEBE Do not cache instruction fetches. Cache instruction fetches. Do not prefetch in response to instruction fetches. Enable prefetches in response to instruction fetches. Bank 0 Single Entry Buffer Enable This bit controls whether the single entry page buffer is enabled in response to flash read accesses. Its operation is independent from bank 1's cache. A high-to-low transition of this enable forces the page buffer to be invalidated. 0 1 Single entry buffer is disabled. Single entry buffer is enabled. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 572 Freescale Semiconductor, Inc. Chapter 27 Flash Memory Controller (FMC) 27.4.3 Flash Bank 1 Control Register (FMC_PFB1CR) This register has a format similar to that for PFB0CR, except it controls the operation of flash bank 1, and the "global" cache control fields are empty. Address: 4001_F000h base + 8h offset = 4001_F008h Bit 31 30 29 28 27 26 25 24 B1RWSC[3:0] R 23 22 21 20 19 0 18 17 B1MW[1:0] 16 0 Reset 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 B1DCE B1ICE B1DPE B1IPE B1SEBE W 1 1 1 1 1 0 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 FMC_PFB1CR field descriptions Field 31-28 B1RWSC[3:0] Description Bank 1 Read Wait State Control This read-only field defines the number of wait states required to access the bank 1 flash memory. The relationship between the read access time of the flash array (expressed in system clock cycles) and RWSC is defined as: Access time of flash array [system clocks] = RWSC + 1 The FMC automatically calculates this value based on the ratio of the system clock speed to the flash clock speed. For example, when this ratio is 4:1, the field's value is 3h. 27-19 Reserved 18-17 B1MW[1:0] This field is reserved. This read-only field is reserved and always has the value 0. Bank 1 Memory Width This read-only field defines the width of the bank 1 memory. Table continues on the next page... KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 573 Memory map and register descriptions FMC_PFB1CR field descriptions (continued) Field Description 00 01 10 11 32 bits 64 bits Reserved Reserved 16 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 15-8 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 7-5 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 4 B1DCE Bank 1 Data Cache Enable This bit controls whether data references are loaded into the cache. 0 1 3 B1ICE Bank 1 Instruction Cache Enable This bit controls whether instruction fetches are loaded into the cache. 0 1 2 B1DPE This bit controls whether prefetches (or speculative accesses) are initiated in response to data references. Do not prefetch in response to data references. Enable prefetches in response to data references. Bank 1 Instruction Prefetch Enable This bit controls whether prefetches (or speculative accesses) are initiated in response to instruction fetches. 0 1 0 B1SEBE Do not cache instruction fetches. Cache instruction fetches. Bank 1 Data Prefetch Enable 0 1 1 B1IPE Do not cache data references. Cache data references. Do not prefetch in response to instruction fetches. Enable prefetches in response to instruction fetches. Bank 1 Single Entry Buffer Enable This bit controls whether the single entry buffer is enabled in response to flash read accesses. Its operation is independent from bank 0's cache. A high-to-low transition of this enable forces the page buffer to be invalidated. 0 1 Single entry buffer is disabled. Single entry buffer is enabled. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 574 Freescale Semiconductor, Inc. Chapter 27 Flash Memory Controller (FMC) 27.4.4 Cache Tag Storage (FMC_TAGVDW0Sn) The cache is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and the sets are numbered 0-7. In TAGVDWxSy, x denotes the way, and y denotes the set. This section represents tag/vld information for all sets in the indicated way. Address: 4001_F000h base + 100h offset + (4d x i), where i=0d to 7d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 0 R 17 16 tag[18:5] W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Reset 0 tag[18:5] W 0 0 0 0 0 0 0 0 0 0 0 0 0 valid 0 0 0 FMC_TAGVDW0Sn field descriptions Field Description 31-19 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 18-5 tag[18:5] 14-bit tag for cache entry 4-1 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 0 valid 1-bit valid for cache entry KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 575 Memory map and register descriptions 27.4.5 Cache Tag Storage (FMC_TAGVDW1Sn) The cache is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and the sets are numbered 0-7. In TAGVDWxSy, x denotes the way, and y denotes the set. This section represents tag/vld information for all sets in the indicated way. Address: 4001_F000h base + 120h offset + (4d x i), where i=0d to 7d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 0 R 17 16 tag[18:5] W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Reset 0 tag[18:5] W 0 0 0 0 0 0 0 0 0 0 0 0 0 valid 0 0 0 FMC_TAGVDW1Sn field descriptions Field Description 31-19 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 18-5 tag[18:5] 14-bit tag for cache entry 4-1 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 0 valid 1-bit valid for cache entry KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 576 Freescale Semiconductor, Inc. Chapter 27 Flash Memory Controller (FMC) 27.4.6 Cache Tag Storage (FMC_TAGVDW2Sn) The cache is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and the sets are numbered 0-7. In TAGVDWxSy, x denotes the way, and y denotes the set. This section represents tag/vld information for all sets in the indicated way. Address: 4001_F000h base + 140h offset + (4d x i), where i=0d to 7d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 0 R 17 16 tag[18:5] W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Reset 0 tag[18:5] W 0 0 0 0 0 0 0 0 0 0 0 0 0 valid 0 0 0 FMC_TAGVDW2Sn field descriptions Field Description 31-19 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 18-5 tag[18:5] 14-bit tag for cache entry 4-1 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 0 valid 1-bit valid for cache entry KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 577 Memory map and register descriptions 27.4.7 Cache Tag Storage (FMC_TAGVDW3Sn) The cache is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and the sets are numbered 0-7. In TAGVDWxSy, x denotes the way, and y denotes the set. This section represents tag/vld information for all sets in the indicated way. Address: 4001_F000h base + 160h offset + (4d x i), where i=0d to 7d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 0 R 17 16 tag[18:5] W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 tag[18:5] W Reset 0 0 0 0 0 0 0 0 0 0 0 0 valid 0 0 0 0 FMC_TAGVDW3Sn field descriptions Field Description 31-19 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 18-5 tag[18:5] 14-bit tag for cache entry 4-1 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 0 valid 1-bit valid for cache entry 27.4.8 Cache Data Storage (upper word) (FMC_DATAW0SnU) The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and the sets are numbered 0-7. In DATAWxSyU and DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and lower word, respectively. This section represents data for the upper word (bits [63:32]) of all sets in the indicated way. Address: 4001_F000h base + 200h offset + (8d x i), where i=0d to 7d Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data[63:32] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 578 Freescale Semiconductor, Inc. Chapter 27 Flash Memory Controller (FMC) FMC_DATAW0SnU field descriptions Field Description data[63:32] Bits [63:32] of data entry 27.4.9 Cache Data Storage (lower word) (FMC_DATAW0SnL) The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and the sets are numbered 0-7. In DATAWxSyU and DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and lower word, respectively. This section represents data for the lower word (bits [31:0]) of all sets in the indicated way. Address: 4001_F000h base + 204h offset + (8d x i), where i=0d to 7d Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FMC_DATAW0SnL field descriptions Field Description data[31:0] Bits [31:0] of data entry 27.4.10 Cache Data Storage (upper word) (FMC_DATAW1SnU) The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and the sets are numbered 0-7. In DATAWxSyU and DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and lower word, respectively. This section represents data for the upper word (bits [63:32]) of all sets in the indicated way. Address: 4001_F000h base + 240h offset + (8d x i), where i=0d to 7d Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data[63:32] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FMC_DATAW1SnU field descriptions Field data[63:32] Description Bits [63:32] of data entry KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 579 Memory map and register descriptions 27.4.11 Cache Data Storage (lower word) (FMC_DATAW1SnL) The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and the sets are numbered 0-7. In DATAWxSyU and DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and lower word, respectively. This section represents data for the lower word (bits [31:0]) of all sets in the indicated way. Address: 4001_F000h base + 244h offset + (8d x i), where i=0d to 7d Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FMC_DATAW1SnL field descriptions Field Description data[31:0] Bits [31:0] of data entry 27.4.12 Cache Data Storage (upper word) (FMC_DATAW2SnU) The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and the sets are numbered 0-7. In DATAWxSyU and DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and lower word, respectively. This section represents data for the upper word (bits [63:32]) of all sets in the indicated way. Address: 4001_F000h base + 280h offset + (8d x i), where i=0d to 7d Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data[63:32] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FMC_DATAW2SnU field descriptions Field data[63:32] Description Bits [63:32] of data entry KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 580 Freescale Semiconductor, Inc. Chapter 27 Flash Memory Controller (FMC) 27.4.13 Cache Data Storage (lower word) (FMC_DATAW2SnL) The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and the sets are numbered 0-7. In DATAWxSyU and DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and lower word, respectively. This section represents data for the lower word (bits [31:0]) of all sets in the indicated way. Address: 4001_F000h base + 284h offset + (8d x i), where i=0d to 7d Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FMC_DATAW2SnL field descriptions Field Description data[31:0] Bits [31:0] of data entry 27.4.14 Cache Data Storage (upper word) (FMC_DATAW3SnU) The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and the sets are numbered 0-7. In DATAWxSyU and DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and lower word, respectively. This section represents data for the upper word (bits [63:32]) of all sets in the indicated way. Address: 4001_F000h base + 2C0h offset + (8d x i), where i=0d to 7d Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data[63:32] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FMC_DATAW3SnU field descriptions Field data[63:32] Description Bits [63:32] of data entry KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 581 Functional description 27.4.15 Cache Data Storage (lower word) (FMC_DATAW3SnL) The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and the sets are numbered 0-7. In DATAWxSyU and DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and lower word, respectively. This section represents data for the lower word (bits [31:0]) of all sets in the indicated way. Address: 4001_F000h base + 2C4h offset + (8d x i), where i=0d to 7d Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FMC_DATAW3SnL field descriptions Field data[31:0] Description Bits [31:0] of data entry 27.5 Functional description The FMC is a flash acceleration unit with flexible buffers for user configuration. Besides managing the interface between the device and the flash memory, the FMC can be used to restrict access from crossbar switch masters and --for program flash only--to customize the cache and buffers to provide single-cycle system-clock data-access times. Whenever a hit occurs for the prefetch speculation buffer, the cache, or the single-entry buffer, the requested data is transferred within a single system clock. 27.5.1 Default configuration Upon system reset, the FMC is configured to provide a significant level of buffering for transfers from the flash memory: * Crossbar masters 0, 1, 2 have read access to bank 0 and bank 1. * For bank 0 and bank 1: * Prefetch support for data and instructions is enabled for crossbar masters 0, 1, 2. * The cache is configured for least recently used (LRU) replacement for all four ways. * The cache is configured for data or instruction replacement. * The single-entry buffer is enabled. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 582 Freescale Semiconductor, Inc. Chapter 27 Flash Memory Controller (FMC) 27.5.2 Configuration options Though the default configuration provides a high degree of flash acceleration, advanced users may desire to customize the FMC buffer configurations to maximize throughput for their use cases. When reconfiguring the FMC for custom use cases, do not program the FMC's control registers while the flash memory is being accessed. Instead, change the control registers with a routine executing from RAM in supervisor mode. The FMC's cache and buffering controls within PFB0CR and PFB1CR allow the tuning of resources to suit particular applications' needs. The cache and buffer are each controlled individually. The register controls enable buffering and prefetching per memory bank and access type (instruction fetch or data reference). The cache also supports 3 types of LRU replacement algorithms: * LRU per set across all 4 ways, * LRU with ways [0-1] for instruction fetches and ways [2-3] for data fetches, and * LRU with ways [0-2] for instruction fetches and way [3] for data fetches. As an application example: if both instruction fetches and data references are accessing flash memory, then control is available to send instruction fetches, data references, or both to the cache or the single-entry buffer. Likewise, speculation can be enabled or disabled for either type of access. If both instruction fetches and data references are cached, then the cache's way resources may be divided in several ways between the instruction fetches and data references. In another application example, the cache can be configured for replacement from bank 0, while the single-entry buffer can be enabled for bank 1 only. This configuration is ideal for applications that use bank 0 for program space and bank 1 for data space. 27.5.3 Speculative reads The FMC has a single buffer that reads ahead to the next word in the flash memory if there is an idle cycle. Speculative prefetching is programmable for each bank for instruction and/or data accesses using the B0DPE and B0IPE fields of PFB0CR and the B1DPE and B1IPE fields of PFB1CR. Because many code accesses are sequential, using the speculative prefetch buffer improves performance in most cases. When speculative reads are enabled, the FMC immediately requests the next sequential address after a read completes. By requesting the next word immediately, speculative reads can help to reduce or even eliminate wait states when accessing sequential code and/or data. KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 583 Functional description For example, consider the following scenario: * Assume a system with a 4:1 core-to-flash clock ratio and with speculative reads enabled. * The core requests four sequential longwords in back-to-back requests, meaning there are no core cycle delays except for stalls waiting for flash memory data to be returned. * None of the data is already stored in the cache or speculation buffer. In this scenario, the sequence of events for accessing the four longwords is as follows: 1. The first longword read requires 4 to 7 core clocks. See Wait states for more information. 2. Due to the 64-bit data bus of the flash memory, the second longword read takes only 1 core clock because the data is already available inside the FMC. While the data for the second longword is being returned to the core, the FMC also starts reading the third and fourth longwords from the flash memory. 3. Accessing the third longword requires 3 core clock cycles. The flash memory read itself takes 4 clocks, but the first clock overlaps with the second longword read. 4. Reading the fourth longword, like the second longword, takes only 1 clock due to the 64-bit flash memory data bus. 27.5.4 Flash Access Control (FAC) Function The Flash Access Control (FAC) is a configurable memory protection scheme optimized to allow end users to use software libraries while offering programmable restrictions to these libraries. The flash memory is divided into equal size segments that provide protection to proprietary software libraries. The protection of these segments is controlled: the FAC provides a cycle-by-cycle evaluation of the access rights for each transaction routed to the on-chip flash memory. Two levels of vendors can add their proprietary software to a device; FAC protection of segments for each level are defined once, using the PGMONCE command. Flash access control aligns to the 3 privilege levels supported by ARM Cortex-M family products: * Most secure state is supervisor/privileged secure: allows execute-only and provides supervisor-only access control. * Mid-level state is execute-only. * Unsecure state is where no access control states are set. Features: * Lightweight access control logic for on-chip flash memory KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 584 Freescale Semiconductor, Inc. Chapter 27 Flash Memory Controller (FMC) * Flash address space divided into (32 or 64) equal-sized segments (segment size is defined as flash_size [bytes]/(32 or 64)) * Separate control bits for supervisor-only access and execute-only access per segment * Access control evaluated on each bus cycle routed to the flash * Access violation errors terminate the bus cycle and return zeroes for read data * Programming model allows 2 levels of protected segments 27.5.4.1 Memory map and register definitions The following table shows the mapping of FAC registers. Descriptions of each register and its bit assignments follow. * The Flash Management Unit (FMU) supports access to its FAC programming model via a 32-bit slave peripheral bus connection. * Unimplemented register bits read as zero. * For implementations supporting only 32 segments, only the 32-bit "low" register is implemented. * Writes to any read-only or reserved registers are ignored; attempts to access flash register space above offset '2B' will generate a transfer error. * The terms supervisor and user modes are equivalent to privileged and unprivileged modes. * In this FAC section, n refers to the segment number, and x is the acronym of the module that the registers are in (which sometimes varies from one device to another). x memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 18 Execute-only Access Register High (x_XACCH) 32 R See section 27.5.4.1.1/ 586 1C Execute-only Access Register Low (x_XACCL) 32 R See section 27.5.4.1.2/ 586 20 Supervisor-only Access Register High (x_SACCH) 32 R See section 27.5.4.1.3/ 587 24 Supervisor-only Access Register Low (x_SACCL) 32 R See section 27.5.4.1.4/ 588 28 Configuration Register (x_CR) 32 R See section 27.5.4.1.5/ 588 KV31F Sub-Family Reference Manual , Rev. 4, 02/2016 Freescale Semiconductor, Inc. 585 Functional description 27.5.4.1.1 Execute-only Access Register High (x_XACCH) The execute-only access register is a 64-bit register that is implemented as two 32-bit registers. * High execute-only access bits (segments 63-32) are contained in x_XACCH. * Low execute-only access bits (segments 31-0) are contained in x_XACCL. The x_XACC{H,L} registers provide a bit map for the flash segments, to allow data read or execute only or both data and instruction fetches for each associated segment. By definition, execute-only accesses include