KV31F Sub-Family Reference Manual
Supports: MKV31F512VLL12, MKV31F512VLH12, MKV31512VLL12P
Document Number: KV31P100M120SF7RM
Rev. 4, 02/2016
KV31F Sub-Family Reference Manual , Rev. 4, 02/2016
2 Freescale Semiconductor, Inc.
Contents
Section number Title Page
Chapter 1
About This Document
1.1 Overview.......................................................................................................................................................................43
1.1.1 Purpose.........................................................................................................................................................43
1.1.2 Audience...................................................................................................................................................... 43
1.2 Conventions.................................................................................................................................................................. 43
1.2.1 Numbering systems......................................................................................................................................43
1.2.2 Typographic notation................................................................................................................................... 44
1.2.3 Special terms................................................................................................................................................44
Chapter 2
Introduction
2.1 Overview.......................................................................................................................................................................45
2.2 Module Functional Categories......................................................................................................................................45
2.2.1 ARM® Cortex®-M4 Core Modules............................................................................................................46
2.2.2 System Modules...........................................................................................................................................47
2.2.3 Memories and Memory Interfaces............................................................................................................... 48
2.2.4 Clocks...........................................................................................................................................................48
2.2.5 Security and Integrity modules.................................................................................................................... 48
2.2.6 Analog modules........................................................................................................................................... 49
2.2.7 Timer modules............................................................................................................................................. 49
2.2.8 Communication interfaces........................................................................................................................... 50
2.2.9 Human-machine interfaces.......................................................................................................................... 50
2.2.10 Kinetis Motor Suite......................................................................................................................................51
2.3 Orderable part numbers.................................................................................................................................................51
Chapter 3
Chip Configuration
3.1 Introduction...................................................................................................................................................................53
3.2 Core modules................................................................................................................................................................ 53
KV31F Sub-Family Reference Manual , Rev. 4, 02/2016
Freescale Semiconductor, Inc. 3
Section number Title Page
3.2.1 ARM Cortex-M4 Core Configuration..........................................................................................................53
3.2.2 Nested Vectored Interrupt Controller (NVIC) Configuration......................................................................55
3.2.3 Asynchronous Wake-up Interrupt Controller (AWIC) Configuration.........................................................61
3.2.4 FPU Configuration.......................................................................................................................................62
3.2.5 JTAG Controller Configuration...................................................................................................................62
3.3 System modules............................................................................................................................................................ 63
3.3.1 SIM Configuration....................................................................................................................................... 63
3.3.2 System Mode Controller (SMC) Configuration...........................................................................................64
3.3.3 PMC Configuration......................................................................................................................................64
3.3.4 Low-Leakage Wake-up Unit (LLWU) Configuration.................................................................................65
3.3.5 MCM Configuration.................................................................................................................................... 66
3.3.6 Crossbar-Light Switch Configuration..........................................................................................................67
3.3.7 Peripheral Bridge Configuration..................................................................................................................69
3.3.8 DMA request multiplexer configuration......................................................................................................70
3.3.9 DMA Controller Configuration................................................................................................................... 73
3.3.10 External Watchdog Monitor (EWM) Configuration....................................................................................74
3.3.11 Watchdog Configuration..............................................................................................................................76
3.4 Clock modules.............................................................................................................................................................. 77
3.4.1 MCG Configuration..................................................................................................................................... 77
3.4.2 OSC Configuration...................................................................................................................................... 79
3.5 Memories and memory interfaces.................................................................................................................................79
3.5.1 Flash Memory Configuration.......................................................................................................................79
3.5.2 Flash Memory Controller Configuration..................................................................................................... 82
3.5.3 SRAM Configuration...................................................................................................................................83
3.5.4 System Register File Configuration.............................................................................................................84
3.5.5 EzPort Configuration................................................................................................................................... 85
3.5.6 FlexBus Configuration.................................................................................................................................86
3.6 Security......................................................................................................................................................................... 89
3.6.1 CRC Configuration...................................................................................................................................... 89
KV31F Sub-Family Reference Manual , Rev. 4, 02/2016
4 Freescale Semiconductor, Inc.
Section number Title Page
3.6.2 RNG Configuration......................................................................................................................................90
3.7 Analog...........................................................................................................................................................................91
3.7.1 16-bit SAR ADC Configuration.................................................................................................................. 91
3.7.2 CMP Configuration......................................................................................................................................97
3.7.3 12-bit DAC Configuration........................................................................................................................... 99
3.7.4 VREF Configuration....................................................................................................................................101
3.8 Timers........................................................................................................................................................................... 102
3.8.1 PDB Configuration...................................................................................................................................... 102
3.8.2 FlexTimer Configuration............................................................................................................................. 105
3.8.3 PIT Configuration........................................................................................................................................ 111
3.8.4 Low-power timer configuration...................................................................................................................112
3.9 Communication interfaces............................................................................................................................................ 114
3.9.1 SPI configuration......................................................................................................................................... 114
3.9.2 I2C Configuration........................................................................................................................................ 118
3.9.3 UART Configuration................................................................................................................................... 118
3.9.4 LPUART configuration................................................................................................................................121
3.10 Human-machine interfaces........................................................................................................................................... 121
3.10.1 GPIO configuration......................................................................................................................................122
3.11 Kinetis Motor Suite Configuration............................................................................................................................... 122
3.11.1 KMS configuration...................................................................................................................................... 123
3.11.2 KMS Library................................................................................................................................................123
3.11.3 Library Protection........................................................................................................................................ 124
3.11.4 Flash protection............................................................................................................................................124
Chapter 4
Memory Map
4.1 Introduction...................................................................................................................................................................125
4.2 System memory map.....................................................................................................................................................125
4.2.1 Aliased bit-band regions.............................................................................................................................. 127
4.2.2 Flash Access Control Introduction...............................................................................................................128
KV31F Sub-Family Reference Manual , Rev. 4, 02/2016
Freescale Semiconductor, Inc. 5
Section number Title Page
4.3 Flash Memory Map.......................................................................................................................................................128
4.3.1 Alternate Non-Volatile IRC User Trim Description....................................................................................129
4.4 SRAM memory map.....................................................................................................................................................129
4.5 Peripheral bridge (AIPS-Lite) memory map.................................................................................................................130
4.5.1 Read-after-write sequence and required serialization of memory operations..............................................130
4.5.2 Peripheral Bridge 0 (AIPS-Lite 0) Memory Map........................................................................................ 130
4.6 Private Peripheral Bus (PPB) memory map..................................................................................................................134
Chapter 5
Clock Distribution
5.1 Introduction...................................................................................................................................................................137
5.2 Programming model......................................................................................................................................................137
5.3 High-Level device clocking diagram............................................................................................................................137
5.4 Clock definitions...........................................................................................................................................................138
5.4.1 Device clock summary.................................................................................................................................139
5.5 Internal clocking requirements..................................................................................................................................... 141
5.5.1 Clock divider values after reset....................................................................................................................142
5.5.2 VLPR mode clocking...................................................................................................................................143
5.6 Clock Gating.................................................................................................................................................................143
5.7 Module clocks...............................................................................................................................................................143
5.7.1 PMC 1-kHz LPO clock................................................................................................................................145
5.7.2 IRC 48MHz clock........................................................................................................................................ 145
5.7.3 WDOG clocking.......................................................................................................................................... 146
5.7.4 Debug trace clock.........................................................................................................................................146
5.7.5 PORT digital filter clocking.........................................................................................................................147
5.7.6 LPTMR clocking..........................................................................................................................................147
5.7.7 CLKOUT32K clocking................................................................................................................................148
5.7.8 UART clocking............................................................................................................................................148
5.7.9 LPUART0 clocking..................................................................................................................................... 149
Chapter 6
KV31F Sub-Family Reference Manual , Rev. 4, 02/2016
6 Freescale Semiconductor, Inc.
Section number Title Page
Reset and Boot
6.1 Introduction...................................................................................................................................................................151
6.2 Reset..............................................................................................................................................................................152
6.2.1 Power-on reset (POR).................................................................................................................................. 152
6.2.2 System reset sources.................................................................................................................................... 152
6.2.3 MCU Resets................................................................................................................................................. 156
6.2.4 Reset Pin ..................................................................................................................................................... 157
6.2.5 Debug resets.................................................................................................................................................158
6.3 Boot...............................................................................................................................................................................159
6.3.1 Boot sources.................................................................................................................................................159
6.3.2 Boot options................................................................................................................................................. 159
6.3.3 FOPT boot options.......................................................................................................................................159
6.3.4 Boot sequence.............................................................................................................................................. 161
Chapter 7
Power Management
7.1 Introduction...................................................................................................................................................................163
7.2 Clocking modes............................................................................................................................................................ 163
7.2.1 Partial Stop...................................................................................................................................................163
7.2.2 DMA Wakeup..............................................................................................................................................164
7.2.3 Compute Operation......................................................................................................................................165
7.2.4 Peripheral Doze............................................................................................................................................166
7.2.5 Clock Gating................................................................................................................................................ 167
7.3 Power Modes Description.............................................................................................................................................167
7.4 Entering and exiting power modes............................................................................................................................... 169
7.5 Power mode transitions.................................................................................................................................................170
7.6 Power modes shutdown sequencing............................................................................................................................. 171
7.7 Flash Program Restrictions...........................................................................................................................................172
7.8 Module Operation in Low Power Modes......................................................................................................................172
Chapter 8
Security
KV31F Sub-Family Reference Manual , Rev. 4, 02/2016
Freescale Semiconductor, Inc. 7
Section number Title Page
8.1 Introduction...................................................................................................................................................................177
8.2 Flash Security............................................................................................................................................................... 177
8.3 Security Interactions with other Modules.....................................................................................................................178
8.3.1 Security interactions with FlexBus.............................................................................................................. 178
8.3.2 Security Interactions with EzPort................................................................................................................ 178
8.3.3 Security Interactions with Debug.................................................................................................................178
Chapter 9
Debug
9.1 Introduction...................................................................................................................................................................181
9.1.1 References....................................................................................................................................................183
9.2 The Debug Port.............................................................................................................................................................183
9.2.1 JTAG-to-SWD change sequence................................................................................................................. 184
9.2.2 JTAG-to-cJTAG change sequence...............................................................................................................184
9.3 Debug Port Pin Descriptions.........................................................................................................................................185
9.4 System TAP connection................................................................................................................................................185
9.4.1 IR Codes.......................................................................................................................................................185
9.5 JTAG status and control registers.................................................................................................................................186
9.5.1 MDM-AP Control Register..........................................................................................................................187
9.5.2 MDM-AP Status Register............................................................................................................................ 189
9.6 Debug Resets................................................................................................................................................................ 190
9.7 AHB-AP........................................................................................................................................................................191
9.8 ITM............................................................................................................................................................................... 191
9.9 Core Trace Connectivity...............................................................................................................................................192
9.10 TPIU..............................................................................................................................................................................192
9.11 DWT............................................................................................................................................................................. 192
9.12 Debug in Low Power Modes........................................................................................................................................ 193
9.12.1 Debug Module State in Low Power Modes.................................................................................................193
9.13 Debug & Security......................................................................................................................................................... 194
Chapter 10
KV31F Sub-Family Reference Manual , Rev. 4, 02/2016
8 Freescale Semiconductor, Inc.
Section number Title Page
Signal Multiplexing and Signal Descriptions
10.1 Introduction...................................................................................................................................................................195
10.2 Signal Multiplexing Integration....................................................................................................................................195
10.2.1 Port control and interrupt module features.................................................................................................. 196
10.2.2 Clock gating................................................................................................................................................. 197
10.2.3 Signal multiplexing constraints....................................................................................................................197
10.3 Pinout............................................................................................................................................................................197
10.3.1 KV31F Signal Multiplexing and Pin Assignments......................................................................................197
10.3.2 KV31F Pinouts.............................................................................................................................................201
10.4 Module Signal Description Tables................................................................................................................................204
10.4.1 Core Modules...............................................................................................................................................204
10.4.2 System Modules...........................................................................................................................................204
10.4.3 Clock Modules............................................................................................................................................. 205
10.4.4 Memories and Memory Interfaces............................................................................................................... 205
10.4.5 Analog..........................................................................................................................................................208
10.4.6 Timer Modules.............................................................................................................................................209
10.4.7 Communication Interfaces........................................................................................................................... 210
10.4.8 Human-Machine Interfaces (HMI).............................................................................................................. 212
Chapter 11
Port Control and Interrupts (PORT)
11.1 Introduction...................................................................................................................................................................213
11.2 Overview.......................................................................................................................................................................213
11.2.1 Features........................................................................................................................................................ 213
11.2.2 Modes of operation...................................................................................................................................... 214
11.3 External signal description............................................................................................................................................215
11.4 Detailed signal description............................................................................................................................................215
11.5 Memory map and register definition.............................................................................................................................215
11.5.1 Pin Control Register n (PORTx_PCRn).......................................................................................................222
11.5.2 Global Pin Control Low Register (PORTx_GPCLR)..................................................................................225
KV31F Sub-Family Reference Manual , Rev. 4, 02/2016
Freescale Semiconductor, Inc. 9
Section number Title Page
11.5.3 Global Pin Control High Register (PORTx_GPCHR).................................................................................225
11.5.4 Interrupt Status Flag Register (PORTx_ISFR)............................................................................................ 226
11.5.5 Digital Filter Enable Register (PORTx_DFER)...........................................................................................226
11.5.6 Digital Filter Clock Register (PORTx_DFCR)............................................................................................227
11.5.7 Digital Filter Width Register (PORTx_DFWR).......................................................................................... 227
11.6 Functional description...................................................................................................................................................228
11.6.1 Pin control....................................................................................................................................................228
11.6.2 Global pin control........................................................................................................................................ 229
11.6.3 External interrupts........................................................................................................................................229
11.6.4 Digital filter..................................................................................................................................................230
Chapter 12
System Integration Module (SIM)
12.1 Introduction...................................................................................................................................................................233
12.1.1 Features........................................................................................................................................................ 233
12.2 Memory map and register definition.............................................................................................................................234
12.2.1 System Options Register 1 (SIM_SOPT1).................................................................................................. 235
12.2.2 SOPT1 Configuration Register (SIM_SOPT1CFG)....................................................................................236
12.2.3 System Options Register 2 (SIM_SOPT2).................................................................................................. 237
12.2.4 System Options Register 4 (SIM_SOPT4).................................................................................................. 239
12.2.5 System Options Register 5 (SIM_SOPT5).................................................................................................. 242
12.2.6 System Options Register 7 (SIM_SOPT7).................................................................................................. 243
12.2.7 System Options Register 8 (SIM_SOPT8).................................................................................................. 245
12.2.8 System Device Identification Register (SIM_SDID)...................................................................................247
12.2.9 System Clock Gating Control Register 4 (SIM_SCGC4)............................................................................249
12.2.10 System Clock Gating Control Register 5 (SIM_SCGC5)............................................................................251
12.2.11 System Clock Gating Control Register 6 (SIM_SCGC6)............................................................................253
12.2.12 System Clock Gating Control Register 7 (SIM_SCGC7)............................................................................256
12.2.13 System Clock Divider Register 1 (SIM_CLKDIV1)...................................................................................256
12.2.14 Flash Configuration Register 1 (SIM_FCFG1)........................................................................................... 259
KV31F Sub-Family Reference Manual , Rev. 4, 02/2016
10 Freescale Semiconductor, Inc.
Section number Title Page
12.2.15 Flash Configuration Register 2 (SIM_FCFG2)........................................................................................... 261
12.2.16 Unique Identification Register High (SIM_UIDH)..................................................................................... 261
12.2.17 Unique Identification Register Mid-High (SIM_UIDMH)..........................................................................262
12.2.18 Unique Identification Register Mid Low (SIM_UIDML)........................................................................... 262
12.2.19 Unique Identification Register Low (SIM_UIDL)...................................................................................... 263
12.3 Functional description...................................................................................................................................................263
Chapter 13
Kinetis Flashloader
13.1 Chip-Specific Information............................................................................................................................................ 265
13.2 Introduction...................................................................................................................................................................265
13.3 Functional Description..................................................................................................................................................267
13.3.1 Memory Maps..............................................................................................................................................267
13.3.2 Start-up Process............................................................................................................................................267
13.3.3 Clock Configuration.....................................................................................................................................268
13.3.4 Flashloader Protocol.................................................................................................................................... 268
13.3.5 Flashloader Packet Types.............................................................................................................................273
13.3.6 Flashloader Command API..........................................................................................................................280
13.4 Peripherals Supported................................................................................................................................................... 299
13.4.1 I2C Peripheral.............................................................................................................................................. 299
13.4.2 SPI Peripheral.............................................................................................................................................. 301
13.4.3 UART Peripheral......................................................................................................................................... 303
13.5 Get/SetProperty Command Properties..........................................................................................................................306
13.5.1 Property Definitions.....................................................................................................................................307
13.6 Kinetis Flashloader Status Error Codes........................................................................................................................ 309
Chapter 14
Reset Control Module (RCM)
14.1 Introduction...................................................................................................................................................................311
14.2 Reset memory map and register descriptions............................................................................................................... 311
14.2.1 System Reset Status Register 0 (RCM_SRS0)............................................................................................ 312
KV31F Sub-Family Reference Manual , Rev. 4, 02/2016
Freescale Semiconductor, Inc. 11
Section number Title Page
14.2.2 System Reset Status Register 1 (RCM_SRS1)............................................................................................ 313
14.2.3 Reset Pin Filter Control register (RCM_RPFC).......................................................................................... 315
14.2.4 Reset Pin Filter Width register (RCM_RPFW)........................................................................................... 316
14.2.5 Mode Register (RCM_MR)......................................................................................................................... 317
14.2.6 Sticky System Reset Status Register 0 (RCM_SSRS0)...............................................................................318
14.2.7 Sticky System Reset Status Register 1 (RCM_SSRS1)...............................................................................319
Chapter 15
System Mode Controller (SMC)
15.1 Introduction...................................................................................................................................................................321
15.2 Modes of operation....................................................................................................................................................... 321
15.3 Memory map and register descriptions.........................................................................................................................323
15.3.1 Power Mode Protection register (SMC_PMPROT).....................................................................................324
15.3.2 Power Mode Control register (SMC_PMCTRL).........................................................................................325
15.3.3 Stop Control Register (SMC_STOPCTRL).................................................................................................327
15.3.4 Power Mode Status register (SMC_PMSTAT)........................................................................................... 328
15.4 Functional description...................................................................................................................................................329
15.4.1 Power mode transitions................................................................................................................................329
15.4.2 Power mode entry/exit sequencing.............................................................................................................. 332
15.4.3 Run modes....................................................................................................................................................334
15.4.4 Wait modes.................................................................................................................................................. 336
15.4.5 Stop modes...................................................................................................................................................337
15.4.6 Debug in low power modes......................................................................................................................... 340
Chapter 16
Power Management Controller (PMC)
16.1 Introduction...................................................................................................................................................................343
16.2 Features.........................................................................................................................................................................343
16.3 Low-voltage detect (LVD) system................................................................................................................................343
16.3.1 LVD reset operation.....................................................................................................................................344
16.3.2 LVD interrupt operation...............................................................................................................................344
KV31F Sub-Family Reference Manual , Rev. 4, 02/2016
12 Freescale Semiconductor, Inc.
Section number Title Page
16.3.3 Low-voltage warning (LVW) interrupt operation....................................................................................... 344
16.4 I/O retention..................................................................................................................................................................345
16.5 Memory map and register descriptions.........................................................................................................................345
16.5.1 Low Voltage Detect Status And Control 1 register (PMC_LVDSC1)........................................................ 346
16.5.2 Low Voltage Detect Status And Control 2 register (PMC_LVDSC2)........................................................ 347
16.5.3 Regulator Status And Control register (PMC_REGSC)..............................................................................348
Chapter 17
Low-Leakage Wakeup Unit (LLWU)
17.1 Introduction...................................................................................................................................................................351
17.1.1 Features........................................................................................................................................................ 351
17.1.2 Modes of operation...................................................................................................................................... 352
17.1.3 Block diagram..............................................................................................................................................353
17.2 LLWU signal descriptions............................................................................................................................................ 354
17.3 Memory map/register definition................................................................................................................................... 354
17.3.1 LLWU Pin Enable 1 register (LLWU_PE1)................................................................................................355
17.3.2 LLWU Pin Enable 2 register (LLWU_PE2)................................................................................................356
17.3.3 LLWU Pin Enable 3 register (LLWU_PE3)................................................................................................357
17.3.4 LLWU Pin Enable 4 register (LLWU_PE4)................................................................................................358
17.3.5 LLWU Module Enable register (LLWU_ME)............................................................................................ 359
17.3.6 LLWU Flag 1 register (LLWU_F1).............................................................................................................361
17.3.7 LLWU Flag 2 register (LLWU_F2).............................................................................................................363
17.3.8 LLWU Flag 3 register (LLWU_F3).............................................................................................................364
17.3.9 LLWU Pin Filter 1 register (LLWU_FILT1).............................................................................................. 366
17.3.10 LLWU Pin Filter 2 register (LLWU_FILT2).............................................................................................. 367
17.4 Functional description...................................................................................................................................................368
17.4.1 LLS mode.....................................................................................................................................................369
17.4.2 VLLS modes................................................................................................................................................ 369
17.4.3 Initialization................................................................................................................................................. 369
Chapter 18
KV31F Sub-Family Reference Manual , Rev. 4, 02/2016
Freescale Semiconductor, Inc. 13
Section number Title Page
Miscellaneous Control Module (MCM)
18.1 Introduction...................................................................................................................................................................371
18.1.1 Features........................................................................................................................................................ 371
18.2 Memory map/register descriptions............................................................................................................................... 371
18.2.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)................................................................372
18.2.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC)............................................................ 372
18.2.3 Crossbar Switch (AXBS) Control Register (MCM_PLACR)..................................................................... 373
18.2.4 Interrupt Status and Control Register (MCM_ISCR).................................................................................. 373
18.2.5 Compute Operation Control Register (MCM_CPO)................................................................................... 376
18.3 Functional description...................................................................................................................................................377
18.3.1 Interrupts...................................................................................................................................................... 377
Chapter 19
Crossbar Switch Lite (AXBS-Lite)
19.1 Introduction...................................................................................................................................................................379
19.1.1 Features........................................................................................................................................................ 379
19.2 Memory Map / Register Definition...............................................................................................................................380
19.3 Functional Description..................................................................................................................................................380
19.3.1 General operation.........................................................................................................................................380
19.3.2 Arbitration....................................................................................................................................................381
19.4 Initialization/application information........................................................................................................................... 382
Chapter 20
Peripheral Bridge (AIPS-Lite)
20.1 Introduction...................................................................................................................................................................383
20.1.1 Features........................................................................................................................................................ 383
20.1.2 General operation.........................................................................................................................................383
20.2 Memory map/register definition................................................................................................................................... 384
20.3 Functional description...................................................................................................................................................384
20.3.1 Access support............................................................................................................................................. 384
Chapter 21
Direct Memory Access Multiplexer (DMAMUX)
KV31F Sub-Family Reference Manual , Rev. 4, 02/2016
14 Freescale Semiconductor, Inc.
Section number Title Page
21.1 Introduction...................................................................................................................................................................385
21.1.1 Overview......................................................................................................................................................385
21.1.2 Features........................................................................................................................................................ 386
21.1.3 Modes of operation...................................................................................................................................... 386
21.2 External signal description............................................................................................................................................387
21.3 Memory map/register definition................................................................................................................................... 387
21.3.1 Channel Configuration register (DMAMUX_CHCFGn)............................................................................ 388
21.4 Functional description...................................................................................................................................................389
21.4.1 DMA channels with periodic triggering capability......................................................................................389
21.4.2 DMA channels with no triggering capability...............................................................................................391
21.4.3 Always-enabled DMA sources.................................................................................................................... 392
21.5 Initialization/application information........................................................................................................................... 393
21.5.1 Reset.............................................................................................................................................................393
21.5.2 Enabling and configuring sources................................................................................................................393
Chapter 22
Enhanced Direct Memory Access (eDMA)
22.1 Introduction...................................................................................................................................................................397
22.1.1 eDMA system block diagram...................................................................................................................... 397
22.1.2 Block parts................................................................................................................................................... 398
22.1.3 Features........................................................................................................................................................ 399
22.2 Modes of operation....................................................................................................................................................... 400
22.3 Memory map/register definition................................................................................................................................... 401
22.3.1 TCD memory............................................................................................................................................... 401
22.3.2 TCD initialization........................................................................................................................................ 401
22.3.3 TCD structure...............................................................................................................................................401
22.3.4 Reserved memory and bit fields...................................................................................................................402
22.3.1 Control Register (DMA_CR).......................................................................................................................413
22.3.2 Error Status Register (DMA_ES)................................................................................................................ 416
22.3.3 Enable Request Register (DMA_ERQ)....................................................................................................... 418
KV31F Sub-Family Reference Manual , Rev. 4, 02/2016
Freescale Semiconductor, Inc. 15
Section number Title Page
22.3.4 Enable Error Interrupt Register (DMA_EEI)...............................................................................................420
22.3.5 Clear Enable Error Interrupt Register (DMA_CEEI).................................................................................. 422
22.3.6 Set Enable Error Interrupt Register (DMA_SEEI)...................................................................................... 423
22.3.7 Clear Enable Request Register (DMA_CERQ)...........................................................................................424
22.3.8 Set Enable Request Register (DMA_SERQ)...............................................................................................425
22.3.9 Clear DONE Status Bit Register (DMA_CDNE)........................................................................................426
22.3.10 Set START Bit Register (DMA_SSRT)...................................................................................................... 427
22.3.11 Clear Error Register (DMA_CERR)............................................................................................................428
22.3.12 Clear Interrupt Request Register (DMA_CINT)......................................................................................... 429
22.3.13 Interrupt Request Register (DMA_INT)......................................................................................................430
22.3.14 Error Register (DMA_ERR)........................................................................................................................ 432
22.3.15 Hardware Request Status Register (DMA_HRS)........................................................................................ 435
22.3.16 Enable Asynchronous Request in Stop Register (DMA_EARS).................................................................438
22.3.17 Channel n Priority Register (DMA_DCHPRIn).......................................................................................... 440
22.3.18 TCD Source Address (DMA_TCDn_SADDR)...........................................................................................441
22.3.19 TCD Signed Source Address Offset (DMA_TCDn_SOFF)........................................................................441
22.3.20 TCD Transfer Attributes (DMA_TCDn_ATTR).........................................................................................442
22.3.21 TCD Minor Byte Count (Minor Loop Mapping Disabled) (DMA_TCDn_NBYTES_MLNO)................. 443
22.3.22 TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
(DMA_TCDn_NBYTES_MLOFFNO).......................................................................................................444
22.3.23 TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)
(DMA_TCDn_NBYTES_MLOFFYES)..................................................................................................... 445
22.3.24 TCD Last Source Address Adjustment (DMA_TCDn_SLAST).................................................................446
22.3.25 TCD Destination Address (DMA_TCDn_DADDR)...................................................................................447
22.3.26 TCD Signed Destination Address Offset (DMA_TCDn_DOFF)................................................................447
22.3.27 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
(DMA_TCDn_CITER_ELINKYES)...........................................................................................................448
22.3.28 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
(DMA_TCDn_CITER_ELINKNO)............................................................................................................ 449
22.3.29 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCDn_DLASTSGA).......... 450
KV31F Sub-Family Reference Manual , Rev. 4, 02/2016
16 Freescale Semiconductor, Inc.
Section number Title Page
22.3.30 TCD Control and Status (DMA_TCDn_CSR)............................................................................................ 451
22.3.31 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
(DMA_TCDn_BITER_ELINKYES)...........................................................................................................453
22.3.32 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
(DMA_TCDn_BITER_ELINKNO)............................................................................................................ 454
22.4 Functional description...................................................................................................................................................455
22.4.1 eDMA basic data flow................................................................................................................................. 455
22.4.2 Fault reporting and handling........................................................................................................................458
22.4.3 Channel preemption..................................................................................................................................... 461
22.4.4 Performance................................................................................................................................................. 461
22.5 Initialization/application information........................................................................................................................... 465
22.5.1 eDMA initialization..................................................................................................................................... 465
22.5.2 Programming errors..................................................................................................................................... 467
22.5.3 Arbitration mode considerations..................................................................................................................468
22.5.4 Performing DMA transfers.......................................................................................................................... 468
22.5.5 Monitoring transfer descriptor status........................................................................................................... 472
22.5.6 Channel Linking...........................................................................................................................................474
22.5.7 Dynamic programming................................................................................................................................ 475
Chapter 23
External Watchdog Monitor (EWM)
23.1 Introduction...................................................................................................................................................................481
23.1.1 Features........................................................................................................................................................ 481
23.1.2 Modes of Operation..................................................................................................................................... 482
23.1.3 Block Diagram............................................................................................................................................. 483
23.2 EWM Signal Descriptions............................................................................................................................................ 484
23.3 Memory Map/Register Definition.................................................................................................................................484
23.3.1 Control Register (EWM_CTRL)................................................................................................................. 484
23.3.2 Service Register (EWM_SERV)..................................................................................................................485
23.3.3 Compare Low Register (EWM_CMPL)......................................................................................................485
23.3.4 Compare High Register (EWM_CMPH).....................................................................................................486
KV31F Sub-Family Reference Manual , Rev. 4, 02/2016
Freescale Semiconductor, Inc. 17
Section number Title Page
23.3.5 Clock Prescaler Register (EWM_CLKPRESCALER)................................................................................487
23.4 Functional Description..................................................................................................................................................487
23.4.1 The EWM_out Signal.................................................................................................................................. 487
23.4.2 The EWM_in Signal.................................................................................................................................... 488
23.4.3 EWM Counter..............................................................................................................................................489
23.4.4 EWM Compare Registers............................................................................................................................ 489
23.4.5 EWM Refresh Mechanism...........................................................................................................................489
23.4.6 EWM Interrupt.............................................................................................................................................490
23.4.7 Counter clock prescaler................................................................................................................................490
Chapter 24
Watchdog Timer (WDOG)
24.1 Introduction...................................................................................................................................................................491
24.2 Features.........................................................................................................................................................................491
24.3 Functional overview......................................................................................................................................................492
24.3.1 Unlocking and updating the watchdog.........................................................................................................494
24.3.2 Watchdog configuration time (WCT)..........................................................................................................495
24.3.3 Refreshing the watchdog..............................................................................................................................496
24.3.4 Windowed mode of operation......................................................................................................................496
24.3.5 Watchdog disabled mode of operation.........................................................................................................496
24.3.6 Debug modes of operation........................................................................................................................... 496
24.4 Testing the watchdog.................................................................................................................................................... 497
24.4.1 Quick test..................................................................................................................................................... 498
24.4.2 Byte test........................................................................................................................................................498
24.5 Backup reset generator..................................................................................................................................................499
24.6 Generated resets and interrupts.....................................................................................................................................500
24.7 Memory map and register definition.............................................................................................................................500
24.7.1 Watchdog Status and Control Register High (WDOG_STCTRLH)........................................................... 501
24.7.2 Watchdog Status and Control Register Low (WDOG_STCTRLL)............................................................ 503
24.7.3 Watchdog Time-out Value Register High (WDOG_TOVALH).................................................................503
KV31F Sub-Family Reference Manual , Rev. 4, 02/2016
18 Freescale Semiconductor, Inc.
Section number Title Page
24.7.4 Watchdog Time-out Value Register Low (WDOG_TOVALL)..................................................................504
24.7.5 Watchdog Window Register High (WDOG_WINH).................................................................................. 504
24.7.6 Watchdog Window Register Low (WDOG_WINL)................................................................................... 505
24.7.7 Watchdog Refresh register (WDOG_REFRESH)....................................................................................... 505
24.7.8 Watchdog Unlock register (WDOG_UNLOCK).........................................................................................505
24.7.9 Watchdog Timer Output Register High (WDOG_TMROUTH)................................................................. 506
24.7.10 Watchdog Timer Output Register Low (WDOG_TMROUTL).................................................................. 506
24.7.11 Watchdog Reset Count register (WDOG_RSTCNT).................................................................................. 507
24.7.12 Watchdog Prescaler register (WDOG_PRESC).......................................................................................... 507
24.8 Watchdog operation with 8-bit access.......................................................................................................................... 507
24.8.1 General guideline......................................................................................................................................... 507
24.8.2 Refresh and unlock operations with 8-bit access.........................................................................................508
24.9 Restrictions on watchdog operation..............................................................................................................................509
Chapter 25
Multipurpose Clock Generator (MCG)
25.1 Introduction...................................................................................................................................................................511
25.1.1 Features........................................................................................................................................................ 511
25.1.2 Modes of Operation..................................................................................................................................... 515
25.2 External Signal Description.......................................................................................................................................... 515
25.3 Memory Map/Register Definition.................................................................................................................................515
25.3.1 MCG Control 1 Register (MCG_C1)...........................................................................................................516
25.3.2 MCG Control 2 Register (MCG_C2)...........................................................................................................517
25.3.3 MCG Control 3 Register (MCG_C3)...........................................................................................................518
25.3.4 MCG Control 4 Register (MCG_C4)...........................................................................................................519
25.3.5 MCG Control 5 Register (MCG_C5)...........................................................................................................520
25.3.6 MCG Control 6 Register (MCG_C6)...........................................................................................................521
25.3.7 MCG Status Register (MCG_S).................................................................................................................. 523
25.3.8 MCG Status and Control Register (MCG_SC)............................................................................................524
25.3.9 MCG Auto Trim Compare Value High Register (MCG_ATCVH)............................................................ 526
KV31F Sub-Family Reference Manual , Rev. 4, 02/2016
Freescale Semiconductor, Inc. 19
Section number Title Page
25.3.10 MCG Auto Trim Compare Value Low Register (MCG_ATCVL)..............................................................526
25.3.11 MCG Control 7 Register (MCG_C7)...........................................................................................................526
25.3.12 MCG Control 8 Register (MCG_C8)...........................................................................................................527
25.3.13 MCG Control 12 Register (MCG_C12).......................................................................................................528
25.3.13 MCG Status 2 Register (MCG_S2)............................................................................................................. 528
25.3.13 MCG Test 3 Register (MCG_T3)................................................................................................................ 529
25.4 Functional description...................................................................................................................................................529
25.4.1 MCG mode state diagram............................................................................................................................ 529
25.4.2 Low-power bit usage....................................................................................................................................533
25.4.3 MCG Internal Reference Clocks..................................................................................................................533
25.4.4 External Reference Clock............................................................................................................................ 534
25.4.5 MCG Fixed Frequency Clock .....................................................................................................................535
25.4.6 MCG PLL clock ..........................................................................................................................................535
25.4.7 MCG Auto TRIM (ATM)............................................................................................................................535
25.5 Initialization / Application information........................................................................................................................ 536
25.5.1 MCG module initialization sequence...........................................................................................................536
25.5.2 Using a 32.768 kHz reference......................................................................................................................539
25.5.3 MCG mode switching.................................................................................................................................. 539
Chapter 26
Oscillator (OSC)
26.1 Introduction...................................................................................................................................................................549
26.2 Features and Modes...................................................................................................................................................... 549
26.3 Block Diagram..............................................................................................................................................................550
26.4 OSC Signal Descriptions.............................................................................................................................................. 550
26.5 External Crystal / Resonator Connections.................................................................................................................... 551
26.6 External Clock Connections......................................................................................................................................... 552
26.7 Memory Map/Register Definitions...............................................................................................................................553
26.7.1 OSC Memory Map/Register Definition.......................................................................................................553
26.8 Functional Description..................................................................................................................................................555
KV31F Sub-Family Reference Manual , Rev. 4, 02/2016
20 Freescale Semiconductor, Inc.
Section number Title Page
26.8.1 OSC module states.......................................................................................................................................555
26.8.2 OSC module modes..................................................................................................................................... 557
26.8.3 Counter.........................................................................................................................................................559
26.8.4 Reference clock pin requirements................................................................................................................559
26.9 Reset..............................................................................................................................................................................559
26.10 Low power modes operation.........................................................................................................................................560
26.11 Interrupts.......................................................................................................................................................................560
Chapter 27
Flash Memory Controller (FMC)
27.1 Introduction...................................................................................................................................................................561
27.1.1 Overview......................................................................................................................................................561
27.1.2 Features........................................................................................................................................................ 561
27.2 Modes of operation....................................................................................................................................................... 562
27.3 External signal description............................................................................................................................................562
27.4 Memory map and register descriptions.........................................................................................................................562
27.4.1 Flash Access Protection Register (FMC_PFAPR).......................................................................................568
27.4.2 Flash Bank 0 Control Register (FMC_PFB0CR)........................................................................................ 570
27.4.3 Flash Bank 1 Control Register (FMC_PFB1CR)........................................................................................ 573
27.4.4 Cache Tag Storage (FMC_TAGVDW0Sn)................................................................................................. 575
27.4.5 Cache Tag Storage (FMC_TAGVDW1Sn)................................................................................................. 576
27.4.6 Cache Tag Storage (FMC_TAGVDW2Sn)................................................................................................. 577
27.4.7 Cache Tag Storage (FMC_TAGVDW3Sn)................................................................................................. 578
27.4.8 Cache Data Storage (upper word) (FMC_DATAW0SnU)..........................................................................578
27.4.9 Cache Data Storage (lower word) (FMC_DATAW0SnL).......................................................................... 579
27.4.10 Cache Data Storage (upper word) (FMC_DATAW1SnU)..........................................................................579
27.4.11 Cache Data Storage (lower word) (FMC_DATAW1SnL).......................................................................... 580
27.4.12 Cache Data Storage (upper word) (FMC_DATAW2SnU)..........................................................................580
27.4.13 Cache Data Storage (lower word) (FMC_DATAW2SnL).......................................................................... 581
27.4.14 Cache Data Storage (upper word) (FMC_DATAW3SnU)..........................................................................581
KV31F Sub-Family Reference Manual , Rev. 4, 02/2016
Freescale Semiconductor, Inc. 21
Section number Title Page
27.4.15 Cache Data Storage (lower word) (FMC_DATAW3SnL).......................................................................... 582
27.5 Functional description...................................................................................................................................................582
27.5.1 Default configuration................................................................................................................................... 582
27.5.2 Configuration options.................................................................................................................................. 583
27.5.3 Speculative reads..........................................................................................................................................583
27.5.4 Flash Access Control (FAC) Function.........................................................................................................584
27.6 Initialization and application information.....................................................................................................................595
Chapter 28
Flash Memory Module (FTFA)
28.1 Introduction...................................................................................................................................................................597
28.1.1 Features........................................................................................................................................................ 598
28.1.2 Block Diagram............................................................................................................................................. 598
28.1.3 Glossary....................................................................................................................................................... 599
28.2 External Signal Description.......................................................................................................................................... 600
28.3 Memory Map and Registers..........................................................................................................................................601
28.3.1 Flash Configuration Field Description.........................................................................................................601
28.3.2 Program Flash IFR Map...............................................................................................................................601
28.3.3 Register Descriptions................................................................................................................................... 602
28.4 Functional Description..................................................................................................................................................616
28.4.1 Flash Protection............................................................................................................................................616
28.4.2 Flash Access Protection............................................................................................................................... 616
28.4.3 Interrupts...................................................................................................................................................... 618
28.4.4 Flash Operation in Low-Power Modes........................................................................................................ 619
28.4.5 Functional Modes of Operation................................................................................................................... 619
28.4.6 Flash Reads and Ignored Writes.................................................................................................................. 619
28.4.7 Read While Write (RWW)...........................................................................................................................620
28.4.8 Flash Program and Erase..............................................................................................................................620
28.4.9 Flash Command Operations.........................................................................................................................620
28.4.10 Margin Read Commands............................................................................................................................. 626
KV31F Sub-Family Reference Manual , Rev. 4, 02/2016
22 Freescale Semiconductor, Inc.
Section number Title Page
28.4.11 Flash Command Description........................................................................................................................627
28.4.12 Security........................................................................................................................................................ 645
28.4.13 Reset Sequence............................................................................................................................................ 647
Chapter 29
EzPort
29.1 Overview.......................................................................................................................................................................649
29.1.1 Block diagram..............................................................................................................................................649
29.1.2 Features........................................................................................................................................................ 650
29.1.3 Modes of operation...................................................................................................................................... 650
29.2 External signal descriptions.......................................................................................................................................... 651
29.2.1 EzPort Clock (EZP_CK)..............................................................................................................................651
29.2.2 EzPort Chip Select (EZP_CS)......................................................................................................................652
29.2.3 EzPort Serial Data In (EZP_D)....................................................................................................................652
29.2.4 EzPort Serial Data Out (EZP_Q)................................................................................................................. 652
29.3 Command definition..................................................................................................................................................... 652
29.3.1 Command descriptions.................................................................................................................................653
29.4 Flash memory map for EzPort access...........................................................................................................................660
Chapter 30
External Bus Interface (FlexBus)
30.1 Introduction...................................................................................................................................................................661
30.1.1 Definition..................................................................................................................................................... 661
30.1.2 Features........................................................................................................................................................ 661
30.2 Signal descriptions........................................................................................................................................................662
30.3 Memory Map/Register Definition.................................................................................................................................664
30.3.1 Chip Select Address Register (FB_CSARn)................................................................................................665
30.3.2 Chip Select Mask Register (FB_CSMRn)................................................................................................... 666
30.3.3 Chip Select Control Register (FB_CSCRn).................................................................................................667
30.3.4 Chip Select port Multiplexing Control Register (FB_CSPMCR)................................................................670
30.4 Functional description...................................................................................................................................................671
KV31F Sub-Family Reference Manual , Rev. 4, 02/2016
Freescale Semiconductor, Inc. 23
Section number Title Page
30.4.1 Use cases......................................................................................................................................................671
30.4.2 Address comparison.....................................................................................................................................672
30.4.3 Address driven on address bus.....................................................................................................................672
30.4.4 Connecting address/data lines......................................................................................................................672
30.4.5 Bit ordering.................................................................................................................................................. 673
30.4.6 Data transfer signals.....................................................................................................................................673
30.4.7 Signal transitions..........................................................................................................................................673
30.4.8 Data-byte alignment and physical connections............................................................................................673
30.4.9 Address/data bus multiplexing.....................................................................................................................675
30.4.10 Data transfer states.......................................................................................................................................676
30.4.11 FlexBus Timing Examples...........................................................................................................................677
30.4.12 Burst cycles..................................................................................................................................................696
30.4.13 Extended Transfer Start/Address Latch Enable...........................................................................................705
30.4.14 Bus errors..................................................................................................................................................... 706
30.5 Initialization/Application Information..........................................................................................................................707
30.5.1 Initializing a chip-select...............................................................................................................................707
30.5.2 Reconfiguring a chip-select......................................................................................................................... 707
Chapter 31
Cyclic Redundancy Check (CRC)
31.1 Introduction...................................................................................................................................................................709
31.1.1 Features........................................................................................................................................................ 709
31.1.2 Block diagram..............................................................................................................................................709
31.1.3 Modes of operation...................................................................................................................................... 710
31.2 Memory map and register descriptions.........................................................................................................................710
31.2.1 CRC Data register (CRC_DATA)............................................................................................................... 711
31.2.2 CRC Polynomial register (CRC_GPOLY).................................................................................................. 712
31.2.3 CRC Control register (CRC_CTRL)............................................................................................................712
31.3 Functional description...................................................................................................................................................713
31.3.1 CRC initialization/reinitialization................................................................................................................713
KV31F Sub-Family Reference Manual , Rev. 4, 02/2016
24 Freescale Semiconductor, Inc.
Section number Title Page
31.3.2 CRC calculations..........................................................................................................................................714
31.3.3 Transpose feature......................................................................................................................................... 715
31.3.4 CRC result complement...............................................................................................................................717
Chapter 32
Random Number Generator Accelerator (RNGA)
32.1 Introduction...................................................................................................................................................................719
32.1.1 Overview......................................................................................................................................................719
32.2 Modes of operation....................................................................................................................................................... 720
32.2.1 Entering Normal mode.................................................................................................................................720
32.2.2 Entering Sleep mode.................................................................................................................................... 720
32.3 Memory map and register definition.............................................................................................................................721
32.3.1 RNGA Control Register (RNG_CR)........................................................................................................... 721
32.3.2 RNGA Status Register (RNG_SR).............................................................................................................. 723
32.3.3 RNGA Entropy Register (RNG_ER)...........................................................................................................725
32.3.4 RNGA Output Register (RNG_OR)............................................................................................................ 725
32.4 Functional description...................................................................................................................................................726
32.4.1 Output (OR) register.................................................................................................................................... 726
32.4.2 Core engine / control logic...........................................................................................................................726
32.5 Initialization/application information........................................................................................................................... 727
Chapter 33
Analog-to-Digital Converter (ADC)
33.1 Introduction...................................................................................................................................................................729
33.1.1 Features........................................................................................................................................................ 729
33.1.2 Block diagram..............................................................................................................................................730
33.2 ADC signal descriptions............................................................................................................................................... 731
33.2.1 Analog Power (VDDA)............................................................................................................................... 732
33.2.2 Analog Ground (VSSA)...............................................................................................................................732
33.2.3 Voltage Reference Select.............................................................................................................................732
33.2.4 Analog Channel Inputs (ADx)..................................................................................................................... 733
KV31F Sub-Family Reference Manual , Rev. 4, 02/2016
Freescale Semiconductor, Inc. 25
Section number Title Page
33.2.5 Differential Analog Channel Inputs (DADx)...............................................................................................733
33.3 Memory map and register definitions...........................................................................................................................733
33.3.1 ADC Status and Control Registers 1 (ADCx_SC1n)...................................................................................735
33.3.2 ADC Configuration Register 1 (ADCx_CFG1)...........................................................................................739
33.3.3 ADC Configuration Register 2 (ADCx_CFG2)...........................................................................................740
33.3.4 ADC Data Result Register (ADCx_Rn).......................................................................................................741
33.3.5 Compare Value Registers (ADCx_CVn)..................................................................................................... 743
33.3.6 Status and Control Register 2 (ADCx_SC2)................................................................................................744
33.3.7 Status and Control Register 3 (ADCx_SC3)................................................................................................746
33.3.8 ADC Offset Correction Register (ADCx_OFS)...........................................................................................747
33.3.9 ADC Plus-Side Gain Register (ADCx_PG).................................................................................................748
33.3.10 ADC Minus-Side Gain Register (ADCx_MG)............................................................................................ 748
33.3.11 ADC Plus-Side General Calibration Value Register (ADCx_CLPD)......................................................... 749
33.3.12 ADC Plus-Side General Calibration Value Register (ADCx_CLPS)..........................................................750
33.3.13 ADC Plus-Side General Calibration Value Register (ADCx_CLP4).......................................................... 750
33.3.14 ADC Plus-Side General Calibration Value Register (ADCx_CLP3).......................................................... 751
33.3.15 ADC Plus-Side General Calibration Value Register (ADCx_CLP2).......................................................... 751
33.3.16 ADC Plus-Side General Calibration Value Register (ADCx_CLP1).......................................................... 752
33.3.17 ADC Plus-Side General Calibration Value Register (ADCx_CLP0).......................................................... 752
33.3.18 ADC Minus-Side General Calibration Value Register (ADCx_CLMD).....................................................753
33.3.19 ADC Minus-Side General Calibration Value Register (ADCx_CLMS)..................................................... 753
33.3.20 ADC Minus-Side General Calibration Value Register (ADCx_CLM4)..................................................... 754
33.3.21 ADC Minus-Side General Calibration Value Register (ADCx_CLM3)..................................................... 754
33.3.22 ADC Minus-Side General Calibration Value Register (ADCx_CLM2)..................................................... 755
33.3.23 ADC Minus-Side General Calibration Value Register (ADCx_CLM1)..................................................... 755
33.3.24 ADC Minus-Side General Calibration Value Register (ADCx_CLM0)..................................................... 756
33.4 Functional description...................................................................................................................................................756
33.4.1 Clock select and divide control....................................................................................................................757
33.4.2 Hardware trigger and channel selects.......................................................................................................... 758
KV31F Sub-Family Reference Manual , Rev. 4, 02/2016
26 Freescale Semiconductor, Inc.
Section number Title Page
33.4.3 Conversion control.......................................................................................................................................759
33.4.4 Automatic compare function........................................................................................................................766
33.4.5 Calibration function..................................................................................................................................... 768
33.4.6 User-defined offset function........................................................................................................................ 769
33.4.7 Temperature sensor......................................................................................................................................770
33.4.8 MCU wait mode operation...........................................................................................................................771
33.4.9 MCU Normal Stop mode operation.............................................................................................................772
33.4.10 MCU Low-Power Stop mode operation...................................................................................................... 773
33.5 Initialization information.............................................................................................................................................. 773
33.5.1 ADC module initialization example............................................................................................................ 773
33.6 Application information................................................................................................................................................775
33.6.1 External pins and routing............................................................................................................................. 775
33.6.2 Sources of error............................................................................................................................................777
Chapter 34
Comparator (CMP)
34.1 Introduction...................................................................................................................................................................783
34.1.1 CMP features................................................................................................................................................783
34.1.2 6-bit DAC key features................................................................................................................................ 784
34.1.3 ANMUX key features.................................................................................................................................. 784
34.1.4 CMP, DAC and ANMUX diagram..............................................................................................................785
34.1.5 CMP block diagram..................................................................................................................................... 786
34.2 Memory map/register definitions..................................................................................................................................788
34.2.1 CMP Control Register 0 (CMPx_CR0)....................................................................................................... 788
34.2.2 CMP Control Register 1 (CMPx_CR1)....................................................................................................... 789
34.2.3 CMP Filter Period Register (CMPx_FPR)...................................................................................................791
34.2.4 CMP Status and Control Register (CMPx_SCR).........................................................................................791
34.2.5 DAC Control Register (CMPx_DACCR)....................................................................................................792
34.2.6 MUX Control Register (CMPx_MUXCR).................................................................................................. 793
34.3 Functional description...................................................................................................................................................794
KV31F Sub-Family Reference Manual , Rev. 4, 02/2016
Freescale Semiconductor, Inc. 27
Section number Title Page
34.3.1 CMP functional modes.................................................................................................................................794
34.3.2 Power modes................................................................................................................................................803
34.3.3 Startup and operation................................................................................................................................... 804
34.3.4 Low-pass filter............................................................................................................................................. 805
34.4 CMP interrupts..............................................................................................................................................................807
34.5 DMA support................................................................................................................................................................ 807
34.6 CMP Asynchronous DMA support...............................................................................................................................808
34.7 Digital-to-analog converter...........................................................................................................................................809
34.8 DAC functional description.......................................................................................................................................... 809
34.8.1 Voltage reference source select....................................................................................................................809
34.9 DAC resets....................................................................................................................................................................810
34.10 DAC clocks...................................................................................................................................................................810
34.11 DAC interrupts..............................................................................................................................................................810
Chapter 35
12-bit Digital-to-Analog Converter (DAC)
35.1 Introduction...................................................................................................................................................................811
35.2 Features.........................................................................................................................................................................811
35.3 Block diagram...............................................................................................................................................................811
35.4 Memory map/register definition................................................................................................................................... 812
35.4.1 DAC Data Low Register (DACx_DATnL)................................................................................................. 815
35.4.2 DAC Data High Register (DACx_DATnH)................................................................................................ 815
35.4.3 DAC Status Register (DACx_SR)............................................................................................................... 816
35.4.4 DAC Control Register (DACx_C0)............................................................................................................. 817
35.4.5 DAC Control Register 1 (DACx_C1).......................................................................................................... 818
35.4.6 DAC Control Register 2 (DACx_C2).......................................................................................................... 819
35.5 Functional description...................................................................................................................................................819
35.5.1 DAC data buffer operation...........................................................................................................................819
35.5.2 DMA operation............................................................................................................................................ 821
35.5.3 Resets........................................................................................................................................................... 821
KV31F Sub-Family Reference Manual , Rev. 4, 02/2016
28 Freescale Semiconductor, Inc.