AD8522ARZ - ANALOG DEVICES - Datasheet.Directory

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FUNCTIONAL BLOCK DIAGRAM

REV. A

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

+5 Volt, Serial Input,

Dual 12-Bit DAC

CLK

SDI

(DATA)

SDO

LDA

LDB

DGND MSB RS AGND

REF

BUF

BANDGAP

REFERENCE

AMP

DAC A

AMP

AD8522

DAC A

DAC B

OUTA

REF

OUTB

CONTROL

LOGIC

CLK

LATCH

REF

BUF

DAC B

SHIFT

inputs. A serial data output allows the user to easily daisy-chain

multiple devices in conjunction with a chip select input. A reset

RS input sets the outputs to zero scale or midscale, as deter-

mined by the input MSB.

The output 4.095 V full scale is laser trimmed to maintain accu-

racy over the operating temperature range of the device, and

gives the user an easy-to-use one-millivolt-per-bit resolution. A

2.5 V reference output is also available externally for other data

acquisition circuitry, and for ratiometric applications. The out-

put buffers are capable of driving ±5 mA.

The AD8522 is available in the 14-pin plastic DIP and low pro-

file 1.5 mm SOIC-14 packages.

GENERAL DESCRIPTION

The AD8522 is a complete dual 12-bit, single-supply, voltage

output DAC in a 14-pin DIP, or SO-14 surface mount package.

Fabricated in a CBCMOS process, features include a serial digi-

tal interface, onboard reference, and buffered voltage output.

Ideal for +5 V-only systems, this monolithic device offers low

cost and ease of use, and requires no external components to

realize the full performance of the device.

The serial digital interface allows interfacing directly to numer-

ous microcontroller ports, with a simple high speed, three-wire

data, clock, and load strobe format. The 16-bit serial word con-

tains the 12-bit data word and DAC select address, which is de-

coded internally or can be decoded externally using LDA, LDB

0.6

0.4

0.2

–1.0

–0.6

–0.8

–0.2

–0.4

40960 30721024 2048

DIGITAL INPUT CODE – Decimal

LINEARITY ERROR – LSB

= +4.5V

= –55°C, +25°C, +85°C, +125°C

+85°C

+125°C

+25°C

–55°C

PACKAGE TYPES AVAILABLE

AD8522

FEATURES

Complete Dual 12-Bit DAC

No External Components

+5 V Single-Supply Operation 610%

4.095 V Full Scale (1 mV/LSB)

Buffered Voltage Outputs

Low Power: 5 mW/DAC

Space Saving 1.5 mm Height SO-14 Package

APPLICATIONS

Digitally Controlled Calibration

Servo Controls

Process Control Equipment

Computer Peripherals

Portable Instrumentation

Cellular Base Stations Voltage Adjustment

Figure 1. Linearity Error vs. Digital Code & Temperature

PDIP-14

SO-14

AD8522–SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

Parameter Symbol Condition Min Typ Max Units

STATIC PERFORMANCE

Resolution

N 12 Bits

Relative Accuracy INL -1.5 ±0.5 +1.5 LSB

Differential Nonlinearity DNL Monotonic -1 ±0.5 +1 LSB

Zero-Scale Error V

ZSE

Data = 000

+0.5 +3 mV

Full-Scale Voltage

Data = FFF

4.079 4.095 4.111 Volts

Full-Scale Tempco

2, 3

TCV

±15 ppm/°C

MATCHING PERFORMANCE

Linearity Matching Error ∆V

A/B ±1 LSB

ANALOG OUTPUT

Output Current I

OUT

Data = 800

, ∆V

OUT

≤ 3 LSB ±5mA

Load Regulation at Half-Scale LD

REG

= 402 Ω to ∞, Data = 800

1 3 LSB

Capacitive Load

No Oscillation 500 pF

REFERENCE OUTPUT

Output Voltage V

REF

2.484 2.500 2.516 V

Output Source Current

REF

∆V

REF

< 18 mV 5 mA

Line Rejection LN

REJ

0.025 0.08 %/V

Load Regulation LD

REG

REF

= 0 to 5 mA, Data = 800

0.025 0.1 %/mA

LOGIC INPUTS & OUTPUTS

Logic Input Low Voltage V

0.8 V

Logic Input High Voltage V

2.4 V

Input Leakage Current I

10 µA

Input Capacitance

10 pF

Logic Output Voltage Low V

= 1.6 mA 0.4 V

Logic Output Voltage High V

= 400 µA 3.5 V

TIMING SPECIFICATIONS

3, 5

Clock Width High t

35 ns

Clock Width Low t

35 ns

Load Pulse Width t

LDW

25 ns

Data Setup t

10 ns

Data Hold t

20 ns

Clear Pulse Width t

CLRW

20 ns

Load Setup t

LD1

10 ns

Load Hold t

LD2

10 ns

Select t

CSS

30 ns

Deselect t

CSH

30 ns

Clock to SDO Propagation Delay t

20 45 80 ns

AC CHARACTERISTICS

3, 5

Voltage Output Settling Time

To ±1 LSB of Final Value 16 µs

Crosstalk C

Signal Measured at DAC Output,

While Changing Opposite LDA/B38 dB

DAC Glitch Q Half-Scale Transition 13 nV s

Digital Feedthrough D

Signal Measured at DAC Output,

While Changing Data Without LDA/B2 nV s

SUPPLY CHARACTERISTICS

Positive Supply Current I

= 5.5 V, V

= 2.4 V or V

= 0.8 V 3 5 mA

= 5 V, V

= 0 V 1 2 mA

Power Dissipation

DISS

= 5 V, V

= 2.4 V or V

= 0.8 V 15 25 mW

= 5 V, V

= 0 V 5 10 mW

Power Supply Sensitivity PSS ∆V

= ±5% 0.002 0.004 %/%

NOTES

1 LSB = 1 mV for 0 V to +4.095 V output range.

Includes internal voltage reference error.

These parameters are guaranteed by design and not subject to production testing.

Very little sink current is available at the V

REF

pin. Use external buffer if setting up a virtual ground.

All input control signals are specified with t

= t

= 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.

The settling time specification does not apply for negative going transitions within the last 6 LSBs of ground. Some devices exhibit double the typical settling time in this 6 LSB region.

Power Dissipation is calculated I

× 5 V.

Specifications subject to change without notice.

(@ VDD = +5.0 V 6 10%, RL = No Load, –408C ≤ TA ≤ +858C, both DACs tested, unless

otherwise noted)

REV. A

–2–

AD8522

REV. A –3–

SERIAL INPUT REGISTER DATA FORMAT

Last First

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15

DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 NC A B Sf/Hd

Table I. Truth Table

Data Word Ext Pins

Sf/Hd BALDA LDB DAC Register

Hardware Load:

LXX↓↓Loads DACA + DACB with Data from SR

LXX↓H Loads DACA with Data from SR

L XXH↓Loads DACB with Data from SR

L X X H H No Load

Software Decode Load:

H L L X X No Load

HHL↓↓Loads DACB with Data from SR, See Note 1 Below

H H L H H No Load

HLH↓↓Loads DACA with Data from SR, See Note 1 Below

H L H H H No Load

HHH↓↓Loads DACA + DACB with Data from SR, See 1 Note Below

H H H H H No Load

NOTES

In software mode LDA and LDB perform the same function. They can be tied together or the unused pin should be tied high.

External Pins LDA and LDB should always be high when shifting Data into the shift register.

↓ symbol denotes negative transition.

200µA

1.6 VOLT

SDO

1.6mA

Figure 3. AC Timing SDO Pin Load Circuit

CLK

SDI

CSS

LD1

LD2

CSH

SDI

CLK

LDW

CLRW

±1 LSB

ERROR BAND

LD2

DB11 DB10

Sf/Hd DB4 DB3 DB2 DB1 DB0

OUT

LDW

SDO

Figure 2. Timing Diagram

AD8522

–4– REV. A

ABSOLUTE MAXIMUM RATINGS*

to DGND & AGND . . . . . . . . . . . . . . . . . . . –0.3 V, +7 V

Logic Inputs and Output to DGND . . . . .–0.3 V, V

+ 0.3 V

OUT

to AGND . . . . . . . . . . . . . . . . . . . . .–0.3 V, V

+ 0.3 V

REF

to AGND . . . . . . . . . . . . . . . . . . . . .–0.3 V, V

+ 0.3 V

AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V

OUT

Short Circuit to GND or V

. . . . . . . . . . . . . . . . 50 mA

Package Power Dissipation . . . . . . . . . . . . . . .(T

max–T

)/θ

Thermal Resistance, θ

14-Pin Plastic DIP Package (N-14) . . . . . . . . . . . . . 83°C/W

14-Lead SOIC Package (SO-14) . . . . . . . . . . . . . . 120°C/W

Maximum Junction Temperature (T

max) . . . . . . . . . . 150°C

Operating Temperature Range . . . . . . . . . . . . .–40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . .–65°C to +150°C

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +300°C

*Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated in the

operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

ORDERING GUIDE

Temperature Package Package

Model Range Description Option

AD8522AN –40°C to +85°C 14-Pin P-DIP N-14

AD8522AR –40°C to +85°C 14-Lead SOIC SO-14

The AD8522 contains 1482 transistors.

PIN CONFIGURATION

14-Pin Plastic DIP 14-Lead SO-14

OUTA

AGND

OUTB

REF

CLK

SDI

SDO

LDA

LDB

DGND

MSB

AD8522

(Not To Scale)

Table II. Truth Tables

DAC Register Preset

RS MSB Register Activity

0 0 Asynchronously Resets DAC Registers to Zero

Scale

0 1 Asynchronously Presets DAC Registers to

Half Scale (800

)

1 X None

Shift Register

CS CLK Shift Register

1 X No Effect

0↑Shifts Register One Bit, SDO Outputs Data

from 16 Clocks Earlier

WARNING!

ESD SENSITIVE DEVICE

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the AD8522 features proprietary ESD protection circuitry, permanent damage may

occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD

precautions are recommended to avoid performance degradation or loss of functionality.

PIN DESCRIPTION

Pin Function

SDI Serial Data Input, input data loads directly into the shift register.

CLK Clock input, positive edge clocks data into shift register.

CS Chip Select, active low input. Prevents shift register loading when high. Does not affect LDA and LDB operation.

LDA/BLoad DAC register strobes, active low. Transfers shift register data to DAC register. See truth table for operation.

Software decode feature only requires one LD strobe. Tie LDA and LDB together or use one of them with the

other pin tied high.

SDO Serial Data Output. Output of shift register, always active.

RS Resets DAC registers to condition determined by MSB pin. Active low input.

MSB Digital input: High presets DAC registers to half scale (800

); Low clears all registers to zero (000

), when RS is

strobed to active low.

Positive +5 V power supply input. Tolerance ±10%.

AGND Analog Ground Input.

DGND Digital Ground Input.

REF

Reference Voltage Output, 2.5 V nominal.

OUT A/B

DAC A/B voltage outputs, 4.095 V full scale, ±5 mA output.

AD8522

REV. A –5–

OPERATION

The AD8522 is a complete ready-to-use dual 12-bit digital-to-

analog converter. Only one +5 V power supply is necessary for

operation. It contains two voltage-switched, 12-bit, laser-

trimmed digital-to-analog converters, a curvature-corrected

bandgap reference, rail-to-rail output op amps, input registers,

and DAC registers. The serial data interface consists of a serial

data input (SDI), clock (CLK), and two load strobe pins (LDA,

LDB) with an active low CS strobe. In addition, an asynchro-

nous RS pin will set all DAC register bits to zero causing the

OUT

to become zero volts, or to midscale for trimming applica-

tions when the MSB pin is programmed to Logic 1. This func-

tion is useful for power on reset or system failure recovery to a

known state.

D/A CONVERTER SECTION

The internal DAC is a 12-bit voltage-mode device with an out-

put that swings from AGND potential to the 2.5 V internal

bandgap voltage. It uses a laser-trimmed R-2R ladder which is

switched by N channel MOSFETs. The output voltage of the

DAC has a constant resistance independent of digital input

code. The DAC output is internally connected to the rail-to-rail

output op amp.

AMPLIFIER SECTION

The internal DAC’s output is buffered by a low power con-

sumption precision amplifier. This low power amplifier contains

a differential PNP pair input stage that provides low offset volt-

age and low noise, as well as the ability to amplify the zero-scale

DAC output voltages. The rail-to-rail amplifier is configured in

a gain of 1.638 (= 4.095 V/2.5 V) in order to set the 4.095 V

full-scale output (1 mV/LSB). See Figure 4 for an equivalent

circuit schematic of the analog section.

BUFFER

SPDT

N CH FET

SWITCHES 2R

RAIL-TO-RAIL

OUTPUT

AMPLIFIER

OUT

BANDGAP

REFERENCE V

REF

2.5V

VOLTAGE SWITCHED 12-BIT

R-2R D/A CONVERTER

= 4.096/2.5

= 1.638V/V

Figure 4. Equivalent AD8522 Schematic of Analog Portion

The op amp has a 16 µs typical settling time to 0.01%. There

are slight differences in settling time for negative slewing signals

versus positive. See the oscilloscope photos in the “Typical Per-

formance Characteristics” section of this data sheet.

OUTPUT SECTION

The rail-to-rail output stage of this amplifier has been designed

to provide precision performance while operating near either

power supply. Figure 5 shows an equivalent output schematic of

the rail-to-rail amplifier with its N channel pull-down FETs that

will pull an output load directly to GND. The output sourcing

current is provided by a P channel pull-up device that can sup-

ply GND terminated loads, especially important at the –10%

supply tolerance value of 4.5 V.

P-CH

N-CH

OUT

AGND

Figure 5. Equivalent Analog Output Circuit

Figures 6 and 7 in the typical performance characteristics sec-

tion provide information on output swing performance near

ground and full scale as a function of load. In addition to resis-

tive load driving capability the amplifier has also been carefully

designed and characterized for up to 500 pF capacitive load

driving capability.

REFERENCE SECTION

The internal 2.5 V curvature-corrected bandgap voltage refer-

ence is laser trimmed for both initial accuracy and low tempera-

ture coefficient. The voltage generated by the reference is

available at the V

REF

pin. Since V

REF

is not intended to drive

heavy external loads, it must be buffered. The equivalent emit-

ter follower output circuit of the V

REF

pin is shown in Figure 4.

Bypassing the V

REF

pin will improve noise performance; how-

ever, bypassing is not required for proper operation. Figure 10

shows broad band noise performance.

POWER SUPPLY

The very low power consumption of the AD8522 is a direct

result of a circuit design optimizing use of a CBCMOS process.

By using the low power characteristics of the CMOS for the

logic, and the low noise, tight matching of the complementary

bipolar transistors good analog accuracy is achieved.

For power consumption sensitive applications it is important to

note that the internal power consumption of the AD8522 is

strongly dependent on the actual in

put voltage levels present on

the SDI, CLK, CS, MSB, LDA, LDB and RS pins. Since these in-

puts are standard CMOS logic structures, they contribute static

power dissipation dependent on the actual driving logic V

and

voltage levels. Consequently for optimum dissipation use of

CMOS logic versus TTL provides minimal dissipation in the static

state. A V

INL

= 0 V on the logic input pins provides the lowest

standby dissipation of 1 mA with a +5 V power supply.

As with any analog system, it is recommended that the AD8522

power supply be bypassed on the same PC card that contains

the chip. Figure 12 shows the power supply rejection versus fre-

quency performance. This should be taken into account when

using higher frequency switched-mode power supplies with

ripple frequencies of 100 kHz and higher.

One advantage of the rail-to-rail output amplifiers used in the

AD8522 is the wide range of usable supply voltage. The part is

fully specified and tested over temperature for operation from

+4.5 V to +5.5 V. If reduced linearity and source current capa-

bility near full scale can be tolerated, operation of the AD8522

AD8522

input register and transferring the 12 bits of data into the de-

coded address determined by the address bits A and B in the se-

rial input register.

Unipolar Output Operation

This is the basic mode of operation for the AD8522. The

AD8522 has been designed to drive loads as low as 820 Ω in

parallel with 500 pF. The code table for this operation is shown

in Table III.

Table III. Unipolar Code Table

Hexadecimal Decimal Analog

Number in Number in Output

DAC Register DAC Register Voltage (V)

FFF 4095 +4.095

801 2049 +2.049

800 2048 +2.048

7FF 2047 +2.047

000 0 0

10 100 100k10k1k

TIED TO AGND

DATA = FFF

= +5V

= +25

TIED TO +5V

DATA = 000

LOAD RESISTANCE – Ω

OUTPUT VOLTAGE – Volts

H = +5V

L = 0V

Figure 6. Output Swing vs. Load

–20

–40

–60

–80

123

OUTPUT VOLTAGE – Volts

OUTPUT CURRENT – mA

DATA = 800

POSITIVE

CURRENT

LIMIT

NEGATIVE

CURRENT

LIMIT

Figure 9. I

OUT

vs. V

OUT

5.2

5.0

4.8

4.6

4.4

4.2

4.0

0.01 0.1 100101.0

OUTPUT LOAD CURRENT – mA

MIN – Volts

∆V

≤ 1 LSB

DATA = FFF

= +25°C

PROPER OPERATION

WHEN V

SUPPLY

VOLTAGE IS ABOVE

CURVE

Figure 7. Minimum Supply Voltage

vs. Load Current

100

200µV/DIV

100µs/DIV

= +25°C

NBW = 1MHz

Figure 10. Broadband Noise

1 10 1000100

100

0.1

0.01

+85°C

–55°C

+25°C

= +5V

DATA = 000

= 5.0V

= 0.0V

OUTPUT SINK CURRENT – µA

OUTPUT PULL-DOWN VOLTAGE – mV

Figure 8. Pull-Down Voltage vs. Out-

put Sink Current Capability

001 3452

= +4.5V

= +5V

= +25°C

SUPPLY CURRENT I

– mA

LOGIC INPUT VOLTAGE V

H – Volts

Figure 11. Supply Current vs. Logic

Input Voltage

Typical Performance Characteristics

is possible down to +4.3 V. The minimum operating supply

voltage versus load current plot, in Figure 7, provides informa-

tion for operation below V

= +4.5 V.

TIMING AND CONTROL

The AD8522 has a 16-bit serial input register that accepts

clocked in data when the CS pin is active low. The DAC regis-

ters are updated by the Load Enable (LDA and LDB) pins.

The AD8522 offers two modes of data loading. The first mode,

hardware-load, directs the data currently clocked into the serial

shift register into either the DAC A or the DAC B register or

both depending on the external active low strobing of the LDA

or LDB pin. Serial data register bit Sf/Hd must be low for this

mode to be in effect.

The second mode of operation is software-load which is de-

signed to minimize the number of control lines connected to

the AD8522. In this mode of operation the LDA and LDB pins

act as one control input taking the present contents of the serial

–6– REV. A

AD8522

REV. A –7–

140

120

100

010 100 1k 10k 100k 1M

FREQUENCY – Hz

POWER SUPPLY REJECTION – dB

= +5V ± 200mV

= +25°C

DATA = FFF

#299, DAC A

H = +5V

L = 0V

Figure 12. Power Supply Rejection

vs. Frequency

0543210–1–2–3–4–5 TOTAL UNADJUSTED ERROR – mV

FREQUENCY

TUE = ∑ (INL+ZS+FS)

SSZ = 300 UNITS

= +4.5V

= +25°C

Figure 15. Total Unadjusted Error

Histogram

100

1.0

0.110 100 100k10k1k

FREQUENCY – Hz

OUTPUT NOISE DENSITY – µV/√Hz

= +5V

DATA = FFF

= +25°C

Figure 18. Output Voltage Noise

Density vs. Frequency

OUT

100mV/

DIV

TIME – 500ns/DIV

100

100mV 500ns

= +25°C

= +5V

2048

TO 2047

Figure 13. Midscale Transition

Performance

4.11

4.105

4.1

4.095

4.09

4.085

4.08

4.075

FULL SCALE VOLTAGE – Volts

–55 –35 –15 5 25 45 65 85 105 125

TEMPERATURE – °C

AVG +1

AVG

AVG –1

= +4.5V

NO LOAD

SSZ = 300 UNITS

Figure 16. Full-Scale Voltage vs.

Temperature

4.095

4.094

4.093

4.092

4.091

4.090

4.089

4.088

4.087

4.086

4.085

4.084

4.096

FULL-SCALE OUTPUT VOLTAGE – Volts

0 100 200 300 400 500 600

HOURS OF OPERATION AT +150°C

AVG +1σ

AVG

AVG –1σ

VDD = +4.5V

SSZ = 135 UNITS

DATA = FFFH

Figure 19. Long Term Drift Acceler-

ated by Burn-In

–SR +SR

OUTPUT INPUT

TIME – 20µs/DIV

100

VOUT

TA = +25°C

VDD = +5V

Figure 14. Large Signal Settling Time

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

ZERO-SCALE VOLTAGE – mV

–55 –35 –15 5 25 45 65 85 105 125

TEMPERATURE – °C

AVG +1

AVG

AVG –1

= +4.5V

NO LOAD

SSZ = 300 UNITS

Figure 17. Zero-Scale Voltage vs.

Temperature

3.5

3.0

2.5

2.0

1.5

1.0

0.5

4.0

SUPPLY CURRENT – mA

–55 –35 –15 5 25 65 12545 85 105

TEMPERATURE – °C

= +5.5V

= +2.4V

NO LOAD

= +5V

= +4.5V

Figure 20. Supply Current vs.

Temperature

AD8522

–8– REV. A

PRINTED IN U.S.A. C1942–18–94

CLK

OUT

20mV/

DIV

TIME – 5µs/DIV

Figure 22. Digital Feedthrough vs.

Time

REF

TIME – 1µs/DIV

100

1V 1µs

= +25°C

NO LOAD

= +5V

Figure 21. Reference Startup vs.

Time

–0.01

–0.02

–0.03

–0.04

–0.05

–0.06

REF

LOAD REGULATION – %/mA

–55 –35 –15 5 25 65 12545 85 105

TEMPERATURE – °C

= +4.5V

SSZ = 300 UNITS

∆ I

= 5mA

AVG +3

AVG

AVG –3

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

14-Lead Epoxy DIP (N-14)14-Lead Narrow Body SOIC (SO-14)

0.0098 (0.25)

0.0075 (0.19)

0.0500 (1.27)

0.0160 (0.41)

0.0196 (0.50)

0.0099 (0.25) x 45

PIN 1

0.1574 (4.00)

0.1497 (3.80)

0.2440 (6.20)

0.2284 (5.80)

14 8

0.0192 (0.49)

0.0138 (0.35)

0.0500

(1.27)

BSC

0.0688 (1.75)

0.0532 (1.35)

0.3444 (8.75)

0.3367 (8.55)

0.0098 (0.25)

0.0040 (0.10)

0.210

(5.33)

MAX

0.160 (4.06)

0.115 (2.93)

0.795 (20.19)

0.725 (18.42)

0.022 (0.558)

0.014 (0.356) 0.100

(2.54)

BSC

0.070 (1.77)

0.045 (1.15) SEATING

PLANE

0.060 (1.52)

0.015 (0.38)

0.130

(3.30)

MIN

PIN 1 0.280 (7.11)

0.240 (6.10)

0.325 (8.25)

0.300 (7.62)

0.015 (0.381)

0.008 (0.204)

0.195 (4.95)

0.115 (2.93)

2.502

2.500

2.498

2.496

2.494

2.492

2.504

REF

– Volts

–55 –35 –15 5 25 65 12545 85 105

TEMPERATURE – °C

= +4.5V

SSZ = 300 UNITS

AVG +1

AVG

AVG –1

Figure 23. Reference Voltage vs.

Temperature

Figure 24. Reference Load Regulation

vs. Temperature

0.04

0.03

0.02

0.01

0.05

REF

LINE REGULATION – %/Volts

–55 –35 –15 5 25 65 12545 85 105

TEMPERATURE – °C

∆ V

= +4.5V TO +5.5V

SSZ = 300 UNITS

AVG +3

AVG

AVG –3

Figure 25. Reference Line Regulation vs.

Temperature