CHG
DSG
BAT
PACK
VCC
VC4
VC3
VC2
VC1
VSS SRNSRP
PACK+
PACK–
PRES
SMBC
SMBD
SMBD
SMBC
PBI TS1 TS2
FUSE
LEDCNTLA
LEDCNTLB
DISP
PTC
LEDCNTLC
TS3TS4BTP
BTP
VC1
VC2
VC3OUT
VDD
GND
2nd level
protector
Cell 1
Cell 2
Cell 3
PRES
PCHG
Product
Folder
Sample &
Buy
Technical
Documents
Tools &
Software
Support &
Community
bq40z50-R1
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bq40z50-R1 1-Series, 2-Series, 3-Series, and 4-Series Li-Ion Battery Pack Manager
1 Features 3 Description
The bq40z50-R1 device, incorporating patented
1• Fully Integrated 1-Series, 2-Series, 3-Series, and Impedance Track™ technology, is a fully integrated,
4-Series Li-Ion or Li-Polymer Cell Battery Pack single-chip, pack-based solution that provides a rich
Manager and Protection array of features for gas gauging, protection, and
• Next-Generation Patented Impedance Track™ authentication for 1-series, 2-series, 3-series, and 4-
Technology Accurately Measures Available series cell Li-Ion and Li-Polymer battery packs.
Charge in Li-Ion and Li-Polymer Batteries Using its integrated high-performance analog
• High Side N-CH Protection FET Drive peripherals, the bq40z50-R1 device measures and
• Integrated Cell Balancing While Charging or At maintains an accurate record of available capacity,
voltage, current, temperature, and other critical
Rest parameters in Li-Ion or Li-Polymer batteries, and
• Full Array of Programmable Protection Features reports this information to the system host controller
– Voltage over an SMBus v1.1 compatible interface.
– Current Device Information(1)
– Temperature PART NUMBER PACKAGE BODY SIZE (NOM)
– Charge Timeout bq40z50-R1 VQFN (32) 4.00 mm × 4.00 mm
– CHG/DSG FETs (1) For all available packages, see the orderable addendum at
– AFE the end of the datasheet.
• Sophisticated Charge Algorithms Simplified Schematic
– JEITA
– Enhanced Charging
– Adaptive Charging
– Cell Balancing
• Supports TURBO BOOST Mode
• Supports Battery Trip Point (BTP)
• Diagnostic Lifetime Data Monitor and Black Box
Recorder
• LED Display
• Supports Two-Wire SMBus v1.1 Interface
• SHA-1 Authentication
• Compact Package: 32-Lead QFN (RSM)
2 Applications
• Notebook/Netbook PCs
• Medical and Test Equipment
• Portable Instrumentation
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
7.24 Electrical Characteristics: Internal 1.8-V LDO ..... 14
1 Features.................................................................. 17.25 Electrical Characteristics: High-Frequency
2 Applications ........................................................... 1Oscillator.................................................................. 14
3 Description............................................................. 17.26 Electrical Characteristics: Low-Frequency
4 Revision History..................................................... 2Oscillator.................................................................. 14
5 Description (continued)......................................... 37.27 Electrical Characteristics: Voltage Reference 1.... 15
6 Pin Configuration and Functions......................... 37.28 Electrical Characteristics: Voltage Reference 2.... 15
7.29 Electrical Characteristics: Instruction Flash.......... 15
7 Specifications......................................................... 77.30 Electrical Characteristics: Data Flash ................... 15
7.1 Absolute Maximum Ratings ...................................... 77.31 Electrical Characteristics: OCD, SCC, SCD1, SCD2
7.2 ESD Ratings.............................................................. 7Current Protection Thresholds................................. 16
7.3 Recommended Operating Conditions....................... 87.32 Timing Requirements: OCD, SCC, SCD1, SCD2
7.4 Thermal Information.................................................. 8Current Protection Timing........................................ 16
7.5 Electrical Characteristics: Supply Current................. 87.33 Timing Requirements: SMBus .............................. 17
7.6 Electrical Characteristics: Power Supply Control...... 87.34 Timing Requirements: SMBus XL......................... 17
7.7 Electrical Characteristics: AFE Power-On Reset...... 97.35 Typical Characteristics ......................................... 19
7.8 Electrical Characteristics: AFE Watchdog Reset and 8 Detailed Description............................................ 22
Wake Timer................................................................ 98.1 Overview................................................................. 22
7.9 Electrical Characteristics: Current Wake
Comparator................................................................ 98.2 Functional Block Diagram ...................................... 22
7.10 Electrical Characteristics: VC1, VC2, VC3, VC4, 8.3 Feature Description................................................. 23
BAT, PACK .............................................................. 10 8.4 Device Functional Modes........................................ 26
7.11 Electrical Characteristics: SMBD, SMBC.............. 10 9 Applications and Implementation ...................... 27
7.12 Electrical Characteristics: PRES, BTP_INT, DISP 9.1 Application Information .......................................... 27
................................................................................. 10 9.2 Typical Applications ................................................ 28
7.13 Electrical Characteristics: LEDCNTLA, LEDCNTLB, 10 Power Supply Recommendations ..................... 42
LEDCNTLC ............................................................. 11 11 Layout................................................................... 43
7.14 Electrical Characteristics: Coulomb Counter ........ 11 11.1 Layout Guidelines ................................................. 43
7.15 Electrical Characteristics: CC Digital Filter ........... 11 11.2 Layout Example .................................................... 45
7.16 Electrical Characteristics: ADC............................. 11
7.17 Electrical Characteristics: ADC Digital Filter......... 12 12 Device and Documentation Support................. 47
7.18 Electrical Characteristics: CHG, DSG FET Drive . 12 12.1 Documentation Support ........................................ 47
7.19 Electrical Characteristics: PCHG FET Drive......... 13 12.2 Community Resources.......................................... 47
7.20 Electrical Characteristics: FUSE Drive.................. 13 12.3 Trademarks........................................................... 47
7.21 Electrical Characteristics: Internal Temperature 12.4 Electrostatic Discharge Caution............................ 47
Sensor...................................................................... 13 12.5 Glossary................................................................ 47
7.22 Electrical Characteristics: TS1, TS2, TS3, TS4.... 13 13 Mechanical, Packaging, and Orderable
7.23 Electrical Characteristics: PTC, PTCEN............... 14 Information ........................................................... 47
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE REVISION NOTES
July 2015 * Initial Release
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1
2
VC4
3
VC3
4
VC2
5
VC1
6
VSS
7
TS1
8
TS2
9
TS3
10
TS4
11
SRP
12
SRN
13
BTP_INT
19
LEDCNTLC
18
LEDCNTLB
17
LEDCNTLA
16
15
SMBC
22
23
PACK
24
DSG
29
NC
30
CHG
31
BAT
32
PBI
SMBD
14
21
VCC
20
FUSE
PRES or
SHUTDN
NC
PCHG
25
26
27
28
DISP
PTC
PTCEN
NC
¯¯¯¯
¯¯¯¯
¯¯¯¯
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5 Description (continued)
The bq40z50-R1 device supports TURBO BOOST mode by providing the available max power and max current
to the host system. The device also supports Battery Trip Point to send a BTP interrupt signal to the host system
at the pre-set state of charge thresholds.
The bq40z50-R1 provides software-based 1st- and 2nd-level safety protection against overvoltage, undervoltage,
overcurrent, short-circuit current, overload, and overtemperature conditions, as well as other pack- and cell-
related faults.
SHA-1 authentication, with secure memory for authentication keys, enables identification of genuine battery
packs.
The compact 32-lead QFN package minimizes solution cost and size for smart batteries while providing
maximum functionality and safety for battery gauging applications.
6 Pin Configuration and Functions
RSM Package
32-Pin VQFN with Exposed Thermal Pad
Top View
Pin Functions
PIN NAME NUMBER TYPE(1) DESCRIPTION
PBI 1 P Power supply backup input pin
Sense voltage input pin for most positive cell, and balance current input for most positive
VC4 2 IA cell
Sense voltage input pin for second most positive cell, balance current input for second
VC3 3 IA most positive cell, and return balance current for most positive cell
Sense voltage input pin for third most positive cell, balance current input for third most
VC2 4 IA positive cell, and return balance current for second most positive cell
Sense voltage input pin for least positive cell, balance current input for least positive cell,
VC1 5 IA and return balance current for third most positive cell
Analog input pin connected to the internal coulomb counter peripheral for integrating a
SRN 6 I small voltage between SRP and SRN where SRP is the top of the sense resistor.
NC 7 — Not internally connected. Connect to VSS.
Analog input pin connected to the internal coulomb counter peripheral for integrating a
SRP 8 I small voltage between SRP and SRN where SRP is the top of the sense resistor.
VSS 9 P Device ground
TS1 10 IA Temperature sensor 1 thermistor input pin
TS2 11 IA Temperature sensor 2 thermistor input pin
TS3 12 IA Temperature sensor 3 thermistor input pin
TS4 13 IA Temperature sensor 4 thermistor input pin
NC 14 — Not internally connected
(1) P = Power Connection, O = Digital Output, AI = Analog Input, I = Digital Input, I/OD = Digital Input/Output
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Pin Functions (continued)
PIN NAME NUMBER TYPE(1) DESCRIPTION
BTP_INT 15 O Battery Trip Point (BTP) interrupt output
Host system present input for removable battery pack or emergency system shutdown
PRES or SHUTDN 16 I input for embedded pack
DISP 17 — Display control for LEDs
SMBD 18 I/OD SMBus data pin
SMBC 19 I/OD SMBus clock pin
LED display segment that drives the external LEDs depending on the firmware
LEDCNTLA 20 — configuration
LED display segment that drives the external LEDs depending on the firmware
LEDCNTLB 21 — configuration
LED display segment that drives the external LEDs depending on the firmware
LEDCNTLC 22 — configuration
PTC 23 IA Safety PTC thermistor input pin. To disable, connect both PTC and PTCEN to VSS.
Safety PTC thermistor enable input pin. Connect to BAT. To disable, connect both PTC
PTCEN 24 IA and PTCEN to VSS.
FUSE 25 O Fuse drive output pin
VCC 26 P Secondary power supply input
PACK 27 IA Pack sense input pin
DSG 28 O NMOS Discharge FET drive output pin
NC 29 — Not internally connected
PCHG 30 O PMOS Precharge FET drive output pin
CHG 31 O NMOS Charge FET drive output pin
BAT 32 P Primary power supply input pin
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BAT PACKVCC
PBI
Reference
System
1.8 V
Domain
+
–PACK
Detector
BATDET
ENVCC
3.1 V
Shutdown
Latch
BAT
Control
ENBAT
PACKDET
SHUTDOWN
SHOUT
BAT CHG
Pump
CHG2 kΩ
CHGOFF
CHGEN
BAT DSG
Pump
DSG2 kΩ
DSGEN
PACK
DSGOFF
Power Supply Control
CHG, DSG Drive
PCHG
2 kΩ
VCC
PCHGEN
8 kΩ
Pre-Charge Drive
VCC
Zero-Volt Charge
BAT CHG
Pump
CHGEN
BAT
ZVCD
ZVCHGEN
Cell Balancing
VC1
VC2
VC3
VC4
CDEN4
CDEN3
CDEN2
CDEN1
ADC Mux ADC
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Figure 1. Pin Equivalent Diagram 1
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SMBus Interface
100 kΩ
1 MΩ
SMBC
SMBCIN
SMBCEN
SMBCOUT
100 kΩ
1 MΩ
SMBD
SMBDIN
SMBDEN
SMBDOUT
FUSE
2 kΩ
FUSE Drive
FUSEEN
BAT
FUSEWKPUP
100 kΩ FUSEDIG
150 nA
Thermistor Inputs
ADTHx
2 kΩ
TS1,2,3,4
18 kΩ
1.8 V
ADC Mux
High-Voltage GPIO
RHOEN
PBI
100 kΩ
RHIN
10 kΩ
PRES
RHOUT
LED Drive
RLOEN
BAT
100 kΩ
RLIN
10 kΩ
LED1, 2, 3
RLOUT
22.5 mA
ADC
PTC PTC
Counter
PTC
Latch
PTCDIG
290 nA
PTCEN
30 kΩ PTC
Comparator
PTC Detection
RCWKPUP
1 kΩ RCIN
RCOUT
1.8 V
RCPUP
1.8 V
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Figure 2. Pin Equivalent Diagram 2
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Figure 3. Pin Equivalent Diagram 3
7 Specifications
7.1 Absolute Maximum Ratings
Over-operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage range, BAT, VCC, PBI –0.3 30 V
VCC PACK, SMBC, SMBD, PRES or SHUTDN, BTP_INT, DISP –0.3 30 V
TS1, TS2, TS3, TS4 –0.3 VREG + 0.3 V
PTC, PTCEN, LEDCNTLA, LEDCNTLB, LEDCNTLC –0.3 VBAT + 0.3 V
SRP, SRN –0.3 0.3 V
VC3 + 8.5, or
VC4 VC3 – 0.3 V
Input voltage range, VSS + 30
VIN VC2 + 8.5, or
VC3 VC2 – 0.3 V
VSS + 30
VC1 + 8.5, or
VC2 VC1 – 0.3 V
VSS + 30
VSS + 8.5, or
VC1 VSS – 0.3 V
VSS + 30
CHG, DSG –0.3 32
Output voltage range,
VOPCHG, FUSE –0.3 30 V
Maximum VSS current, ISS 50 mA
Storage temperature, TSTG –65 150 °C
Lead temperature (soldering, 10 s), TSOLDER 300 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000
Electrostatic
V(ESD) V
Charged-device model (CDM), per JEDEC specification JESD22-
discharge ±500
C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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7.3 Recommended Operating Conditions
Typical values stated where TA= 25°C and VCC = 14.4 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted) MIN NOM MAX UNIT
VCC Supply voltage BAT, VCC, PBI 2.2 26 V
VSHUTDOWN– Shutdown voltage VPACK < VSHUTDOWN– 1.8 2.0 2.2 V
VSHUTDOWN+ Start-up voltage VPACK > VSHUTDOWN– + VHYS 2.05 2.25 2.45 V
Shutdown voltage
VHYS VSHUTDOWN+ – VSHUTDOWN– 250 mV
hysteresis PACK, SMBC, SMBD, PRES, BTP_IN, DISP 26
TS1, TS2, TS3, TS4 VREG
PTC, PTCEN, LEDCNTLA, LEDCNTLB, LEDCNTLC VBAT
SRP, SRN –0.2 0.2
VIN Input voltage range V
VC4 VVC3 VVC3 + 5
VC3 VVC2 VVC2 + 5
VC2 VVC1 VVC1 + 5
VC1 VVSS VVSS + 5
Output voltage
VOCHG, DSG, PCHG, FUSE 26 V
range
External PBI
CPBI 2.2 µF
capacitor
Operating
TOPR –40 85 °C
temperature
7.4 Thermal Information RSM (QFN)
THERMAL METRIC(1) UNIT
32 PINS
RθJA, High K Junction-to-ambient thermal resistance 47.4
RθJC(top) Junction-to-case(top) thermal resistance 40.3
RθJB Junction-to-board thermal resistance 14.7 °C/W
ψJT Junction-to-top characterization parameter 0.8
ψJB Junction-to-board characterization parameter 14.4
RθJC(bottom) Junction-to-case(bottom) thermal resistance 3.8
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
7.5 Electrical Characteristics: Supply Current
Typical values stated where TA= 25°C and VCC = 14.4 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 20 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INORMAL NORMAL mode CHG on. DSG on, no Flash write 336 µA
CHG off, DSG on, no SBS communication 75
ISLEEP SLEEP mode µA
CHG off, DSG off, no SBS communication 52
ISHUTDOWN SHUTDOWN mode 1.6 µA
7.6 Electrical Characteristics: Power Supply Control
Typical values stated where TA= 25°C and VCC = 14.4 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
BAT to VCC
VSWITCHOVER– switchover VBAT < VSWITCHOVER– 1.95 2.1 2.2 V
voltage
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Electrical Characteristics: Power Supply Control (continued)
Typical values stated where TA= 25°C and VCC = 14.4 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VCC to BAT
VSWITCHOVER+ switchover VBAT > VSWITCHOVER– + VHYS 2.9 3.1 3.25 V
voltage
Switchover
VHYS VSWITCHOVER+ – VSWITCHOVER– 1000 mV
voltage hysteresis BAT pin, BAT = 0 V, VCC = 25 V, PACK = 25 V 1
Input Leakage PACK pin, BAT = 25 V, VCC = 0 V, PACK = 0 V 1
ILKG µA
current BAT and PACK terminals, BAT = 0 V, VCC = 0 V, PACK 1
= 0 V, PBI = 25 V
Internal pulldown
RPD PACK 30 40 50 kΩ
resistance
7.7 Electrical Characteristics: AFE Power-On Reset
Typical values stated where TA= 25°C and VCC = 14.4 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Negative-going
VREGIT– VREG 1.51 1.55 1.59 V
voltage input
Power-on reset
VHYS VREGIT+ – VREGIT– 70 100 130 mV
hysteresis
Power-on reset
tRST 200 300 400 µs
time
7.8 Electrical Characteristics: AFE Watchdog Reset and Wake Timer
Typical values stated where TA= 25°C and VCC = 14.4 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tWDT = 500 372 500 628
tWDT = 1000 744 1000 1256
AFE watchdog
tWDT ms
timeout tWDT = 2000 1488 2000 2512
tWDT = 4000 2976 4000 5024
tWAKE = 250 186 250 314
tWAKE = 500 372 500 628
tWAKE AFE wake timer ms
tWAKE = 1000 744 1000 1256
tWAKE = 512 1488 2000 2512
FET off delay after
tFETOFF tFETOFF = 512 409 512 614 ms
reset
7.9 Electrical Characteristics: Current Wake Comparator
Typical values stated where TA= 25°C and VCC = 14.4 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VWAKE = ±0.625 mV ±0.3 ±0.625 ±0.9
VWAKE = ±1.25 mV ±0.6 ±1.25 ±1.8
Wake voltage
VWAKE mV
threshold VWAKE = ±2.5 mV ±1.2 ±2.5 ±3.6
VWAKE = ±5 mV ±2.4 ±5.0 ±7.2
Temperature drift
VWAKE(DRIFT) 0.5% °C
of VWAKE accuracy
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Electrical Characteristics: Current Wake Comparator (continued)
Typical values stated where TA= 25°C and VCC = 14.4 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Time from
application of
tWAKE 700 µs
current to wake
interrupt
Wake comparator
tWAKE(SU) 500 1000 µs
startup time
7.10 Electrical Characteristics: VC1, VC2, VC3, VC4, BAT, PACK
Typical values stated where TA= 25°C and VCC = 14.4 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VC1–VSS, VC2–VC1, VC3–VC2, VC4–VC3 0.1980 0.2000 0.2020
K Scaling factor BAT–VSS, PACK–VSS 0.049 0.050 0.051 —
VREF2 0.490 0.500 0.510
VC1–VSS, VC2–VC1, VC3–VC2, VC4–VC3 –0.2 5
VIN Input voltage range V
BAT–VSS, PACK–VSS –0.2 20
VC1, VC2, VC3, VC4, cell balancing off, cell detach
ILKG Input leakage current 1 µA
detection off, ADC multiplexer off
Internal cell balance
RCB RDS(ON) for internal FET switch at 2 V < VDS < 4 V 200 Ω
resistance
Internal cell detach
ICD VCx > VSS + 0.8 V 30 50 70 µA
check current
7.11 Electrical Characteristics: SMBD, SMBC
Typical values stated where TA= 25°C and VCC = 14.4 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIH Input voltage high SMBC, SMBD, VREG = 1.8 V 1.3 V
VIL Input voltage low SMBC, SMBD, VREG = 1.8 V 0.8 V
VOL Output low voltage SMBC, SMBD, VREG = 1.8 V, IOL = 1.5 mA 0.4 V
CIN Input capacitance 5 pF
ILKG Input leakage current 1 µA
RPD Pulldown resistance 0.7 1.0 1.3 MΩ
7.12 Electrical Characteristics: PRES, BTP_INT, DISP
Typical values stated where TA= 25°C and VCC = 14.4 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIH High-level input 1.3 V
VIL Low-level input 0.55 V
VBAT > 5.5 V, IOH = –0 µA 3.5
VOH Output voltage high V
VBAT > 5.5 V, IOH = –10 µA 1.8
VOL Output voltage low IOL = 1.5 mA 0.4 V
CIN Input capacitance 5 pF
ILKG Input leakage current 1 µA
Output reverse
ROBetween PRES or BTP_INT or DISP and PBI 8 kΩ
resistance
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7.13 Electrical Characteristics: LEDCNTLA, LEDCNTLB, LEDCNTLC
Typical values stated where TA= 25°C and VCC = 14.4 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIH High-level input 1.45 V
VIL Low-level input 0.55 V
VBAT –
VOH Output voltage high VBAT > 3.0 V, IOH = –22.5 mA V
1.6
VOL Output voltage low IOL = 1.5 mA 0.4 V
High level output
ISC –30 –45 –6 0 mA
current protection
Low level output
IOL VBAT > 3.0 V, VOH = 0.4 V 15.75 22.5 29.25 mA
current
Current matching
ILEDCNTLx VBAT = VLEDCNTLx + 2.5 V ±1%
between LEDCNTLx
CIN Input capacitance 20 pF
ILKG Input leakage current 1 µA
Frequency of LED
fLEDCNTLx 124 Hz
pattern
7.14 Electrical Characteristics: Coulomb Counter
Typical values stated where TA= 25°C and VCC = 14.4 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Input voltage range –0.1 0.1 V
Full scale range –VREF1/10 VREF1/10 V
Integral nonlinearity(1) 16-bit, best fit over input voltage range ±5.2 ±22.3 LSB
Offset error 16-bit, Post-calibration ±5 ±10 µV
Offset error drift 15-bit + sign, Post-calibration 0.2 0.3 µV/°C
Gain error 15-bit + sign, over input voltage range ±0.2% ±0.8% FSR
Gain error drift 15-bit + sign, over input voltage range 150 PPM/°C
Effective input resistance 2.5 MΩ
(1) 1 LSB = VREF1/(10 × 2N) = 1.215/(10 × 215) = 3.71 µV
7.15 Electrical Characteristics: CC Digital Filter
Typical values stated where TA= 25°C and VCC = 14.4 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Conversion time Single conversion 250 ms
Effective resolution Single conversion 15 Bits
7.16 Electrical Characteristics: ADC
Typical values stated where TA= 25°C and VCC = 14.4 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Internal reference (VREF1) –0.2 1
Input voltage range V
External reference (VREG) –0.2 0.8 x VREG
Full scale range VFS = VREF1 or VREG –VFS VFS V
16-bit, best fit, –0.1 V to 0.8 x VREF1 ±6.6
Integral nonlinearity(1) LSB
16-bit, best fit, –0.2 V to –0.1 V ±13.1
(1) 1 LSB = VREF1/(2N) = 1.225/(215) = 37.4 µV (when tCONV = 31.25 ms)
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Electrical Characteristics: ADC (continued)
Typical values stated where TA= 25°C and VCC = 14.4 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Offset error(2) 16-bit, Post-calibration, VFS = VREF1 ±67 ±157 µV
Offset error drift 16-bit, Post-calibration, VFS = VREF1 0.6 3 µV/°C
Gain error 16-bit, –0.1 V to 0.8 x VFS ±0.2% ±0.8% FSR
Gain error drift 16-bit, –0.1 V to 0.8 x VFS 150 PPM/°C
Effective input resistance 8 MΩ
(2) For VC1–VSS, VC2–VC1, VC3–VC2, VC4–VC3, VC4–VSS, PACK–VSS, and VREF1/2, the offset error is multiplied by (1/ADC
multiplexer scaling factor (K)).
7.17 Electrical Characteristics: ADC Digital Filter
Typical values stated where TA= 25°C and VCC = 14.4 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Single conversion 31.25
Single conversion 15.63
Conversion time ms
Single conversion 7.81
Single conversion 1.95
Resolution No missing codes 16 Bits
With sign, tCONV = 31.25 ms 14 15
With sign, tCONV = 15.63 ms 13 14
Effective resolution Bits
With sign, tCONV = 7.81 ms 11 12
With sign, tCONV = 1.95 ms 9 10
7.18 Electrical Characteristics: CHG, DSG FET Drive
Typical values stated where TA= 25°C and VCC = 14.4 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RatioDSG = (VDSG – VBAT)/VBAT, 2.2 V < VBAT < 4.92 V, 2.133 2.333 2.433
10 MΩbetween PACK and DSG
Output voltage —
ratio RatioCHG = (VCHG – VBAT)/VBAT, 2.2 V < VBAT < 4.92 V, 2.133 2.333 2.433
10 MΩbetween BAT and CHG
VDSG(ON) = VDSG – VBAT, VBAT ≥4.92 V, 10 MΩbetween 10.5 11.5 12
PACK and DSG, VBAT = 18 V
Output voltage,
V(FETON) V
CHG and DSG on VCHG(ON) = VCHG – VBAT, VBAT ≥4.92 V, 10 MΩbetween 10.5 11.5 12
BAT and CHG, VBAT = 18 V
VDSG(OFF) = VDSG – VPACK, 10 MΩbetween PACK and –0.4 0.4
Output voltage, DSG
V(FETOFF) V
CHG and DSG off VCHG(OFF) = VCHG – VBAT, 10 MΩbetween BAT and CHG –0.4 0.4
VDSG from 0% to 35% VDSG(ON)(TYP), VBAT ≥2.2 V, CL=
4.7 nF between DSG and PACK, 5.1 kΩbetween DSG 200 500
and CL, 10 MΩbetween PACK and DSG
tRRise time µs
VCHG from 0% to 35% VCHG(ON)(TYP), VBAT ≥2.2 V, CL=
4.7 nF between CHG and BAT, 5.1 kΩbetween CHG 200 500
and CL, 10 MΩbetween BAT and CHG
VDSG from VDSG(ON)(TYP) to 1 V, VBAT ≥2.2 V, CL= 4.7 nF
between DSG and PACK, 5.1 kΩbetween DSG and CL, 40 300
10 MΩbetween PACK and DSG
tFFall time µs
VCHG from VCHG(ON)(TYP) to 1 V, VBAT ≥2.2 V, CL= 4.7
nF between CHG and BAT, 5.1 kΩbetween CHG and 40 200
CL, 10 MΩbetween BAT and CHG
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7.19 Electrical Characteristics: PCHG FET Drive
Typical values stated where TA= 25°C and VCC = 14.4 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Output voltage, VPCHG(ON) = VVCC – VPCHG, 10 MΩbetween VCC and
V(FETON) 6 7 8 V
PCHG on PCHG
Output voltage, VPCHG(OFF) = VVCC – VPCHG, 10 MΩbetween VCC and
V(FETOFF) –0.4 0.4 V
PCHG off PCHG
VPCHG from 10% to 90% VPCHG(ON)(TYP), VVCC ≥8 V, CL=
tRRise time 4.7 nF between PCHG and VCC, 5.1 kΩbetween PCHG 40 200 µs
and CL, 10 MΩbetween VCC and CHG
VPCHG from 90% to 10% VPCHG(ON)(TYP), VCC ≥8 V, CL=
tFFall time 4.7 nF between PCHG and VCC, 5.1 kΩbetween PCHG 40 200 µs
and CL, 10 MΩbetween VCC and CHG
7.20 Electrical Characteristics: FUSE Drive
Typical values stated where TA= 25°C and VCC = 14.4 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VBAT ≥8 V, CL= 1 nF, IAFEFUSE = 0 µA 6 7 8.65
Output voltage
VOH V
high VBAT < 8 V, CL= 1 nF, IAFEFUSE = 0 µA VBAT – 0.1 VBAT
VIH High-level input 1.5 2.0 2.5 V
Internal pullup
IAFEFUSE(PU) VBAT ≥8 V, VAFEFUSE = VSS 150 330 nA
current
RAFEFUSE Output impedance 2 2.6 3.2 kΩ
CIN Input capacitance 5 pF
Fuse trip detection
tDELAY 128 256 µs
delay
Fuse output rise
tRISE VBAT ≥8 V, CL= 1 nF, VOH = 0 V to 5 V 5 20 µs
time
7.21 Electrical Characteristics: Internal Temperature Sensor
Typical values stated where TA= 25°C and VCC = 14.4 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Internal VTEMPP –1.9 –2.0 –2.1
temperature
VTEMP mV/°C
sensor voltage VTEMPP – VTEMPN, assured by design 0.177 0.178 0.179
drift
7.22 Electrical Characteristics: TS1, TS2, TS3, TS4
Typical values stated where TA= 25°C and VCC = 14.4 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TS1, TS2, TS3, TS4, VBIAS = VREF1 –0.2 0.8 x VREF1
Input voltage
VIN V
range TS1, TS2, TS3, TS4, VBIAS = VREG –0.2 0.8 x VREG
Internal pullup
RNTC(PU) TS1, TS2, TS3, TS4 14.4 18 21.6 kΩ
resistance
Resistance drift
RNTC(DRIFT) over TS1, TS2, TS3, TS4 –360 –280 –200 PPM/°C
temperature
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7.23 Electrical Characteristics: PTC, PTCEN
Typical values stated where TA= 25°C and VCC = 14.4 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PTC trip
RPTC(TRIP) 1.2 2.5 3.95 MΩ
resistance
VPTC(TRIP) PTC trip voltage VPTC(TRIP) = VPTCEN – VPTC 200 500 890 mV
Internal PTC
IPTC TA= –40°C to 110°C 200 290 350 nA
current bias
tPTC(DELAY) PTC delay time TA= –40°C to 110°C 40 80 145 ms
7.24 Electrical Characteristics: Internal 1.8-V LDO
Typical values stated where TA= 25°C and VCC = 14.4 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VREG Regulator voltage 1.6 1.8 2.0 V
Regulator output
ΔVO(TEMP) ΔVREG/ΔTA, IREG = 10 mA ±0.25%
over temperature
ΔVO(LINE) Line regulation ΔVREG/ΔVBAT, VBAT = 10 mA –0 .6% 0.5%
ΔVO(LOAD) Load regulation ΔVREG/ΔIREG, IREG = 0 mA to 10 mA –1.5% 1.5%
Regulator output
IREG VREG = 0.9 x VREG(NOM), VIN > 2.2 V 20 mA
current limit
Regulator short-
ISC VREG = 0 x VREG(NOM) 25 40 55 mA
circuit current limit
Power supply
PSRRREG ΔVBAT/ΔVREG, IREG = 10 mA ,VIN > 2.5 V, f = 10 Hz 40 dB
rejection ratio
Slew rate
VSLEW enhancement VREG 1.58 1.65 V
voltage threshold
7.25 Electrical Characteristics: High-Frequency Oscillator
Typical values stated where TA= 25°C and VCC = 14.4 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fHFO Operating frequency 16.78 MHz
TA= –20°C to 70°C, includes frequency drift –2.5% ±0.25% 2.5%
fHFO(ERR) Frequency error TA= –40°C to 85°C, includes frequency drift –3.5% ±0.25% 3.5%
TA= –20°C to 85°C, oscillator frequency within 4 ms
+/–3% of nominal
tHFO(SU) Start-up time oscillator frequency within +/–3% of nominal 100 µs
7.26 Electrical Characteristics: Low-Frequency Oscillator
Typical values stated where TA= 25°C and VCC = 14.4 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fLFO Operating frequency 262.144 kHz
TA= –20°C to 70°C, includes frequency drift –1.5% ±0.25% 1.5%
fLFO(ERR) Frequency error TA= –40°C to 85°C, includes frequency drift –2.5 ±0.25 2.5
Failure detection
fLFO(FAIL) 30 80 100 kHz
frequency
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7.27 Electrical Characteristics: Voltage Reference 1
Typical values stated where TA= 25°C and VCC = 14.4 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Internal reference
VREF1 TA= 25°C, after trim 1.21 1.215 1.22 V
voltage TA= 0°C to 60°C, after trim ±50
Internal reference
VREF1(DRIFT) PPM/°C
voltage drift TA= –40°C to 85°C, after trim ±80
7.28 Electrical Characteristics: Voltage Reference 2
Typical values stated where TA= 25°C and VCC = 14.4 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Internal reference
VREF2 TA= 25°C, after trim 1.22 1.225 1.23 V
voltage TA= 0°C to 60°C, after trim ±50
Internal reference
VREF2(DRIFT) PPM/°C
voltage drift TA= –40°C to 85°C, after trim ±80
7.29 Electrical Characteristics: Instruction Flash
Typical values stated where TA= 25°C and VCC = 14.4 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Data retention 10 Years
Flash programming 1000 Cycles
write cycles
Word programming
tPROGWORD TA= –40°C to 85°C 40 µs
time
tMASSERASE Mass-erase time TA= –40°C to 85°C 40 ms
tPAGEERASE Page-erase time TA= –40°C to 85°C 40 ms
IFLASHREAD Flash-read current TA= –40°C to 85°C 2 mA
IFLASHWRITE Flash-write current TA= –40°C to 85°C 5 mA
IFLASHERASE Flash-erase current TA= –40°C to 85°C 15 mA
7.30 Electrical Characteristics: Data Flash
Typical values stated where TA= 25°C and VCC = 14.4 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Data retention 10 Years
Flash programming 20000 Cycles
write cycles
Word programming
tPROGWORD TA= –40°C to 85°C 40 µs
time
tMASSERASE Mass-erase time TA= –40°C to 85°C 40 ms
tPAGEERASE Page-erase time TA= –40°C to 85°C 40 ms
IFLASHREAD Flash-read current TA= –40°C to 85°C 1 mA
IFLASHWRITE Flash-write current TA= –40°C to 85°C 5 mA
IFLASHERASE Flash-erase current TA= –40°C to 85°C 15 mA
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7.31 Electrical Characteristics: OCD, SCC, SCD1, SCD2 Current Protection Thresholds
Typical values stated where TA= 25°C and VCC = 14.4 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOCD = VSRP – VSRN, AFE PROTECTION –16.6 –100
CONTROL[RSNS] = 1
OCD detection
VOCD mV
threshold voltage range VOCD = VSRP – VSRN, AFE PROTECTION –8.3 –50
CONTROL[RSNS] = 0
VOCD = VSRP – VSRN, AFE PROTECTION –5.56
OCD detection CONTROL[RSNS] = 1
ΔVOCD threshold voltage mV
VOCD = VSRP – VSRN, AFE PROTECTION
program step –2.78
CONTROL[RSNS] = 0
VSCC = VSRP – VSRN, AFE PROTECTION 44.4 200
CONTROL[RSNS] = 1
SCC detection
VSCC mV
threshold voltage range VSCC = VSRP – VSRN, AFE PROTECTION 22.2 100
CONTROL[RSNS] = 0
VSCC = VSRP – VSRN, AFE PROTECTION 22.2
SCC detection CONTROL[RSNS] = 1
ΔVSCC threshold voltage mV
VSCC = VSRP – VSRN, AFE PROTECTION
program step 11.1
CONTROL[RSNS] = 0
VSCD1 = VSRP – VSRN, AFE PROTECTION –44.4 –200
CONTROL[RSNS] = 1
SCD1 detection
VSCD1 mV
threshold voltage range VSCD1 = VSRP – VSRN, AFE PROTECTION –22.2 –100
CONTROL[RSNS] = 0
VSCD1 = VSRP – VSRN, AFE PROTECTION –22.2
SCD1 detection CONTROL[RSNS] = 1
ΔVSCD1 threshold voltage mV
VSCD1 = VSRP – VSRN, AFE PROTECTION
program step –11.1
CONTROL[RSNS] = 0
VSCD2 = VSRP – VSRN, AFE PROTECTION –44.4 –200
CONTROL[RSNS] = 1
SCD2 detection
VSCD2 mV
threshold voltage range VSCD2 = VSRP – VSRN, AFE PROTECTION –22.2 –100
CONTROL[RSNS] = 0
VSCD2 = VSRP – VSRN, AFE PROTECTION –22.2
SCD2 detection CONTROL[RSNS] = 1
ΔVSCD2 threshold voltage mV
VSCD2 = VSRP – VSRN, AFE PROTECTION
program step –11.1
CONTROL[RSNS] = 0
OCD, SCC, and SCDx
VOFFSET Post-trim –2.5 2.5 mV
offset error No trim –10% 10%
OCD, SCC, and SCDx
VSCALE —
scale error Post-trim –5% 5%
7.32 Timing Requirements: OCD, SCC, SCD1, SCD2 Current Protection Timing
Typical values stated where TA= 25°C and VCC = 14.4 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted) MIN NOM MAX UNIT
OCD detection
tOCD 1 31 ms
delay time
OCD detection
ΔtOCD delay time 2 ms
program step
SCC detection
tSCC 0 915 µs
delay time
SCC detection
ΔtSCC delay time 61 µs
program step AFE PROTECTION CONTROL[SCDDx2] = 0 0 915
SCD1 detection
tSCD1 µs
delay time AFE PROTECTION CONTROL[SCDDx2] = 1 0 1850
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Timing Requirements: OCD, SCC, SCD1, SCD2 Current Protection Timing (continued)
Typical values stated where TA= 25°C and VCC = 14.4 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted) MIN NOM MAX UNIT
SCD1 detection AFE PROTECTION CONTROL[SCDDx2] = 0 61
ΔtSCD1 delay time µs
AFE PROTECTION CONTROL[SCDDx2] = 1 121
program step AFE PROTECTION CONTROL[SCDDx2] = 0 0 458
SCD2 detection
tSCD2 µs
delay time AFE PROTECTION CONTROL[SCDDx2] = 1 0 915
SCD2 detection AFE PROTECTION CONTROL[SCDDx2] = 0 30.5
ΔtSCD2 delay time µs
AFE PROTECTION CONTROL[SCDDx2] = 1 61
program step
Current fault VSRP – VSRN = VT– 3 mV for OCD, SCD1, and SC2,
tDETECT 160 µs
detect time VSRP – VSRN = VT+ 3 mV for SCC
Current fault
tACC delay time Max delay setting –10% 10%
accuracy
7.33 Timing Requirements: SMBus
Typical values stated where TA= 25°C and VCC = 14.4 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted) MIN NOM MAX UNIT
SMBus operating
fSMB SLAVE mode, SMBC 50% duty cycle 10 100 kHz
frequency
SMBus master clock
fMAS MASTER mode, no clock low slave extend 51.2 kHz
frequency
Bus free time between start
tBUF 4.7 µs
and stop
Hold time after (repeated)
tHD(START) 4.0 µs
start
tSU(START) Repeated start setup time 4.7 µs
tSU(STOP) Stop setup time 4.0 µs
tHD(DATA) Data hold time 300 ns
tSU(DATA) Data setup time 250 ns
tTIMEOUT Error signal detect time 25 35 ms
tLOW Clock low period 4.7 µs
tHIGH Clock high period 4.0 50 µs
tRClock rise time 10% to 90% 1000 ns
tFClock fall time 90% to 10% 300 ns
Cumulative clock low slave
tLOW(SEXT) 25 ms
extend time
Cumulative clock low
tLOW(MEXT) 10 ms
master extend time
7.34 Timing Requirements: SMBus XL
Typical values stated where TA= 25°C and VCC = 14.4 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted) MIN NOM MAX UNIT
fSMBXL SMBus XL operating SLAVE mode 40 400 kHz
frequency
tBUF Bus free time between start 4.7 µs
and stop
tHD(START) Hold time after (repeated) 4.0 µs
start
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SMBC
SMBD
SMBC
SMBD
SMBC
SMBD
S
tSU(START)T
SP
TtBUFT
tSU(STOP)p
TtRTtF
SMBC
SMBD
TtTIMEOUT
TtHIGHT
TtLOWT
TtFTtR
tHD(DATA)TTtSU(DATA)
tHD(START)
Start and Stop Condition Wait and Hold Condition
Timeout Condition Repeated Start Condition
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Timing Requirements: SMBus XL (continued)
Typical values stated where TA= 25°C and VCC = 14.4 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted) MIN NOM MAX UNIT
tSU(START) Repeated start setup time 4.7 µs
tSU(STOP) Stop setup time 4.0 µs
tTIMEOUT Error signal detect time 5 20 ms
tLOW Clock low period 20 µs
tHIGH Clock high period 20 µs
Figure 4. SMBus Timing Diagram
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16.6
16.7
16.8
16.9
±40 ±20 0 20 40 60 80 100 120
High-Frequency Oscillator (MHz)
Temperature (C)
C008
±25.8
±25.6
±25.4
±25.2
±25.0
±24.8
±24.6
±40 ±20 0 20 40 60 80 100 120
OCD Protection Threshold (mV)
Temperature (C)
C009
1.20
1.21
1.22
1.23
1.24
±40 ±20 0 20 40 60 80 100
Reference Voltage (V)
Temperature (C)
C006
250
252
254
256
258
260
262
264
±40 ±20 0 20 40 60 80 100
Low-Frequency Oscillator (kHz)
Temperature (C)
C007
±8.0
±6.0
±4.0
±2.0
0.0
2.0
4.0
6.0
8.0
±40 ±20 0 20 40 60 80 100 120
ADC Offset Error (V/C)
Temperature (C)
Max ADC Offset Error
Min ADC Offset Error
C003
±0.15
±0.10
±0.05
0.00
0.05
0.10
0.15
±40 ±20 0 20 40 60 80 100 120
CC Offset Error (V/C)
Temperature (C)
Max CC Offset Error
Min CC Offset Error
C001
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7.35 Typical Characteristics
Figure 5. CC Offset Error vs. Temperature Figure 6. ADC Offset Error vs. Temperature
Figure 7. Reference Voltage vs. Temperature Figure 8. Low-Frequency Oscillator vs. Temperature
Threshold setting is 25 mV.
Figure 9. High-Frequency Oscillator vs. Temperature Figure 10. Overcurrent Discharge Protection Threshold vs.
Temperature
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432
434
436
438
440
442
444
446
448
450
452
±40 ±20 0 20 40 60 80 100 120
SC Charge Current Delay Time (S)
Temperature (C)
C014
400
420
440
460
480
±40 ±20 0 20 40 60 80 100 120
SC Discharge 1 Delay Time (S)
Temperature (C)
C015
±173.6
±173.5
±173.4
±173.3
±173.2
±173.1
±173.0
±172.9
±40 ±20 0 20 40 60 80 100 120
SCD 2 Protection Threshold (mV)
Temperature (C)
C012
10.70
10.75
10.80
10.85
10.90
10.95
11.00
±40 ±20 0 20 40 60 80 100 120
Over-Current Delay Time (mS)
Temperature (C)
C013
86.2
86.4
86.6
86.8
87.0
87.2
87.4
±40 ±20 0 20 40 60 80 100 120
SCC Protection Threshold (mV)
Temperature (C)
C010
±87.2
±87.0
±86.8
±86.6
±86.4
±86.2
±86.0
±40 ±20 0 20 40 60 80 100 120
SCD 1 Protection Threshold (mV)
Temperature (C)
C011
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Typical Characteristics (continued)
Threshold setting is 25 mV. Threshold setting is –88.85 mV.
Figure 11. Short Circuit Charge Protection Threshold vs. Figure 12. Short Circuit Discharge 1 Protection Threshold
Temperature vs. Temperature
Threshold setting is –177.7 mV. Threshold setting is 11 ms.
Figure 13. Short Circuit Discharge 2 Protection Threshold Figure 14. Overcurrent Delay Time vs. Temperature
vs. Temperature
Threshold setting is 465 µs. Threshold setting is 465 µs (including internal delay).
Figure 15. Short Circuit Charge Current Delay Time vs. Figure 16. Short Circuit Discharge 1 Delay Time vs.
Temperature Temperature
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4.2478
4.24785
4.2479
4.24795
4.248
4.24805
±40 ±20 0 20 40 60 80 100 120
Cell Voltage (V)
Temperature (C)
C018
99.00
99.05
99.10
99.15
99.20
99.25
±40 ±20 0 20 40 60 80 100 120
Measurement Current (mA)
Temperature (C)
C019
2.498
2.49805
2.4981
2.49815
2.4982
2.49825
2.4983
2.49835
2.4984
±40 ±20 0 20 40 60 80 100 120
Cell Voltage (V)
Temperature (C)
C016
3.498
3.49805
3.4981
3.49815
3.4982
3.49825
±40 ±20 0 20 40 60 80 100 120
Cell Voltage (V)
Temperature (C)
C017
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Typical Characteristics (continued)
This is the VCELL average for single cell.
Figure 17. VCELL Measurement at 2.5-V vs. Temperature Figure 18. VCELL Measurement at 3.5-V vs. Temperature
This is the VCELL average for single cell. ISET = 100 mA
Figure 19. VCELL Measurement at 4.25-V vs. Temperature Figure 20. I measured vs. Temperature
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DMAddr (16bit)
Cell
Balancing
Over
Current
Comparator
Short Circuit
Comparator
Power On
Reset
Voltage
Reference2
Watchdog
Timer
Zero Volt
Charge
Control
Wake
Comparator
Internal
Temp
Sensor
Random
Number
Generator
AFE ControlADC MUX
Cell Detach
Detection
High
Frequency
Oscillator
SBS COM
Engine
AFE COM
Engine
I/O &
Interrupt
Controller
Data Flash
EEPROM
ADC/CC
Digital Filter
Program
Flash
EEPROM
bqBMP
CPU
Timers&
PWM
PMAddr
(16bit)
PMInstr
(8bit)
Cell, Stack,
Pack
Voltage
Voltage
Reference1
SMBC
SMBD
LEDCNTLA
LEDCNTLB
LEDCNTLC
/DISP
/PRES or /SHUTDN
BTP_INT
FUSE
PTCEN
SRP
PCHG
DSG
CHG
VSS
PACK
BAT
VCC
VC4
VC3
VC2
VC1
High Side
N-CH FET
Drive
P-CH
FET Drive
FUSE
Control
High
Voltage
I/O
LED Display
Drive I/O
PBI
Power Mode
Control
SBS High
Voltage
Translation
Low
Frequency
Oscillator
ADC/CC
FRONTEND
1.8V LDO
Regulator
TS1
TS2
TS3
TS4
Low Voltage
I/O
PTC
Overtemp PTC
SRN
AFE COM
Engine
Data
SRAM
Data (8bit)
I/O
NTC Bias
bq40z50-R1
SLUSCB3 –JULY 2015
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8 Detailed Description
8.1 Overview
The bq40z50-R1 device, incorporating patented Impedance Track™ technology, provides cell balancing while
charging or at rest. This fully integrated, single-chip, pack-based solution provides a rich array of features for gas
gauging, protection, and authentication for 1-series, 2-series, 3-series, and 4-series cell Li-Ion and Li-Polymer
battery packs, including a diagnostic lifetime data monitor and black box recorder.
8.2 Functional Block Diagram
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8.3 Feature Description
8.3.1 Primary (1st Level) Safety Features
The bq40z50-R1 supports a wide range of battery and system protection features that can easily be configured.
See the bq40z50-R1 Technical Reference Manual (SLUUBC1) for detailed descriptions of each protection
function.
The primary safety features include:
• Cell Overvoltage Protection
• Cell Undervoltage Protection
• Cell Undervoltage Protection Compensated
• Overcurrent in Charge Protection
• Overcurrent in Discharge Protection
• Overload in Discharge Protection
• Short Circuit in Charge Protection
• Short Circuit in Discharge Protection
• Overtemperature in Charge Protection
• Overtemperature in Discharge Protection
• Undertemperature in Charge Protection
• Undertemperature in Discharge Protection
• Overtemperature FET protection
• Precharge Timeout Protection
• Host Watchdog Timeout Protection
• Fast Charge Timeout Protection
• Overcharge Protection
• Overcharging Voltage Protection
• Overcharging Current Protection
• Over Precharge Current Protection
8.3.2 Secondary (2nd Level) Safety Features
The secondary safety features of the bq40z50-R1 can be used to indicate more serious faults via the FUSE pin.
This pin can be used to blow an in-line fuse to permanently disable the battery pack from charging or
discharging. See the bq40z50-R1 Technical Reference Manual (SLUUBC1) for detailed descriptions of each
protection function.
The secondary safety features provide protection against:
• Safety Overvoltage Permanent Failure
• Safety Undervoltage Permanent Failure
• Safety Overtemperature Permanent Failure
• Safety FET Overtemperature Permanent Failure
• Qmax Imbalance Permanent Failure
• Impedance Imbalance Permanent Failure
• Capacity Degradation Permanent Failure
• Cell Balancing Permanent Failure
• Fuse Failure Permanent Failure
• PTC Permanent Failure
• Voltage Imbalance at Rest Permanent Failure
• Voltage Imbalance Active Permanent Failure
• Charge FET Permanent Failure
• Discharge FET Permanent Failure
• AFE Register Permanent Failure
• AFE Communication Permanent Failure
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Feature Description (continued)
• Second Level Protector Permanent Failure
• Instruction Flash Checksum Permanent Failure
• Open Cell Connection Permanent Failure
• Data Flash Permanent Failure
• Open Thermistor Permanent Failure
8.3.3 Charge Control Features
The bq40z50-R1 charge control features include:
• Supports JEITA temperature ranges. Reports charging voltage and charging current according to the active
temperature range
• Handles more complex charging profiles. Allows for splitting the standard temperature range into two sub-
ranges and allows for varying the charging current according to the cell voltage
• Reports the appropriate charging current needed for constant current charging and the appropriate charging
voltage needed for constant voltage charging to a smart charger using SMBus broadcasts
• Reduces the charge difference of the battery cells in fully charged state of the battery pack gradually using a
voltage-based cell balancing algorithm during charging. A voltage threshold can be set up for cell balancing to
be active. This prevents fully charged cells from overcharging and causing excessive degradation and also
increases the usable pack energy by preventing premature charge termination.
• Supports pre-charging/zero-volt charging
• Supports charge inhibit and charge suspend if battery pack temperature is out of temperature range
• Reports charging fault and also indicates charge status via charge and discharge alarms
8.3.4 Gas Gauging
The bq40z50-R1 uses the Impedance Track algorithm to measure and calculate the available capacity in battery
cells. The bq40z50-R1 accumulates a measure of charge and discharge currents and compensates the charge
current measurement for the temperature and state-of-charge of the battery. The bq40z50-R1 estimates self-
discharge of the battery and also adjusts the self-discharge estimation based on temperature. The device also
has TURBO BOOST mode support, which enables the bq40z50-R1 to provide the necessary data for the MCU to
determine what level of peak power consumption can be applied without causing a system reset or transient
battery voltage level spike to trigger termination flags. See the bq40z50-R1 Technical Reference Manual
(SLUUBC1) for further details.
8.3.5 Configuration
8.3.5.1 Oscillator Function
The bq40z50-R1 fully integrates the system oscillators and does not require any external components to support
this feature.
8.3.5.2 System Present Operation
The bq40z50-R1 checks the PRES pin periodically (1 s). If PRES input is pulled to ground by the external
system, the bq40z50-R1 detects this as system present.
8.3.5.3 Emergency Shutdown
For battery maintenance, the emergency shutdown feature enables a push button action connecting the
SHUTDN pin to shutdown an embedded battery pack system before removing the battery. A high-to-low
transition of the SHUTDN pin signals the bq40z50-R1 to turn off both CHG and DSG FETs, disconnecting the
power from the system to safely remove the battery pack. The CHG and DSG FETs can be turned on again by
another high-to-low transition detected by the SHUTDN pin or when a data flash configurable timeout is reached.
8.3.5.4 1-Series, 2-Series, 3-Series, or 4-Series Cell Configuration
In a 1-series cell configuration, VC4 is shorted to VC, VC2 and VC1. In a 2-series cell configuration, VC4 is
shorted to VC3 and VC2. In a 3-series cell configuration, VC4 is shorted to VC3.
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Feature Description (continued)
8.3.5.5 Cell Balancing
The device supports cell balancing by bypassing the current of each cell during charging or at rest. If the device's
internal bypass is used, up to 10 mA can be bypassed and multiple cells can be bypassed at the same time.
Higher cell balance current can be achieved by using an external cell balancing circuit. In external cell balancing
mode, only one cell at a time can be balanced.
The cell balancing algorithm determines the amount of charge needed to be bypassed to balance the capacity of
all cells.
8.3.6 Battery Parameter Measurements
8.3.6.1 Charge and Discharge Counting
The bq40z50-R1 uses an integrating delta-sigma analog-to-digital converter (ADC) for current measurement, and
a second delta-sigma ADC for individual cell and battery voltage and temperature measurement.
The integrating delta-sigma ADC measures the charge/discharge flow of the battery by measuring the voltage
drop across a small-value sense resistor between the SRP and SRN terminals. The integrating ADC measures
bipolar signals from –0.1 V to 0.1 V. The bq40z50-R1 detects charge activity when VSR = V(SRP) – V(SRN) is
positive, and discharge activity when VSR = V(SRP) – V(SRN) is negative. The bq40z50-R1 continuously integrates
the signal over time, using an internal counter. The fundamental rate of the counter is 0.26 nVh.
8.3.7 Battery Trip Point (BTP)
Required for WIN8 OS, the battery trip point (BTP) feature indicates when the RSOC of a battery pack has
depleted to a certain value set in a DF register. This feature allows a host to program two capacity-based
thresholds that govern the triggering of a BTP interrupt on the BTP_INT pin and the setting or clearing of the
OperationStatus[BTP_INT] on the basis of RemainingCapacity().
An internal weak pull-up is applied when the BTP feature is active. Depending on the system design, an external
pull-up may be required to put on the BTP_INT pin. See Electrical Characteristics: PRES, BTP_INT, DISP for
details.
8.3.8 Lifetime Data Logging Features
The bq40z50-R1 offers lifetime data logging for several critical battery parameters. The following parameters are
updated every 10 hours if a difference is detected between values in RAM and data flash:
• Maximum and Minimum Cell Voltages
• Maximum Delta Cell Voltage
• Maximum Charge Current
• Maximum Discharge Current
• Maximum Average Discharge Current
• Maximum Average Discharge Power
• Maximum and Minimum Cell Temperature
• Maximum Delta Cell Temperature
• Maximum and Minimum Internal Sensor Temperature
• Maximum FET Temperature
• Number of Safety Events Occurrences and the Last Cycle of the Occurrence
• Number of Valid Charge Termination and the Last Cycle of the Valid Charge Termination
• Number of Qmax and Ra Updates and the Last Cycle of the Qmax and Ra Updates
• Number of Shutdown Events
• Cell Balancing Time for Each Cell
(This data is updated every 2 hours if a difference is detected.)
• Total FW Runtime and Time Spent in Each Temperature Range
(This data is updated every 2 hours if a difference is detected.)
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Feature Description (continued)
8.3.9 Authentication
The bq40z50-R1 supports authentication by the host using SHA-1.
8.3.10 LED Display
The bq40z50-R1 can drive a 3-, 4-, or 5- segment LED display for remaining capacity indication and/or a
permanent fail (PF) error code indication.
8.3.11 Voltage
The bq40z50-R1 updates the individual series cell voltages at 0.25-second intervals. The internal ADC of the
bq40z50-R1 measures the voltage, and scales and calibrates it appropriately. This data is also used to calculate
the impedance of the cell for the Impedance Track gas gauging.
8.3.12 Current
The bq40z50-R1 uses the SRP and SRN inputs to measure and calculate the battery charge and discharge
current using a 1-mΩto 3-mΩtyp. sense resistor.
8.3.13 Temperature
The bq40z50-R1 has an internal temperature sensor and inputs for four external temperature sensors. All five
temperature sensor options can be individually enabled and configured for cell or FET temperature usage. Two
configurable thermistor models are provided to allow the monitoring of cell temperature in addition to FET
temperature, which use a different thermistor profile.
8.3.14 Communications
The bq40z50-R1 uses SMBus v1.1 with MASTER mode and packet error checking (PEC) options per the SBS
specification.
8.3.14.1 SMBus On and Off State
The bq40z50-R1 detects an SMBus off state when SMBC and SMBD are low for two or more seconds. Clearing
this state requires that either SMBC or SMBD transition high. The communication bus will resume activity within
1 ms.
8.3.14.2 SBS Commands
See the bq40z50-R1 Technical Reference Manual (SLUUBC1) for further details.
8.4 Device Functional Modes
The bq40z50-R1 supports three power modes to reduce power consumption:
• In NORMAL mode, the bq40z50-R1 performs measurements, calculations, protection decisions, and data
updates in 250-ms intervals. Between these intervals, the bq40z50-R1 is in a reduced power stage.
• In SLEEP mode, the bq40z50-R1 performs measurements, calculations, protection decisions, and data
updates in adjustable time intervals. Between these intervals, the bq40z50-R1 is in a reduced power stage.
The bq40z50-R1 has a wake function that enables exit from SLEEP mode when current flow or failure is
detected.
• In SHUTDOWN mode, the bq40z50-R1 is completely disabled.
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9 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The bq40z50-R1 is a gas gauge with primary protection support, and that can be used with a 1-series to 4-series
Li-Ion/Li Polymer battery pack. To implement and design a comprehensive set of parameters for a specific
battery pack, users need the Battery Management Studio (bqSTUDIO) graphical user-interface tool installed on a
PC during development. The firmware installed on the bqSTUDIO tool has default values for this product, which
are summarized in the bq40z50-R1 Technical Reference Manual (SLUUBC1). Using the bqSTUDIO tool, these
default values can be changed to cater to specific application requirements during development once the system
parameters, such as fault trigger thresholds for protection, enable/disable of certain features for operation,
configuration of cells, chemistry that best matches the cell used, and more are known. This data is referred to as
the "golden image."
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Product Folder Links: bq40z50-R1
2P
1P
1N
4P
3P
Sys Pres
PACK-
PACK+
SRP SRN
BAT
CHG
DSG
FUSEPIN
FUSE
1
1
IC ground should be connected to the 1N cell tab.
Place RT1 close to Q2 and Q3.
2
SMBC
SMBD
2
Wake
For Thumbus-SMB
LED3
LED5
LED2
LED4
LED1
0.1uF
C8
0.1uF
C10
12
GND SIDE
12
GND SIDE
12
GND SIDE
12
GND SIDE
1
2
3
4
J2
100
R25
100
R27
1K
R29
200
R24
200
R26
200
R28
10K
RT2
100
R30
100
R31
DNP
C19
DNP
C20
0.1uF
C18
0.001
R19
0.1uF
C12
1
2
3
J3
1
2
J4
1
2
3
J5 1
2
J1
100
R20
100
R21
100
R22
100
R23
0.1uF
C14
0.1uF
C15
0.1uF
C16
0.1uF
C17
2.2uF
C13
BAT54HT1
D1
0.1uF
C4
0.1uF
C5
0.1uF
C9
0.1uF
C11
1K
R18
0.1uF
C6
0.1uF
C7
Si1406DH
1
2
3
4
5
6
Q5
51K
R6
0.1uF
C3
1 2
3
SFDxxxx
F1
5.1K
R16
5.1K
R17
5.1K
R7 R8
100
R9
5.1K
R10
10K
R12
10M
R2
10M
R3
10M
R5
0.1uF
C1
0.1uF
C2
Si7116DN
1
2
3
4
5
Q2 Si7116DN
1
2
3
4
5
Q3
300
R1
2N7002K
1
23
Q4
10K
R4
10K
RT3
10K
RT4
10K
RT5
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
MM3ZxxVyC
D2
MM3ZxxVyC
D3
MM3ZxxVyC
D4
FDN358P
1
3 2
Q1
BQ2947xyDSG
VDD
1
V4
2
V3
3
V2
4V1 5
VSS 6
CD 7
OUT 8
EP
9
U2
PBI
1
VC4
2
VC3
3
VC2
4
VC1
5
SRN
6
NC
7
SRP
8
VSS
9
TS1
10
TS2
11
TS3
12
TS4
13
NC
14
BTP_INT
15
PRESorSHUTDN
16
DISP 17
SMBD 18
SMBC 19
LEDCNTLA 20
LEDCNTLB 21
LEDCNTLC 22
PTC 23
PTCEN 24
FUSE 25
VCC 26
PACK 27
DSG 28
NC 29
PCHG 30
CHG 31
BAT 32
PWPD 33
10K
R32
1
2
3
4
5
67
J6
CHGND
CHGND
BAT
4P
SMBD
SMBC
PACK+
GND
BAT
GND
BAT
CHGND
CHGND
CHGND
GND GND GND
GND
GND
CHGND
GND
GND
AGND
AGND
4P
PACK+
4P PACK+
CHGND
I2C_VOUT
SMBD
SMBC
SMBC
SMBD
GND
A
A'
B
B'
S1
GND
A
A'
B
B'
S3
A
A'
B
B'
S2
GND
DNP
C21
1
1
D5 D6
D7
D9
D8
NT1
Net-Tie
PACK-
PACK+
LED DISPLAY
SHUTDOWN
11
TP12
1
2
J7
10KRT1
GND
1
1
1
1
TP3
1K
R13
1K
R14
1K
R15
100
R11
VSS
SMBD
SMBC
GND
3Replace D1 and R9 with a 10 ohm resistor for single cell applications
3
3
5.1K
bq40z50-R1
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9.2 Typical Applications
Figure 21. Application Schematic
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Typical Applications (continued)
9.2.1 Design Requirements
Table 1 shows the default settings for the main parameters. Use the bqSTUDIO tool to update the settings to
meet the specific application or battery pack configuration requirements.
The device should be calibrated before any gauging test. Follow the bqSTUDIO Calibration page to calibrate the
device, and use the bqSTUDIO Chemistry page to update the match chemistry profile to the device.
Table 1. Design Parameters
DESIGN PARAMETER EXAMPLE
Cell Configuration 3s1p (3-series with 1 Parallel)(1)
Design Capacity 4400 mAh
Device Chemistry 1210 (LiCoO2/graphitized carbon)
Cell Overvoltage at Standard Temperature 4300 mV
Cell Undervoltage 2500 mV
Shutdown Voltage 2300 mV
Overcurrent in CHARGE Mode 6000 mA
Overcurrent in DISCHARGE Mode –6000 mA
Short Circuit in CHARGE Mode 0.1 V/Rsense across SRP, SRN
Short Circuit in DISCHARGE Mode 0.1 V/Rsense across SRP, SRN
Safety Overvoltage 4500 mV
Cell Balancing Disabled
Internal and External Temperature Sensor External Temperature Sensor is used.
Undertemperature Charging 0°C
Undertemperature Discharging 0°C
BROADCAST Mode Disabled
Battery Trip Point (BTP) with active high interrupt Disabled
(1) When using the device the first time, if the a 1-s or 2-s battery pack is used, then a charger or power supply should be connected to the
PACK+ terminal to prevent device shutdown. Then update the cell configuration (see the bq40z50-R1 Technical Reference Manual
[SLUUBC1] for details) before removing the charger connection.
9.2.2 Detailed Design Procedure
9.2.2.1 High-Current Path
The high-current path begins at the PACK+ terminal of the battery pack. As charge current travels through the
pack, it finds its way through protection FETs, a chemical fuse, the lithium-ion cells and cell connections, and the
sense resistor, and then returns to the PACK– terminal (see Figure 22). In addition, some components are
placed across the PACK+ and PACK– terminals to reduce effects from electrostatic discharge.
9.2.2.1.1 Protection FETs
Select the N-channel charge and discharge FETs for a given application. Most portable battery applications are a
good match for the CSD17308Q3. The TI CSD17308Q3 is a 47A, 30-V device with Rds(on) of 8.2 mΩwhen the
gate drive voltage is 8 V.
If a precharge FET is used, R1 is calculated to limit the precharge current to the desired rate. Be sure to account
for the power dissipation of the series resistor. The precharge current is limited to (VCHARGER – VBAT)/R1 and
maximum power dissipation is (Vcharger – Vbat)2/R1.
The gates of all protection FETs are pulled to the source with a high-value resistor between the gate and source
to ensure they are turned off if the gate drive is open.
Capacitors C1 and C2 help protect the FETs during an ESD event. Using two devices ensures normal operation
if one becomes shorted. To have good ESD protection, the copper trace inductance of the capacitor leads must
be designed to be as short and wide as possible. Ensure that the voltage rating of both C1 and C2 are adequate
to hold off the applied voltage if one of the capacitors becomes shorted.
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Figure 22. bq40z50-R1 Protection FETs
9.2.2.1.2 Chemical Fuse
The chemical fuse (Dexerials, Uchihashi, and so forth) is ignited under command from either the bq294700
secondary voltage protection IC or from the FUSE pin of the gas gauge. Either of these events applies a positive
voltage to the gate of Q5, shown in Figure 23, which then sinks current from the third terminal of the fuse,
causing it to ignite and open permanently.
It is important to carefully review the fuse specifications and match the required ignition current to that available
from the N-channel FET. Ensure that the proper voltage, current, and Rds(on) ratings are used for this device.
The fuse control circuit is discussed in detail in FUSE Circuitry.
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Figure 23. FUSE Circuit
9.2.2.1.3 Lithium-Ion Cell Connections
The important part to remember about the cell connections is that high current flows through the top and bottom
connections; therefore, the voltage sense leads at these points must be made with a Kelvin connection to avoid
any errors due to a drop in the high-current copper trace. The location marked 4P in Figure 24 indicates the
Kelvin connection of the most positive battery node. The connection marked 1N is equally important. The VC5
pin (a ground reference for cell voltage measurement), which is in the older generation devices, is not in the
bq40z50-R1 device. Therefore, the single-point connection at 1N to the low-current ground is needed to avoid an
undesired voltage drop through long traces while the gas gauge is measuring the bottom cell voltage.
Figure 24. Lithium-Ion Cell Connections
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9.2.2.1.4 Sense Resistor
As with the cell connections, the quality of the Kelvin connections at the sense resistor is critical. The sense
resistor must have a temperature coefficient no greater than 50 ppm in order to minimize current measurement
drift with temperature. Choose the value of the sense resistor to correspond to the available overcurrent and
short-circuit ranges of the bq40z50-R1. Select the smallest value possible to minimize the negative voltage
generated on the bq40z50-R1 VSS node(s) during a short circuit. This pin has an absolute minimum of –0.3 V.
Parallel resistors can be used as long as good Kelvin sensing is ensured. The device is designed to support a 1-
mΩto 3-mΩsense resistor.
The ground scheme of bq40z50-R1 is different from the older generation devices. In previous devices, the device
ground (or low current ground) is connected to the SRN side of the Rsense resistor pad. The bq40z50-R1,
however, connects the low-current ground on the SRP side of the Rsense resistor pad, close to the battery 1N
terminal (see Lithium-Ion Cell Connections). This is because the bq40z50-R1 has one less VC pin (a ground
reference pin VC5) compared to the previous devices. The pin was removed and was internally combined to
SRP.
Figure 25. Sense Resistor
9.2.2.1.5 ESD Mitigation
A pair of series 0.1-μF ceramic capacitors is placed across the PACK+ and PACK– terminals to help in the
mitigation of external electrostatic discharges. The two devices in series ensure continued operation of the pack
if one of the capacitors becomes shorted.
Optionally, a tranzorb such as the SMBJ2A can be placed across the terminals to further improve ESD immunity.
9.2.2.2 Gas Gauge Circuit
The Gas Gauge Circuit includes the bq40z50-R1 and its peripheral components. These components are divided
into the following groups: Differential Low-Pass Filter, PBI, System Present, SMBus Communication, FUSE
circuit, and LED.
9.2.2.2.1 Coulomb-Counting Interface
The bq40z50-R1 uses an integrating delta-sigma ADC for current measurements. Add a 100-Ωresistor from the
sense resistor to the SRP and SRN inputs of the device. Place a 0.1-µF (C18) filter capacitor across the SRP
and SRN inputs. Optional 0.1-µF filter capacitors (C19 and C20) can be added for additional noise filtering, if
required for your circuit.
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Figure 26. Differential Filter
9.2.2.2.2 Power Supply Decoupling and PBI
The bq40z50-R1 has an internal LDO that is internally compensated and does not require an external decoupling
capacitor.
The PBI pin is used as a power supply backup input pin providing power during brief transient power outages. A
standard 2.2-µF ceramic capacitor is connected from the PBI pin to ground as shown in Figure 27.
Figure 27. Power Supply Decoupling
9.2.2.2.3 System Present
The System Present signal is used to inform the gas gauge whether the pack is installed into or removed from
the system. In the host system, this pin is grounded. The PRES pin of the bq40z50-R1 is occasionally sampled
to test for system present. To save power, an internal pullup is provided by the gas gauge during a brief 4-μs
sampling pulse once per second. A resistor can be used to pull the signal low and the resistance must be 20 kΩ
or lower to insure that the test pulse is lower than the VIL limit. The pull-up current source is typically 10 µA to
20 µA.
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Figure 28. System Present Pull-Down Resistor
Because the System Present signal is part of the pack connector interface to the outside world, it must be
protected from external electrostatic discharge events. An integrated ESD protection on the PRES device pin
reduces the external protection requirement to just R29 for an 8-kV ESD contact rating. However, if it is possible
that the System Present signal may short to PACK+, then R28 and D4 must be included for high-voltage
protection.
Figure 29. System Present ESD and Short Protection
9.2.2.2.4 SMBus Communication
The SMBus clock and data pins have integrated high-voltage ESD protection circuits, however, adding a Zener
diode (D2 and D3) and series resistor (R24 and R26) provides more robust ESD performance.
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The SMBus clock and data lines have internal pulldown. When the gas gauge senses that both lines are low
(such as during removal of the pack), the device performs auto-offset calibration and then goes into SLEEP
mode to conserve power.
Figure 30. ESD Protection for SMB Communication
9.2.2.2.5 FUSE Circuitry
The FUSE pin of the bq40z50-R1 is designed to ignite the chemical fuse if one of the various safety criteria is
violated. The FUSE pin also monitors the state of the secondary-voltage protection IC. Q5 ignites the chemical
fuse when its gate is high. The 7-V output of the bq294700 is divided by R16 and R6, which provides adequate
gate drive for Q5 while guarding against excessive back current into the bq294700 if the FUSE signal is high.
Using C3 is generally a good practice, especially for RFI immunity. C3 may be removed, if desired, because the
chemical fuse is a comparatively slow device and is not affected by any sub-microsecond glitches that come from
the FUSE output during the cell connection process.
Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 35
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Figure 31. FUSE Circuit
When the bq40z50-R1 is commanded to ignite the chemical fuse, the FUSE pin activates to give a typical 8-V
output. The new design makes it possible to use a higher Vgs FET for Q5. This improves the robustness of the
system, as well as widens the choices for Q5.
9.2.2.3 Secondary-Current Protection
The bq40z50-R1 provides secondary overcurrent and short-circuit protection, cell balancing, cell voltage
multiplexing, and voltage translation. The following discussion examines Cell and Battery Inputs, Pack and FET
Control, Temperature Output, and Cell Balancing.
9.2.2.3.1 Cell and Battery Inputs
Each cell input is conditioned with a simple RC filter, which provides ESD protection during cell connect and acts
to filter unwanted voltage transients. The resistor value allows some trade-off for cell balancing versus safety
protection.
The integrated cell balancing FETs allow the AFE to bypass cell current around a given cell or numerous cells,
effectively balancing the entire battery stack. External series resistors placed between the cell connections and
the VCx I/O pins set the balancing current magnitude. The internal FETs provide a 200-Ωresistance (2 V < VDS
< 4 V). Series input resistors between 100 Ωand 1 kΩare recommended for effective cell balancing.
The BAT input uses a diode (D1) to isolate and decouple it from the cells in the event of a transient dip in voltage
caused by a short-circuit event.
Also, as described in High-Current Path, the top and bottom nodes of the cells must be sensed at the battery
connections with a Kelvin connection to prevent voltage sensing errors caused by a drop in the high-current PCB
copper.
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Figure 32. Cell and BAT Inputs
9.2.2.3.2 External Cell Balancing
Internal cell balancing can only support up to 10 mA. External cell balancing provide as another option for faster
cell balancing. For details, refer to the application note, Fast Cell Balancing Using External MOSFET (SLUA420).
9.2.2.3.3 PACK and FET Control
The PACK and VCC inputs provide power to the bq40z50-R1 from the charger. The PACK input also provides a
method to measure and detect the presence of a charger. The PACK input uses a 100-Ωresistor; whereas, the
VCC input uses a diode to guard against input transients and prevents mis-operation of the date driver during
short-circuit events.
Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 37
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Figure 33. bq40z50-R1 PACK and FET Control
The N-channel charge and discharge FETs are controlled with 5.1-kΩseries gate resistors, which provide a
switching time constant of a few microseconds. The 10-MΩresistors ensure that the FETs are off in the event of
an open connection to the FET drivers. Q4 is provided to protect the discharge FET (Q3) in the event of a
reverse-connected charger. Without Q4, Q3 can be driven into its linear region and suffer severe damage if the
PACK+ input becomes slightly negative.
Q4 turns on in that case to protect Q3 by shorting its gate to source. To use the simple ground gate circuit, the
FET must have a low gate turn-on threshold. If it is desired to use a more standard device, such as the 2N7002
as the reference schematic, the gate should be biased up to 3.3 V with a high-value resistor. The bq40z50-R1
device has the capability to provide a current-limited charging path typically used for low battery voltage or low
temperature charging. The bq40z50-R1 device uses an external P-channel, pre-charge FET controlled by PCHG.
9.2.2.3.4 Temperature Output
For the bq40z50-R1 device, TS1, TS2, TS3, and TS4 provide thermistor drive-under program control. Each pin
can be enabled with an integrated 18-kΩ(typical) linearization pullup resistor to support the use of a 10-kΩat
25°C (103) NTC external thermistor such as a Mitsubishi BN35-3H103. The reference design includes four 10-kΩ
thermistors: RT1, RT2, RT3, and RT4. The bq40z50-R1 device supports up to four external thermistors. Connect
unused thermistor pins to VSS.
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Figure 34. Thermistor Drive
9.2.2.3.5 LEDs
Three LED control outputs provide constant current sinks for the driving external LEDs. These outputs are
configured to provide voltage and control for up to 5 LEDs. No external bias voltage is required. Unused
LEDCNTL pins can remain open or they can be connected to VSS. The DISP pin should be connected to VSS, if
the LED feature is not used.
Figure 35. LEDs
9.2.2.3.6 Safety PTC Thermistor
The bq40z50-R1 device provides support for a safety PTC thermistor. The PTC thermistor is connected between
the PTC pin and VSS. It can be placed close to the CHG/DSG FETs to monitor the temperature. The PTC pin
outputs a very small current, typical ~370 nA, and the PTC fault will be triggered at ~0.7 V typical. A PTC fault is
one of the permanent failure modes. It can only be cleared by a POR.
To disable this feature, connect a 10-kΩresistor between PTC and VSS.
Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 39
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Figure 36. PTC Thermistor
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10.70
10.75
10.80
10.85
10.90
10.95
11.00
±40 ±20 0 20 40 60 80 100 120
Over-Current Delay Time (mS)
Temperature (C)
C013
432
434
436
438
440
442
444
446
448
450
452
±40 ±20 0 20 40 60 80 100 120
SC Charge Current Delay Time (S)
Temperature (C)
C014
±87.2
±87.0
±86.8
±86.6
±86.4
±86.2
±86.0
±40 ±20 0 20 40 60 80 100 120
SCD 1 Protection Threshold (mV)
Temperature (C)
C011
±173.6
±173.5
±173.4
±173.3
±173.2
±173.1
±173.0
±172.9
±40 ±20 0 20 40 60 80 100 120
SCD 2 Protection Threshold (mV)
Temperature (C)
C012
±25.8
±25.6
±25.4
±25.2
±25.0
±24.8
±24.6
±40 ±20 0 20 40 60 80 100 120
OCD Protection Threshold (mV)
Temperature (C)
C009
86.2
86.4
86.6
86.8
87.0
87.2
87.4
±40 ±20 0 20 40 60 80 100 120
SCC Protection Threshold (mV)
Temperature (C)
C010
bq40z50-R1
www.ti.com
SLUSCB3 –JULY 2015
9.2.3 Application Curves
Threshold setting is 25 mV. Threshold setting is 25 mV.
Figure 37. Overcurrent Discharge Protection Threshold Vs. Figure 38. Short Circuit Charge Protection Threshold Vs.
Temperature Temperature
Threshold setting is –177.7 mV.
Threshold setting is –88.85 mV.
Figure 40. Short Circuit Discharge 2 Protection Threshold
Figure 39. Short Circuit Discharge 1 Protection Threshold Vs. Temperature
Vs. Temperature
Threshold setting is 11 ms. Threshold setting is 465 µs.
Figure 41. Overcurrent Delay Time Vs. Temperature Figure 42. Short Circuit Charge Current Delay Time Vs.
Temperature
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10 Power Supply Recommendations
The device manages its supply voltage dynamically according to the operation conditions. Normally, the BAT
input is the primary power source to the device. The BAT pin should be connected to the positive termination of
the battery stack. The input voltage for the BAT pin ranges from 2.2 V to 26 V.
The VCC pin is the secondary power input, which activates when the BAT voltage falls below minimum Vcc. This
allows the device to source power from a charger (if present) connected to the PACK pin. The VCC pin should
be connected to the common drain of the CHG and DSG FETs. The charger input should be connected to the
PACK pin.
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11 Layout
11.1 Layout Guidelines
A battery fuel gauge circuit board is a challenging environment due to the fundamental incompatibility of high-
current traces and ultra-low current semiconductor devices. The best way to protect against unwanted trace-to-
trace coupling is with a component placement, such as that shown in Figure 43, where the high-current section is
on the opposite side of the board from the electronic devices. Clearly this is not possible in many situations due
to mechanical constraints. Still, every attempt should be made to route high-current traces away from signal
traces, which enter the bq40z50-R1 directly. IC references and registers can be disturbed and in rare cases
damaged due to magnetic and capacitive coupling from the high-current path. Note that during surge current and
ESD events, the high-current traces appear inductive and can couple unwanted noise into sensitive nodes of the
gas gauge electronics, as illustrated in Figure 44.
Figure 43. Separating High- and Low-Current Sections Provides an Advantage in Noise Immunity
Figure 44. Avoid Close Spacing Between High-Current and Low-Level Signal Lines
Kelvin voltage sensing is extremely important in order to accurately measure current and top and bottom cell
voltages. Place all filter components as close as possible to the device. Route the traces from the sense resistor
in parallel to the filter circuit. Adding a ground plane around the filter network can add additional noise immunity.
Figure 45 and Figure 46 demonstrates correct kelvin current sensing.
Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 43
Product Folder Links: bq40z50-R1
Current Direction
To SRP – SRN pin or HSRP – HSRN pin
RSNS
Current Sensing Direction
bq40z50-R1
SLUSCB3 –JULY 2015
www.ti.com
Layout Guidelines (continued)
Figure 45. Sensing Resistor PCB Layout
Figure 46. Sense Resistor, Ground Shield, and Filter Circuit Layout
11.1.1 Protector FET Bypass and Pack Terminal Bypass Capacitors
The general principle is to use wide copper traces to lower the inductance of the bypass capacitor circuit. In
Figure 47, an example layout demonstrates this technique.
Figure 47. Use Wide Copper Traces to Lower the Inductance of Bypass Capacitors C1, C2, and C3
44 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: bq40z50-R1
CHARGE
AND
DISCHARGE
PATH
CURRENT
FILTER
SENSE
RESISTOR
2ND LEVEL
PROTECTOR
LEDS
THERMISTORS
bq40z50-R1
www.ti.com
SLUSCB3 –JULY 2015
Layout Guidelines (continued)
11.1.2 ESD Spark Gap
Protect SMBus Clock, Data, and other communication lines from ESD with a spark gap at the connector. The
pattern in Figure 48 recommended, with 0.2-mm spacing between the points.
Figure 48. Recommended Spark-Gap Pattern Helps Protect Communication Lines from ESD
11.2 Layout Example
Figure 49. Top Layer
Figure 50. Internal Layer 1
Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 45
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FILTER
COMPONENTS
CHARGE
AND
DISCHARGE
PATH
bq40z50-R1
SLUSCB3 –JULY 2015
www.ti.com
Layout Example (continued)
Figure 51. Internal Layer 2
Figure 52. Bottom Layer
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the bq40z50-R1 Technical Reference Manual (SLUUBC1).
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
Impedance Track, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.5 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 47
Product Folder Links: bq40z50-R1
PACKAGE OPTION ADDENDUM
www.ti.com 8-Dec-2017
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
BQ40Z50RSMR-R1 ACTIVE VQFN RSM 32 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ40Z50
BQ40Z50RSMT-R1 ACTIVE VQFN RSM 32 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ40Z50
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 8-Dec-2017
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
BQ40Z50RSMR-R1 VQFN RSM 32 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
BQ40Z50RSMT-R1 VQFN RSM 32 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Jul-2015
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
BQ40Z50RSMR-R1 VQFN RSM 32 3000 367.0 367.0 35.0
BQ40Z50RSMT-R1 VQFN RSM 32 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Jul-2015
Pack Materials-Page 2
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