Digital Signal Processors MSC8156/MSC8156E Broadband Wireless Access DSP Advanced 45 nm, six-core DSP for 3G-LTE, TDD-LTE, WiMAX, 3GPP-HSPA and TD-SCDMA Overview device that previously required multiple packet networks while significantly offloading The MSC8156/MSC8156E is a six-core DSP discrete parts. processing from the DSP cores. The optional based on Freescale's new SC3850 StarCore technology and designed to advance the capabilities of wireless broadband equipment. It delivers industry-leading performance and power savings, leveraging 45 nm process technology in a highly integrated SoC to provide performance equivalent to 6 GHz of a single core device. The MSC8156/MSC8156E will help equipment manufacturers and carriers create solutions and services that enable near-term, mainstream adoption of next-generation wireless standards such as 3G-LTE, WiMAX, HSPA+ and TDD-LTE. The device is designed to lower system costs by integrating functionality into a single security engine core (SEC) in the MSC8156E The MSC8156/MSC8156E DSP delivers a accelerates data plane encryption/decryption high level of performance and integration, and code protection with minimal DSP core combining six fully programmable new intervention. and enhanced SC3850 DSP cores, each running at up to 1 GHz with an architecture The MSC8156/MSC8156E embeds large highly optimized for wireless infrastructure internal memory and supports a variety applications. Developed by Freescale and of advanced, high-speed interface types, integrated on chip, the MAPLE-B baseband including two Serial RapidIO(R) interfaces, accelerator supports hardware acceleration two Gigabit Ethernet interfaces for network for Turbo and Viterbi channel decoding and for communications, a PCI Express(R) controller, DFT/iDFT and FFT/iFFT algorithms. An internal two DDR controllers for high-speed, industry RISC-based QUICC Engine subsystem standard memory interface and four multi- supports multiple networking protocols channel TDM interfaces. to guarantee reliable data transport over MSC8158/MSC8158E Block Diagram DDR Interface 64/32-bit 800 MHz DDR Interface 64/32-bit 800 MHz DDR2/DDR3 DDR2/DDR3 SDRAM Controller SDRAM Controller JTAG I/O Interrupt Concentrator M3 Memory 1056 KB UART Clocks Timers Class Reset SC3850 DSP Core 32 KB L1 I-Cache 32 KB L1 D-Cache 512 KB L2 Cache/ M2 Memory MAPLE-B Dual RISC Processors Turbo/ DFT/ FFT/ CRC Viterbi IDFT IFFT SEC DMA 4 TDMs QUICC Engine Subsystem Semaphores Virtual Interrupts I2C Other Modules Four TDMs Each Two RGMII Supporting 8 E1 SPI Optional High-Speed Serial Interface Boot ROM MSC8156E only Six DSP Cores at 1 GHz Cores Two SGMII Two Serial RapidIO(R) 1x/4x 3.125 Gbaud PCI Express(R) 1x/2x/4x Two SGMII Features and Benefits * Six StarCore DSP SC3850 core subsystems * HSSI that supports two 4x SerDes ports, including: Development Support Freescale supplies a complete set of operating at up to 1 GHz/8000 MMACS per Two Serial RapidIO controllers supporting CodeWarrior DSP development tools for core and up to 48000 MMACS per device 1x/4x operation up to 3.125 Gbaud the MSC8156/MSC8156E device. The One PCI Express controller that supports tools provide easier and more robust ways * Multi-accelerator platform engine for baseband (MAPLE-B) 1x/2x/4x operation Highly flexible, programmable Turbo and Multiplexing capability for RapidIO, Viterbi decoder supports configurable PCI Express and SGMII signals through decoding parameters. It can perform up the two SerDes ports to 200 Mbps of Turbo decoding * Four TDM interfaces (six iterations) or up to 115 Mbps of * UART and I2C interfaces K = 9 (zero tail) Viterbi decoding FFT/iFFT for sizes 128, 256, 512, 1024 or 2048 points at up to 350 million samples per second DFT/iDFT for sizes up to 1536 points at up to 175 million samples per second * Two master buses for data transfers from/to the system memory at total throughput up to 50 Gbps * High-speed, high-bandwidth CLASS fabric arbitrates between the DSP cores and other CLASS masters to M2 memory, M3 memory, DDR controllers, MAPLE-B and the configuration registers * Two DDR controllers with up to 400 MHz clock (800 MHz data) rate and 32/64bit DDR2/3 SDRAM data bus. Supports SODIMMs and up to 0.5 GB per controller architecture. Support tools include: * 16 16-bit timers * Two 32-bit general purpose timers per core for RTOS support * I/O interrupt concentrator and virtual Two Gigabit Ethernet controllers supporting RGMII or SGMII Serial peripheral interface * Eclipse-based integrated development environment (IDE) * C and C++ compiler with in-line assembly * Librarian interrupt support * Eight hardware semaphores * Multicore debugger * 32 GPIO ports multiplexed with interface * Royalty-free RTOS * Software simulator signals and IRQ inputs * Optional SEC (MSC8156E) optimized to * Profiler process all the encryption/decryption * High-speed run control algorithms associated with IPsec, IKE, * Host platform support WTLS/WAP, SSL/TLS, AES, DES, RC-4, SNOW-3G and Kasumi for 3G-LTE and 3GPP * Boot options: Ethernet, Serial RapidIO, I2C and SPI * MSC8156ADS development board * MSC8156EVM evaluation module Contact your local sales office or representative for availability. * JTAG Test Access Port (TAP) and boundary Supports: development environment gives designers * Eight software watchdog timers * Dual RISC core QUICC Engine subsystem the DSP cores 3G-LTE, TD-SCDMA or WiMAX system, the capabilities of the MSC8156/MSC8156E * 32-channel DMA controller parallel packet processing independent of systems. Whether the application targets a everything they need to exploit the advanced * Three input clocks and five PLLs operating at up to 500 MHz provides for designers to develop optimized DSP scan architecture designed to comply with IEEE 1149.1TM standard for profiling and performance monitoring support * Reduced power dissipation with wait, stop and power down low-power standby modes * Optimized power management circuitry * Technology: CMOS 45 nm SOI technology in 29 mm, 29 mm, 783 ball, FC-PBGA package Learn More: Freescale, the Freescale logo, StarCore, QUICC Engine and CodeWarrior technologies are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. QUICC Engine is the trademark of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. (c) 2010 Freescale Semiconductor, Inc. Document Number: MSC8156FS REV 3 For current information about Freescale products and documentation, please visit freescale.com/DSP.