Semiconductor Components Industries, LLC, 2002
February, 2002 – Rev. 8 1Publication Order Number:
SN74LS157/D
SN74LS157
Quad 2-Input Multiplexer
The LSTTL/MSI SN74LS157 is a high speed Quad 2-Input
Multiplexer. Four bits of data from two sources can be selected using
the common Select and Enable inputs. The four buffered outputs
present the selected data in the true (non-inverted) form. The LS157
can also be used to generate any four of the 16 different functions of
two variables. The LS157 is fabricated with the Schottky barrier diode
process for high speed and is completely compatible with all
ON Semiconductor TTL families.
•Schottky Process for High Speed
•Multifunction Capability
•Non-Inverting Outputs
•Input Clamp Diodes Limit High Speed Termination Effects
•Special Circuitry Ensures Glitch Free Multiplexing
•ESD > 3500 Volts
GUARANTEED OPERATING RANGES
Symbol Parameter Min Typ Max Unit
VCC Supply Voltage 4.75 5.0 5.25 V
TAOperating Ambient
Temperature Range 0 25 70 °C
IOH Output Current – High –0.4 mA
IOL Output Current – Low 8.0 mA
LOW
POWER
SCHOTTKY
SOIC
D SUFFIX
CASE 751B
PLASTIC
N SUFFIX
CASE 648
16
1
16
1
SOEIAJ
M SUFFIX
CASE 966
16
1
Device Package Shipping
ORDERING INFORMATION
SN74LS157N 16 Pin DIP 2000 Units/Box
SN74LS157D SOIC–16 38 Units/Rail
SN74LS157DR2 SOIC–16 2500/Tape & Reel
SN74LS157M SOEIAJ–16 See Note 1
SN74LS157MEL SOEIAJ–16
1. For ordering information on the EIAJ version of
the SOIC package, please contact your local
ON Semiconductor representative.
See Note 1
http://onsemi.com
SN74LS157
http://onsemi.com
2
Figure 1. Connection Diagram DIP (TOP VIEW)
Common Select Input
Enable (Active LOW) Input
Data Inputs from Source 0
Data Inputs from Source 1
Multiplexer Outputs
S
E
I0a – I0d
I1a – I1d
Za – Zd
1.0 U.L.
1.0 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
0.5 U.L.
0.5 U.L.
0.25 U.L.
0.25 U.L.
5 U.L.
NOTES: a) 1 TTL Unit Load (U.L.) = 40 A HIGH/1.6 mA LOW.
HIGH LOW
(Note a)LOADING
PIN NAMES
VCC = PIN 16
GND = PIN 8
NOTE: The Flatpak version has the same
pinouts (Connection Diagram) as
the Dual In-Line Package.
14 13 12 11 10 9
123456 7
16 15
8
VCC
S
EI0c I1c ZcI1d
I0d Zd
I0a I1a ZaI0b I1b ZbGND
Figure 2. Logic Symbol
15 2 3 5 6 14 13 11 10
1
4 7 12 9
EI
0a I1a I0b I1b I0c I1c I0d I1d
ZaZbZcZd
S
SN74LS157
http://onsemi.com
3
Figure 3. Logic Diagram
14 126
7
3
4
5
9
11
12
10
13 15
VCC = PIN 16
GND = PIN 8
= PIN NUMBERS
FUNCTIONAL DESCRIPTION
The LS157 is a Quad 2-Input Multiplexer fabricated with
the Schottky barrier diode process for high speed. It selects
four bits of data from two sources under the control of a
common Select Input (S). The Enable Input (E) is active
LOW. When E is HIGH, all of the outputs (Z) are forced
LOW regardless of all other inputs.
The LS157 is the logic implementation of a 4-pole,
2-position switch where the position of the switch is
determined by the logic levels supplied to the Select Input.
The logic equations for the outputs are:
Za = E ⋅ (I1a ⋅ S + I0a ⋅S) Zb = E ⋅(I1b ⋅S + I0b ⋅S)
Zc = E ⋅ (I1c ⋅S + I0c ⋅S)Z
d = E ⋅(I1d ⋅S + I0d ⋅S)
A common use of the LS157 is the moving of data from
two groups of registers to four common output busses. The
particular register from which the data comes is determined
by the state of the Select Input. A less obvious use is as a
function generator. The LS157 can generate any four of
the 16 dif ferent functions of two variables with one variable
common. This is useful for implementing highly irregular
logic.
TRUTH TABLE
ENABLE SELECT
INPUT INPUTS OUTPUT
E S I0I1Z
H X X X L
L H X LL
L H X HH
L L L XL
L L H X H
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
SN74LS157
http://onsemi.com
4
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol Parameter Min Typ Max Unit Test Conditions
VIH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage for
All Inputs
VIL Input LOW Voltage 0.8 VGuaranteed Input LOW Voltage for
All Inputs
VIK Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA
VOH Output HIGH Voltage 2.7 3.5 V VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
V
Out
p
ut LOW Voltage
0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN,
V V or V
VOL Output LOW Voltage 0.35 0.5 V IOL = 8.0 mA VIN = VIL or VIH
per Truth Table
I
IH
Input HIGH Current
I0, I1
E, S 20
40 µA VCC = MAX, VIN = 2.7 V
IIH
I0, I1
E, S 0.1
0.2 mA VCC = MAX, VIN = 7.0 V
IIL
Input LOW Current
I0, I1
E, S –0.4
–0.8 mA VCC = MAX, VIN = 0.4 V
IOS Short Circuit Current (Note 2) –20 –100 mA VCC = MAX
ICC Power Supply Current 16 mA VCC = MAX
2. Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (TA = 25°C)
Limits
Symbol Parameter Min Typ Max Unit Test Conditions
tPLH
tPHL Propagation Delay
Data to Output 9.0
9.0 14
14 ns Figure 2
tPLH
tPHL Propagation Delay
Enable to Output 13
14 20
21 ns Figure 1 VCC = 5.0 V
CL = 15 pF
tPLH
tPHL Propagation Delay
Select to Output 15
18 23
27 ns Figure 2
L
AC WAVEFORMS
Figure 1. Figure 2.
VIN
VOUT
1.3 V
tPHL
1.3 V
tPLH
1.3 V 1.3 V
VIN
VOUT
1.3 V
tPHL
1.3 V
tPLH
1.3 V 1.3 V
SN74LS157
http://onsemi.com
5
PACKAGE DIMENSIONS
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
–A–
B
FC
S
HGD
J
L
M
16 PL
SEATING
18
916
K
PLANE
–T–
M
A
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.740 0.770 18.80 19.55
B0.250 0.270 6.35 6.85
C0.145 0.175 3.69 4.44
D0.015 0.021 0.39 0.53
F0.040 0.70 1.02 1.77
G0.100 BSC 2.54 BSC
H0.050 BSC 1.27 BSC
J0.008 0.015 0.21 0.38
K0.110 0.130 2.80 3.30
L0.295 0.305 7.50 7.74
M0 10 0 10
S0.020 0.040 0.51 1.01
SN74LS157
http://onsemi.com
6
PACKAGE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
18
16 9
SEATING
PLANE
F
J
M
RX 45
G
8 PLP
–B–
–A–
M
0.25 (0.010) B S
–T–
D
K
C
16 PL
S
B
M
0.25 (0.010) A S
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A9.80 10.00 0.386 0.393
B3.80 4.00 0.150 0.157
C1.35 1.75 0.054 0.068
D0.35 0.49 0.014 0.019
F0.40 1.25 0.016 0.049
G1.27 BSC 0.050 BSC
J0.19 0.25 0.008 0.009
K0.10 0.25 0.004 0.009
M0 7 0 7
P5.80 6.20 0.229 0.244
R0.25 0.50 0.010 0.019
SN74LS157
http://onsemi.com
7
PACKAGE DIMENSIONS
HE
A1
DIM MIN MAX MIN MAX
INCHES
--- 2.05 --- 0.081
MILLIMETERS
0.05 0.20 0.002 0.008
0.35 0.50 0.014 0.020
0.18 0.27 0.007 0.011
9.90 10.50 0.390 0.413
5.10 5.45 0.201 0.215
1.27 BSC 0.050 BSC
7.40 8.20 0.291 0.323
0.50 0.85 0.020 0.033
1.10 1.50 0.043 0.059
0
0.70 0.90 0.028 0.035
--- 0.78 --- 0.031
A1
HE
Q1
LE
10 0
10
LEQ1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
M
L
DETAIL P
VIEW P
c
A
b
e
M
0.13 (0.005) 0.10 (0.004)
1
16 9
8
D
Z
E
A
b
c
D
E
e
L
M
Z
M SUFFIX
SOEIAJ PACKAGE
CASE 966–01
ISSUE O
SN74LS157
http://onsemi.com
8
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or
death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold
SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable
attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
JAPAN: ON Semiconductor, Japan Customer Focus Center
4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031
Phone: 81–3–5740–2700
Email: r14525@onsemi.com
ON Semiconductor Website: http://onsemi.com
For additional information, please contact your local
Sales Representative.
SN74LS157/D
Literature Fulfillment:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada
Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada
Email: ONlit@hibbertco.com
N. American Technical Support: 800–282–9855 Toll Free USA/Canada
