PIC32MX1XX/2XX PIC32MX1XX/2XX Family Silicon Errata and Data Sheet Clarification The PIC32MX1XX/2XX family devices that you have received conform functionally to the current Device Data Sheet (DS61168D), except for the anomalies described in this document. The errata described in this document will be addressed in future revisions of the PIC32MX1XX/2XX silicon. Note: The silicon issues discussed in the following pages are for silicon revisions with the Device and Revision IDs listed in Table 1 and Table 2. The last column of each table represents the latest silicon revision for the devices listed. The silicon issues are summarized in Table 3. For example, to identify the silicon revision level using MPLAB IDE in conjunction with the REAL ICETM in-circuit emulator: 1. 2. 3. 4. Data Sheet clarifications and corrections start on page 7, following the discussion of silicon issues. The silicon revision level can be identified using the current version of MPLAB(R) IDE and Microchip's programmers, debuggers and emulation tools, which are available at the Microchip corporate web site (www.microchip.com). TABLE 1: Note: If you are unable to extract the silicon revision level, please contact your local Microchip sales office for assistance. The Device and Revision ID values for the various silicon revisions are provided in Table 1 and Table 2. SILICON DEVREV VALUES FOR DEVICES WITH 16/32 KB FLASH Part Number PIC32MX110F016B Device ID(1) Revision ID for Silicon Revision(1) A0 A1 0x0 0x1 0x04A07053 PIC32MX110F016C 0x04A09053 PIC32MX110F016D 0x04A0B053 PIC32MX210F016B 0x04A01053 PIC32MX210F016C 0x04A03053 PIC32MX210F016D 0x04A05053 PIC32MX120F032B 0x04A06053 PIC32MX120F032C 0x04A08053 PIC32MX120F032D 0x04A0A053 PIC32MX220F032B 0x04A00053 PIC32MX220F032C 0x04A02053 PIC32MX220F032D 0x04A04053 Note 1: Using the appropriate interface, connect the device to the REAL ICE in-circuit emulator. From the main menu in MPLAB IDE, select Configure>Select Device, and then select the target part number in the dialog box. Select the MPLAB hardware tool (Debugger>Select Tool). Perform a "Connect" operation to the device (Debugger>Connect). Depending on the development tool used, the part number and Device Revision ID value appear in the Output window. Refer to the "PIC32MX Flash Programming Specification" (DS61145) for detailed information on Device and Revision IDs for your specific device. (c) 2011-2012 Microchip Technology Inc. DS80531B-page 1 PIC32MX1XX/2XX TABLE 2: SILICON DEVREV VALUES FOR DEVICES WITH 64/128 KB FLASH Part Number PIC32MX130F064B Device ID(1) A0 A1 0x0 0x1 0x04D07053 PIC32MX130F064C 0x04D09053 PIC32MX130F064D 0x04D0B053 PIC32MX230F064B 0x04D01053 PIC32MX230F064C 0x04D03053 PIC32MX230F064D 0x04D05053 PIC32MX150F128B 0x04D08053 PIC32MX150F128C 0x04D08053 PIC32MX150F128D 0x04D0A053 PIC32MX250F128B 0x04D00053 PIC32MX250F128C 0x04D02053 PIC32MX250F128D 0x04D04053 Note 1: Revision ID for Silicon Revision(1) Refer to the "PIC32MX Flash Programming Specification" (DS61145) for detailed information on Device and Revision IDs for your specific device. DS80531B-page 2 (c) 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX TABLE 3: SILICON ISSUE SUMMARY Affected Device Module Feature Item # Issue Summary Voltage Regulator BOR 1. Device may not exit Brown-out Reset (BOR) state if a BOR event occurs. Oscillator Clock Switch 2. If a Fail-Safe Clock Monitor (FSCM) event occurs when Primary Oscillator (POSC) mode is used, firmware clock switch requests to switch from FRC mode will fail. I CTM Slave Mode 3. The I2C module does not respond to address 0x78 when the STRICT and A10M bits are cleared in the I2CxCON register. USB UIDLE Interrupt 4. UIDLE interrupts cease if the UIDLE interrupt flag is cleared. ADC -- 5. The DNL parameter of the ADC module is not within the published data sheet specifications when the ADC module is operating at maximum conversion rate. ADC CTMU Calibration 6. Open selection for Channel 0 positive input is not functional. ADC Conversion Trigger from INT0 Interrupt 7. The ADC module conversion triggers occur on the rising edge of the INT0 signal even when INT0 is configured to generate an interrupt on the falling edge. Parallel Master Port (PMP) Address Pins 8. When the Parallel Master Port (PMP) module is enabled, address pins cannot be used as GPIO output pins. I/O Ports RA0 and RA1 Output 9. Output High Voltage (VOH) on pins RA0 and RA1 is not within the published data sheet specification. CPU Data Write to a Peripheral 10. A data write operation by the CPU to a peripheral may be repeated if an interrupt occurs during initial write operation. 11. A clock signal is present on the CLKO pin, regardless of the clock source and setting of the CLKO Enable Configuration bit, during a Power-on Reset (POR) condition. 2 Oscillator Clock Out Silicon Flash Revision Memory (KB) A0 A1 16/32 X 64/128 X 16/32 X X 64/128 X X 16/32 X X 64/128 X X 16/32 X X 64/128 X X 16/32 X X 64/128 X X 16/32 X X 16/32 X X 64/128 X X 16/32 X X 64/128 X X 16/32 X X 64/128 X X 16/32 X X 64/128 X X 16/32 X X 64/128 X X 64/128 Legend: An `X' indicates the issue is present in this revision of silicon; Shaded cells with an Em dash (`--') indicate that this silicon revision does not exist for this issue; Blank cells indicate an issue has been corrected in this revision of silicon. (c) 2011-2012 Microchip Technology Inc. DS80531B-page 3 PIC32MX1XX/2XX Silicon Errata Issues Note: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. The table provided in each issue indicates which issues exist for a particular revision of silicon based on memory size. 1. Module: Voltage Regulator Device may not exit the Brown-out Reset (BOR) state if a BOR event occurs. 3. Module: I2CTM The slave address, 0x78, is one of a group of reserved addresses. It is used as the upper byte of a 10-bit address when 10-bit addressing is enabled. The I2C module control register allows the programmer to enable both 10-bit addressing and strict enforcement of reserved addressing, with the A10M and STRICT bits, respectively. When both bits are cleared, the device should respond to the reserved address 0x78, but does not. Work around Work arounds None. Work around 1: Affected Silicon Revisions VDD must remain within the published specification (see parameter DC10 of the device data sheet). A0 A1 16/32 64/128 X X X X Work around 2: Reset the device by providing the Power-on Reset (POR) condition. Affected Silicon Revisions Device Silicon Revision Device Flash Memory (KB) A0 16/32 64/128 X X A1 2. Module: Oscillator If the Primary Oscillator (POSC) mode is implemented and a Fail-Safe Clock Monitor (FSCM) event occurs (failure of the external primary clock), the internal clock source will switch to the FRC oscillator. Subsequent firmware clock switch requests from the FRC oscillator to other clock sources will fail and the device will continue to execute on the FRC oscillator. Upon repair of the external clock source and a power-on state, the device will resume operation with the primary oscillator clock source. Work around None. Affected Silicon Revisions Device Silicon Revision Device Flash Memory (KB) A0 A1 16/32 64/128 X X X X DS80531B-page 4 Device Silicon Revision Device Flash Memory (KB) 4. Module: USB In the case where the bus has been idle for more than 3 ms, and the UIDLE interrupt flag is set, if software clears the interrupt flag and the bus remains idle, the UIDLE interrupt flag will not be set again. Work around Software can leave the UIDLE bit set until it has received some indication of bus resumption (i.e., Resume, Reset, SOF, or Error). Note: Resume and Reset are the only interrupts that should be gotten following UIDLE assertion. If, at any point in time, the UIDLE bit is set, it should be okay to suspend the USB module (as long as this code is protected by the GUARD and/or ACTPEND logic). Note that this will require software to clear the UIDLE interrupt enable bit to exit the USB ISR (if using interrupt driven code). Affected Silicon Revisions Device Silicon Revision Device Flash Memory (KB) A0 A1 16/32 64/128 X X X X (c) 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX 5. Module: ADC 7. Module: ADC If the ADC module is configured to operate at a maximum conversion rate of 1.1 Msps, missing codes are possible every 25 codes and the DNL parameter will not be within the published specification. Work around Configure the ADC module to operate for a maximum conversion rate of 500 ksps. Affected Silicon Revisions Device Silicon Revision Device Flash Memory (KB) A0 A1 16/32 64/128 X X X X If the ADC module is used in conjunction with the CTMU module in Absolute Capacitive/Time Measurement mode, Channel 0 positive input must remain open (CH0SA<3:0> = 1111 or CH0SB<3:0> = 1111) during calibration step. However, open selection for Channel 0 positive input is not functional and connects this input to AVSS. Work around Use the ADC and CTMU modules for relative capacitive/time measurement, where calibration step is not required. Affected Silicon Revisions 16/32 64/128 Work around Generate ADC conversion triggers on the rising edge of the INT0 signal. Alternately, use external circuitry to invert the signal appearing at the INT0 pin, so that a falling edge of the input signal is detected as a rising edge by the INT0 pin. Affected Silicon Revisions 6. Module: ADC Device Flash Memory (KB) When the ADC module is configured to start conversion on an external interrupt (SSRC<2:0> = 001), the start of conversion always occurs on a rising edge detected at the INT0 pin, even when the INT0 pin has been configured to generate an interrupt on a falling edge (INT0EP = 0). Device Silicon Revision A0 A1 X X Device Silicon Revision Device Flash Memory (KB) A0 A1 16/32 64/128 X X X X 8. Module: Parallel Master Port (PMP) If the PMP module is enabled, any pin with a PMP addressing capability (PMAx) cannot be used as a general purpose output pin, even when the corresponding PTEN<10:0> bit in the PMAEN register is cleared. All other functionality on these pins, including GPIO input functionality is not affected. Work around To use a GPIO pin as an output when this pin is shared with PMP addressing functionality and PMP is enabled, do the following: 1. 2. Enable PMP addressing by setting the corresponding PTEN<10:0> bit in the PMAEN register. Instead of using corresponding LATx registers to output GPIO data, use the PMADDR register. Affected Silicon Revisions (c) 2011-2012 Microchip Technology Inc. Device Silicon Revision Device Flash Memory (KB) A0 A1 16/32 64/128 X X X X DS80531B-page 5 PIC32MX1XX/2XX 9. Module: I/O Ports 11. Module: Oscillator Output High Voltage (VOH) on pins RA0 and RA1 is not within the published data sheet specification. Work around Disable slew rate control of the I2C1 module by setting the DISSLW bit (I2C1CON<9>). Affected Silicon Revisions Device Flash Memory (KB) Device Silicon Revision A0 A1 X X X X 16/32 64/128 10. Module: CPU During normal operation, if a CPU write operation is interrupted by an incoming interrupt, it should be aborted (not completed) and resumed after the interrupt is serviced. However, some of these write operations may not be aborted, resulting in a double write to peripherals by the CPU (the first write during the interrupt and the second write after the interrupt is serviced). A clock signal is present on the CLKO pin, regardless of the clock source and setting of the CLKO Enable Configuration bit, OSCIOFNC (DEVCFG1<10>), during a Power-on Reset (POR) condition. Work around Do not connect the CLKO pin to a device that would be adversely affected by rapid pin toggling or a frequency other than that defined by the oscillator configuration. Do not use the CLKO pin as an input if the device connected to the CLKO pin would be adversely affected by the pin driving a signal out. Affected Silicon Revisions Device Flash Memory (KB) 16/32 64/128 Device Silicon Revision A0 A1 X X X X Work around Most peripherals are not affected by this issue, as a double write will not have a negative impact. However, the following communication peripherals will double-send data if their respective transmit buffers are written twice: SPI, I2C, UART and PMP. To avoid double transmission of data, utilize DMA to transfer data to these peripherals. Affected Silicon Revisions Device Flash Memory (KB) 16/32 64/128 DS80531B-page 6 Device Silicon Revision A0 A1 X X X X (c) 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX Data Sheet Clarifications APPENDIX A: The following typographic corrections and clarifications are to be noted for the latest version of the device data sheet (DS61168D): Rev A Document (10/2011) Note: Corrections are shown in bold. Where possible, the original bold text formatting has been removed for clarity. None to report at this time. REVISION HISTORY Initial release of this document; issued for revision A0 silicon. Includes silicon issues 1 (Voltage Regulator), 2 (Oscillator), 3 (I2CTM), 4 (USB), 5 (ADC), 6 (ADC), 7 (ADC), 8 (Parallel Master Port (PMP)), and 9 (I/O Ports). Rev B Document (2/2012) Added silicon revision A1 for 16/32 KB Flash devices. Added 64/128 KB Flash devices. Added silicon issues 10 (CPU) and 11 (Oscillator). (c) 2011-2012 Microchip Technology Inc. DS80531B-page 7 PIC32MX1XX/2XX NOTES: DS80531B-page 8 (c) 2011-2012 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2011-2012, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-62076-046-8 Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. (c) 2011-2012 Microchip Technology Inc. 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