74VHC32MTCX_NL - Fairchild Semiconductor

November 1992

Revised February 2005

74VHC32 Quad 2-Input OR Gate

74VHC32

Quad 2-Input OR Gate

General Descript ion

The VHC 3 2 is an advanced h igh speed CM OS 2 -In put OR

Gate fabricated with silicon gate CMOS technology. It

achieves the high speed operation similar to equivalent

Bipolar Schottky TTL while maintaining the CMOS low

power dissipation.

The internal circuit is composed of 4 stages including buffer

output, which provide high noise immunity and stable out-

put. An input protection circuit ensures that 0V to 7V can be

applied to the input pins without regar d to the supply volt-

age. This device can be used to interface 5V to 3V systems

and two supp ly systems such as battery back up. This cir-

cuit preven ts device destruc tion du e to mismatch ed supply

and input voltages.

Features

■High Speed:

tPD

3.8 ns (typ) at VCC

■Low Power Dissipatio n:

ICC

A (Max) at TA

■High Noise Immunity: VNIH

VNIL

28% VCC (Min)

■Power down protection is provided on all inputs

■Low Noise: VOLP

0.8V (Max)

■Pin and Function Compatible with 74HC32

Ordering Code:

Surface m ount pack ages are also avai lable on Tape and Reel. Specify by appending the suffix let t er “X” to the o rdering code.

Pb-Free package per JEDEC J-STD-020B.

Note 1: “_NL” indicat es Pb-Free package (per JED EC J -STD-0 20B). Devic e availa ble in Tape and Reel on ly.

Logic Symbol

IEEE/IEC

Pin Descriptions

Connection Diagram

Truth Table

Order Number Package Package Description

Number

74VHC32M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

74VHC32MX_NL

(Note 1) M14A Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

74VHC32SJ M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74VHC32MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

74VHC32MTCX_NL

(Note 1) MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide

74VHC32N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Pin Names Description

An, BnInputs

OnOutputs

ABO

HHH

LHH

HLH

LLL

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74VHC32

Absolute Maximum Ratings(Note 2) Recommended Operating

Conditions (Note 3)

Note 2: Absolute Maximum Ratings are values beyond which the device

may be damaged or have its useful life impaired. The databook specifica-

tions should be met, without exception, to ensure that the system design is

reliable over its power supply, temperature, and output/input loading vari-

ables. Fairchild does not recommend operation outside databook specifica-

tions.

Note 3: Unu s ed inputs m us t be held HIG H or LOW. They may no t float.

DC Electrical Characteristi cs

Noise Characteristics

Note 4: Parameter guaranteed by design.

Supply Voltage (VCC)



0.5V to



7.0V

DC Input Voltage (VIN)



0.5V to



7.0V

DC Output Voltage (VOUT)



0.5V to VCC



0.5V

Input Diode Current (IIK)



20 mA

Output Diode Current (IOK)

20 mA

DC Output Curren t (IOUT)

25 mA

DC VCC/GND Current (ICC)

50 mA

Storage Temper atu re (TSTG)



C to



150

Lead Temperature (TL)

(Soldering, 10 seconds) 260

Supply Voltage (VCC) 2.0V to



5.5V

Input Voltage (VIN)0V to



5.5V

Output Voltage (VOUT) 0V to VCC

Operati ng Temperature (T OPR)



C to



Input Rise and Fall Time (tr, tf)

VCC

3.3V

0.3V 0

100 ns/V

VCC

5.0V

0.5V 0

20 ns/V

Symbol Parameter VCC

(V)



C to



CUnits Conditions

Min Typ Max Min Max

VIH HIGH Level 2.0 1.50 1.50 V

Input V oltage 3.0



5.5 0.7 VCC 0.7 VCC

VIL LOW Level 2.0 0.50 0.50 V

Input V oltage 3.0



5.5 0.3 VCC 0.3 VCC

VOH HIGH Level 2.0 1.9 2.0 1.9 VIN

VIH IOH



Output Voltage 3.0 2.9 3.0 2.9 V or VIL

4.5 4.4 4.5 4.4

3.0 2.58 2.48 VIOH



4 mA

4.5 3.94 3.80 IOH



8 mA

VOL LOW Level 2.0 0.0 0.1 0.1 VIN

VIH IOL

Output Voltage 3.0 0.0 0.1 0.1 V or VIL

4.5 0.0 0.1 0.1

3.0 0.36 0.44 VIOL

4 mA

4.5 0.36 0.44 IOL

8 mA

IIN Input Leakage 0



5.5

0.1

1.0

5.5V or GND

Current

ICC Quiescent Supply Current 5.5 2.0 20.0

VCC or GND

Symbol Parameter VCC

(V)

CUnits Conditions

Typ Limit

VOLP Quiet Output Maximum 5.0 0.3 0.8 V CL

50 pF

(Note 4) Dynamic VOL

VOLV Quiet Output Minimum 5.0



0.3



0.8 V CL

50 pF

(Note 4) Dynamic VOL

VIHD Minimum HIGH Level 5.0 3.5 V CL

50 pF

(Note 4) Dynamic Input Voltage

VILD Maximum LOW Level 5.0 1.5 V CL

50 pF

(Note 4) Dynamic Input Voltage

3 www.fairchildsemi.com

74VHC32

AC Electrical Characteristics

Note 5: CPD is defined as the value of t he internal equivalent ca pac ita nc e w hich is c alculate d f rom the o perating c urrent consum pt ion without load. Average

operati ng c urrent ca n be obtained by the eq uat ion: ICC (opr.)

CPD * VCC * fIN



ICC/4 (per gate).

Symbol Parameter VCC

(V)



C to



CUnits Conditions

Min Typ Max Min Max

tPHL Propagation Delay 3.3 5.5 7.9 1.0 9.5 ns CL

15 pF

tPLH

0.3 8.0 11.4 1.0 13.0 CL

50 pF

5.0 3.8 5.5 1.0 6.5 ns CL

15 pF

0.5 5.3 7.5 1.0 8.5 CL

50 pF

CIN Input Capacitance 4 10 10 pF VCC

Open

CPD Power Dissipation 14 pF (Note 5)

Capacitance

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74VHC32

Physical Dimensions inches (millimeters) unless otherwise noted

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

Package Number M14A

5 www.fairchildsemi.com

74VHC32

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M14D

www.fairchildsemi.com 6

74VHC32

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Package Number MTC14

7 www.fairchildsemi.com

74VHC32 Quad 2-Input OR Gate

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Package Number N14A

Fairchild does not assum e any responsibility for use of any circuitry described, no cir cuit patent licenses are im plied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life suppor t de vices o r syst ems are dev ic es or syste ms

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instruct ions fo r use provided in the l abe li ng, can be re a-

sonably expected to result in a significant injury to the

user.

2. A crit ical com ponen t in any com ponen t of a life s uppor t

device or system whose failure to perform can be rea-

sonabl y e xpec ted to cause th e fa i lure of the l ife suppor t

device or system, or to affect its safety or effectiveness.