AK8181B 3.3V LVPECL 1:4 Clock Fanout Buffer AK8181B Features Description The AK8181B is a member of AKM' LVPECL clock fanout buffer family designed for telecom, networking and computer applications, requiring a range of clocks with high performance and low skew. The AK8181B distributes 4 buffered clocks. Four differential 3.3V LVPECL outputs Selectable LVTTL/LVCMOS CLK or crystal input Clock output frequency up to 266MHz Output skew : 10ps typical Part-to-part skew : 200ps maximum Propagation delay : 1.4ns maximum Additive phase jitter(RMS) : 0.057ps(typical) Operating Temperature Range: -40 to +85C Package: 20-pin TSSOP (Pb free) Pin compatible with ICS8535I-31 AK8181B are derived from AKM' long-termexperienced clock device technology, and enable clock output to perform low skew. The AK8181B is available in a 20-pin TSSOP package. Block Diagram MS1417-E-02 Dec-2012 -1- AK8181B Pin Descriptions Package: 20-Pin TSSOP (Top View) Pin No. 1 Pin Name VSS Pin Type Pullup down PWR -- 2 CLK_EN IN Pull up 3 CLK_SEL IN Pull down Description Negative power supply Synchronizing clock output enable (LVCMOS/LVTTL) Pin is connected to VDD by internal resistor. (typ. 51k High (Open): clock outputs follow clock input. Low: Q outputs are forced low, Qn outputs are forced high. CLK Select Input (LVCMOS/LVTTL) Pin is connected to VSS by internal resistor. (typ. 51k High: selects XTAL input Low (Open): selects CLK input LVCMOS/LVTTL Clock Input Pin is connected to VSS by internal resistor. (typ. 51k 4 CLK IN Pull down 5 NC -- -- 6 XTAL_IN IN -- 7 XTAL_OUT OUT -- *When using CLK input (CLK_SEL=Low), it should be connected to VSS or opened. 8 NC -- -- No connect *When using crystal input (CLK_SEL=High), it should be connected to VSS or opened. No connect Crystal oscillator interface *When using CLK input (CLK_SEL=Low), it should be connected to VSS or opened. Crystal oscillator interface 9 NC -- -- No connect 10 VDD PWR -- Positive power supply 11, 12 Q3n, Q3 OUT -- Differential clock output (LVPECL) 13 VDD PWR -- Positive power supply 14, 15 Q2n, Q2 OUT -- Differential clock output (LVPECL) 16, 17 Q1n, Q1 OUT -- Differential clock output (LVPECL) 18 VDD PWR -- Positive power supply 19, 20 Q0n, Q0 OUT -- Differential clock output (LVPECL) Ordering Information Part Number Marking Shipping Packaging Package Temperature Range AK8181B AK8181B Tape and Reel 20-pin TSSOP -40 to 85 C Dec-2012 MS1417-E-02 -2- AK8181B Absolute Maximum Rating Over operating free-air temperature range unless otherwise noted Items Supply voltage Input voltage (2) Symbol Ratings Unit VDD -0.3 to 4.6 V Vin -0.5 to VDD+0.5 V IIN 10 mA Tstg -55 to 150 C (2) Input current (any pins except supplies) Storage temperature (1) Note (1) Stress beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under "Recommended Operating Conditions" is not implied. Exposure to absolute-maximum-rating conditions for extended periods may affect device reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. (2) VSS=0V ESD Sensitive Device This device is manufactured on a CMOS process, therefore, generically susceptible to damage by excessive static voltage. Failure to observe proper handling and installation procedures can cause damage. AKM recommends that this device is handled with appropriate precautions. Recommended Operation Conditions Parameter Operating temperature Supply voltage (1) Symbol Conditions Ta VDD Min Typ -40 VDD5%, VSS=0V (1) Power of 3.3V requires to be supplied from a single source. be located close to each VDD pin. 3.135 3.3 Max Unit 85 C 3.465 V A decoupling capacitor of 0.1F for power supply line should Pin Characteristics Parameter Symbol Conditions Min Typ Max Unit Input Capacitance CIN 4 pF Input Pullup Resistor RPU 51 k Input Pulldown Resistor RPD 51 k MS1417-E-02 Dec-2012 -3- AK8181B DC Characteristics All specifications at VDD= 3.3V5%, VSS=0V, Ta: -40 to +85C, unless otherwise noted Parameter Symbol Input High Voltage VIH Input Low Voltage VIL CLK, CLK_SEL Input High Current CLK_EN Input Low Current IH IL CLK_EN (1) MIN TYP 2.0 MAX Unit VDD+0.3 V 0.8 V Vin=VDD=3.465V -0.3 150 A Vin=VDD=3.465V 5 A Vin=VSS, CLK, CLK_SEL Output High Voltage Conditions VDD=3.465V Vin=VSS, VDD=3.465V -5 A -150 A VOH VDD-1.4 VDD-0.9 V VOL VDD-2.0 VDD-1.7 V VSWING 0.6 1.0 V 60 mA MAX Unit 50 MHz Equivalent Series Resistance (ESR) 50 Shunt Capacitance 7 pF Drive Level 1 mW Output Low Voltage (1) Peak-to-Peak Output Voltage Swing Supply Current IDD (1) Outputs terminated with 50 to VDD-2V. Crystal Characteristics All specifications at VDD= 3.3V5%, VSS=0V, Ta: -40 to +85C, unless otherwise noted Parameter Conditions MIN Mode of Oscillation TYP Fundamental Frequency 12 Dec-2012 MS1417-E-02 -4- AK8181B AC Characteristics All specifications at VDD= 3.3V5%, VSS=0V, Ta: -40 to +85C, unless otherwise noted Parameter Symbol Output Frequency Propagation Delay MIN tPD (2)(3) 0.6 tsk(O) (3)(5) Part-to-Part Skew Output Rise/Fall Time (4) tr , tf MAX Unit 266 MHz 1.4 ns 10 tskPP Buffer Additive Jitter, RMS tjit Output Duty Cycle TYP fOUT (1) Output Skew (1) (2) (3) (4) (5) Conditions ps 200 155.52MHz (12kHz - 20MHz) 20% to 80% 0.057 200 DCOUT ps 46 50 ps 600 ps 54 % Measured from the VDD/2 of the input to the differential output crossing point. Defined as skew between outputs at the same supply voltage and with equal load conditions. This parameter is defined in accordance with JEDEC Standard 65. Design value. Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. MS1417-E-02 Dec-2012 -5- AK8181B Parameter Measurement Information Figure 1 3.3V Output Load Test Circuit Figure 2 Part-to-Part Skew Qxn 80% Clock Outputs Qx Qyn 80% VSWING 20% 20% tR tF Qy tsk(o) Figure 3 Output Skew Figure 4 Output Rise/Fall Time Figure 5 Propagation Delay Figure 6 Output Duty/ Pulse Width/ Period Dec-2012 MS1417-E-02 -6- AK8181B Function Table The following table shows the inputs/outputs clock state configured through the control pins. Table 1: Control Input Function Table Inputs Outputs CLK_EN CLK_SEL Selected Source Q0:Q3 Q0n:Q3n 0 0 (Open) CLK Disabled: Low Disabled: High 0 1 Disabled: Low Disabled: High 1 (Open) 0 (Open) Enabled Enabled 1 (Open) 1 Enabled Enabled XTAL_IN, XTAL_OUT CLK XTAL_IN, XTAL_OUT After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock or crystal oscillator edge as shown in Figure 7. In the active mode, the state of the outputs are a function of the CLK input as described in Table 2. Figure 7 CLK_EN Timing Diagram Table 2 Clock Input Function Table Inputs Outputs CLK Q0 : Q3 Q0n : Q3n 0 Low High 1 High Low MS1417-E-02 Dec-2012 -7- AK8181B Package Information Mechanical data : 20pin TSSOP 6.500.10 0.150.05 11 1 6.400.10 4.400.10 0.60.10 20 10 0.250.05 0.65 08 S S 1.10 MAX 0.10 0.100.05 0.900.05 Marking 20 11 b AK8181B XXXXXXX c a: b: c: #1 Pin Index Part number Date code ( 7 digits) a 10 1 RoHS Compliance All integrated circuits form Asahi Kasei Microdevices Corporation (AKM) assembled in "lead-free" packages* are fully compliant with RoHS. (*) RoHS compliant products from AKM are identified with "Pb free" letter indication on product label posted on the anti-shield bag and boxes. Dec-2012 MS1417-E-02 -8- AK8181B IMPORTANT NOTICE These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei Microdevices Corporation (AKM) or authorized distributors as to current status of the products. Descriptions of external circuits, application circuits, software and other related information contained in this document are provided only to illustrate the operation and application examples of the semiconductor products. You are fully responsible for the incorporation of these external circuits, application circuits, software and other related information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of such information contained herein. Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. AKM products are neither intended nor authorized for use as critical components Note1) in any safety, life support, or other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKM. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS1417-E-02 Dec-2012 -9-