AK8181B
MS1417-E-02 Dec-2012
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Features
Four differential 3.3V LVPECL outputs
Selectable LVTTL/LVCMOS CLK or crystal
input
Clock output frequency up to 266MHz
Output skew : 10ps typical
Part-to-part skew : 200ps maximum
Propagation delay : 1.4ns maximum
Additive phase jitter(RMS) : 0.057ps(typical)
Operating Temperature Range: -40 to +85°C
Package: 20-pin TSSOP (Pb free)
Pin compatible with ICS8535I-31
Description
The AK8181B is a member of AKM’ｓ LVPECL
clock fanout buffer family designed for telecom,
networking and computer applications, requiring a
range of clocks with high performance and low
skew. The AK8181B distributes 4 buffered
clocks.
AK8181B are derived from AKM’ｓ long-term-
experienced clock device technology, and enable
clock output to perform low skew. The AK8181B
is available in a 20-pin TSSOP package.
Block Diagram
3.3V LVPECL 1:4
Clock Fanout Buffer
AK8181B
AK8181B
Dec-2012 MS1417-E-02
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Pin Descriptions
Package: 20-Pin TSSOP (Top View)
Pin No.
Pin Name
Pin
Type
Pullup
down
Description
1
VSS
PWR
--
Negative power supply
2
CLK_EN
IN
Pull up
Synchronizing clock output enable (LVCMOS/LVTTL)
Pin is connected to VDD by internal resistor. (typ. 51kΩ
High (Open): clock outputs follow clock input.
Low: Q outputs are forced low, Qn outputs are forced high.
3
CLK_SEL
IN
Pull down
CLK Select Input (LVCMOS/LVTTL)
Pin is connected to VSS by internal resistor. (typ. 51kΩ
High: selects XTAL input Low (Open): selects CLK input
4
CLK
IN
Pull down
LVCMOS/LVTTL Clock Input
Pin is connected to VSS by internal resistor. (typ. 51kΩ
*When using crystal input (CLK_SEL=High), it should be connected
to VSS or opened.
5
NC
--
--
No connect
6
XTAL_IN
IN
--
Crystal oscillator interface
*When using CLK input (CLK_SEL=Low), it should be connected to
VSS or opened.
7
XTAL_OUT
OUT
--
Crystal oscillator interface
*When using CLK input (CLK_SEL=Low), it should be connected to
VSS or opened.
8
NC
--
--
No connect
9
NC
--
--
No connect
10
VDD
PWR
--
Positive power supply
11, 12
Q3n, Q3
OUT
--
Differential clock output (LVPECL)
13
VDD
PWR
--
Positive power supply
14, 15
Q2n, Q2
OUT
--
Differential clock output (LVPECL)
16, 17
Q1n, Q1
OUT
--
Differential clock output (LVPECL)
18
VDD
PWR
--
Positive power supply
19, 20
Q0n, Q0
OUT
--
Differential clock output (LVPECL)
Ordering Information
Part Number
Marking
Package
Temperature
Range
AK8181B
AK8181B
20-pin TSSOP
-40 to 85 °C
AK8181B
MS1417-E-02 Dec-2012
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Absolute Maximum Rating
Over operating free-air temperature range unless otherwise noted (1)
Items
Symbol
Ratings
Unit
Supply voltage (2)
VDD
-0.3 to 4.6
V
Input voltage (2)
Vin
-0.5 to VDD+0.5
V
Input current (any pins except supplies)
IIN
±10
mA
Storage temperature
Tstg
-55 to 150
C
Note
(1) Stress beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
These are stress ratings only. Functional operation of the device at these or any other conditions beyond those
indicated under “Recommended Operating Conditions” is not implied. Exposure to absolute-maximum-rating
conditions for extended periods may affect device reliability. Electrical parameters are guaranteed only over the
recommended operating temperature range.
(2) VSS=0V
This device is manufactured on a CMOS process, therefore, generically susceptible to
damage by excessive static voltage. Failure to observe proper handling and
installation procedures can cause damage. AKM recommends that this device is handled with
appropriate precautions.
Recommended Operation Conditions
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Operating temperature
Ta
-40
85
C
Supply voltage (1)
VDD
VDD5%, VSS=0V
3.135
3.3
3.465
V
(1) Power of 3.3V requires to be supplied from a single source. A decoupling capacitor of 0.1μF for power supply line should
be located close to each VDD pin.
Pin Characteristics
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Input Capacitance
CIN
4
pF
Input Pullup Resistor
RPU
51
kΩ
Input Pulldown Resistor
RPD
51
kΩ
ESD Sensitive Device
AK8181B
Dec-2012 MS1417-E-02
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DC Characteristics
All specifications at VDD= 3.3V5%, VSS=0V, Ta: -40 to +85°C, unless otherwise noted
Parameter
Symbol
Conditions
MIN
TYP
MAX
Unit
Input High Voltage
VIH
2.0
VDD+0.3
V
Input Low Voltage
VIL
-0.3
0.8
V
Input
High Current
CLK, CLK_SEL
IH
Vin=VDD=3.465V
150
μA
CLK_EN
Vin=VDD=3.465V
5
μA
Input
Low Current
CLK, CLK_SEL
IL
Vin=VSS,
VDD=3.465V
-5
μA
CLK_EN
Vin=VSS,
VDD=3.465V
-150
μA
Output High Voltage(1)
VOH
VDD-1.4
VDD-0.9
V
Output Low Voltage(1)
VOL
VDD-2.0
VDD-1.7
V
Peak-to-Peak Output
Voltage Swing
VSWING
0.6
1.0
V
Supply Current
IDD
60
mA
(1) Outputs terminated with 50Ω to VDD-2V.
Crystal Characteristics
All specifications at VDD= 3.3V5%, VSS=0V, Ta: -40 to +85°C, unless otherwise noted
Parameter
Conditions
MIN
TYP
MAX
Unit
Mode of Oscillation
Fundamental
Frequency
12
50
MHz
Equivalent Series Resistance (ESR)
50
Ω
Shunt Capacitance
7
pF
Drive Level
1
mW
AK8181B
MS1417-E-02 Dec-2012
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AC Characteristics
All specifications at VDD= 3.3V5%, VSS=0V, Ta: -40 to +85°C, unless otherwise noted
(1) Measured from the VDD/2 of the input to the differential output crossing point.
(2) Defined as skew between outputs at the same supply voltage and with equal load conditions.
(3) This parameter is defined in accordance with JEDEC Standard 65.
(4) Design value.
(5) Defined as skew between outputs on different devices operating at the same supply voltages and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
Parameter
Symbol
Conditions
MIN
TYP
MAX
Unit
Output Frequency
fOUT
266
MHz
Propagation Delay(1)
tPD
0.6
1.4
ns
Output Skew(2)(3)
tsk(O)
10
ps
Part-to-Part Skew(3)(5)
tskPP
200
ps
Buffer Additive Jitter, RMS
tjit
155.52MHz (12kHz – 20MHz)
0.057
ps
Output Rise/Fall Time(4)
tr, tf
20% to 80%
200
600
ps
Output Duty Cycle
DCOUT
46
50
54
%
AK8181B
Dec-2012 MS1417-E-02
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Parameter Measurement Information
Figure 1 3.3V Output Load Test Circuit Figure 2 Part-to-Part Skew
Clock
Outputs
80%
Qx
tsk(o)
Qxn
Qyn
Qy tRtF
20%
80%
20%
VSWING
Figure 3 Output Skew Figure 4 Output Rise/Fall Time
Figure 5 Propagation Delay Figure 6 Output Duty/ Pulse Width/ Period
AK8181B
MS1417-E-02 Dec-2012
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Function Table
The following table shows the inputs/outputs clock state configured through the control pins.
Table 1: Control Input Function Table
Inputs
Outputs
CLK_EN
CLK_SEL
Selected Source
Q0:Q3
Q0n:Q3n
0
0 (Open)
CLK
Disabled: Low
Disabled: High
0
1
XTAL_IN,
XTAL_OUT
Disabled: Low
Disabled: High
1 (Open)
0 (Open)
CLK
Enabled
Enabled
1 (Open)
1
XTAL_IN,
XTAL_OUT
Enabled
Enabled
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock or
crystal oscillator edge as shown in Figure 7. In the active mode, the state of the outputs are a function of the CLK
input as described in Table 2.
Figure 7 CLK_EN Timing Diagram
Table 2 Clock Input Function Table
Inputs
Outputs
CLK
Q0 : Q3
Q0n : Q3n
0
Low
High
1
High
Low
AK8181B
Dec-2012 MS1417-E-02
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Package Information
Mechanical data : 20pin TSSOP
20 11
101
0.10±0.05
0.90±0.05
1.10 MAX
S
4.40±0.10
0.10 S
6.50±0.10
6.40±0.10
0.6±0.10
0.15±0.05
0.25±0.05
0.65
0°～8°
Marking
RoHS Compliance
All integrated circuits form Asahi Kasei Microdevices Corporation (AKM)
assembled in “lead-free” packages* are fully compliant with RoHS.
(*) RoHS compliant products from AKM are identified with “Pb free” letter indication on
product label posted on the anti-shield bag and boxes.
a: #1 Pin Index
b: Part number
c: Date code ( 7 digits)
1
20
10
11
AK8181B
XXXXXXX
a
b
c
AK8181B
MS1417-E-02 Dec-2012
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IMPORTANT NOTICE
These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
Microdevices Corporation (AKM) or authorized distributors as to current status of the products.
Descriptions of external circuits, application circuits, software and other related information contained in this
document are provided only to illustrate the operation and application examples of the semiconductor products. You
are fully responsible for the incorporation of these external circuits, application circuits, software and other related
information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third
parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent,
intellectual property, or other rights in the application or use of such information contained herein.
Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it,
and which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety
or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or
perform may reasonably be expected to result in loss of life or in significant injury or damage to person or
property.
It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places
the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer
or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all
claims arising from the use of said product in the absence of such notification.