VNQ830E-E Quad channel high-side driver Features Type RDS(on) IOUT VCC VNQ830E-E 65 m(1) 9.5 A(1) 36 V ) s ( ct 1. Per each channel. Output current: 9.5 A CMOS compatible inputs On-state open-load detection Off-state open-load detection Output stuck to VCC detection Open drain status outputs Undervoltage shutdown Overvoltage clamp Thermal shutdown Current and power limitation Very low standby current Protection against loss of ground and loss of VCC Reverse battery protection Very low electromagnetic susceptibility Optimized electromagnetic emission r P e Description t e l o ) (s t c u d o r P e t e l o s b O Table 1. The VNQ830E-E is a quad HSD formed by assembling two VND830E-E chips in the same SO-28 package. The VND830E-E is a monolithic device made using STMicroelectronicsTM VIPowerTM M0-3 technology. s b O It is intended for driving resistive or inductive loads with one side connected to ground. Active VCC pin voltage clamp protects the device against low energy spikes (see ISO7637 transient compatibility table). The device detects open-load condition both in on-state and off-state. Output shorted to VCC is detected in the off-state. Output current limitation protects the device in overload condition. In case of long duration overload, the device limits the dissipated power to safe level up to thermal shutdown intervention. Thermal shutdown with automatic restart allows the device to recover normal operation as soon as fault condition disappears. Device summary Package SO-28 May 2010 u d o SO-28 (double island) Order codes Tube Tape and reel VNQ830E-E VNQ830ETR-E Doc ID 17459 Rev 1 1/28 www.st.com 1 VNQ830E-E Contents Contents 1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1 4 u d o GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 18 r P e 3.1.1 Solution 1: a resistor in the ground line (RGND only) . . . . . . . . . . . . . . 18 3.1.2 Solution 2: a diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . 19 t e l o 3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.3 MCU I/O protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.4 Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.5 Maximum demagnetization energy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 ) (s s b O t c u Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.1 5 d o r SO-28 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 P e Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 let so b O 6 ) s ( ct 5.1 ECOPACK(R) packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.2 SO-28 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Doc ID 17459 Rev 1 2/28 List of tables VNQ830E-E List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6 Absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal data (per island) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Power output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Switching (per each channel) (VCC = 13 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 VCC - output diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Status pin (per each channel) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Protections (per each channel) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Logic input (per each channel) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Open-load detection (per each channel) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Electrical transient requirements on VCC pin (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Electrical transient requirements on VCC pin (part 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Electrical transient requirements on VCC pin (part 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Thermal calculation according to the PCB heatsink area . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 SO-28 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r P e t e l o s b O 3/28 Doc ID 17459 Rev 1 VNQ830E-E List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Status timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Switching time waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Off-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Status leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Status low output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Status clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 On-state resistance vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 On-state resistance vs VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Open-load on-state detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Open-load off-state detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Overvoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 ILIM vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Maximum turn-off current versus load inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 SO-28 PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . 23 SP-28 thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . . 23 Thermal fitting model of a quad channel HSD in SO-28 . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 SO-28 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 SO-28 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 SO-28 tape and reel shipment (suffix "13TR") . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r P e s b O t e l o Doc ID 17459 Rev 1 4/28 VNQ830E-E 1 Block diagram and pin description Block diagram and pin description Figure 1. Block diagram VCC1,2 Vcc OVERVOLTAGE CLAMP UNDERVOLTAGE GND1,2 OUTPUT1 INPUT1 DRIVER 1 u d o CLAMP 2 STATUS1 CURRENT LIMITER 1 LOGIC OPEN-LOAD ON 1 INPUT2 ) (s OVERTEMP. 2 ct Vcc CLAMP P e s b O t e l o du ro GND3,4 ete ol OPEN-LOAD OFF 1 STATUS2 Pr DRIVER 2 OVERTEMP. 1 INPUT3 ) s ( ct CLAMP 1 s b O CURRENT LIMITER 2 OPEN-LOAD ON 2 OPEN-LOAD OFF 2 VCC3,4 3,4 OVERVOLTAGE UNDERVOLTAGE CLAMP 3 OUTPUT3 DRIVER 3 CLAMP 4 STATUS3 OVERTEMP. 3 OUTPUT2 LOGIC CURRENT LIMITER 3 DRIVER 4 OUTPUT4 OPEN-LOAD ON 3 CURRENT LIMITER 4 INPUT4 OPEN-LOAD OFF 3 OPEN-LOAD ON 4 STATUS4 OPEN-LOAD OFF 4 OVERTEMP. 4 Doc ID 17459 Rev 1 5/28 VNQ830E-E Block diagram and pin description Figure 2. Configuration diagram (top view) VCC1,2 1 VCC1,2 28 GND 1,2 OUTPUT1 INPUT1 OUTPUT1 STATUS1 OUTPUT1 STATUS2 OUTPUT2 INPUT2 OUTPUT2 VCC1,2 OUTPUT2 VCC3,4 OUTPUT3 GND 3,4 OUTPUT3 INPUT3 OUTPUT3 u d o r P e OUTPUT4 STATUS3 STATUS4 t e l o INPUT4 VCC3,4 Table 2. ) s ( ct 14 ) (s s b O 15 OUTPUT4 OUTPUT4 VCC3,4 Suggested connections for unused and not connected pins ct Connection / pin du Floating ro To ground P e Status N.C. Output Input X X X X X Through 10 K resistor t e l o s b O Doc ID 17459 Rev 1 6/28 VNQ830E-E Electrical specifications 2 Electrical specifications 2.1 Absolute maximum ratings Stressing the device above the rating listed in Table 3 may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality document. Table 3. Absolute maximum rating Symbol VCC Parameter DC supply voltage - VCC Reverse DC supply voltage - IGND DC reverse ground pin current IOUT - IOUT ISTAT DC status current VESD Electrostatic discharge (Human Body Model: R=1.5 K; C = 100 pF) - INPUT - STATUS - OUTPUT - VCC s b O t c u d o r Maximum switching energy L = 0.5 mH; RL = 0 ; Vbat = 13.5 V; Tjstart = 150 C; IL = 13.5 A) P e O bs e t e ol Reverse DC output current DC input current t e l o Ptot 41 V -0.3 IIN EMAX Unit u d o DC output current ) (s ) s ( ct Value Power dissipation (per island) at Tlead = 25 C Pr V -200 mA Internally limited A -6 A +/-10 mA +/-10 mA 4000 4000 5000 5000 V V V V 64 mJ 6.25 W Internally limited C Tj Junction operating temperature Tc Case operating temperature - 40 to 150 C Storage temperature - 55 to 150 C Tstg Doc ID 17459 Rev 1 7/28 VNQ830E-E 2.2 Electrical specifications Thermal data Table 4. Thermal data (per island) Symbol Parameter Value Unit 20 C/W Rthj-lead Thermal resistance junction-lead per chip Rthj-amb Thermal resistance junction-ambient (one chip ON) 60(1) 45(2) C/W Rthj-amb Thermal resistance junction-ambient (two chips ON) 46(1) 30(2) C/W 1. When mounted on a standard single-sided FR-4 board with 0.5 cm2 of Cu (at least 35 m thick) connected to all VCC pins. Horizontal mounting and no artificial air flow. ) s ( ct 2. When mounted on a standard single-sided FR-4 board with 6 cm2 of Cu (at least 35 m thick) connected to all VCC pins. Horizontal mounting and no artificial air flow. 2.3 u d o Electrical characteristics r P e Values specified in this section are for 8 V < VCC < 36 V; -40 C < Tj < 150 C, unless otherwise stated. t e l o (Per each channel) Figure 3. s b O Current and voltage conventions ) (s (1) t c u d o r P e t e l o s b O 1. VFn = VCCn - VOUTn during reverse battery condition. Table 5. Power output Symbol Parameter VCC(1) Operating supply voltage 5.5 13 36 V VUSD(1) Undervoltage shutdown 3 4 5.5 V VOV(1) Overvoltage shutdown 36 Test conditions Doc ID 17459 Rev 1 Min. Typ. Max. Unit V 8/28 VNQ830E-E Electrical specifications Table 5. Power output (continued) Symbol RON Parameter Test conditions Min. Typ. Max. Unit IOUT = 2 A; Tj = 25 C IOUT = 2 A; VCC > 8 V On-state resistance Off-state; VCC = 13 V; VIN = VOUT = 0 V IS(1) Off-state; VCC = 13 V; VIN = VOUT = 0 V; Tj = 25C Supply current 65 130 m m 12 40 A 12 25 A On-state; VCC = 13 V; VIN = 5 V; IOUT = 0 A IL(off1) Off-state output current VIN = VOUT = 0 V IL(off2) Off-state output current VIN = 0 V; VOUT = 3.5 V IL(off3) Off-state output current VIN = VOUT = 0 V; VCC = 13 V; Tj = 125 C IL(off4) Off-state output current VIN = VOUT = 0 V; VCC = 13 V; Tj =25 C e t e ol 1. Per island. ) (s Table 6. du 0 -75 o r P 7 mA 50 A 0 A 5 A 3 A s b O Switching (per each channel) (VCC = 13 V) Symbol Parameter Min. Typ. RL = 6.5 from VIN rising edge to VOUT = 1.3 V - 50 - s RL = 6.5 from VIN falling edge to VOUT = 11.7 V - 50 - s dVOUT/dt(on) Turn-on voltage slope RL = 6.5 from VOUT = 1.3 V to VOUT = 10.4 V - See Figure 21 - V/s dVOUT/dt(off) Turn-off voltage slope RL = 6.5 from VOUT = 11.7 V to VOUT = 1.3 V - See Figure 22 - V/s td(on) td(off) t c u Turn-on delay time d o r P e Turn-off delay time t e l o s b O ) s ( ct 5 Table 7. Test conditions Max. Unit VCC - output diode Symbol Parameter Test conditions VF Forward on voltage - IOUT = 1.2 A; Tj = 150 C Doc ID 17459 Rev 1 Min. Typ. Max. Unit - - 0.6 V 9/28 VNQ830E-E Electrical specifications Table 8. Status pin (per each channel) Symbol Parameter Test conditions Min. Typ. Max. Unit VSTAT Status low output voltage ISTAT = 1.6 mA 0.5 V ILSTAT Status leakage current Normal operation; VSTAT = 5 V 10 A CSTAT Status pin input capacitance Normal operation; VSTAT = 5 V 100 pF VSCL Status clamp voltage ISTAT = 1 mA ISTAT = - 1 mA 8 V V Table 9. Parameter Test conditions Shutdown temperature Min. ) s ( ct Reset temperature Thyst Thermal hysteresis tSDL Status delay in overload conditions Tj > TTSD Ilim Current limitation VCC = 13 V 5.5 V < VCC < 36 V Pr 135 e t e ol bs O ) Turn-off output clamp voltage IOUT = 2 A; L = 6 mH Typ. u d o 150 TR Vdemag 6.8 - 0.7 Protections (per each channel)(1) Symbol TTSD 6 7 9.5 175 Max. Unit 200 C C 15 13.5 C 20 s 18 18 A A VCC-41 VCC-48 VCC-55 V s ( t c 1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles. Pr Table 10. Symbol s b O e t e ol u d o Logic input (per each channel) Parameter Test conditions Min. Typ. Max. Unit 1.25 V VIL Low level input voltage VIH High level input voltage 3.25 V VI(hyst) Input hysteresis voltage 0.5 V IIL Low level input current VIN = 1.5 V 1 A IIH High level input current VIN = 3.25 V Input clamp voltage IIN = 1 mA IIN = -1 mA VICL Doc ID 17459 Rev 1 6 6.8 - 0.7 10 A 8 V V 10/28 VNQ830E-E Electrical specifications Table 11. Open-load detection (per each channel) Symbol Parameter Test conditions IOL Open-load on-state detection threshold VIN = 5 V tDOL(on) Open-load on-state detection delay IOUT = 0 A Open-load off-state voltage detection threshold VIN = 0 V VOL tDOL(off) Min. Typ. Max. Unit 50 115 200 mA 200 s 3.5 V 1000 s 1.5 2.9 Open-load detection delay at turn-off Figure 4. ) s ( ct Status timings OPEN -LOAD STATUS TIMING (with external pull-up) IOUT < IOL VOUT > VOL VINn OVERTEMP STATUS TIMING VINn r P e t e l o VSTATn u d o Tj > TTSD VSTATn tDOL(off) ) (s Figure 5. s b O tDOL(on) tSDL tSDL Switching time waveforms t c u d o r P e t e l o s b O Doc ID 17459 Rev 1 11/28 VNQ830E-E Electrical specifications Table 12. Truth table Conditions Input Output Status Normal operation L H L H H H Current limitation L H H L X X H (Tj < TTSD) H (Tj > TTSD) L Overtemperature L H L L H L Undervoltage L H L L X X Overvoltage L H L L Output voltage > VOL L H H H Output current < IOL L H L H ) (s r P e u d o t e l o ) s ( ct H H L H H L s b O t c u d o r P e t e l o s b O Doc ID 17459 Rev 1 12/28 VNQ830E-E Electrical specifications Table 13. Electrical transient requirements on VCC pin (part 1) ISO T/R Test levels 7637/1 Test pulse I II III IV Delays and impedance 1 - 25 V - 50 V - 75 V - 100 V 2 ms, 10 2 + 25 V + 50 V + 75 V + 100 V 0.2 ms, 10 3a - 25 V - 50 V - 100 V - 150 V 0.1 s, 50 3b + 25 V + 50 V + 75 V + 100 V 0.1 s, 50 4 -4V -5V -6V -7V 100 ms, 0.01 5 + 26.5 V + 46.5 V + 66.5 V + 86.5 V 400 ms, 2 Table 14. Electrical transient requirements on VCC pin (part 2) ISO T/R Test levels results I II 1 C C 2 C C 3a C 3b C 4 C b O s ( t c 5 Table 15. s b O let IV C C C C C C C C C C C E E E so u d o Electrical transient requirements on VCC pin (part 3) Pr Class e t e ol C III C C )- u d o r P e 7637/1 Test pulse ) s ( ct Contents C All functions of the device are performed as designed after exposure to disturbance. E One or more functions of the device is not performed as designed after exposure and cannot be returned to proper operation without replacing the device. Doc ID 17459 Rev 1 13/28 VNQ830E-E Electrical specifications Figure 6. Waveforms NORMAL OPERATION INPUTn LOAD VOLTAGEn STATUSn UNDERVOLTAGE VUSDhyst VCC VUSD INPUTn ) s ( ct LOAD VOLTAGEn STATUS r P e OVERVOLTAGE VCC<VOV VCC > VOV t e l o VCC INPUTn LOAD VOLTAGEn STATUSn ) (s t c u INPUTn od LOAD VOLTAGEn r P e STATUSn t e l o O bs u d o undefined s b O OPEN-LOAD with external pull-up VOUT > VOL VOL OPEN-LOAD without external pull-up INPUTn LOAD VOLTAGEn STATUSn Tj TTSD TR OVERTEMPERATURE INPUTn LOAD CURRENTn STATUSn Doc ID 17459 Rev 1 14/28 VNQ830E-E Electrical specifications 2.4 Electrical characteristics curves Figure 7. Off-state output current Figure 8. IL(off1) (A) lih (A) 0.9 6 0.8 5.5 Off state Vcc=13V Vin=Vout=0V 0.7 High level input current 5 Vin=3.25V 4.5 0.6 4 0.5 3.5 3 0.4 2.5 0.3 ) s ( ct 2 0.2 1.5 0.1 1 0 u d o 0.5 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 Tc (C) Figure 9. 50 75 Tc (C) Input clamp voltage 100 125 150 175 r P e Figure 10. Status leakage current Ilstat (A) t e l o Vicl (V) 0.2 12 0.195 11 Vstat=5V s b O 0.19 Iin=1mA 10 0.185 9 )- 8 7 t(s 6 c u d 5 4 3 2 -50 -25 0 Figure 11. ete 50 75 0.175 0.17 0.165 0.16 0.155 0.15 -50 100 125 150 -25 0 25 50 175 75 100 125 150 175 Tc (C) Tc (C) Status low output voltage l o s b O 25 o r P 0.18 Figure 12. Status clamp voltage Vscl (V) Vstat (V) 10 0.8 9 0.7 Istat=1mA Istat=1.6mA 8 0.6 7 0.5 6 0.4 5 0.3 4 0.2 3 0.1 2 0 -50 -25 0 25 50 75 100 125 150 175 -50 Tc (C) Doc ID 17459 Rev 1 -25 0 25 50 75 100 125 150 175 Tc (C) 15/28 VNQ830E-E Electrical specifications Figure 13. On-state resistance vs Tcase Figure 14. On-state resistance vs VCC Ron (mOhm) Ron (mOhm) 160 120 140 105 Iout=2A Vcc=8V; 13V & 36V 120 Tc=150C 90 100 75 80 60 60 45 40 30 20 15 Tc=25C Tc=25 Tc=-40C Iout=2A 0 -25 0 25 50 75 100 125 150 175 5 10 15 Tc (C) 4.5 140 3.5 120 )- 110 t(s 100 c u d 90 -25 0 e t e ol o r P 25 50 75 100 125 40 Vin=0V s b O 4 Vcc=13V Vin=5V -50 u d o 35 t e l o 5 150 70 30 r P e Vol (V) 80 25 Figure 16. Open-load off-state detection threshold Iol (mA) 130 20 Vcc (V) Figure 15. Open-load on-state detection threshold 3 2.5 2 1.5 1 0.5 0 150 175 -50 -25 0 25 Tc (C) 50 75 100 125 150 175 100 125 150 175 Tc (C) Figure 17. Input high level Figure 18. Input low level Vih (V) bs Vil (V) 3.6 O ) s ( ct 0 -50 2.6 3.4 2.4 3.2 2.2 3 2 2.8 1.8 2.6 1.6 2.4 1.4 2.2 1.2 2 -50 -25 0 25 50 75 Tc (C) 100 125 150 175 1 -50 -25 0 25 50 75 Tc (C) Doc ID 17459 Rev 1 16/28 VNQ830E-E Electrical specifications Figure 19. Input hysteresis voltage Figure 20. Overvoltage shutdown Vhyst (V) Vov (V) 2 70 65 1.75 60 1.5 55 50 1.25 45 1 40 35 0.75 30 0.5 25 ) s ( ct 20 0.25 15 0 -50 -25 0 25 50 75 100 125 150 175 10 -50 -25 0 25 Tc (C) 100 125 u d o 150 175 150 175 Figure 22. Turn-off voltage slope dVout/dt(on) (Vms) r P e dVout/dt(off) (Vms) 800 500 t e l o 450 Vcc=13V Rl=6.5Ohm 600 75 Tc (C) Figure 21. Turn-on voltage slope 700 50 400 s b O 350 500 Vcc=13V Rl=6.5Ohm 300 )- 400 s ( t c 300 200 u d o 100 0 -50 -25 0 e t e ol Pr 25 50 75 100 250 200 150 100 50 0 125 150 -50 175 0 25 50 75 100 125 Tc (C) Tc (C) Figure 23. ILIM vs Tcase Figure 24. Undervoltage shutdown Ilim (A) Vusd (V) 30 10 s b O -25 9 25 8 Vcc=13V 20 7 6 15 5 10 4 3 5 2 0 1 -50 -25 0 25 50 75 100 125 150 175 -50 Tc (C) -25 0 25 50 75 100 125 150 175 Tc (C) Doc ID 17459 Rev 1 17/28 VNQ830E-E 3 Application information Application information Figure 25. Application schematic +5V +5V +5V VCC1,2 VCC3,4 Rprot STATUS1 Rprot INPUT1 ) s ( ct Dld Rprot STATUS2 Rprot INPUT2 C Rprot OUTPUT1 u d o r P e Rprot INPUT3 Rprot STATUS4 )- Rprot INPUT4 s b O s ( t c du e t e ol Note: s b O 3.1 3.1.1 o r P t e l o STATUS3 +5V +5V OUTPUT2 OUTPUT3 OUTPUT4 GND1,2 GND3,4 RGND VGND DGND Channels 3 & 4 have the same internal circuit as channel 1 & 2. GND protection network against reverse battery This section provides two solutions for implementing a ground protection network against reverse battery. Solution 1: a resistor in the ground line (RGND only) This can be used with any type of load. The following show how to dimension the RGND resistor: 1. RGND 600m V / 2 (IS(on)max) 2. RGND ( - VCC) / (- IGND) Doc ID 17459 Rev 1 18/28 VNQ830E-E Application information where - IGND is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device's datasheet. Power dissipation in RGND (when VCC < 0 during reverse battery situations) is: PD = (- VCC)2 / RGND This resistor can be shared amongst several different HSDs. Please note that the value of this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the maximum on-state currents of the different devices. Please note that, if the microprocessor ground is not shared by the device ground, then the RGND produces a shift (IS(on)max * RGND) in the input thresholds and the status output values. This shift varies depending on how many devices are ON in the case of several high side drivers sharing the same RGND. ) s ( ct If the calculated power dissipation requires the use of a large resistor, or several devices have to share the same resistor, then ST suggests using Section 3.1.2 described below. 3.1.2 Solution 2: a diode (DGND) in the ground line u d o r P e A resistor (RGND = 1 k) should be inserted in parallel to DGND if the device is driving an inductive load. This small signal diode can be safely shared amongst several different HSD. Also in this case, the presence of the ground network produces a shift (~600mV) in the input threshold and the status output values if the microprocessor ground is not common with the device ground. This shift does not vary if more than one HSD shares the same diode/resistor network. t e l o ) (s 3.2 Load dump protection s b O t c u Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the VCC maximum DC rating. The same applies if the device is subject to transients on the VCC line that are greater than those shown in Table 13. 3.3 d o r P e MCU I/O protection s b O t e l o If a ground protection network is used and negative transients are present on the VCC line, the control pins are pulled negative. ST suggests to insert a resistor (Rprot) in line to prevent the microcontroller I/O pins from latching up. The value of these resistors is a compromise between the leakage current of microcontroller and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of microcontroller I/Os: - VCCpeak / Ilatchup Rprot (VOHC-VIH-VGND) / IIHmax Example For the following conditions: VCCpeak= - 100 V and Ilatchup 20 mA; VOHC 4.5 V 5 k Rprot 65 k. Recommended values are: Rprot = 10 k Doc ID 17459 Rev 1 19/28 VNQ830E-E 3.4 Application information Open-load detection in off-state Off-state open-load detection requires an external pull-up resistor (RPU) connected between OUTPUT pin and a positive supply voltage (VPU) like the +5 V line used to supply the microprocessor. The external resistor has to be selected according to the following requirements: 1. No false open-load indication when load is connected: in this case we have to avoid VOUT to be higher than VOlmin; this results in the following condition VOUT = (VPU / (RL + RPU))RL < VOlmin. 2. No misdetection when load is disconnected: in this case the VOUT has to be higher than VOLmax; this results in the following condition RPU < (VPU - VOLmax) / IL(off2) ) s ( ct Because Is(OFF) may significantly increase if Vout is pulled high (up to several mA), the pullup resistor RPU should be connected to a supply that is switched OFF when the module is in standby. u d o The values of VOLmin, VOLmax and IL(off2) are available in the Chapter 2: Electrical specifications. r P e Figure 26. Open-load detection in off-state let V b a tt. o s b V CC IN P U T O ) D R IV E R + L O G IC s ( t c du STATUS e t e l o r P V PU R PU IL (o ff2 ) OUT + R V OL RL GROUND o s b O Doc ID 17459 Rev 1 20/28 VNQ830E-E 3.5 Application information Maximum demagnetization energy Figure 27. Maximum turn-off current versus load inductance ) s ( ct u d o r P e t e l o ) (s A = single pulse at TJstart = 150 C s b O t c u B= repetitive pulse at TJstart = 100 C C= repetitive pulse at TJstart = 125 C d o r Conditions: VCC = 13.5 V P e t e l o VIN, IL Demagnetization Demagnetization Demagnetization s b O t Note: Values are generated with RL = 0 . In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves B and C. Doc ID 17459 Rev 1 21/28 VNQ830E-E Package and PCB thermal data 4 Package and PCB thermal data 4.1 SO-28 thermal data Figure 28. SO-28 PC board ) s ( ct u d o r P e Note: Layout condition of Rth and Zth measurements (PCB FR4 area = 58 mm x 58 mm, PCB thickness = 2 mm, Cu thickness = 35 m, Copper areas: 0.5 cm2, 3 cm2, 6 cm2). Table 16. Thermal calculation according to the PCB heatsink area Chip 1 Chip 2 t e l o Tjchip1 s b O Tjchip2 Note On Off RthA x Pdchip1 + Tamb Off On RthC x Pdchip2 + Tamb On On RthB x (Pdchip1 + Pdchip2) + Tamb On On (RthA x Pdchip1) + RthC x Pdchip2 + Tamb (RthA x Pdchip2) + RthC x Pdchip1 + Tamb Pdchip1 Pdchip2 RthC x Pdchip1 + Tamb )- t(s c u d RthA x Pdchip2 + Tamb RthB x (Pdchip1 + Pdchip2) + Tamb Pdchip1 = Pdchip2 o r P RthA = thermal resistance junction to ambient with one chip ON RthB = thermal resistance junction to ambient with both chips ON and Pdchip1 = Pdchip2 e t e ol RthC = mutual thermal resistance s b O Doc ID 17459 Rev 1 22/28 VNQ830E-E Package and PCB thermal data Figure 29. Rthj-amb vs PCB copper area in open box free air condition RTHj_am b (C/W) 70 60 50 RthA 40 ) s ( ct RthB 30 RthC 20 10 0 1 r P e u d o 2 3 4 5 PCB Cu heatsink area (cm ^2)/island 6 7 t e l o s b O Figure 30. SP-28 thermal impedance junction ambient single pulse ) (s t c u d o r P e t e l o s b O Doc ID 17459 Rev 1 23/28 VNQ830E-E Package and PCB thermal data Equation 1: pulse calculation formula Z TH = R TH + Z THtp ( 1 - ) where = tp T Figure 31. Thermal fitting model of a quad channel HSD in SO-28 Tj_1 P d1 T j _2 C1 C2 C3 C4 C5 C6 R1 R2 R3 R4 R5 R6 C 13 R 13 P d2 C 14 R 17 Tj_3 ) s ( ct R 14 C7 C8 C9 R7 R8 R9 r P e C 10 C 11 P d3 T j _4 P d4 Table 17. s b O ol ete C 15 R 15 u d o R 18 let R 10 o s b C 16 R 16 O ) s ( t c R 11 C 12 R 12 T_am b Thermal parameters u d o Area / island (cm2) Footprint R1 = R7 = R13 = R15 (C/W) 0.15 R2 = R8 = R14 = R16 (C/W) 0.7 R3 = R9 (C/W) 1.8 R4 = R10 (C/W) 10 R5 = R11 (C/W) 15 R6 = R12 (C/W) 30 C1 = C7 = C13 = C15 (W.s/C) 0.0005 C2 = C8 = C14 = C16 (W.s/C) 0.003 C3 = C9 (W.s/C) 0.015 C4 = C10 (W.s/C) 0.15 C5 = C11 (W.s/C) 1.5 C6 = C12 (W.s/C) 5 R17 = R18 (C/W) 150 Pr Doc ID 17459 Rev 1 6 13 8 24/28 VNQ830E-E Package and packing information 5 Package and packing information 5.1 ECOPACK(R) packages In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. Figure 32. SO-28 package dimensions ) s ( ct u d o r P e t e l o Table 18. SO-28 mechanical data Pr A s b O ct u d o Symbol e t e ol ) (s s b O Min. Millimeters Typ. Max. 2.65 a1 0.10 0.30 b 0.35 0.49 b1 0.23 0.32 C 0.50 c1 45 (typ.) D 17.7 18.1 E 10.00 10.65 e 1.27 e3 16.51 F 7.40 7.60 L 0.40 1.27 S 8 (max.) Doc ID 17459 Rev 1 25/28 VNQ830E-E 5.2 Package and packing information SO-28 packing information Figure 33. SO-28 tube shipment (no suffix) C Base Q.ty Bulk Q.ty Tube length ( 0.5) A B C ( 0.1) B 28 700 532 3.5 13.8 0.6 All dimensions are in mm. ) s ( ct u d o A r P e Figure 34. SO-28 tape and reel shipment (suffix "13TR") let so ) (s b O Reel dimensions Base Q.ty Bulk Q.ty A (max) B (min) C ( 0.2) F G (+ 2 / -0) N (min) T (max) t c u 1000 1000 330 1.5 13 20.2 16.4 60 22.4 d o r P e Tape dimensions According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 1986 s b O t e l o Tape width Tape hole spacing Component spacing Hole diameter Hole diameter Hole position Compartment depth Hole spacing W P0 ( 0.1) P D ( 0.1/-0) D1 (min) F ( 0.05) K (max) P1 ( 0.1) All dimensions are in mm. 16 4 12 1.5 1.5 7.5 6.5 2 End Start Top cover tape No components Components No components 500mm min Empty components pockets saled with cover tape. 500mm min User direction of feed Doc ID 17459 Rev 1 26/28 VNQ830E-E 6 Revision history Revision history Table 19. Document revision history Date Revision 03-May-2010 1 Changes Initial release. ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r P e t e l o s b O Doc ID 17459 Rev 1 27/28 VNQ830E-E ) s ( ct Please Read Carefully: u d o Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. r P e All ST products are sold pursuant to ST's terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. t e l o No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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