VNQ830E-E - STMicroelectronics, Inc.

May 2010 Doc ID 17459 Rev 1 1/28

VNQ830E-E

Quad channel high-side driver

Features

■Output current: 9.5 A

■CMOS compatible inputs

■On-state open-load detection

■Off-state open-load detection

■Output stuck to VCC detection

■Open drain status outputs

■Undervoltage shutdown

■Overvoltage clamp

■Thermal shutdown

■Current and power limitation

■Very low standby current

■Protection against loss of ground and loss of

VCC

■Reverse battery protection

■Very low electromagnetic susceptibility

■Optimized electromagnetic emission

Description

The VNQ830E-E is a quad HSD formed by

assembling two VND830E-E chips in the same

SO-28 package. The VND830E-E is a monolithic

device made using STMicroelectronics™

VIPower™ M0-3 technology.

It is intended for driving resistive or inductive

loads with one side connected to ground. Active

VCC pin voltage clamp protects the device against

low energy spikes (see ISO7637 transient

compatibility table).

The device detects open-load condition both in

on-state and off-state. Output shorted to VCC is

detected in the off-state. Output current limitation

protects the device in overload condition. In case

of long duration overload, the device limits the

dissipated power to safe level up to thermal

shutdown intervention. Thermal shutdown with

automatic restart allows the device to recover

normal operation as soon as fault condition

disappears.

Type RDS(on) IOUT VCC

VNQ830E-E 65 mΩ(1)

1. Per each channel.

9.5 A(1) 36 V

SO-28 (double island)

Table 1. Device summary

Package

Order codes

Tube Tape and reel

SO-28 VNQ830E-E VNQ830ETR-E

www.st.com

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VNQ830E-E Contents
Doc ID 17459 Rev 1 2/28
Contents
Block diagram and pin description  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical specifications  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  7
2 Thermal data   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  8
3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  8
4 Electrical characteristics curves  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  15
Application information   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1 GND protection network against reverse battery  . . . . . . . . . . . . . . . . . . .  18
1.1 Solution 1: a resistor in the ground line (RGND only)   . . . . . . . . . . . . . . 18
1.2 Solution 2: a diode (DGND) in the ground line   . . . . . . . . . . . . . . . . . . . . 19
2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  19
3 MCU I/O protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  19
4 Open-load detection in off-state  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  20
5 Maximum demagnetization energy   . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  21
Package and PCB thermal data  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1 SO-28 thermal data  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  22
Package and packing information  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1 ECOPACK® packages  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  25
2 SO-28 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  26
Revision history   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
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List of tables VNQ830E-E
3/28 Doc ID 17459 Rev 1
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Suggested connections for unused and not connected pins  . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. Absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 4. Thermal data (per island) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 5. Power output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 6. Switching (per each channel) (VCC = 13 V)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 7. VCC - output diode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 8. Status pin (per each channel). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 9. Protections (per each channel) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 10. Logic input (per each channel) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 11. Open-load detection (per each channel)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 12. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 13. Electrical transient requirements on VCC pin (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 14. Electrical transient requirements on VCC pin (part 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 15. Electrical transient requirements on VCC pin (part 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 16. Thermal calculation according to the PCB heatsink area . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 17. Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 18. SO-28 mechanical data  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 19. Document revision history  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
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VNQ830E-E List of figures
Doc ID 17459 Rev 1 4/28
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Configuration diagram (top view)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Current and voltage conventions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. Status timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 5. Switching time waveforms  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 6. Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 7. Off-state output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 8. High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 9. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 10. Status leakage current  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 11. Status low output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 12. Status clamp voltage  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 13. On-state resistance vs Tcase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 14. On-state resistance vs VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 15. Open-load on-state detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 16. Open-load off-state detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 17. Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 18. Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 19. Input hysteresis voltage  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 20. Overvoltage shutdown  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 21. Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 22. Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 23. ILIM vs Tcase  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 24. Undervoltage shutdown  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 25. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 26. Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 27. Maximum turn-off current versus load inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 28. SO-28 PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 29. Rthj-amb vs PCB copper area in open box free air condition   . . . . . . . . . . . . . . . . . . . . . . 23
Figure 30. SP-28 thermal impedance junction ambient single pulse   . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 31. Thermal fitting model of a quad channel HSD in SO-28. . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 32. SO-28 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 33. SO-28 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 34. SO-28 tape and reel shipment (suffix “13TR”)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
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VNQ830E-E Block diagram and pin description

Doc ID 17459 Rev 1 5/28

1 Block diagram and pin description

Figure 1. Block diagram

OVERTEMP. 1

VCC1,2

GND1,2

INPUT1 OUTPUT1

OVERVOLTAGE

LOGIC

DRIVER 1

STATU S1

Vcc

CLAMP

UNDERVOLTAGE

CLAMP 1

OPEN-LOAD ON 1

CURRENT LIMITER 1

OPEN-LOAD OFF 1

OUTPUT2

DRIVER 2

CLAMP 2

OPEN-LOAD ON 2

OPEN-LOAD OFF 2

OVERTEMP. 2

INPUT2

STATUS2

CURRENT LIMITER 2

OVERTEMP. 3

VCC3,4

GND3,4

INPUT3 OUTPUT3

OVERVOLTAGE

LOGIC

DRIVER 3

STATUS3

Vcc

CLAMP

UNDERVOLTAGE

CLAMP 3

OPEN-LOAD ON 3

CURRENT LIMITER 3

OPEN-LOAD OFF 3

OUTPUT4

DRIVER 4

CLAMP 4

OPEN-LOAD ON 4

OPEN-LOAD OFF 4

OVERTEMP. 4

INPUT4

STATUS4

CURRENT LIMITER 4

3,4

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VNQ830E-E Block diagram and pin description

Doc ID 17459 Rev 1 6/28

Figure 2. Configuration diagram (top view)

Table 2. Suggested connections for unused and not connected pins

Connection / pin Status N.C. Output Input

Floating X X X X

To ground X Through 10 KΩ

resistor

VCC1,2

GND 1,2

INPUT1

STATUS1

STATUS2

VCC1,2

VCC3,4

GND 3,4

INPUT3

STATUS3

VCC3,4 VCC3,4

OUTPUT4

OUTPUT3

OUTPUT2

OUTPUT1

VCC1,2

OUTPUT3

OUTPUT1

INPUT2

STATUS4

INPUT4

14 15

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VNQ830E-E Electrical specifications

Doc ID 17459 Rev 1 7/28

2 Electrical specifications

2.1 Absolute maximum ratings

Stressing the device above the rating listed in Ta bl e 3 may cause permanent damage to the

device. These are stress ratings only and operation of the device at these or any other

conditions above those indicated in the operating sections of this specification is not implied.

Exposure to Absolute Maximum Rating conditions for extended periods may affect device

reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality

document.

Table 3. Absolute maximum rating

Symbol Parameter Value Unit

VCC DC supply voltage 41 V

- VCC Reverse DC supply voltage -0.3 V

- IGND DC reverse ground pin current -200 mA

IOUT DC output current Internally limited A

- IOUT Reverse DC output current -6 A

IIN DC input current +/-10 mA

ISTAT DC status current +/-10 mA

VESD

Electrostatic discharge (Human Body Model: R=1.5 KΩ;

C = 100 pF)

- INPUT

- STATUS

- OUTPUT

- VCC

4000

5000

EMAX

Maximum switching energy

L=0.5mH; R

L=0Ω; Vbat = 13.5 V; Tjstart =150°C;

IL= 13.5 A)

64 mJ

Ptot Power dissipation (per island) at Tlead =25°C 6.25 W

TjJunction operating temperature Internally limited °C

TcCase operating temperature - 40 to 150 °C

Tstg Storage temperature - 55 to 150 °C

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VNQ830E-E Electrical specifications

Doc ID 17459 Rev 1 8/28

2.2 Thermal data

2.3 Electrical characteristics

Values specified in this section are for 8 V < VCC < 36 V; -40 °C < Tj < 150 °C, unless

otherwise stated.

(Per each channel)

Figure 3. Current and voltage conventions

1. VFn = VCCn - VOUTn during reverse battery condition.

Table 4. Thermal data (per island)

Symbol Parameter Value Unit

Rthj-lead Thermal resistance junction-lead per chip 20 °C/W

Rthj-amb

Thermal resistance junction-ambient

(one chip ON) 60(1)

1. When mounted on a standard single-sided FR-4 board with 0.5 cm2 of Cu (at least 35 µm thick) connected

to all VCC pins. Horizontal mounting and no artificial air flow.

45(2)

2. When mounted on a standard single-sided FR-4 board with 6 cm2 of Cu (at least 35 µm thick) connected to

all VCC pins. Horizontal mounting and no artificial air flow.

°C/W

Rthj-amb

Thermal resistance junction-ambient

(two chips ON) 46(1) 30(2) °C/W

Table 5. Power output

Symbol Parameter Test conditions Min. Typ. Max. Unit

VCC(1) Operating supply voltage 5.5 13 36 V

VUSD(1) Undervoltage shutdown 3 4 5.5 V

VOV(1) Overvoltage shutdown 36 V

(1)

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VNQ830E-E Electrical specifications

Doc ID 17459 Rev 1 9/28

RON On-state resistance IOUT =2A; T

j=25°C

IOUT =2A; V

CC > 8 V

130

mΩ

IS(1) Supply current

Off-state; VCC = 13 V;

VIN = VOUT = 0 V

Off-state; VCC = 13 V;

VIN = VOUT = 0 V;

Tj = 25°C

On-state; VCC = 13 V; VIN = 5 V;

IOUT = 0 A

µA

IL(off1) Off-state output current VIN = VOUT = 0 V 0 50 µA

IL(off2) Off-state output current VIN = 0 V; VOUT = 3.5 V -75 0 µA

IL(off3) Off-state output current VIN = VOUT = 0 V; VCC = 13 V;

Tj = 125 °C 5µA

IL(off4) Off-state output current VIN = VOUT = 0 V; VCC = 13 V;

Tj =25 °C 3µA

1. Per island.

Table 6. Switching (per each channel) (VCC =13V)

Symbol Parameter Test conditions Min. Typ. Max. Unit

td(on) Turn-on delay time RL = 6.5 Ω from VIN rising

edge to VOUT = 1.3 V -50 -µs

td(off) Turn-off delay time RL = 6.5 Ω from VIN falling

edge to VOUT = 11.7 V -50 -µs

dVOUT/dt(on) Turn-on voltage slope RL = 6.5 Ω from VOUT = 1.3 V

to VOUT = 10.4 V -See

Figure 21 -V/µs

dVOUT/dt(off) Turn-off voltage slope RL = 6.5 Ω from VOUT = 11.7 V

to VOUT = 1.3 V -See

Figure 22 -V/µs

Table 7. VCC - output diode

Symbol Parameter Test conditions Min. Typ. Max. Unit

VFForward on voltage - IOUT = 1.2 A; Tj = 150 °C - - 0.6 V

Table 5. Power output (continued)

Symbol Parameter Test conditions Min. Typ. Max. Unit

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VNQ830E-E Electrical specifications

Doc ID 17459 Rev 1 10/28

Table 8. Status pin (per each channel)

Symbol Parameter Test conditions Min. Typ. Max. Unit

VSTAT Status low output voltage ISTAT = 1.6 mA 0.5 V

ILSTAT Status leakage current Normal operation;

VSTAT = 5 V 10 µA

CSTAT

Status pin input

capacitance

Normal operation;

VSTAT = 5 V 100 pF

VSCL Status clamp voltage ISTAT = 1 mA

ISTAT = - 1 mA

66.8

- 0.7

Table 9. Protections (per each channel)(1)

1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related

diagnostic signals must be used together with a proper software strategy. If the device is subjected to

abnormal conditions, this software must limit the duration and number of activation cycles.

Symbol Parameter Test conditions Min. Typ. Max. Unit

TTSD Shutdown temperature 150 175 200 °C

TRReset temperature 135 °C

Thyst Thermal hysteresis 7 15 °C

tSDL

Status delay in overload

conditions Tj > TTSD 20 µs

Ilim Current limitation VCC = 13 V

5.5 V < VCC < 36 V

9.5 13.5 18

Vdemag

Turn-off output clamp

voltage IOUT =2A; L = 6mH V

CC-41 VCC-48 VCC-55 V

Table 10. Logic input (per each channel)

Symbol Parameter Test conditions Min. Typ. Max. Unit

VIL Low level input voltage 1.25 V

VIH High level input voltage 3.25 V

VI(hyst) Input hysteresis voltage 0.5 V

IIL Low level input current VIN = 1.5 V 1 µA

IIH High level input current VIN = 3.25 V 10 µA

VICL Input clamp voltage IIN = 1 mA

IIN = -1 mA

66.8

- 0.7

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VNQ830E-E Electrical specifications

Doc ID 17459 Rev 1 11/28

Figure 4. Status timings

Figure 5. Switching time waveforms

Table 11. Open-load detection (per each channel)

Symbol Parameter Test conditions Min. Typ. Max. Unit

IOL

Open-load on-state detection

threshold VIN = 5 V 50 115 200 mA

tDOL(on)

Open-load on-state detection

delay IOUT = 0 A 200 µs

VOL

Open-load off-state voltage

detection threshold VIN = 0 V 1.5 2.9 3.5 V

tDOL(off)

Open-load detection delay at

turn-off 1000 µs

INn

STATn

DOL(off)

OPEN -LOAD STATUS TIMING (with external pull-up)

INn

STATn

OVERTEMP STATUS TIMING

SDL

OUT

< I

OUT

> V

DOL(on)

> T

TSD

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VNQ830E-E Electrical specifications

Doc ID 17459 Rev 1 12/28

Table 12. Truth table

Conditions Input Output Status

Normal operation L

Current limitation

(Tj < TTSD) H

(Tj > TTSD) L

Overtemperature L

Undervoltage L

Overvoltage L

Output voltage > VOL

Output current < IOL

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VNQ830E-E Electrical specifications

Doc ID 17459 Rev 1 13/28

Table 13. Electrical transient requirements on VCC pin (part 1)

ISO T/R

7637/1

Test pulse

Test levels

I II III IV Delays and impedance

1 - 25 V - 50 V - 75 V - 100 V 2 ms, 10 Ω

2 + 25 V + 50 V + 75 V + 100 V 0.2 ms, 10 Ω

3a - 25 V - 50 V - 100 V - 150 V 0.1 µs, 50 Ω

3b + 25 V + 50 V + 75 V + 100 V 0.1 µs, 50 Ω

4 - 4V - 5V - 6V - 7V 100ms, 0.01Ω

5 + 26.5 V + 46.5 V + 66.5 V + 86.5 V 400 ms, 2 Ω

Table 14. Electrical transient requirements on VCC pin (part 2)

ISO T/R

7637/1

Test pulse

Test levels results

IIIIIIIV

1C C C C

2C C C C

3a C C C C

3b C C C C

4C C C C

5C E E E

Table 15. Electrical transient requirements on VCC pin (part 3)

Class Contents

CAll functions of the device are performed as designed after exposure to

disturbance.

EOne or more functions of the device is not performed as designed after exposure

and cannot be returned to proper operation without replacing the device.

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VNQ830E-E Electrical specifications

Doc ID 17459 Rev 1 14/28

Figure 6. Waveforms

OPEN-LOAD without external pull-up

STATUSn

INPUTn

NORMAL OPERATION

UNDERVOLTAGE

VCC

VUSD

VUSDhyst

INPUTn

OVERVOLTAGE

VCC

VCC > VOV

STATUS

INPUTn

STATUSn

INPUTn

STATUSn

INPUTn

OPEN-LOAD with external pull-up

undefined

OVERTEMPERATURE

INPUTn

STATUSn

TTSD

LOAD VOLTAGEn

VCC<VOV

LOAD VOLTAGEn

LOAD CURRENTn

VOUT > VOL

VOL

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VNQ830E-E Electrical specifications

Doc ID 17459 Rev 1 15/28

2.4 Electrical characteristics curves

Figure 7. Off-state output current Figure 8. High level input current

Figure 9. Input clamp voltage Figure 10. Status leakage current

Figure 11. Status low output voltage Figure 12. Status clamp voltage

-50 -25 0 25 50 75 100 125 150 175

Tc ( ° C )

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

IL(off1) (µA)

Off state

Vcc=13V

Vin=Vout=0V

-50 -25 0 25 50 75 100 125 150 175

Tc ( ° C )

0.5

1.5

2.5

3.5

4.5

5.5

lih (µA)

Vin=3.25V

-50 -25 0 25 50 75 100 125 150 175

Tc ( ° C )

Vicl (V)

Iin=1mA

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

0.15

0.155

0.16

0.165

0.17

0.175

0.18

0.185

0.19

0.195

0.2

Ilstat (µA)

Vstat=5V

-50 -25 0 25 50 75 100 125 150 175

Tc ( ° C )

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

Vstat (V)

Istat=1.6mA

-50 -25 0 25 50 75 100 125 150 175

Tc ( ° C )

Vscl (V)

Istat=1mA

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VNQ830E-E Electrical specifications

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Figure 13. On-state resistance vs Tcase Figure 14. On-state resistance vs VCC

Figure 15. Open-load on-state detection

threshold

Figure 16. Open-load off-state detection

threshold

Figure 17. Input high level Figure 18. Input low level

-50 -25 0 25 50 75 100 125 150 175

Tc ( ° C )

100

120

140

160

Ron (mOhm)

Iout=2A

Vcc=8V; 13V & 36V

5 10152025303540

Vcc (V)

105

120

Ron (mOhm)

Tc=-40°C

Tc=25°Tc=25 ° C

Tc=150 °C

Iout=2A

-50 -25 0 25 50 75 100 125 150 175

Tc ( ° C )

100

110

120

130

140

150

Iol (mA)

Vcc=13V

Vin=5V

-50 -25 0 25 50 75 100 125 150 175

Tc ( ° C )

0.5

1.5

2.5

3.5

4.5

Vol (V)

Vin=0V

-50 -25 0 25 50 75 100 125 150 175

Tc ( ° C )

2.2

2.4

2.6

2.8

3.2

3.4

3.6

Vih (V)

-50 -25 0 25 50 75 100 125 150 175

Tc ( ° C )

1.2

1.4

1.6

1.8

2.2

2.4

2.6

Vil (V)

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Figure 19. Input hysteresis voltage Figure 20. Overvoltage shutdown

Figure 21. Turn-on voltage slope Figure 22. Turn-off voltage slope

Figure 23. ILIM vs Tcase Figure 24. Undervoltage shutdown

-50 -25 0 25 50 75 100 125 150 175

Tc ( ° C )

0.25

0.5

0.75

1.25

1.5

1.75

Vhyst (V)

-50 -25 0 25 50 75 100 125 150 175

Tc ( ° C )

Vov (V)

-50 -25 0 25 50 75 100 125 150 175

Tc ( ° C)

100

200

300

400

500

600

700

800

dVout/dt(on) (Vms)

Vcc=13V

Rl=6.5Ohm

-50 -25 0 25 50 75 100 125 150 175

Tc ( ° C )

100

150

200

250

300

350

400

450

500

dVout/dt(off) (Vms)

Vcc=13V

Rl=6.5Ohm

-50 -25 0 25 50 75 100 125 150 175

Tc ( ° C )

Ilim (A)

Vcc=13V

-50 -25 0 25 50 75 100 125 150 175

Tc ( ° C )

Vusd (V)

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VNQ830E-E Application information

Doc ID 17459 Rev 1 18/28

3 Application information

Figure 25. Application schematic

Note: Channels 3 & 4 have the same internal circuit as channel 1 & 2.

3.1 GND protection network against reverse battery

This section provides two solutions for implementing a ground protection network against

reverse battery.

3.1.1 Solution 1: a resistor in the ground line (RGND only)

This can be used with any type of load.

The following show how to dimension the RGND resistor:

1. RGND ≤ 600m V / 2 (IS(on)max)

2. RGND ≥ ( - VCC) / (- IGND)

CC1,2

OUTPUT2

+5V

prot

OUTPUT1

STATUS1

INPUT1

+5V

STATUS2

INPUT2

+5V

GND

GND1,2 GND3,4

OUTPUT3

OUTPUT4

CC3,4

STATUS3

INPUT3

STATUS4

INPUT4

+5V

prot

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VNQ830E-E Application information

Doc ID 17459 Rev 1 19/28

where - IGND is the DC reverse ground pin current and can be found in the absolute

maximum rating section of the device’s datasheet.

Power dissipation in RGND (when VCC < 0 during reverse battery situations) is:

PD = (- VCC)2/ RGND

This resistor can be shared amongst several different HSDs. Please note that the value of

this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the

maximum on-state currents of the different devices.

Please note that, if the microprocessor ground is not shared by the device ground, then the

RGND produces a shift (IS(on)max * RGND) in the input thresholds and the status output

values. This shift varies depending on how many devices are ON in the case of several high

side drivers sharing the same RGND.

If the calculated power dissipation requires the use of a large resistor, or several devices

have to share the same resistor, then ST suggests using Section 3.1.2 described below.

3.1.2 Solution 2: a diode (DGND) in the ground line

A resistor (RGND = 1 kΩ) should be inserted in parallel to DGND if the device is driving an

inductive load. This small signal diode can be safely shared amongst several different HSD.

Also in this case, the presence of the ground network produces a shift (~600mV) in the input

threshold and the status output values if the microprocessor ground is not common with the

device ground. This shift does not vary if more than one HSD shares the same

diode/resistor network.

3.2 Load dump protection

Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the

VCC maximum DC rating. The same applies if the device is subject to transients on the VCC

line that are greater than those shown in Ta bl e 1 3 .

3.3 MCU I/O protection

If a ground protection network is used and negative transients are present on the VCC line,

the control pins are pulled negative. ST suggests to insert a resistor (Rprot) in line to prevent

the microcontroller I/O pins from latching up.

The value of these resistors is a compromise between the leakage current of microcontroller

and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of

microcontroller I/Os:

- VCCpeak / Ilatchup ≤ Rprot ≤ (VOHμC-VIH-VGND) / IIHmax

Example

For the following conditions:

VCCpeak= - 100 V and Ilatchup ≥ 20 mA; VOHµC ≥ 4.5 V

5kΩ ≤ Rprot ≤ 65 kΩ.

Recommended values are:

Rprot = 10 kΩ

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VNQ830E-E Application information

Doc ID 17459 Rev 1 20/28

3.4 Open-load detection in off-state

Off-state open-load detection requires an external pull-up resistor (RPU) connected between

OUTPUT pin and a positive supply voltage (VPU) like the +5 V line used to supply the

microprocessor.

The external resistor has to be selected according to the following requirements:

1. No false open-load indication when load is connected: in this case we have to avoid

VOUT to be higher than VOlmin; this results in the following condition

VOUT = (VPU / (RL + RPU))RL < VOlmin.

2. No misdetection when load is disconnected: in this case the VOUT has to be higher than

VOLmax; this results in the following condition RPU < (VPU - VOLmax) / IL(off2)

Because Is(OFF) may significantly increase if Vout is pulled high (up to several mA), the pull-

up resistor RPU should be connected to a supply that is switched OFF when the module is in

standby.

The values of VOLmin, VOLmax and IL(off2) are available in the Chapter 2: Electrical

specifications.

Figure 26. Open-load detection in off-state

VOL

V batt. VPU

RPU

DRIVER

LOGIC

IN PU T

STATUS

VCC

OUT

GROUND

IL(off2)

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3.5 Maximum demagnetization energy

Figure 27. Maximum turn-off current versus load inductance

Note: Values are generated with RL = 0 Ω.

In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse

must not exceed the temperature specified above for curves B and C.

VIN, IL

Demagnetization Demagnetization Demagnetization

A = single pulse at TJstart = 150 °C

B= repetitive pulse at TJstart = 100 °C

C= repetitive pulse at TJstart = 125 °C

Conditions:

VCC =13.5V

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VNQ830E-E Package and PCB thermal data

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4 Package and PCB thermal data

4.1 SO-28 thermal data

Figure 28. SO-28 PC board

Note: Layout condition of Rth and Zth measurements (PCB FR4 area = 58 mm x 58 mm, PCB

thickness = 2 mm, Cu thickness = 35 µm, Copper areas: 0.5 cm2, 3 cm2, 6 cm2).

RthA = thermal resistance junction to ambient with one chip ON

RthB = thermal resistance junction to ambient with both chips ON and Pdchip1 = Pdchip2

RthC = mutual thermal resistance

Table 16. Thermal calculation according to the PCB heatsink area

Chip 1 Chip 2 Tjchip1 Tjchip2 Note

On Off RthA x Pdchip1 + Tamb RthC x Pdchip1 + Tamb

Off On RthC x Pdchip2 + Tamb RthA x Pdchip2 + Tamb

On On RthB x (Pdchip1 + Pdchip2) + Tamb RthB x (Pdchip1 + Pdchip2) + Tamb Pdchip1 = Pdchip2

On On (RthA x Pdchip1) + RthC x Pdchip2 + Tamb (RthA x Pdchip2) + RthC x Pdchip1 + Tamb Pdchip1 ≠ Pdchip2

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VNQ830E-E Package and PCB thermal data

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Figure 29. Rthj-amb vs PCB copper area in open box free air condition

Figure 30. SP-28 thermal impedance junction ambient single pulse

01234567

PCB Cu heatsink area (cm ^2)/island

RTHj_am b

(°C/W)

RthA

RthB

RthC

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VNQ830E-E Package and PCB thermal data

Doc ID 17459 Rev 1 24/28

Equation 1: pulse calculation formula

Figure 31. Thermal fitting model of a quad channel HSD in SO-28

Table 17. Thermal parameters

Area / island (cm2) Footprint 6

R1 = R7 = R13 = R15 (°C/W) 0.15

R2 = R8 = R14 = R16 (°C/W) 0.7

R3 = R9 (°C/W) 1.8

R4 = R10 (°C/W) 10

R5 = R11 (°C/W) 15

R6 = R12 (°C/W) 30 13

C1 = C7 = C13 = C15 (W.s/°C) 0.0005

C2 = C8 = C14 = C16 (W.s/°C) 0.003

C3 = C9 (W.s/°C) 0.015

C4 = C10 (W.s/°C) 0.15

C5 = C11 (W.s/°C) 1.5

C6 = C12 (W.s/°C) 5 8

R17 = R18 (°C/W) 150

ZTHδRTH δZTHtp 1δ–()+⋅=

where

δtpT⁄=

Pd1

C3 C4

R3R1 R6R5R2

C5 C6C2

Pd2

R14

C13 C14

R13

Tj_1

Tj_2

T_amb

Pd3

R10

C9 C10

R9R7 R12R11

C11 C12

Pd4

R16

C15 C16

R15

Tj_3

Tj_4

R17 R18

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VNQ830E-E Package and packing information

Doc ID 17459 Rev 1 25/28

5 Package and packing information

5.1 ECOPACK® packages

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®

specifications, grade definitions and product status are available at: www.st.com.

ECOPACK® is an ST trademark.

Figure 32. SO-28 package dimensions

Table 18. SO-28 mechanical data

Symbol

Millimeters

Min. Typ. Max.

A2.65

a1 0.10 0.30

b 0.35 0.49

b1 0.23 0.32

C0.50

c1 45° (typ.)

D 17.7 18.1

E 10.00 10.65

e1.27

e3 16.51

F 7.40 7.60

L 0.40 1.27

S 8° (max.)

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5.2 SO-28 packing information

Figure 33. SO-28 tube shipment (no suffix)

Figure 34. SO-28 tape and reel shipment (suffix “13TR”)

All dimensions are in mm.

Base Q.ty 28

Bulk Q.ty 700

Tube length (± 0.5) 532

A3.5

B13.8

C (± 0.1) 0.6

Base Q.ty 1000

Bulk Q.ty 1000

A (max) 330

B (min) 1.5

C (± 0.2) 13

F20.2

G (+ 2 / -0) 16.4

N (min) 60

T (max) 22.4

Tape dimensions

According to Electronic Industries Association

(EIA) Standard 481 rev. A, Feb. 1986

All dimensions are in mm.

Tape width W 16

Tape hole spacing P0 (± 0.1) 4

Component spacing P 12

Hole diameter D (± 0.1/-0) 1.5

Hole diameter D1 (min) 1.5

Hole position F (± 0.05) 7.5

Compartment depth K (max) 6.5

Hole spacing P1 (± 0.1) 2

Top

cover

tape

End

Start

No componentsNo components Components

500mm min

Empty components pockets

saled with cover tape.

User direction of feed

Reel dimensions

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VNQ830E-E Revision history

Doc ID 17459 Rev 1 27/28

6 Revision history

Table 19. Document revision history

Date Revision Changes

03-May-2010 1 Initial release.

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VNQ830E-E

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