SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DESCRIPTION
The 7534 Group is the 8-bit microcomputer based on the 740 family
core technology.
The 7534 Group has a USB, 8-bit timers, and an A-D converter, and
is useful for an input device for personal computer peripherals.
FEATURES
•Basic machine-language instructions....................................... 69
•The minimum instruction execution time .......................... 0.34 µs
(at 6 MHz oscillation frequency for the shortest instruction)
•Memory sizeROM ...............................................8K to 16K bytes
RAM ..............................................256 to 384 bytes
•Programmable I/O ports ...................................... 28 (36-pin type)
............................................................................ 24 (32-pin type)
............................................................................ 33 (42-pin type)
•Interrupts .................................................... 14 sources, 8 vectors
•Timers ............................................................................ 8-bit ✕ 3
MITSUBISHI MICROCOMPUTERS
7534 Group
•Serial I/O1 ................................ used only for Low Speed in USB
(based on USBSpec. Rev.1.1)
(USB/UART)
•Serial I/O2 ...................................................................... 8-bit ✕ 1
(Clock-synchronized)
•A-D converter ................................................ 10-bit ✕ 8 channels
•Clock generating circuit ............................................. Built-in type
(connect to external ceramic resonator or quartz-crystal oscillator )
•Watchdog timer ............................................................ 16-bit ✕ 1
•Power source voltage
At 6 MHz XIN oscillation frequency at ceramic resonator
................................4.1 to 5.5 V(4.4 to 5.25 V at USB operation)
•Power dissipation ............................................ 30 mW (standard)
•Operating temperature range................................... –20 to 85 °C
(0 to 70 °C at USB operation)
•Built-in USB 3.3 V Regulator + transceiver based on USB Spec.
Rev.1.1
APPLICATION
Input device for personal computer peripherals
PIN CONFIGURATION (TOP VIEW)
Fig. 1 Pin configuration of M37534M4-XXXFP, M37534E8FP
Package type: 36P2R-A
10
1
2
3
4
6
7
8
9
11
12
14
15
16
5
13
17
18
36
35
34
33
31
30
26
25
24
23
22
21
20
19
32
27
29
28
P0
0
CNV
SS
X
OUT
X
IN
V
SS
P0
1
P0
2
P0
3
P0
4
P3
0
(LED
0
)
Vcc
V
REF
P0
5
P1
0
/R
X
D/D-
P2
6
/AN
6
P2
7
/AN
7
P1
1
/T
X
D/D+
P1
2
/S
CLK
P1
3
/S
DATA
P2
3
/AN
3
P2
2
/AN
2
P2
1
/AN
1
P2
0
/AN
0
P3
1
(LED
1
)
P3
7
/INT
0
P2
4
/AN
4
P2
5
/AN
5
P0
6
P0
7
USBV
REFOUT
RESET
M37534M4-XXXFP
M37534E8FP
P1
4
/CNTR
0
P3
5
(LED
5
)
P3
4
(LED
4
)
P3
3
(LED
3
)
P3
2
(LED
2
)
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7534 Group
MITSUBISHI MICROCOMPUTERS
2
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
PIN CONFIGURATION (TOP VIEW)
Fig. 2 Pin configuration of M37534M4-XXXGP
Outline 32P6U-A
P07
P10/RXD/D-
P11/TXD/D+
P12/SCLK
P13/SDATA
P14/CNTR0
P20/
AN
0
P2
1/AN
1
32
31
30
29
28
27
26
25 P34(LED4)
P33(LED3)
P32(LED2)
P31(LED1)
P30(LED0)
VSS
XOUT
XIN
9
10
11
12
13
14
15
16
2
8
7
6
5
3
1
4
VCC
CNVSS
RESET
P22/AN2P05
20
17
18
19
21
24
P02
P04
P03
P06
23
22
P01
P00
USBVREFOUT
M37534M4-XXXGP
P23/AN3
P24/AN4
P25/AN5
VREF
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7534 Group
MITSUBISHI MICROCOMPUTERS
3
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
PIN CONFIGURATION (TOP VIEW)
Fig. 3 Pin configuration of M37534RSS, M37534M4-XXXSP, M37534E8SP
Outline 42S1M, 42P4B
10
1
2
3
4
6
7
8
9
11
12
14
15
16
5
13
17
18
36
35
34
33
31
30
26
25
24
23
22
32
27
29
28
19
20
21
42
41
40
39
37
38
P0
0
CNV
SS
X
OUT
X
IN
V
SS
P0
1
P0
2
P0
3
P0
4
P3
0
(LED
0
)
Vcc
V
REF
P0
5
P1
2
/S
CLK
P2
5
/AN
5
P2
6
/AN
6
P1
3
/S
DATA
P1
4
/CNTR
0
P2
2
/AN
2
NC
P2
1
/AN
1
P2
0
/AN
0
P3
1
(LED
1
)
P2
3
/AN
3
P2
4
/AN
4
P0
6
P0
7
P3
7
/INT
0
RESET
M37534RSS
M37534M4-XXXSP
M37534E8SP
P3
5
(LED
5
)
P3
4
(LED
4
)
P3
3
(LED
3
)
P3
2
(LED
2
)
USBV
REFOUT
P1
0
/R
X
D/D-
P1
1
/T
X
D/D+
P2
7
/AN
7
P1
6
P1
5
P4
0
P4
1
P3
6
(LED
6
)/INT
1
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7534 Group
MITSUBISHI MICROCOMPUTERS
4
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
FUNCTIONAL BLOCK
Fig. 4 Functional block diagram (36P2R package type)
FUNCTIONAL BLOCK DIAGRAM (Package: 36P2R)
SI/O1(8)
USB(LS)
R A M R O M C P U
A
X
Y
S
PCHPCL
PS
VSS
18
RESET
13
VCC
15 14
CNVSS
CNTR0
P0(8)
34 32 30 28
33 31 29 27
P1(5)
3135236
756 4
P2(8)
P3(7)
12
16 17
11 9
10 8
VREF
0
26
INT0
2023 21 1922
2425
SI/O2(8)
USBVREFOUT
XIN XOUT
Clock input Clock output
Clock generating circuit
Watchdog timer Reset
A-D
converter
(10)
I/O port P3 I/O port P2 I/O port P1 I/O port P0
Key-on wake up
Timer 1 (8)
Timer 2 (8)
Timer X (8)
Prescaler 12 (8)
Prescaler X (8)
Reset input
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7534 Group
MITSUBISHI MICROCOMPUTERS
5
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 5 Functional block diagram (32P6U-A package type)
FUNCTIONAL BLOCK DIAGRAM (Package: 32P6U-A)
SI/O1(8)
USB(LS)
R A M R O M C P U
A
X
Y
S
PC
H
PC
L
PS
V
SS
11
RESET
6
V
CC
87
CNV
SS
CNTR0
P0(8)
25 23 21 19
24 22 20 18
P1(5)
30 28 2629 27
32 31
P2(6)
P3(5)
5
910
42
31
V
REF
0
17
1316 14 1215
SI/O2(8)
USBV
REFOUT
X
IN
X
OUT
Clock input Clock output
Clock generating circuit
Watchdog timer Reset
A-D
converter
(10)
I/O port P3 I/O port P2 I/O port P1 I/O port P0
Key-on wake up
Timer 1 (8)
Timer 2 (8)
Timer X (8)
Prescaler 12 (8)
Prescaler X (8)
Reset input
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7534 Group
MITSUBISHI MICROCOMPUTERS
6
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 6 Functional block diagram (42P4B package type)
Timer 1 (8)
Timer 2 (8)
Timer X (8)
Prescaler 12 (8)
Prescaler X (8)
XIN OUT
X
R A M R O M
C P U
A
X
Y
S
PCHPCL
PS
VSS
21
RESET
16
VCC
18 17
CNVSS
CNTR0
P1(7)
P2(8)
P3(8)
19 20
VREF
0
INT0
USBVREFOUT
INT1
P4(2)
SI/O1(8)
USB(LS) SI/O2(8)
Clock generating circuit
Watchdog timer Reset
A-D
converter
(10)
I/O port P3 I/O port P2 I/O port P1 I/O port P0
I/O port P4
Key-on wakeup
Clock input Clock output Reset input
13 14 15 2427 25 23262829 22 857412 1011 9 30 3141242 3940
P0(8)
38 36 34 3237 35 33 31
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7534 Group
MITSUBISHI MICROCOMPUTERS
7
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
PIN DESCRIPTION
Table 1 Pin description
Pin
Vcc, Vss
VREF
USBVREFOUT
CNVss
RESET
P00–P07
P10/RxD/D-
P11/TxD/D+
P12/SCLK
P13/SDATA
P14/CNTR0
P15, P16
P20/AN0–
P27/AN7
P30–P35
P36/INT1
P37/INT0
P40, P41
XIN
XOUT
Function
•Apply voltage of 4.1 to 5.5 V to Vcc, and 0 V to Vss.
•Reference voltage input pin for A-D converter
•Output pin for pulling up a D- line with 1.5 kΩ external resistor
•Chip operating mode control pin, which is always connected to Vss.
•Reset input pin for active “L”
•Input and output pins for main clock generating circuit
•Connect a ceramic resonator or quartz crystal oscillator between the XIN and XOUT pins.
•If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.
Function expect a port function
Name
Power source
Analog reference
voltage
USB reference
voltage output
CNVss
Reset input
•8-bit I/O port.
•I/O direction register allows each pin to be individually pro-
grammed as either input or output.
•CMOS compatible input level
•CMOS 3-state output structure
•Whether a built-in pull-up resistor is to be used or not can be
determined by program.
•7-bit I/O port
•I/O direction register allows each pin to be individually pro-
grammed as either input or output.
•CMOS compatible input level
•CMOS 3-state output structure
•CMOS/TTL level can be switched for P10, P12, P13.
•When using the USB function, input level of ports P10 and
P11 becomes USB input level, and output level of them
becomes USB output level.
•8-bit I/O port having almost the same function as P0
•CMOS compatible input level
•CMOS 3-state output structure
Clock input
Clock output
I/O port P0
I/O port P1
I/O port P2
I/O port P3
I/O port P4
•Whether a built-in pull-up resistor is to be used or not can be
determined by program.
•2-bit I/O port
•I/O direction register allows each pin to be individually programmed as either input or output.
•Key-input (key-on wake up
interrupt input) pins
•Serial I/O1 function pin
•Serial I/O2 function pin
•Timer X function pin
•Input pins for A-D converter
•Interrupt input pins
•8-bit I/O port
•I/O direction register allows each pin to be individually programmed as either input or output.
•CMOS compatible input level (CMOS/TTL level can be switched for P36, P37).
•CMOS 3-state output structure
•P30 to P36 can output a large current for driving LED.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7534 Group
MITSUBISHI MICROCOMPUTERS
8
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
GROUP EXPANSION
Mitsubishi plans to expand the 7534 group as follow:
Memory type
Support for Mask ROM version, One Time PROM version, and Emu-
lator MCU .
Memory size
ROM/PROM size ..................................................8 K to 16 K bytes
RAM size................................................................256 to 384 bytes
Fig. 7 Memory expansion plan
Currently supported products are listed below.
Table 2 List of supported products
Product
M37534M4-XXXFP
M37534M4-XXXGP
M37534M4-XXXSP
M37534E8FP
M37534E8SP
M37534RSS
Remarks
Mask ROM version
Mask ROM version
Mask ROM version
One Time PROM version (blank)
One Time PROM version (blank)
Emulator MCU
Package
36P2R-A
32P6U-A
42P4B
36P2R-A
42P4B
42S1M
(P) ROM size (bytes)
ROM size for User ()
8192 (8062)
8192 (8062)
8192 (8062)
16384 (16254)
16384 (16254)
RAM size
(bytes)
256
256
256
384
384
384
ROM size
(Byte)
RAM size
(Byte)
128
16K
256 384
8K
0
M37534E8
M37534M4
Package
36P2R-A ..................................... 0.8 mm-pitch plastic molded SOP
32P6U-A ................................... 0.8 mm-pitch plastic molded LQFP
42P4B ................................................... 42 pin plastic molded SDIP
42SIM...................................... 42 pin shrink ceramic PIGGY BACK
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7534 Group
MITSUBISHI MICROCOMPUTERS
9
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
FUNCTIONAL DESCRIPTION
Central Processing Unit (CPU)
The 7534 Group uses the standard 740 family instruction set. Refer
to the table of 740 family addressing modes and machine-language
instructions or the 740 Family Software Manual for details on each
instruction set.
Machine-resident 740 family instructions are as follows:
1. The FST and SLW instructions cannot be used.
2. The MUL and DIV instructions cannot be used.
3. The WIT instruction can be used.
4. The STP instruction can be used.
[CPU Mode Register] CPUM
The CPU mode register contains the stack page selection bit.
This register is allocated at address 003B16.
Fig. 9 Switching method of CPU mode register
Switching method of CPU mode register
Switch the CPU mode register (CPUM) at the head of program after
releasing Reset in the following method.
Fig. 8 Structure of CPU mode register
CPU mode register
(CPUM: address 003B
16
)
Stack page selection bit
0 : 0 page
1 : 1 page
Main clock division ratio selection bits
b7 b6
0 0 : f(φ) = f(X
IN
)/2 (High-speed mode)
0 1 : f(φ) = f(X
IN
)/8 (Middle-speed mode)
1 0 : applied from ring oscillator
1 1 : f(φ) = f(X
IN
) (Double-speed mode)
Not used (returns “0” when read)
(Do not write “1” to these bits )
Processor mode bits
b1 b0
0 0 Single-chip mode
0 1
1 0
1 1 Not available
b7 b0
Switch the clock division ratio
selection bits (bits 6 and 7 of CPUM)
After releasing reset
Main routine
Start with a built-in ring oscillator (Note)
Switch to other mode except a ring oscillator
(Select one of 1/1, 1/2, and 1/8)
Note. After releasing reset the operation starts by starting a ring oscillator automatically.
Do not use a ring oscillator at ordinary operation.
Wait until establish ceramic oscillator
clock.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7534 Group
MITSUBISHI MICROCOMPUTERS
10
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Memory
Special function register (SFR) area
The SFR area in the zero page contains control registers such as I/O
ports and timers.
RAM
RAM is used for data storage and for a stack area of subroutine calls
and interrupts.
ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing and the rest is a user area for storing programs.
Interrupt vector area
The interrupt vector area contains reset and interrupt vectors.
Zero page
The 256 bytes from addresses 000016 to 00FF16 are called the zero
page area. The internal RAM and the special function registers (SFR)
are allocated to this area.
The zero page addressing mode can be used to specify memory and
register addresses in the zero page area. Access to this area with
only 2 bytes is possible in the zero page addressing mode.
Special page
The 256 bytes from addresses FF0016 to FFFF16 are called the spe-
cial page area. The special page addressing mode can be used to
specify memory addresses in the special page area. Access to this
area with only 2 bytes is possible in the special page addressing
mode.
Fig. 10 Memory map diagram
0100
16
0000
16
0040
16
0440
16
FF00
16
FFEC
16
FFFE
16
FFFF
16
256
384
XXXX
16
013F
16
01BF
16
8192
16384 E000
16
C000
16
E080
16
C080
16
YYYY
16
ZZZZ
16
RAM
ROM
Reserved area
SFR area
Not used
Interrupt vector area
ROM area
Reserved ROM area
(128 bytes)
Zero page
Special page
RAM area
RAM capacity
(bytes) address
XXXX
16
ROM capacity
(bytes) address
YYYY
16
Reserved ROM area
address
ZZZZ
16
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7534 Group
MITSUBISHI MICROCOMPUTERS
11
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 11 Memory map of special function register (SFR)
0000
16
0001
16
0002
16
0003
16
0004
16
0005
16
0006
16
0007
16
0008
16
0009
16
000A
16
000B
16
000C
16
000D
16
000E
16
000F
16
0010
16
0011
16
0012
16
0013
16
0014
16
0015
16
0016
16
0017
16
0018
16
0019
16
001A
16
001B
16
001C
16
001D
16
001E
16
001F
16
Port P0 (P0)
Port P0 direction register (P0D)
Port P1 (P1)
Port P1 direction register (P1D)
Port P2 (P2)
Port P2 direction register (P2D)
Port P3 (P3)
Port P3 direction register (P3D)
Pull-up control register (PULL)
Transmit/Receive buffer register (TB/RB)
USB status register (USBSTS)/UART status register (UARTSTS)
Serial I/O1 control register (SIO1CON)
UART control register (UARTCON)
Baud rate generator (BRG)
Port P1P3 control register (P1P3C)
USB data toggle synchronization register ( TRSYNC)
USB interrupt source discrimination register 1 (USBIR1)
USB interrupt source discrimination register 2 (USBIR2)
0020
16
0021
16
0022
16
0023
16
0024
16
0025
16
0026
16
0027
16
0028
16
0029
16
002A
16
002B
16
002C
16
002D
16
002E
16
002F
16
0030
16
0031
16
0032
16
0033
16
0034
16
0035
16
0036
16
0037
16
0038
16
0039
16
003A
16
003B
16
003C
16
003D
16
003E
16
003F
16
Timer count source set register (TCSS)
A-D conversion register (low-order) (ADL)
Prescaler 12 (PRE12)
Timer 1 (T1)
Timer 2 (T2)
Timer X mode register
(TM)
Prescaler X
(PREX)
Timer X
(TX)
Serial I/O2 control register (SIO2CON)
Serial I/O2 register (SIO2)
A-D control register (ADCON)
A-D conversion register (high-order) (ADH)
MISRG
Watchdog timer control register (WDTCON)
Interrupt edge selection register
(INTEDGE)
CPU mode register (CPUM)
Interrupt request register 1 (IREQ1)
Interrupt control register 1 (ICON1)
USB interrupt control register (USBICON)
USB transmit data byte number set register 0 (EP0BYTE)
USB transmit data byte number set register 1 (EP1BYTE)
USBPID control register 0 (EP0PID)
USBPID control register 1 (EP1PID)
USB address register (USBA)
USB sequence bit initialization register (INISQ1)
USB control register (USBCON)
Port P4 (P4)
Port P4 direction register (P4D)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7534 Group
MITSUBISHI MICROCOMPUTERS
12
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
I/O Ports
[Direction registers] PiD
The I/O ports have direction registers which determine the input/out-
put direction of each pin. Each bit in a direction register corresponds
to one pin, and each pin can be set to be input or output.
When “1” is set to the bit corresponding to a pin, this pin becomes an
output port. When “0” is set to the bit, the pin becomes an input port.
When data is read from a pin set to output, not the value of the pin
itself but the value of port latch is read. Pins set to input are floating,
and permit reading pin values.
If a pin set to input is written to, only the port latch is written to and the
pin remains floating.
[Pull-up control] PULL
By setting the pull-up control register (address 001616), ports P0 and
P3 can exert pull-up control by program. However, pins set to output
are disconnected from this control and cannot exert pull-up control.
[Port P1P3 control] P1P3C
By setting the port P1P3 control register (address 001716), a CMOS
input level or a TTL input level can be selected for ports P10, P12,
P13, P36 and P37 by program.
Then, as for the 36-pin version, set “1” to each bit 6 of the port P3
direction register and port P3 register.
As for the 32-pin version, set “1” to respective bits 5, 6, 7 of the port
P3 direction register and port P3 register.
Fig. 13 Structure of port P1P3 control register
Fig. 12 Structure of pull-up control register
Pull-up control register
(PULL: address 0016
16
)
P0
0
pull-up control bit
P0
1
pull-up control bit
P0
2
, P0
3
pull-up control bit
P0
4
– P0
7
pull-up control bit
P3
0
– P3
3
pull-up control bit
P3
4
pull-up control bit
P3
5
, P3
6
pull-up control bit
P3
7
pull-up control bit
Note : Pins set to output ports are disconnected from pull-up control.
b7 b0
0: Pull-up off
1: Pull-up on
Initial value: FF
16
Port P1P3 control register
(P1P3C: address 0017
16
)
b7 b0
P3
7
/INT
0
input level selection bit
0 : CMOS level
1 : TTL level
P3
6
/INT
1
input level selection bit
0 : CMOS level
1 : TTL leve
P1
0
,P1
2
,P1
3
input level selection bit
0 : CMOS level
1 : TTL level
Not used
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7534 Group
MITSUBISHI MICROCOMPUTERS
13
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Table 3 I/O port function table
Name
I/O port P0
I/O port P1
I/O port P2
I/O port P3
I/O port P4
Pin
P00–P07
P10/RxD/D-
P11/TxD/D+
P12/SCLK
P13/SDATA
P14/CNTR0
P15, P16
P20/AN0–
P27/AN7
P30–P35
P36/INT1
P37/INT0
P40, P41
Related SFRs
Pull-up control register
Serial I/O1 control
register
Serial I/O2 control
register
Timer X mode register
A-D control register
Interrupt edge selection
register
Diagram No.
Input/output
I/O individual
bits
I/O format
•CMOS compatible input level
•CMOS 3-state output
•USB input/output level when
selecting USB function
•CMOS compatible input level
•CMOS 3-state output
(Note)
Non-port function
Key input interrupt
Serial I/O1 function
input/output
Serial I/O2 function
input/output
Timer X function input/output
A-D conversion input
External interrupt input
(1)
(2)
(3)
(4)
(5)
(6)
(10)
(7)
(8)
(9)
(10)
Note: Port P10, P12, P13, P36, P37 is CMOS/TTL level.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7534 Group
MITSUBISHI MICROCOMPUTERS
14
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 14 Block diagram of ports (1)
Data bus
+
-
(1) Port P0
Data bus
Direction
register
Port latch
Pull-up control
To key input interrupt
generating circuit
Data bus
Direction
register
Port latch
Serial I/O1 mode selection bit (b7)
Serial I/O1 mode selection bit (b6)
Receive enable bit
Serial I/O1 mode selection bit (b7)
Serial I/O1 mode selection bit (b6)
P1
0
,P1
2
,P1
3
input
level selection bit
D- input
D- output
Serial I/O1 input
USB output enable
(internal signal)
USB differential input
D+ input
D+ output
Serial I/O1 output
USB output enable
(internal signal)
Direction
register
Port latch
(3) Port P1
1
P-channel output disable bit
(2) Port P1
0
(4) Port P1
2
(5) Port P1
3
Data bus
Direction
register
P1
0
,P1
2
,P1
3
input
level selection bit
S
CLK
pin selection bit
Port latch
Serial I/O2 clock output
Serial I/O2 clock input Serial I/O2 clock output
Serial I/O2 clock input
P1
0
,P1
2
,P1
3
input
level selection bit
Data bus
Direction
register
Signals during the
S
DATA
output action
Port latch
S
DATA
pin selection bit
S
DATA
pin
selection bit
: P1
0
, P1
2
, P1
3
, P3
6
, P3
7
input levels are switched to the CMOS/TTL level by the port P1P3 control register.
Serial I/O1 mode selection bit (b7)
Serial I/O1 mode selection bit (b6)
Serial I/O1 mode selection bit (b7)
Serial I/O1 mode selection bit (b6)
Transmit enable bit
When the TTL level is selected, there is no hysteresis characteristics.
*
**
*
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7534 Group
MITSUBISHI MICROCOMPUTERS
15
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 15 Block diagram of ports (2)
(6) Port P1
4
(8) Ports P3
0
– P3
5
Data bus
Pull-up
control
Data bus
Timer output
Pulse output mode
CNTR
0
interrupt input
(7) Ports P2
0
– P2
7
A-D conversion input
Data bus
Analog input pin selection bit
Data bus
Pull-up
control
(9) Port P3
6
, P3
7
INT
interrupt input
Direction
register
Port latch
P3
7
/INT
0
input
level selection bit
Direction
register
Port latch
Direction
register
Port latch
Direction
register
Port latch
: P1
0
, P1
2
, P1
3
, P3
6
, P3
7
input levels are switched to the CMOS/TTL level by the port P1P3 control register.
(10) Ports P1
5,
P1
6
, P4
0,
P4
1
Direction
register
Port latch
Data bus
When the TTL level is selected, there is no hysteresis characteristics.
*
*
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7534 Group
MITSUBISHI MICROCOMPUTERS
16
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Interrupt operation
Upon acceptance of an interrupt the following operations are auto-
matically performed:
1. The processing being executed is stopped.
2. The contents of the program counter and processor status regis-
ter are automatically pushed onto the stack.
3. The interrupt disable flag is set and the corresponding interrupt
request bit is cleared.
4. Concurrently with the push operation, the interrupt destination
address is read from the vector table into the program counter.
Notes on use
When the active edge of an external interrupt (INT0, INT1, CNTR0) is
set, the interrupt request bit may be set.
Therefore, please take following sequence:
1. Disable the external interrupt which is selected.
2. Change the active edge in interrupt edge selection register. (in
case of CNTR0: Timer X mode register)
3. Clear the set interrupt request bit to “0”.
4. Enable the external interrupt which is selected.
Remarks
Non-maskable
Valid in UART mode
Valid in USB mode
Valid in UART mode
Valid in USB mode
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt (valid at falling)
STP release timer underflow
External interrupt (active edge
selectable)
Non-maskable software interrupt
Note 1: Vector addressed contain internal jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
Interrupts
Interrupts occur by 14 different sources : 4 external sources, 9 inter-
nal sources and 1 software source.
Interrupt control
All interrupts except the BRK instruction interrupt have an interrupt
request bit and an interrupt enable bit, and they are controlled by the
interrupt disable flag. When the interrupt enable bit and the interrupt
request bit are set to “1” and the interrupt disable flag is set to “0”, an
interrupt is accepted.
The interrupt request bit can be cleared by program but not be set.
The interrupt enable bit can be set and cleared by program.
It becomes usable by switching CNTR0 and A-D interrupt sources
with bit 7 of the interrupt edge selection register, timer 2 and serial I/
O2 interrupt sources with bit 6, timer X and key-on wake-up interrupt
sources with bit 5, and serial I/O transmit and INT1 interrupt sources
with bit 4.
The reset and BRK instruction interrupt can never be disabled with
any flag or bit. All interrupts except these are disabled when the in-
terrupt disable flag is set.
When several interrupts occur at the same time, the interrupts are
received according to priority.
Table 6 Interrupt vector address and priority
Vector addresses (Note 1)
High-order
FFFD16
FFFB16
FFF916
FFF716
FFF516
FFF316
FFF116
FFEF16
FFED16
Priority
1
2
3
4
5
6
7
8
9
Low-order
FFFC16
FFFA16
FFF816
FFF616
FFF416
FFF216
FFF016
FFEE16
FFEC16
Interrupt request generating conditions
At reset input
At completion of UART data receive
At detection of IN token
At completion of UART transmit shift or
when transmit buffer is empty
At detection of SETUP/OUT token or
At detection of Reset/ Suspend/ Resume
At detection of either rising or falling edge
of INT1 input
At detection of either rising or falling edge
of INT0 input
At timer X underflow
At falling of conjunction of input logical
level for port P0 (at input)
At timer 1 underflow
At timer 2 underflow
At completion of transmit/receive shift
At detection of either rising or falling edge
of CNTR0 input
At completion of A-D conversion
At BRK instruction execution
Interrupt source
Reset (Note 2)
UART receive
USB IN token
UART transmit
USB SETUP/OUT token
Reset/Suspend/Resume
INT1
INT0
Timer X
Key-on wake-up
Timer 1
Timer 2
Serial I/O2
CNTR0
A-D conversion
BRK instruction
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7534 Group
MITSUBISHI MICROCOMPUTERS
17
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 16 Interrupt control
Fig. 17 Structure of Interrupt-related registers
Interrupt disable flag I
Interrupt request
Interrupt request bit
Interrupt enable bit
BRK instruction
Reset
b7 b0
b7 b0
Interrupt edge selection register
INT
0
interrupt edge selection bit
0 : Falling edge active
1 : Rising edge active
INT
1
interrupt edge selection bit
0 : Falling edge active
1 : Rising edge active
Not used (returns “0” when read)
Serial I/O1 or INT
1
interrupt selection bit
0 : Serial I/O1
1 : INT
1
Timer X or key-on wake up interrupt selection bit
0 : Timer X
1 : Key-on wake up
Timer 2 or serial I/O2 interrupt selection bit
0 : Timer 2
1 : Serial I/O2
CNTR
0
or AD converter interrupt selection bit
0 : CNTR
0
1 : AD converter
(INTEDGE : address 003A
16
)
Interrupt request register 1
UART receive/USB IN token interrupt request bit
UART transmit/USB SETUP/OUT token/ Reset/Suspend/Resume/INT interrupt request bit
INT
0
interrupt request bit
Timer X or key-on wake up interrupt request bit
Timer 1 interrupt request bit
Timer 2 or serial I/O2 interrupt request bit
CNTR
0
or AD converter interrupt request bit
Not used (returns “0” when read) 0 : No interrupt request issued
1 : Interrupt request issued
(IREQ1 : address 003C
16
)
b7 b0 Interrupt control register 1
UART receive/USB IN token interrupt enable bit
UART transmit/USB SETUP/OUT token/ Reset/Suspend/Resume/INT interrupt enable bit
INT
0
interrupt enable bit
Timer X or key-on wake up interrupt enable bit
Timer 1 interrupt enable bit
Timer 2 or serial I/O2 interrupt enable bit
CNTR
0
or AD converter interrupt enable bit
Not used (returns “0” when read)
(Do not write “1” to this bit) 0 : Interrupts disabled
1 : Interrupts enabled
(ICON1 : address 003E
16
)
1
1
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7534 Group
MITSUBISHI MICROCOMPUTERS
18
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Key Input Interrupt (Key-On Wake-Up)
A key-on wake-up interrupt request is generated by applying “L” level
to any pin of port P0 that has been set to input mode.
In other words, it is generated when the AND of input level goes from
“1” to “0”. An example of using a key input interrupt is shown in Fig-
ure 18, where an interrupt request is generated by pressing one of
the keys provided as an active-low key matrix which uses ports P00
to P03 as input ports.
Fig. 18 Connection example when using key input interrupt and port P0 block diagram
Port PXx
“L” level output
PULL register
bit 3 = “0”
Port P07
latch
Port P07
Direction register = “1”
***
P07 output
Key input interrupt request
Port P0
Input read circuit
* P-channel transistor for pull-up
** CMOS output buffer
PULL register
bit 3 = “0”
Port P06
latch
Port P06
Direction register = “1”
***
P06 output
PULL register
bit 3 = “0”
Port P05
latch
Port P05
Direction register = “1”
***
P05 output
PULL register
bit 3 = “0”
Port P04
latch
Port P04
Direction register = “1”
***
P04 output
PULL register
bit 2 = “1”
Port P03
latch
Port P03
Direction register = “0”
***
P03 input
PULL register
bit 2 = “1”
Port P02
latch
Port P02
Direction register = “0”
***
P02 input
PULL register
bit 1 = “1”
Port P01
latch
Port P01
Direction register = “0”
***
P01 input
PULL register
bit 0 = “1”
Port P00
latch
Port P00
Direction register = “0”
***
P00 input
Falling edge
detection
Falling edge
detection
Falling edge
detection
Falling edge
detection
Falling edge
detection
Falling edge
detection
Falling edge
detection
Falling edge
detection
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7534 Group
MITSUBISHI MICROCOMPUTERS
19
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Timers
The 7534 Group has 3 timers: timer X, timer 1 and timer 2.
The division ratio of every timer and prescaler is 1/(n+1) provided
that the value of the timer latch or prescaler is n.
All the timers are down count timers. When a timer reaches “0”, an
underflow occurs at the next count pulse, and the corresponding timer
latch is reloaded into the timer. When a timer underflows, the inter-
rupt request bit corresponding to each timer is set to “1”.
●Timer 1, Timer 2
Prescaler 12 always counts f(XIN)/16. Timer 1 and timer 2 always
count the prescaler output and periodically sets the interrupt request
bit.
●Timer X
Timer X can be selected in one of 4 operating modes by setting the
timer X mode register.
• Timer Mode
The timer counts the signal selected by the timer X count source
selection bit.
• Pulse Output Mode
The timer counts the signal selected by the timer X count source
selection bit, and outputs a signal whose polarity is inverted each
time the timer value reaches “0”, from the CNTR0 pin.
When the CNTR0 active edge switch bit is “0”, the output of the
CNTR0 pin is started with an “H” output.
At “1”, this output is started with an “L” output. When using a timer in
this mode, set the port P14 direction register to output mode.
• Event Counter Mode
The operation in the event counter mode is the same as that in the
timer mode except that the timer counts the input signal from the
CNTR0 pin.
When the CNTR0 active edge switch bit is “0”, the timer counts
the rising edge of the CNTR0 pin. When this bit is “1”, the timer
counts the falling edge of the CNTR0 pin.
• Pulse Width Measurement Mode
When the CNTR0 active edge switch bit is “0”, the timer counts the
signal selected by the timer X count source selection bit while the
CNTR0 pin is “H”. When this bit is “1”, the timer counts the signal
while the CNTR0 pin is “L”.
In any mode, the timer count can be stopped by setting the timer X
count stop bit to “1”. Each time the timer overflows, the interrupt
request bit is set.
Fig. 19 Structure of timer X mode register
Fig. 20 Timer count source set register
Timer X mode register
(TM : Address 002B
16
)
CNTR
0
active edge switch bit
0 : Interrupt at falling edge
Count at rising edge
(in event counter mode)
1 : Interrupt at rising edge
Count at falling edge
(in event counter mode)
Timer X operating mode bits
b1 b0
0 0 : Timer mode
0 1 : Pulse output mode
1 0 : Event counter mode
1 1 : Pulse width measurement mode
Not used (return “0” when read)
Timer X count stop bit
0 : Count start
1 : Count stop
b7 b0
Timer count source set register
(TCSS : Address 002E
16
)
b7 b0
Timer X count source selection bit (Note)
0 : f(X
IN
)/16
1 : f(X
IN
)/2
Not used (return “0” when read)
Note : To switch the timer X count source selection bit ,
stop the timer X count operation.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7534 Group
MITSUBISHI MICROCOMPUTERS
20
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 21 Block diagram of timer X, timer 1 and timer 2
Timer mode
pulse output mode
Q
R
To timer X
interrupt
request bit
f(X
IN
)/16 Timer X latch (8)
Timer X (8)
Prescaler X latch (8)
Prescaler X (8)
Pulse width
measurement
mode
f(X
IN
)/2
Timer X count
source selection bit
Event
counter
mode Timer X count stop bit
Port P1
4
direction
register
Q
“0”
“1”
CNTR
0
active
edge switch bit
Port P1
4
latch
Pulse output mode
“1”
“0”
CNTR
0
active
edge switch bit
P1
4
/CNTR
0
Toggle
flip-flop
Timer X latch write
Pulse output mode
T
To CNTR
0
interrupt
request bit
Data bus
To timer 1
interrupt
request bit
To timer 2
interrupt
request bit
Data bus
Prescaler 12 (8)
f(X
IN
)/16 Timer 1 (8) Timer 2 (8)
Timer 2 latch (8)Timer 1 latch (8)Prescaler 12 latch (8)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7534 Group
MITSUBISHI MICROCOMPUTERS
21
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 22 Block diagram of UART serial I/O
Fig. 23 Operation of UART serial I/O function
Serial I/O
●Serial I/O1
• Asynchronous serial I/O (UART) mode
Serial I/O1 can be used as an asynchronous (UART) serial I/O. A
dedicated timer (baud rate generator) is also provided for baud rate
generation when serial I/O1 is in operation.
Eight serial data transfer formats can be selected, and the transfer
formats to be used by a transmitter and a receiver must be identi-
cal.
Each of the transmit and receive shift registers has a buffer register
(the same address on memory). Since the shift register cannot be
written to or read from directly, transmit data is written to the trans-
mit buffer, and receive data is read from the respective buffer regis-
ters. These buffer registers can also hold the next data to be trans-
mitted and receive 2-byte receive data in succession.
By selecting “1” for continuous transmit valid bit (bit 2 of SIO1CON),
continuous transmission of the same data is made possible.
This can be used as a simplified PWM.
OE
PE FE
1/16
X
IN
1/4
1/16
Data bus
Receive Buffer Register
Address
(0018
16
)
Receive Shift Register
Receive buffer full flag (RBF)
Receive interrupt request (RI)
ST Detector
SP Detector UART Control Register
Address (001A
16
)
Character length selection bit
7-bit
8-bit
Address (001B
16
)
Clock Control Circuit
Baud Rate Generator
Division ratio 1/(n+1)
Address (001C
16
)
BRG count source selection bit
Transmit Buffer Register
Data bus
Transmit Shift Register
Address
(0018
16
)
Transmit shift register shift
completion flag (TSC)
Transmit buffer empty flag (TBE)
Transmit interrupt request (TI)
Address (0019
16
)
Character length selection bit
Transmit interrupt source selection bit
Continuous transmit valid bit
Serial I/O1 control register
P1
0
/R
X
D
P1
1
/T
X
D
Serial I/O1 status register
ST/SP/PA Generator
TSC=0
TBE=1
RBF=0
TBE=0 TBE=0
RBF=1 RBF=1
STD
0
D
1
SP D
0
D
1
ST SP
TBE=1 TSC=1*
STD
0
D
1
SP D
0
D
1
ST SP
1 : Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).
2 : The transmit interrupt (TI) can be selected to occur when either the TBE or TSC flag becomes “1”, depending on the setting of the transmit
interrupt source selection bit (TIC) of the serial I/O1 control register.
3 : The receive interrupt (RI) is set when the RBF flag becomes “1”.
4 : After data is written to the transmit buffer when TSC = 1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC = 0.
Notes
Transmit/Receive Clock
Transmit Buffer Register
Write Signal
Serial Output T
X
D
Receive Buffer Register
Read Signal
Serial Input R
X
D
* Generated at second bit in 2-stop -bit
mode
1 Start Bit
7 or 8 Data Bit
1 or 0 Parity Bit
1 or 2 Stop Bit
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7534 Group
MITSUBISHI MICROCOMPUTERS
22
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
[Serial I/O1 control register] SIO1CON
The serial I/O1 control register consists of eight control bits for the
serial I/O1 function.
[UART control register] UARTCON
The UART control register consists of four control bits (bits 0 to 3)
which are valid when asynchronous serial I/O is selected and set the
data format of an data transfer. One bit in this register (bit 4) is al-
ways valid and sets the output structure of the P11/TxD pin.
[UART status register] UARTSTS
The read-only UART status register consists of seven flags (bits 0 to
6) which indicate the operating status of the UART function and vari-
ous errors. This register functions as the UART status register
(UARTSTS) when selecting the UART.
The receive buffer full flag (bit 1) is cleared to “0” when the receive
buffer is read.
If there is an error, it is detected at the same time that data is trans-
ferred from the receive shift register to the receive buffer, and the
receive buffer full flag is set. A write to the UART status register clears
all the error flags OE, PE, FE, and SE (bit 3 to bit 6, respectively).
Writing “0” to the serial I/O1 mode selection bits MOD1 and MOD0
(bit 7 and 6 of the Serial I/O1 control register ) also clears all the
status flags, including the error flags.
All bits of the serial I/O1 status register are initialized to “8116” at
reset, but if the transmit enable bit (bit 4) of the serial I/O1 control
register has been set to “1”, the continuous transmit valid bit (bit 2)
becomes “1”.
[Transmit/Receive buffer register] TB/RB
The transmit buffer and the receive buffer are located at the same
address. The transmit buffer is write-only and the receive buffer is
read-only. If a character bit length is 7-bit, the MSB of data stored in
the receive buffer is “0”.
Fig. 24 Continuous transmission operation of UART serial I/O
[Baud Rate Generator] BRG
The baud rate generator determines the baud rate for serial transfer.
The baud rate generator divides the frequency of the count source
by 1/(n + 1), where n is the value written to the baud rate generator.
TSC=0
TBE=1
TBE=0
STD
0
D
1
SP D
0
D
1
ST SP ST
1 : When the serial I/O1 mode selection bits (b7, b6) is “10”, the transmit enable bit is “1”, and continuous transmit valid bit is “1”, writing on the
transmit buffer initiates continuous transmission of the same data.
2 : Select 0 for continuous transmit valid bit to stop continuous transmission.
The T
X
D pin will stop at high level after completing transmission of 1 byte.
3 : If the transmit buffer contents are rewritten during a continuous transmission, transmission of the rewritten data will be started after
completing transmission of 1 byte.
Notes
1 Start Bit
7 or 8 Data Bit
1 or 0 Parity Bit
1 or 2 Stop Bit
Transmit/Receive Clock
Transmit Buffer Register
Write Signal
Serial Output T
X
D
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7534 Group
MITSUBISHI MICROCOMPUTERS
23
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
• Universal serial bus (USB) mode
By setting bits 7 and 6 of the serial I/O1 control register (address
001A16) to “11”, the USB mode is selected.
This mode conforms to “Low Speed device” of USB Specification
1.1. In this mode serial I/O1 interrupt have 5 sources; USB in and
out token receive, USB reset, suspend, and resume. The USB
Fig. 26 USB transceiver block diagram
status/UART status register functions as the USB status register
(USBSTS).There is the USBVREFOUT pin for the USB reference
voltage output, and a D-line with 1.5 kΩ external resistor can be pull
up. USB mode block and USB transceiver block show in figures 25
and 26.
Fig. 25 USB mode block diagram
XIN
Address 001816
Receive shift register
RxRDY
Receive buffer register
SYNC decoder
PID decoder
RxPID
OPID
PIDE
Address
comparative unit
USBA
End pointer
decoder
RxEP
CRC check
CRCE
Reset interrupt request
Suspend interrupt request
Resume interrupt request
Token interrupt request
EOP
NRZI,
bit stuffing decoder
BSTFE
Bus state
detection
Digital
PLL
6 MHz
USB
transceiver
NRZI,
bit stuffing encoder
Data bus
Data bus
Address 001816
Transmit shift register
TxRDY
Transmit buffer register
EP0BYTE
EP1BYTE
SYNC, PID
generating unit
EP0PID
EP1PID
CRC encoder
EOP generating unit
USB transmit unit
P10/D-
P11/D+
Differential input and
Single end input
Output data and
I/O control
1.5 MHz
Serial I/O1 control register
MOD0
MOD1
USB reference
power source voltage
USB control register
UVOE
(initial value “0”)
Output enable signal
Voltage input
Output amplifier USBV
REFOUT
D+/D-
output amplifier
Internal D- output signal
Internal D+ output signal
D-
D+
Suspend
OE
(internal signal)
Signal for function stop
Output enable signal
-
+
Differential input
Single end input
Single end input
Voltage input
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7534 Group
MITSUBISHI MICROCOMPUTERS
24
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 27 Structure of serial I/O1-related registers (1)
b7 b0
b7 b0
USB status register
(USBSTS: address 0019
16
)
Transmit buffer empty flag
0: Buffer full
1: Buffer empty
EOP detection flag
0: Not detected
1: Detect
False EOP error flag
0: No error
1: False EOP error
CRC error flag
0: No error
1: CRC error
PID error flag
0: No error
1: PID error
Bit stuffing error flag
0: No error
1: Bit stuffing error
Summing error flag
0: No error
1: Summing error
Receive buffer full flag
0: Buffer empty
1: Buffer full
b7 b0
Transmit buffer register
(TB: address 0018
16
)
After setting data to address 0018
16
, a content of the
transmit buffer register transfers to the transmit shift
register automatically.
CPU read: Disabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Not used
Receive buffer register
(RB: address 0018
16
)
By reading data from address 0018
16
, a content of the
receive buffer register can be read out.
CPU read: Enabled
CPU write: Disabled
Hardware read: Not used
Hardware write: Set/Clear
CPU read: Enabled
CPU write: Disabled
Hardware read: Not used
Hardware write: Set/Clear
CPU read: Enabled
CPU write: Clear
Hardware read: Not used
Hardware write: Set
CPU read: Enabled
CPU write: Disabled
Hardware read: Not used
Hardware write: Set/Clear
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7534 Group
MITSUBISHI MICROCOMPUTERS
25
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 28 Structure of serial I/O1-related registers (2)
Not used (return “1” when read)
Endpoint 1 enable
0: Endpoint 1 invalid
1: Endpoint 1 valid
USB reset interrupt enable
0: USB reset invalid
1: USB reset valid
Resume interrupt enable
0: Resume invalid
1: Resume valid
Token interrupt enable
0: Token invalid
1: Token valid
USB enable flag
0: USB invalid
1: USB valid
b7 b0
CPU read: Enabled
CPU write: Clear
Hardware read: Not used
Hardware write: Set
USB data toggle synchronization register
(TRSYNC: address 001D
16
)
Not used (return “1” when read)
Sequence bit toggle flag
0: No toggle
1: Sequence toggle
b7 b0
CPU read: Enabled
CPU write: Disabled
Hardware read: Not used
Hardware write: Set/Clear
USB interrupt source discrimination register 1
(USBIR1: address 001E
16
)
Not used (return “1” when read)
Endpoint determination flag
0: Endpoint 0 interrupt
1: Endpoint 1 interrupt
b7 b0
b7 b0
CPU read: Enabled
CPU write: Clear
Hardware read: Not used
Hardware write: Set
USB interrupt source discrimination register 2
(USBIR2: address 001F
16
)
Not used (return “1” when read)
Suspend request flag
0: No request
1: Suspend request
USB reset request flag
0: No request
1: Reset request
Not used (return “1” when read)
Token PID determination flag
0: SETUP interrupt
1: OUT interrupt
Token interrupt flag
0: No request
1: Token request
CPU read: Enabled
CPU write: Disabled
Hardware read: Not used
Hardware write: Set/Clear
CPU read: Enabled
CPU write: Disabled
Hardware read: Not used
Hardware write: Set/Clear
USB interrupt control register
(USBICON: address 0020
16
)
CPU read: Enabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Not used
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7534 Group
MITSUBISHI MICROCOMPUTERS
26
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 29 Structure of serial I/O1-related registers (3)
b7 b0
USB transmit data byte number set register 1
(EP1BYTE: address 0022
16
)
Set a number of data byte for transmitting with endpoint 1.
CPU read: Enabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Not used
Not used (return “0” when read)
b7 b0
USB transmit data byte number set register 0
(EP0BYTE: address 0021
16
)
Set a number of data byte for transmitting with endpoint 0.
CPU read: Enabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Not used
Not used (return “0” when read)
b7 b0
USB address register
(USBA: address 0025
16
)
Set an address allocated by the USB host.
CPU read: Disabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Not used
Not used (returns “1” when read)
USB PID control register 1
(EP1PID: address 0024
16
)
Not used (return “1” when read)
Endpoint 1 PID selection flag
1x: IN token interrupt of DATA0/1 is valid
01: STALL handshake is valid for IN token
00: NACK handshake is valid for IN token
b7 b0
x: any data
b6
CPU read: Enabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Not used
b7
CPU read: Enabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Clear
b7 b0
USB PID control register 0
(EP0PID: address 0023
16
)
Not used (return “1” when read)
Endpoint 0 enable flag
0: Endpoint 0 invalid
1: Endpoint 0 valid
Endpoint 0 PID selection flag
1xxx: IN token interrupt of DATA0/1 is valid
01xx: STALL handshake is valid for IN token
00xx: NACK handshake is valid for IN token
xxx1: STALL handshake is valid for OUT token (Note)
xx10: ACK handshake is valid for OUT token
xx00: NACK handshake is valid for OUT token
CPU read: Enabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Not used
b4, b5, b6
CPU read: Enabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Not used
b7
CPU read: Enabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Clear
x: any data
Note: In the status stage of the control read transfer, when PID
of data packet = DATA0 (incorrect PID), this bit is set forcibly
by hardware and STALL handshake is valid.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7534 Group
MITSUBISHI MICROCOMPUTERS
27
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 30 Structure of serial I/O1-related registers (4)
USB sequence bit initialization register
(INISQ1: address 002616)
A sequence bit of endpoint 1 is initialized.
CPU read: Disabled
CPU write: Dummy
Hardware read: Not used
Hardware write: Not used
b7 b0
b7 b0
b7 b0
b7 b0
USB control register
(USBCON: address 002716)
Not used (return “1” when read)
USBVREFOUT output valid flag
0: Output off
1: Output on
Remote wake up request flag
0: No request
1: Remote wake up request
CPU read: Disabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Not used
CPU read: Disabled
CPU write: Set
Hardware read: Used
Hardware write: Clear
UART status register
(UARTSTS: address 001916)
Transmit buffer empty flag
0: Buffer full
1: Buffer empty
Receive buffer full flag
0: Buffer empty
1: Buffer full
Transmit shift register shift completion flag
0: Transmit shift in progress
1: Transmit shift completed
Overrun error flag
0: No error
1: Overrun error
Parity error flag
0: No error
1: Parity error
Framing error flag
0: No error
1: Framing error
Summing error flag
0: No error
1: Summing error
Not used (returns “1” when read)
CPU read: Enabled
CPU write: Disabled
Hardware read: Not used
Hardware write: Set/Clear
Baud rate generator
(BRG: address 001C16)
This register is valid only when selecting the UART mode.
A baud rate value is set.
CPU read: Disabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Not used
CPU read: Enabled
CPU write: Clear
Hardware read: Not used
Hardware write: Set
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7534 Group
MITSUBISHI MICROCOMPUTERS
28
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 31 Structure of serial I/O1-related registers (5)
UART control register
(UARTCON: address 001B
16
)
Character length selection bit
0: 8 bits
1: 7 bits
Parity enable bit
0: Parity checking disabled
1: Parity checking enabled
Parity selection bit
0: Even parity
1: Odd parity
Stop bit length selection bit
0: 1 stop bit
1: 2 stop bits
P-channel output disable bit
0: CMOS output
1: N-channel open-drain output
Not used (returns “1” when read)
CPU read: Disabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Not used
b7 b0
b7 b0
Serial I/O1 control register
(SIO1CON: address 001A
16
)
BRG count source selection bit
0: f(X
IN
)
1: f(X
IN
)/4
Not used (returns “1” when read)
Continuous transmit valid bit
0: Continuous transmit invalid
1: Continuous transmit valid
Transmit interrupt source selection bit
0: Interrupt when transmit buffer has
emptied
1: Interrupt when transmit shift
operation is completed
Transmit enable bit
0: Transmit disabled
1: Transmit enabled
Receive enable bit
0: Receive disabled
1: Receive enabled
Serial I/O1 mode selection bits
00: I/O port
01: Not available
10: UART mode
11: USB mode
CPU read: Disabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Not used
CPU read: Disabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Not used
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7534 Group
MITSUBISHI MICROCOMPUTERS
29
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Note on using USB mode
Handling of SE0 signal in program (at receiving)
7534 group has the border line to detect as USB RESET or EOP
(End of Packet) on the width of SE0 (Single Ended 0).
A response apposite to a state of the device is expected.
The name of the following short words which is used in table 5 shows
as follow.
•TKNE: Token interrupt enable (bit 6 of address 2016)
•RSME: Resume interrupt enable (bit 5 of address 2016)
•RSTE: USB reset interrupt enable (bit 4 of address 2016)
•Spec: A response of the device requested by USB Specification 1.1
•SIE: Hardware operation in 7534 group
•F/W: Recommendation process in the program
•FEOPE: False EOP error flag (bit 2 of address 1916)
•RxPID: Token interrupt flag (bit 7 of address 1F16)
Spec
SIE
F/W
Reset or resume
Reset interrupt
request
Reset interrupt
processing
Resume interrupt
processing
Table 5 Relation of the width of SE0 and the state of the device
Width of SE0
0 µ sec.
0.5 µ sec.
0.5 µ sec.
2.5 µ sec.
2.5 µ sec.
2.67 µ sec.
2.67 µ sec.
Spec
SIE
F/W
Spec
SIE
F/W
Spec
SIE
F/W
Spec
SIE
F/W
Idle state
TKNE = X
RSME = 0
RSTE =1
Ignore
Keep counting suspend
timer
Not acknowledge
Keep alive
Initialize suspend timer
count value
Not acknowledge
Keep alive or Reset
may determine as keep
alive and Reset interrupt
Keep alive in case of no
interrupt request
Reset processing in case
of interrupt request
Reset
Reset interrupt request
Reset processing
End of Token in transaction
TKNE = 1
RSME = 0
RSTE =1
Ignore
Not detected as EOP(in
case of no detection EOP,
SIE returns idle state as
time out. FEOPE flag is
set.)
Not acknowledge
EOP
Token interrupt request
Token interrupt processing
execute
EOP or Reset
may determine as EOP and
Reset interrupt
RxPID = 1> Token interrupt
processing
RxPID = 0> Reset interrupt
processing
Reset
Reset interrupt request
Reset processing
End of data or handshake
in transaction
TKNE = 0
RSME = 0
RSTE = 0 or 1
Ignore
Not detected as EOP(in
case of no detection EOP,
SIE returns idle state as
timeup. FEOPE flag is
set.)
Wait for the next EOP flag
EOP
Set EOP flag
After checking the set of
EOP flag, go to the next
processing
EOP or Reset
may determine as EOP
and Reset interrupt
Continue the processing
in case of no interrupt
request
Reset processing in case
of interrupt request
Reset
Reset interrupt request
Reset processing
Suspend state
TKNE = 0
RSME = 1
RSTE = 0
State of device
• Function of USBPID control register 0 (address 002316)
Bit 4 (STALL handshake control for OUT token) of this register is forcibly set by SIE under the special condition shown below.
Set condition; when PID of data packet = DATA0 (incorrect PID) in the status stage of the control read transfer.
• SYNC field at reception
Normally, the SYNC field consists of “KJKJKJKK” (8 bits). However , as for SIE of the 7534 Group, when the low-order 6 bits are “KJKJKK”, it is
determined as SYNC.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7534 Group
MITSUBISHI MICROCOMPUTERS
30
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
●Serial I/O2
The serial I/O2 function can be used only for clock synchronous se-
rial I/O.
For clock synchronous serial I/O2 the transmitter and the receiver
must use the same clock. When the internal clock is used, transfer is
started by a write signal to the serial I/O2 register.
[Serial I/O2 control register] SIO2CON
The serial I/O2 control register contains 8 bits which control various
serial I/O functions.
• For receiving, set “0” to bit 3.
• When receiving, bit 7 is cleared by writing dummy data to serial I/
O2 register after shift is completed.
• Bit 7 is set earlier a half cycle of shift clock than completion of shift
operation. Accordingly, when checking shift completion by using
this bit, the setting is as follows:
(1) check that this bit is set to “1”,
(2) wait a half cycle of shift clock,
(3) read/write to serial I/O2 register. Fig. 32 Structure of serial I/O2 control registers
Fig. 33 Block diagram of serial I/O2
Serial I/O2 control register
(SIO2CON: address 0030
16
)
S
DATA
pin selection bit (Note)
0 : I/O port/S
DATA
input
1 : S
DATA
output
Internal synchronous clock selection bits
000 : f(X
IN
)/8
001 : f(X
IN
)/16
010 : f(X
IN
)/32
011 : f(X
IN
)/64
110 : f(X
IN
)/128
111 : f(X
IN
)/256
b7 b0
Not used
(returns “0” when read)
Transfer direction selection bit
0 : LSB first
1 : MSB first
S
CLK
pin selection bit
0 : External clock (S
CLK
is an input)
1 : Internal clock (S
CLK
is an output)
Transmit / receive shift completion flag
0 : shift in progress
1 : shift completed
Note : When using it as an S
DATA
input, set the port P1
3
direction register to “0”.
“1”
“0”
“0”
“1”
“0”
“1”
1/8
1/16
1/32
1/64
1/128
1/256
X
IN
Data bus
Serial I/O2
interrupt request
S
DATA
pin selection bit
Serial I/O counter 2 (3)
Serial I/O shift register 2 (8)
S
CLK
pin selection bit
Internal synchronous
clock selection bits
Divider
P1
2
/S
CLK
P1
3
/S
DATA
P1
2
latch
S
CLK pin
selection bit
S
CLK
P1
3
latch
S
DATA
pin selection bit
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7534 Group
MITSUBISHI MICROCOMPUTERS
31
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Serial I/O2 operation
By writing to the serial I/O2 register(address 003116) the serial I/O2
counter is set to “7”.
After writing, the SDATA pin outputs data every time the transfer clock
shifts from a high to a low level. And, as the transfer clock shifts from
a low to a high, the SDATA pin reads data, and at the same time the
contents of the serial I/O2 register are shifted by 1 bit.
When the internal clock is selected as the transfer clock source, the
following operations execute as the transfer clock counts up to 8.
• Serial I/O2 counter is cleared to “0”.
• Transfer clock stops at an “H” level.
• Interrupt request bit is set.
• Shift completion flag is set.
Also, the SDATA pin is in a high impedance state after the data trans-
fer is complete. Refer to Figure 34.
When the external clock is selected as the transfer clock source, the
interrupt request bit is set as the transfer clock counts up to 8, but
external control of the clock is required since it does not stop. Notice
that the SDATA pin is not in a high impedance state on the completion
of data transfer.
Fig. 34 Serial I/O2 timing (LSB first)
D
0
Note : When the internal clock is selected as the transfer and the direction register of P1
3
/S
DATA
pin is set to the input mode,
Synchronous clock
Serial I/O2 register
write signal
Transfer clock
(Note)
S
DATA
at serial I/O2
input receive
S
DATA
at serial I/O2
output transmit
Serial I/O2 interrupt request bit set
D
1
D
2
D
3
D
4
D
5
D
6
D
7
the S
DATA
pin is in a high impedance state after the data transfer is completed.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7534 Group
MITSUBISHI MICROCOMPUTERS
32
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
A-D Converter
The functional blocks of the A-D converter are described below.
[A-D conversion register] AD
The A-D conversion register is a read-only register that stores the
result of A-D conversion. Do not read out this register during an A-D
conversion.
[A-D control register] ADCON
The A-D control register controls the A-D converter. Bit 2 to 0 are
analog input pin selection bits. Bit 4 is the AD conversion completion
bit. The value of this bit remains at “0” during A-D conversion, and
changes to “1” at completion of A-D conversion.
A-D conversion is started by setting this bit to “0”.
[Comparison voltage generator]
The comparison voltage generator divides the voltage between VSS
and VREF by 1024 by a resistor ladder, and outputs the divided volt-
ages. Since the generator is disconnected from VREF pin and VSS
pin, current is not flowing into the resistor ladder.
[Channel Selector]
The channel selector selects one of ports P27/AN7 to P20/AN0, and
inputs the voltage to the comparator.
[Comparator and control circuit]
The comparator and control circuit compares an analog input volt-
age with the comparison voltage and stores its result into the A-D
conversion register. When A-D conversion is completed, the control
circuit sets the AD conversion completion bit and the AD interrupt
request bit to “1”. Because the comparator is constructed linked to a
capacitor, set f(XIN) to 500 kHz or more during A-D conversion.
Fig. 35 Structure of A-D control register
Fig. 36 Structure of A-D conversion register
Fig. 37 Block diagram of A-D converter
A-D control register
(ADCON : address 0034
16
)
Not used (returns “0” when read)
Not used (returns “0” when read)
AD conversion completion bit
0 : Conversion in progress
1 : Conversion completed
b7 b0
Analog input pin selection bits
000 : P2
0
/AN
0
001 : P2
1
/AN
1
010 : P2
2
/AN
2
011 : P2
3
/AN
3
100 : P2
4
/AN
4
101 : P2
5
/AN
5
110 : P2
6
/AN
6
111 : P2
7
/AN
7
Read 8-bit (Read only address 0035
16
)
b7 b0
b9 b8 b7 b6 b5 b4 b3 b2
(Address 0035
16
)
Read 10-bit (read in order address 0036
16
, 0035
16
)
b7 b0
b9 b8
(Address 0036
16
)
b7 b0
b7 b6 b5 b4 b3 b2 b1 b0
(Address 0035
16
)
High-order 6-bit of address 0036
16
returns “0” when read.
control register
d
dress 0034
16
)
Channel selector
A-D control circuit
Resistor ladder
V
SS
Comparator
A-D interrupt request
b7 b0
3
10
A-D conversion register (low-order)
(Address 0036
16
)
(Address 0035
16
)
A-D conversion register (high-order)
V
REF
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7534 Group
MITSUBISHI MICROCOMPUTERS
33
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Watchdog Timer
The watchdog timer gives a means for returning to a reset status
when the program fails to run on its normal loop due to a runaway.
The watchdog timer consists of an 8-bit watchdog timer H and an 8-
bit watchdog timer L, being a 16-bit counter.
Standard operation of watchdog timer
The watchdog timer stops when the watchdog timer control register
(address 003916) is not set after reset. Writing an optional value to
the watchdog timer control register (address 003916) causes the
watchdog timer to start to count down. When the watchdog timer H
underflows, an internal reset occurs. Accordingly, it is programmed
that the watchdog timer control register (address 003916) can be set
before an underflow occurs.
When the watchdog timer control register (address 003916) is read,
the values of the high-order 6-bit of the watchdog timer H, STP in-
struction disable bit and watchdog timer H count source selection bit
are read.
Initial value of watchdog timer
By a reset or writing to the watchdog timer control register (address
003916), the watchdog timer H is set to “FF16” and the watchdog
timer L is set to “FF16”.
Operation of watchdog timer H count source selection bit
A watchdog timer H count source can be selected by bit 7 of the
watchdog timer control register (address 003916). When this bit is
“0”, the count source becomes a watchdog timer L underflow signal.
The detection time is 174.763 ms at f(XIN)=6 MHz.
When this bit is “1”, the count source becomes f(XIN)/16. In this
case, the detection time is 683 µs at f(XIN)=6 MHz.
This bit is cleared to “0” after reset.
Operation of STP instruction disable bit
When the watchdog timer is in operation, the STP instruction can be
disabled by bit 6 of the watchdog timer control register (address
003916).
When this bit is “0”, the STP instruction is enabled.
When this bit is “1”, the STP instruction is disabled, and an internal
reset occurs if the STP instruction is executed.
Once this bit is set to “1”, it cannot be changed to “0” by program.
This bit is cleared to “0” after reset.
Fig. 38 Block diagram of watchdog timer
Fig. 39 Structure of watchdog timer control register
XIN
Data bus
“0”
“1”
1/16
Watchdog timer H count
source selection bit
Reset
circuit
STP Instruction Disable Bit
Watchdog timer H (8)
Write “FF16” to the
watchdog timer
control register
Internal reset
RESET
Watchdog timer L (8)
STP Instruction
Write “FF16” to the
watchdog timer
control register
Watchdog timer control register(address 0039
16
)
WDTCON
Watchdog timer H (read-only for high-order 6-bit)
STP instruction disable bit
0 : STP instruction enabled
1 : STP instruction disabled
Watchdog timer H count source selection bit
0 : Watchdog timer L underflow
1 : f(X
IN
)/16
b7 b0
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7534 Group
MITSUBISHI MICROCOMPUTERS
34
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Reset Circuit
The microcomputer is put into a reset status by holding the RESET
pin at the “L” level for 15 µs or more when the power source voltage
is 4.1 to 5.5 V and XIN is in stable oscillation.
After that, this reset status is released by returning the RESET pin to
the “H” level. The program starts from the address having the con-
tents of address FFFD16 as high-order address and the contents of
address FFFC16 as low-order address.
Note that the reset input voltage should be 0.82 V or less when the
power source voltage passes 4.1 V.
Fig. 40 Example of reset circuit
Fig. 41 Timing diagram at reset
(Note)
0.2 V
CC
0 V
0 V
Poweron
V
CC
RESET
V
CC
RESET
Power source
voltage
detection circuit
Power source
voltage
Reset input
voltage
Note : Reset release voltage Vcc= 4.1 V
Data
Address
8-13 clock cycles
Reset address from the
vector table
1 : A built-in ring oscillator applies about 250 kHz frequency as clock φ at average of Vcc = 5 V.
2 : The mark “?” means that the address is changeable depending on the previous state.
3 : These are all internal signals except RESET
Notes
φ
RESET
RESET
OUT
SYNC
?? FFFC FFFD
AD
H
,AD
L
???
?? AD
L
AD
H
???
Clock from built-in
ring oscillator
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7534 Group
MITSUBISHI MICROCOMPUTERS
35
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 42 Internal status of microcomputer at reset
Serial I/O1 control register
UART control register
(8)
(9)
Prescaler 12
Timer 1
Timer 2
Timer X mode register
Prescaler X
Timer X
Timer count source set register
Serial I/O2 control register
A-D control register
MISRG
Watchdog timer control register
Interrupt edge selection register
CPU mode register
Interrupt request register 1
Interrupt control register 1
Processor status register
Program counter
(21)
(22)
(23)
(24)
(25)
(26)
(27)
(28)
(29)
(30)
(31)
(32)
(33)
(34)
(35)
(36)
(37)
(6)
USB/UART status register
(7)
USB data toggle synchronization register
(10)
USB interrupt source discrimination register 1
(11)
USB interrupt source discrimination register 2
(12)
USB interrupt control register
(13)
USB transmit data byte number set register 0
(14)
USB transmit data byte number set register 1
(15)
USBPID control register 0
(16)
USBPID control register 1
(17)
USB address register
(18)
USB sequence bit initialization register
(19)
USB control register
(20)
001A
16
001B
16
02
16
11100000
Contents of address FFFC
16
(PC
H
)
(PC
L
)
FF
16
01
16
00
16
00
16
FF
16
FF
16
00
16
00
16
10
16
00
16
0028
16
0029
16
002A
16
002B
16
002C
16
002D
16
002E
16
0030
16
0034
16
0038
16
0039
16
003A
16
003B
16
003C
16
003E
16
(PS)
Note X : Undefined
Contents of address FFFD
16
00111111
00
16
00
16
00
16
10000000
XXXXX1XX
Port P0 direction register
Port P1 direction register
Port P2 direction register
Port P3 direction register
Port P4 direction register
(1)
(2)
(3)
(4)
(5)
Register contents
00
16
00
16
0001
16
0003
16
0005
16
0007
16
0009
16
X00000
Address
0019
16 10000001
001D
16 01111111
001E
16 01111111
001F
16 01110011
0020
16 00000111
0021
16
0022
16
0023
16 00000111
0024
16 00111111
0025
16 10000000
0026
16 11111111
0027
16 00111111
00
16
00
16
Pull-up control register
FF
16
0016
16
XXX 0 0XXX
00
16
00
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7534 Group
MITSUBISHI MICROCOMPUTERS
36
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 43 External circuit of ceramic resonator
Fig. 44 External clock input circuit
Fig. 45 Structure of MISRG
Clock Generating Circuit
An oscillation circuit can be formed by connecting a resonator be-
tween XIN and XOUT.
Use the circuit constants in accordance with the resonator
manufacturer's recommended values. No external resistor is needed
between XIN and XOUT since a feed-back resistor exists on-chip.
●Oscillation control
• Stop mode
When the STP instruction is executed, the internal clock φ stops at
an “H” level and the XIN oscillator stops. At this time, timer 1 is set to
“0116” and prescaler 12 is set to “FF16” when the oscillation
stabilization time set bit after release of the STP instruction is “0”.
On the other hand, timer 1 and prescaler 12 are not set when the
above bit is “1”. Accordingly, set the wait time fit for the oscillation
stabilization time of the oscillator to be used.
f(XIN)/16 is forcibly connected to the input of prescaler 12.
When an external interrupt is accepted, oscillation is restarted but
the internal clock φ remains at “H” until timer 1 underflows. As soon
as timer 1 underflows, the internal clock φ is supplied. This is
because when a ceramic oscillator is used, some time is required
until a start of oscillation.
In case oscillation is restarted by reset, no wait time is generated.
______
So apply an “L” level to the RESET pin while oscillation becomes
stable.
• Wait mode
If the WIT instruction is executed, the internal clock φ stops at an
“H” level, but the oscillator does not stop. The internal clock restarts
if a reset occurs or when an interrupt is received.
Since the oscillator does not stop, normal operation can be started
immediately after the clock is restarted.
To ensure that interrupts will be received to release the STP or WIT
state, interrupt enable bits must be set to “1” before the STP or
WIT instruction is executed.
When the STP status is released, prescaler 12 and timer 1 will start
counting clock which is XIN divided by 16, so set the timer 1 inter-
rupt enable bit to “0” before the STP instruction is executed.
Note
For use with the oscillation stabilization set bit after release of the
STP instruction set to “1”, set values in timer 1 and prescaler
12 after fully appreciating the oscillation stabilization time of the
oscillator to be used.
• Clock mode
Operation is started by a built-in ring oscillator after releasing reset.
A division ratio (1/1,1/2,1/8) is selected by setting bits 7 and 6 of the
CPU mode register after releasing it.
X
IN
C
OUT
C
IN
X
OUT
X
IN
X
OUT
External oscillation
circuit
V
CC
V
SS
Open
MISRG(Address 0038
16
)
b7 b0
Oscillation stabilization time set bit after
release of the STP instruction
0: Set “01
16
” in timer1, and “FF
16
”
in prescaler 12 automatically
1: Not set automatically
Reserved bits (return “0” when read)
(Do not write “1” to these bits)
Not used (return “0” when read)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7534 Group
MITSUBISHI MICROCOMPUTERS
37
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 46 Block diagram of system clock generating circuit (for ceramic resonator)
S
R
QS
R
Q
1/2
Rd
R
S
Q
Rf
1/4 1/2
WIT
instruction STP instruction
Timing φ
(Internal clock)
STP instruction
Interrupt request
Reset
Interrupt disable flag l
High-speed mode
Middle-speed mode
Prescaler 12 Timer 1
Main clock division
ratio selection bit
Double-speed mode
Ring oscillator mode
Ring oscillator
(Note)
Note: Ring oscillator is used only for starting.
X
OUT
X
IN
1/8
Middle-speed, High-speed, double -speed mode
Main clock division ratio selection bit
Ring oscillator
mode
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7534 Group
MITSUBISHI MICROCOMPUTERS
38
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
NOTES ON PROGRAMMING
Processor Status Register
The contents of the processor status register (PS) after reset are
undefined except for the interrupt disable flag I which is “1”. After
reset, initialize flags which affect program execution. In particular, it
is essential to initialize the T flag and the D flag because of their
effect on calculations.
Interrupts
The contents of the interrupt request bit do not change even if the
BBC or BBS instruction is executed immediately after they are
changed by program because this instruction is executed for the pre-
vious contents. For executing the instruction for the changed con-
tents, execute one instruction before executing the BBC or BBS in-
struction.
Decimal Calculations
• For calculations in decimal notation, set the decimal mode flag D to
“1”, then execute the ADC instruction or SBC instruction. In this
case, execute SEC instruction, CLC instruction or CLD instruction
after executing one instruction before the ADC instruction or SBC
instruction.
• In the decimal mode, the values of the N (negative), V (overflow)
and Z (zero) flags are invalid.
Timers
• When n (0 to 255) is written to a timer latch, the frequency division
ratio is 1/(n+1).
• When a count source of timer X is switched, stop a count of timer X.
Ports
• The values of the port direction registers cannot be read.
That is, it is impossible to use the LDA instruction, memory opera-
tion instruction when the T flag is “1”, addressing mode using di-
rection register values as qualifiers, and bit test instructions such
as BBC and BBS.
It is also impossible to use bit operation instructions such as CLB
and SEB and read/modify/write instructions of direction registers
for calculations such as ROR.
For setting direction registers, use the LDM instruction, STA in-
struction, etc.
• As for the 36-pin version, set "1" to each bit 6 of the port P3 direc-
tion register and the port P3 register.
• As for the 32-pin version, set “1” to respective bits 5, 6, 7 of the port
P3 direction register and port P3 register.
A-D Converter
The comparator uses internal capacitors whose charge will be lost if
the clock frequency is too low.
Make sure that f(XIN) is 500kHz or more during A-D conversion.
Do not execute the STP instruction during A-D conversion.
Instruction Execution Timing
The instruction execution time can be obtained by multiplying the
frequency of the internal clock φ by the number of cycles mentioned
in the machine-language instruction table.
The frequency of the internal clock f is the same as that of the
XIN in double-speed mode, twice the XIN cycle in high-speed
mode and 8 times the XIN cycle in middle-speed mode.
NOTES ON USE
Handling of Power Source Pin
In order to avoid a latch-up occurrence, connect a capacitor suitable
for high frequencies as bypass capacitor between power source pin
(Vcc pin) and GND pin (Vss pin). Besides, connect the capacitor to
as close as possible. For bypass capacitor which should not be lo-
cated too far from the pins to be connected, a ceramic capacitor of
0.1 µF is recommended.
Handling of USBVREFOUT Pin
In order to prevent the instability of the USBVREFOUT output due to
external noise, connect a capacitor as bypass capacitor between
USBVREFOUT pin and GND pin (VSS pin). Besides, connect the ca-
pacitor to as close as possible. For bypass capacitor, a ceramic or
electrolytic capacitor of 0.1 µF is recommended.
One Time PROM Version
The CNVss pin is connected to the internal memory circuit block by a
low-ohmic resistance, since it has the multiplexed function to be a
programmable power source pin (VPP pin) as well.
To improve the noise reduction, connect a track between CNVss pin
and Vss pin with 1 to 10 kΩ resistance.
The mask ROM version track of CNVss pin has no operational inter-
ference even if it is connected via a resistor.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7534 Group
MITSUBISHI MICROCOMPUTERS
39
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
DATA REQUIRED FOR MASK ORDERS
The following are necessary when ordering a mask ROM produc-
tion:
(1) Mask ROM Order Confirmation Form
(2) Mark Specification Form
(3) Data to be written to ROM, in EPROM form
(three identical copies)
ROM PROGRAMMING METHOD
The built-in PROM of the blank One Time PROM version can be
read or programmed with a general-purpose PROM programmer us-
ing a special programming adapter. Set the address of PROM pro-
grammer in the user ROM area.
The PROM of the blank One Time PROM version is not tested or
screened in the assembly process and following processes. To en-
sure proper operation after programming, the procedure shown in
Figure 47 is recommended to verify programming.
Package
36P2R-A
42P4B
Name of Programming Adapter
PCA7435FP
PCA7435SP
Table 6 Special programming adapter
Fig. 47 Programming and testing of One Time PROM version
Programming with
PROM programmer
Screening (Caution)
(150 °C for 40 hours)
Verification with PROM
programmer
Functional check in
target device
The screening temperature is far higher
than the storage temperature. Never
expose to 150 °C exceeding 100 hours.
Caution:
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7534 Group
MITSUBISHI MICROCOMPUTERS
40
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Table 7 Absolute maximum ratings
–0.3 to 7.0
–0.3 to VCC + 0.3
–0.3 to VCC + 0.3
–0.3 to 13
–0.3 to VCC + 0.3
1000 (Note 3)
–20 to 85
–40 to 125
Power source voltage
Input voltage P00–P07, P10–P16, P20–P27, P30–
P37, VREF, P40, P41
Input voltage RESET, XIN
Input voltage CNVSS (Note 1)
Output voltage P00–P07, P10–P16, P20–P27, P30–
P37, XOUT, USBVREFOUT, P40, P41
Power dissipation (Note 2)
Operating temperature
Storage temperature
V
V
V
V
V
mW
°C
°C
VCC
VI
VI
VI
VO
Pd
Topr
Tstg
ConditionsSymbol Ratings UnitParameter
All voltages are
based on VSS.
Output transistors
are cut off.
Ta = 25°C
Notes 1: It is a rating only for the One Time PROM version. Connect to VSS for mask ROM version.
2: The rating value depends on packages.
3: The value of the 36-pin version is 300 mW.
The value of the 32-pin version is 200 mW.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7534 Group
MITSUBISHI MICROCOMPUTERS
41
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Recommended Operating Conditions
Table 8 Recommended operating conditions
(VCC = 4.1 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol Parameter Unit
Power source voltage
Limits
f(XIN) =
6 MHz
VCC
VSS
VREF
VIH
VIH
VIH
VIH
VIL
VIL
VIL
VIL
VIL
∑IOH(peak)
∑IOL(peak)
∑IOL(peak)
∑IOH(avg)
∑IOL(avg)
∑IOL(avg)
IOH(peak)
IOL(peak)
IOL(peak)
IOH(avg)
IOL(avg)
IOL(avg)
f(XIN)
V
V
V
V
V
V
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
MHz
Note 1:The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average
value measured over 100 ms. The total peak current is the peak value of all the currents.
2: The peak output current is the peak current flowing in each port.
3: The average output current IOL (avg), IOH (avg) in an average value measured over 100 ms.
4: When the oscillation frequency has a duty cycle of 50 %.
5.5
VCC
VCC
VCC
VCC
3.6
0.3 VCC
0.8
0.2 VCC
0.8
0.16VCC
–80
80
60
–40
40
30
–10
10
30
–5
5
15
6
Max.
Power source voltage
Analog reference voltage
“H” input voltage P00–P07, P10–P16, P20–P27,
P30–P37, P40, P41
“H” input voltage (TTL input level selected) P10, P12, P13, P36, P37
“H” input voltage RESET, XIN
“H” input voltage D+, D-
“L” input voltage P00–P07, P10–P16, P20–P27,
P30–P37, P40, P41
“L” input voltage (TTL input level selected) P10, P12, P13, P36, P37
“L” input voltage RESET, CNVSS
“L” input voltage D+, D-
“L” input voltage XIN
“H” total peak output current (Note 1) P00–P07, P10–P16, P20–P27,
P30–P37, P40, P41
“L” total peak output current (Note 1) P00–P07, P10–P16, P20–P27,
P37, P40, P41
“L” total peak output current (Note 1) P30–P36
“H” total average output current (Note 1) P00–P07, P10–P16, P20–P27,
P30–P37, P40, P41
“L” total average output current (Note 1) P00–P07, P10–P16, P20–P27,
P37, P40, P41
“L” total average output current (Note 1) P30–P36
“H” peak output current (Note 2) P00–P07, P10–P16, P20–P27,
P30–P37, P40, P41
“L” peak output current (Note 2) P00–P07, P10–P16, P20–P27,
P37 , P40, P41
“L” peak output current (Note 2) P30–P36
“H” average output current (Note 3) P00–P07, P10–P16, P20–P27,
P30–P37, P40, P41
“L” average output current (Note 3) P00–P07, P10–P16, P20–P27,
P37, P40, P41
“L” average output current (Note 3) P30–P36
Oscillation frequency (Note 4) VCC = 4.1 to 5.5 V
at ceramic oscillation or external clock input Double-speed mode
Typ.
5.0
0
4.1
2.0
0.8 VCC
2.0
0.8 VCC
2.0
0
0
0
0
0
Min.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7534 Group
MITSUBISHI MICROCOMPUTERS
42
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Electrical Characteristics
Table 9 Electrical characteristics (1) (VCC = 4.1 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Min. Typ. Max.
Symbol Parameter Limits
IOH = –5 mA
VCC = 4.1 to 5.5 V
IOH = –1.0 mA
VCC = 4.1 to 5.5 V
VCC = 4.4 to 5.25 V
Pull-down through
15kΩ ±5 % for D+, D-
Pull-up through 1.5kΩ
±5 % by USBVREFOUT
for D- (Ta = 0 to 70 °C)
IOL = 5 mA
VCC = 4.1 to 5.5 V
IOL = 1.5 mA
VCC = 4.1 to 5.5 V
VCC = 4.4 to 5.25 V
Pull-down through
15kΩ ±5 % for D+, D-
Pull-up through 1.5kΩ
±5 % by USBVREFOUT
for D-(Ta = 0 to 70 °C)
IOL = 15 mA
VCC = 4.1 to 5.5 V
IOL = 1.5 mA
VCC = 4.1 to 5.5 V
VI = VCC
(Pin floating. Pull-up
transistors “off”)
VI = VCC
VI = VCC
VI = VSS
(Pin floating. Pull-up
transistors “off”)
VI = VSS
VI = VSS
VI = VSS
(Pull-up transistors“on”)
Test conditions
VCC–1.5
VCC–1.0
2.8
“H” output voltage P00–P07, P10–P16, P20–P27,
P30–P37, P40, P41 (Note 1)
“H” output voltage D+, D-
“L” output voltage P00–P07, P10–P16, P20–P27,
P37, P40, P41
“L” output voltage D+, D-
“L” output voltage P30–P36
Hysteresis D+, D-
Hysteresis CNTR0, INT0, INT1 (Note 2),
P00–P07(Note 3)
Hysteresis RXD, SCLK, SDATA (Note 2)
Hysteresis RESET
“H” input current P00–P07, P10–P16, P20–P27,
P30–P37, P40, P41
“H” input current RESET
“H” input current XIN
“L” input current P00–P07, P10–P16, P20–P27,
P30–P37, P40, P41
“L” input current RESET, CNVSS
“L” input current XIN
“L” input current P00–P07, P30–P37
RAM hold voltage
V
V
VOH
VOH 3.6 V
VOL
0.3
1.5 V
V
0.3 V
2.0
0.3 V
V
VOL
VOL
VT+–VT–
VT+–VT–
VT+–VT–
IIH
IIH
IIL
IIH
IIL
IIL
IIL
VRAM When clock stopped
0.5
0.5
0.4 V
V
V
4
–4
–0.2
5.0
5.0
–5.0
–5.0
–0.5
µA
µA
µA
µA
µA
µA
mA
2.0 5.5 V
Note 1:P11 is measured when the P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2:RXD, SCLK, SDATA, INT0 and INT1 have hystereses only when bits 0, 1 and 2 of the port P1P3 control register are set to “0” (CMOS level).
3:It is available only when operating key-on wake-up.
Unit
VT+–VT– 0.15 V
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7534 Group
MITSUBISHI MICROCOMPUTERS
43
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Resolution
Linearity error
Differential nonlinear error
Zero transition voltage
Full scale transition voltage
Conversion time
Ladder resistor
Reference power source input current
A-D port input current
Min. Typ. Max.
Symbol Parameter Limits Unit
Test conditions
VCC = 4.1 to 5.5 V
Ta = 25 °C
VCC = 4.1 to 5.5 V
Ta = 25 °C
0520
LSB
LSB
Bits
±0.9
±3
10
A-D Converter Characteristics
Table 11 A-D Converter characteristics (1) (VCC = 4.1 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
mV
5105
50
30
5115 5125 mV
—
—
—
VOT
VFST
tCONV
RLADDER
IVREF
II(AD)
VREF = 5.0 V
122
200
55
150
tc(XIN)
kΩ
5.0 µA
µA
VREF = 3.0 V 120
70
VCC = VREF = 5.12 V
VCC = VREF = 5.12 V
Fig. 48 Power source current measurement circuit in USB mode
at oscillation stop
V
CC
I
CC
V
CC
V
SS
USBV
REFOUT
D-
1.5 kΩ
15 kΩ
I
OUT
I
OUT
is included to this ratings.
Table 10 Electrical characteristics (2)
(VCC = 4.1 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
ICC Power source current 6
1.6
0.8
0.1
10 mA
mA
mA
Double-speed mode, f(XIN) = 6 MHz,
Output transistors “off”
f(XIN) = 6 MHz, (in WIT state)
Output transistors “off”
Increment when A-D conversion is executed
f(XIN) = 6 MHz, VCC = 5 V
All oscillation stopped (in STP state)
Output transistors “off”
VCC = 4.4 V to 5.25 V
Oscillation stopped in USB mode
USB (SUSPEND), (pull-up resistor
output included) (Fig. 48)
Ta = 25 °C
Ta = 85 °C1.0
10 µA
µA
Ta = 0 to 70 °C300 µA
Min. Typ. Max.
Symbol Parameter Limits
Test conditions Unit
3.2
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7534 Group
MITSUBISHI MICROCOMPUTERS
44
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Timing Requirements
Table 12 Timing requirements (VCC = 4.1 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Min. Typ. Max.
Symbol Parameter Limits Unit
tW(RESET)
tC(XIN)
tWH(XIN)
tWL(XIN)
tC(CNTR)
tWH(CNTR)
tWL(CNTR)
tC(SCLK)
tWH(SCLK)
tWL(SCLK)
tsu(SDATA–SCLK)
th(SCLK–SDATA)
Reset input “L” pulse width
External clock input cycle time
External clock input “H” pulse width
External clock input “L” pulse width
CNTR0 input cycle time
CNTR0, INT0, INT1 input “H” pulse width
CNTR0, INT0, INT1 input “L” pulse width
Serial I/O2 clock input cycle time
Serial I/O2 clock input “H” pulse width
Serial I/O2 clock input “L” pulse width
Serial I/O2 input set up time
Serial I/O2 input hold time
15
166
70
70
200
80
80
1000
400
400
200
200
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Switching Characteristics
Table 13 Switching characteristics (VCC = 4.1 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Min. Typ. Max.
Symbol Parameter Limits Unit
tWH(SCLK)
tWL(SCLK)
td(SCLK–SDATA)
tv(SCLK–SDATA)
tr(SCLK)
tf(SCLK)
tr(CMOS)
tf(CMOS)
tr(D+), tr(D-)
tf(D+), tf(D-)
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
Serial I/O2 output valid time
Serial I/O2 clock output rising time
Serial I/O2 clock output falling time
CMOS output rising time (Note)
CMOS output falling time (Note)
USB output rising time, CL = 200 to 450 pF, Ta = 0 to 70 °C, VCC =
4.4 to 5.25 V
USB output falling time, CL = 200 to 450 pF, Ta = 0 to 70 °C, VCC =
4.4 to 5.25 V
10
10
150
150
75
75
Notes: XOUT pin is excluded.
Fig. 49 Output switching characteristics measurement circuit
100 pF
Measured
output pin
CMOS output
tC(SCLK)/2–30
tC(SCLK)/2–30
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
140
30
30
30
30
300
300
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7534 Group
MITSUBISHI MICROCOMPUTERS
45
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 50 Timing chart
0.2V
CC
t
d
(S
CLK
-S
DATA
)
t
f
0.2V
CC
0.8V
CC
0.8V
CC
t
r
t
su
(S
DATA
-S
CLK
)t
h
(S
CLK
-S
DATA
)
t
v
(S
CLK
-S
DATA
)
t
C
(S
CLK
)
t
WL
(S
CLK
) t
WH
(S
CLK
)
S
DATA
(at receive)
S
CLK
0.2V
CC
t
WL
(X
IN
)
0.8V
CC
t
WH
(X
IN
)t
C
(X
IN
)
X
IN
0.2V
CC
0.8V
CC
t
W
(RESET)
RESET
0.2V
CC
t
WL
(CNTR)
0.8V
CC
t
WH
(CNTR)
t
C
(CNTR)
0.2V
CC
t
WL
(INT)
0.8V
CC
t
WH
(INT)
S
DATA
(at transmit)
INT
0
/INT
1
CNTR
0
0.1V0H
D+, D-
t
f
0.9V0H
t
r
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7534 Group
MITSUBISHI MICROCOMPUTERS
46
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Differences among 32-pin, 36-pin and 42-pin
The 7534 Group has three package types, and each of the number
of I/O ports are different. Accordingly, when the pins which have the
function except a port function are eliminated, be careful that the
functions are also eliminated.
Table 15 Differences among 32-pin, 36-pin and 42-pin
I/O port
Port P1
Port P2
Port P3
Port P4
42-pin SDIP
P10–P16 (7-bit structure)
P20–P27 (8-bit structure)
(A-D converter 8-channel)
P30–P37 (8-bit structure)
(INT0, INT1 available)
P40, P41 (2-bit structure)
36-pin SSOP
P10–P14 (5-bit structure)
P20–P27 (8-bit structure)
(A-D converter 8-channel)
P30–P35, P37 (7-bit structure)
(INT0 available)
No port
32-pin LQFP
P10–P14 (5-bit structure)
P20–P25 (6-bit structure)
(A-D converter 6-channel)
P30–P34 (5-bit structure)
(INT function not available)
No port
Description of improved USB function for 7534
Group
Table 14 Description of improved USB function for 7534 Group
No.
1
2
3
4
5
Parameter
Response at Control transfer
D+/D- transceiver circuit
Power dissipation at Suspend
STALL in Status stage
6-bit decode of SYNC field
7532 Group
Not deal with the host which performs the Control
transfer in parallel to plural device.
USB function can be used only at the condition of
CL = 150 pF to 350 pF.
Rating is Max. 300 µA not including the output cur-
rent of USBVREFOUT.
ACK is returned once to OUT (DATA0) to be valid
in Status stage.
SYNC is detected only when 8-bit full code (8016)
is complete.
7534 Group
Connectable to the host which performs the Con-
trol transfer in parallel to plural device.
Deal with the the following USB Spefification Rev.
1.1.
CL = 200 pF to 450 pF,
Trise and Tfall: 75 ns to 300 ns,
Tr/Tf: 80 % to 125 %,
Cross over Voltage: 1.3 V to 2.0 V.
Rating is Max. 300 µA including the output current
of USBVREFOUT, by low-power dissipation of D+/
D- input circuit and 3.3 V-regulator.
STALL is set automaticcally by hardware when
OUT (DATA0) is received in Status stage.
SYNC is detected only the low-order 6 bits even if
the high-order 2 bits are corrupted.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7534 Group
MITSUBISHI MICROCOMPUTERS
47
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Table 16 Differences among 32-pin, 36-pin and 42-pin (SFR)
42-pin SDIP
Bit 7 not available
All bits available
All bits available
Bits 2 to 7 not available
Bit 6 definition:
“P35, P36 pull-up control”
Bit 7 definition:
“P37 pull-up control”
Bit 0 definition:
“P37/INT0 input level selection”
Bit 1 definition:
“P36/INT1 input level selection”
Bits 0 to 2
“Input pins selected by setting these
bits to 000 to 111”
Bit 0 definition
“INT0 interrupt edge selection”
Bit 1 definition
“INT1 interrupt edge selection”
Bit 4 definition
“Serial I/O1, INT1 interrupt selection”
Bit 1 definition
“UART transmission, USB (except IN),
INT1”
Bit 2 definition
“INT0”
Bit 1 definition
“UART transmission, USB (except IN),
INT1”
Bit 2 definition
“INT0”
36-pin SSOP
Bits 5 to 7 not available
All bits available
Bit 6 not available
All bits not available
Bit 6 definition:
“P35 pull-up control”
Bit 7 definition:
“P37 pull-up control”
Bit 0 definition:
“P37/INT0 input level selection”
Bit 1 not available
Bits 0 to 2
“Input pins selected by setting these
bits to 000 to 111”
Bit 0 definition
“INT0 interrupt edge selection”
Bits 1 and 4 not available
Bit 1 definition
“UART transmission, USB (except IN)”
Bit 2 definition
“INT0”
Bit 1 definition
“UART transmission, USB (except IN)”
Bit 2 definition
“INT0”
32-pin LQFP
Bits 5 to 7 not available
Bits 6 and 7 not available
Bits 5 to 7 not available
All bits not available
Bits 6 and 7 not available
Bits 0 and 1 not available
Bits 0 to 2
“Input pins selected by setting these
bits to 000 to 101”
Bits 0, 1 and 4 not available
Bit 1 definition
“UART transmission, USB (except IN)”
Bit 2 not available
Bit 1 definition
“UART transmission, USB (except IN)”
Bit 2 not available
Additionally, there are differences of SFR usage and functional defi-
nitions.
Register (Address)
Port P1/Direction
(0216/0316)
Port P2/Direction
(0416/0516)
Port P3/Direction
(0616/0716)
Port P4/Direction
(0816/0916)
Pull-up control
(1616)
Port P1P3 control
(1716)
A-DControl
(3416)
Interrupt edge
selection
(3A16)
Interrupt request
(3C16)
Interrupt control
(3E16)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7534 Group
MITSUBISHI MICROCOMPUTERS
48
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 51 Handling of VCC, USBVREFOUT pins of M37534M4-XXXFP, M37534E8FP
Description supplement for use of USB function stably
Outline 36P2R-A
10
1
2
3
4
6
7
8
9
11
12
14
15
16
5
13
17
18
36
35
34
33
31
30
26
25
24
23
22
21
20
19
32
27
29
28
P0
0
CNV
SS
X
OUT
X
IN
V
SS
P0
1
P0
2
P0
3
P0
4
P3
0
(LED
0
)
Vcc
V
REF
P0
5
P1
0
/R
X
D/D-
P2
6
/AN
6
P2
7
/AN
7
P1
1
/T
X
D/D+
P1
2
/S
CLK
P1
3
/S
DATA
P2
3
/AN
3
P2
2
/AN
2
P2
1
/AN
1
P2
0
/AN
0
P3
1
(LED
1
)
P3
7
/INT
0
P2
4
/AN
4
P2
5
/AN
5
P0
6
P0
7
USBV
REFOUT
RESET
M37534M4-XXXFP
M37534E8FP
P1
4
/CNTR
0
P3
5
(LED
5
)
P3
4
(LED
4
)
P3
3
(LED
3
)
P3
2
(LED
2
)
1.5kΩ
Reason of ➀ is to reduce the effect by switcing noise of microcomputer to the
analog circuit generating USBVREFOUT output. Use the bigger capacitor and
connect to device at the shortest distance.
Reason of ➁ is to prevent the instability of the USBVREFOUT output due to
external noise.
Connect a capacitor to a device as
close as possible. For the capacitor,
a ceramic capacitor or an electrolytic
capacitor of 0.22 µF is recommended.
➁
Connect a bypass capacitor to a device
as close as possible. For the capacitor,
a ceramic capacitor or an electrolytic
capacitor of 1.0 µF is recommended.
➀
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7534 Group
MITSUBISHI MICROCOMPUTERS
49
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 52 Handling of VCC, USBVREFOUT pins of M37534M4-XXXGP
Outline 32P6U-A
P0
7
P1
0
/R
X
D/D-
P1
1
/T
X
D/D+
P1
2
/S
CLK
P1
3
/S
DATA
P1
4
/CNTR
0
P2
0
/
AN
0
P2
1
/
AN
1
32
31
30
29
28
27
26
25
P3
4
(LED
4
)
P3
3
(LED
3
)
P3
2
(LED
2
)
P3
1
(LED
1
)
P3
0
(LED
0
)
V
SS
X
OUT
X
IN
9
10
11
12
13
14
15
16
2
8
7
6
5
3
1
4
V
CC
CNV
SS
RESET
P2
2
/AN
2
P0
5
20
17
18
19
21
24
P0
2
P0
4
P0
3
P0
6
23
22
P0
1
P0
0
USBV
REFOUT
M37534M4-XXXGP
P2
3
/AN
3
P2
4
/AN
4
P2
5
/AN
5
V
REF
1.5kΩ
Reason of ➀ is to reduce the effect by switcing noise of microcomputer to the
analog circuit generating USBVREFOUT output. Use the bigger capacitor and
connect to device at the shortest distance.
Reason of ➁ is to prevent the instability of the USBVREFOUT output due to
external noise.
➁
➀
Connect a capacitor to a device as
close as possible. For the capacitor,
a ceramic capacitor or an electrolytic
capacitor of 0.22 µF is recommended.
Connect a bypass capacitor to a device
as close as possible. For the capacitor,
a ceramic capacitor or an electrolytic
capacitor of 1.0 µF is recommended.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7534 Group
MITSUBISHI MICROCOMPUTERS
50
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 53 Handling of VCC, USBVREFOUT pins of M37534E8SP, M37534M4-XXXSP, M37534RSS
Outline 42P4B
10
1
2
3
4
6
7
8
9
11
12
14
15
16
5
13
17
18
36
35
34
33
31
30
26
25
24
23
22
32
27
29
28
19
20
21
42
41
40
39
37
38
P0
0
CNV
SS
X
OUT
X
IN
V
SS
P0
1
P0
2
P0
3
P0
4
P3
0
(LED
0
)
Vcc
V
REF
P0
5
P1
2
/S
CLK
P2
5
/AN
5
P2
6
/AN
6
P1
3
/S
DATA
P1
4
/CNTR
0
P2
2
/AN
2
NC
P2
1
/AN
1
P2
0
/AN
0
P3
1
(LED
1
)
P2
3
/AN
3
P2
4
/AN
4
P0
6
P0
7
P3
7
/INT
0
RESET
M37534E8SP
M37534M4-XXXSP
M37534RSS
P3
5
(LED
5
)
P3
4
(LED
4
)
P3
3
(LED
3
)
P3
2
(LED
2
)
USBV
REFOUT
P1
0
/R
X
D/D-
P1
1
/T
X
D/D+
P2
7
/AN
7
1.5kΩ
Reason of ➀ is to reduce the effect by switcing noise of microcomputer to the
analog circuit generating USBVREFOUT output. Use the bigger capacitor and
connect to device at the shortest distance.
Reason of ➁ is to prevent the instability of the USBVREFOUT output due to
external noise.
➁
➀
P1
6
P1
5
P4
0
P4
1
P3
6
(LED
6
)/INT
1
Connect a capacitor to a device as
close as possible. For the capacitor,
a ceramic capacitor or an electrolytic
capacitor of 0.22 µF is recommended.
Connect a bypass capacitor to a device
as close as possible. For the capacitor,
a ceramic capacitor or an electrolytic
capacitor of 1.0 µF is recommended.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7534 Group
MITSUBISHI MICROCOMPUTERS
51
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
PACKAGE OUTLINE
SSOP36-P-450-0.80 Weight(g)
–
JEDEC Code 0.53
EIAJ Package Code Lead Material
Alloy 42
36P2R-A
Plastic 36pin 450mil SSOP
Symbol Min Nom Max
A
A
2
b
c
D
E
L
L
1
y
Dimension in Millimeters
H
E
A
1
I
2
–
–
.350
.050
.130.814.28–
.6311.30–
–
–
.271
–
–
.02.40.150.015.48.80.9311.50.7651–
.4311–
–
.42
–
.50.20.215.68–
.2312.70–
.150
–
b
2
–.50–
–
0°–10°
e
e
1
36 19
18
1
H
E
E
D
b
ey
F
A
A
2
A
1
L
1
L
c
eb
2
e
1
I
2
Recommended Mount Pad
Detail F
© 2000 MITSUBISHI ELECTRIC CORP.
KI-0001 Printed in Japan (ROD) II
New publication, effective Jan. 2000.
Specifications subject to change without notice.
Notes regarding these materials
• These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property
rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
• Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples
contained in these materials.
• All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by
Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product
distributor for the latest product information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.
Please also pay attention to information published by Mitsubishi Electric Corporation by various means, including the Mitsubishi Semiconductor home page (http://www.mitsubishichips.com).
• When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision
on the applicability of the information and products. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein.
• Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric
Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical,
aerospace, nuclear, or undersea repeater use.
• The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials.
• If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved
destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
• Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
Keep safety first in your circuit designs!
• Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to
personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable
material or (iii) prevention against any malfunction or mishap.
HEAD OFFICE: 2-2-3, MARUNOUCHI, CHIYODA-KU, TOKYO 100-8310, JAPAN
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7534 Group
MITSUBISHI MICROCOMPUTERS
SDIP42-P-600-1.78 Weight(g)
–
JEDEC Code 4.1
EIAJ Package Code Lead Material
Alloy 42/Cu Alloy
42P4B
Plastic 42pin 600mil SDIP
Symbol Min Nom Max
A
A
2
b
b
1
b
2
c
E
D
L
Dimension in Millimeters
A
1
0.51 – –
–3.8–
0.35 0.45 0.55
0.9 1.0 1.3
0.63 0.73 1.03
0.22 0.27 0.34
36.5 36.7 36.9
12.85 13.0 13.15
– 1.778 –
– 15.24 –
3.0 – –
0°–15°
– – 5.5
e
e
1
42 22
21
1
E
c
e
1
A
2
A
1
b
b
1
b
2
e
LA
SEATING PLANE
D
Rev. Rev.
No. date
1.0 First Edition 000118
1.1 Page 2: package type revised; 32P6B-A → 32P6U-A 000614
Page 5: package type revised; 32P6B-A → 32P6U-A
Page 8 package type revised; 32P6B-A → 32P6U-A
Page 34: Description revised; RESET “L” pulse width 2 µs → 15 µs
Page 43: Table 11 revised; Absolute accuracy (excluding quantization error) → Linearity error
Page 44: Table 12 revised; tw(RESET): 2 → 15
Page 48: Fig. 51 Description ➀, ➁ revised
Page 49: Fig. 52 Description ➀, ➁ and package type revised; 32P6B-A → 32P6U-A
Page 50: Fig. 53 Description ➀, ➁ revised
Page 51: Package outline revised; 32P6B-A → 32P6U-A
REVISION DESCRIPTION LIST 7534 Group DATA SHEET
(1/2)
Revision Description
