 
  
FEATURES APPLICATIONS
DESCRIPTION
CDAC
_
+
Output
Latches
and
3-State
Drivers
BYTE
16-/8-Bit
ParallelDA TA
OutputBus
SAR
Conversion
and
ControlLogic
Comparator
Clock
+IN
−IN
REFIN CONVST
BUSY
CS
RD
4.096-V
Internal
Reference
REFOUT
BUS18/16
ADS8482
SLAS386A – JULY 2005 – REVISED JUNE 2006
18-BIT, 1-MSPS, PSEUDO-BIPOLAR, FULLY DIFFERENTIAL INPUT, MICROPOWERSAMPLING ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE,REFERENCE
•Medical Instruments•0 to 1-MHz Sample Rate
•Optical Networking• ± 1.2 LSB Typ, ±2.5 LSB Max INL
•Transducer Interface•+0.75/-0.6 LSB Typ, +1.5/-1 LSB Max DNL
•High Accuracy Data Acquisition Systems•18-Bit NMC Ensured Over Temperature
•Magnetometers• ± 0.05-mV Offset Error• ± 0.05-PPM/ °C Offset Error Drift• ± 0.035 %FSR Gain Error
The ADS8482 is an 18-bit, 1-MSPS A/C converter• ± 0.5-PPM/ °C Gain Error Drift
with an internal 4.096-V reference and a•99dB SNR, -121dB THD, 123dB SFDR
pseudo-bipolar, fully differential input. The deviceincludes a 18-bit capacitor-based SAR A/D converter•Zero Latency
with inherent sample and hold. The ADS8482 offers•Low Power: 225 mW at 1 MSPS
a full 18-bit interface, a 16-bit option where data is•Unipolar Differential Input Range: V
ref
to –Vref
read using two read cycles, or an 8-bit bus optionusing three read cycles.•Onboard Reference with 6 PPM/ °C Drift•Onboard Reference Buffer
The ADS8482 is available in a 48-lead 7x7 QFNpackage and is characterized over the industrial•High-Speed Parallel Interface
–40 °C to 85 °C temperature range.•Wide Digital Supply 2.7 V to 5.25 V•8-/16-/18-Bit Bus Transfer•48-Pin 7x7 QFN Package
HIGH SPEED SAR CONVERTER FAMILYTYPE/SPEED 500 kHz ~600 kHz 750 kHz 1 MHz 1.25 MHz 2 MHz 3 MHz 4MHz
ADS8383 ADS8381 ADS848118-Bit Pseudo-Diff
ADS8380 (s)
18-Bit Pseudo-Bipolar, Fully Diff ADS8382 (s) ADS8482
ADS8327 ADS8370 (s) ADS8371 ADS8471 ADS8401 ADS841116-Bit Pseudo-Diff
ADS8328 ADS8372 (s) ADS8405 ADS8410 (s)
ADS8472 ADS8402 ADS8412 ADS842216-Bit Pseudo-Bipolar, Fully Diff
ADS8406 ADS8413 (s)
14-Bit Pseudo-Diff ADS7890 (s) ADS7891
12-Bit Pseudo-Diff ADS7886 ADS7883 ADS7881
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2005–2006, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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ABSOLUTE MAXIMUM RATINGS
(1)
ADS8482
SLAS386A – JULY 2005 – REVISED JUNE 2006
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
(1)
MAXIMUM
MAXIMUMINTEGRAL NO MISSING CODES PACKAGE PACKAGE TEMPER-ATURE ORDERING TRANS-PORTMODEL DIFFERENTIALLINEARITY RESOLUTION (BIT) TYPE DESIGNATOR RANGE INFORMATION MEDIA QTY.LINEARITY (LSB)(LSB)
Tape and reelADS8482IRGZT
2507x7 48 PinADS8482I ±4 –1 to +1.5 18 RGZ –40 °C to 85 °CQFN
Tape and reelADS8482IRGZR
1000
Tape and reelADS8482IBRGZT
2507x7 48 PinADS8482IB ±2.5 –1 to +1.5 18 RGZ –40 °C to 85 °CQFN
Tape and reelADS8482IBRGZR
1000
(1) For the most current specifications and package information, refer to our website at www.ti.com .
over operating free-air temperature range (unless otherwise noted)
VALUE UNIT
+IN to AGND –0.4 to +VA + 0.1 V–IN to AGND –0.4 to +VA + 0.1 VVoltage +VA to AGND –0.3 to 7 V+VBD to BDGND –0.3 to 7 V+VA to +VBD –0.3 to 2.55 VDigital input voltage to BDGND –0.3 to +VBD + 0.3 VDigital output voltage to BDGND –0.3 to +VBD + 0.3 VT
A
Operating free-air temperature range –40 to 85 °CT
stg
Storage temperature range –65 to 150 °CJunction temperature (T
J
max) 150 °CPower dissipation (T
J
Max – T
A
)/ θ
JAQFN package
θ
JA
thermal impedance 22 °C/WVapor phase (60 sec) 215 °CLead temperature, soldering
Infrared (15 sec) 220 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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SPECIFICATIONS
ADS8482
SLAS386A – JULY 2005 – REVISED JUNE 2006
T
A
= –40 °C to 85 °C, +VA = 5 V, +VBD = 3 V or 5 V, V
ref
= 4.096 V, f
SAMPLE
= 1 MSPS (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUT
Full-scale input voltage
(1)
+IN – (–IN) –V
ref
V
ref
V
+IN –0.2 V
ref
+ 0.2Absolute input voltage V–IN –0.2 V
ref
+ 0.2
Common-mode input range (V
ref
)/2 – 0.2 (V
ref
)/2 (V
ref
)/2 + 0.2 V
Input capacitance 65 pF
Input leakage current 1 nA
SYSTEM PERFORMANCE
Resolution 18 Bits
ADS8482I 18No missing codes BitsADS8482IB 18
ADS8482I –4 ±1.2 4
LSBIntegral linearity
(2)
(18 bit)
(3)ADS8482IB –2.5 ±1.2 2.5
ADS8482I –1 –0.6/0.75 1.5
LSBDifferential linearity
(18 bit)ADS8482IB –1 –0.6/0.75 1.5
ADS8482I –0.5 ±0.05 0.5Offset error
(4)
mVADS8482IB –0.5 ±0.05 0.5
ADS8482I ±0.05Offset error temperature drift ppm/ °CADS8482IB ±0.05
ADS8482I V
ref
= 4.096 V –0.1 ±0.035 0.1 %FSGain error
(4) (5)
ADS8482IB V
ref
= 4.096 V –0.1 ±0.035 0.1 %FS
ADS8482I ±0.5Gain error temperature drift ppm/ °CADS8482IB ±0.5
At dc ( ±0.2 V around V
ref
/2) 60Common-mode rejection ratio dB+IN – (–IN) = 1 Vpp at 1 MHz 55
Noise 25 µV RMS
Power supply rejection ratio At 1FFFFh output code 60 dB
SAMPLING DYNAMICS
Conversion time 625 650 ns
Acquisition time 320 350 ns
Throughput rate 1 MHz
Aperture delay 4 ns
Aperture jitter 5 ps
Step response 150 ns
Over voltage recovery 150 ns
(1) Ideal input span, does not include gain or offset error.(2) This is endpoint INL, not best fit.(3) LSB means least significant bit(4) Measured relative to an ideal full-scale input [+IN – (–IN)] of 8.192 V(5) This specification does not include the internal reference voltage error and drift.
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SPECIFICATIONS (Continued)
ADS8482
SLAS386A – JULY 2005 – REVISED JUNE 2006
T
A
= –40 °C to 85 °C, +VA = 5 V, +VBD = 3 V or 5 V, V
ref
= 4.096 V, f
SAMPLE
= 1 MSPS (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DYNAMIC CHARACTERISTICS
ADS8482I –120V
IN
= 8 V
pp
at 2 kHzADS8482IB –121
ADS8482I –105Total harmonic distortion (THD)
(1)
V
IN
= 8 V
pp
at 20 kHz dBADS8482IB –110
ADS8482I –100V
IN
= 8 V
pp
at 100 kHzADS8482IB –103
ADS8482I 96 98.6V
IN
= 8 V
pp
at 2 kHzADS8482IB 97.5 99
ADS8482I 98Signal to noise ratio (SNR)
(1)
V
IN
= 8 V
pp
at 20 kHz dBADS8482IB 98.5
ADS8482I 95V
IN
= 8 V
pp
at 100 kHzADS8482IB 97
ADS8482I 96 98.5V
IN
= 8 V
pp
at 2 kHzADS8482IB 97.5 99
ADS8482I 97Signal to noise + distortion (SINAD)
(1)
V
IN
= 8 V
pp
at 20 kHz dBADS8482IB 98
ADS8482I 93V
IN
= 8 V
pp
at 100 kHzADS8482IB 95
ADS8482I 120V
IN
= 8 V
pp
at 2 kHzADS8482IB 123
ADS8482I 107Spurious free dynamic range (SFDR)
(1)
V
IN
= 8 V
pp
at 20 kHz dBADS8482IB 113
ADS8482I 102V
IN
= 8 V
pp
at 100 kHzADS8482IB 105
–3dB Small signal bandwidth 15 MHz
(1) Calculated on the first nine harmonics of the input frequency.
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SPECIFICATIONS (Continued)
ADS8482
SLAS386A – JULY 2005 – REVISED JUNE 2006
T
A
= –40 °C to 85 °C, +VA = 5 V, +VBD = 3 V or 5 V, V
ref
= 4.096 V, f
SAMPLE
= 1 MSPS (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOLTAGE REFERENCE INPUT
Reference voltage at REFIN, V
ref
3.0 4.096 +VA – 0.8 V
Reference resistance
(1)
500 k Ω
Reference current drain f
s
= 1 MHz 1 mA
INTERNAL REFERENCE OUTPUT
Internal reference start-up time From 95% (+VA), with 1- µF storage capacitor 120 ms
Reference voltage range, V
ref
I
O
= 0 4.081 4.096 4.111 V
Source current Static load 10 µA
Line regulation +VA = 4.75 V ~ 5.25 V 60 µV
Drift I
O
= 0 ±6 PPM/ °C
DIGITAL INPUT/OUTPUT
Logic family –CMOS
V
IH
I
IH
= 5 µA +VBD – 1 +VBD + 0.3
V
IL
I
IL
= 5 µA –0.3 0.8Logic level VV
OH
I
OH
= 2 TTL loads +VBD – 0.6
V
OL
I
OL
= 2 TTL loads
Data format – Straight Binary
POWER SUPPLY REQUIREMENTS
+VBD 2.7 3.3 5.25 VPower supplyvoltage
+VA 4.75 5 5.25 V
Supply current
(2)
f
s
= 1 MHz 45 50 mA
Power dissipation
(2)
f
s
= 1 MHz 225 250 mW
TEMPERATURE RANGE
Operating free-air –40 85 °C
(1) Can vary ±20%(2) This includes only +VA current. +VBD current is typical 1 mA with 5 pF load capacitance on all output pins.
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TIMING CHARACTERISTICS
ADS8482
SLAS386A – JULY 2005 – REVISED JUNE 2006
All specifications typical at –40 °C to 85 °C, +VA =+VBD = 5 V
(1) (2) (3)
PARAMETER MIN TYP MAX UNIT
t
(CONV)
Conversion time 650 nst
(ACQ)
Acquisition time 320 nst
(HOLD)
Sample capacitor hold time 25 nst
pd1
CONVST low to BUSY high 40 nst
pd2
Propagation delay time, end of conversion to BUSY low 15 nst
pd3
Propagation delay time, start of convert state to rising edge of BUSY 15 nst
w1
Pulse duration, CONVST low 40 nst
su1
Setup time, CS low to CONVST low 20 nst
w2
Pulse duration, CONVST high 20 nsCONVST falling edge jitter 10 pst
w3
Pulse duration, BUSY signal low t
(ACQ)
min nst
w4
Pulse duration, BUSY signal high 650 nst
h1
Hold time, first data bus transition ( RD low, or CS low for read cycle, or BYTE or
40 nsBUS18/ 16 input changes) after CONVST lowt
d1
Delay time, CS low to RD low 0 nst
su2
Setup time, RD high to CS high 0 nst
w5
Pulse duration, RD low 50 nst
en
Enable time, RD low (or CS low for read cycle) to data valid 20 nst
d2
Delay time, data hold from RD high 5 nst
d3
Delay time, BUS18/ 16 or BYTE rising edge or falling edge to data valid 10 20 nst
w6
Pulse duration, RD high 20 nst
w7
Pulse duration, CS high 20 nst
h2
Hold time, last RD (or CS for read cycle ) rising edge to CONVST falling edge 50 nst
pd4
Propagation delay time, BUSY falling edge to next RD (or CS for read cycle) falling
0 nsedget
d4
Delay time, BYTE edge to BUS18/ 16 edge skew 0 nst
su3
Setup time, BYTE or BUS18/ 16 transition to RD falling edge 10 nst
h3
Hold time, BYTE or BUS18/ 16 transition to RD falling edge 10 nst
dis
Disable time, RD high ( CS high for read cycle) to 3-stated data bus 20 nst
d5
Delay time, BUSY low to MSB data valid delay 0 nst
d6
Delay time, CS rising edge to BUSY falling edge 50 nst
d7
Delay time, BUSY falling edge to CS rising edge 50 nst
su5
BYTE transition setup time, from BYTE transition to next BYTE transition, or BUS18/ 16
50 nstransition setup time, from BUS18/ 16 to next BUS18/ 16.t
su(ABORT)
Setup time from the falling edge of CONVST (used to start the valid conversion) to thenext falling edge of CONVST (when CS = 0 and CONVST are used to abort) or to the 60 550 nsnext falling edge of CS (when CS is used to abort).
(1) All input signals are specified with t
r
= t
f
= 5 ns (10% to 90% of +VBD) and timed from a voltage level of (V
IL
+ V
IH
)/2.(2) See timing diagrams.(3) All timing are measured with 20 pF equivalent loads on all data bits and BUSY pins.
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TIMING CHARACTERISTICS
ADS8482
SLAS386A – JULY 2005 – REVISED JUNE 2006
All specifications typical at –40 °C to 85 °C, +VA = 5 V +VBD = 3 V
(1) (2) (3)
PARAMETER MIN TYP MAX UNIT
t
(CONV)
Conversion time 650 nst
(ACQ)
Acquisition time 310 nst
(HOLD)
Sample capacitor hold time 25 nst
pd1
CONVST low to BUSY high 40 nst
pd2
Propagation delay time, end of conversion to BUSY low 25 nst
pd3
Propagation delay time, start of convert state to rising edge of BUSY 25 nst
w1
Pulse duration, CONVST low 40 nst
su1
Setup time, CS low to CONVST low 20 nst
w2
Pulse duration, CONVST high 20 nsCONVST falling edge jitter 10 pst
w3
Pulse duration, BUSY signal low t
(ACQ)
min nst
w4
Pulse duration, BUSY signal high 650 nst
h1
Hold time, first data bus transition ( RD low, or CS low for read cycle, or BYTE or
40 nsBUS18/ 16 input changes) after CONVST lowt
d1
Delay time, CS low to RD low 0 nst
su2
Setup time, RD high to CS high 0 nst
w5
Pulse duration, RD low 50 nst
en
Enable time, RD low (or CS low for read cycle) to data valid 30 nst
d2
Delay time, data hold from RD high 5 nst
d3
Delay time, BUS18/ 16 or BYTE rising edge or falling edge to data valid 10 30 nst
w6
Pulse duration, RD high 20 nst
w7
Pulse duration, CS high 20 nst
h2
Hold time, last RD (or CS for read cycle ) rising edge to CONVST falling edge 50 nst
pd4
Propagation delay time, BUSY falling edge to next RD (or CS for read cycle) falling
0 nsedget
d4
Delay time, BYTE edge to BUS18/ 16 edge skew 0 nst
su3
Setup time, BYTE or BUS18/ 16 transition to RD falling edge 10 nst
h3
Hold time, BYTE or BUS18/ 16 transition to RD falling edge 10 nst
dis
Disable time, RD high ( CS high for read cycle) to 3-stated data bus 30 nst
d5
Delay time, BUSY low to MSB data valid delay 0 nst
d6
Delay time, CS rising edge to BUSY falling edge 50 nst
d7
Delay time, BUSY falling edge to CS rising edge 50 nst
su5
BYTE transition setup time, from BYTE transition to next BYTE transition, or BUS18/ 16
50 nstransition setup time, from BUS18/ 16 to next BUS18/ 16.t
su(ABORT)
Setup time from the falling edge of CONVST (used to start the valid conversion) to thenext falling edge of CONVST (when CS = 0 and CONVST are used to abort) or to the 70 550 nsnext falling edge of CS (when CS is used to abort).
(1) All input signals are specified with t
r
= t
f
= 5 ns (10% to 90% of +VBD) and timed from a voltage level of (V
IL
+ V
IH
)/2.(2) See timing diagrams.(3) All timing are measured with 20 pF equivalent loads on all data bits and BUSY pins.
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PIN ASSIGNMENTS
+VBD
BUS18/16
BYTE
CONVST
RD
CS
+VA
AGND
AGND
+VA
REFM
REFM
RGZ PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
48 47 46 45 44 43 42 41 40 39 38 37
13 14 15 16 17 18 19 20 21 22 23 24
REFIN
REFOUT
NC
+VA
AGND
+IN
−IN
+VA
+VA
AGND
AGND
AGND
+VBD
DB10
DB11
DB12
DB13
DB14
DB15
DB16
DB17
AGND
AGND
+VA
BUSY
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB9
BDGND
NC − No internal connection
NOTE: The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
DB8
ADS8482
SLAS386A – JULY 2005 – REVISED JUNE 2006
TERMINAL FUNCTIONSNAME NO I/O DESCRIPTION
8, 9, 17, 20,AGND 23, 24, 26, – Analog ground27
BDGND 37 – Digital ground for bus interface digital supply
BUSY 48 O Status output. High when a conversion is in progress.
Bus size select input. Used for selecting 18-bit or 16-bit wide bus transfer.0: Data bits output on the 18-bit data bus pins DB[17:0].BUS18/ 16 2 I 1: Last two data bits D[1:0] from 18-bit wide bus output on:a) the low byte pins DB[9:2] if BYTE = 0b) the high byte pins DB[17:10] if BYTE = 1
Byte select input. Used for 8-bit bus reading.BYTE 3 I 0: No fold back1: Low byte D[9:2] of the 16 most significant bits is folded back to high byte of the 16 most significant pins DB[17:10].
CONVST 4 I Convert start. The falling edge of this input ends the acquisition period and starts the hold period.
CS 6 I Chip select. The falling edge of this input starts the acquisition period.
8-BIT BUS 16-BIT BUS 18-BIT BUS
Data Bus BYTE = 0 BYTE = 1 BYTE = 1 BYTE = 0 BYTE = 0 BYTE = 0
BUS18/ 16 = 0 BUS18/ 16 = 0 BUS18/ 16 = 1 BUS18/ 16 = 0 BUS18/ 16 = 1 BUS18/ 16 = 0
DB17 28 O D17 (MSB) D9 All ones D17 (MSB) All ones D17 (MSB)
DB16 29 O D16 D8 All ones D16 All ones D16
DB15 30 O D15 D7 All ones D15 All ones D15
DB14 31 O D14 D6 All ones D14 All ones D14
DB13 32 O D13 D5 All ones D13 All ones D13
DB12 33 O D12 D4 All ones D12 All ones D12
DB11 34 O D11 D3 D1 D11 All ones D11
DB10 35 O D10 D2 D0 (LSB) D10 All ones D10
DB9 38 O D9 All ones All ones D9 All ones D9
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TYPICAL CHARACTERISTICS
4.09713
4.09714
4.09715
4.09716
4.09717
4.09718
4.09719
4.0972
4.75 4.85 4.95 5.05 5.15 5.25
SupplyVoltage-V
ReferenceVoltage-V
T =25°C
A
0 6 196
1474
3615
2383
481
36 1 0
0
500
1000
1500
2000
2500
3000
3500
4000
-4 -3 -2 -1 0 1 2 3 4 5
OutputCode
Frequency
+VA =5V,
+VBD=5V,
T =25C,
f =1MSPS,
V =4.096V,
Input=Midscale
A
i
ref
4.095
4.0955
4.096
4.0965
4.097
4.0975
4.098
-40 -25 -10 5 20 35 50 65 80
T -Free-AirTemperature-°C
A
ReferenceVoltage-V
+VA =5V,
+VBD=5V
ADS8482
SLAS386A – JULY 2005 – REVISED JUNE 2006
TERMINAL FUNCTIONS (continued)NAME NO I/O DESCRIPTION
DB8 39 O D8 All ones All ones D8 All ones D8
DB7 40 O D7 All ones All ones D7 All ones D7
DB6 41 O D6 All ones All ones D6 All ones D6
DB5 42 O D5 All ones All ones D5 All ones D5
DB4 43 O D4 All ones All ones D4 All ones D4
DB3 44 O D3 All ones All ones D3 D1 D3
DB2 45 O D2 All ones All ones D2 D0 (LSB) D2
DB1 46 O D1 All ones All ones D1 All ones D1
DB0 47 O D0 (LSB) All ones All ones D0 (LSB) All ones D0 (LSB)
–IN 19 I Inverting input channel
+IN 18 I Noninverting input channel
NC 15 No connection
REFIN 13 I Reference input
REFOUT 14 O Reference output. Add 1- µF capacitor between the REFOUT pin and REFM pin when internal reference is used.
REFM 11, 12 I Reference ground
Synchronization pulse for the parallel output. When CS is low, this serves as output enable and puts the previousRD 5 I
conversion results on the bus.
7, 10, 16,+VA – Analog power supplies, 5-V DC21, 22, 25
+VBD 1, 36 – Digital power supply for bus
INTERNAL REFERENCE VOLTAGE INTERNAL REFERENCE VOLTAGEDC HISTOGRAM vs vs(8192 Conversion Outputs) FREE-AIR TEMPERATURE SUPPLY VOLTAGE
Figure 1. Figure 2. Figure 3.
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39
40
41
42
43
44
45
46
250 500 750 1000
SampleRate-KSPS
SupplyCurrent-mA
+VA =5V,
+VBD=5V,
T =25°C,
V =4.096V
A
ref
44
44.4
44.8
45.2
45.6
46
-40 -25 -10 5 20 35 50 65 80
T -Free-AirTemperature-°C
A
SupplyCurrent-mA
+VA =5V,
+VBD=5V,
f =1MSPS,
V =4.096V
i
ref
-1
-0.50
0
0.50
1
1.50
4.75 4.95 5.15
SupplyVoltage-V
DNL -LSBs
Max
Min
+VA =5V,
+VBD=5V,
T =25°C,
f =1MSPS,
V =4.096V,
A
i
ref
-2.5
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
2.5
-40 -25 -10 5 20 35 50 65 80
T -Free-AirTemperature-°C
A
INL -LSBs
Min
Max
+VA =5V,
+VBD=5V,
f =1MSPS,
V =4.096V
i
ref
-1
-0.50
0
0.50
1
1.50
-40 -25 -10 5 20 35 50 65 80
T -Free-AirTemperature-°C
A
DNL -LSBs
+VA =5V,
+VBD=5V,
f =1MSPS,
V =4.096V
i
ref Max
Min
-2.50
-2
-1.50
-1
-0.50
0
0.50
1
1.50
2
2.50
3 3.2 3.4 3.6 3.8 4 4.2
ReferenceVoltage-V
INL -LSBs
Max
Min
V =5V,
T =25°C,
f =1MSPS
DD
A
i
-2.50
-2
-1.50
-1
-0.50
0
0.50
1
1.50
2
2.50
4.75 4.85 4.95 5.05 5.15 5.25
SupplyVoltage-V
INL -LSBs
Max
Min
+VA =5V,
+VBD=5V,
T =25°C,
f =1MSPS,
V =4.096V,
A
i
ref
-1
-0.50
0
0.50
1
1.50
3 3.2 3.4 3.6 3.8 44.2
ReferenceVoltage-V
DNL -LSBs
Max
Min
V =5V,
T =25°C,
f =1MSPS
DD
A
i
ADS8482
SLAS386A – JULY 2005 – REVISED JUNE 2006
TYPICAL CHARACTERISTICS (continued)
SUPPLY CURRENT SUPPLY CURRENT SUPPLY CURRENTvs vs vsFREE-AIR TEMPERATURE SUPPLY VOLTAGE SAMPLE RATE
Figure 4. Figure 5. Figure 6.
DIFFERENTIAL NONLINEARITY INTEGRAL NONLINEARITY DIFFERENTIAL NONLINEARITYvs vs vsFREE-AIR TEMPERATURE FREE-AIR TEMPERATURE SUPPLY VOLTAGE
Figure 7. Figure 8. Figure 9.
INTEGRAL NONLINEARITY DIFFERENTIAL NONLINEARITY INTEGRAL NONLINEARITYvs vs vsSUPPLY VOLTAGE REFERENCE VOLTAGE REFERENCE VOLTAGE
Figure 10. Figure 11. Figure 12.
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-0.1
-0.09
-0.08
-0.07
-0.06
-0.05
-0.04
-0.03
-0.01
0
4.75 4.85 4.95 5.05 5.15 5.25
SupplyVoltage-V
OffsetError-mV
-0.02
T =25°C,
f =1MSPS,
V =4.096V
A
i
ref
-0.1
-0.09
-0.08
-0.07
-0.06
-0.05
-0.04
-0.03
-0.02
-0.01
0
3 3.2 3.4 3.6 3.8 4 4.2
ReferenceVoltage-V
OffsetError-mV
V =5V,
T =25°C,
f =1MSPS
DD
A
i
-0.1
-0.09
-0.08
-0.07
-0.06
-0.05
-0.04
-0.03
-0.02
-0.01
0
-40 -25 -10 5 20 35 50 65 80
T -Free-AirTemperature-°C
A
OffsetError-mV
+VA =5V,
+VBD=5V,
f =1MSPS,
V =4.096V
i
ref
-0.08
-0.07
-0.06
-0.05
-0.04
-0.03
-0.02
-0.01
4.75 4.85 4.95 5.05 5.15 5.25
SupplyVoltage-V
GainError-%FS
T =25°C,
f =1MSPS,
V =4.096
A
i
ref
-0.07
-0.065
-0.06
-0.055
-0.05
-0.045
-0.04
-0.035
-0.03
-0.025
-0.02
-40 -25 -10 5 20 35 50 65 80
GainError-%FS
+VA =5V,
+VBD=5V,
f =1MSPS,
V =4.096V
i
ref
T -Free-AirTemperature-°C
A
-0.1
-0.08
-0.06
-0.04
-0.02
0
0.02
0.04
0.06
0.08
0.1
3 3.2 3.4 3.6 3.8 4 4.2
ReferenceVoltage-V
GainError-%FS
V =5V,
T =25°C,
f =1MSPS
DD
A
i
0
3
13
11
4
0
2
4
6
8
10
12
14
0.01 0.03 0.04 0.05 0.07 0.08
OffsetDrift-ppm/C
Frequency
4
+VA =5V,
+VBD=5V,
f =1MSPS,
V =4.096V
i
ref
1
9
8
7
4
6
0
1
2
3
4
5
6
7
8
9
10
0.03 0.19 0.35 0.50 0.66 0.90
GainErrorDrift-ppm/C
Frequency
+VA =5V,
+VBD=5V,
f =1MSPS,
V =4.096V
i
ref
ADS8482
SLAS386A – JULY 2005 – REVISED JUNE 2006
TYPICAL CHARACTERISTICS (continued)
OFFSET ERROR OFFSET ERROR OFFSET ERRORvs vs vsFREE-AIR TEMPERATURE SUPPLY VOLTAGE REFERENCE VOLTAGE
Figure 13. Figure 14. Figure 15.
GAIN ERROR GAIN ERROR GAIN ERRORvs vs vsSUPPLY VOLTAGE FREE-AIR TEMPERATURE REFERENCE VOLTAGE
Figure 16. Figure 17. Figure 18.
TOTAL HARMONIC DISTORTIONOFFSET ERROR TEMPERATURE GAIN ERROR TEMPERATURE vsDRIFT DISTRIBUTION (35 Samples) DRIFT DISTRIBUTION (35 Samples) REFERENCE VOLTAGE
Figure 19. Figure 20. Figure 21.
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96.5
97
97.5
98
98.5
99
99.5
3 3.2 3.4 3.6 3.8 4 4.2
V -ReferenceVoltage-V
ref
SINAD-Signal-to-noise+Distortion-dB
+VA =5V,
+VBD=5V,
f =1MSPS,
s
T =25°C,
f =2kHz
A
i
-122
-121
-120
-119
-118
-117
-116
-115
-40 -25 -10 5 20 35 50 65 80
T -Free-AirTemperature-°C
A
THD-TotalHarmonicDistortion-dB
+VA =5V,
+VBD=5V,
f =1MSPS,
s
V =4.096V,
f =2kHz
ref
i
98.1
98.2
98.3
98.4
98.5
98.6
98.7
98.8
98.9
-40 -25 -10 5 20 35 50 65 80
SNR-Signal-to-NoiseRatio-dB
T -Free-AirTemperature-°C
A
+VA =5V,
+VBD=5V,
f =1MSPS,
V =4.096V,
s
ref
f =2kHz
i
98.1
98.2
98.3
98.4
98.5
98.6
98.7
98.8
98.9
-40 -25 -10 5 20 35 50 65 80
SINAD-Signal-to-Noise+Distortion-dB
T -Free-AirTemperature-°C
A
+VA =5V,
+VBD=5V,
f =1MSPS,
V =4.096V,
s
ref
f =2kHz
i
118.5
119
119.5
120
120.5
121
121.5
122
122.5
123
123.5
-40 -25 -10 5 20 35 50 65 80
T -Free-AirTemperature-°C
A
SFDR-SpuriousFreeDynamicRange-dB
+VA =5V,
+VBD=5V,
f =1MSPS,
s
V =4.096V,
f =2kHz
ref
i
-1.5
-1
-0.5
0
0.5
1
1.5
-131072 -65536 0 65536 131072
OutputCode
DNL -LSBs
+VA =5V,+VBD=5V, T =25C,f =1MSPS,V =4.096V
A i ref
ADS8482
SLAS386A – JULY 2005 – REVISED JUNE 2006
TYPICAL CHARACTERISTICS (continued)
SIGNAL-TO-NOISE RATIO SIGNAL-TO-NOISE + DISTORTION TOTAL HARMONIC DISTORTIONvs vs vsREFERENCE VOLTAGE REFERENCE VOLTAGE FREE-AIR TEMPERATURE
Figure 22. Figure 23. Figure 24.
SPURIOUS FREE DYNAMIC RANGE SIGNAL-TO-NOISE RATIO SIGNAL-TO-NOISE + DISTORTIONvs vs vsFREE-AIR TEMPERATURE FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE
Figure 25. Figure 26. Figure 27.
DNL
Figure 28.
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-2.5
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
2.5
-131072 -65536 0 65536 131072
OutputCode
INL -LSBs
+VA =5V,+VBD=5V, T =25C,f =1MSPS,V =4.096V
A i ref
ADS8482
SLAS386A – JULY 2005 – REVISED JUNE 2006
TYPICAL CHARACTERISTICS (continued)
INL
Figure 29.
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TIMING DIAGRAMS
MSB
Hi−Z Hi−Z
tw1
CONVST
tpd1 tpd2
tw4
tsu1
BUSY
CS
CONVERT†
t(CONV)
SAMPLING†
(When CS Toggle)
BYTE
tw2
tw3
t(ACQ)
th1
tpd4
ten
BUS 18/16
RD
DB[17:12]
td1
tdis
th2
tsu2
t(CONV)
†Signal internal to device
DB[11:10]
DB[9:0] D[9:0]
D[11:10] D[3:2] D[1:0]
D[17:12] D[9:4]
Hi−Z
Hi−Z
Hi−Z
Hi−Z
td6
tsu5
tsu5
tsu(ABORT)
tsu(ABORT)
td7 tw7
tpd3
t(HOLD)
ADS8482
SLAS386A – JULY 2005 – REVISED JUNE 2006
Figure 30. Timing for Conversion and Acquisition Cycles With CS and RD Toggling
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DB[17:12] MSB
Hi−Z
Hi−Z
Hi−Z
CONVST
BUSY
CS
CONVERT†
SAMPLING†
(When CS Toggle)
BYTE
BUS 18/16
RD = 0
tw1
tpd1 tpd2
tw4
tw2
tw3
tsu1
t(CONV)
t(ACQ)
t(CONV)
th1
tpd4
ten
th2
tdis
†Signal internal to device
td6
tsu5
tdis
Hi−Z
Hi−Z
ten
Previous
Previous
Repeated
Repeated
D [9:0]
Hi−Z Previous Repeated
td7
tpd3
t(HOLD)
ten Hi−Z
Hi−Z
DB[11:10] D[11:10] D[3:2] D[1:0]
D[17:12] D[9:4]
Hi−Z
DB[9:0] D[9:0] D [9:0]
tw7
tsu(ABORT)
tsu(ABORT)
D[17:12]
D[17:12]
D[11:10] D[11:10]
ADS8482
SLAS386A – JULY 2005 – REVISED JUNE 2006
Figure 31. Timing for Conversion and Acquisition Cycles With CS Toggling, RD Tied to BDGND
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BYTE
BUS 18/16
RD
th1
tpd4 th2
ten tdis
†Signal internal to device
MSB
Hi−Z Hi−Z
DB[17:12]
DB[11:10]
DB[9:0] D[9:0]
D[11:10] D[3:2] D[1:0]
D[17:12] D[9:4]
Hi−Z
Hi−Z
Hi−Z
Hi−Z
tsu5
tsu5
CONVST
BUSY
CS = 0
CONVERT†
SAMPLING†
(When CS = 0)
tw1
tpd2
tpd1 tw4
tw2
tw3
t(CONV)
t(ACQ)
t(HOLD)
tsu(ABORT) tsu(ABORT)
t(CONV)
ADS8482
SLAS386A – JULY 2005 – REVISED JUNE 2006
Figure 32. Timing for Conversion and Acquisition Cycles With CS Tied to BDGND, RD Toggling
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th1
td5
th1
BYTE
BUS 18/16
RD = 0
DB[17:12] D[17:12] D[9:4]
Previous LSB
DB[11:10] D[11:10]
DB[9:0] D[9:0]
D[3:2]
Next D[17:12]
D[1:0] Next D[11:10]
Next D[9:0]
tsu5 tsu5
tsu5
tsu5
tw1 tw2
tpd1 tpd2
tw4
t(CONV)
tw3
t(CONV)
t(ACQ)
CONVST
BUSY
CS = 0
SAMPLING†
(When CS = 0)
CONVERT†
tpd3 tpd3
t(HOLD) t(HOLD)
†Signal internal to device
tsu(ABORT) tsu(ABORT)
ADS8482
SLAS386A – JULY 2005 – REVISED JUNE 2006
Figure 33. Timing for Conversion and Acquisition Cycles With CS and RD Tied to BDGND - Auto Read
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Valid Hi−Z
ten tdis
ten
td3
td3 tdis
ValidValid Hi−ZHi−Z
CS
RD
BYTE
BUS 18/16
DB[17:0]
tsu5
ADS8482
SLAS386A – JULY 2005 – REVISED JUNE 2006
Figure 34. Detailed Timing for Read Cycles
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APPLICATION INFORMATION
MICROCONTROLLER INTERFACING
ADS8482 to 8-Bit Microcontroller Interface
CS
BYTE
BUS18/16
RD
CONVST BDGND
+VBD
DB[17:10]
Micro
Controller
GPIO
RD
10 µF
0.1 µF
Analog 5 V
0.1 µF
Digital 3 V
Ext Ref Input
Analog Input
+VA
REFM
AGND
+IN
−IN
AD8482
0.1 µF
REFIN
BDGND
AGND
AD[7:0] Data Bus D[17:0]
GPIO
GPIO
GPIO
+VA
REFOUT
REFIN
REFM
AGND
0.1 µF
1 µF
0.1 µF
10 µF
Analog 5 V
ADS8482
AGND
AGND
ADS8482
SLAS386A – JULY 2005 – REVISED JUNE 2006
Figure 35 shows a parallel interface between the ADS8482 and a typical microcontroller using the 8-bit data bus.
The BUSY signal is used as a falling-edge interrupt to the microcontroller.
Figure 35. ADS8482 Application Circuitry
Figure 36. ADS8482 Using Internal Reference
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PRINCIPLES OF OPERATION
REFERENCE
ADS8482
REFIN
REFM
0.1 Fm
100 W
REF3240
_
+
830pF
ToCDAC
ToCDAC
10kW
300pF
REFIN
REFM
ADS8482
SLAS386A – JULY 2005 – REVISED JUNE 2006
The ADS8482 is a high-speed successive approximation register (SAR) analog-to-digital converter (ADC). Thearchitecture is based on charge redistribution which inherently includes a sample/hold function. See Figure 35for the application circuit for the ADS8482.
The conversion clock is generated internally. The conversion time of 650 ns is capable of sustaining a 1 MHzthroughput.
The analog input is provided to two input pins: +IN and –IN. When a conversion is initiated, the differential inputon these pins is sampled on the internal capacitor array. While a conversion is in progress, both inputs aredisconnected from any internal function.
The ADS8482 can operate with an external reference with a range from 3.0 V to 4.2 V. The reference voltage onthe input pin #13 (REFIN) of the converter is internally buffered. A clean, low noise, well-decoupled referencevoltage on this pin is required to ensure good performance of the converter. A low noise band-gap reference likethe REF3240 can be used to drive this pin. A 0.1- µF decoupling capacitor is required between REFIN andREFM pins (pin #13 and pin #12) of the converter. This capacitor should be placed as close as possible to thepins of the device. Designers should strive to minimize the routing length of the traces that connect the terminalsof the capacitor to the pins of the converter. An RC network can also be used to filter the reference voltage. A100- Ωseries resistor and a 0.1- µF capacitor, which can also serve as the decoupling capacitor can be used tofilter the reference voltage.
Figure 37. ADS8482 Using External Reference
The ADS8482 also has limited low pass filtering capability built into the converter. The equivalent circuitry on theREFIN input ia as shown in Figure 38 .
Figure 38. Simplified Reference Input Circuit
The REFM input of the ADS8482 should always be shorted to AGND. A 4.096-V internal reference is included.When internal reference is used, pin 14 (REFOUT) is connected to pin 13 (REFIN) with an 0.1- µF decouplingcapacitor and 1- µF storage capacitor between pin 14 (REFOUT) and pins 11 and 12 (REFM) (see Figure 36 ).The internal reference of the converter is double buffered. If an external reference is used, the second bufferprovides isolation between the external reference and the CDAC. This buffer is also used to recharge all of thecapacitors of the CDAC during conversion. Pin 14 (REFOUT) can be left unconnected (floating) if externalreference is used.
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ANALOG INPUT
ADS8482
SLAS386A – JULY 2005 – REVISED JUNE 2006
PRINCIPLES OF OPERATION (continued)
When the converter enters the hold mode, the voltage difference between the +IN and –IN inputs is captured onthe internal capacitor array. Both +IN and –IN input has a range of –0.2 V to Vref + 0.2 V. The input span [+IN –(–IN)] is limited to –V
ref
to V
ref
.
The input current on the analog inputs depends upon a number of factors: sample rate, input voltage, andsource impedance. Essentially, the current into the ADS8482 charges the internal capacitor array during thesample period. After this capacitance has been fully charged, there is no further input current. The source of theanalog input must be able to charge the input capacitance (65 pF) to an 18-bit settling level within the acquisitiontime (320 ns) of the device. When the converter goes into the hold mode, the input impedance is greater than 1GΩ.
Care must be taken regarding the absolute analog input voltage. To maintain the linearity of the converter, the+IN and –IN inputs and the span [+IN – (–IN)] must be within the limits specified. Outside of these ranges, theconverter's linearity may not meet specifications. To minimize noise, low bandwidth input signals with low-passfilters are used.
Care must be taken to ensure that the output impedance of the sources driving the +IN and –IN inputs arematched. If this is not observed, the two inputs could have different setting times. This may result in offset error,gain error, and linearity error which varies with temperature and input voltage.
The analog input to the converter needs to be driven with a low noise, high-speed op-amp like the THS4031. AnRC filter is recommended at the input pins to low-pass filter the noise from the source. The input to the converteris a uni-polar input voltage in the range 0 to V
ref
. The THS4031 can be used in the source follower configurationto drive the converter.
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+12V
-12V
THS4031
2200pF
(+)IN
+VIN
+12V
-12V
THS4031 (-)IN
+0Vto+4V
+2.048V
R
C
1 Fm
1 Fm
1 Fm
1 Fm
1 Fm
1 Fm
5W
75 W
300 W
300 W
5W
ADS8482
SLAS386A – JULY 2005 – REVISED JUNE 2006
PRINCIPLES OF OPERATION (continued)
Figure 39. Single-Ended Input, Differential Output Configuration
In systems, where the input is differential, the THS4031 can be used in the inverting configuration with anadditional DC bias applied to its + input so as to keep the input to the ADS8482 within its rated operating voltagerange. The DC bias can be derived from the REF3220 or the REF3240 reference voltage ICs. The inputconfiguration shown below is capable of delivering better than 97dB SNR and -103db THD at an input frequencyof 100 kHz. In case band-pass filters are used to filter the input, care should be taken to ensure that the signalswing at the input of the band-pass filter is small so as to keep the distortion introduced by the filter minimal. Insuch cases, the gain of the circuit shown below can be increased to keep the input to the ADS8482 large tokeep the SNR of the system high. Note that the gain of the system from the + input to the output of theTHS4031 in such a configuration is a function of the gain of the AC signal. A resistor divider can be used toscale the output of the REF3220 or REF3240 to reduce the voltage at the DC input to THS4031 to keep thevoltage at the input of the converter within its rated operating range.
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+12V
-12V
+2.048V
THS4031
2200pF
(+)IN
+VIN
+12V
-12V
THS4031 (-)IN
+2.048V
-VIN
AP Cascade
TwoSystem
AP Cascade TwoSystem
PatternGeneratorPlatform
f =1kHz
i
SNR:99dB
SINAD:99dB
THD:-121dB
SFDR:123dB
ENOB(SINAD):16.15
1 Fm
1 Fm1 Fm
1 Fm
1 Fm
1 Fm
12 W
300 W
300 W
300 W
12 W
300 W
DIGITAL INTERFACE
Timing and Control
ADS8482
SLAS386A – JULY 2005 – REVISED JUNE 2006
PRINCIPLES OF OPERATION (continued)
Figure 40. Differential Input, Differential Output Configuration
See the timing diagrams in the specifications section for detailed information on timing signals and theirrequirements.
The ADS8482 uses an internal oscillator generated clock which controls the conversion rate and in turn thethroughput of the converter. No external clock input is required.
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Reading Data
ADS8482
SLAS386A – JULY 2005 – REVISED JUNE 2006
PRINCIPLES OF OPERATION (continued)Conversions are initiated by bringing the CONVST pin low for a minimum of 20 ns (after the 20 ns minimumrequirement has been met, the CONVST pin can be brought high), while CS is low. The ADS8482 switches fromthe sample to the hold mode on the falling edge of the CONVST command. A clean and low jitter falling edge ofthis signal is important to the performance of the converter. The BUSY output is brought high immediatelyfollowing CONVST going low. BUSY stays high throughout the conversion process and returns low when theconversion has ended.
Sampling starts with the falling edge of the BUSY signal when CS is tied low or starts with the falling edge of CSwhen BUSY is low.
Both RD and CS can be high during and before a conversion with one exception ( CS must be low whenCONVST goes low to initiate a conversion). Both the RD and CS pins are brought low in order to enable theparallel output bus with the conversion.
The ADS8482 outputs full parallel data in straight binary format as shown in Table 1 . The parallel output isactive when CS and RD are both low. There is a minimal quiet zone requirement around the falling edge ofCONVST. This is 50 ns prior to the falling edge of CONVST and 40 ns after the falling edge. No data readshould attempted within this zone. Any other combination of CS and RD sets the parallel output to 3-state. BYTEand BUS18/ 16 are used for multiword read operations. BYTE is used whenever lower bits on the bus are outputon the higher byte of the bus. BUS18/ 16 is used whenever the last two bits on the 18-bit bus is output on eitherbytes of the higher 16-bit bus. Refer to Table 1 for ideal output codes.
Table 1. Ideal Input Voltages and Output Codes
DESCRIPTION ANALOG VALUE DIGITAL OUTPUT STRAIGHT BINARY
Full scale range +V
ref
Least significant bit (LSB) 2 ×(+V
ref
)/262144 BINARY CODE HEX CODE
+Full scale (+V
ref
) – 1 LSB 01 1111 1111 1111 1111 1FFFFMidscale 0 V 00 0000 0000 0000 0000 00000Midscale – 1 LSB 0 V – 1 LSB 11 1111 1111 1111 1111 3FFFFZero –V
ref
10 0000 0000 0000 0000 20000
The output data is a full 18-bit word (D17–D0) on DB17–DB0 pins (MSB–LSB) if both BUS18/ 16 and BYTE arelow.
The result may also be read on an 16-bit bus by using only pins DB17–DB2. In this case two reads arenecessary: the first as before, leaving both BUS18/ 16 and BYTE low and reading the 16 most significant bits(D17–D2) on pins DB17–DB2, then bringing BUS18/ 16 high while holding BYTE low. When BUS18/ 16 is high,the lower two bits (D1–D0) appear on pins DB3–DB2.
The result may also be read on an 8-bit bus for convenience. This is done by using only pins DB17–DB10. Inthis case three reads are necessary: the first as before, leaving both BUS18/ 16 and BYTE low and reading the 8most significant bits on pins DB17–DB10, then bringing BYTE high while holding BUS18/ 16 low. When BYTE ishigh, the medium bits (D9–D2) appear on pins DB17–DB10. The last read is done by bringing BUS18/ 16 highwhile holding BYTE high. When BUS18/ 16 is high, the lower two bits (D1–D0) appear on pins DB11–DB10. Thelast read cycle is not necessary if only the first 16 most significant bits are of interest.
All of these multiword read operations can be performed with multiple active RD (toggling) or with RD held lowfor simplicity. This is referred to as the AUTO READ operation.
Table 2. Conversion Data Read Out
DATA READ OUTBYTE BUS18/ 16
PINS PINS PINS PINS PINSDB17–DB12 DB11–DB10 DB9–DB4 DB3–DB2 DB1–DB0
High High All One's D1–D0 All One's All One's All One'sLow High All One's All One's All One's D1–D0 All One's
24
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RESET
LAYOUT
ADS8482
SLAS386A – JULY 2005 – REVISED JUNE 2006
Table 2. Conversion Data Read Out (continued)
DATA READ OUTBYTE BUS18/ 16
PINS PINS PINS PINS PINSDB17–DB12 DB11–DB10 DB9–DB4 DB3–DB2 DB1–DB0
High Low D9–D4 D3–D2 All One's All One's All One'sLow Low D17–D12 D11–D10 D9–D4 D3–D2 D1–D0
On power-up, internal POWER-ON RESET circuitry generates the reset required for the device. The first threeconversions after power-up are used to load factory trimming data for a specific device to assure high accuracyof the converter. The results of the first three conversions are invalid and should be discarded.
The device can also be reset through the use of the combination fo CS and CONVST. Since the BUSY signal isheld at high during the conversion, either one of these conditions triggers an internal self-clear reset to theconverter.
•Issue a CONVST when CS is low and the internal convert state is high. The falling edge of CONVST startsa reset.•Issue a CS (select the device) while the internal convert state is high. The falling edge of CS causes a reset.
Once the device is reset, all output latches are cleared (set to zeroes) and the BUSY signal is brought low. Anew sampling period is started at the falling edge of the BUSY signal immediately after the instant of the internalreset.
For optimum performance, care must be taken with the physical layout of the ADS8482 circuitry.
As the ADS8482 offers single-supply operation, it is often used in close proximity with digital logic,microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design andthe higher the switching speed, the more difficult it is to achieve good performance from the converter.
The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, groundconnections and digital inputs that occur just prior to latching the output of the analog comparator. Thus, drivingany single conversion for an n-bit SAR converter, there are at least n windows in which large external transientvoltages can affect the conversion result. Such glitches might originate from switching power supplies, nearbydigital logic, or high power devices.
The degree of error in the digital output depends on the reference voltage, layout, and the exact timing of theexternal event.
On average, the ADS8482 draws very little current from an external reference as the reference voltage isinternally buffered. If the reference voltage is external and originates from an op amp, make sure that it can drivethe bypass capacitor or capacitors without oscillation. A 0.1- µF capacitor is recommended from pin 13 (REFIN)directly to pin 12 (REFM). REFM and AGND must be shorted on the same ground plane under the device.
The AGND and BDGND pins should be connected to a clean ground point. In all cases, this should be theanalog ground. Avoid connections which are too close to the grounding point of a microcontroller or digital signalprocessor. If required, run a ground trace directly from the converter to the power supply entry point. The ideallayout consists of an analog ground plane dedicated to the converter and associated analog circuitry.
As with the AGND connections, +VA should be connected to a 5-V power supply plane or trace that is separatefrom the connection for digital logic until they are connected at the power entry point. Power to the ADS8482should be clean and well bypassed. A 0.1- µF ceramic bypass capacitor should be placed as close to the deviceas possible. See Table 3 for the placement of the capacitor. In addition, a 1- µF to 10- µF capacitor isrecommended. In some situations, additional bypassing may be required, such as a 100- µF electrolytic capacitoror even a Pi filter made up of inductors and capacitors-all designed to essentially low-pass filter the 5-V supply,removing the high frequency noise.
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ADS8482
SLAS386A – JULY 2005 – REVISED JUNE 2006
Table 3. Power Supply Decoupling Capacitor Placement
POWER SUPPLY PLANE
CONVERTERCONVERTER ANALOG SIDE
DIGITAL SIDESUPPLY PINS
Pin pairs that require shortest path to decoupling capacitors (7,8), (9,10), (16,17), (20,21), (22,23), (25,26) (36,37)Pins that require no decoupling 24, 26 1
26
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PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
ADS8482IBRGZR ACTIVE VQFN RGZ 48 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS8482IBRGZRG4 ACTIVE VQFN RGZ 48 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS8482IBRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS8482IBRGZTG4 ACTIVE VQFN RGZ 48 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS8482IRGZR ACTIVE VQFN RGZ 48 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS8482IRGZRG4 ACTIVE VQFN RGZ 48 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS8482IRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS8482IRGZTG4 ACTIVE VQFN RGZ 48 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 8-Dec-2009
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
ADS8482IBRGZR VQFN RGZ 48 1000 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2
ADS8482IBRGZT VQFN RGZ 48 250 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2
ADS8482IRGZR VQFN RGZ 48 1000 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2
ADS8482IRGZT VQFN RGZ 48 250 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Feb-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ADS8482IBRGZR VQFN RGZ 48 1000 336.6 336.6 28.6
ADS8482IBRGZT VQFN RGZ 48 250 336.6 336.6 28.6
ADS8482IRGZR VQFN RGZ 48 1000 336.6 336.6 28.6
ADS8482IRGZT VQFN RGZ 48 250 336.6 336.6 28.6
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Feb-2012
Pack Materials-Page 2
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