(MA) MOTOROLA Advance Information Universal Cordless Telephone Subsystem IC The MC13109A integrates several of the functions required for a cordless telephone into a single integrated circuit. This significantly reduces component count, board space requirements, and external adjustments. It is designed for use in both the handset and the base. Dual Conversion FM Receiver Complete Dual Conversion Receiver Antenna Input to Audio Output 80 MHz Maximum Carrier Frequency RSSI Output Carrier Detect Output with Programmable Threshold Comparator for Data Recovery Operates with Either a Quad Coil or Ceramic Discriminator Compander Expandor Includes Mute, Digital Volume Control and Speaker Driver Compressor Includes Mute, ALC and Limiter Dual Universal Programmable PLL Supports New 25 Channel U.S. Standard with No External Switches Universal Design for Domestic and Foreign CT-O Standards Digitally Controlled Via a Serial Interface Port Receive Side Includes 1st LO VCO, Phase Detector, and 14Bit Programmable Counter and 2nd LO with 12Bit Counter Transmit Section Contains Phase Detector and 14Bit Counter MPU Clock Output Eliminates Need for MPU Crystal Supply Voltage Monitor Externally Adjustable Trip Point Order this document by MC13109A/D MC13109A UNIVERSAL CT-0 SUBSYSTEM INTEGRATED CIRCUIT FB SUFFIX PLASTIC PACKAGE CASE 848B (QFP-52) FTA SUFFIX PLASTIC PACKAGE CASE 932 (LQFP-48) ORDERING INFORMATION 2.0 to 5.5 V Operation with One-Third the Power Consumption of Tested Operating Competing Devices Device Temperature Range| Package MC13109AFB QFP-52 Ta =-20 to 85C MC13109AFTA LQFP-48 Simplified Block Diagram OTT TTT TT TTT TTT TTT 7 1 id Limiting IF ! Rx | | st 2n imiting | mn Mixer Mixer Amplifier Detector | | | Y | | rr and LO RSSI Mute | Rx | PLL Expander Out Carrier | Data Detect | < | ~ Out Tx In <_| Mute = ag P Serial | | Compressor interface -t+-+ < srl Tx Out ~ fo | Tx Phase Low Batter Low _ y TxVCO Detector pa Detect | + 4 Battery | | Indicator bee 4 This device contains 6,609 active transistors. This document contains information on a new product. Specifications and information herein Motorola, Inc. 1999 are subject to change without notice. Rev 0MC13109A Figure 1. MC13109AFB Test Circuit Rx_Audio -__ ExtC_In, Tx In Open Voce d card 4 MIC_] 4 quF Am Out | R28 Open Ext_Ret C30 49.9k + Pe Rag ] R30 1.0uF C38 49.9k | 49.9k 5.0nF C35 0.01pF | Voca Fl ob HW cat Open} LO1 Mixt_In C42 | 0.47 50nF | LF Voc b C40 = 1.0uF 50 = cel = 3 Spl 1 0.01 pF x 3 F36 Tx] Amp J Lim} Amp Gnd] Vegan | LOy | LO 0.0047 3 221k Ct NAQ Ret} Out] Inf Out[ Cap| Cin| Out| In ]Audiol Ci] Out] in Fo = C46 = 50 40 MTs SSPE iy Lp O- Ses Mix, B R35 In Int = 32.4k 10.24 TAS, G9 - . g R34 MHz Out ze Mix, In2 & 17 T- = (38) oS otr | 4gpr 4 OF 6) Mixy Out R33 3.0k () 6) VB C34 = Mixe | 1.0nF C3 .0.047uF 0.01, F men > a Supply 5 eference Mix Out % @) 2 C5 OR tst LO 2nd Mix O4pF 324k Voca Gnd RF R38 Tx_VCO LVet @ Lim In cw Ask ' 32.4k a = C32 0.1yF = C33 0.1uF 455k 1 25|| 8 Lim C1 AMA vy ce00zuF pg C14 aes ss | Lim: 031 O.1pF R23 100k $ 1.0uF =2|| Sz cao cos Voc 10.2 | R8 i insi4g OF L 100k Voc RF ompFT T 10uF 15pF 29 b C8 18pF Q Coil = C. Ap L3 0.22uH @ S R22 a3 * AA 7 C27 OF WwW Cio Status CD] BD] DA] SA] SAT E] Voc] DA] Pre-] Rx] Det] Rssl P RS 221k apr Out Out | Out} Ouid) Out] in] Out | Audio] In} Amp| Audio} Out 1 | Hardware Out In ~ TOKO C11 47pF Interrupt a13 ee A7MES-12597Z ai | R27 3.9k oF MPS5179 100k ox 15 O lock R21 8.2k WW 6, | 10pF Veep : AW T Det_Out RE Ly 5 C26 10k C12 33pF o |b = oomrT Open L ut r ria} DA = Out] 11 4 2 . Gnd o Audio_In_In en 14] "CC o } EN 50V 7 | 5 Log | open c22 Data 5.0V 9 Ut c19 ) 0.1pF O 10uF L RI7 Voca > 562k = R18 Ok 50V 1.0uF 20k E_Out o) Ext_SA_In C17 Exp_IF 47uF R14 M 3 130 7 SA_Out MOTOROLA RF/IF DEVICE DATAMC13109A Figure 2. MC13109AFTA Test Circuit Rx_Audio o Tx_In Open Ext_C_In Voce ica7 1.0uF MIC R32 Amp. $28 100k Vecj2 Ext Ret Out 5 o Open P C30 c38 R29 1.0uF Bi d 199K Veep 5.0nF C46 100k ! CCA Sd R36 | 0.0047 22.1k| PF c42 R30 c40 R27 Wk 5.0nF | 49:9 C41 71.0uF 49.9k R35 CAs r uF 32.4k = O4pF Spl y 4 Tx Amp Lim Cc Amp Tx C45 Ret | Out In} Out} Cap} Cin] Out In | ay OME ct Lo2 )N9)/)}-) +9) 2) 3M 9-35pF XLT In 10.24 =k Loz TI SH VB C36 0.01pF L MHz Out S| 2nd Mix, In. 3 R33 + (2 23] Lo XX| ws 1 Ing 7 3.0k C2 castor PLL az = c30047F | 43F 4 M Mela) a x= Fa 2 C40.0tuF PD o Gnd (4) Compressor Out i PLL 6) mT Mig In = al ch R2 Ri Tx "Supply > 1 O.1NF 324k 1.5k = PD Reference Os @ Mix Out thn tH WV WW 6 2nd LO n 2nd Mix 2 = | E Cap Gnd RF Co 8 $3 Veca (7) G0) = 3] 3 7 324k Tx vCO cag Tx PLL Viet = CF2 Out & 1 ro 1.0uF VCO 4 Carrier Lim In o C6 0.022uF 6 5][ 28] | Detect (29) 0221 L > Os|/| se as = ook Ext Data as 3||Ee ES Limct k C14 Lee es instag Ler 1.0 EN Lim G2 1 15pF uF (19) 7) C8 18pF V Clk 3 Ver RE SC | tre @ 2 p08 13 0.22uH oO 100k Clk : = Out Q Coil R5 33 oe R7 (2) |] C5) zo.tk YP 224k CC) Ww WwW c27 cio cDOuv] BD] DA C Pre-| Rx! Det | RSSI O.ApF C11 47pF = 68pF Hardware | Out | Out) Out Out | Audio In] Amp | Audio| Out Det_Out p e -+ Interrupt Out In + O R6 a C13 R13 C24 R22 1.0k ZC 0.01 3.9k | 510pF R21 C26 12k AW uF O15 t ax To01nr ci2. MPSs5i79 T Prd R12 O Veep s Fie R20 = 33pF = 100k > 49.9k 49.93 d 2 = db TOKO Vv C17 c28 ce amr | [2 cot 0 ATMES-12597Z 9 {ur 50V 4g Ui Rid = Pre Amp 1.0uF I oO DA Out} 11 Open 130 b Audio_In_In = 12] 5p e 14} Veg ont Data_| EN_5.0V c22 R18 [s09_| = 50V SA_Out DAF OF 20k Data_5.0V 2 Voce : we I NW i. pen blk SOV Voca DAIn scat 58% S023 DA out 8 AW +0.033NF 0.001pF 9| pp Rg Open Ribs Mt Vvoq Gnd} 1.0k 18969 oe | ects. Lez = 10uF 0.1pF Lsog tL Rios g AM 10uF H B 1.0k7 = 7 1.0k EN_5.0V 1 Ut 4 DA oui 8 5} pp Voc Gnd - Ck SOV ut E Out Lsog + af Ok uit oO Ext. SAIn DB Exp_IF 14) veg Gnd} - LS09 1 MOTOROLA RF/IF DEVICE DATA 3MAXIMUM RATINGS MC13109A Rating Symbol Value Unit Power Supply Voltage Vec -0.510+5.5 Vde Junction Temperature TJ 65 to +150 C NOTES: 1. Devices should not be operated at or outside these limits. The Recommended Operating Conditions table provides for actual device operation. 2. ESD data available upon request. 3. Meets Human Body Model (HBM) <2000V and Machine Model (MM) <200V. RECOMMENDED OPERATING CONDITIONS Characteristic Min Typ Max Unit Vec 2.0 - 5.5 Vde Operating Ambient Temperature -20 - 85 C NOTE: All limits are not necessarily functional concurrently. ELECTRICAL CHARACTERISTICS (Vcc = 2.6 V, Ta = 25C, RF In = 46.61 MHz, fp Ey =+3.0 kHZ, fmog = 1.0 kHz; Test Circuit Figure 1.) Characteristic Min Typ Max Unit POWER SUPPLY Static Current Active Mode (Vcc = 2.6 V) - 6.1 12 mA Active Mode (Vcc = 3.6 V) - 6.5 - mA Receive Mode (Vcc = 2.6 V) - 3.9 7.0 mA Receive Mode (Vcc = 3.6 V) - 43 - mA Standby Mode (Vcc = 2.6 V) - 320 600 pA Standby Mode (Vcc = 3.6 V) - 550 - HA Inactive Mode (Vcc = 2.6 V) - 40 80 HA Inactive Mode (Vcc = 3.6 V) - 54 - HA MOTOROLA RF/IF DEVICE DATAMC13109A ELECTRICAL CHARACTERISTICS (continued) FM Receiver The FM receivers can be used with either a quad coil or a ceramic resonator. The FM receiver and ist LO have been designed to work for all country channels, including 25 channel U.S., without the need for any external switching circuitry (see Figure 25.) (Test Conditions: Vcc = 2.6 V, Ta = 25C, fo = 46.61 MHz, fpoey = 3.0 kHz, fmod = 1.0 kHz.) Input Measure Characteristic Condition Pin Pin Symbol Min Typ Max Unit Sensitivity (Input for Matched Impedance Mix4 Det Out VSIN - 0.7 - pVrms 12 dB SINAD) Differential Input In4/2 1st Mixer Voltage Vin = 1.0 mVrms, with Mix4 Mix, Out | MXgain1 - 10 - dB Conversion Gain CF as Load In4/2 2nd Mixer Voltage Vin = 3.0 mVrms, with Mixa In | Mixg Out | MXgain2 - 20 - dB Conversion Gain CFo as Load 1st Mixer Input - - Mix4 In4 Rp4 - 0.88 - kQ Impedance Mix Ina Cp 2.5 pF 2nd Mixer Input - - Mixa In Rp2 - 3.0 - kQ Impedance Cpa 2.7 pF 1st Mixer Output - - Mixy Out | Rp Out - 390 - Q Impedance Cp, Out 1.8 pF 2nd Mixer Output - - Mixa Out | Rpe Out - 1.5 - kQ Impedance Cpa Out 12 pF ist and 2nd Mixer Vin = 1.0 mVrms, with Mix4 Mix Out | MXgajinT 24 27 - dB Voltage Gain Total CF 1 and CF9 as Load In4/2 IF 3.0 dB Limiting fin = 455 kHz Lim In Det Out IF Sens - 55 100 yVrms Sensitivity Total Harmonic Distortion | With Ro = 8.2 kQ/ Mix4 Det Out THD - 1.0 3.0 % (CCITT Filter) 0.01 LF Filter at Det In4/2 Out Recovered Audio With Rc = 8.2 kQ/ Mix4 Det Out AFO 80 100 154 mVrms 0.01 LF Filter at Det In4/2 Out Demodulator Bandwidth - Lim In Det Out BW - 20 - kHz Signal to Noise Ratio Vin = 10 mVrms, Mix4 Det Out SN - 50 - dB Rc = 8.2 kQ/0.01 pF In4/2 AM Rejection Ratio 30% AM, Vin = Mix4 Det Out AMR 30 40 - dB 10 mVrms, In4/2 Rc = 8.2 kQ/0.001 WF First Mixer 3rd Order Matched Impedance Mix4 Mixy Out | TOlmix4 - -10 - dBm Intercept (Input Input In4/2 Referred) Second Mixer 3rd Order | Matched Impedance Mixa In | Mixa Out | TOlmix2 - -27 - dBm Intercept (Input Input Referred) Detector Output - - Det Out ZO - 870 - Q Impedance MOTOROLA RF/IF DEVICE DATA 5MC13109A ELECTRICAL CHARACTERISTICS (continued) RSSI/Carrier Detect Connect 0.01 UF to Gnd from RSSI output pin to form the carrier detect filter. CD Out is an open collector output which requires an external 100 kQ pull-up resistor to Vcc. The carrier detect threshold is programmable through the MPU interface. (RL = 100 kQ, Vcc = 2.6 V, Ta = 25C.) Input Measure Characteristic Condition Pin Pin Symbol Min Typ Max Unit RSSI Output Current - Mix4 In RSSI RSSl - 65 - dB Dynamic Range Carrier Sense Threshold CD Threshold Adjust = Mix4 In CD Out VT - 11 - mVrms (10100) Hysteresis - Mix In CD Out Hys - 1.5 - dB Output High Voltage Vin =O pVrms, RL = 100 | Mix, In CD Out VOH - 2.6 - Vv kQ, CD = (10100) Output Low Voltage Vin = 100 pVrms, Ri = Mix4 In CD Out VOL - 0.01 0.4 Vv 100 kQ, CD = (10100) Carrier Sense Threshold Programmable through - - VTrange -20 - 11 dB Adjustment Range MPU Interface Carrier Sense Threshold Programmable through - - VTn - 32 - - Number of Steps MPU Interface Data Amp Comparator Inverting hysteresis comparator. Open collector output with internal 100 kQ pull-up resistor. A band pass filter is connected between the Det Out pin and the DA In pin with component values as shown in the attached block diagram. The DA In input signal is ac coupled. (Voc = 2.6 V, Ta = 25C) Input Measure Characteristic Condition Pin Pin Symbol Min Typ Max Unit Hysteresis - DA In DA Out Hys 30 40 50 mV Threshold Voltage - DA In DA Out VT Veco -2.9 | Voc -9.7 | Voo-0.5 Vv Input Impedance - - DA In Z| - 12 - kQ Output Impedance - - DA Out ZO - 104 - kQ Output High Voltage Vin =Voco 1.0 V, DA In DA Out VOH Voc 0.1 2.6 - v loH =OmA Output Low Voltage Vin = Voc 0.4 V, DA In DA Out VOL - 0.04 0.4 v lol =0 mA MOTOROLA RF/IF DEVICE DATAMC13109A ELECTRICAL CHARACTERISTICS (continued) PreAmplifier/Expander/Rx Mute/Volume Control The Pre-Amplifier is an inverting rail-to-rail output swing operational amplifier with the non-inverting input terminal connected to the internal Vp half supply reference. External resistors and capacitors can be connected to set the gain and frequency response. The expander analog ground is set to the half supply reference so the input and output swing capability will increase as the supply voltage increases. The volume control can be adjusted through the MPU interface. The Rx Audio In input signal is ac coupled. (Test Conditions: Voc = 2.6 V, Ta = 25C, fi, = 1.0 kHz, Set External Pre-Amplifier Rs for Gain of 1, Volume Control = (0111).) MOTOROLA RF/IF DEVICE DATA Input Measure Characteristic Condition Pin Pin Symbol Min Typ Max Unit PreAmp Open Loop - Rx PreAmp AVOL - 60 - dB Gain Audio In Pre-Amp Gain - Rx Pre-Amp GBW - 100 - kHz Bandwidth Audio In Pre-Amp Maximum RL = 10 kQ Rx Pre-Amp | Vomax - Voc -0.3 - Vpp Output Swing Audio In Expander 0 dB Gain Vin =10 dBV Rx E Out G -3.0 0.3 3.0 dB Level Audio In Expander Gain Vin = 20 dBV, Output Rx E Out Gt -21 19.84 -19 dB Tracking Relative to G Audio In Vin =30 dBV, Output 42 40.12 -37 Relative to G Total Harmonic Vin =10 dBV Rx E Out THD - 0.2 - % Distortion Audio In Maximum Output Increase input voltage Rx E Out Vomax - -5.0 - dBV Voltage until output voltage Audio In THD = 5%, then measure output voltage. RL = 10 kQ Attack Time Ecap = 1.0 pF, Rx E Out ta - 3.0 - ms Rilt = 20 kQ Audio In (See Appendix B) Release Time Ecap = 1.0 HF, Rx E Out tr - 13.5 - ms Rilt = 20 kQ Audio In (See Appendix B) Compressor to V (Rx Audio In) Clin E Out CT - -76 - dB Expander Crosstalk =0 Vrms, Vin = -10 dBV Rx Mute Vin =10 dBV Rx E Out Me - -65 - dB No popping detectable | Audio In during Rx Mute transitions Volume Control Range Programmable through - - VCrange -14 - 16 dB MPU Interface Volume Control Steps Programmable through - - Von - 16 - - MPU Interface 7MC13109A ELECTRICAL CHARACTERISTICS (continued) Speaker Amplifier/SP Mute The Speaker Amplifier is an inverting rail-to-rail resistors and capacitors are used to set the gain and operational amplifier. The non-inverting input terminal is frequency response. The SA In input is ac coupled. connected to the internal Vp half supply reference. External (Test Conditions: Vcc = 2.6 V, Ta = 25C, fin = 1.0 kHz, External Resistors Set for Gain of 1.) Input Measure Characteristic Condition Pin Pin Symbol Min Typ Max Unit Maximum Output Swing | Voc =2.3 V, SA In SA Out Vomax - 0.8 - Vpp RL = 130 Q Voc = 2.3 V, - 2.0 - Ri = 600 Voc = 3.4 V, - 3.0 - Ri = 600 SP Mute Vin = -20 dBV SA In SA Out Msp - -67 - dB RL = 130 Q No popping detectable during SP Mute transitions Mic Amplifier The Mic Amplifier is an inverting rail-to-rail output resistors and capacitors are connected to set the gain and operational amplifier with the non-inverting input terminal frequency response. The Tx In input is ac coupled. connected to the internal Vp half supply reference. External (Test Conditions: Vcc = 2.6 V, Ta = 25C, fin = 1.0 kHz, External Resistors Set for Gain of 1.) Input Measure Characteristic Condition Pin Pin Symbol Min Typ Max Unit Open Loop Gain - Tx In Amp Out AVOL - 60 - dB Gain Bandwidth - Tx In Amp Out GBw - 100 - kHz Maximum Output Swing | RL = 10 kQ Tx In Amp Out Vomax - Voc -0.3 - Vpp 8 MOTOROLA RF/IF DEVICE DATAMC13109A ELECTRICAL CHARACTERISTICS (continued) Compressor/ALC/Tx Mute/Limiter The compressor analog gound is set to the half supply reference so the input and output swing capability will increase as the supply voltage increases. The C In input is ac coupled. The ALC (Automatic Level Control) provides a soft limit to the output signal swing as the input voltage increases slowly (i.., a sine wave is maintained). The Limiter circuit limits rapidly changing signal levels by clipping the signal peaks. The ALC and/or Limiter can be disabled through the MPU serial interface. (Test Conditions: Voc = 2.6 V, fin = 1.0 KHz, Ta = 25C.) MOTOROLA RF/IF DEVICE DATA Input Measure Characteristic Condition Pin Pin Symbol Min Typ Max Unit Compressor 0 dB Gain Vin =10 dBV, ALC Cin Lim Out G -3.0 0.06 3.0 dB Level disabled, Limiter disabled Compressor Gain Vin =30 dBV, Output Cin Lim Out Gt -11 10.12 -9.0 dB Tracking Relative to G Vin = 50 dBV, Output 23 20.16 -17 Relative to G Maximum Compressor Vin 70 dBV Cin Lim Out Aymax - 29 - dB Gain Total Harmonic Vin -10 dBV, ALC Clin Lim Out THD - 0.5 - % Distortion disabled, Limiter disabled Input Impedance - Cin Lim Out Zin - 16 - kQ Attack Time Ceap = 1.0 UF, Clin Lim Out ta - 3.0 - ms Rit = 20 kQ (see Appendix B) Release Time Ccap = 1.0 LF, Cin Lim Out tr - 13.5 - ms Rit = 20 kQ (see Appendix B) Expander to V (C In) =0 Vrms, Rx Lim Out CT - 43.6 - dB Compressor Crosstalk Vin =10 dBV Audio In Tx Data Mute Vin =10 dBV, ALC Cin Lim Out Me - -76 - dB disabled No popping detectable during Rx Mute transitions ALC Dynamic Range - Cin Lim Out DR - -18 1025 - dBV ALC Output Level Vin =18 dBV Cin Lim Out ALCout - 16 - dBV Vin =2.5 dBV - 11.4 - Limiter Output Level ALC disabled Cin Tx Out Viim - 0.8 - Vop 9MC13109A ELECTRICAL CHARACTERISTICS (continued) Splatter Amplifier The Splatter Amplifier is an inverting rail-to-rail output operational amplifier with the non-inverting input terminal connected to the internal Vp half supply reference. External resistors and capacitors can be connected to set the gain and frequency response. The Spl Amp In input is ac coupled. (Test Conditions: Vcc = 2.6 V, Ta = 25C, fin = 1.0 kHz, External resistors Set for Gain of 1.) Input Measure Characteristic Condition Pin Pin Symbol Min Typ Max Unit Open Loop Gain - Spl Amp Tx Out AVOL - 60 - dB In Gain Bandwidth - Spl Amp Tx Out GBW - 100 - kHz In Maximum Output Swing | Ry = 10 kQ Spl Amp | Tx Out Vomax - Voc - 0.3 - Vpp In Tx Audio Path Recommendation The recommended configuration for the Tx Audio path includes setting the Microphone Amplifier gain to 16 dB using the external gain setting resistors and setting the Splatter Amplifier gain to 9.0 dB using the external gain setting resistors. PLL Voltage Regulator The PLL supply voltage is regulated to a nominal of 2.2 V. The Vcc Audio pin is the supply voltage for the internal voltage regulator. The PLL Vref pin is the 2.2 V regulated output voltage. Two capacitors with 10 uF and 0.01 uF values must be connected to the PLL Vref pin to filter and stabilize this regulated voltage. The voltage regulator provides power for the 2nd LO, Rx and Tx PLLs, and MPU Interface. The voltage regulator can also be used to provide a regulated supply voltage for external ICs. Rx and Tx PLL loop (Test Conditions: Voc = 2.6 V, Ta = 25C.) performance are independent of the power supply voltage when the voltage regulator is used. The voltage regulator requires about 200 mV of headroom. When the power supply decreases to within about 200 mV of the output voltage, the regulator will go out of regulation but the output voltage will not turn off. Instead, the output voltage will maintain about a 200 mV delta to the power supply voltage as the power supply voltage continues to decrease. The PLL Vref pin can be connected to Vcc Audio by the external wiring if voltage higher than 2.2 V is required. But it should not be connected to other supply except Vcc Audio. The voltage regulator is on in the Active and Rx modes. In the Standby and Inactive modes, the voltage regulator is turned off to reduce current drain and the PLL Vref pin is internally connected to Vcc Audio (i.e., the supply voltage is maintained but is now unregulated). Input Measure Characteristic Condition Pin Pin Symbol Min Typ Max Unit Output Volige Level Voc =2.6 V, - Voc PLL Vout - 2.2 - Vv OL= OmA Line Regulation IL=OmA, Voc = 2.6 to Voc Voc PLL | Regline - 3.66 40 mV 5.5 V Load Regulation Voc =2.6 V, IL =O to Voc Voc PLL | Regload 40 2.28 - mV 1.0mA 10 MOTOROLA RF/IF DEVICE DATAMC13109A ELECTRICAL CHARACTERISTICS (continued) Low Battery Detect An external resistor divider is connected to the Ref input Bandgap reference voltage. The BD Out pin is open pin to set the threshold for the low battery detect. The voltage collector and requires and external pull-up resistor to Vcc. at the Ref input pin is compared to an internal 1.23 V (Test Conditions: Vcc = 2.6 V, Ta = 25C.) Input Measure Characteristic Condition Pin Pin Symbol Min Typ Max Unit Average Threshold Take average of rising Ref Ref/ Threshold - 1.23 - Vv Voltage and falling threshold BD Out Hysteresis - Ref Ref/ Hys - 2.0 - mV BD Out Input Current Vin =1.6 V - Ref lin - 12.33 50 nA Output High Voltage Vref = 1.6, RL = 3.9 kQ Ref BD Out VOH Voc 0.1 2.59 - Output Low Voltage Vref = 0.9, RL = 3.9 kQ Ref BD Out VOL - 0.6 0.4 Figure 3. Data Amp Operation a Data Amp Data | Signal 1 Hysteresis Output MOTOROLA RF/IF DEVICE DATA 1MC13109A PIN FUNCTION DESCRIPTION 48-TQFP | 52-QFP Pin Pin Symbol Type Description 1 1 LOo In - These pins form the PLL reference oscillator when connected to an external 2 LO2 Out parallelresonant crystal (10.24 MHz typical). The reference oscillator is also the second Local Oscillator (LO) for the RF receiver. 3 3 PLL Vref Supply Voltage Regulator output pin. The internal voltage regulator provides a stable power supply voltage for the Rx and Tx PLLs and can also be used as a regulated supply voltage for the other ICs. 4 4 Rx PD Output Three state voltage output of the Rx Phase Detector. This pin is either high, low, or high impedance depending on the phase difference of the phase detector input signals. During lock, very narrow pulses with a frequency equal to the reference frequency are present. This pin drives the external Rx PLL loop filter. It is important to minimize the line length and capacitance of this pin. 5 5 Gnd PLL Gnd Ground pin for PLL section of IC. 6 6 Tx PD Output Three state voltage output of the Tx Phase Detector. This pin is either high, low, or high impedance depending on the phase difference of the phase detector input signals. During lock, very narrow pulses with a frequency equal to the reference frequency are present. This pin drives the external Tx PLL loop filter. It is important to minimize the line length and capacitance on this pin. 7 7 E Cap - Expander rectifier filter capacitor pin. Connect capacitor to Vcc. 8 8 Tx VCO Input Transmit divide counter input which is driven by an ac coupled external transmit loop VCO. The minimum signal level is 200 mVpp @ 80.0 MHz. This pin also functions as the test mode input for the counter tests. 9 9 Data Input Microprocessor serial interface input pins for programming various counters and 10 10 EN control functions. 11 11 Clk 12 12 Clk Out Output Microprocessor Clock Output which is derived from the 2nd LO crystal oscillator and a programmable divider. It can be used to drive a microprocessor and thereby reduce the number of crystals required in the system design. The driver has an internal resistor in series with the output which can be combined with an external capacitor to form a low pass filter to reduce radiated noise on the PCB. This output also functions as the output for the counter test modes. N/A 14 Status Out Output This pin indicates when the internal latches may have lost memory due to a power glitch. 13 15 CD Out/ Output/ Dual function pin; 1) Carrier detect output (open collector with external 100 kQ Hardware Input pull-up resistor. 2) Hardware interrupt input which can be used to wake-up Interrupt from Inactive Mode. 14 16 BD Out Output Low battery detect output (open collector with external pull-up resistor). 15 17 DA Out Output Data amplifier output (open collector with internal 100 kQ pull-up resistor). 16 18 SA Out Output Speaker amplifier output. 17 19 SA In Input Speaker amplifier input (ac coupled). 18 20 E Out Output Expander output. 19 21 Vcc Audio Supply Voc supply for audio section. 20 22 DA In Input Data amplifier input (ac coupled). 21 23 Pre-Amp Out Output Preamplifier output for connection of preamplifier feedback resistor. 22 24 Rx Audio In Input Rx audio input to preamplifier (ac coupled). 23 25 Det Out Output Audio output from FM detector. 24 26 RSSI - Receive signal strength indicator filter capacitor. N/A 27 N/A - Not used. 25 28 Q Coil - A quad coil or ceramic discriminator are connected to this pin. 26 29 Voc RF Supply Voc supply for RF receiver section. 27 30 Lim C2 - IF amplifier/limiter capacitor pins. 28 31 Lim C1 12 MOTOROLA RF/IF DEVICE DATAMC13109A PIN FUNCTION DESCRIPTION (continued) 48-TQFP | 52-QFP Pin Pin Symbol Type Description 29 32 Lim In Input Signal input for IF amplifier/imiter. 30 33 Gnd RF Gnd Ground pin for RF section of the IC. 31 34 Mixa Out Output Second mixer output. 32 35 Mixa In Input Second mixer input. 33 36 VB - Internal half supply analog ground reference. 34 37 Mix Out Output First mixer output. 35 38 Mix, Ino Input Negative polarity first mixer input. 36 39 Mix Inq Input Positive polarity first mixer input. 37 40 LO, In - Tank elements for 1st LO multivibrator oscillator are connected to these pins. 38 A LO Out 39 42 Veap Ctrl - 1st LO varactor control pin. 40 43 Gnd Audio Gnd Ground for audio section of the IC. 41 44 Tx In Input Tx path input to Microphone Amplifier (ac coupled). 42 45 Amp Out Output Microphone amplifier output. 43 46 Clin Input Compressor input (ac coupled). 44 47 C Cap - Compressor rectifier filter capacitor pin. Connect capacitor to Vcc. 45 48 Lim Out Output Tx path limiter output. 46 49 Spl Amp In Input Splatter amplifier input (ac coupled). 47 50 Tx Out Output Tx path audio output. 48 51 Ref Input Reference voltage input for low battery detect. N/A 52 N/A - Not used. Power Supply Voltage programmed divider value for the reference divider is This circuit is used in a cordless telephone handset and base unit. The handset is battery powered and can operate on two or three NiCad cells or on 5.0 V power. PLL Frequency Synthesizer General Description Figure 4 shows a simplified block diagram of the programmable universal dual phase locked loop (PLL). This dual PLL is fully programmable through the MCU serial interface and supports most country channel frequencies including USA (25 ch), France, Spain, Australia, Korea, New Zealand, U.K., Netherlands and China (see channel frequency tables in Appendix A). The 2nd local oscillator and reference divider provide the reference frequency for the Rx and Tx PLL loops. The selected based on the crystal frequency and the desired Rx and Tx reference frequency values. Additional divide by 25 and divide by 4 blocks are provided to allow for generation of the 1.0 kHz and 6.25 kHz reference frequencies required for the U.K. The 14-Bit Tx counter is programmed for the desired transmit channel frequency. The 14Bit Rx counter is programmed for the desired first local oscillator frequency. All counters power up in the proper default state for USA channel #6 and for a 10.24 MHz reference frequency crystal. Internal fixed capacitors can be connected to the tank circuit of the 1st LO through microprocessor control to extend the sensitivity of the 1st LO for U.S. 25 channel operation. MOTOROLA RF/IF DEVICE DATA 131,1 10 out 2,2 Figure 4. Dual PLL Simplified Block Diagram MC13109A 12-b Programmable Reference Counter ee _ 14-b Programmable | Tx VCO [> Tx Counter 3 3 vco UK. Base Tx Phase | Tx PD IPE TxRet | Detector | 6,6 +25;--9 r U.K. Handset +4 #_, U.K. Base | +1 Rx Ref Rx PD . Rx Phase O LPF 'o U.K. Handset Detector | 4,4 Veap Ctr LT 7 139,42 B | [Loy In 14-b Programmable tt to iso] FUTT % 157.40 ae Rx Counter LO Out Dow J 38, 41 ELECTRICAL CHARACTERISTICS (Vcc = 2.6 V, Ta = 25C) Measure Characteristic Condition Pin Symbol Min Typ Max Unit PLL PIN DC Input Voltage Low - Data VIL - - 0.3 v Clk EN Hardware Int. Input Voltage High - Data VIH PLL Vref - Vcc Audio v Clk 0.3 EN Input Current Low Vin = 0.3 V Data NIL 5.0 -3.0 - HA Clk EN Input Current High Vin = (Voc Audio) Data IIH - 0.6 5.0 HA 0.3 Clk EN Hysteresis Voltage - Data Vhys - 1.0 - v Clk EN Output Current High - Rx PD IOH - - -0.7 mA Tx PD Output Current Low - Rx PD loL 0.7 - - mA Tx PD Output Voltage Low IIL =0.7 mA Rx PD VOL - - (PLL Vrer)* Vv Tx PD 0.2 Output Voltage High IIH =0. 7mMA Rx PD VOH (PLL Vref) - - Vv Tx PD 0.8 Tri-State Leakage V=1.2V Rx PD loz 50 - 50 nA Current Tx PD Input Capacitance - Data Cin - - 8.0 pF Clk EN Output Capacitance - Rx PD Cout - - 8.0 pF Tx PD 14 MOTOROLA RF/IF DEVICE DATAMC13109A ELECTRICAL CHARACTERISTICS (continued) (Vcc = 2.6 V, Ta = 25C) Measure Characteristic Condition Pin Symbol Min Typ Max Unit PLL PIN INTERFACE EN to Clk Setup Time - EN, Clk tsuEC 200 - - ns Data to Clk Setup Time - Data, Clk tsuDC 100 - - ns Hold Time - Data, Clk th 90 - - ns Recovery Time - EN, Clk trec 90 - - ns Input Pulse Width - EN, Clk tw 100 - - ns Input Rise and Fall Time - Data tr tf - - 9.0 ys Clk EN MPU Interface 90% of PLL Vref to - tpuMPU - 100 - ys PowerUp Delay Data, Clk, EN PLL LOOP 2nd LO Frequency - LOe In fLo - - 12 MHz LOg Out Tx VCO" Input Frequency | Vin = 200 MVpp Tx VCO ftxmax - - 80 MHz PLL I/O Pin Specifications The 2nd LO, Rx and Tx PLLs and MPU serial interface are normally powered by the internal voltage regulator at the PLL Vref pin. The PLL V;ef pin is the output of a voltage regulator which is powered from the Vcc Audio power supply pin. Therefore, the maximum input and output levels for most PLL VO pins (LO2 In, LO2 Out, Rx PD, Tx PD, Tx VCO) is the regulated voltage at the PLL Vref pin. The ESD protection diodes on these pins are also connected to PLL Vref. Internal level shift buffers are provided for the pins (Data, Clk, EN, Clk Out) which connect directly to the microprocessor. The maximum input and output levels for these pins is Vcc. Figure 5 shows a simplified schematic of the PLL I/O pins. Figure 5. PLL I/O Pin Simplified Schematics PLL Vret Voc Audio = PLL Vet Vcc Audio (2.2V) (2.0t05.5V) (2.2) (2.01055) LO In, LO Out, Data, Clk, and EN Pins Clk Out Pin Rx PD, Tx PD and Tx VCO Pins Microprocessor Serial Interface The Data, Clk, and EN pins provide an MPU serial interface for programming the reference counters, the transmit and receive channel divider counter and various control functions. The Data and Clk pins are used to load data into the shift register. Figure 6 shows Data and Clk pin timing. Data is clocked on positive clock transitions. Figure 6. Data and Clock Timing Requirement tr < tt F 90% Data, 10% Clk, EN 50% Data tsuDC 50% Clk After data is loaded into the shift register, the data is latched into the appropriate latch register using the EN pin. This is done in two steps. First, an 8Bit address is loaded into the shift register and latched into the 8Bit address latch register. Then, up to 16Bits of data is loaded into the shift register and latched into the data latch register specified by the address that was previously loaded. Figure 7 shows the timing required on the EN pin. Latching occurs on the negative EN transition. MOTOROLA RF/IF DEVICE DATA 15MC13109A Figure 7. Enable Timing Requirement EN Previous Data Latch The state of the EN pin when clocking data into the shift register determines whether the data is latched into the address register or a data register. Figure 8 shows the address and data programming diagrams. In the data programming mode, there must not be any clock transitions when EN? is high. The clock can be in a high state (default high) or a low state (default low) but must not have any transitions during the EN high state. The convention in these figures is that latch bits to the left are loaded into the shift register first. Figure 8. Microprocessor Interface Programming Mode Diagrams Data{ MSB 8-Bit Address \s8}- EN | Address Register Programming Mode Data{ MSB 16-Bit Data \s8}- a Xe Data Register Programming Mode The MPU serial interface is fully operational within 100 us after the power supply has reached its minimum level during power-up (See Figure 9). The MPU Interface shift registers and data latches are operational in all four power saving modes; Inactive, Standby, Rx, and Active Modes. Data can be loaded into the shift registers and latched into the latch registers in any of the operating modes. Figure 9. Microprocessor Serial Interface PowerUp Delay 2.0V Vec touMPU Data, Clk, EN Status Out This is a digital output which indicates whether the latch registers have been reset to their power-up default values. Latch power-up default values are given in Figure 28. If there is a power glitch or ESD event which causes the latch registers to be reset to their default values, the Status Out pin will indicate this to the MPU so it can reload the correct information into the latch registers. Figure 10. Status Out Operation Status Out Status Latch Register Bits Logic Level Latch bits not at powerup default value 0 Latch bits at power-up default value 1 Data Registers Figure 11 shows the data latch registers and addresses which are used to select each of these registers. Latch bits to the left (MSB) are loaded into the shift register first. The LSB bit must always be the last bit loaded into the shift register. Dont Care bits can be loaded into the shift register first if 8-Bit bytes of data are loaded. 16 MOTOROLA RF/IF DEVICE DATAMC13109A Figure 11. Microprocessor Interface Data Latch Registers Latch Address (ise 14-Bit Tx Counter LSB 1. (00000001) Tx Counter Latch (ue 14-Bit Rx Counter ) 2. (00000010) Rx Counter Latch U.K. Handset U.K. Base ( Select Xx Select Xs 12-Bit Reference Counter 9) 3. (00000011) Reference Counter Latch 14-Bit ALC Not VV Limiter\Y ck \Y meu LY meu stdoy \f Rx Tx Rx SP = Used Xie ota Ck X ClO Xie ome Oc Mode A Mute A Mute A Mute ) 4 (00000100) Mode Control Latch (is 5-Bit CD Threshold Control ) 5. (00000101) Threshold Control Latch 6. (00000110) 3-Bit 1st LO ( 4-Bit Test Mode X Capacitor Selection ) 7. (00000111) 7-Bit Auxillary Latch Reference Frequency Selection The LO In and LO Out pins form a reference oscillator when connected to an external parallel-resonant crystal. The reference oscillator is also the second local oscillator for the RF Receiver. Figure 12 shows the relationship between different crystal frequencies and reference frequencies for cordless phone applications in various countries. Figure 12. Reference Frequency and Reference Divider Values Reference U.K. Base/ Crystal Divider Handset Reference Frequency Value Divider Frequency 10.24 MHz 2048 1 5.0 kHz 10.24 MHz 1024 4 2.5 kHz 11.15 MHz 2230 1 5.0 kHz 12.00 MHz 2400 1 5.0 kHz 11.15 MHz 1784 1 6.25 kHz 11.15 MHz 446 4 6.25 kHz 11.15 MHz 446 25 1.0 kHz Reference Counter Figure 13 shows how the reference frequencies for the Rx and Tx loops are generated. All countries except U.K. require that the Tx and Rx reference frequencies be identical. In this case, set U.K. Base Select and U.K. Handset Select bits to O. Then the fixed divider is set to 1 and the Tx and Rx reference frequencies will be equal to the crystal oscillator frequency divided by the programmable reference counter value. The U.K. is a special case which requires a different reference frequency value of Tx and Rx. For U.K. base operation, set U.K. Base Select to 1. For U.K. handset operation, set U.K. Handset Select to 1. The Netherlands is also a special case since a 2.5 kHz reference frequency is used for both the Tx and Rx reference and the total divider value required is 4096 which is larger than the maximum divide value available from the 12-Bit reference divider (4095). In this case, set U.K. Base Select to 1 and set U.K. Handset Select to 1. This will give a fixed divide by 4 for both the Tx and Rx reference. Then set the reference divider to 1024 to get a total divider of 4096. Mode Control Register Power saving modes, mutes, disables, volume control, and microprocessor clock output frequency are all set by the Control Register. Operation of the Control Register is explained in Figures 14 through 21. MOTOROLA RF/IF DEVICE DATA 17MC13109A Figure 13. Reference Register Programming Mode -_ U.K. Base Tx Reference Frequency ) LOd | an 12-b +25 U.K. Handset Programmable | C1 LO9 Reference |= 4 T~9 U.K. Base Counter +1 Rx Reference Frequency LOp Out 0 U.K. Handset U.K. Handset U.K. Base | Tx Divider | Rx Divider Select Select Value Value Application 0 0 1 1 All but U.K. and Netherlands 0 1 25 4 U.K. Baseset 1 0 4 25 U.K. Handset 1 1 4 4 Netherlands Base and Handset (eX Yeon Nise 12-Bit Reference Counter st) 14-Bit Reference Counter Latch Figure 14. Control Register Bits ALC Not Limiter Clk MPU MPU MSB 4Bit Volume LSB Stdby Rx Tx Rx SP Disable Used Disable (\ Disable Clk1 Clko Control Mode Mode Mute Mute Mute Figure 15. Mute and Disable Control Bit Descriptions ALC Disable 1 Automatic Level Control Disabled 0 Normal Operation Limiter Disable 1 Limiter Disabled 0 Normal Operation Clock Disable 1 MPU Clock Output Disabled 0 Normal Operation Tx Mute 1 Transmit Channel Muted 0 Normal Operation Rx Mute 1 Receive Channel Muted 0 Normal Operation SP Mute 1 Speaker Amp Muted 0 Normal Operation Power Saving Operating Modes When the MC13109A is used in a handset, it is important sections needed to receive a transmission from the base. In the Standby and Interrupt Modes, all circuitry is powered down except for the circuitry needed to provide the clock output for the microprocessor. In Inactive Mode, all circuitry is powered down except the MPU interface. Latch memory is maintained in all modes. Figure 16 shows the control register bit values for selection of each power saving mode and Figure 17 show the circuit blocks which are powered in each of these operating mode. Figure 16. Power Saving Mode Selection to conserve power in order to prolong battery life. There are five modes of operation; Active, Rx, Standby, Interrupt and Inactive. In Active Mode, all circuit blocks are powered. In Rx mode, all circuitry is powered down except for those circuit Stdby Rx Mode Mode CD Out/Hardware Power Saving Bit Bit Interrupt Pin Mode 0 0 X Active 0 1 X Rx 1 0 X Standby 1 1 1 or High Impedance Inactive 1 1 0 Inactive 18 MOTOROLA RF/IF DEVICE DATAMC13109A Figure 17. Circuit Blocks Powered During Power Saving Modes Circuit Blocks Active Rx Standby Inactive PLL Vref Regulated Voltage x1 x1 MPU Interface X 2nd LO Oscillator MPU Clock Output RF Receiver ist LO VCO Rx PLL Carrier Detect Data Amp Low Battery Detect x | K | mK] mK] OK] KK] OK] OK) OK Tx PLL Rx Audio Path | | K | mK] mK] KL OK] KK] OK] OK Tx Audio Path ~< NOTE: 1. In Standby and Inactive Modes, PLL V;e7 remains powered but is not regulated. It will fluctuate with Voc. Inactive Mode Operation and Hardware Interrupt In some handset applications it may be desirable to power down all circuitry including the microprocessor (MPU). First put the MC13109A into the Inactive mode, which turns off the MPU Clock Output (see Figure 18), and then disable the microprocessor. In order to give the MPU adequate time to power down, the MPU Clock output remains active for a minimum of one reference counter cycle (about 200 us) after the command is given to switch into the Inactive mode. An external timing circuit should be used to initiate the turnon sequence. The CD Out pin has a dual function. In the Active and Rx modes it performs the carrier detect function. In the Standby and Inactive modes the carrier detect circuit is disabled and the CD Out pin is in a High state due to the external pull-up resistor. In the Inactive mode the CD Out pin is the input for the hardware interrupt function. When the CD Out pin is pulled low by the external timing circuit, the MC13109A switches from the Inactive to the Interrupt mode thereby turning on the MPU Clock Output. The MPU can then resume control of the combo IC. The CD Out pin must remain low until the MPU changes the operating mode from Interrupt to Standby, Active or Rx modes. Figure 18. Hardware Interrupt Operation Mode Active/Rx Inactive Interrupt Standby/Rx/Active LY MPU Initiates Y MPU Initiates EN /\ Inactive Mode / \ Mode Change | CD Out Li CD Out/Hardware Interrupt utLow / My \ CD Turns Off MPU Clock Out Delay after MPU selects Inactive Mode to when CD turns off >| b< >| External Timer Pulls Pin Low L/ \ Timer Output Disabled << MPU Clock Out remains active for a minimum of one count of reference counter after CD Out/Hardware Interrupt pin goes high MOTOROLA RF/IF DEVICE DATA 19MC13109A Clk Out Divider Programming The Clk Out pin is derived from the 2nd local oscillator and can be used to drive a microprocessor, thereby reducing the number of crystals required. Figure 19 shows the relationship between the crystal frequency and the clock output for different divider values. Figure 20 shows the Clk Out register bit values. Figure 19. Clock Output Values Crystal Clock Output Divider Frequency 2 3 5 10 10.24 MHz | 5.120 MHz | 3.413 MHz | 2.048 MHz | 1.024 MHz 11.15 MHz | 5.575 MHz | 3.717 MHz | 2.230 MHz | 1.115 MHz 12.00 MHz | 6.000 MHz | 4.000 MHz | 2.400 MHz | 1.200 MHz Figure 20. Clock Output Divider Clk Out Clk Out Clk Out Bit #1 Bit #2 Divider Value 0 0 2 0 1 3 1 0 5 1 1 10 MPU Clk Out Power-Up Default Divider Value The power-up default divider value is divide by 10. This provides an MPU clock of about 1.0 MHz after initial power-up. The reason for choosing this relatively low clock frequency after intial power-up is that some microprocessors that operate down to a 2.0 V power supply have a maximum clock frequency of 1.0 MHz. After initial powerup, the MPU can change the clock divider value to set the clock to the desired operating frequency. Special care has been taken in the design of the clock divider to ensure that the transition between one clock divider value and another is smooth (i.e., there will be no narrow clock pulses to disturb the MPU). MPU Clk Out Radiated Noise on Circuit Board The clock line running between the MC13109A and the microprocessor has the potential to radiate noise which can cause problems in the system especially if the clock is a square wave digital signal with large high frequency harmonics. In order to minimize radiated noise, a 1.0 kQ resistor is included on-chip inseries with the Clk Out output driver. A small capacitor can be connected to the Clk Out line on the PCB to form a single pole low pass filter. This filter will significantly reduce noise radiated from the Clk Out line. Volume Control The volume control can be programmed in 2.0 dB gain steps from 14 cB to 16 dB. The power-up default value is 0 dB. Figure 21. Volume Control Volume Control Volume Control Volume Control Volume Control Volume Gain/Attenuation Bit #3 Bit #2 Bit #1 Bit #0 Control # Amount 0 0 0 0 0 -14dB 0 0 0 1 1 12 dB 0 0 1 0 2 -10 dB 0 0 1 1 3 -8.0dB 0 1 0 0 4 -6.0 dB 0 1 0 1 5 -4.0dB 0 1 1 0 6 -2.0dB 0 1 1 1 7 0 dB 1 0 0 0 8 2.0 dB 1 0 0 1 9 4.0 dB 1 0 1 0 10 6.0 dB 1 0 1 1 11 8.0 dB 1 1 0 0 12 10 dB 1 1 0 1 13 12 dB 1 1 1 0 14 14dB 1 1 1 1 15 16 dB Gain Control Register The gain control register contains bits which control the Carrier Detect threshold. Operation of these latch bits are explained in Figures 22 and 23. Figure 22. Gain Control Latch Bits 5-Bit CD Threshold Control (i 0) 20 MOTOROLA RF/IF DEVICE DATAMC13109A Carrier Detect Threshold Programming detect threshold is given in the carrier detect specification The CD Out pin will give an indication to the section of this document. If a different carrier detect threshold microprocessor if a carrier signal is present on the selected value is desired, it can be set through the MPU interface as channel. The nominal value and tolerance of the carrier shown in Figure 23 below. Figure 23. Carrier Detect Threshold Control cD cD cD cD Carrier Detect Bit #2 Bit #1 Bit #0 Control # Threshold 0 0 0 0 20 dB 0 1 a 0 -19dB 0 0 -18dB 0 -17 dB -16 dB -15dB -14dB -13 dB 12 dB Oo; CO] N] om] oo] BR] wo] MY -11 dB 4 o -10 dB =a = -9.0 dB 4 Nh 8.0 dB ae ao -7.0 dB a ms 6.0 dB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 ol 5.0 dB a oO 4.0 dB = I 3.0 dB -2.0 dB afou oO] @ -1.0 dB No oO 0dB Nh a 1.0 dB 2.0 dB OoO;/o;/o;o; ao; o]; oa] o0 nN No N oa 3.0 dB No 4.0 dB nN ol 5.0 dB No o 6.0 dB N ~I 7.0 dB NO co 8.0 dB nN o 9.0 dB o oO 10 dB 11 dB ao 4 MOTOROLA RF/IF DEVICE DATA 21MC13109A circuit to change the 1st LO sensitivity. Internal switches and capacitors are provided to enable microprocessor control over internal fixed capacitor values. Figure 25 shows the schematic of the 1st LO tank circuit. Figure 26 shows the latch control bit values. Auxiliary Register The auxiliary register contains a 3-Bit 1st LO Capacitor Selection latch and a 4Bit Test Mode latch. Operation of these latch bits are explained in Figures 24, 25 and 26. Figure 24. Auxiliary Register Latch Bits Figure 25. First LO Schematic ; BBitistLO j.\Q TTT (ie 4-Bit Test Mode sa) Capacitor Selection 2) | | Voap Ctr Varactor 42 he on 5 opera Capacitor Selection for 25 Internal Capacitor 4 LOy In anne U.S. peration -$99_p# I O c ft There is a very large frequency difference between the istlo| TPP Tm Z| 40 eX Lext minimum and maximum channel frequencies in the proposed Varactor| ) LO1 Out 25 Channel U.S. standard. The sensitivity of the 1st LO is not | 44 large enough to accommodate this large frequency variation. | Fixed capacitors can be connected across the 1st LO tank | Figure 26. 1st LO Capacitor Select for U.S. 25 Channels 1st LO 1st LO 1st LO 1st LO U.S. U.S. Varactor Value External External Cap. Cap. Cap. Cap. Base Handset over 0.5 to 2.2 Capacitor Inductor Bit 2 Bit 1 Bit 0 Select Channels Channels V Range Value Value 0 0 0 0 16 25 - 10 6.4 pF 27 pF 0.47 LH 0 0 0 0 - 16 25 10 6.4 pF 33 pF 0.47 LH 0 0 1 1 1-6 - 10 -6.4 pF 27 pF 0.47 pH 0 1 0 2 7-15 - 10 6.4 pF 27 pF 0.47 LH 0 1 1 3 - 1-6 10 -6.4 pF 33 pF 0.47 pH 1 0 0 4 - 7-15 10 6.4 pF 33 pF 0.47 LH 22 MOTOROLA RF/IF DEVICE DATAMC13109A Figure 27. Test Mode Description Counter Under Test or Tx VCO TM# | TM3 | TM2 | TM1 | TMO Test Mode Option Input Signal Clk Out Output Expected 0 0 0 0 0 Normal Operation >200 mVpp - 1 0 0 0 1 Rx Counter, upper 6 Oto22V Input Frequency/64 2 0 0 1 0 Rx Counter, lower 8 O0to2.2V See Note Below 3 0 0 1 1 Rx Prescaler Oto22V Input Frequency/4 4 0 1 0 0 Tx Counter, upper 6 Oto22V Input Frequency/64 5 0 1 0 1 Tx Counter, lower 8 O0to2.2V See Note Below 6 0 1 1 0 Tx Prescaler >200 mVpp Input Frequency/4 7 0 1 1 1 Reference Counter Oto22V Input Frequency/Reference Counter Value 8 1 0 0 0 Divide by 4, 25 Oto22V Input Frequency/100 9 1 0 0 1 AGC Gain = 10 Option N/A - 10 1 0 1 0 AGC Gain = 25 Option N/A - NOTE: To determine the correct output, look at the lower 8 bits in the Rx or Tx register (Divisor (7;0). If the value of the divisor is > 16, then the output divisor value is Divisor (7;2) (the upper 6 bits of the divisor). If Divisor (7;0) < 16 and Divisor (3;2) > = 2, then output divisor value is Divisor (3;2) (bits 2 and 3 of the divisor). If Divisor (7;0) < 16 and Divisor (3;2) < 2, then output divisor value is (Divisor (3;2) + 60). Test Modes Test Mode Control latch bits enable independent testing of internal counters and set AGC Gain Options. In test mode, the Tx VCO input pin is multiplexed to the input of the counter under test and the output of the counter under test is multiplexed to the Clk Out output pin so that each counter can be individually tested. Make sure test mode bits are set to 0 for normal operation. Test mode operation is described in Figure 27. During normal operation and when testing the Tx Prescaler, the Tx VCO input can be a minimum of 200 mVpp at 80 MHz and should be ac coupled. For other test modes, input signals should be standard logic levels of 0 to 2.2 V and a maximum frequency of 16 MHz. PowerUp Defaults for Control and Counter Registers When the IC is first powered up, all latch registers are initialized to a defined state. The MC13109A is initially placed in the Rx mode with all mutes active and nothing disabled. The reference counter is set to generate a 5.0 kHz reference frequency from a 10.24 MHz crystal. The MPU clock output divider is set to 10 to give the minimum clock output frequency. The Tx and Rx latch registers are set for USA Channel Frequency #21. Figure 28 shows the initial power-up states for all latch registers. Figure 28. Latch Register PowerUp Defaults MSB LSB Register Count 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Tx 9965 - - 1 0 0 1 1 0 1 1 1 0 1 1 1 0 Rx 7215 - - 0 1 1 1 0 0 0 0 1 0 1 1 1 1 Ref 2048 - - 0 0 1 0 0 0 0 0 0 0 0 0 0 0 Mode N/A - 0 0 0 0 1 1 0 1 1 1 0 1 1 1 1 Gain N/A - - - - - - - - - - - 1 0 1 0 0 T N/A - - - - - - - - - 0 0 0 0 0 0 0 MOTOROLA RF/IF DEVICE DATA 23MC13109A Figure 29. lcc versus Vcc at Active Mode lec, SUPPLY CURRENT (mA) 0 2.5 3.0 35 40 45 5.0 Voc, SUPPLY VOLTAGE (V} Figure 31. lc versus Vcc at Standby Mode 1.2 10 ZO 0.8 AO 0.6 1] 0.4 0.2 loc. SUPPLY CURRENT (mA) 0 2.5 3.0 35 40 45 5.0 Voc, SUPPLY VOLTAGE (V} Figure 33. RSSI Output versus RFjn lec, SUPPLY CURRENT (mA) loc. SUPPLY CURRENT (1A) Figure 30. Icc versus Vcc at Receive Mode 5.0 45 | a 3.5 25 3.0 35 4.0 45 5.0 Vcc, SUPPLY VOLTAGE (V) Figure 32. Ic versus Vcc at Inactive Mode 0 2.5 3.0 3.5 4.0 45 5.0 Voc, SUPPLY VOLTAGE (V} Figure 34. Recovered Audio/THD versus fpEy 300 6.0 250 - R22 = 12 kQ ot 50 S i Ss 2 200 Recovered Audio 4.0 > 2 = EE a ra Lf & > i 150 i 3.0 5 i YY 2 3 S 100 A 2.0 c a LT THD 50 1.0 0 0 0 -120 100 -80 60 40 -20 0 10 20 30 40 50 60 70 80 90 RF in, RF INPUT (dBm) {pry DEVIATION, (kHz) 24 MOTOROLA RF/IF DEVICE DATAEXPANDER, E OUT (dBV) MC13109A Figure 35. Typical Expander Response Rx AUDIO IN (dBV} Figure 37. First Mixer Third Order Intercept Performance ls 20 Za E a S | 5 / a 49 w 5 LY o & | = = -60 oe -80 -80 -70 -60 -50 40 -30 -20 -10 MIXER; IN (dBm) COMPRESSOR LEVEL OUTPUT, LIM OUT (dBV) MIXER OUTPUT (dBm) Figure 36. Typical Compressor Response 10 ACL ors -20 ACL On _] -30 -40 A] i 50 -60 -80 -70 -60 50 40 -30 = -20 -10 0 COMPRESSOR, Cj, LEVEL INPUT (dBV) Figure 38. Second Mixer Third Order Intercept Performance 0 fap ereaTa| -20 / -40 f -60 / -80 -90 30 -70 60 50 40 -30 2 -10 0 MIXERg IN (dBm) MOTOROLA RF/IF DEVICE DATA 25MC13109A APPENDIX A - MEASUREMENT OF COMPANDOR ATTACK/DECAY TIME This measurement definition is based on EIA/CCITT recommendations. Compressor Attack Time For a 12 dB step up at the input, attack time is defined as the time for the output to settle to 1.5X of the final steady state value. Compressor Decay Time For a 12 dB step down at the input, decay time is defined as the time for the input to settle to 0.75X of the final steady state value. 12 dB Input | OmvV Attack Time >| ~ = / Decay Time 1.5X Final Value Output 0.75X Final Value OmvV Expander Attack For a 6.0 GB step up at the input, attack time is defined as the time for the output to settle to 0.57X of the final steady state value. Expander Decay For a 6.0 dB step down at the input, decay time is defined as the time for the output to settle to 1.5X of the final steady state value. 6.0 dB Input | OmvV Attack Time > _ Decay Time 0.57X Final Value 1.5X Final Value Output OmvV 26 MOTOROLA RF/IF DEVICE DATAMC13109A OUTLINE DIMENSIONS FB SUFFIX PLASTIC PACKAGE CASE 848B-04 (QFP-52) es ISSUE C | | i 39 27 I Dg __ i a @ @ DETAILA oc |o | |O | Cc DETAILA T @ @ < F z 2 <= | << { f= |m .o | LT } Y el|x|* le i iG N elal | le olo oS s/s | |S olw sls oS | BASE METAL = IN| | |/P < D | | 0.02 (0.008)@|c| A-B| D ] [ SECTION B-B NOTES: B 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. mal am 2, CONTROLLING DIMENSION: MILLIMETER. i 3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS @ 0.20 (0.008) | H] A B | D Q| COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE L 0.05 (0 002) | A-B PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. : : 4, DATUMS -A-, -B- AND -D- TO BE DETERMINED AT DATUM at V PLANE -H-, 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING = PLANE -C-. L| 0.20 (0.008) @| c| A B | D ] 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER 3. leg DETAILC SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH Co M AND ARE DETERMINED AT DATUM PLANE -H-. -E yr x. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. Z N ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) C| SEATING PLANE DATUM TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM PLANE MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON ' a THE LOWER RADIUS OR THE FOOT. y . | 0.10 (0.004) MILLIMETERS INCHES f 4 _ LL ate G M _ 7 R \ Q? T K ~|W) x -< DETAIL C Motorola reserves the right to make changes without further notice to any products herein. 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MOTOROLA RF/IF DEVICE DATA 27MC13109A OUTLINE DIMENSIONS FTA SUFFIX PLASTIC PACKAGE 4x CASE 932-02 Thi P NQTES: a lo. 2] Pz] ( oO. . ( eet 8) AB DIMENSIONING AND TOLERANCING PER ANSI / \ D E T Y14.5M, 1982. A I TROLLING DIMENSION: MILLIMETER. > P JATUM PLANE -AB- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. DATUMS -T-, -U-, AND -Z- TO BE DETERMINED AT DATUM PLANE -AB-. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -AC-. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -AB-. DIMENSION D DOES NOT INCLUDE DAMBAR ] I | PROTRUSION. DAMBAR PROTRUSION SHALL A E MOT CAUSE THE D DIMENSION TO EXCEED 0.350 (0.014). MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). EXACT SHAPE OF EACH CORNER IS OPTIONAL. rc wor a a LC ~ o MILLIMETERS INCHES I 4 I I Cc 0 ( 0 oO ~~ mM oc T a LM T oO P & B oO R G A U G E P L A N E 0 : 2 5 0 ( 0 0 Cc E + \ [0 . 0@|a | tc @| | 0... 4 s E Cc T l Oo Ny A iv E Q oO D E T A }K A oD <# X M f a x i s H w t r e a c h u s : USA/EUROPE/ Locations Not Listed: Motorola Literature Distribution; JAPAN: Motorola Japan Lid.; SPD, Strategic Planning Office, 141, P.O. Box 5405, Denver, Colorado 80217. 1-303-675-2140 or 1-800-441-2447 4-321 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan. 81-3-5487-8488 Customer Focus Center: 1-800-521-6274 Mfax: RMFAX0@email.sps.mot.com TOUCHTONE 1-602-244-6609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, Motorola Fax Back System US & Canada ONLY 1-800-774-1848 2, Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. http://sps.motorola.com/mfax/ 85226629298 HOME PAGE: hittp://motorola.com/sps/ (S) MOTOROLA % MC13109A/D