Wideband IF Receiver Subsystem AD6676 Data Sheet FEATURES APPLICATIONS High instantaneous dynamic range Noise figure (NF) as low as 13 dB Noise spectral density (NSD) as low as -159 dBFS/Hz IIP3 up to 36.9 dBm with spurious tones <-99 dBFS Tunable band-pass - analog-to-digital converter (ADC) 20 MHz to 160 MHz signal bandwidth 70 MHz to 450 MHz IF center frequency Configurable input full-scale level of -2 dBm to -14 dBm Easy to drive resistive IF input Gain flatness of 1 dB with under 0.5 dB out-of-band peaking Alias rejection greater than 50 dB 2.0 GSPS to 3.2 GSPS ADC clock rate On-chip PLL clock multiplier 16-bit I/Q rate up to 266 MSPS On-chip digital signal processing NCO and quadrature digital downconverter (QDDC) Selectable decimation factor of 12, 16, 24, and 32 Automatic gain control (AGC) support On-chip attenuator with 27 dB span in 1 dB steps Fast attenuator control via configurable AGC data port Peak detection flags with programmable thresholds Single or dual lane, JESD204B capable Low power consumption: 1.20 W 1.1 V and 2.5 V supply voltage TDD power saving up to 60% 4.3 mm x 5.0 mm WLCSP Wideband cellular infrastructure equipment and repeaters Point-to-point microwave equipment Instrumentation Spectrum and communication analyzers Software defined radio GENERAL DESCRIPTION The AD66761 is a highly integrated IF subsystem that can digitize radio frequency (RF) bands up to 160 MHz in width centered on an intermediate frequency (IF) of 70 MHz to 450 MHz. Unlike traditional Nyquist IF sampling ADCs, the AD6676 relies on a tunable band-pass - ADC with a high oversampling ratio to eliminate the need for band specific IF SAW filters and gain stages, resulting in significant simplification of the wideband radio receiver architecture. On-chip quadrature digital downconversion followed by selectable decimation filters reduces the complex data rate to a manageable rate between 62.5 MSPS to 266.7 MSPS. The 16-bit complex output data is transferred to the host via a single or dual lane JESD204B interface supporting line rates of up to 5.333 Gbps. FUNCTIONAL BLOCK DIAGRAM VSS2IN VSS2OUT VDD2NV AGC4, AGC3 AGC2, AGC1 VDDIO RESETB -2.0V REG VIN+ BAND-PASS - ADC VIN- SCLK SDIO SDO VDDHSI QDDC + NCO I I Mx Q L+ L- CLOCK SYNTHESIZER SPI CLOCK GENERATION M = 12, 16, 24, 32 Q JESD204B SERIALIZER Tx OUTPUTS 27dB ATTENUATOR (1dB STEPS) CSB AGC SUPPORT JESD204B SUBCLASS 1 CONTROL SERDOUT0+ SERDOUT0- SERDOUT1+ SERDOUT1- SYNCINB SYSREF VDDQ VDDC CLK+ CLK- VDD2 VDDL VDD1 VSSA VDDD VSSD 12348-001 AD6676 Figure 1. 1 This product is protected by U.S. and international patents. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2014-2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD6676 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Attenuator.................................................................................... 33 Applications ....................................................................................... 1 Clock Synthesizer ....................................................................... 35 General Description ......................................................................... 1 Digital Processing Blocks .............................................................. 38 Functional Block Diagram .............................................................. 1 Digital Signal Processing Path .................................................. 39 Revision History ............................................................................... 3 AGC Features and Peak Detection........................................... 42 Product Highlights ........................................................................... 4 GPIO Functionality .................................................................... 44 Specifications..................................................................................... 5 Power Saving Modes .................................................................. 44 Digital High Speed SERDES Specifications .............................. 7 Introduction to the JESD204B Interface ................................. 45 CLK to SYSREF Timing Diagram ......................................... 8 Functional Overview ................................................................. 47 Digital CMOS Input/Output Specifications ............................. 8 JESD204B Link Establishment ................................................. 47 Absolute Maximum Ratings............................................................ 9 Physical Layer Input/Outputs ................................................... 49 Thermal Resistance ...................................................................... 9 Configuring the JESD204B Link .............................................. 50 ESD Caution .................................................................................. 9 Synchronization Using SYSREF ............................................. 51 Pin Configuration and Function Descriptions ........................... 10 Applications Information .............................................................. 53 Typical Performance Characteristics ........................................... 12 Analog Input Considerations ................................................... 53 Nominal Performance for IF = 115 MHz (Direct Sampling VHF Receiver) ............................................................................ 12 Clock Input Considerations ...................................................... 54 Nominal Performance for IF = 140 MHz (W Point-to-Point Receivers)..................................................................................... 14 PCB Design Guidelines ............................................................. 57 Nominal Performance for IF = 181 MHz (Wireless Infrastructure Receiver)............................................................. 15 AD6676 Start-Up Initialization ................................................ 61 IF Frequency Planning .............................................................. 56 Powering the AD6676................................................................ 59 Nominal Performance for IF = 250 MHz AND BW = 75 MHz ....................................................................................................... 17 Serial Port Interface (SPI) .............................................................. 64 Nominal Performance for IF = 350 MHz AND BW = 160 MHz ...................................................................................... 19 SPI Operation ............................................................................. 64 Register Memory Map and Details .............................................. 66 Equivalent Circuits ......................................................................... 21 Register Memory Map ............................................................... 66 Terminology .................................................................................... 22 Register Details ........................................................................... 68 Theory of Operation ...................................................................... 23 Outline Dimensions ....................................................................... 90 Overview...................................................................................... 23 Ordering Guide .......................................................................... 90 SPI Register Map Description .................................................. 64 Band-Pass - ADC Architecture ........................................... 24 - ADC Configuration Considerations................................ 28 Rev. D | Page 2 of 90 Data Sheet AD6676 REVISION HISTORY 5/2017--Rev. C to Rev. D Change to Differential Output Voltage Parameter, Table 2 ......... 7 Changes to Figure 147 ....................................................................65 3/2017--Rev. B to Rev. C Added Endnote 1, Table 12 ............................................................36 Changes to Synchronization Using SYSREF Section ..............51 Added Table 123; Renumbered Sequentially ...............................87 4/2016--Rev. A to Rev. B Changes to Figure 3 and Table 6 ...................................................10 Changes to Clock Input Considerations Section and Figure 133 .........................................................................................55 9/2015--Rev. 0 to Rev. A Changes to Product Highlights Section ......................................... 4 Changes to Clock Synthesizer Enabled Parameter, Table 1 and Out-of-Range Recovery Time Parameter Unit, Table 1 ............... 5 Changes to Differential Output Voltage, Table 2 .......................... 7 Changes to Table 3 ............................................................................ 8 Changes to Figure 3.........................................................................10 Changes to Figure 4, Figure 8 Caption, and Figure 9 .................12 Changes to Figure 26 ......................................................................15 Changes to Figure 36 and Figure 38 .............................................17 Changes to Figure 40, Figure 41, and Figure 44 ..........................18 Changes to Figure 50 ......................................................................19 Changes to Attenuator Section ......................................................33 Changes to Table 12 ........................................................................36 Changes to Phase Noise Performance Section, Figure 101, and Figure 102 .........................................................................................37 Changes to Quadrature Digital Downconversion Section ........39 Changes to Synchronization Using SYSREF Section ............... 51 Added Figure 127; Renumbered Sequentially ............................. 52 Changes to Input Driver Filter Considerations Section and Figure 130 ......................................................................................... 54 Changes to Clock Input Considerations Section and Figure 133 to Figure 135 .................................................................................... 55 Changes to PCB Design Guidelines Section ............................... 57 Added Figure 141; Renumbered Sequentially ............................. 58 Changes to Power the AD6676 Section and Figure 142 ............ 59 Changes to AD6676 Start-Up Initialization Section and Table 25 ............................................................................................. 61 Changes to Table 26 ........................................................................ 62 Changes to Table 27 and Table 29 ................................................. 63 Changes to Table 32 ........................................................................ 66 Changes to Coarse NCO Tuning Register Section and Table 57 ............................................................................................. 72 Changes to Fine NCO Tuning Register Section and Table 58 .. 73 Changes to Table 70 to Table 72 .................................................... 75 Changes to Table 73 ........................................................................ 76 Changes to Table 109 ...................................................................... 84 Added Physical Control 1 Register Section and Table 116 ........ 85 Changes to Table 120 ...................................................................... 86 Changes to Table 121 and Table 123, and Table 125 .................. 87 Changes to CLKSYN Reference Divider and SYSREF Control Register Section, Table 128, CLKSYN Status Register Section, and Table 129 ................................................................................... 88 JESDSYN Status Register Section, Table 130, and Table 131 to Table 133 ........................................................................................... 89 10/2014--Revision 0: Initial Version Rev. D | Page 3 of 90 AD6676 Data Sheet The band-pass - ADC of the AD6676, which operates between 2.0 GHz to 3.2 GHz, provides exceptional instantaneous dynamic range and inherent antialiasing capability. Its in-band frequency response typically maintains better than 1 dB pass band flatness with out-of-band peaking better than 0.5 dB. An integrated digital peak detector enables the instantaneous signal power to be monitored over a wide band (shortly after digitization), thus providing AGC capability to cope quickly with large in-band or out-of-band blockers. The AD6676 includes various AGC monitoring and control features along with an internal 27 dB step attenuator in 1 dB steps. A flexible AGC port with digital input/output pins allows fast control of the AD6676 on-chip step attenuator and/or updates on the input signal via status flags. These features, along with the high instantaneous dynamic range, can significantly simplify AGC implementation compared to traditional narrow-band IF approaches that often require separate AGC capability for RF and IF protection. In addition to reducing system complexity, the AD6676 enables significant space and power consumption savings for next generation multiple input/multiple output (MIMO) receiver architectures. The AD6676 is available in an 8 x 10 ball array WLCSP package that is approximately 4.3 mm x 5.0 mm, with a JESD204B serial interface that allows simple interfacing to the host processor. Its low power consumption of 1.2 W compares favorably to IF sampling ADCs with similar bandwidth (BW) and dynamic range capabilities even without considering the added power savings from the elimination of an entire IF strip. The AD6676 features multichip synchronization that allows synchronization to within a fraction of an output data sample. For time-domain duplex (TDD) applications, the AD6676 features a fast powerup/power-down mode that further reduces power consumption while still maintaining multichip synchronization. Power savings of up to 60% or 42% is achievable with recovery times of 11.5 s or 2.5 s, depending on the device configuration. Auxiliary blocks include an on-chip PLL clock multiplier to generate the - ADC clock. For applications that require better phase noise performance, an external differential RF clock source may also be used. The SPI port programs numerous parameters of the AD6676, allowing the device to be optimized for a variety of applications. The AD6676 is available in an 80-ball WLCSP package with an optimized pinout that enables low cost printed circuit board (PCB) manufacturing. The device operates from a 1.1 V and 2.5 V supply with a total typical power consumption of 1.2 W at 3.2 GSPS operation. This product is protected by several United States patents. Contact Analog Devices, Inc., for further information. PRODUCT HIGHLIGHTS 1. 2. 3. 4. 5. 6. 7. 8. Rev. D | Page 4 of 90 Industry leading dynamic range enables high performance, reconfigurable heterodyne (or direct sampling VHF) software defined radios with high AGC-free range. Continuous time, band-pass - ADC supports IFs from 70 MHz to 450 MHz with IF signal bandwidths of up to 160 MHz and reduces IF filtering requirements. The high instantaneous dynamic range and oversampling nature of the - ADC significantly reduces the IF filter complexity. On-chip 27 dB digital attenuator with easy to drive resistive input simplifies interface to RF/IF components. Small 4.3 mm x 5.0 mm package, simple interface, and integrated digital attenuator and clock synthesizer save PCB space. Low input full-scale level of -2 dBm (or less) enables 3.3 V RF/IF component lineups at reduced P1dB and power. Fast power saving mode supports TDD protocols. Unique profile mode allows the AD6676 to switch between up to four different ADC IF/BW configurations in 1 s. Data Sheet AD6676 SPECIFICATIONS VDD1 = VDDL = VDDC = VDDQ = 1.1 V, VDDD = VDDHSI = 1.1 V, VDD2 = 2.5 V, VDDIO = 1.8 V, FIF = 250 MHz, BW = 75 MHz, FADC = 3.2 GHz, attenuator = 0 dB, L (inductor values) = 19 nH, maximum PIN_0dBFS setting with IDAC1FS = 4 mA, fDATA_IQ = 200 MSPS, shuffler enabled (every clock cycle) with default threshold of 5, unless otherwise noted. Table 1. Parameter SYSTEM DYNAMIC PERFORMANCE Full-Scale Input Power Level (PIN_0dBFS)1 Maximum Continuous Wave (CW) Input Power2 Noise Figure (NF) Worst In-Band Noise Spectral Density Noise Figure at IF Center (NF) In-Band Noise Spectral Density (NSD) Input Second-Order Intercept (IIP2) Second-Order Intermodulation Distortion (IMD) (IMD2) Input Third-Order Intercept (IIP3) Third-Order IMD (IMD3) Worst In-Band Spur for Swept CW Tone In-Band Noise Gain Variation IF INPUT (VIN) Input Span 0 dB Attenuator Setting 12 dB Attenuator Setting Common-Mode Input Voltage Differential Input Impedance Common-Mode Input Impedance Full-Scale Input Power Adjustment (PIN_0dBFS) DIGITAL STEP ATTENUATOR (VIN) Attenuation Range Step Size Input Return Loss Input Return Loss Variation vs. Attenuator Setting CLOCK INPUT (CLK) Clock Synthesizer Disabled Frequency Range Amplitude Range Differential Input Impedance Common Mode Impedance Input Return Loss Common-Mode Voltage Clock Synthesizer Enabled Frequency Range3 Amplitude Range CLK+ Input Impedance Minimum Slew Rate Common-Mode Voltage Temperature Full Full Full Full Full Full Full Test Conditions/Comments Min Typ -2 -2 -1 No signal and measured Over a 5 MHz bandwidth No signal and measured Over a 5 MHz bandwidth -6 dBFS tones See Table 20 17 -155 13 -159 60 -68.3 -8 dBFS tones -8 dBFS tones -2 dBFS tone -10 dBFS tone -2 dBFS tone No CW tone 36.9 -95 -99 -109.6 -75.5 -78.5 0.5 Max Unit dBm dBFS -152.5 -84.2 -93.5 -73.7 -76.5 dB dBFS/Hz dB dBFS/Hz dBm dBc dBm dBc dBFS dBFS dBFS dBFS dB 0 dBFS Self biased 25C 25C IDAC1FS span of 1 mA to 4 mA Full Full Full Full Full Full 25C 25C 25C 25C 2.0 0.4 At 3 GHz At 3 GHz With 1:2 balun Self biased Full Full 25C Single-ended into CLK+ 25C Self biased Rev. D | Page 5 of 90 10 0.4 0.48 1.92 1.0 60||2 3.5 12 V p-p V p-p V ||pF k dB 27 1 20 2 dB dB dB dB 0.8 86||0.3 700||0.8 15 0.70 0.8 1.4||1.0 12 0.55 3.2 2.0 GHz V p-p ||pF ||pF dB V 320 1.1 MHz V p-p k||pF V/s V AD6676 Parameter CLOCK SYNTHESIZER Phase Detector Frequency Minimum Charge Pump Output Current Maximum Charge Pump Output Current VCO Tuning Range - ADC AND DIGITAL DOWNCONVERTER Resolution Clock Frequency (FADC) IF Center Frequency (FIF) IF Bandwidth IF Pass Band Gain Flatness Out-of-Band Peaking Alias Rejection Fixed Decimation Factors Data Sheet Temperature Full Full Full Full Full Digital Supply Voltage (VDDD) JESD204B Supply Voltage (VDDHSI) SPI Interface Supply Voltage (VDDIO) Analog Supply Current IVDD1 + IVDDL IVDDC + IVDDQ IVDDC4 + IVDDQ IVDD2 + IVDD2NV Digital Supply Current (IVDDD) JESD204B Supply Current (IVDDHSI) SPI Interface Supply Current (IVDDIO) Power Consumption With CLK SYN Disabled With CLK SYN Enabled Standby5 Power-Down OPERATING TEMPERATURE RANGE Min 2.94 Unit 80 MHz mA mA GHz 3.2 16 Maximum BW applies to higher FIF FADC, FIF, and BW dependent Depends on FADC, FIF, and BW Regions of FADC FIF 2.0 70 0.005 x FADC dB dB dB 1/FADC 1.1 2.5 -2.0 1.1275 2.5625 V V V 1.0725 1.0725 1.7 1.1 1.1 1.8 1.1275 1.1275 2.5625 V V V 368 57 93 145 141 164 0.4 397 68 106 165 208 190 1 mA mA mA mA mA mA mA 1.16 1.20 0.44 66 1.31 1.34 W W W mW C CLK synthesizer disabled CLK synthesizer enabled Full Full -40 1 Bits GHz MHz 1.0725 2.4375 Use on-chip regulator, tie to VSS2OUT Full Full Full 3.2 450 0.05 x FADC 1.0 0.5 51 12, 16, 24, 32 FADC/3072 FADC/4096 52 Decimate by 12 or 24 Decimate by 16 or 32 Relative to ADC clock cycles Full Full Full Full Full Full Full Full Full Full Max 0.1 6.4 Full Full Typ 10 Full Full Full NCO Tuning Resolution Out-of-Range Recovery Time POWER SUPPLY AND CONSUMPTION Analog Supply Voltage VDD1, VDDL, VDDQ, VDDC VDD2, VDD2NV VSS2IN Test Conditions/Comments 177 +85 Extrapolated input power level is measured at the center of IF pass band that results in a 0 dBFS power level. The overload level of the - ADC for a CW tone is guaranteed up to -2 dBFS back off from full scale but typically exceeds -1 dBFS. Input signals that have a higher peak-to-average ratio (PAR) than a CW tone (PAR = 3 dB) must apply additional back off based on the difference in PAR. 3 The clock synthesizer reference divider (Register 0x2BB, Bits[7:6]) must be set to divide by 4 or by 2 to ensure that its phase detector frequency remains 40 MHz. 4 fCLK = 200 MHz, FADC = 3.2 GHz. 5 The AD6676 is configured for recovery time of 11.5 s with VSS2 generator/ digital data in standby (Register 0x150 = 0x40) and low power ADC state (Register 0x250 = 0x95). 2 Rev. D | Page 6 of 90 Data Sheet AD6676 DIGITAL HIGH SPEED SERDES SPECIFICATIONS VDD1 = VDDL = VDDC = VDDQ = 1.1 V, VDDD = VDDHSI = 1.1 V, VDD2 = 2.5 V, VDDIO = 1.8 V, unless otherwise noted. Table 2. Parameter HIGH SPEED SERIAL INPUT/OUTPUT Line Rate Dual Lane Data Output Period or Unit Interval Single Lane Data Output Period or Unit Interval Data Output Duty Cycle Data Valid Time PLL Lock Time Wake-Up Time (Standby) Wake-Up Time (Power-Down) Pipeline Delay (Latency) Deterministic Jitter Random Jitter at 5.333 Gbps Output Rise/Fall Time SYNCINB Falling Edge to First K.28 Characters CGS Phase K.28 Characters Duration DIGITAL OUTPUTS (SERDOUT0, SERDOUT1) Logic Compliance Differential Output Voltage Output Offset Voltage, ANSI Mode Differential Termination Impedance SYSREF INPUT (SYSREF) Logic Compliance Differential Input Voltage Differential Input Impedance2 Input Common-Mode Voltage SYNCIN INPUT (SYNCINB+, SYNCINB-) Logic Compliance3 CMOS Input Voltage High CMOS Input Voltage Low LVDS Differential Input Voltage LVDS Differential Input Impedance LVDS Input Common-Mode Voltage LVDS Input Common-Mode Impedance SYSREF (SYSREF) TIMING REQUIREMENTS4 Clock Synthesizer Disabled Setup Time Hold Time Clock Synthesizer Enabled Setup Time Hold Time Symbol Temp. UI UI Full Full 25C 25C 25C 25C 25C Full 25C 25C 25C 25C 25C Min Typ 1.6668 VOD VOS Full Full Full 25C Full 25C Max Unit 5.333 Gbps sec sec % UI s s ms 1/fDATA_IQ1 ps ps rms ps Multiframes Multiframes 750 1.05 mV p-p V 1.8 V p-p k||pF V 1/(20 x fDATA_IQ)1 1/(40 x fDATA_IQ)1 50 0.78 4 5 2.5 32.3 9 0.7 45 4 1 CML 360 0.75 0.6 0.8 VDDHSI/2 100 LVDS/PECL 1.2 35/2 0.85 2.0 25C CMOS/LVDS 0.65 x VDDIO 0.35 x VDDIO 1.2 100||1 0.85 1||1 tSU_SR tH_SR 25C 25C 0.16 0.84 ns ns tSU_SR tH_SR 25C 25C 0.5 0.5 ns ns VIH VIL Full 25C 0.6 0.8 1 1.8 2.0 V V V p-p ||pF V k||pF FDATA_IQ corresponds to the complex output data rate (that is, FADC/DEC_FACTOR). Latency specification also includes ADC and digital filters delays. See Table 15 The SYSREF input requires an external differential resistor for proper termination. 3 Set via Register 0x1E7, Bit 2, with CMOS being the default setting. 4 SYSREF setup and hold times are defined with respect to the rising SYSREF edge and rising clock edge. Positive setup time leads the clock edge. Positive hold time also lags the clock rising edge. Note that the hold time takes into consideration that the internal clock signal used to sample SYSREF operates at FADC/2; thus, SYSREF must remain high for at least two FADC clock cycles. 2 Rev. D | Page 7 of 90 AD6676 Data Sheet CLK TO SYSREF TIMING DIAGRAM CLK- CLK+ tSU_SR tH_SR 12348-102 SYSREF- SYSREF+ Figure 2. SERDES CLK+ to SYSREF+ Timing DIGITAL CMOS INPUT/OUTPUT SPECIFICATIONS VDD1 = VDDL = VDDC = VDDQ = VDDD = VDDHSI = 1.1 V, VDD2 = 2.5 V, VDDIO = 1.8 V, unless otherwise noted. Table 3. Parameter CMOS INPUT/OUTPUT LEVELS Input Voltage High Input Voltage Low Output Voltage High SDIO/SDO AGCx Output Voltage Low SDIO/SDO AGCx Input Capacitance SPI TIMING SCLK Frequency SCLK Period SCLK Pulse Width High SCLK Pulse Width Low SDIO Setup Time SDIO Hold Time SPI_RESET Setup Time1 SCLK Falling Edge to SDO Valid Propagation Delay CSB Rising Edge to SDIO High-Z CSB Fall to SCLK Rise Setup Time SCLK Fall to CSB Rise Hold Time 1 Symbol Test Conditions/Comments VIH VIL VOH Min Typ Max Unit VDDIO x 0.35 V V VDDIO x 0.65 IOH = 3 mA IOH = 0.5 mA VDDIO x 0.7 VDDIO x 0.7 V V VOL VOL IOL = 3 mA IOL = 0.5 mA 0.4 0.4 V V pF 25 10 MHz ns ns ns ns ns ms ns 10 2 2 ns ns ns 1 See Figure 148, Figure 149, and Figure 150 fSCLK tSCLK tHIGH tLOW tDS tDH tSPI_RST tACCESS 40 10 10 2 2 Not shown in Figure 148 to Figure 150 tZ tS tH This is the time required after a software or hardware reset until SPI access is available again. Rev. D | Page 8 of 90 2 Data Sheet AD6676 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 4. Parameter VDD1, VDDC, VDDL, VDDQ to VSSA VDD2 to VSSA VDD2NV to VSSA VSS2IN, VSS2OUT to VSSA VDDD, VDDHSI to VSSD VDDIO to VSSD VIN+, VIN- to VSSA L+, L- to VSSA CLK+, CLK- to VSSA SYSREF+, SYSREF-, SERDOUT0+, SERDOUT0-, SERDOUT1+, SERDOUT1- to VSSD SYNCINB+, SYNCINB- to VSSD CSB, SDO, SDIO, SCLK, RESETB, AGC1, AGC2, AGC3, AGC4 to VSSD Normal Operating Temperature Range Maximum Junction Temperature Under Bias Storage Temperature Range Rating -0.2 V to +1.2 V -0.3 V to +3.0 V -0.3 V to +3.0 V -2.5 V to +0.3 V -0.2 V to +1.2 V -0.3 V to +3.0 V -0.3 V to VDD2 + 0.3 V -0.3 V to VDD2 + 0.3 V -0.3 V to VDDC + 0.3 V -0.3 V to VDDHSI + 0.3 V Typical JA is specified for a 4-layer printed circuit board (PCB) with a solid ground plane in conformance to JESD51-9 2s2p. In addition, metal in direct contact with the package leads from metal traces, through holes, ground, and power planes reduces the value of JA. Table 5. Thermal Resistance Package Type 4.3 mm x 5.0 mm WLCSP ESD CAUTION -0.3 V to VDDIO + 0.3 V -0.3 V to VDDIO + 0.3 V -40C to +85C 125C -65C to +150C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. D | Page 9 of 90 JA 26 JC 0.2 JB 4.5 Unit C/W AD6676 Data Sheet 1 2 3 4 5 6 7 8 A VDDQ VDD1 VSSA VDD1 VDD2 L+ L- VSSA B CLK+ VDD1 VDD1 VSSA VDD1 VDD2 VDD2 VIN+ C CLK- VDDC VDD1 VDD1 VSSA VDD1 VSSA VIN- D VDDC VDDC VDD1 VDDL VDDL VSSA VDD1 VSSA E VSSA VSSA VSSA VSSA VSSA VSSA VDD2 VDD2 F VSSA VSSA VSSA VSSD VSSD VSS2IN VDD2NV VSSA G SYSREF+ VSSD VSSD VSSD VSSD RESETB VSS2OUT VDDIO H SYSREF- VSSD VDDD VDDD VDDD SDO AGC4 AGC2 J VDDHSI VDDHSI VDDD VDDD VDDD CSB AGC3 AGC1 K SERDOUT0- SERDOUT0+ SERDOUT1- SERDOUT1+ SYNCINB+ SYNCINB- SCLK SDIO 1.1V ANALOG SUPPLY ANALOG SUPPLY GROUND 1.1V DIGITAL SUPPLY 2.5V ANALOG SUPPLY DIGITAL SUPPLY GROUND -2V ANALOG SUPPLY 1.8V TO 2.5V DIGITAL I/O ANALOG SUPPLY JESD204B INTERFACE AGC I/O SPI INTERFACE ADC I/O 12348-003 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 3. Pin Configuration (Top View, Not to Scale) Table 6. Pin Function Descriptions Pin No. - ADC Modulator B8, C8 A6, A7 B1, C1 Mnemonic Description VIN+, VIN- L+, L- CLK+, CLK- Analog Inputs with Nominal 60 Differential Input Termination. Analog Outputs for External Inductor. Clock Inputs, Nominal 100 Differential Input Termination When the Clock Synthesizer is Disabled. When the clock synthesizer is enabled, each input is 1.2 k; therefore, an external, 100 differential termination is recommended if the clock source is LVDS or PECL. For a CMOS source driving a long trace, the addition of a series 33 resistor next to the source reduces overshoot seen at CLK+ input pin. JESD204B Interface K1, K2 K3, K4 G1, H1 K5, K6 SERDOUT0-, SERDOUT0+ SERDOUT1-, SERDOUT1+ SYSREF+, SYSREF- SYNCINB+, SYNCINB- Lane 0 JESD204B Digital CML Outputs. Lane 1 JESD204B Digital CML Outputs. JESD204B SYSREF Inputs. Note that these pins have no differential termination. JESD204B CMOS or LVDS SYNC Inputs. Selectable via Register 0x1E7, Bit 2. Default CMOS mode uses the SYNCINB+ pin only. LVDS mode has a 100 differential termination. Rev. D | Page 10 of 90 Data Sheet Pin No. CMOS Input/Outputs J8, H8, J7, H7 J6 K8 H6 K7 G6 Power Supplies G8 J1, J2 H3 to H5, J3 to J5 F4, F5, G2 to G5, H2 A1 C2, D1, D2 D4, D5 A2, A4, B2, B3, B5, C3, C4, C6, D3, D7 A5, B6, B7, E7, E8 A3, A8, B4, C5, C7, D6, D8, E1 to E6, F1 to F3, F8 Negative Voltage Regulator F7 G7 F6 AD6676 Mnemonic Description AGC1, AGC2, AGC3, AGC4 AGC Bidirectional Inputs/Outputs. By default, AGC2 and AGC1 are inputs, whereas AGC4 and AGC3 are outputs. If the AGC2 and AGC1 pins are unused, connect them to VSSD via a 100 k resistor. Serial Port Enable Input. Active low. Serial Port Input/Output. Serial Port Output. Serial Clock Input. Active Low Reset Input. This pin places digital logic and SPI registers into a known default state. Leave this pin open if unused because it has an internal pull-up resistor. CSB SDIO SDO SCLK RESETB VDDIO VDDHSI VDDD VSSD VDDQ VDDC VDDL VDD1 Digital Supply Input for CMOS Input/Outputs (1.8 V to 2.5 V). Digital 1.1 V Supply Input for the High Speed Serial Interface. Digital 1.1 V Supply Input. Digital Supply Return. Analog 1.1 V Supply Input for the CLK Synthesizer Charge Pump and Dividers. Analog 1.1 V Supply Input for the CLK Synthesizer VCO. Analog 1.1 V Supply Input for the ADC. Analog 1.1 V Supply Input for the ADC. VDD2 VSSA Analog 2.5 V Supply Input. Analog Supply Return. VDD2NV VSS2OUT VSS2IN Analog 2.5 V Supply Input. Internal -2.0 V Supply Output. Connect this pin to VSS2IN. Analog -2.0 V Supply Input. Connect this pin to VSS2OUT. Rev. D | Page 11 of 90 AD6676 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS NOMINAL PERFORMANCE FOR IF = 115 MHz (DIRECT SAMPLING VHF RECEIVER) 5 0.25 0 0 -0.25 -0.50 -0.75 -1.00 -1.25 -1.50 80 90 100 110 120 130 140 150 FREQUENCY (MHz) -5 -10 -15 -20 -25 -30 -35 0 50 100 150 200 250 300 350 400 450 500 550 600 FREQUENCY (MHz) Figure 4. IF Pass Band Flatness (Includes Digital Filter) 12348-610 NORMALIZED STF RESPONSE (dBFS) 0.50 12348-607 NORMALIZED STF RESPONSE (dBFS) FIF = 115 MHz, BW = 20 MHz, FADC = 2.4 GHz, attenuator = 0 dB, LEXT = 100 nH, maximum PIN_0dBFS setting, fDATA_IQ = 75 MSPS, nominal supplies, shuffler enabled (every 4 clock cycles), with default threshold settings, unless otherwise noted. Figure 7. Wideband Frequency Response (Before Digital Filter) -153 -153 -154 -154 -155 -155 -156 -156 NSD (dBFS/Hz) NSD (dBFS/Hz) PIN_0dBFS = -2.9dBm -157 -158 -159 -157 SHUFFLE-EVERY-4TH CLOCK -158 -159 -160 -160 -161 -161 SHUFFLER DISABLED 115 120 125 INPUT FREQUENCY (MHz) -163 -44 -41 -38 -35 -32 -29 -26 -23 -20 -17 -14 -11 -8 0 -85 PIN_0dBFS = -2.9dBm -10 -1dBFS AT 108MHz -87 SHUFFLE-EVERY-4TH CLOCK -40 -88 -50 -89 IBN (dBFS) AMPLITUDE (dBFS/NBW) -86 -30 -60 -70 -80 -90 -91 SHUFFLER DISABLED -90 -92 -100 IF PASS BAND REGION -110 -93 NBW = 3.4kHz -94 -120 110 115 INPUT FREQUENCY (MHz) 120 125 -95 -44 -41 -38 -35 -32 -29 -26 -23 -20 -17 -14 -11 -8 12348-609 -130 105 -2 Figure 8. NSD vs. CW Input Power, CW at 108 MHz (NSD Measured at IF Center of 115 MHz) Figure 5. NSD With and Without Full-Scale CW at 108 MHz -20 -5 INPUT POWER (dBm) 12348-611 110 Figure 6. Spectral Plot of IF Pass Band Region with -1 dBFS CW at 108 MHz INPUT POWER (dBm) -5 -2 12348-612 -163 105 -162 NSD (-1dBFS SIGNAL) NSD (NO SIGNAL) 12348-608 -162 Figure 9. Integrated In-Band Noise (IBN) in IF Pass Band Region of 10 MHz vs. Swept Single Tone Input Power with CW at 130 MHz Rev. D | Page 12 of 90 Data Sheet AD6676 0 -100 -30 WORST PASS BAND SPUR (dBFS) -1dBFS AT 101.6MHz -20 AMPLITUDE (dBFS) -1dBFS -6dBFS -12dBFS -18dBFS IF PASS BAND REGION = 20MHz -10 -40 -50 -60 WORST SWEPT SPUR FOR -1dBFS CW AT -3dBm -70 2 x fDATA-IQ CLOCK SPUR AT 150MHz, AT -87dBFS -80 -90 -111dBFS -100 -110 -103 -106 -109 -112 -115 90 100 110 120 130 140 150 INPUT FREQUENCY (MHz) Figure 10. Worst Spur Falling in 75 MHz Pass Band for Swept CW from 77.5 MHz to 152.5 MHz 77.5 0 -10 -20 117.5 127.5 137.5 147.5 152.5 -20 TWO TONES AT -8dBFS (-10.9dBm) AT 114MHz AND 116MHz AMPLITUDE (dBFS/NBW) AMPLITUDE (dBFS/NBW) 107.5 Figure 13. Worst Pass Band Spur with Swept CW from 77.5 MHz to 150 MHz, over PIN = -1 dBFS, -6 dBFS, -12 dBFS, and -18 dBFS 0 -40 97.5 INPUT FREQUENCY (MHz) -10 -30 87.5 12348-616 80 -50 -60 -70 -95dBFS -80 -94dBFS -90 -100 NBW = 3.4kHz -110 TWO TONES AT -8dBFS (-10.9dBm) AT 108MHz AND 110MHz -30 -40 -50 -60 -70 -80 -95dBFS -95dBFS -90 -100 NBW = 3.4kHz -110 -120 -120 110 115 120 125 INPUT FREQUENCY (MHz) -130 105 12348-614 -130 105 110 115 120 125 INPUT FREQUENCY (MHz) Figure 11. Two-Tone IMD Performance (f1 = 114 MHz, f2 = 116 MHz) 12348-617 -130 12348-613 -120 Figure 14. Two-Tone IMD Performance (f1 = 108 MHz, f2 = 110 MHz) -80 -80 -85 -85 WORST IMD3 (dBFS) -95 -100 -105 -110 -115 -8dBFS -90 -95 -20dBFS -100 -14dBFS -120 -105 -130 -39 -36 -33 -30 -27 -24 -21 -18 -15 -12 -9 -6 INPUT AMPLITUDE (dBFS) Figure 12. Swept Two-Tone Worst IMD3 vs. Tone Input Amplitude (f1 = 113 MHz, f2 =118 MHz) -110 110 115 120 125 FREQUENCY (MHz) 130 135 12348-618 -125 12348-615 WORST IMD3 (dBFS) -90 Figure 15. Swept Two Tone Worst IMD3 vs. Frequency over Pass Band (f = 5 MHz for Two Tones, PIN = -8 dBFS, -14 dBFS, and -20 dBFS) Rev. D | Page 13 of 90 AD6676 Data Sheet NOMINAL PERFORMANCE FOR IF = 140 MHz (W POINT-TO-POINT RECEIVERS) FIF = 140 MHz, BW = 56 MHz or 112 MHz, FADC = 3.2 GHz, attenuator = 0 dB, LEXT = 43 nH, maximum PIN_0dBFS setting, fDATA_IQ = 200 MSPS, nominal supplies, shuffler enabled (every clock cycle), with default threshold settings, unless otherwise noted. 0.5 5 -0.5 -1.0 112MHz BW SETTING -1.5 -2.0 80 90 100 110 120 130 140 150 160 170 180 190 200 FREQUENCY (MHz) -15 -20 -25 -30 50 100 150 200 250 300 350 400 450 500 550 600 FREQUENCY (MHz) Figure 19. Wideband Frequency Response (Before Digital Filter) -75 PIN_0dBFS = -2.7dBm -148 -80 CH BW = 56MHz -150 IBN (dBFS) NSD (dBFS/Hz) 56MHz BW SETTING -10 0 BW SETTING OF 112MHz (IBN = -72.2dBFS) BW SETTING OF 56MHz (IBN = -80.5dBFS) -146 -5 -35 Figure 16. IF Pass Band Flatness (Includes Digital Filter) -144 0 12348-622 NORMALIZED STF RESPONSE (dBFS) 0 12348-619 NORMALIZED STF RESPONSE (dBFS) 112MHz BW SETTING 56MHz BW SETTING -152 -154 -85 -156 CH BW = 28MHz CH BW = 14MHz -158 -90 CH BW = 7MHz -160 90 100 110 120 130 140 150 160 170 180 190 200 INPUT FREQUENCY (MHz) -95 -44 -41 -38 -35 -32 -29 -26 -23 -20 -17 -14 -11 -8 12348-620 Figure 17. NSD with No Signal, IBN = 112 MHz and 56 MHz 0 0 -19.7dBm CW INTERFERER TONE AT -22dBFS -10 2.5x CH BW = 35MHZ -20 -20 -30 -30 -40 -40 AMPLITUDE (dBFS) AMPLITUDE (dBFS) -2 Figure 20. IBN vs. Swept Single Tone Input Power over Channel BW = 7 MHz, 14 MHz, 28 MHz, and 56 MHz, CW Blocker at 350 MHz -10 -50 14MHz -60 QAM1024 AT -52dBFS CNR = 36dB -70 -80 -90 IBN = -88dBFS TWO TONES AT -8dBFS (-10.7dBm) AT 137.5MHz AND 142.5MHz -50 -60 -70 -80 -100dBFS -101dBFS -90 -100 -100 -110 -110 -120 60 80 100 120 140 160 180 INPUT FREQUENCY (MHz) 200 220 240 12348-621 NBW = 9.2kHz -120 40 -5 INPUT POWER (dBm) Figure 18. Spectral Plot of CW Interferer Dynamic Range for QAM1024, Channel BW = 14 MHz at Sensitivity Level with CW Interferer 30 dB Higher at 35 MHz Offset Rev. D | Page 14 of 90 NBW = 9.6kHz -130 115 120 125 130 135 140 145 150 155 INPUT FREQUENCY (MHz) Figure 21. Two-Tone IMD Performance (f1 = 137.5 MHz, f2 = 142.5 MHz) 160 165 12348-624 80 12348-623 -162 Data Sheet AD6676 NOMINAL PERFORMANCE FOR IF = 181 MHz (WIRELESS INFRASTRUCTURE RECEIVER) FIF = 181 MHz, BW = 75 MHz, FADC = 2.94912 GHz, attenuator = 0 dB, LEXT = 43 nH, maximum PIN_0dBFS setting, fDATA_IQ = 122.88 MSPS, shuffler enabled (every clock cycle), with default threshold settings, unless otherwise noted. 5 0 -0.25 -0.50 -0.75 -1.00 140 145 150 155 160 165 170 175 180 185 190 195 200 205 210 215 220 FREQUENCY (MHz) -10 -15 -20 -25 -30 50 100 150 200 250 300 350 400 450 500 550 600 FREQUENCY (MHz) -150 -152 -151 -153 -154 PIN_0dBFS = -2.5dBm 216MHz -155 NSD (dBFS) -153 -154 -155 -156 -156 -157 146MHz -158 -159 -157 181MHz -160 -158 NSD (-1dBFS SIGNAL) NSD (NO SIGNAL) 155 165 175 185 195 205 215 INPUT FREQUENCY (MHz) -162 -44 -41 -38 -35 -32 -29 -26 -23 -20 -17 -14 -11 -8 12348-626 0 -75.0 -10 PIN_0dBFS = -2.5dBm -75.5 -1dBFS (-3.5dBm) AT 220MHz -76.0 -30 -76.5 -50 -77.0 IBN (dBFS) -40 -60 -70 -80 -77.5 -78.0 75MHz IF PASS BAND REGION -90 -78.5 -100 -79.0 -110 -79.5 -120 NBW = 5.6kHz 150 160 170 180 190 200 INPUT FREQUENCY (MHz) 210 220 225 -80.0 -44 -41 -38 -35 -32 -29 -26 -23 -20 -17 -14 -11 -8 12348-627 -130 140 -2 Figure 26. NSD vs. CW Input Power, CW = 210 MHz (NSD Measured at 181 MHz as well as 146 MHz and 216 MHz Band Edges) Figure 23. NSD With and Without Full-Scale CW at 210 MHz -20 -5 INPUT POWER (dBm) Figure 24. Spectral Plot of IF Pass Band Region with -1 dBFS CW at 220 MHz INPUT POWER (dBm) -5 -2 12348-630 145 12348-629 -161 -159 -160 0 Figure 25. Wideband Frequency Response (Before Digital Filter) -152 NSD (dBFS/Hz) -5 -35 Figure 22. IF Pass Band Flatness (Includes Digital Filter) AMPLITUDE (dBFS/NBW) 0 12348-628 NORMALIZED STF RESPONSE (dBFS) 0.25 12348-625 NORMALIZED STF RESPONSE (dBFS) 0.50 Figure 27. IBN in IF Pass Band Region (BW = 75 MHz) vs. Swept Single Tone Input Power with CW at 220 MHz Rev. D | Page 15 of 90 AD6676 Data Sheet -94 -1dBFS -6dBFS -12dBFS -18dBFS -30 IF PASS BAND REGION = 75MHz -40 -50 -60 WORST SWEPT PASS BAND SPUR FOR -1dBFS CW AT -3.5dBm -70 -80 -97dBFS -90 -100 -110 -120 NBW = 5.6kHz 125 135 145 155 165 175 185 195 205 215 225 235 INPUT FREQUENCY (MHz) Figure 28. Worst Spur Falling in 75 MHz Pass Band for Swept CW from 122.88 MHz to 245.76 MHz -103 -106 -109 -112 0 -10 AMPLITUDE (dBFS/NBW) -50 -60 -70 -94dBFS -80 -96dBFS -90 -100 -110 185 205 225 245 TWO TONES AT -8dBFS (-10.5dBm) AT 169MHz AND 193MHz -30 -40 -50 -60 -70 -90dBFS -92dBFS -80 -90 -100 -110 -120 -120 NBW = 5.6kHz 145 155 165 175 185 195 205 215 INPUT FREQUENCY (MHz) -130 12348-632 -130 165 -20 TWO TONES AT -8dBFS (-10.5dBm) AT 178.5MHz AND 183.5MHz -40 145 Figure 31. Swept Worst Pass Band Spur with CW Swept from 122.88 MHz to 245.76 MHz, over PIN = -1 dBFS, -6 dBFS, -12 dBFS, and -18 dBFS 0 -30 125 INPUT FREQUENCY (MHz) -10 -20 AMPLITUDE (dBFS/NBW) -100 -115 12348-631 -130 -97 NBW = 5.6kHz 145 155 165 175 185 195 205 215 INPUT FREQUENCY (MHz) Figure 29. Two-Tone IMD Performance (f1 = 178.5 MHz, f2 = 183.5 MHz) 12348-635 AMPLITUDE (dBFS/NBW) -20 WORST PASS BAND SPUR (dBFS) -1dBFS AT 185MHz 12348-634 0 -10 Figure 32. Two-Tone IMD Performance (f1 = 169 MHz, f2 = 193 MHz) -80 -80 -85 -85 WORST IMD3 (dBFS) -95 -100 -105 -110 -115 -20dBFS -90 -95 -8dBFS -100 -105 -14dBFS -120 -125 -130 -39 -36 -33 -30 -27 -24 -21 -18 -15 -12 -9 -6 INPUT AMPLITUDE (dBFS) Figure 30. Swept Two-Tone Worst IMD3 vs. Tone Level (dBFS) (f1 = 178.5 MHz, f2 = 183.5 MHz) -115 140 150 160 170 180 190 200 FREQUENCY (MHz) 210 220 230 12348-636 -110 12348-633 WORST IMD3 (dBFS) -90 Figure 33. Swept Two-Tone Worst IMD3 vs. Frequency over Pass Band (f = 5 MHz for Two Tones, PIN = -8 dBFS, -14 dBFS, and -20 dBFS) Rev. D | Page 16 of 90 Data Sheet AD6676 NOMINAL PERFORMANCE FOR IF = 250 MHz AND BW = 75 MHz FIF = 250 MHz, BW = 75 MHz, FADC = 3.2 GHz, attenuator = 0 dB, LEXT = 19 nH, maximum PIN_0dBFS setting, fDATA_IQ = 200 MSPS, nominal supplies, shuffler enabled (every clock cycle), with default threshold settings, unless otherwise noted. 5 -0.25 220 230 240 250 260 270 280 290 FREQUENCY (MHz) -15 -20 -25 100 200 300 400 500 600 700 Figure 37. Wideband Frequency Response (Before Digital Filter) -150 NSD (-1 dBFS SIGNAL) PIN_0dBFS = -2.3dBm -151 -152 -153 -153 -154 -154 NSD (dBFS) -152 -155 -156 287.5MHz -155 212.5MHz -156 -157 -157 -158 -158 NSD (NO SIGNAL) 220 230 240 250 260 270 280 250MHz -159 290 INPUT FREQUENCY (MHz) -160 -44 -41 -38 -35 -32 -29 -26 -23 -20 -17 -14 -11 -8 12348-638 -159 -160 210 0 FREQUENCY (MHz) -150 NSD (dBFS/Hz) -10 -30 Figure 34. IF Pass Band Flatness (Includes Digital Filter) -151 -5 Figure 35. NSD With and Without Full-Scale CW at 243 MHz -5 -3 INPUT POWER (dBm) 12348-641 -0.50 210 0 12348-640 NORMALIZED STF RESPONSE (dBFS) 0 12348-637 NORMALIZED STF RESPONSE (dBFS) 0.25 Figure 38. NSD vs. CW Input Power, CW at 243 MHz (NSD Measured at 250 MHz as well as 212.5 MHz and 287.5 MHz Band Edges) 0 -75.0 PIN_0dBFS = -2.3dBm -75.5 -1 dBFS AT 288MHz -76.0 -76.5 -40 IBN (dBFS) AMPLITUDE (dBFS/NBW) -20 -60 -80 NBW = 9.2kHz -77.0 -77.5 -78.0 -78.5 IF PASS BAND REGION -79.0 -100 220 230 240 250 260 INPUT FREQUENCY (MHz) 270 280 290 -80.0 -45 -42 -39 -36 -33 -30 -27 -24 -21 -18 -15 -12 -9 12348-639 -120 210 Figure 36. Spectral Plot of IF Pass Band Region with -1 dBFS CW at 288 MHz INPUT POWER (dBm) -6 -3 12348-642 -79.5 Figure 39. IBN in the Pass Band Region (BW = 75 MHz) vs. Swept Single Tone Input Power with CW at 288 MHz Rev. D | Page 17 of 90 AD6676 Data Sheet 0 -80 IF PASS BAND REGION WORST SPUR (dBFS/NBW) WORST SWEPT SPUR FOR -1dBFS CW AT -3.4dBm < -88dBFS -40 -60 WORST PASS BAND SPUR (dBFS) -1dBFS AT 315MHz -20 -79dBFS AT 200MHz CLOCK SPUR -88dBFS -80 -100 -85 -1dBFS -6dBFS -12dBFS -18dBFS -90 -95 -100 -105 -110 170 190 210 230 250 270 290 310 330 350 INPUT FREQUENCY (MHz) -115 150 12348-643 Figure 40. Worst Spur Falling in 75 MHz Pass Band for Swept CW from 150 MHz to 300 MHz 190 210 230 250 270 290 330 350 Figure 43. Swept Worst Pass Band Spur with CW Swept from 150 MHz to 300 MHz for PIN = -1 dBFS, -6 dBFS, -12 dBFS, and -18 dBFS 0 -20 -20 AMPLITUDE (dBFS/NBW) 2 TONE AT -8dBFS (-10.4dBm) AT 247.5MHz AND 252.2MHz -40 -60 -80 -94dBFS -102dBFS 2 TONE AT -8dBFS (-10.4dBm) AT 238MHz AND 262MHz -40 -60 -80 -91dBFS -91dBFS -100 -100 NBW = 9.2kHz 220 230 240 250 260 270 280 NBW = 9.2kHz 290 INPUT FREQUENCY (MHz) -120 210 12348-644 -120 210 310 INPUT FREQUENCY (MHz) 0 WORST SPUR (dBFS/NBW) 170 220 230 240 250 260 270 280 290 INPUT FREQUENCY (MHz) Figure 41. Two-Tone IMD Performance (f1 = 247.5 MHz, f2 = 252.5 MHz) 12348-647 -120 150 12348-646 NBW = 9.2kHz Figure 44. Two-Tone IMD Performance (f1 = 238 MHz, f2 = 262 MHz) -80 -80 -85 -85 WORST IMD3 (dBFS) -95 -100 -105 -110 -115 -120 -90 -20dBFS -95 -100 -8dBFS -105 -14dBFS -130 -39 -36 -33 -30 -27 -24 -21 -18 -15 -12 -9 -6 INPUT AMPLITUDE (dBFS) Figure 42. Swept Two-Tone Worst IMD3 vs. Tone Level (dBFS) (f1 = 252.5 MHz, f2 = 257.5 MHz) -110 210 220 230 240 250 260 270 FREQUENCY (MHz) 280 290 300 12348-648 -125 12348-645 WORST IMD3 (dBFS) -90 Figure 45. Swept Two-Tone Worst IMD3 vs. Frequency over Pass Band (f = 5 MHz for Two Tones, PIN =-8 dBFS, -14 dBFS, and -20 dBFS ) Rev. D | Page 18 of 90 Data Sheet AD6676 NOMINAL PERFORMANCE FOR IF = 350 MHZ AND BW = 160 MHZ FIF = 350 MHz, BW = 160 MHz, FADC = 3.2 GHz, attenuator = 0 dB, LEXT = 10 nH, maximum PIN_0dBFS setting, fDATA_IQ = 266.7 MSPS, shuffler enabled (every clock cycle), with default threshold settings, unless otherwise noted. 0.75 0.50 0.25 0 -0.25 -0.50 270 290 310 330 350 370 390 410 430 FREQUENCY (MHz) 0 -5 -10 -15 -20 -25 -30 -35 0 200 300 400 500 600 700 800 900 1000 FREQUENCY (MHz) Figure 46. IF Pass Band Flatness (Includes Digital Filter) Figure 49. Wideband Frequency Response (Before Digital Filter) -140 -140 NSD (-1 dBFS SIGNAL) -142 100 12348-652 NORMALIZED STF RESPONSE (dBFS) 5 12348-649 NORMALIZED STF RESPONSE (dBFS) 1.00 PIN_0dBFS = -2.3dBm -142 -144 -146 -146 NSD (dBFS) -148 -150 -148 -150 350MHz -152 -152 NSD (NO SIGNAL) -156 270 290 310 330 350 370 390 -154 410 430 INPUT FREQUENCY (MHz) -156 -44 -41 -38 -35 -32 -29 -26 -23 -20 -17 -14 -11 -8 12348-650 -154 Figure 47. NSD With and Without Full-Scale CW at 355 MHz Figure 50. NSD vs. CW Input Power, CW at 355 MHz (NSD Measured at 350 MHz as well as 350 MHz and 400 MHz Band Edges) -60 PIN_0dBFS = -2.3dBm -61 -1 dBFS AT 431MHz -20 -5 -3 INPUT POWER (dBm) 0 -62 -63 -40 IBN (dBFS) AMPLITUDE (dBFS/NBW) 400MHz 12348-653 NSD (dBFS) 310MHz -144 -60 NBW = 12.2kHz -80 -64 -65 -66 -67 IF PASS BAND REGION -68 -100 280 300 320 340 360 380 INPUT FREQUENCY (MHz) 400 420 440 -70 -45 -42 -39 -36 -33 -30 -27 -24 -21 -18 -15 -12 -9 12348-651 -120 260 Figure 48. Spectral Plot of IF Pass Band Region with -1 dBFS CW at 431 MHz INPUT POWER (dBm) -6 -3 12348-654 -69 Figure 51. IBN in IF Pass Band Region (BW = 160 MHz) vs. Swept Single Tone Input Power with CW at 431 MHz Rev. D | Page 19 of 90 AD6676 Data Sheet -80 -40 WORST SWEPT SPUR FOR -1dBFS CW AT -3.3dBm -60 -83dBFS IMAGE SPUR -77dBFS AT 267MHz CLOCK SPUR -80 NBW = 12.2kHz -120 220 240 260 280 300 320 340 360 380 400 420 440 460 480 INPUT FREQUENCY (MHz) Figure 52. Worst Spur Falling in 160 MHz Pass Band for Swept CW from 217 MHz to 484 MHz -95 -100 220 240 260 280 300 320 340 360 380 400 420 440 460 480 INPUT FREQUENCY (MHz) 0 -20 -20 TWO TONE AT -8dBFS (-10.4dBm) AT 340MHz AND 360MHz -40 WORST SPUR (dBFS/NBW) -60 -87dBFS -93dBFS -80 -40 NBW = 12.2kHz 310 330 350 370 390 410 430 -87dBFS -80 -120 270 12348-656 290 INPUT FREQUENCY (MHz) NBW = 12.2kHz 290 310 330 -75 -85 -80 WORST IMD3 (dBFS) -90 -95 -100 -105 -27 -24 -21 -18 -15 -12 -9 -6 410 430 -85 -90 -14dBFS -95 INPUT AMPLITUDE (dBFS) Figure 54. Swept Two-Tone Worst IMD3 vs. Tone Level (dBFS) (f1 = 347.5 MHz, f2 = 352.5 MHz) -105 270 12348-657 -30 390 -20dBFS -100 -110 -33 370 Figure 56. Two-Tone IMD Performance (f1 = 325 MHz, f2 = 375 MHz) -80 -36 350 INPUT FREQUENCY (MHz) Figure 53. Two-Tone IMD Performance (f1 = 340 MHz, f2 = 360 MHz) WORST IMD3 (dBFS) -74dBFS -60 -100 -100 -115 -39 TWO TONE AT -8dBFS (-10.4dBm) AT 325MHz AND 375MHz 12348-659 WORST SPUR (dBFS/NBW) -90 Figure 55. Swept Worst Pass Band Spur with CW Swept from 217 MHz to 484 MHz over PIN = -1 dBFS, -6 dBFS, -12 dBFS, and -18 dBFS 0 -120 270 -85 -105 12348-655 -100 -1dBFS -6dBFS -12dBFS -18dBFS -8dBFS 290 310 330 350 370 FREQUENCY (MHz) 390 410 430 12348-660 WORST SPUR (dBFS/NBW) -20 -1dBFS AT 372MHz WORST PASS BAND SPUR (dBFS) IF PASS BAND REGION 12348-658 0 Figure 57. Swept Two-Tone Worst IMD3 vs. Frequency over Pass Band (f = 5 MHz for Two Tones, PIN =-8 dBFS, -14 dBFS, and -20 dBFS) Rev. D | Page 20 of 90 Data Sheet AD6676 EQUIVALENT CIRCUITS VDDIO VDDIO VDDIO ESD PROTECTED I/O SDIO OR AGCx 1k 12348-017 1k ESD PROTECTED Figure 58. Equivalent CSB or SCLK Input Circuit 12348-015 CSB, SCLK OR SDI Figure 62. Equivalent SDIO or AGCx Input/Output Circuit RIN = 60 VCM = 1.0V VIN+ VDDIO VIN- 25k AC 1k 12348-016 Figure 59. Equivalent Analog Input Figure 63. Equivalent RESETB Input Circuit VDDIO NC VDD1 SYNCINB+ TO CLK SYN CLK+ + CLK- - DGND TO BAND-PASS - ADC 50 VDDIO SYNCINB- Figure 60. Equivalent Clock Input Circuit VCM SYNCINB PIN CONTROL (SPI) Figure 64. Equivalent SYNCINB Input VDDHSI EMPHASIS/SWING CONTROL (SPI) 1k VDDHSI LEVEL TRANSLATOR VDDHSI SERDOUTx+ x = 0, 1 DATA+ OUTPUT DRIVER VCM = 0.55V 10k DATA- VDDHSI SERDOUTx- x = 0, 1 12348-012 1k Figure 61. Equivalent SYSREF Input Figure 65. Digital CML Output Circuit Rev. D | Page 21 of 90 12348-014 10k SYSREF- VCM = 0.85V 20k 1k DGND SYSREF+ 20k LEVEL TRANSLATOR 12348-011 50 1k 12348-013 DC 12348-401 RESETB AD6676 Data Sheet TERMINOLOGY Noise Figure (NF) NF is the degradation in SNR performance (in dB) of an input signal having a noise density of -174 dBm/Hz after it passes through a component or system. Mathematically, NF = 10 x log(SNRIN/SNROUT) The noise figure of the AD6676 is determined by the equation NF = PIN - (10 x log(BW)) - (-174.0 dBm/Hz) - SNR where: PIN is the input power of an unmodulated carrier. BW is the noise measurement bandwidth. -174.0 dBm/Hz is the thermal noise floor at 290 K. SNR is the measured signal-to-noise ratio in dB of the AD6676. Note that PIN is set to a low level (that is, <-40 dBm) to minimize any degradation in measured SNR due to phase noise from either the input signal or - ADC clock source. Noise Spectral Density (NSD) NSD is the noise power normalized to 1 Hz bandwidth (at a particular frequency) relative to the full scale of the ADC (dBFS) and hence is given in units of dBFS/Hz. The AD6676, being a - ADC, displays a uneven NSD across its IF pass band. Both the worst-case NSD as well as NSD at the pass band center are reported. Note that NSD is calculated from the IBN measured over a 5 MHz bandwidth. In-Band Noise (IBN) IBN is the integrated noise power measured over a user defined bandwidth relative to the full scale of the ADC (dBFS). This bandwidth is typically equal to the IF pass band setting (BW) of the AD6676, unless otherwise noted. Input Third-Order Intercept (IIP3) IIP3 is a figure of merit used to quantify the third-order intermodulation distortion (IMD3) of a component or system. Two equal amplitude unmodulated carriers at specified frequencies (f1 and f2) injected into a nonlinear system exhibiting third-order nonlinearities produce IMD components at 2 f1 - f2 and 2 f2 - f1. IIP3 is the extrapolated tone power at which the intermodulation terms and the input tones have equal amplitude. IIP3 = PIN - IMD3/2 Note that the third-order IMD performance of an ADC does not necessarily follow the 3:1 rule that is typical of RF/IF linear devices. IMD performance is dependent on the dual tone frequencies, signal input levels, and ADC clock rate. Worst In-Band Spur (SFDR) Worst in-band spur is the worst spur falling in the IF pass band relative to the full scale of the ADC (dBFS) when a single tone with defined power level is stepped (typically 1 MHz increments) across a user defined frequency range. Note that this worst spur can often be an image (or clock) related spur depending on the IF, BW, and IQ output data rate setting of the AD6676 and on the sweep range. Signal Transfer Function (STF) STF is the frequency response of the output signal of the ADC relative to a swept single tone at its input. The STF presented for different AD6676 setup conditions in the Typical Performance Characteristics section shows the STF over the IF pass band after the digital filter to highlight pass band flatness. The wideband STF response is measured before the digital filter to highlight the pass band response of the AD6676 - ADC. Input Second-Order Intercept (IIP2) IIP2 is a figure of merit used to quantify the second-order intermodulation distortion (IMD2) of a component or system. Two equal amplitude unmodulated carriers at specified frequencies (f1 and f2) injected into a nonlinear system exhibiting second-order nonlinearities produce IMD components at f1 - f2 and f1 + f2. For the AD6676, the two frequencies are situated at 1/2 the IF frequency (with a 2 MHz offset) at a power level corresponding to -6 dBFS at the IF center frequency with only the intermodulation term at f1 + f2 considered. IIP2 is the extrapolated tone power at which the intermodulation terms and the input tones have equal amplitude. IIP2 = PIN - IMD2 Rev. D | Page 22 of 90 Data Sheet AD6676 THEORY OF OPERATION On-chip digital signal processing blocks include a quadrature digital downconverter (QDDC) followed by selectable decimation filters supporting decimation factors of 12, 16, 24, or 32. The QDDC performs a complex shift of the desired IF pass band such that it is centered about dc, that is, zero IF. Cascaded decimation filters remove the inherent out-of-band noise of the ADC along with any other out-of-band signal content such that the 16-bit complex IQ data is reduced to a more manageable data rate for transfer to the host via a single or dual lane JESD204B interface supporting up to 5.333 Gbps lane rates. OVERVIEW The AD6676 is a highly integrated and flexible IF subsystem capable of digitizing IF signals. The ability to tune the IF frequency and bandwidth allows the - ADC to be optimized for different applications while trading off bandwidth for dynamic range. To facilitate its evaluation and design in, a software tool that is part of the AD6676EBZ development platform must be used to configure and evaluate the device. This tool saves the SPI initialization and configuration sequence to a file for later use. A screenshot of the GUI front panel (see Figure 66) shows the different user specified application parameters that configure the AD6676. The following discussion provides more insight into the device operation and how these application parameters affect performance. 12348-018 The AD6676 also includes features for AGC support and/or levelplanning optimization. AGC support includes the ability to monitor peak power at the - ADC output or rms power after the first internal decimation stage. The host can initiate fast AGC action by configuring various flags whose status are made available on the AGC4 to AGC1 pins. Flags can be set with programmable thresholds indicating whether the signal level is above or below a defined level. A 27 dB attenuator with a step size of 1 dB is available for IF AGC control or level planning optimization during initial system calibration. Alternatively, the nominal 0 dBFS full-scale input power level (PIN_0dBFS) of -2 dBm can be reduced by up to 12 dB thus further reducing the RF/IF gain requirements. The SPI programs numerous parameters of the AD6676, allowing the device to be optimized for a variety of applications. Figure 66. Screenshot of AD6676 GUI Software Tool that Facilitates Device Configuration and Evaluation A functional block diagram of the AD6676 is shown Figure 67. The focal point of the AD6676 is its continuous time, band-pass - ADC that operates with a clock rate between 2.0 GHz and 3.2 GHz. An on-chip controller configures the - ADC based on the user specified application parameters. The - ADC provides exceptional dynamic range and pass band flatness within the desired IF span while limiting out-of-band peaking to less than 0.5 dB. An on-chip clock synthesizer supplies a 2.94 GHz to 3.2 GHz - ADC clock. Alternatively, an external clock can be supplied for lower clock rates or improved phase noise performance. VSS2IN VSS2OUT VDD2NV AGC4, AGC3 AGC2, AGC1 VDDIO RESETB -2.0V REG VIN+ BAND-PASS - ADC VIN- SCLK SDIO SDO VDDHSI QDDC + NCO I I Mx Q L+ L- CLOCK GENERATION CLOCK SYNTHESIZER SPI M = 12, 16, 24, 32 Q JESD204B SERIALIZER Tx OUTPUTS 27dB ATTENUATOR (1dB STEPS) CSB AGC SUPPORT JESD204B SUBCLASS 1 CONTROL SERDOUT0+ SERDOUT0- SERDOUT1+ SERDOUT1- SYNCINB SYSREF VDDQ VDDC CLK+ CLK- VDD2 VDDL VDD1 VSSA Figure 67. Functional Block Diagram Rev. D | Page 23 of 90 VDDD VSSD 12348-400 AD6676 AD6676 Data Sheet G53 RESON1 CARRAY RESON2 C3 LEXT AV C4 C5 G43 -G56 G54 C6 G65 17-LEVEL FLASH ADC 17 ENCODER 5 DOUT 17 12348-020 IDAC6 IDAC5 IDAC4 IDAC1FS ADJUST IDAC3 RIN IDAC1 VIN G31 -G34 RESON3 OPTIONAL SHUFFLER Figure 68. Simplified Single-Ended Representation of the Band-Pass - ADC Modulator BAND-PASS - ADC ARCHITECTURE Figure 68 shows a simplified single-ended representation of the AD6676 band-pass - ADC. It is a sixth-order modulator consisting of three cascaded second-order continuous-time resonators with feedback DACs and an oversampling quantizer. The first resonator (RESON1) is based on a LC tank with its resonant frequency tuned via CARRAY to the IF center while the second and third resonators (RESON2 and RESON3) are active RC-based with their resonant frequencies tuned to frequencies offset symmetrically about the IF. These resonant frequencies correspond to the zero locations of the - ADC quantization noise and are set according to the user defined IF frequency and bandwidth. A 17-level flash ADC oversamples the analog output of RESON3 with the digital output of the flash ADC feeding back to each of the resonators via current mode DACs (IDACx). Note that because the ADC thermometer code output can range from -8 to +8, it is represented by five bits that are passed to the AD6676 digital path. The IDAC1 full-scale current setting (IDAC1FS) sets the maximum full-scale input power level (PIN_0DBFS). The full-scale settings of the other IDACs set the pole location of the modulator to achieve a flat pass band response. Lastly, a programmable shuffler follows the flash ADC to improve the linearity performance of the AD6676 under large signal conditions. The tunable nature of the - ADC is a result of the full-scale current of the feedback DACs, as well as the conductances (G) and capacitances (C) associated with each resonator. The value of these programmable components are calculated from the user specified application parameters listed in Table 7. The impact of each of these parameters on the performance of the AD6676 is described in subsequent sections. Table 7. List of User Specified Application Parameters That Determine the - ADC Internal Settings Application Parameter FIF BW FADC LEXT MRGN IDAC1FS Description IF center frequency in MHz IF pass band bandwidth in MHz - ADC clock rate in MHz External inductor value in nH Margin offset to set resonator frequency in MHz Full-scale current of IDAC1 that sets PIN_0dBFS level SPI Register(s) 0x102, 0x103 0x104, 0x105 0x100, 0x101 0x106 0x107 to 0x109 0x10A The on-chip controller is used only during device initialization and performs the following tasks: Power-up negative regulator (used by IDACs) Calibrate RESON1 and 17-level flash ADC Tune - ADC based on user input parameters Set up PLL used by JESD204B PHY After device initialization, the on-chip controller is disabled; it is not used during normal device operation. Signal and Noise Transfer Functions The frequency domain response of a - ADC is defined by its signal and noise transfer functions (STF and NTF). Figure 69 shows a simplified feedback model of a - modulator with the ADC quantization error modeled as an additive noise source (E) after the loop filter (H). The STF is the frequency response of the output signal (V) relative to a swept single tone at its input (U) while the NTF is the frequency response of the ADC quantization noise (that is, V/E) that undergoes noise shaping due to of the loop filter of the ADC. Note that the ADC and DACs within the feedback loop operate at a much higher clock rate than a traditional open-loop ADC in which only the Nyquist criterion must be satisfied (FADC = 2 x BW). The oversampling ratio (OSR) is a key parameter of any - ADC and is defined as follows: OSR = FADC/(2 x BW) Rev. D | Page 24 of 90 (1) Data Sheet -60 ADC NBW = 146.5kHz V - NOISE (dBFS/NBW) DAC E U -120 -70 + H(z) V - ADC -80 -130 OBSERVED NSD -140 -90 THEORETICAL NSD FROM ADC QUANTIZATION -100 -160 -110 DAC -120 H(z) 1 U(z) + E(z) 1 + H(z) 1 + H(z) STF NTF -130 100 In the case of the AD6676, the loop filter consists of three cascaded resonators to implement a sixth-order band-pass response, thus allowing the oversampling ratio of the AD6676 to be kept to moderate levels (10) such that useable bandwidths of up to 160 MHz can be realized. The loop filter utilizes a feedback architecture so that the STF has minimal out-of-band gain peaking while the NTF suppresses the in-band quantization noise. Figure 70 shows an example of the STF and the shaped noise of the - ADC when it is configured for BW = 80 MHz, FIF = 300 MHz, and FADC = 3.2 GHz. Note that the NSD near FIF is much lower than the NSD elsewhere and that the STF is quite broadband. NBW = 146.5kHz NOISE (dBFS/NBW) -40 -60 NTF SHAPED NOISE -80 -100 400 600 800 1000 1200 1400 1600 FREQUENCY (MHz) 12348-022 NSD = -161.5dBFS/Hz 200 200 250 300 -180 350 400 450 500 Unlike conventional ADCs, the NSD of a - ADC is not flat due to its frequency dependent loop filter, H(s), which shapes the quantization noise as well as various other noise sources. Because the - ADC is highly programmable, its NSD can be optimized for the user specified application parameter settings. In general, the NSD performance varies based on the application parameter settings in the following ways: STF 0 150 Figure 71. Measured vs. Ideal NTF (FIF = 300 MHz, BW = 80 MHz, FADC = 3.2 GHz, LEXT = 19 nH) 0 -120 -170 RESON3 FREQUENCY (MHz) Figure 69. Simplified Model of a - ADC Showing Origins of STF and NTF -20 RESON2 RESON1 12348-021 V(z) = -150 (dBFS/Hz) LOOP FILTER H(s) + 12348-023 U AD6676 Figure 70. STF and NTF Shaped Noise of the - ADC (FIF = 300 MHz, BW = 80 MHz, FADC = 3.2 GHz, LEXT = 19 nH) Figure 71 focuses on the IF pass band region to compare the measured vs. ideal shaped noise with the theoretical NSD curve accounting only for the ideal ADC quantization effect. The resonator zero locations are highlighted on the theoretical trace and are recognizable in the measured response. Note that the region with the lowest NSD performance or the deepest notch is always centered about the FIF setting. This is because the gain of RESON1 peaks at FIF and the noise from stages which follow RESON1 is input referred by dividing by the gain of RESON1. Rev. D | Page 25 of 90 Operating with a high oversampling ratio (OSR > 20) results in the lowest and flattest NSD performance. This is because the resonant frequencies (or zero locations) associated with RESON1, RESON2, and RESON3 are close together when the oversampling ratio is high thereby reducing the quantization noise to the point where thermal noise from the first stage IDAC1 dominates. Operating at reduced oversampling ratio (oversampling ratio < 20) causes the quantization noise contribution to become more significant, causing humps to appear in the NSD. Bumpiness in the NSD occurs because the resonant frequencies associated RESON2 and RESON3 are further offset from RESON1 to accommodate the increase in BW; therefore, resulting in less overall loop gain to suppress this increasingly dominant noise source. The effect of different oversampling ratios on the NSD is shown in Figure 72. Operating at a lower FIF while keeping the same oversampling ratio results in degraded NSD performance at the pass band edges, as shown in Figure 73. AD6676 Data Sheet STF and NTF Repeatability -130 OSR = 10 (BW = 160MHz) OSR = 20 (BW = 80MHz) OSR = 40 (BW = 40MHz) OSR = 80 (BW = 20MHz) -140 -145 -150 -160 200 220 240 260 280 300 320 340 360 380 400 FREQUENCY (MHz) 12348-024 -155 Figure 72. NSD vs. Oversampling Ratio (FIF = 300 MHz, FADC = 3.2 GHz, LEXT = 19 nH) -140 -142 -144 -148 The following application parameters were used to demonstrate STF and NTF repeatability: fCLK = 3.2 GHz, FIF = 250 MHz, BW = 75 MHz, LEXT = 19 nH, IDAC1FS = 4 mA, MRGN = default. Figure 74 and Figure 75 demonstrate the repeatability and temperature stability of the STF and NTF responses of single devices for five consecutive power-up initialization operations in which the device is calibrated at 25C and then allowed to drift to -40C and +85C. -150 0.2 -152 -154 -160 -100 IF = 100MHz WITH LEXT = 100nH IF = 200MHz WITH LEXT = 43nH -80 -60 -40 IF = 300MHz WITH LEXT = 19nH -20 0 20 40 60 NORMALIZED ZERO IF FREQUENCY (MHz) 80 100 12348-025 -158 Figure 73. NSD at Pass Band Edge Improvement as FIF Is Increased from 100 MHz to 300 MHz with Fixed Oversampling Ratio = 16 (BW = 100 MHz, FADC = 3.2 GHz) NORMALIZED STF (dBFS) 0 -156 -0.2 -0.4 -0.6 -0.8 -1.0 200 TA = +85C TA = +25C TA = -40C 210 220 230 240 250 260 270 280 290 300 FREQUENCY (MHz) Figure 74. STF Variation over Temperature for a Single Device for Five Consecutive Power-Up Initialization Operations -146 TA = +85C TA = +25C TA = -40C -148 -150 NSD (dBFS) The impact of a uneven NSD profile on a particular application depends on the bandwidth and modulation characteristics of the IF signal being digitized and demodulated. For example, a multimode software defined radio containing narrow-band carriers situated anywhere across the pass band must consider the NSD performance at the highest levels across the pass band because this represents the worst-case NSD when calculating the in-band noise for a narrow-band signal in this region. Conversely, a single wideband QAM signal falling at the center of the IF pass band benefits from excellent in-band noise performance because the NSD remains the lowest in this region. Note that the AD6676 specified NF is measured in the region where its NSD is highest. 12348-700 NOISE (dBFS/Hz) -146 After the application parameters have been determined, the STF and NTF characteristics of the AD6676 remain repeatable and stable over temperature and among devices. The on-chip calibration performed during the power-up initialization phase reduces the device-to-device variation that may otherwise exist due to tolerances associated with the device process or the external inductor, LEXT. It is worth noting that that the small variation in STF and NTF that does exist is likely to be less than traditional receiver solutions employing low oversampling ADCs with aggressive high order LC antialiasing filters. L and C component tolerances as well as variation in active device source and load impedances must be considered in the Monte Carlo analysis. -152 -154 -156 -158 -160 200 210 220 230 240 250 260 FREQUENCY (MHz) 270 280 290 300 12348-701 NOISE (dBFS/Hz) -135 Figure 75. NTF Variation over Temperature for a Single Device for Five Consecutive Power-Up Initialization Operations Rev. D | Page 26 of 90 Data Sheet AD6676 Figure 76 to Figure 79 show the measured overload recovery response for each of the decimation filter modes (DEC_MODE) when driven by a periodic pulsed CW waveform of 10 ns duration and 2% duty cycle. The narrow pulse region of the waveform was set to be only 1 dB higher than the other region with its peak power adjusted slightly above the overload threshold level resulting in an occasional overload event. The AD6676 was configured for FIF = 300 MHz, BW = 100 MHz, and FADC = 3.2 GHz. The absolute settling response for any decimation factor scales with fDATA_IQ. For example, the settling time shown in Figure 77 is an additional seven samples at fDATA_IQ = 200 MSPS, thus the absolute settling time is 35 ns (7 x 1/200 MSPS). Selecting a decimation factor of 12 or 16 improves the absolute settling time because it reduces the additive delay caused by the last stage decimation filter. LARGE SCALE SETTLING 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 NO OVERLOAD/ RECOVERY OVERLOAD/ RECOVERY 1.05 1.04 1.03 1.02 1.01 1.00 0.99 0.98 0.97 0.96 0.95 95 ZOOM-IN OF LARGE SCALE SETTLING RESPONSE FOR 1% SETTLING 7 SAMPLES @ 266.7MSPS 97 99 101 103 105 107 109 111 113 115 SAMPLES 12348-030 Second, to ensure that the ADC does not become stuck in a self sustaining overload condition, the AD6676 includes the means to detect overload, reset the - ADC, and quickly return it to normal operation. An overload condition is declared if more than five out of eight samples from the quantizer are equal to a positive or negative full-scale value. After overload is detected, the internal nodes within the - ADC are reset to their zero state and the attenuation setting is temporarily increased by 6 dB. The ADC reset is removed after 16 FADC clock cycles and over the next 48 FADC clock cycles, the attenuation is returned to its original value. If the input signal is such that an overload occurs again, this process repeats until the signal falls within the no overload range of the - ADC. Although the - ADC produces good data within 64 FADC clock cycles of the signal falling within the no overload range, the bad data associated with an overload event must be flushed out of the decimation filters before the output of the AD6676 is completely clean of any memory effects. Figure 76. Comparison of Normalized IQ Magnitude Response for Decimate by 12 Case When a Pulsed CW Waveform (10 ns Width) Is Just Below and Above Peak Power Level, Resulting in ADC Overload LARGE SCALE SETTLING 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 NO OVERLOAD/ RECOVERY OVERLOAD/ RECOVERY ZOOM-IN OF LARGE SCALE SETTLING RESPONSE FOR 1% SETTLING 1.08 1.07 1.06 1.05 1.04 1.03 1.02 1.01 1.00 0.99 0.98 7 SAMPLES @ 200MSPS 0 2 4 6 8 10 SAMPLES 12 14 16 18 20 12348-031 First, to make the no overload range with continuous wave tones approach levels near 0 dBFS, the AD6676 uses a 5-bit quantizer. The AD6676 is specified to remain unconditionally stable for continuous wave levels below -2 dBFS over its full operation range, with a typical overload level of -0.5 dBFS. In practice, the large signal waveform characteristics that determine the occurrence and duration of its peaks affect the overload threshold. A continuous wave tone is close to the worst-case scenario for overload because the peak levels have the highest probability of occurrence. Alternatively, a signal that has a much higher crest factor and a more Gaussian-like histogram is less likely to cause overload due to the short duration of its peak excursions. For this reason, for systems employing AGC, consider the waveform characteristics when setting the AGC threshold. Note the following: NORMALIZED IQ MAGNITUDE RESPONSE The - ADC is a sixth-order modulator employing negative feedback to reduce the noise contribution of its internal quantizer. Like any ADC, the quantizer is driven into overload under large signal conditions, causing its output to be a poor representation of its input. However, unlike traditional ADCs that operate in open-loop, a - ADC can be driven into overload with signals slightly below its 0 dBFS full-scale input level and the feedback loop can become unstable and may not return to normal operation when the overload condition is removed. A typical unstable - ADC produces a digital output that varies between plus or minus full scale. The AD6676 employs several techniques to solve these problems. Each plot compares the envelope response between a pulse that results in an overload event to a pulse where the - ADC remains stable and includes a zoom in region showing settling time to within 1% following the large scale settling plot. Because the phase response recovers two to three samples before the envelope response, the phase response is not shown. NORMALIZED IQ MAGNITUDE RESPONSE - ADC Overload and Recovery Figure 77. Comparison of Normalized IQ Magnitude Response for Decimate by 16 Case When a Pulsed CW Waveform (10 ns Width) Is Just Below and Above Peak Power Level, Resulting in ADC Overload Rev. D | Page 27 of 90 AD6676 Data Sheet 1.07 1.06 1.05 1.04 1.03 1.02 1.01 1.00 0.99 0.98 0.97 0.96 0.95 Ultimately, the maximum feedback signal current that can be generated by IDAC1 is limited by its full-scale setting, IDAC1FS, thus setting the 0 dBFS level on which feedback can no longer cancel any further increase in input signal level (or power). For example, the AD6676 nominal setting for IDAC1FS at 4 mA equates to a PIN_0dBFS of -3 dBm, resulting in a differential voltage swing of 240 mV peak. NO OVERLOAD/ RECOVERY OVERLOAD/ RECOVERY ZOOM-IN OF LARGE SCALE SETTLING RESPONSE FOR 1% SETTLING 6 SAMPLES @ 266.7MSPS 0 2 4 6 8 10 Equation 2 assumes that the attenuator setting is 0 dB. Any setting beyond 0 dB increases the effective PIN_0dBFS measured at the input of the attenuator by an amount equal to the attenuator setting. 12 14 16 18 20 SAMPLES 12348-032 NORMALIZED IQ MAGNITUDE RESPONSE LARGE SCALE SETTLING 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 LARGE SCALE SETTLING 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 The range of permissible values for LEXT depends on the following application parameters: FIF, FADC, and IDAC1FS. Figure 80 shows the upper and lower settings (LMAX and LMIN) when IDAC1FS is set to its default settings of 4 mA. Note that the LMAX limit is set by the largest voltage swing across the LC tank and the LMIN limit is set by the maximum tuning capacitance available from an internal capacitor array. NO OVERLOAD/ RECOVERY OVERLOAD/ RECOVERY ZOOM-IN OF LARGE SCALE SETTLING RESPONSE FOR 1% SETTLING 200 ABSOLUTE MAXIMUM MAXIMUM FOR FADC = 3.2GHz MAXIMUM FOR FADC = 2.6GHz MAXIMUM FOR FADC = 2.0GHz MINIMUM 5 SAMPLES @ 100MSPS 100 0 2 4 6 8 10 12 14 16 18 20 SAMPLES LEXT (nH) 1.08 1.07 1.06 1.05 1.04 1.03 1.02 1.01 1.00 0.99 0.98 LEXT Selection 12348-033 NORMALIZED IQ MAGNITUDE RESPONSE Figure 78. Comparison of Normalized IQ Magnitude Response for Decimate by 24 Case When a Pulsed CW Waveform (10 ns Width) Is Just Below and Above Peak Power Level, Resulting in ADC Overload In practice, the actual measured PIN_0dBFS may vary a few tenths of a decibel for different application parameter settings due to some amount of pass band tilt. For this reason, PIN_0dBFS is defined at the IF center. 20 Figure 79. Comparison of Normalized IQ Magnitude Response for Decimate by 32 Case When a Pulsed CW Waveform (10 ns Width) Is Just Below and Above Peak Power Level, Resulting in ADC Overload 15 10 Maximum Input Power (PIN_0dBFS and IDAC1FS) 5 The AD6676 maximum full-scale input power (PIN_0dBFS) for a sinusoidal input signal is dependent on the IDAC1 peak fullscale output current (IDAC1FS) and the RIN of the attenuator (that is, 60 ) as shown in the equation below. PIN_0dBFS = 10 x log10(1/2 x RIN x IDAC1FS2) (2) The derivation of this equation becomes apparent when considering the AD6676 input stage consisting of RESON1, IDAC1, and RIN, as shown in Figure 68. RIN is the input resistance of the attenuator. The cascode transistor associated with IDAC1 and RIN establishes a low impedance node serving as a current mode summing junction whereby the input signal (equal to VIN/RIN) is compared to the feedback signal from IDAC1. Note that the feedback loop of the - modulator attempts to generate an equal but opposite feedback current to cancel the signal current appearing at this summing junction. 0 50 100 150 200 250 300 350 FIF (MHz) 400 450 500 12348-034 - ADC CONFIGURATION CONSIDERATIONS Figure 80. Maximum External Inductor Value as a Function of IF Frequency and Clock Rate for IDAC1FS = 4 mA Note the following points when selecting LEXT: Rev. D | Page 28 of 90 Larger values of LEXT result in larger voltage swings across the LC tank. Selecting a value that is approximately 55% to 80% of the LMAX value can be considered with a lower value, typically resulting in improved IMD performance due to reduced voltage swing across the inductor. Conversely, a higher value may lead to a slight improvement in noise performance (mostly near the IF center), but at the expense of IMD performance. Inductor accuracy of 10% is sufficient because it falls well within the calibration range of the AD6676 during its initialization phase on power-up. Data Sheet -145 IDAC1 FS = 1mA, LEXT = 39nH (IBN = -67.9dBFS) IDAC1 FS = 2mA, LEXT = 39nH (IBN = -72.5dBFS) The following example highlights how LEXT can be determined with the following application parameters: FIF = 150 MHz, FADC = 3.0 GHz and IDAC1FS = 4 mA. Referring to Figure 80, the LMAX and LMIN range is from 20 nH to 70 nH. A value of 43 nH represents 61% of LMAX and thus is suitable. Note that if the IDAC1FS is reduced to 2 mA, this value can be increased to 86 nH because this value is below the absolute maximum. Reduced PIN_0dBFS Operation via Scaling IDAC1FS -160 250 280 290 300 310 320 330 340 350 -80 IDAC1 FS = 1mA (39nH) -82 -84 -86 IDAC1 FS = 2mA (39nH) -88 -90 -92 -94 IDAC1 FS = 4mA (19nH) -96 -98 250 (4) 260 270 280 290 300 310 320 330 340 350 FREQUENCY (MHz) where IDAC1_FS is the decimal equivalent of the value in Register 0x10A. Figure 82. Swept Dual-Tone IMD vs. IDAC1FS Setting with Decimate by 16, I/Q Output, Dual Tones Set to -8 dBFS (IF = 300 MHz, BW = 100 MHz, FADC = 3.2 GHz) The LEXT value can be increased proportionally to any reduction in IDAC1FS to maintain similar voltage swings across the LC tank. With an IF of 300 MHz, the absolute maximum inductor is 39 nH; therefore, this inductor value is selected for both IDAC1FS = 2.0 mA and 1.0 mA. Reducing IDAC1FS from 4.0 mA to 2.0 mA and doubling LEXT lowers the PIN_0dBFS by 6 dB but increases the average in-band noise, IBN, by only 1.8 dB. The noise figure of the ADC therefore improves by 4.2 dB. Reducing IDAC1FS from 2.0 mA to 1.0 mA lowers the ADC full scale by a further 6 dB and increases the average inband noise by only 4.6 dB. In this case, the noise figure improvement is a modest 1.4 dB. 0.5 NORMALIZED STF RESPONSE (dBFS) The NSD and IMD performance are shown in Figure 81 and Figure 82 for IDAC1FS settings of 4.0 mA, 2.0 mA, and 1.0 mA. Figure 83 shows the STF response for each of these cases. Note the following observations from this example: 270 Figure 81. NSD vs. IDAC1FS Setting with Decimate by 16, I/Q Output (IF = 300 MHz, BW = 100 MHz, FADC = 3.2 GHz) The PIN_0dBFS can be reduced by up to 12 dB because IDAC1FS is adjustable over a 4 mA to 1 mA span as defined by Equation 4. 260 IDAC1 FS = 4mA, LEXT = 19nH (IBN = -74.3dBFS) INPUT FREQUENCY (MHz) WORST IMD SPUR (dBFS) Tie the two external inductors, LEXT, to the VDD2 supply via a 10 resistor that includes a 0.1 F decoupling capacitor, as shown in Figure 93. -155 (3) The minimum capacitance contribution of the array can be up to 6.6 pF due to 20 process variation. An additional 0.5 pF of PCB parasitic capacitance is also included, thus a value of 7.1 pF is used. IDAC1FS = 4 mA x (IDAC1_FS/64) -150 12348-035 LMAX_TUNE = ((2 x FIF) x 7.1 pF) -1 The swept IMD performance shows a degradation at reduced IDAC1FS settings. The STF response remains largely unaffected by reduced IDAC1FS settings. 12348-036 2 0.4 0.3 0.2 IDAC1FS = 1mA (39nH) 0.1 0 -0.1 IDAC1 FS = 2mA (39nH) -0.2 -0.3 -0.4 -0.5 250 IDAC1 FS = 4mA (19nH) 260 270 280 290 300 310 FREQUENCY (MHz) 320 330 340 350 12348-037 Surface mount inductors can be either wire-wound or multilayer. The lower cost multilayer inductors typically have quality factors below 20 that may have a slight impact on the AD6676 NSD performance. Compare performance between the two inductor types before making a decision to select a lower cost multilayer type. Because the voltage swing across the LC tank scales proportionally with IDAC1FS, which sets PIN_0dBFS, a reduction in IDAC1FS allows an inversely proportional increase of LEXT to maintain a similar voltage swing. Note that the minimum tuning capacitance from the internal capacitor array along with any parasitic PCB capacitance sets largest the LEXT as defined in Equation 3. NSD (dBFS/Hz) AD6676 Figure 83. STF vs. IDAC1FS Setting with Decimate by 16, I/Q Output, Dual Tones Set to -8 dBFS (IF = 300 MHz, BW = 100 MHz, FADC = 3.2 GHz) Rev. D | Page 29 of 90 AD6676 Data Sheet Some applications may benefit from a reduced IDAC1FS setting because a reduction in the PIN_0dBFS levels results in a decibel per decibel reduction in the gain and linearity (P1dB, IIP3) requirements of the front-end driver. This enables a lower power RF line-up with the possibility of 3.3 V operations. Alternatively, it can allow a greater IF AGC operation range from the AD6676 when the previous stages output (P1dB) level is set by its power supply setting. Carefully evaluate the tradeoff in the ac performance of the AD6676 when deciding to operate at reduced IDAC1FS settings. Table 8. Resonator Frequencies vs. MRGN Settings (FADC = 3.2 GHz, FIF = 300 MHz, BW = 160 MHz) MRGN_L 5 10 15 8 MRGN_U 5 10 15 16 MRGN_IF 0 0 0 2 RESON2 (MHz) 233 229 227 230 RESON1 (MHz) 298 299 298 306 RESON3 (MHz) 365 370 373 374 -140 MRGN = [15 15 0] Using the MRGN Parameter to Optimize NTF -150 -155 220 240 260 280 300 320 340 360 380 INPUT FREQUENCY (MHz) 12348-038 MRGN = [5 5 0] Figure 84. NSD Performance for MRGN Settings Shown in Table 8 Maintaining a flat STF across the pass band is also desirable when modifying the MRGN settings. Figure 84 shows how each of the different MRGN settings affects the STF. Note that the asymmetrical MRGN setting of [8 16 2] results in an STF that is slightly skewed above IF center but still maintains 0.5 dB flatness. 0.25 MRGN = [5 5 0] 0 -0.25 -0.50 MRGN = [10 10 2] -0.75 MRGN = [15 15 2] MRGN = [8 16 2] -1.00 -1.25 220 240 260 280 300 320 340 360 FREQUENCY (MHz) 380 12348-039 The following example using a low oversampling ratio of 10 highlights the effects of the MRGN parameters on the NTF and STF. In this example, the goal is to optimize the worst-case NSD performance across a 160 MHz pass band region with FADC = 3.2 GHz and IF = 300 MHz while trying to preserve a flat STF. Figure 84 shows the corresponding NTF performance for different MRGN settings, and Table 8 lists the resonant frequencies of RESON1, RESON3, and RESON3 that pertain to these settings. Note that the default setting of [5 5 0] results in the upper half of the pass band having the worst NSD (-141 dBFS/Hz at 380 MHz). Symmetrical MRGN settings of [10 10 0] and [15 15 0] are shown to highlight how the NTF varies as only the resonant frequencies of RESON2 and RESON3 are increasingly offset symmetrically about the IF center of 300 MHz. To improve on the default setting of [5 5 0], an asymmetrical setting of [8 16 2] that is weighted towards the upper half of the pass band region was found to achieve a more distributed worst-case NSD of -145 dBFS/Hz. -145 MRGN = [8 16 2] NORMALIZED STF RESPONSE (dBFS) The MRGN_L, MRGN_U, and MRGN_IF parameters are located in Register 0x107 through Register 0x109. MRGN_L and MRGN_U specify the number of megahertz by which the lower and upper edges of the target pass band are extended, whereas MRGN_IF specifies the resonance frequency offset of RESON1 from the center of the target pass band. The maximum setting in these registers must be in the range of 10 MHz to 20 MHz because higher offset settings can adversely affect the STF. The MRGN parameter is represented as an array equal to [MRGN_L, MRGN_U, MRGN_IF]. NSD (dBFS/Hz) MRGN = [10 10 0] The MRGN application parameters provide an additional degree of freedom when trying to optimize the NTF for a particular application. This feature is particularly useful when the AD6676 operates with a low oversampling ratio where the quantization noise contribution begins to limit the NSD performance. In such cases, the default MRGN settings may not be adequate, resulting in regions of the pass band (typically at the edges) where the worst-case NSD is higher than in other regions. For these cases, the NTF can be optimized by adjusting the - ADC resonator frequencies in such a way that that result in a more optimally distributed NSD over the entire pass band. Figure 85. STF for Four Different MRGN Settings Whereas the previous example represents an extreme case, other cases having higher oversampling ratio can also potentially benefit from optimization. After the values of fCLK, IF, and BW have been determined for a particular application, it may be advantageous to explore whether a different MRGN setting yields any improvement. It is important to note that this sort of optimization is based on an iterative trial and error method. However, after the MRGN setting has been determined, both the STF and NTF remain repeatable. Rev. D | Page 30 of 90 Data Sheet AD6676 - ADC Adaptive Shuffler Table 9. Default SPI Register Settings for Adaptive Shuffling The AD6676 includes a programmable adaptive shuffler that improves the SFDR and IMD performance of the - ADC under large signal conditions. As shown in Figure 68, the adaptive shuffler randomizes the selection of the unit elements used by the feedback DACs to reconstruct the output signal of the quantizer. Both static and dynamic mismatch errors associated with the quantizer and feedback DACs are dithered such that the spurious contribution is spread across a wider frequency span. Figure 86 compares the improved IMD performance for a two tone excitation when the shuffler is enabled and disabled. Shuffling Rate FADC FADC/2 FADC/3 FADC/4 Disable shuffler AMPLITUDE (dBFS) 0 ADAPTIVE SHUFFLING DISABLED -20 -40 -60 -80 -100 -120 Register 0x342 0xF5 0x5F 0xFF 0xFF 0xFF Register 0x343 0xFF 0xFF 0xF5 0x5F 0xFF Table 10. Threshold Setting Values that Trigger the Shuffler for a Continuous Wave Tone PIN (dBFS) -3 -5 -7 -10 -14 -20 Threshold Setting 8 7 6 5 4 3 ADAPTIVE SHUFFLING ENABLED SHUFFLE EVERY ONE ADC CLOCK CYCLE (0x342 = 0xF5, 0x343 = 0xFF) -40 -60 -80 -100 -120 140 150 160 170 180 190 FREQUENCY (MHz) 200 210 220 12348-040 AMPLITUDE (dBFS) 0 -20 Figure 86. IMD Performance when Shuffler Is Disabled vs. Enabled for Two CW Tones at -8 dBFS, (FIF = 180 MHz, BW = 80 MHz, FADC = 3.2 GHz, LEXT = 43 nH) Although the shuffler improves the SFDR and IMD performance, it does so at the expense of the in-band NSD performance. For this reason, both the degree of shuffling as well as the enabling threshold relative to the quantizer output code is user programmable, allowing optimization for a target application. The shuffling rate is variable from 1 to 4 ADC clock cycles (1/FADC). The shuffler remains enabled for a fixed amount of clock cycles from the instant that the input signal falls below this threshold and remains below it. The enabling threshold is relative to the quantizer code and represents the peak absolute value that triggers the shuffler. The quantizer can produce an output code ranging from -8 to +8, therefore the threshold can assume a value between 0 to 8. The 4-bit value is set via Register 0x342 or Register 0x343. A hexadecimal value of 0x0 sets the shuffler to always enabled whereas a value of 0xF effectively disables the shuffler. The 4-bit fields in Register 0x342 and Register 0x343 set the threshold value based on the shuffling rate selected. Set only the 4-bit field pertaining to the selected shuffling rate while the remaining nonapplicable 4-bit fields set to 0xF. Disable the shuffler by setting all the 4-bit fields to 0xF, the highest threshold setting. Table 9 shows the SPI register settings for the various shuffling modes when the threshold is set to its default setting of 5. Other threshold values ranging from 3 to 8 are also possible. Table 10 shows the input power level that triggers the shuffler for different threshold value settings when driven by a continuous wave tone. When enabled, the shuffler can introduce colored noise into the pass band spectrum. This additional noise is a result of the increased switching activity within the - ADC core along with the pseudorandom element selection process, thus resulting in signal level dependent colored noise at frequency offsets related to the shuffling rate. Figure 87 highlights the effect of the colored noise between shuffle every four clock cycles vs. one cycle with and without a large signal continuous wave tone present and the shuffling threshold set to 0. Typically, the shuffling threshold is set in the range of 4 to 6. This example serves to highlight the colored noise effects of shuffling. Selecting a higher threshold setting is preferable when trying to preserve the NSD performance. For this reason, the AD6676 default threshold setting is 5 with the shuffle every clock cycle option. The four-cycle option introduces visible noise humps with a -1 dBFS signal level. This colored noise is at an offset of fCLK/128, resulting from the pseudorandom element selection process. Other shuffling options also introduce colored noise but at a greater frequency offset that are related to the shuffling rate factor (SRF) as described by the following equation: Frequency Offset = fCLK/(32 x SRF) (5) The effect of this colored noise is worthy of consideration when selecting the shuffling rate and threshold. For example, sweeping a -1 dBFS continuous wave tone across the usable IF pass band region while monitoring the NSD characteristics is helpful to identify what shuffling rate may have the least impact on the NSD performance. Rev. D | Page 31 of 90 AD6676 Data Sheet -140 -74 SHUFFLE EVERY 1 ADC CYCLE IBN = -75.5dBFS SHUFFLE EVERY 4 ADC CYCLES IBN = -76.3dBFS SHUFFLE DISABLED IBN = -77.4dBFS -142 -144 SHUFFLING EVERY 1 ADC CYCLE -75 SHUFFLING EVERY 2 ADC CYCLES -76 -148 IBN (dBFS) NOISE (dBFS/Hz) -146 -150 -152 -77 SHUFFLING EVERY 4 ADC CYCLES -78 -154 SHUFFLING EVERY 3 ADC CYCLES SHUFFLING DISABLED -156 -79 150 160 170 180 190 200 210 220 INPUT FREQUENCY (MHz) Figure 87. NSD Performance of the Various Shuffling Settings with No Signal; Threshold Set to 0 (Shuffler Is Always Enabled); FIF = 180 MHz, BW = 80 MHz, FADC = 3.2 GHz, LEXT = 43 nH -140 -142 SHUFFLE DISABLED IBN = -74.6dBFS -800 -40 12348-094 -160 140 -30 -20 -15 -10 -5 0 Figure 89. Pass Band Degradation in IBN (dBFS) as a Continuous Wave Tone at 225 MHz, Swept from -40 dBFS to -1 dBFS with Different Shuffling Rate Settings, Threshold Set to 0, FIF = 180 MHz, BW = 80 MHz, FADC = 3.2 GHz, LEXT = 43 nH -74 -75 SHUFFLING EVERY 2 ADC CYCLES THRESHOLD = 4 -146 -148 -76 IBN (dBFS) NOISE (dBFS/Hz) -25 INPUT POWER (dBFS) SHUFFLE EVERY 1 ADC CYCLE IBN = -73.6dBFS SHUFFLE EVERY 4 ADC CYCLES IBN = -74.0dBFS -144 -35 12348-042 -158 -150 -152 -154 SHUFFLING EVERY 2 ADC CYCLES THRESHOLD = 5 -77 -78 -156 SHUFFLING DISABLED -158 150 160 170 180 190 INPUT FREQUENCY (MHz) 200 210 220 Figure 88. NSD Performance of the Various Shuffling Settings with a -1 dBFS Signal; Threshold Set to 0 (Shuffler Is Always Enabled); FIF = 180 MHz, BW = 80 MHz, FADC = 3.2 GHz, LEXT = 43 nH The degradation in NSD performance is also dependent on the input signals amplitude; thus, it is important to select a shuffling rate and threshold setting that result in an optimum trade-off between large signal linearity performance and low signal level in-band noise performance. Figure 89 shows how the in-band noise (dBFS) degrades at increasing signal levels for the same settings used in Figure 87. In this example, a continuous wave tone is placed just above the pass band with its power swept from -40 dBFS to -1 dBFS. At low signal levels (less than -20 dBFS), the degradation in in-band noise performance is dependent on the shuffling rate. At higher signal levels (greater than-20 dBFS), the degradation is a result of increased colored noise falling in the pass band. Selecting a shuffle rate of every two ADC cycles with a threshold in the range of 4 or 5 is a good compromise, as shown in Figure 90. -80 -40 -35 -30 -25 -20 -15 INPUT POWER (dBFS) -10 -5 0 12348-043 -79 12348-041 -160 140 Figure 90. IBN vs. Input Power Performance for Threshold Settings of 4 and 5 When Configured for Shuffle Every Two ADC Cycles After a particular shuffling configuration is selected, the effects on the - ADC performance remain repeatable over time and among different devices - ADC Profile Feature The AD6676 includes a feature that allows the - ADC to store up to four different profile settings that can be recalled quickly via Register 0x118 without recalibrating the - ADC. Calibration of each of the different profiles specified in Register 0x115 occurs during the device initialization phase with each profile consisting of the following various application parameters: BW, FIF, IDAC1FS, and MRGN. FADC, along with the decimation filter and JESD204B settings, remains common to ensure that the JESD204B link is maintained when switching between profile settings. Note that the - ADC is operational with the updated profile settings within 1 s upon receipt of the SPI command. Rev. D | Page 32 of 90 Data Sheet AD6676 The following example highlights how this feature is used for applications that require wide bandwidth capability but not necessarily instantaneous bandwidth. In these applications, it may be possible to divide the required IF bandwidth into narrow subbands where the - ADC can provide higher dynamic range. For instance, in an application that requires 120 MHz of IF bandwidth, consider dividing this bandwidth into three contiguous blocks of 40 MHz, with each IF being offset by 40 MHz. Figure 91 shows that the worst-case NSD is limited to -149 dBFS/Hz when the AD6676 is configured for the wider bandwidth of 120 MHz. Figure 92 shows how the NSD performance is improved by 10 dB when the 120 MHz bandwidth is subdivided into three 40 MHz bands. The AD6676 includes an on-chip differential 27 dB attenuator with a resolution of 1 dB. The attenuator can be used to rescale the fullscale input level into the ADC for system calibration or for optimization purposes or to prevent possible overload of the - ADC when used with external AGC control. Figure 93 shows a simplified equivalent circuit of the AD6676 input stage, which includes RESON1 and IDAC1. The attenuator provides a nominal input resistance (RIN) of 60 to the signal source to facilitate its interface to external driver circuitry. The attenuator is configurable via Register 0x181 to Register 0x183 and includes options for fast external gain control via the AGC pins. Note that the latency from when an external CMOS signal is applied to the AGC pins to when the attenuator changes state is within 5 ns. 10 0.1F -149dBFS/Hz -150 LEXT L- AD6676 -155 CARRAY PROFILE = 0 (IF = 260MHz, BW = 120MHz) 220 240 260 280 300 RIN = 60 VCM = 1.0V 320 INPUT FREQUENCY (MHz) VIN- REG 0x180 TO 0x181 PROFILE = 2 (IF = 300MHz, BW = 40MHz) PROFILE = 1 (IF = 260MHz, BW = 40MHz) SUMMING JUNCTION VIN+ Figure 91. NSD Performance with Wideband Profile (FIF = 260 MHz, BW = 120 MHz, FADC = 3.2 GHz, LEXT = 27 nH) -145 ATTENUATOR 0dB TO 27dB = 1dB IDAC1 AC DC 12348-044 -160 200 Figure 93. Simplified Equivalent Input -150 PROFILE = 0 (IF = 220MHz, BW = 40MHz) -155 -159dBFS/Hz -160 200 220 240 260 280 INPUT FREQUENCY (MHz) 300 320 12348-101 NOISE SPECTRAL DENSITY (dBFS/Hz) VDD2 = 2.5V LEXT L+ 12348-100 NOISE SPECTRAL DENSITY (dBFS/Hz) -145 ATTENUATOR Figure 92. NSD Performance with Narrow-Band Profiles (FIF = 220 MHz, 260 MHz, and 300 MHz, BW = 120 MHz, FADC = 3.2 GHz, LEXT = 27 nH) In this example, the frequency and phase settings of the digital mixer remained common among the various profiles such that it remained centered upon 260 MHz. It is also possible to provide a unique digital mixer setting for each profile if it is desirable to re-center the digital IF frequency. This feature is desirable in instances where the range of IFs cannot be supported by the pass band response of the digital decimation filter. Attenuation is achieved by a programmable shunt and series resistor network that steers some designated amount of input current away from the summing junction while keeping the nominal input resistance near 60 over the full attenuation span. For a 0 dB setting, no shunt resistance exists; therefore, all of the input current is fed into the summing junction. For a 6 dB setting, the attenuator is configured with a 120 shunt resistor operating in parallel with two 60 series resistors such that half of the signal input current is directed into the summing junction while maintaining a nominal 60 input resistance. Other settings function in a similar manner with resistor values modified to achieve the desired attenuation value while maintaining the nominal RIN. Figure 94 shows the differential S11 of the AD6676 input for different attenuator settings. Rev. D | Page 33 of 90 AD6676 Data Sheet Note the following conditions and observations: 0dB 2dB 4dB 6dB 8dB 10dB 12dB 14dB -12 -14 -18 The AD6676 is configured as follows: IF = 180 MHz, BW = 80 MHz, and fCLK = 3.2 GHz. Tones are situated at 177.5 MHz and 182.5 MHz. The PIN_0dBFS level is reduced by 6 dB when IDAC1FS is reduced to 2 mA. The IMD performance remains below -80 dBc until an attenuator setting of 9 dB. Further increases in the two-tone power lead to a corresponding steady decline in the IMD performance due to the nonlinearity of the attenuator. Although not shown, the NSD performance centered about the IF improves a few dB with increased attenuation. -20 -22 -24 -26 -30 0 100 200 300 400 500 600 700 800 900 1000 FREQUENCY (MHz) 12348-702 -28 17 Figure 94. Differential S11 vs. Frequency for Different Attenuator Settings 0.10 +85C +25C -40C 0.08 14 11 PIN_0dBFS (dBm) The accuracy of the attenuator is an important consideration in applications implementing AGC or system calibration. The attenuator remains monotonic over its full operating range. Figure 95, which shows a typical devices attenuation error vs. attenuation state at -40C, +25C, and +85C, demonstrates the near instrumentation level accuracy of the AD6676 attenuator. STEP SIZE ERROR (dB) 0.06 0 PIN_0dBFS_IDAC1FS = 2mA PIN_0dBFS_IDAC = 4mA IMD_IDAC1FS = 4mA IMD_ IDAC1FS = 2mA -10 -20 8 -30 5 -40 2 -50 -1 -60 -4 -70 -7 -80 0.04 -10 0.02 3 6 9 12 15 18 -90 21 ATTENUATOR SETTING (dB) 0 Figure 96. IMD Component Degradation as Two-Tone Centered at an IF of 180 MHz Is Increased 1 dB for Every 1 dB Increase in Attenuator Setting, Such That Two-Tone Level Remains at -8 dBFS -0.02 -0.04 -0.06 0 3 6 9 12 15 18 ATTENUATOR SETTING (dB) 21 24 27 12348-046 -0.08 -0.10 0 12348-047 S11 (dB) -16 WORST IMD (dBc) -10 Figure 95. Typical Attenuation Step Size Error vs. Setting over Temperature The linearity performance of the attenuator is another consideration when determining the largest input drive levels before its nonlinearity may dominate over that of the - ADC. The effective PIN_0dFS level of the AD6676 is increased decibelper-decibel by the attenuator setting. At large attenuator settings, the peak-to-peak voltage swing seen at the VIN+ and VIN- pins increases as well as the current that is steered into the attenuator shunt resistance. At a certain level, the IMD contribution from the attenuator begins to dominate over the - ADC contribution. Figure 96 plots the worst third-order IMD spurious vs. attenuator setting for IDAC1FS of 4 mA and 2 mA with the power of the dual tones increased to maintain a constant -8 dBFS level measured by the - ADC. The effective PIN_0dBFS is also plotted to show the maximum continuous wave signal level into the device that results in a 0 dBFS level. The effects of switching transients are another important consideration for AGC implementations that digitally calibrate gain changes in the signal path of the receiver that can otherwise degrade the demodulation of the desired signals. Figure 97 and Figure 98 show the IQ envelope response when the attenuator state is switched between 0 dB and 6 dB via an external control signal using the AGC2 input pin at a rate of 3.3 MHz. Note that the settling response is dominated by the response of the digital filter (decimate by 12) and shows no signs of glitch. Rev. D | Page 34 of 90 Data Sheet AD6676 CLOCK SYNTHESIZER The AD6676 includes an on-chip clock synthesizer capable of generating the clock for the - ADC and digital circuitry. The entire synthesizer is integrated on-chip, including the loop filter and VCO. Figure 99 shows a functional block diagram of the various synthesizer subblocks along with the relevant SPI registers. The clock synthesizer uses a standard integer-N architecture to generate a 2.94 GHz to 3.2 GHz ADC clock from a 10 MHz to 320 MHz reference input. 0.75 0.50 0.25 0 40 60 80 100 120 140 160 SAMPLE 12348-048 NORMALIZED I/Q MAGNITUDE (dB) 1.00 Figure 97. Wide Envelope Response for 6 dB Attenuator Step Change with fDATA_IQ = 250 MSPS, Resulting Sample Period of 4 ns Note that if the clock synthesizer is used to supply the ADC clock, the clock synthesizer must be configured first, before any other blocks are enabled. Also note that because the clock synthesizer sequence involves calibrations, wait intervals or polling loops are needed to ensure that each calibration step completes before issuing the next SPI command. Table 27 lists an example SPI sequence for a particular case where the reference frequency (fCLK) and ADC clock rate (FADC) are 200 MHz and FADC = 3200 MHz, respectively. The remainder of this section describes the configuration of the clock synthesizer in detail. 0.75 0.50 0.25 0 32 33 34 35 36 37 38 39 40 41 42 43 SAMPLE 12348-049 NORMALIZED I/Q MAGNITUDE (dB) 1.00 Configuring the clock synthesizer requires numerous SPI commands to program settings and to initiate calibrations. The SPI sequence to configure the AD6676 for a particular operating mode, including the SPI operations associated with the clock synthesizer, is most easily obtained from the software tool that comes with the AD6676EBZ development platform. This tool allows the SPI sequence used to configure the AD6676 to be saved to a file for later use. Figure 98. Zoom In Envelope Response for 6 dB Attenuator Step Change with fDATA_IQ = 250 MSPS, Resulting Sample Period of 4 ns VDDQ VDDQ fPFD = 10MHz TO 80MHz CHARGE PUMP REG 0x2AC REG 0x2AD REG 0x2BC R-DIVIDER /2 VCO 5.9GHz TO 8.0GHz REG 0x2AA REG 0x2B7 DIRECT RF CLK OPTION UP /2 DN INTEGRATED LOOP FILTER REG 0x2BB TO - ADC AND DIGITAL REG 0x2A5 INITIAL CAL AUTOMATIC LEVEL CONTROL CAL VDDQ REG 0x2AB REG 0x2BC N COUNTER REG 0x2A1 (LSB) REG 0x2A2 (MSB) Figure 99. CLK Synthesizer Block Diagram Rev. D | Page 35 of 90 12348-050 /4 x2 PFD CLK = 10MHz TO 320MHz VDDC ENABLE CLK SYN REG 0x2AO AD6676 Data Sheet R and N Dividers VCO Configuration and Calibration The phase/frequency detector (PFD) requires a 10 MHz to 80 MHz clock. When fCLK = 200 MHz, the R divider must be set to divide by 4 so that fPFD = fCLK/RDIV = 50 MHz, which is within the supported range. Table 11 shows the mapping from RDIV to the value of Register 0x2BB. This register is set in Step 6 of Table 27. VCO configuration consists of writing to the SPI registers in Table 12 that control the VCO core bias, temperature compensation, and varactor settings. These settings depend on the VCO frequency and are optimized via characterization to ensure proper operation of the PLL over supply and temperature. Table 11. R Divider Settings for Register 0x2BB Table 12. VCO Configuration Settings vs. FADC RDIV 1 2 4 0.5 FADC (MHz) 2940 to 2950 2950 to 3100 3100 to 32001 Register 0x2BB [7:6] 0b00 0b01 0b10 0b11 1. Note that operating with the highest permissible fPFD minimizes the clock synthesizer reference spur because the PLL filter bandwidth is fixed at 200 kHz. For a sinusoidal clock input signal that has a limited input slew rate, operation with an input frequency that is 2x or 4x the desired fPFD can also result in a slight improvement in phase noise performance. Because the ADC clock is obtained by dividing the VCO clock by 2, the N-divider must be set according to N = 2FADC/fPFD =2 x 3.2 GHz/50 MHz =128 = 0x80 The value of N is programmed by writing the LSB (0x80) to Register 0x2A1 and the MSB (0x00) to Register 0x2A2 and is set in Step 1 of Table 27. The VCO also must be calibrated during the clock synthesizer initialization phase to ensure proper operation over its full temperature range. VCO calibration is triggered via Register 0x2AB with the amount of time required to complete the calibration again being inversely proportional to the PFD frequency. Specifically, fPFD = 10 MHz requires a 2 ms wait period whereas fPFD = 80 MHz decreases the wait period by a factor of 8 to 0.25 ms. Alternatively, poll Bit 1 of Register 0x2BC; VCO calibration is complete when this bit is clear. After the initialization process is complete, verify that Bit 3 of Register 0x2BC is set to confirm that the PLL is locked. The charge pump current setting (Register 0x2AC) is given by 1.33 1028 1)) f PFD FADC 2 Register 0x2B7 0xF0 0xE0 0xD0 Operation at 3200 MHz requires the following modification to the KVCO and charge pump resistor settings: Register 0x2A9 = 0x2A and Register 0x2AC = 0x12. Charge Pump Current and Calibration I CP round(min(63, Register 0x2AA 0x37 0x37 0x37 (6) For the FADC and fPFD values used in this example, ICP evaluates to 25, or 0x19; this value is programmed in Step 4 of Table 27. The charge pump also must be calibrated during the clock synthesizer initialization phase. Calibration is triggered via Register 0x2AD The time required to complete the calibration is inversely proportional to the PFD frequency. For example, using fPFD = 10 MHz requires a maximum 4 ms wait period but increasing fPFD to 80 MHz decreases the maximum wait period by a factor of 8 to 0.5 ms. Alternatively, poll Bit 0 of Register 0x2BC; charge pump calibration is complete when this bit is set. Rev. D | Page 36 of 90 Data Sheet AD6676 -128 Phase Noise Performance -130 (7) -134 For example, the phase noise at 1 MHz offset for an FADC of 3.2 GHz is approximately -124 dBc/Hz. An IF input frequency of 200 MHz results in a 24 dB improvement, thus the expected phase noise at 1 MHz offset is -148 dBc/Hz. 2.95GHz 3.00GHz 3.10GHz 3.20GHz 0.4 0.6 600kHz -140.93 0.11 0.32 800kHz -144.14 0.11 0.37 1MHz -146.48 0.10 0.39 -136 -138 -140 -142 -144 -146 -148 -150 -152 -154 -156 0.2 0.8 1 2 3 -109 -111 Figure 101. Power Cycle Repeatability (10 Attempts) of Phase Noise Measurement for an IF Input Frequency of 225 MHz and fCLK = 2.94912 GHz with PLL PFD = 61.44 MHz -113 -115 -117 -119 -123 -125 -127 -129 -131 0.4 0.6 0.8 1 2 FREQUENCY OFFSET (MHz) 5 12348-051 -133 PHASE NOISE (dBc/Hz) -121 Figure 100. Clock Synthesizers Typical Phase Noise for Various FADC Values The repeatability of a device that is power cycled 10 times is shown in Figure 101. Note that the measured data in this figure aligns with the expected results based on Equation 5 and Figure 100. The phase noise variation over temperature of a nominal device is shown in Figure 102. -120 -122 -124 -126 -128 -130 -132 -134 -136 -138 -140 -142 -144 -146 -148 -150 -152 -154 -156 0.2 +85C +25C -40C 0.4 0.6 0.8 1 ZERO IF FREQUENCY OFFSET (MHz) 2 3 12348-053 -107 CLK SYN PHASE NOISE @ fCLK (dBc/Hz) 100kHz -125.81 0.23 0.71 ZERO IF FREQUENCY OFFSET (MHz) -105 -135 0.2 MEAN STD PK-PK 12348-052 PNfIN_OFFSET = PNfCLK_OFFSET + 20 x log (FIF/FADC) -132 PHASE NOISE (dBc/Hz) Above the PLL filter bandwidth of 200 kHz, the internal VCO limits the overall phase noise of the clock synthesizer. The VCO phase noise performance shows a slight improvement at its low end of its FADC operating range, as shown in Figure 100 The phase noise for a particular IF input frequency can be calculated using Equation 5. Figure 102. Typical Temperature Stability of Clock Synthesizer with the Same Conditions as Figure 101 Rev. D | Page 37 of 90 AD6676 Data Sheet DIGITAL PROCESSING BLOCKS The AD6676 includes the following digital blocks between the - ADC output and JESD204B transmitter core: An ADC overload and recovery block immediately follows the ADC. This circuitry quickly detects any ADC instability from an overload event while ensuring fast recovery. A digital signal processing block translates the real IF signal from the - ADC to a complex zero IF, suitable for postprocessing by the host without loss of any dynamic range. This block includes both coarse and fine QDDCs, along with a selectable FIR decimation filter stage that provides decimation factors of 12, 16, 24, and 32. A peak detection and AGC support block facilitates the implementation of an external AGC control loop under the control of the host. Note that the AGC pins can also be repurposed for GPIO functions. AGC4, AGC3 AGC2, AGC1 GPIO CONTROL OPTION REG 0x1B0 TO 0x1B4 ATTENUATOR CONTROL REG 0x180 TO 0x184 RESET REG 0x188 TO 0x18B, 0x18F ADC OVERLOAD RECOVERY AGC SUPPORT PEAK DETECTOR INPUT REG 0x193 TO 0x19E MIX1 COARSE QDDC BAND-PASS - ADC 27dB ATTENUATOR (1dB STEPS) MIX2 FINE QDDC 3x OR 4x 5 BITS 2x 16 BITS 2x 2x 2x DEC_MODE = 12, 16, 24 OR 32 REG 0x140 NCO NCO REG 0x141 REG 0x143 REG 0x142 REG 0x144 REG 0x145 Figure 103. Simplified Block Diagram of Digital Processing Blocks Rev. D | Page 38 of 90 2x 16 BITS 12348-054 Figure 103 shows a diagram of the digital functional blocks along with the SPI configurable registers pertaining to these blocks. The following sections provide more insight into the operation of each of these functional blocks. More information pertaining to these SPI registers can be found in Table 32 through Table 135. Data Sheet AD6676 DIGITAL SIGNAL PROCESSING PATH The - ADC provides a highly oversampled 5-bit digital output representing the desired IF signal pass band as well as the out-of-band shaped noise described earlier. Referring to Figure 104, the digital signal processing path translates this oversampled real IF signal to a complex dc centered IF signal, having a more manageable data rate suitable for transfer via the JESD204B interface. The QDDC performs the real-to-complex frequency translation followed by digital filtering to remove the ADC out-of-band noise, as well as any other undesired signal content, before decimation to a lower data rate without any loss of dynamic range. ADC REAL OUTPUT IMAGE SIGNAL -FADC /2 DESIRED SIGNAL -fIF DC ADC NOISE fIF FADC /2 COMPLEX OUTPUT AFTER QDDC Table 13. Finite Composite Tuning Resolution of Coarse and Fine NCO DEC_MODE (Register 0x140, Bits[2:0]) 1 2 3 4 Decimation Factor 32 24 16 12 DC FADC /2 DIGITAL FILTER RESPONSE F MIX1 MIX2 Round M IF 64 FADC FADC /2 DC fDATA_IQ /2 12348-055 COMPLEX OUTPUT AFTER DECIMATION -fDATA_IQ /2 (8) where: MIX1 is a 6-bit binary number representing the NCO frequency setting in MIX1_TUNING. FIF is the desired carrier frequency in hertz (Hz). FADC is the ADC clock rate in hertz (Hz). COMPLEX OUTPUT AFTER FILTERING -FADC /2 Tuning Res. (MHz) at FADC = 3.072 GSPS 0.75 1.00 0.75 1.00 The tuning frequency settings of the combined coarse and fine NCO (SPI Register 0x141 and SPI Register 0x142) are automatically calculated and set by the AD6676 during the device SPI initialization phase. The user defined FADC and IF settings (SPI Register 0x100 thru SPI Register 0x103) are used to calculate the settings such that the center of the IF pass band is centered about dc. The coarse tuning NCO is set via MIX1_TUNING[5:0], whereas the fine tuning NCO is set via MIX2_TUNING[7:0]. The decimal equivalent frequency setting of each NCO register is based on the following equations. F MIX1 Round 64 IF F ADC -FADC /2 Tuning Resolution FADC/4096 FADC/3072 FADC/4096 FADC/3072 Figure 104. Digital Signal Processing Path Performs Frequency Translation to a Zero IF as well as Filtering and Downsampling Quadrature Digital Downconversion Digital downconversion occurs in two stages using a coarse and a fine QDDC. As shown in Figure 103, the coarse QDDC resides immediately after the - ADC and the fine QDDC follows the first decimation stage. The coarse QDDC provides 6-bit tuning resolution whereas the fine QDDC provides 10-bit tuning resolution. The composite tuning resolution is either FADC/3072 or FADC/4096, depending on whether the first decimation stage is configured for 3x or 4x decimation, which in turn depends on the decimation mode selected as described in Table 13. For applications requiring finer tuning resolution to position the IF signal exactly about dc, consider adding a finer resolution QDDC in the host processor. (9) where: MIX2 is a 8-bit twos complement number representing the NCO frequency setting in MIX2_TUNING. M is 3072 for DEC_MODE = 2 and 4, or 4096 for DEC_MODE = 1 and 3. It is important to note the residue, fOFFSET, between the desired FIF and the AD6676 composite NCO setting, FIF_NCO, because any offset may need to be compensated with an additional fine QDDC located in the host processor. Use the following equations to calculate both parameters: Rev. D | Page 39 of 90 FIF _ NCO MIX1 MIX2 FADC 64 M fOFFSET = FIF - FIF_NCO (10) (11) AD6676 Data Sheet Example Calculate the NCO MIX1 and MIX2 values along with FIF_NCO and fOFFSET with the following AD6676 configuration: FIF = 140 MHz, FADC = 3200 MHz, and decimation factor of 16 (that is, fDATA_IQ = 200 MSPS). Substituting FIF and FADC values in Equation 8 results in MIX1 = 3. Substituting these values in Equation 9 (noting that M = 4096 for DEC_MODE = 3 results in MIX2 = -13). Substituting MIX1 and MIX2 values into Equation 10 results in FIF_NCO = 139.84375 MHz. Substituting FIF and FIF_NCO values in Equation 11 results in fOFFSET = 156.25 kHz. NCO Phase Synchronization The AD6676 coarse and fine tuning NCOs can be set to an initial phase after synchronization with an external SYSREF signal. The initial phase of the coarse tuning NCO is set via MIX1_INIT, with an LSB corresponding to 1/64th of a cycle. The initial phase of the fine tuning NCO is set via MIX2_INIT_x, with an LSB corresponding to 1/1024th of a cycle. Digital Filter Modes The AD6676 digital filter path is designed to provide sufficient stop band rejection of the - ADC shaped out-of-band noise as well as any spurious noise that otherwise might alias back into the desired pass band region after decimation and limit the actual NSD performance. The filter path supports decimation factors of 12, 16, 24, and 32 depending on the DEC_MODE setting. The complex output of the coarse QDDC feeds a pair of symmetrical FIR decimation filters divided into three stages, as shown in Figure 103. The first stage is a decimate by 3 or by 4 filter, depending on whether the desired decimation factor is divisible by three. The second and third stages consists of two cascaded decimate by 2 filters with the third stage outputs supporting the decimate by 12 and by 16 options. A bypassable fourth stage provides the decimate by 24 and by 32 options. The normalized pass band and wideband folded frequency response for each filter mode are shown in Figure 105 through Figure 113. Note the following observations: Wide IF bandwidths (MHz) are supported when operating at lower decimation factors along with a high FADC. It is worth noting that many applications requiring wider IF bandwidth may tolerate reduced ripple and rejection as the digital filter response enters its transition region. The reason is that the - ADC achievable NSD performance at the IF pass band edges also degrades as its oversampling ratio is reduced, thus still dominating relative to any aliased noise due to reduced filter stop band rejection. Table 14. Usable Normalized Complex Bandwidth vs. Decimation Factor DEC_MODE 1 2 3 4 Decimation Factor 32 24 16 12 fDATA_IQ 1 1 1 1 BW (>85 dB Rejection) 0.814 0.814 0.571 0.571 BW (>60 dB Rejection) 0.834 0.834 0.617 0.617 Total Pipeline Latency The digital filter path dominates the latency of the AD6676 whereas the JESD204B PHY adds a few samples of delay and the ADC delay is a fraction of an output sample. The latency between the ADC and digital filter output is fixed with the only nondeterministic delay being associated with the JESD204B PHY clock and lane FIFOs before synchronization. See the Synchronization Using SYSREF section for additional information. Table 15 provides the nominal pipeline delay associated with each DEC_MODE. Note that although all DEC_MODE settings provide similar delays relative to the output data rate, fDATA_IQ, applications that require shorter absolute time delays may consider using a lower decimation factor to reduce the absolute delay by 2x. Table 15. Nominal Pipeline Latency vs. DEC_MODE (Sample Delay Relative to 1/fDATA_IQ) DEC_MODE 1 2 3 4 All filter responses provide a linear phase response over its pass band. The usable IF bandwidth depends on the DEC_MODE as well as the minimum acceptable pass band ripple and stop band rejection requirements. Table 14 provides the normalized usable complex bandwidth vs. DEC_MODE for stop band rejections of greater than 85 dB and 60 dB. The last filter stage sets the usable bandwidth and stop band rejection because it has the most aggressive transition band specifications. For this reason, the decimation factors of 12 and 16 have the same normalized usable bandwidths as does decimation factors of 24 and 32. Rev. D | Page 40 of 90 Decimation Factor 32 24 16 12 JESD204B Lanes 1 1 2 2 IQ Data Output Sample Delay 34.2 34.2 32.3 32.3 Data Sheet AD6676 0.5 0 0.4 -20 0.3 MAGNITUDE (dB) MAGNITUDE (dB) 0.2 0.1 0 -0.1 -0.2 -0.3 -40 -60 -80 MINIMUM ALIAS ATTENUATION 85.5dB -100 -120 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 FREQUENCY NORMALIZED TO fDATA_IQ 12348-056 -0.5 Figure 105. Pass Band Frequency Response of Decimate by 12 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 FREQUENCY NORMALIZED TO fDATA_IQ 12348-059 -0.4 Figure 108. Folded Frequency Response of Decimate by 12 Shows Alias Rejection 0.5 0 0.4 -20 0.3 MAGNITUDE (dB) MAGNITUDE (dB) 0.2 0.1 0 -0.1 -0.2 -0.3 -40 -60 -80 MINIMUM ALIAS ATTENUATION 85.5dB -100 -120 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 FREQUENCY NORMALIZED TO fDATA_IQ 12348-057 -0.5 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 FREQUENCY NORMALIZED TO fDATA_IQ 12348-060 -0.4 Figure 109. Folded Frequency Response of Decimate by 16 Shows Alias Rejection Figure 106. Pass Band Frequency Response of Decimate by 16 0.5 0 0.4 -20 0.3 MAGNITUDE (dB) 0.1 0 -0.1 -0.2 -0.3 -40 -60 -80 MINIMUM ALIAS ATTENUATION 85.5dB -100 -0.5 -120 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 FREQUENCY NORMALIZED TO fDATA_IQ Figure 107. Pass Band Frequency Response of Decimate by 24 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 FREQUENCY NORMALIZED TO fDATA_IQ 0.45 0.50 12348-061 -0.4 12348-058 MAGNITUDE (dB) 0.2 Figure 110. Folded Frequency Response of Decimate by 24 Shows Alias Rejection Rev. D | Page 41 of 90 AD6676 Data Sheet 0.5 Peak Detection and AGC Flags 0.4 Peak detection occurs at the output of the second stage decimation filter, as shown in Figure 103. Detection at this stage represents a compromise between the accuracy of the peak detector, delay time and ability to measure large out-of-band signals. At this stage, the - ADC output signal has been frequency translated to dc and its out-of-band noise sufficiently filtered for reasonable threshold detection accuracy down to -12 dBFS peak signal levels. Note that the peak detector monitors the peak power envelope response of the IF input signal and calculates the peak power (that is, I2 + Q2) expressed in dBFS with 12-bit resolution. 0.3 MAGNITUDE (dB) 0.2 0.1 0 -0.1 -0.2 -0.3 -0.5 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 FREQUENCY NORMALIZED TO fDATA_IQ 12348-062 -0.4 Figure 111. Pass Band Frequency Response of Decimate by 32 0 MAGNITUDE (dB) -20 -40 -60 -80 MINIMUM ALIAS ATTENUATION 88dB -100 Because the peak detector is monitoring the peak power at the output of the second stage decimation filter, it provides a wider frequency range than what can be observed in the final IQ data output. The first stage filter is decimate by 3 or by 4; therefore, the output of the second stage filter can be 1/6th or 1/8th of FADC. Figure 113 shows the normalized measurement bandwidth relative to the output rate of the second stage filter centered about its zero IF. Table 16 references the measurement bandwidth to fDATA_IQ for the different decimation factors such that its absolute bandwidth can be easily determined. For example, the -1 dB bandwidth for an fDATA_IQ of 100 MSPS with decimate by 24 or by 32 is 200 MHz and remains at 200 MHz if the decimation factor is reduced to decimate by 12 or by 16. Any droop occurring at the pass band edges, as well as the - ADC STF, must be considered when setting thresholds. 0.10 0.15 0.20 0.25 0.30 0.35 0.40 FREQUENCY NORMALIZED TO fDATA_IQ 0.45 0.50 Figure 112. Folded Frequency Response of Decimate by 32 Shows Alias Rejection AGC FEATURES AND PEAK DETECTION In receiver applications, it is desirable to have a mechanism to reliably determine when the converter is about to be overdriven. The AD6676 - ADC is based on a feedback loop that can be overdriven into a nonlinear region, resulting in oscillation. This oscillation persists until the - ADC is reset and the overload condition is removed. Typically, a receiver lineup employs some form of AGC that attempts to avoid this scenario. The AD6676 pipeline latency along with any additional overhead associated with the host processor (JESD204B Rx PHY) may limit the ability to design a fast reacting digital-based AGC required by some applications. For this reason, the AD6676 includes the AGCx pins that serve as digital input/ outputs to facilitate the implementation of a fast AGC control loop under the control of the host. The AGC4 and AGC3 pins can be allocated to provide flag outputs after a programmable threshold has been exceeded, including an ADC reset event, while the AGC2 and AGC1 pins can be used to control the onchip attenuator. Register 0x18F and Register 0x193 through Register 0x19E are used for AGC purposes. 0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -0.35 -0.25 -0.15 -0.05 0.05 0.15 0.25 0.35 FREQUENCY OFFSET FROM IF CENTER (NORMALIZED TO FIQ@2ND STAGE FILTER) 12348-064 0.05 MAGNITUDE (dBFS) 0 12348-063 0.5 -120 Figure 113. Normalized Pass Band Filter Response Seen by the Peak Detector Table 16. Normalized Measurement Bandwidth of Peak Detector Relative to Output Data Rate, fDATA_IQ DEC_ MODE 1 2 3 4 Rev. D | Page 42 of 90 Decimation Factor 32 24 16 12 Normalized Measurement Bandwidth Relative to fDATA_IQ -0.5 -1.0 -2.0 -3.0 dBFS dBFS dBFS dBFS 1.76 2.00 2.40 2.64 1.76 2.00 2.40 2.64 0.88 1.00 1.20 1.32 0.88 1.00 1.20 1.32 Data Sheet AD6676 The AD6676 allows the user to set three threshold settings that can trigger one of two possible flags. PKTHRH0 and PKTHRH1 are two upper threshold settings while LOWTHRH is a lower threshold setting. The threshold settings are 12 bits with an MSB and LSB register assigned to each threshold. The 12-bit decimal equivalent value can be calculated using Equation 12. Threshold = 3584 + (Threshold Setting in dBFS) x 256/3 (12) where 0 dBFS corresponds to 3584 (0xE00) and -6 dBFS corresponds to 3072 (0xC00). In the time domain, a 0 dBFS setting corresponds to a signal whose peaks observed at the I and Q outputs can reach plus or minus full scale. Meaning, if the 16-bit I and Q output data are normalized such that its peak values correspond to 1, a 0 dBFS setting corresponds to a signal whose peak can reach the unit circle of a normalized I/Q constellation diagram. The LOWTHRH_x register has an associated dwell time of which the signal must remain below this threshold before a flag can be set. The dwell time is represented in exponential form to realize long dwell periods because the counter operates at FADC/12 for decimate by 12 or 24 settings or FADC/16 for decimate by 16 or 32 settings. The dwell time is set in the DWELL_TIME_ MANTISSA register and DWELL_TIME_EXP register using Equation 13 relative to 1/FADC. Dwell Time = N x [DWELL_TIME_MANTISSA] x 2(DWELL_TIME_EXP) (13) where: N = 12 for decimate by 12 or 24. N = 16 for decimate by 16 or 32. Note that the EN_FLAGx bits provide the additional option of logically OR'ing an ADC reset event with an upper peak threshold event to provide an even faster output flag to the host processor indicating that the attenuation must be applied. This scenario applies to the extreme case where the envelope response of a blocker is exceedingly fast, such that the AGC cannot react fast enough to the upper peak threshold setting flag to prevent overloading the - ADC. Figure 114 provides an example of how the Flag 0 and Flag 1 assigned pins behave to the envelope response of an arbitrary IF input signal. Flag 1 is assigned an upper threshold set by PKTHRH1_x, and Flag 0 is assigned a lower threshold and dwell time set by LOWTHRH_x and DWELL_TIME_x. The Flag 1 indicator goes high when the PKTTHR1_x threshold is exceeded and returns low when the signal envelope falls below this threshold. The Flag 0 indicator goes high only when the envelope of the signal remains below the LOWTHRH_x threshold for the designated dwell time. If the signal level exceeds the LOWTHRH_x threshold before the dwell time counter has expired, the dwell time counter resets again and the Flag 0 indicator remains low until the conditions has been met. By offsetting the PKTTHR1_x and LOWTHRH_x threshold settings as well as optimizing the dwell time setting, it may be possible to optimize the operation of an AGC so that it reacts to signal strength variation due to fading conditions as opposed to the peak to minimum response associated with digital modulated signals. IF Attenuator Control via the AGC2 and AGC1 Pins A flag function can be assigned using the FLAG0_SEL register and FLAG1_SEL register to indicate when any of the thresholds have been exceeded or if an ADC reset event has occurred. These flags must also be enabled via the EN_FLAG register such that a CMOS level signal appears on the AGC4 and AGC3 pins where a logic high indicates when a threshold has been exceeded. The delay relative to the ADC input when an AGC threshold is exceeded to when the flag signal goes high is dependent on the DEC_MODE setting selected. For a DEC_MODE value of 1 or 2 (decimate by 32 or 24), the delay equates to 8 to 9 output samples (1/fDATA_IQ). For DEC_MODE values of 3 or 4 (decimate by 16 or 12), the delay is 16 to 18 samples. The delay associated with an ADC reset event is much shorter because it avoids the digital filter path. This delay is 1 sample for DEC_MODE values of 1 or 2 and 2 samples for DEC_MODE values of 3 and 4. Many AGC implementations require fast gain control if the AGC threshold is exceeded. The AD6676 provides two modes in which the IF attenuator can be quickly changed via the AGCx pins. Use Register 0x180, Bit 0, to select the mode. The first mode uses the AGC2 pin to switch between two attenuator settings that are user defined in Register 0x181 and Register 0x182. The second mode uses the AGC2 and AGC1 pins to decrement and increment respectively the attenuation value in 1 dB steps with pulsed inputs. The starting attenuator value is defined in Register 0x183. The actual attenuator value can be read back via Register 0x184. The first mode is used for the default AD6676 power-up setting with both Register 0x181 and Register 0x182 set to 0x0C. For applications that do not require IF attenuator control but require a different attenuator setting, update both registers with the desired attenuator setting value such that the attenuator remains independent of the AGC2 pin state, if it is left floating. Note that connecting the unused AGC2 and AGC1 pins to VSSD via 100 k pull-down resistors is still the preferred method if these pins are unused. Rev. D | Page 43 of 90 AD6676 Data Sheet UPPER THRESHOLD (PKTTHR1) DWELL TIME TIMER RESET BY RISE ABOVE LOWER THRESHOLD MIDSCALE LOWER THRESHOLD (LOWTHRH) DWELL TIME TIMER COMPLETES BEFORE SIGNAL RISES ABOVE LOWER THRESHOLD 12348-065 FLAG1 FLAG0 Figure 114. Example of Flag Behavior as Signal Envelope Crosses Upper and Lower Threshold Settings Table 17. Power Saving for 3.0 GSPS Operation with CLKSYN Enabled and 125 MSPS IQ Rate (Single JESD204B Lane) Power State at 3 GSPS STDBY_SLOW STDBY_FAST Power Down Power Up IVDD2 (mA) 18 95 2.6 146 IVDD1+, IVDDC+ IVDDL (mA) 162 175 25 433 GPIO FUNCTIONALITY The AGCx pins can also be configured for basic GPIO functionality via Register 0x1B0 to Register 0x1B4. Register 0x1B0 determines which pins are used for GPIO functionality, whereas Register 0x1B1 determines if an AGC pin serves as input or output. If the pin serves as an output, Register 0x1B2 determines the high or low state, and Register 0x1B3 reads back the state of these designated output pins. Lastly, if an AGCx pin serves as an input, Register 0x1B4 reads back the state of this pin. POWER SAVING MODES The AD6676 features two SPI configurable and selectable power savings modes. The first mode is a sleep mode where the AD6676 is placed in a low power state for extended periods, and the second mode is a standby mode where the AD6676 enters a reduced power state but still keeps the JESD204B link and digital clocks active to ensure multichip synchronization (or fixed latency) during fast power cycling. Both sleep mode and standby mode can be entered via a SPI write operation to the PD_MODE bits in the DEVICE_CONFIG register (Register 0x002; Bits[1:0]). Note that, depending on whether sleep or standby mode is selected, various functional blocks within the - ADC itself are either powered down, placed in a low bias state, or remain powered. The standby mode is also controllable via a user designated AGCx pin for faster and more precise power cycling. This feature is particularly useful for TDD-based communication protocols, allowing the host processor to quickly power cycle the AD6676 during transmit bursts. The PD_PIN_CTRL register (Register 0x152) enables this feature as well as designates the AGC pin. IVDDD (mA) 216 221 29 310 PTOTAL (mW) 461 673 64 1182 Percent (%) Power Savings 61 43 Not applicable Not applicable The standby register (Register 0x150) powers down different functional blocks during standby mode. However, all functional blocks that affect the clock generation, distribution and the JESD204B link remain enabled to maintain constant latency while in standby. The only exception is STBY_VSS2GEN (Register 0x150, Bit 6) where a trade-off exists in power savings vs. wake-up time, depending on whether the negative voltage generator is placed in standby. Table 17 shows the realized power savings for the different power savings modes at 3.0 GSPS operation with the AD6676 configured for 125 MSPS IQ output and the internal clock synthesizer enabled. Note that STDBY_FAST and STDBY_SLOW correspond to whether the STBY_VSS2GEN bit is enabled or disabled during standby. Note that an additional 18% power savings can be achieved when powering down the STBY_VSS2GEN bit. Although the AD6676 can enter into standby quickly, it does require a few microseconds to exit standby. Figure 115 shows that the AD6676 can achieve a low power state within 100 ns. Figure 116 and Figure 117 show the wake-up time between the STDBY_FAST and STDBY_SLOW cases to achieve 1% envelope settling accuracy being around 2.5 s and 11.5 s, respectively. The phase response is not shown because it settles faster than the envelope response. Note that the digital data path is enabled for these time domain figures such that the setting time responses can be observed. Rev. D | Page 44 of 90 Data Sheet AD6676 1.0 INTRODUCTION TO THE JESD204B INTERFACE NORMALIZED ENVELOPE OUTPUT 0.9 The JESD204B interface reduces the PCB area for data interface routing yet enabling the use of smaller packages for converter and logic devices. The AD6676 digital output complies with the JEDEC Standard No. JESD204B, Serial Interface for Data Converters. JESD204B is a protocol to link the AD6676 to a digital processing device over a serial interface. The AD6676 supports link rates of up 5.333 Gbps while operating with two output lanes in support of a maximum I/Q data rate (fDATA_IQ) of 266.67 MSPS. Note that a two output lane configuration is always required for decimation factors of 12 and 16. 0.8 0.7 AD6676 ENTERS STANDBY WITHIN 100ns 0.6 0.5 0.4 0.3 0.2 0 10.0 10.0 10.2 10.3 10.4 10.5 10.6 10.7 10.8 10.9 11.0 TIME (s) 12348-066 0.1 Figure 115. Fast Power-Down Response When the AD6676 Is Placed in Standby 1.0 1% SETTLING TIME = 2.5s NORMALIZED ENVELOPE OUTPUT 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0 14.0 14.5 15.0 15.5 16.0 16.5 17.0 17.5 18.0 18.5 19.0 TIME (s) 12348-067 0.1 Figure 116. Settling Time for STDBY_FAST with the STBY_VSS2GEN Enabled for Fastest Recovery, Approximately 2.5 s to 1 % JESD204B data transmit block assembles the parallel data from the ADC into frames and uses 8-bit/10-bit encoding as well as optional scrambling to form serial output data. Lane synchronization is supported through the use of special characters during the initial establishment of the link and additional synchronization is embedded in the data stream thereafter. A JESD204B receiver is required to complete the serial link. For additional details on the JESD204B interface, refer to the JESD204B standard. Because the AD6676 provides 16-bit complex IQ data, its JESD204B transmit block effectively maps the output of two virtual ADCs (M = 2) over a link. The link is configurable for either single or dual lanes with each lane providing a serial data stream via a differential output. The JESD204B specification refers to a number of parameters to define the link and these parameters must match between the AD6676 JESD204B transmitter and receiver. The following parameters describe a JESD204B link: 1.0 0.9 NORMALIZED ENVELOPE OUTPUT JESD204B Overview 1% SETTLING TIME = 11.5s 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0 0 2 4 6 8 10 TIME (s) 12 14 16 18 20 12348-068 0.1 Figure 117. Settling Time for STDBY_SLOW with STBY_VSS2GEN in Standby for Additional Power Savings, Approximately 11.5 s to 1 % Rev. D | Page 45 of 90 S = samples transmitted per single converter per frame cycle (AD6676 value = 1) M = number of converters per converter device (AD6676 value = 2) L = number of lanes per converter device (AD6676 value can be 1 or 2) N = converter resolution (AD6676 value = 16) N' = total number of bits per sample (AD6676 value = 16) CF = number of control words per frame clock cycle per converter device (AD6676 value = 0) CS = number of control bits per conversion sample (AD6676 value = 0) K = number of frames per multiframe (configurable on the AD6676 up to 32) HD = high density mode (AD6676 value = 0) F = octets per frame (AD6676 value = 2 or 4, dependent on L = 2 or 1) T = tail bit (AD6676 value = 0) SCR = scrambler enable or disable (configurable on the AD6676) AD6676 Data Sheet The scrambler uses a self synchronizing polynomial-based algorithm defined by the equation 1 + x14 + x15. The descrambler in the receiver must be a self synchronizing version of the scrambler polynomial. Figure 118 shows a simplified block diagram of the AD6676 JESD204B link mapping the 16-bit I and Q outputs onto the two separate lanes. Other configurations are also possible, such as combining the I and Q outputs onto a single lane (fDATA_IQ 153.6 MSPS) or changing the mapping of the I and Q output paths. In any case, the 16-bit I and Q data are each broken into two octets (eight bits of data). Bit 15 (MSB) through Bit 8 are in the first octet. The second octet contains Bit 7 through Bit 0 (LSB). The four resulting octets (2 I octets and 2 Q octets) may be scrambled. Scrambling is optional but is available to avoid spectral peaks when transmitting similar digital data patterns. The four octets are then encoded with an 8-bit/10-bit encoder. The 8-bit/10-bit encoder takes eight bits of data (an octet) and encodes them into a 10-bit symbol. Figure 119 shows how the 16-bit I or Q data is taken from the final decimation stage, formed into octets, the two octets are scrambled, and how the octets are encoded into two 10-bit symbols. I CONVERTER 0 JESD204B LINK CONTROL (L.M.F.M.S) (SPI REG 0x1C3 TO 0x1C9) FRAMER SWAP (SPI REG 0x1E1) ADC SERDOUT0-, SERDOUT0+ LANE SWAP (SPI REG 0x1E1) SERDOUT1-, SERDOUT1+ 12348-069 Q CONVERTER 1 SYSREF SYNCINB Figure 118. Transmit Link Simplified Block Diagram ADC TEST PATTERNS (REG 0x1E5) JESD204B SAMPLE CONSTRUCTION ADC 16-BIT JESD204B TEST PATTERNS (REG 0x1E5, REG 0x1F8 TO REG 0x1FF) FRAME CONSTRUCTION SCRAMBLER 1 + x14 + x15 (OPTIONAL VIA 0x1C3) JESD204B TEST PATTERNS (REG 0x1E5, REG 0x1F8 TO REG 0x1FF) SERIALIZER 8-BIT/10-BIT ENCODER (0x1E4) a b a b c d e f g h i j SERDOUT0 SERDOUT1 i j a b SYMBOL0 i j SYMBOL1 a b c d e f g h i j 12348-070 JESD204B TEST PATTERNS (0x1E5) Figure 119. Digital Formatting of JESD204B Lanes PROCESSED SAMPLES FROM ADC SAMPLE CONSTRUCTION FRAME CONSTRUCTION DATA LINK LAYER SCRAMBLER ALIGNMENT CHARACTER GENERATION 8-BIT/10-BIT ENCODER PHYSICAL LAYER CROSSBAR MUX SERIALIZER Tx OUTPUT 12348-071 TRANSPORT LAYER SYSREF SYNCINB Figure 120. Data Flow Rev. D | Page 46 of 90 Data Sheet AD6676 FUNCTIONAL OVERVIEW The flowchart in Figure 120 shows the flow of data through the JESD204B hardware from the sample input to the physical output. The processing is divided into layers that are derived from the OSI model widely used to describe the abstraction layers of communications systems. These are the transport layer, the data link layer, and the physical layer (serializer and output driver). Transport Layer The transport layer packs the data into JESD204B frames, which are mapped to 8-bit octets that are sent to the data link layer. The transport layer mapping is controlled by rules derived from the link parameters. The AD6676 uses no tail bits in the transport layer because the output of its IQ digital data path is considered two virtual 16-bit converters. Data Link Layer The data link layer is responsible for the low level functions of passing data across the link. These include optional data scrambling, inserting control characters for lane alignment/ monitoring, and encoding 8-bit octets into 10-bit symbols. The data link layer also sends the initial lane alignment sequence (ILAS), which contains the link configuration data, and is used by the receiver to verify the settings in the transport layer. The SYNCINB pin operation options are controllable via SPI registers. Although the SYNCINB input is configured for a CMOS logic level on its positive pin by default, it can also be configured for a differential LVDS input signal on its positive/ negative pins via Register 0x1E7. The polarity of the SYNCINB input signal can also be inverted via Register 0x1E4. Initial Lane Alignment Sequence (ILAS) The ILAS phase follows the CGS phase and begins on the next LMFC boundary. The ILAS consists of four multiframes, with a /R/ character marking the beginning and an /A/ character marking the end. The ILAS begins by sending an /R/ character followed by a data ramp starting with the value, 0, over four multiframes. On the second multiframe, the link configuration data is sent, starting with the third character. The second character in the second multiframe is a /Q/ character to confirm that the link configuration data follows. All undefined data slots are filled with ramp data. The ILAS sequence is never scrambled. The ILAS sequence construction is shown in Figure 121. The four multiframes include the following: Physical Layer The physical layer consists of the high speed circuitry clocked at the serial clock rate. For the AD6676, the 16-bit I and Q data are converted into one or two lanes of high speed differential serial data. JESD204B LINK ESTABLISHMENT The AD6676 JESD204B Tx interface operates in Subclass 0 or Subclass 1 as defined in the JEDEC Standard No. 204B (July 2011) specification. The link establishment process is divided into the following steps: code group synchronization, ILAS, and user data. Code Group Synchronization (CGS) and SYNCINB Code group synchronization (CGS) is the process where the JESD204B receiver finds the boundaries between the 10-bit symbols in the stream of data. During the CGS phase, the JESD204B transmit (JESD Tx) block transmits /K28.5/ characters. The receiver must locate /K28.5/ characters in its input data stream using clock and data recovery (CDR) techniques. Multiframe 1: Begins with an /R/ character (/K28.0/) and ends with an /A/ character (/K28.3/). Multiframe 2: Begins with an /R/ character followed by a /Q/ (/K28.4/) character, followed by link configuration parameters over 14 configuration octets (see Table 18), and ends with an /A/ character. Many of the parameter values are of the notation of n - 1. Multiframe 3: Begins with an /R/ character (/K28.0/) and ends with an /A/ character (/K28.3/). Multiframe 4: Begins with an /R/ character (/K28.0/) and ends with an /A/ character (/K28.3/). User Data and Error Detection After the ILAS is complete, the user data is sent. Normally, in a frame all characters are user data. However, to monitor the frame clock and multiframe clock synchronization, there is a mechanism for replacing characters with /F/ or /A/ alignment characters when the data meets certain conditions. These conditions are different for unscrambled and scrambled data. The scrambling operation is disabled by default, but may be enabled via Register 0x1C3. The receiver issues a synchronization request by asserting a low signal on the SYNCINB pins of the AD6676. The JESD Tx begins to send /K/ characters. After the receiver has synchronized, it then deasserts its SYNCINB signal, causing it to go high. The AD6676 then transmits an ILAS on the following LMFC boundary. For more information on the CGS phase, see the JEDEC Standard No. 204B (July 2011), Section 5.3.3.1. Rev. D | Page 47 of 90 AD6676 Data Sheet For scrambled data, any 0xFC character at the end of a frame is replaced by an /F/ and any 0x7C character at the end of a multiframe is replaced with an /A/. The JESD204B receiver checks for /F/ and /A/ characters in the received data stream and verifies that they only occur in the expected locations. If an unexpected /F/ or /A/ character is found, the receiver uses dynamic realignment or asserts the SYNCINB signal for more than four frames to initiate a resynchronization. For unscrambled data, if the final character of two subsequent frames is equal, the second character is replaced with an /F/ if it is at the end of a frame, and an /A/ if it is at the end of a multiframe. K K R D D A R Q C C D Insertion of alignment characters may be modified using SPI. The frame alignment character insertion is enabled by default. More information on the link controls is available in the SPI register descriptions for Register 0x1E0 to Register 0x1E6. 8-Bit/10-Bit Encoder The 8-bit/10-bit encoder converts 8-bit octets into 10-bit symbols and inserts control characters into the stream when needed. The control characters used in JESD204B are shown in Table 18. The 8-bit/10-bit encoding ensures that the signal is dc balanced by using the same number of ones and zeroes across multiple symbols. Note that the 8-bit/10-bit interface has an invert option available in Register 0x1E4 that has the same effect of swapping the differential output data pins. D A R D D A R D D A D START OF ILAS START OF LINK CONFIGURATION DATA START OF USER DATA 12348-072 END OF MULTIFRAME Figure 121. Initial Lane Alignment Sequence Table 18. Control Characters used in JESD204B Including Running Disparity Values Abbreviation /R/ /A/ /Q/ /K/ /F/ Control Symbol K28.0 K28.3 K28.4 K28.5 K28.7 8-Bit Value 000 11100 011 11100 100 11100 101 11100 111 11100 10-Bit Value (RD = -1) 001111 0100 001111 0011 001111 0010 001111 1010 001111 1000 Rev. D | Page 48 of 90 10-Bit Value (RD = +1) 110000 1011 110000 1100 110000 1101 110000 0101 110000 0111 Description Start of multiframe Lane alignment Start of link configuration data Group synchronization Frame alignment Data Sheet AD6676 Digital Outputs, Timing and Controls The AD6676 physical layer consists of digital drivers that are defined in the JEDEC Standard No. 204B (July 2011). These CML drivers are powered up by default via Register 0x1E2. The drivers utilize a dynamic 100 internal termination to reduce unwanted reflections. A 100 differential termination resistor at each receiver input results in a nominal 300 mV p-p swing at the receiver. The AD6676 JESD204B differential outputs can interface with custom ASICs and FPGA receivers, providing superior switching performance in noisy environments. Single point-to-point network topologies are recommended with receiver inputs having a nominal differential 100 termination. The common mode of the digital output automatically biases itself to half the VDDHSI supply of 1.1 V (VCM = 0.55 V), thus making ac coupling the preferred coupling method to the receiver logic as shown Figure 122. DC coupling can be considered if the receiver device shares the same VDDHSI supply and input common-mode range. SERDOUTx- -100 -300 EYE: ALL BITS, OFFSET: -0.0055 UIs: 4000; 1059998, TOTAL: 4000; 1059998 -400 -150 -100 -50 0 50 100 150 TIME (ps) Figure 123. Digital Outputs Data Eye with External 100 Terminations at 5.333 Gbps in Accordance to LV-OIF-11G-SR Mask 9000 8000 7000 6000 5000 4000 3000 2000 1000 0 -5 -4 -3 -2 -1 0 1 2 3 4 5 TIME (ps) Figure 124. Digital Outputs Histogram with External 100 Terminations at 5.333 Gbps 1 1-2 1-4 RECEIVER 1-6 0.1F OUTPUT SWING = 300mV 0 VCM = VDDHSI/2 1-8 1-10 Figure 122. AC-Coupled Digital Output Termination Example 1-12 Timing errors caused by a degraded eye diagram at the receiver input can often be attributed to poor far end termination or differential trace routing. These potential error sources can be reduced by using well controlled differential 100 traces with lengths below six inches that connect to receivers with integrated differential 100 resistors. 1-14 1-16 -0.5 -0.4 -0.3 -0.2 -0.1 0 UIs 0.1 0.2 0.3 0.4 0.5 12348-505 100 100 -200 BER SERDOUTx+ 200 100 DIFFERENTIAL TRACE PAIR 0.1F 12348-073 VDDHSI 300 12348-503 The optional SYSREF input can be used for multichip synchronization or establishing a repeatable latency between the AD6676 and its host. The SYSREF receiver circuit must be disabled if not used (Register 0x1E7 = 0x04) to prevent potential false triggering if the input pins are left open. The SYSREF input does not include an internal 100 termination resistor; thus, an external differential termination resistor must be included if this input is used. The SYSREF input is logic complaint to LVPECL, LVDS, and CMOS. 400 12348-504 The AD6676 physical layer consists of consists of two digital differential inputs, SYSREF and SYNCINB, whose equivalent input circuits are shown in Figure 61 and Figure 64. These inputs must be dc-coupled to their respective drivers because they are or can be aperiodic. The SYNCINB input is logic compliant to both CMOS and LVDS via Register 0x1E7, Bit 2, with CMOS being the default. Note that the SYNCINB input includes an internal 100 termination resistor when LVDS is selected. VOLTAGE (mV) Digital Inputs Figure 123, Figure 124, and Figure 125 show examples of the digital output data eye, time interval error (TIE) jitter histogram, and bathtub curve for one AD6676 lane running at 5.333 Gbps with Register 0x1EC set to 0xBD. The format of the output data is twos complement by default. The output data format can be changed via Register 0x146. HITS PHYSICAL LAYER INPUT/OUTPUTS Figure 125. Digital Outputs Data Bathtub with External 100 Terminations at 5.333 Gbps Rev. D | Page 49 of 90 AD6676 Data Sheet Preemphasis CONFIGURING THE JESD204B LINK Preemphasis enables the receiver eye diagram mask to be met in conditions where the interconnect insertion loss does not meet the JESD204B specification. The preemphasis feature is controlled via Register 0x1EF and must be used only when the receiver cannot recover the clock due to excessive insertion loss. Under normal conditions, it is disabled to conserve power. Additionally, enabling and setting too high a deemphasis value on a short link may cause the receiver eye diagram to fail or lead to potential EMI issues. For these reasons, consider the use of preemphasis only in instances where meeting the receiver eye diagram mask is a challenge. See the Register Memory Map section for details. The AD6676 has one JESD204B link. The serial outputs (SERDOUT0 and SERDOUT1) are part of one JESD204B link. The basic parameters that determine the link setup are: Serializer PLL This PLL generates the serializer clock that is equal to the JESD204B lane rate. The on-chip controller automatically configures the PLL parameters based on the user specified IQ data rate (FADC/M) and number of lanes. The status of the PLL lock can be checked via the PLL_LCK status bit in Register 0x2DC. This read only bit lets the user know if the PLL has achieved a lock for the specific setup. L is the number of lanes per link M is the number of converters per link F is the number of octets per frame The maximum and minimum specified lane rates for the AD6676 are 5.333 Gbps and 3.072 Gbps, respectively. For this reason, the AD6676 supports a single lane interface for IQ data rates (fDATA_IQ) from 76.8 MSPS to 133.3 MSPS and a two lane interface from 153.6 MSPS to 266.7 MSPS. The lane line rate is related to the JESD204B parameters using the following equation: Lane Line Rate 40 F DATA_IQ (14) L where: FDATA_IQ FADC DEC The decimation ratio (DEC) is the parameter programmed into Register 0x140. Table 19 shows the JESD204B output configurations supported based on fDATA_IQ. Table 19. JESD204B Output Configurations No. Virtual Converters Supported (same as M) 2 fDATA_IQ (MSPS) 76.8 to 133.3 153.6 to 266.7 JESD Serial Line Rate 40 x fDATA_IQ 20 x fDATA_IQ L 1 2 Rev. D | Page 50 of 90 M 2 2 F 4 2 S 1 1 HD 0 0 N 16 16 N' 16 16 K For F = 4, K 5 For F = 2, K 9 Data Sheet AD6676 SYNCHRONIZATION USING SYSREF The AD6676 uses the SYSREF input to provide synchronization for the JESD204B serial output and to establish a fixed phase reference for the decimation filters and the NCO within the QDDC. Synchronization options are configurable via Register 0x1E8. When initially synchronizing, the absolute phase offset relative to the input clock applied to the CLK pins depends on internal clock phases and therefore has an uncertainty of 1 ADC clock cycles. A clock tree diagram is shown in Figure 126 with an internal clock signal, DIG_CLK, used to ultimately sample the SYSREF signal. Note that the SYSREF setup and hold times are defined with respect to the rising SYSREF edge and rising CLK (or CLK+ with the clock synthesizer disabled) edge, as shown in Figure 2. After the SYSREF signal is sampled, the phase remains locked to the same relative internal ADC_CLK phase offset until the AD6676 is intentionally reset or its clock or power interrupted. Note the following considerations when using SYSREF for synchronization. The SYSREF pulse width must be at least two ADC_CLK periods. Bit 3 of Register 0x2BB must be set low when synchronizing with the clock synthesizer enabled. In this case, that SYSREF is sampled on the rising edge of REF_CLK to allow for significant margin in setup and hold time. This synchronization signal is then sampled again with the internally generated DIG_CLK. Because SYSREF is ultimately sampled with an internal clock greater than 1 GHz, it can be difficult to maintain synchronization of the clock and SYSREF distribution in a system over supply and temperature variations, as well as REG 0x2A5 RF_CLK CLK ADC_CLK CLOCK SYNTHESIZER fOUT = 5.9GHz TO 6.4GHz TO - ADC AND DIGITAL /2 /2 DIG_CLK TO DIGITAL REF_CLK Q REG 0x2BB SYSREF Q D Q D Q TO SYNCHRONIZATION CIRCUITRY 12348-131 cumulative jitter affects. Use the one shot with the second SYSREF pulse to avoid unnecessary resetting of the JES204B link by setting Register 0x1E8 to 0x06. A minimum of two SYSREF pulses are required. The coarse and fine digital NCOs can be reset to an initial phase defined in Register 0x143 through Register 0x145 upon receiving SYSREF. For the recommended one shot with the second SYSREF pulse, set Register 0x1E8 to 0x26 so that the same SYSREF pulse that is used to reset the JESD204 internal dividers is used to reset the NCO phases. If continuous SYSREF is still preferred, it is recommended to use the SYSREF_WIN_NEG and SYSREF_WIN_POS bits in Register 0x1EA to allow for slight variation in SYSREF timing relative to DIG_CLK. A phase variance of 1 ADC clock cycles ultimately results in fractions of a sample when referenced to the IQ output data rate, fDATA_IQ, depending on the decimation factor. For example, for a decimation factor of 32, the phase uncertainty is expressed as 1/32 samples relative to fDATA_IQ. The course and fine digital NCOs are also set to an initial phase up defined in Register 0x143 thru Register 0x145 upon receiving SYSREF. Figure 127 shows how the HMC7044 (or the AD9528) can be used for mulichip synchronization. The HMC7044 is best suited for delivering a low phase noise RF clock source for each AD6676 (refer to Figure 135). In addition, its ability to individually control the delays of both the CLK and SYSREF signals to each AD6676 device allows compensation of PCB skew delays. Figure 126. Block Diagram Showing Options of Sampling the SYSREF Input Signal with the Clock Synthesizer Disabled or Enabled Rev. D | Page 51 of 90 AD6676 Data Sheet HMC7044 (OR AD9528) 1nF CLKOUT0 CLKOUT AD6676 CLK+ 1nF CLK- CLKOUT0 240 240 1nF SCLKOUT1 SYSREF+ SYSREF 1nF SCLKOUT1 SYSREF- 240 240 1nF CLKOUT2 AD6676 CLK+ 1nF CLK- CLKOUT2 240 240 1nF SCLKOUT3 SYSREF+ 1nF 240 240 12348-727 SYSREF- SCLKOUT3 Figure 127. Example of Multichip Synchronization of the AD6676 Using the HMC7044 or the AD9528 Rev. D | Page 52 of 90 Data Sheet AD6676 APPLICATIONS INFORMATION ANALOG INPUT CONSIDERATIONS Table 20. Harmonic Levels When Dual Tones = -6 dBFS of PIN_0dBFS Level is Situated at IF/2 Equivalent Input Impedance and S11 10 61 9 60 8 59 7 58 6 57 5 SHUNT SHUNT SHUNT SHUNT 56 55 54 R WITH ATTENUATOR = 0dB R WITH ATTENUATOR = 6dB C WITH ATTENUATOR = 0dB C WITH ATTENUATOR = 6dB 4 3 2 53 52 IF (MHz) 200 250 300 350 400 LEXT (nH) 43 19 19 10 10 PIN_0dBFS (dBm) -2.5 -2.2 -2.2 -2.2 -2.2 Dual Tone Input Power (dBm) -8.5 -8.2 -8.2 -8.2 -8.2 f1 + f2 Spur (dBc) -69.5 -68.3 -73 -66.3 -68.5 Equivalent IP2 (dBm) 61 60 65 58.5 60 Above the IF pass band, the AD6676 is sensitive to high frequency blockers that can increase the noise floor due to jitter or generate an image component that falls back into the pass band. The AD6676 is also fairly insensitive to spurious tones falling in the alias regions occurring at FADC FIF because the AD6676 provides over 50 dB of alias rejection. Table 21 shows the typical alias rejection for different FADC and IF combinations. Because mixers often produce fixed large spurious at M x LO as well as its sum term of LO + FRF, determine if any of these spurs can fall in the alias regions and if so, add the appropriate level of filtering to suppress them below the receivers required spurious level. SHUNT C (pF) 62 1 0 100 200 300 400 500 600 700 FREQUENCY (MHz) 800 900 0 1000 12348-703 SHUNT R () The AD6676 benign input structure along with its low drive level requirements facilitates interfacing it to external driver circuitry. Figure 128 shows the equivalent parallel impedance for attenuator settings of 0 dB and 6 dB. Note that the slight variation in impedance between the different attenuator settings is an error source affecting the absolute accuracy of the attenuator settings. The AD6676 input also displays excellent S11 return loss over a wide frequency range, as shown in Figure 94. Figure 128. Typical Equivalent Parallel Impedance of AIN for Attenuator = 0 and 6 dB Settings Input Driver and Filter Considerations The input driver requirements, along with any additional filtering, are application dependent. Additional filtering maybe considered if any large signal content or blockers falling above or below the IF pass band of interest can cause desensitization by either increasing the ADC noise or spur floor. Below the IF pass band, the AD6676 is most sensitive to second harmonic content that is typically induced by the driver stage itself due to its limited IP2 performance. The AD6676 second-order nonlinearity contribution is typically on par with a balanced mixer and well below the contribution of a single-ended amplifier stage (with output balun) used for VHF applications. Table 20 shows the measured f1 + f2 spurious level and equivalent IIP2 for different IFs when dual tones are injected at -6 dBFS levels and at IF/2. Table 21. Typical Alias Rejection for Different IF and ADC Combinations FADC (MHz) 2000 2400 2800 3200 IF (MHz) 150 200 300 400 FADC - IF Alias Rejection (dBc) 58 53 51 51 FADC + IF Alias Rejection (dBc) 59 54 59 59 Because the required attenuation of out-of-band signal signals is application dependent, evaluate the AD6676 under the desired application conditions to understand the effects and determine what amount of filtering is required. In practice, a simple thirdorder low-pass roofing filter can provide adequate additional suppression against spurs falling in the alias regions as well as large signal signals falling a few 100 MHz above the IF pass band. Note that the AD6676EBZ includes an optional 500 MHz third-order low-pass filter (TDK MEA1210D501R) that may suffice for many applications. This small, 0302 size differential filter is also available with lower frequency options. Its effect on the pass band flatness is mimimal but provides provides additional suppression beyond 700 MHz. as shown in Figure 129 as well as in the alias region as shown in Table 22. Rev. D | Page 53 of 90 AD6676 Data Sheet harmonics that are sensitive to balance fall outside the pass band. Note that the second harmonic of the gain block still must fall outside the VHF pass band so that it can also be digitally filtered. 0 -5 Some additional considerations pertaining to the analog input are as follows: -10 -15 WITHOUT TDK LPF -20 -25 WITH TDK LPF -30 -35 0 100 200 300 400 500 600 700 800 900 1000 FREQUENCY (MHz) 12348-704 NORMALIZED STF RESPONSE (dBFS) 5 Figure 129. TDK Filter Has Minimal Effect on the Pass Band IF Response Table 22. Typical Alias Rejection for Different IF and ADC Combinations with TDK 500 MHz Low-Pass Filter Added FADC (MHz) 2000 2400 2800 3200 IF (MHz) 150 200 300 400 FADC - IF Alias Rejection (dBc) 82 77 71 74 FADC + IF Alias Rejection (dBc) 83 85 83 81 A 1:1 balun is required in applications where the last amplification stage is single-ended with a ZOUT of 50 . This is typically the case in a VHF receiver application where a gain block, such as the ADL5541 to ADL5545 series, precedes the AD6676 for preamplification. ADL5541 TO ADL5545 DEVICES VHF SIGNAL 1:1 BALUN (MABA-007159) 1nF AD6676 VIN+ 12348-077 VIN- 1nF Figure 130. RF Line-Up for Direct Sampling VHF Application For many RF receiver applications, this differential signal may originate from a RF-to-IF mixer whose output impedance often falls within a 50 to 200 range. A low order matching network that also serves as a low-pass roofing filter can compensate for the mismatch impedance. It is worth noting that the impedance mismatch between a source/load mismatch of 200 /60 and 100 /60 is approximately 1.5 dB and 0.3 dB, respectively. This low mismatch loss may be tolerable for some applications seeking a wide, low ripple IF pass band, especially considering the loss of a higher order matching network with finite Q components. Lastly, it is possible to reduce the ADC maximum input power requirements slightly to compensate for this low loss with minimal loss in dynamic range. Other receiver applications in the VHF band may prefer that the AD6676 directly digitize the signal. Typically, the radio lineup may include a low NF gain block whose single-ended output is converted to a differential output via an ac-coupled balun. The amplitude/phase balance requirements of balun can be relaxed (compared to traditional pipeline ADCs) because the even order AC coupling with 10 nF or greater capacitors to the VIN input is required to a maintain 1 V common-mode voltage. Note that this capacitor provides a high-pass response with the AD6676 input impedance and thus must be sized accordingly for low IF applications to prevent excessive droop on the lower pass band response. A series 10 resistor and 0.1 F decoupling capacitor is recommended between the 2.5 V supply and first resonators to provide additional filtering of supply induced noise and ADC common-mode currents. The feedback DAC (operating up to 3.2 GHz) also generates high frequency content (that is, images, clock feedthrough and shaped noise) that is ideally absorbed by the internal source follower. Due to its finite impedance at the higher frequencies, a small amount of this undesired signal content leaks through the attenuator path back to the VIN input. Passive mixers are particularly susceptible to this signal content due to poor isolation between the IF and RF ports while passive mixers with on-chip IF amps and active mixers provide a greater degree of reverse isolation. A simple third-order roofing filter typically provides sufficient rejection to suppress these ADC artifacts while also suppressing the larger M x N artifacts of the mixer. Note that this filter must be designed as two single-ended, pi network filters with shunt capacitors located next to the VIN pins to steer this undesired signal content to ground. Also, use care in component selection and layout to reduce parasitics that can cause unanticipated peaking in the stop-band region of the filter response. CLOCK INPUT CONSIDERATIONS The AD6676 - ADC operates with an internal ADC clock rate (FADC) between 2.0 GSPS to 3.2 GSPS. The clock signal can originate from an external clock source or, alternatively, from its on-chip clock synthesizer. Consider an external clock source if the on-chip synthesizer phase noise or spurious level is not deemed sufficient or if the desired FADC falls below the 2.94 GHz to 3.2 GHz range of the VCO. Referring to Figure 60, the selfbiased clock receiver is configured as either a differential or singleended receiver, depending on whether the clock synthesizer is disabled. In either case, the external clock source must be ac coupled to the AD6676 CLK input and meet the minimum specified input level and slew rate. Also, clock jitter and phase noise must always be a concern in selecting the clock source. When the clock synthesizer is enabled, the CLK inputs are connected to CMOS inverters as shown in Figure 60. These inverters are self-biased at approximately 0.55 V and present an input resistance exceeding 1.2 k when Bit 2 of Register 0x2BB is set. Rev. D | Page 54 of 90 Data Sheet AD6676 When the clock synthesizer is disabled, the CLK inputs are connected to a high speed differential clock receiver with on-chip 100 termination to simplify interfacing to CML, LVPECL, or sinusoidal clock sources. The clock signal is typically ac-coupled to the CLK+ and CLK- pins via an RF balun or capacitors. These pins are biased internally (see Figure 60) at approximately 700 mV and require no external bias. The equivalent shunt impedance of the CLK input is shown in Figure 131. It is recommended to use a 100 differential transmission line to route the clock signal to the CLK+ and CLK- pins due to the high frequency nature of the signal. 130 INSTALL 100 DIFFERENTIAL RESISTOR ONLY WHEN CLK SYN IS ENABLED HMC7044, AD9528 OR ADCLK925 CLK+ 10nF PECL DRIVER AD6676 10nF CLK- 240 240 1.0 110 0.6 100 0.4 90 0.2 80 0 70 Figure 133. Differential PECL Sample Clock Using the HMC7044, AD9528, and ADCLK925 0.8 CAPACITANCE (pF) REAL SHUNT CAPACITANCE SHUNT 120 -0.2 60 50 2.0 2.5 3.0 -0.4 4.0 3.5 FREQUENCY (GHz) 12348-705 REAL SHUNT () A single-ended CMOS or differential ac-coupled PECL/HSTL clock signal can be delivered via clock generation and distribution ICs such as the Analog Devices HMC7044, AD9528, and ADCLK925. A PECL clock signal is recommended when providing an RF clock input signal to the AD6676 or in applications that require deterministic latency or synchronization while using the internal clock synthesizer of the AD6676. Figure 133 shows a simple differential interface in which the AD6676 interfaces to the PECL output available from these ICs. The HMC7044 is an excellent choice for JESD204B clock generation and multichip synchronization because it also generates a very low phase noise RF clock from 2.4 GHz to 3.2 GHz for multiple AD6676 devices. 12348-081 A single-ended clock source need only be ac coupled to the CLK+ input because the inverter output for CLK- input is not used. For CMOS drivers, the addition of a 33 series resistor is recommended to dampen the response for long trace lengths. For a differential clock source, such as an LVDS or PECL source, the addition of a 100 external termination resistor across the CLK pins is recommended to minimize any reflections that result from distorting the clock input waveform. Alternatively, PLL clock synthesizers with on-chip VCOs such as the ADF4351, the ADF4355-2, and HMC1034 also make excellent RF clock sources when multichip synchronization is not required. The CML outputs of these devices allow a simple interface as shown in Figure 134. Figure 135 compares the close in phase noise between the ADF4351, the ADF4355-2, the HMC7044, the AD6676 clock synthesizer, and the R&S SMA100A for a near full-scale sine wave at 300 MHz. Note that the phase noise improvement offered by the high quality RF generator only becomes evident below 400 kHz when compared to the ADF4351. Figure 131. Equivalent Shunt Differential Input Impedance of the CLK Pins with the Clock Synthesizer Disabled 3.9nH PLL FREF VCO REFOUTA+ AD6676 CLK+ CLK- REFOUTA- ADF4351 ADF4355-2 1nF REFOUTB+ REFOUTB- 1nF 0.8V p-p 12348-079 VVCO DIV-BY-2N Figure 132 shows a single-ended clock solution for the AD6676 when its clock synthesizer is disabled. The low phase noise singleended source can be from an external VCXO. A ceramic RF chip 1:2 ratio balun creates the differential clock input signal. The balun must be specified to have low loss (that is, less than 2 dB) at the clock frequency of interest. The single-ended clock source must be capable of 0 dBm drive capability to ensure adequate signal swing into the clock input. Figure 134. Differential CML Driver from the ADF4351 and the ADF4355-2 100pF 100pF AD6676 CLK+ CLK- JT 4000BL14100 100pF 12348-078 CLOCK INPUT Figure 132. Balun Coupled Differential Clock Rev. D | Page 55 of 90 AD6676 Data Sheet -110 Figure 136 shows a normalized image graph (relative to fDATA_IQ) showing the image location relative for a given input frequency. ADF4351 When N > 1, spurious content is often at lower magnitude than other spurious thus often can be ignored. The exception is when fIN falls below the IF pass band such that its lower order harmonics may fall within the pass band (that is, IF/2 and IF/3). -120 -125 AD6676 CLK SYN -130 -135 ADF4355-2 R&S SMA100A 4.5 M=3 -140 M=2 M=1 4.0 HMC7044 0.1 FREQUENCY OFFSET (MHz) 1 Figure 135. Close In Phase Noise Comparison for Different Analog Devices Clock Sources when Compared to the R&S SMA100A and the AD6676 Clock Synthesizer (IF = 300 MHz, BW = 40 MHz, FADC = 3.2 GHz, L = 19 nH) IF FREQUENCY PLANNING 3.0 M=7 2.5 2.0 M=6 1.5 1.0 The - ADC can achieve exceptional SFDR performance over a wide IF frequency range because its high oversampling ratio prevents low order harmonics from aliasing into the IF pass band. Higher order harmonics that do alias back are typically of much lower magnitude, with the shuffling option further reducing their levels. However, finite isolation between the - ADC and the digital block causes additional spurious signals that are a function of the output data rate, fDATA_IQ, and input frequency, fIN. Specifically, the feedback DACs in the - ADC suffer from digital contamination of its clock signal. Therefore, the same equation used to predict spurious locations on high speed DACs with digital interpolation filters applies. Equation 15 defines this relationship with the spur location falling at fMN. fMN = (M x fDATA_IQ) (N x fIN) M=8 3.5 (15) where: M is the digital induced harmonic content from internal clocks. N is the harmonics from the - ADC. When N = 0, signal independent spurs fall at integer multiples of fDATA_IQ. Table 23 shows the measured M x fDATA_IQ spurious levels (dBFS) for different IF frequencies and decimation factors with fDATA_IQ equal to 100 MSPS and 200 MSPS. All of the M x fDATA_IQ regions display low spurious with the exception of 200 MHz. This is because a large portion of digital circuitry is clocked at FADC/16 for DEC_MODES of 1 and 3 or FADC/12 for DEC_MODES of 2 and 4. As a result, the M = 2 spur is dominant when operating at the higher decimation factors of 32 and 24 whereas the M = 1 spur is dominant when operating at the lower decimation factors of 16 and 12. When N = 1, signal dependent spurs falls at integer multiples of fDATA_IQ. These M x N spurs are called images because they have a 1:1 relationship in amplitude and frequency with the input signal, fIN. Note that the magnitude of some images can also vary slightly between power cycles, due to different phase relationships among internal clock dividers upon device initialization. M=2 0.5 0.5 1.0 M=3 1.5 2.0 M=4 2.5 3.0 M=5 3.5 4.0 4.5 NORMALIZED INPUT FREQUENCY 12348-082 -150 -155 0.01 NORMALIZED IMAGE LOCATION -145 12348-080 PHASE NOISE @ IF = 300MHz (dBc/Hz) AVG = 300 -115 Figure 136. Image Location for Different M Factors Normalized to fDATA_IQ Table 23. Measured Spurious Levels at Different IFs Where M x fDATA_IQ Falls On for fDATA_IQ of 100 MSPS and 200 MSPS fDATA_IQ 100 MSPS DEC_MODE = 1 DEC_MODE = 2 200 MSPS DEC_MODE = 3 DEC_MODE = 4 1 IF = 100 MHz Spurious Levels (dBFS) IF = IF = IF = 200 MHz 300 MHz 400 MHz <-100 -100 -81 -79 <-110 <-110 -97 N/A1 <-110 <-110 -81 -77 <-110 <-110 -90 N/A1 N/A means not applicable. Because the image spurs are also at low levels, the AD6676 offers a wide range of suitable IFs for a given output data rate, fDATA_IQ. Even IFs that are situated in a region where the worst M x fDATA_IQ spurious condition described in Table 23 can be used because they remain at a fixed location and remain signal independent. Similar to the LO feedthrough issue in a direct conversion IQ receiver, a slow digital tracking loop in the host processor can be used to nullify it. Figure 137 and Figure 138 show a case where the IF of 200 MHz was selected for an fDATA_IQ of 200 MSPS and 100 MSPS such that dominant spur falls exactly at the IF center. As shown in Figure 136, the IF is positioned at a normalized fDATA_IQ of 1 or 2 for 200 MSPS and 100 MSPS operation, thus explaining why the image term is M = 2 or 4. Note that the image spur is quite low for M = 2 and can be further improved by selecting a higher decimation factor (DEC_MODE of 3 vs. 1) that results in the M = 4 image. Rev. D | Page 56 of 90 Data Sheet AD6676 0 0 -10 -10 fIN = 180MHz -40 -50 M = 1, N = 0 SPUR @ -81dBFS -60 M = 2, N = -1 SPUR @ -88dBc -70 -80 -90 -60 -70 -80 -90 -100 -100 -110 NBW = 9.2kHz 170 180 190 200 210 220 230 240 250 Figure 137. Image Spur for fDATA_IQ = 200 MSPS (DEC_MODE = 3) Attributed to M = 2, N = -1 0 NBW = 9.2kHz 210 220 230 240 250 260 270 INPUT FREQUENCY (MHz) 280 290 300 Figure 139. Digital Induced Spurs for an IF That Is Centered Between fDATA_IQ and 1.5 x fDATA_IQ with fDATA_IQ = 200 MSPS PCB DESIGN GUIDELINES -10 fIN = 180MHz (-1dBFS) -30 -40 -50 M = 1, N = 0 SPUR @ -81dBFS -60 -70 M = 4, N = -1 SPUR @ -96dBc -80 -90 -100 -110 NBW = 9.2kHz 160 170 180 190 200 210 220 230 240 INPUT FREQUENCY (MHz) 250 12348-084 -120 150 -120 200 12348-083 160 INPUT FREQUENCY (MHz) SPUR (dBFS/NBW) -40 -50 -110 -20 (-1dBFS) -30 SPUR (dBFS/NBW) SPUR (dBFS/NBW) -30 -120 150 fIN = 238MHz -20 (-1dBFS) 12348-085 -20 Figure 138. Reduction in Image Spur When fDATA_IQ is Reduced to 100 MSPS IF pass band regions that remain free of any of these spurs exist in the following regions for a swept input tone across its pass band: (M - 0.5) x fDATA_IQ < IF Pass Band < M x fDATA_IQ The design of the PCB is critical in achieving the full performance of the AD6676. The AD6676EBZ evaluation board, used for characterizing the AD6676 ac performance, serves as an example of a possible layout that uses 0.1 mm (4 mil) through-hole vias under the device. Figure 140 shows the top side PCB layout of the region surrounding the AD6676 where all the critical analog input/ outputs, digital input/outputs, and passive components reside. An alternative top side layout is shown in Figure 141 that avoids any through-hole vias under the device. Because this modified layout resulted in only a slight degradation in IMD performance, consider this layout option if via placement under the device is not possible. Note the following: (16) Or M x fDATA_IQ < IF Pass Band < (M + 0.5) x fDATA_IQ (17) Note that because these spur free regions have a bandwidth of 0.5 x fDATA_IQ, it is often desirable to use a higher fDATA_IQ rate (that is, lower decimation factor) to support larger IF bands. Figure 139 shows a spur free region swept SFDR less than -95 dBFS with fDATA_IQ = 200 MSPS and BW = 100 MHz with the IF now centered at 250 MHz. Selecting an IF situated at 350 MHz and BW = 100 MHz also produces similar results. Rev. D | Page 57 of 90 The PCB is a 6-layer board (1.6 mm thick) based on FR4 dielectric that avoids any expensive options, such as micro, hidden or blind vias, thus allowing cost effective manufacturing. Critical analog and digital high speed signal paths are routed on the first layer with controlled impedances. The lower speed CMOS digital input/outputs are placed on the back side sixth layer. A single solid ground plane is used as the second layer underneath the AD6676. The dielectric spacing is 8 mil to establish controlled impedances with the critical signal layer above. The third and fourth layers are dedicated power planes used to isolate the different AD6676 supply domains, and the fifth layer is a solid ground plane. The dielectric spacing between the second and third layer and the fourth and fifth layer is 3 mil to increase the distributed decoupling capacitance for each supply domain. Special consideration was given to via placement, ground fill, and power supply plane layout to main low thermal and electrical impedances. AD6676 12348-086 All critical passive components, such as dc blocking and power supply decoupling capacitors, are 0201 size and placed on top side of the PCB. Two 0201 decoupling capacitors (0.001 F and 0.1 F) are placed adjacent to supply pins with the lower value placed closer to the AD6676. The analog 1.1 V supply pins of the AD6676 share a common 1.1 V supply domain and are tied together below the device. VSS2OUT (Pin G7) must be connected to VSS2IN (Pin F6) on the top side layer of the PCB. The alternative layout shown in Figure 141 uses 0.2 mm through-hole vias just outside of the AD6676 package for all supply and ground domains with all of the 1.1 V analog supply domains (VDD1, VDDL, VDDC, and VDDQ) connected to each other providing a low impedance path to the critical inner VDD1 and VDDL balls. This alternative layout also avoids any narrow signal traces to inner row balls (with exception of CSB) by using a 3-wire SPI interface (with the SDIO, RESETB, AGC4, and AGC3 balls left open). Note that the thin inner trace for CSB (positioned between the SCLK and SYNCINB- balls) could have been avoided by running a wider straight trace instead of connecting the CSB and SYNCINB- balls because, by default, the SYNCINB input is configured for a CMOS input with only SYNCINB+ used for signaling (and SYNCINB- ignored). Figure 140. AD6676EBZ PCB Top Side Layout Example 12348-800 Data Sheet Figure 141. Alternative PCB Top Side Layout Example That Avoids a Through Hole Via under the Device Additional information specifically pertaining to the WLCSP package considerations is contained in the AN-617 Application Note. This application note covers PCB design guidelines, assembly, reliability, and rework in detail. Rev. D | Page 58 of 90 Data Sheet AD6676 POWERING THE AD6676 ADP1752-1.1 The AD6676 requires the following analog and digital power supplies with no restrictions on the power supply sequencing order: An analog 2.5 V and 1.1 V supply A digital 1.1 V and digital input/output supply of 1.8 V to 2.5 V The current consumption from the different analog and digital supply domains does not vary much over the specified 2.0 GHz to 3.2 GHz ADC clock rate range nor the digital decimation factor and number of JESD204B lanes used. Table 24 shows the dependency of a typical device as these settings are modified with the IF and BW remaining fixed at 250 MHz and 75 MHz, respectively. Figure 142 shows the recommended method used on the AD6676EBZ where a universal 3.3 V supply is available. Note that various analog and digital supply domains within the AD6676 are grouped together to reduce the external LDO requirements. A high efficiency step-down regulator, such as the ADP2164, is used to generate a 1.6 V output that drives separate low drop-out LDOs for the analog VDD1 and digital VDDD supplies. 1.6V ADP1752-1.1 3.3V ADP1752-2.5 VDD2, VDD2NV ADP1752-1.8 VDDIO VDDD, VDDHSI 12348-087 ADP2164 VDD1, VDDL, VDDC, VDDQ Figure 142. Low Noise Power Solution for the AD6676 Separate LDOs for the 1.1 V analog and digital supplies provide greater isolation between these critical supply domains as well as reduce the IR drops across ferrite beads that provide further isolation. High quality LDOs that exhibit better PSSR characteristics at the switching regulators operating frequency are preferable. Note that the digital VDDIO supply of the AD6676 is only used for the CMOS SPI and AGCx input/output pins thus it can be tied to the same supply domain used by the host that is connected to these pins. Alternatively, the ADP223 dual output LDO can be used instead of the ADP1752-2.5 and ADP1752-1.8. On the analog 1.1 V supply, amplitude modulation can result in phase modulation via the clock supplies of the AD6676 (VDDC, VDDQ). Table 24. Current Consumption Variation as FADC Is Varied from 3.2 GHz to 2.0 GHz Supply Current IVDD1+ IVDDL IVDDC + IVDDQ IVDD2 + IVDD2NV IVDDD IVDDHSI Conditions Not applicable Not applicable Not applicable Decimate by 16 Decimate by 32 Two lane One lane 3.2 GHz 371 60 143 152 155 168 166 2.8 GHz 364 59 140 144 150 168 167 Rev. D | Page 59 of 90 fCLK 2.4 GHz 357 56 139 131 135 168 167 2.0 GHz 351 52 139 100 106 158 161 Unit mA mA mA mA mA mA mA AD6676 Data Sheet -98 -100 -102 -104 -106 -78 -108 -80 -110 100 150 200 250 300 350 400 450 500 Figure 144. Sideband Spur Level for 1 mV p-p, Continuous Wave Tone Injected on Analog 2.5 V Supply Domain -84 -86 400MHz 800MHz 1600MHz 3200MHz -88 -90 100 400MHz 800MHz 1600MHz 3200MHz IF INPUT FREQUENCY (MHz) -82 150 200 250 300 350 400 IF INPUT FREQUENCY (MHz) 450 500 12348-706 SIDEBAND LEVEL (dBc) -76 -96 12348-707 -74 -94 SIDEBAND LEVEL (dBc) Figure 143 and Figure 144 show the measured sideband level in dBc that results if a 1 mV p-p continuous wave tone has frequencies common among switching regulators are injected onto the 1.1 V and 2.5 V analog supplies. Note that the sideband level increases at roughly 6 dB per octave in IF frequency for the 1.1 V supply domain case because the supply noise results in PM modulation that affects the clock jitter. Figure 143. Sideband Spur Level for 1 mV p-p, Continuous Wave Tone Injected on Analog 1.1 V Supply Domain On the digital 1.1 V supply, amplitude modulation on the JESD204B high speed serializer supply (VDDHSI) can negatively impact the eye opening of the digital data output stream. For these reasons, low noise LDOs, such as the ADP1752, that have a worst-case accuracy of 2% over line, load, and temperature are used for the analog VDD2 and VDD1 supplies. The same regulator is used for the digital VDDD for its low dropout characteristics, power supply rejection ratio, and load capability. Although the digital VDDD is used for the less critical VDDIO supply, a smaller, lower cost regulator such as the ADP121, can also be used to supply 1.8 V. Rev. D | Page 60 of 90 Data Sheet AD6676 AD6676 START-UP INITIALIZATION ALL REGISTERS RETURNED TO DEFAULT HARDWARE OR SOFTWARE RESET On power-up of the AD6676, a host processor is required to initialize and configure the AD6676 via its SPI port. Figure 145 shows a flowchart of the sequential steps required to bring the AD6676 to an operational state. The number of SPI writes and total initialization time is dependent on whether the clock synthesizer is used, as well as any additional configuration associated with the AGC features or its pin configurations. Note that wait states are required during different steps in the initialization process to allow various actions, such as calibration and tuning, to be completed before moving to the next step. WAIT (2ms) INITIALIZE RF CLK PATH NO CLK SYN? YES INITIALIZE CLK SYN PROGRAM CONFIGURATION SETTINGS JESD204B CONFIGURATION ADC PARAMETERS Table 26 shows the minimum SPI writes required to enable the AD6676. Note the following in the sequence of steps shown in Table 26: RUN RESON1 CAL WITH DEC_MODE=1 WAIT (400ms) CAL OK? RESON1 TUNE ERROR (MAKE TWO MORE ATTEMPTS) NO YES PROGRAM DECIMATION MODE RUN ADC CAL + JESD204B INITIALIZATION CALIBRATION + TUNING WAIT (400ms) CAL OK? ADC CAL/TUNE ERROR (MAKE TWO MORE ATTEMPTS) NO YES AD6676 OPERATIONAL PROGRAM OPTIONAL SETTINGS AGC CONFIGURATION ADC SHUFFLER 12348-088 The example SPI writes pertain to the following settings: FADC = 3.200 GHz, FO = 250 MHz, BW = 100 MHz, IDAC1FS = 2 mA, MRGN_L = MRGN_U = 10 MHz, MRGN_IF = 1 MHz, fDATA_IQ = 200 MSPS with decimate by 16, and fREF = 200 MHz with the clock synthesizer enabled. Step 3 refers to Table 28 for the necessary SPI writes when the clock synthesizer is enabled or disabled, respectively. Example AGC parameters are included in Table 29 but are nonessential to device operation. The RESON1 calibration for the ADC occurs first with default DEC_MODE setting. DEC_MODE is updated to the user specified setting prior to JESD204B calibration. ADC and JESD204B calibration and initialization must be successful on first attempt. However, Step 24 and Step 30 are included to provide coverage against external events (supply or clock glitch) that can corrupt this process. The AD6676EVB software GUI has an option that automatically generates and saves the series of SPI writes in the .csv file format, as shown in Table 25, which is the preferred method for generating the AD6676 SPI write initialization sequence. Note the following: The SPI sequence can be shorter when the AD6676EVB development platform is connected to the PC because the software also performs a SPI read back and then only writes to those SPI registers that have been changed from its default setting. To generate a SPI initialization sequence for an alternative development platform, ensure that the AD6676EVB development platform is disconnected from the PC When the software GUI is configured for the profile feature, Register 0x115 and Register 0x118 specify the calibration and ADC profile, respectively, that pertain to the specific ADC application parameter settings in Register 0x100 thru Register 0x109 that follow. A SPI write of 0x01 to Register 0x116 follows to initiate the ADC tuning. This process repeats itself for the remaining specified profiles. Figure 145. Flowchart for Initialization and Configuration of the AD6676 Table 25. Example of Saved .CSV File Format Register Address 0x000 0x2A5 0x2A0 ... ... Rev. D | Page 61 of 90 Write 0x99 0x05 0xC0 ... ... AD6676 Data Sheet Table 26. SPI Initialization Example, fCLK = 3.2 GHz, FIF = 250 MHz, BW = 100 MHz, IDAC1FS = 2 mA, MRGN_L = MRGN_U = 10 MHz, MRGN_IF = 1 MHz, fDATA_IQ = 200 MSPS with Decimate by 16 Step 1 2 3 Address (Hex)1 0x000 Write Value1 0x99 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 0x1E7 0x1C0 0x1C1 0x1C3 0x1C4 0x1C5 0x1EC 0x100 0x101 0x102 0x103 0x104 0x105 0x106 0x107 0x108 0x109 0x10A 0x116 0x04 0x01 0x05 0x01 0x01 0x0F 0xBD 0x80 0x0C 0xFA 0x00 0x64 0x00 0x13 0x0a 0x0a 0x01 0x20 0x0A 0x11A 0x11A 0x01 0x00 27 0x140 0x03 28 29 0x116 0x17 0x11A 0x11A 0x01 0x00 24 25 26 30 31 32 33 1 Comments Software reset, 4-wire SPI. Wait 2 ms for SPI initialization after reset. CLK path or CLK SYN initialization (see Table 28 for using external RF clock; refer to Table 27 for using internal CLK SYN.) Select LVDS input for SYNCINB receiver. JESD204 (DID = 1, optional). JESD204 (BID = 5, optional). JESD204B (SCR = 0, L = 2). JESD204B (F = 2). JESD204B (K = 16). Configure PHY output driver. Set FADC to 3200 MHz. Set FADC to 3200 MHz. Set the IF to 250 MHz. Set the IF to 250 MHz. Set the BW_0 to 100 MHz. Set the BW_1 to 0 MHz. Set LEXT to 19 nH. Set MRGN_L to 10 MHz. Set MRGN_U to 10 MHz. Set MRGN_IF to 1 MHz. Set IDAC1FS to 2 mA, resulting in PIN_0dBFS = -8 dBm. Initiate RESON1 calibration. Wait 250 ms for fCLK = 3.2 GHz. Note that the wait time scales with fCLK proportionally such that the wait = 400 ms for fCLK = 2 GHz. Read back Register 0x117 to see if Bit 0 has been set to 1 indicating ADC calibration is complete. If not, proceed to Step 25. Force end of calibration (toggle Bit 0). Force end of calibration (toggle Bit 0). Return to Step 22 and attempt again. Make two attempts before breaking out of loop if the calibration problem persists. Set DEC_MODE to user defined setting of decimate by 16. Note that coarse and fine NCO settings (SPI Register 0x141 and SPI Register 0x142) are automatically set based on FADC and IF settings (Register 0x100 to Register 0x103). Calibrate and initiate ADC; set-up and initiate JESD204B. Wait 250 ms for fCLK = 3.2 GHz. Note that wait time scales with fCLK proportionally such that the wait = 400 ms for fCLK = 2 GHz. Read back Register 0x117 to see if Bit 0 has been set to 1 indicating ADC calibration is complete. If not, proceed to Step 31. Force end of calibration (toggle Bit 0). Force end of calibration (toggle Bit 0). Return to Step 28 and attempt again. Make two attempts before breaking out of loop if the calibration problem persists. Insert the optional AGC and nondefault shuffler settings (see Table 29 and Table 30 for an example). Cells in the Address (Hex) column and Write Value column were left intentionally blank. Rev. D | Page 62 of 90 Data Sheet AD6676 Table 27. SPI CLK SYN Initialization Example, fCLK = 2.94912 GHz, fREF = 122.88 MHz (Suitable for Decimation by 24) Step 1 2 3 4 5 6 7 8 9 Address (Hex)1 0x2A1 0x2A2 0x2A5 0x2AC 0x2B7 0x2BB 0x2A0 0x2AB Write Value1 0x60 0x00 0x08 0x18 0xF0 0x7D 0x7D 0xC5 10 0x2AD 0x80 1 Comments Set the integer-N value. Set the integer-N value. Reset VCO calibration. Set the charge pump current (see Table 12). Configure VCO. Set the reference divider to DIV = 2, such that fPFD = 61.44 MHz (see Table 11). Enable CLKSYN and the ADC clock. Start VCO calibration. Wait at least 400 ns because fPFD = 50 MHz. Register 0x2BC, Bit 1 = 0 indicates that VCO calibration is done. Start charge pump calibration. Wait at least 800 ns because fPFD = 50 MHz. Register 0x2BC, Bit 0 = 1 indicates that the charge pump is done. Register 0x2BC, Bit 3 = 1 confirms that the PLL is locked. Cells in the Address (Hex) column and Write Value column were left intentionally blank. Table 28. SPI fCLK Initialization Step 1 2 Address 0x2A5 0x2A0 Write Value 0x05 0xC0 Comments Select RF clock path Enable RF clock receiver and ADC clock Table 29. SPI AGC Initialization Example Step 1 2 3 Address 0x181 0x182 0x19E Write Value 0x00 0x06 0x13 4 5 6 7 8 9 10 11 0x19B 0x19C 0x193 0x194 0x197 0x198 0x199 0x19A 0x04 0x06 0x00 0x0d 0x00 0x09 0x01 0x02 Comments Set ATTEN_VALUE_PIN0 to 0 dB. Set ATTEN_VALUE_PIN1 to 6 dB. Enable FLAG1 and 0 on AGC4 and AGC3 pins, respectively. Also, logical OR of ADC reset with a peak detect threshold flag. Select AGC Flag 0 above Peak Threshold 0. Select AGC Flag 1 below low threshold. Peak Threshold 0 set to -3 dBFS. Peak Threshold 0 set to -3 dBFS. Low Threshold set to -15 dBFS. Low Threshold set to -15 dBFS. Low threshold dwell time mantissa. Low threshold dwell time exponent. Table 30. SPI Shuffler Initialization Example Step 1 2 Address 0x342 0x343 Write Value 0x3F 0xFF Comments Shuffle every two clock cycles with a threshold of 3. Rev. D | Page 63 of 90 AD6676 Data Sheet SERIAL PORT INTERFACE (SPI) SPI REGISTER MAP DESCRIPTION SPI OPERATION The AD6676 contains a set of programmable registers (described in the Register Memory Map section) that initialize and configure the device for its intended application. Note the following points when programming the AD6676 SPI registers: The serial port of the AD6676 shown in Figure 146 has a 3- or 4-wire SPI capability, allowing read/write access to all registers that configure the internal parameters of the device. It provides a flexible, synchronous serial communications port, allowing easy interface to most industry-standard FPGAs and microcontrollers. The 1.8 V to 2.5 V serial input/output is compatible with most synchronous transfer formats. Registers pertaining to similar functions are typically grouped together and assigned adjacent addresses. Bits that are undefined within a register must be assigned a 0 when writing to that register. Do not write to registers that are undefined. A hardware or software reset is recommended on powerup to place SPI registers in a known state. SDO (PIN H6) SDIO (PIN K8) AD6676 SCLK (PIN K7) SPI PORT 12348-089 CSB (PIN J6) A SPI initialization routine is required as part of the boot process. See Table 26 for an example procedure. Figure 146. AD6676 SPI Port Reset Issuing a hardware or software reset places the AD6676 SPI registers in a known state. Both types of resets are similar in that they place SPI registers to their default states as described in Table 32, with the notable exception that a software reset does not affect Register 0x000. A hardware reset can be issued from a host or external supervisory IC by applying a low pulse with a minimum width of 40 ns to the RESETB pin (Pin G6). RESETB can also kept be left open if unused because it has an internal pull-up resistor. After issuing a reset, the SPI initialization process need only write to registers that are required for the boot process as well as any other register settings that must be modified, depending on the target application. Although the AD6676 does feature an internal power on reset (POR), it is still recommended that a software or hardware reset be implemented shortly after power-up. The internal reset signal is derived from a logical OR operation from the internal POR signal, the RESETB pin, and the software reset state. A self clearing software reset can be issued via the reset bit (Register 0x00, Bit 7). It is also recommended that the bit settings for Bits[7:4] be mirrored onto Bits[3:0] for the instruction cycle that issues a software reset. Table 31. SPI Registers Pertaining to SPI Options Address (Hex) 0x000 Bit 7 6 4 The default 4-wire SPI interface consists of a clock (SCLK), serial port enable (CSB), serial data input (SDIO), and serial data output (SDO). The inputs to SCLK, CSB, and SDIO contain a Schmitt trigger centered about VDDIO/2. The maximum frequency for SCLK is 40 MHz. The SDO pin is active only during the transmission of data and remains three-stated at any other time. A 3-wire SPI interface can be enabled by clearing the SDIO_DIR bit (Register 0x000, Bit 4). This causes the SDIO pin to become bidirectional such that output data only appears on the SDIO pin during a read operation. The SDO pin remains three-stated in a 3-wire SPI interface. Instruction Header Information MSB I_15 R/W LSB I_14 A14 I_13 A13 I_12 A12 ... ... ... ... I_01 A1 I_00 A0 A 16-bit instruction header must accompany each read and write operation. The MSB is a R/W indicator bit with logic high indicating a read operation. The remaining 15 bits specify the address bits to be accessed during the data transfer portion. The eight data bits immediately follow the instruction header for both read and write operations. For write operations, registers change immediately on writing to the last bit of each transfer byte. Description Software reset SPI Enable SPI LSB first Enable 4-wire Rev. D | Page 64 of 90 Data Sheet AD6676 The AD6676 serial port can support both most significant bit (MSB) first and least significant bit (LSB) first data formats. Figure 147 illustrates how the serial port words are formed for the MSB first and LSB first modes. The bit order is controlled by the LSB_FIRST bit (Register 0x000, Bit 6). The default value is 0, MSB first. When the LSB_FIRST bit is set high, the serial port interprets both instruction and data byte LSBs first. INSTRUCTION CYCLE Figure 149 illustrates the timing for a 3-wire read operation to the SPI port. After CSB goes low, data (SDIO) pertaining to the instruction header is read on the rising edges of SCLK. A read operation occurs if the read/not write indicator is set high. After the address bits of the instruction header are read, the eight data bits pertaining to the specified register are shifted out of the SDIO pin on the falling edges of the next eight clock cycles. DATA TRANSFER CYCLE SCLK A1 A0 D7 INSTRUCTION CYCLE CSB D6 D1 Figure 150 illustrates the timing for a 4-wire read operation to the SPI port. The timing is similar to the 3-wire read operation with the exception that data appears at the SDO pin only, whereas the SDIO pin remains at high impedance throughout the operation. The SDO pin is an active output only during the data transfer phase and remains three-stated at all other times. D0 DATA TRANSFER CYCLE SCLK A0 A1 A2 A14 R/W D0 D1 D6 Lastly, the SPI port must not be active during periods when the full dynamic performance of the converter is required. Because the SCLK, CSB, and SDIO signals are typically asynchronous to the ADC clock, noise from these signals can degrade converter performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD6676 to keep these signals from transitioning at the converter input pins and causing unwanted spurious signals. D7 12348-090 SDATA Figure 147. SPI Timing, MSB First (Upper) and LSB First (Lower) Figure 148 illustrates the timing requirements for a write operation to the SPI port. After the serial port enable (CSB) signal goes low, data (SDIO) pertaining to the instruction header is read on the rising edges of the clock (SCLK). To initiate a write operation, the read/not write bit is set low. After the instruction header is read, the eight data bits pertaining to tS tSCLK CSB tH tLOW tHIGH SCLK tDS tDH SDIO A14 R/W A13 A0 D7 D6 D1 D0 12348-091 R/W A14 A13 Figure 148. SPI Write Operation Timing tS tSCLK CSB tLOW tHIGH SCLK tDS tACCESS tDH SDIO R/W A14 A2 A1 A0 D7 tZ D6 D1 D0 12348-092 SDATA Figure 149. SPI 3-Wire Read Operation Timing tS CSB tSCLK tLOW tHIGH SCLK tDS SDIO tDH R/W A14 A2 A1 A0 tZ tACCESS SDO D7 D6 D1 Figure 150. SPI 4-Wire Read Operation Timing Rev. D | Page 65 of 90 D0 12348-093 CSB the specified register are shifted into the SDIO pin on the rising edge of the next eight clock cycles. AD6676 Data Sheet REGISTER MEMORY MAP AND DETAILS REGISTER MEMORY MAP Note that all address and bit locations that are not included in Table 32 are not currently supported for this device. Table 32. Register Summary Reg Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x000 SPI_CONFIG SW_RESET LSB_FIRST RESERVED SDIO_DIR SDIO_DIR RESERVED LSB_FIRST SW_RESET 0x002 DEVICE_CONFIG RESERVED PD_MODE 0x003 CHIP_TYPE CHIP_TYPE 0x004 CHIP_ID0 CHIP_ID0 0x005 CHIP_ID1 CHIP_ID1 0x006 GRADE_REVISION REVISION GRADE 0x00C VENDOR_ID0 VENDOR_ID0 0x00D VENDOR_ID1 VENDOR_ID1 BP - ADC Configuration Settings 0x100 FADC_0 FADC_0 0x101 FADC_1 FADC_1 0x102 FIF_0 FIF_0 0x103 FIF_1 FIF_1 0x104 BW_0 BW_0 0x105 BW_1 BW_1 0x106 LEXT LEXT 0x107 MRGN_L MRGN_L 0x108 MRGN_U MRGN_U 0x109 MRGN_IF MRGN_IF 0x10A IDAC1_FS IDAC1_FS BP - ADC Calibration/Profile 0x115 CAL_CTRL RESERVED CAL_PROFILE 0x116 CAL_CMD RESERVED INIT_NTF_OP INIT_JESD RESON1_CAL FLASH_CAL INIT_ADC TUNE_ADC 0x117 CAL_DONE RESERVED CAL_DONE 0x118 ADC_PROFILE RESERVED ADC_PROFILE 0x11A FORCE_END_CAL RESERVED FORCE_END_CAL Digital Signal Path 0x140 DEC_MODE RESERVED DEC_MODE 0x141 MIX1_TUNING RESERVED MIX1_TUNING 0x142 MIX2_TUNING MIX2_TUNING 0x143 MIX1_INIT RESERVED MIX1_INIT 0x144 MIX2_INIT_LSB MIX2_INIT_LSB 0x145 MIX2_INIT_MSB RESERVED MIX2_INIT_MSB 0x146 DP_CTRL RESERVED NOT_2S_COMPL Power Control 0x150 STANDBY RESERVED STBY_ STBY_CLK_PLL STBY_JESD_ STBY_JESD_ STBY_FRAMER STBY_DATAPATH STBY_DIGCLK VSS2GEN PLL PHY 0x151 PD_DIG RESERVED PD_FRAMER PD_DATAPATH PD_DIGCLK 0x152 PD_PIN_CTRL RESERVED PD_PIN_EN RESERVED PD_PIN_SEL 0x250 STBY_DAC STBY_DAC Attenuator 0x180 ATTEN_MODE RESERVED ATTEN_MODE 0x181 ATTEN_VALUE_PIN0 ATTEN_VALUE_PIN0 0x182 ATTEN_VALUE_PIN1 ATTEN_VALUE_PIN1 0x183 ATTEN_INIT ATTEN_INIT 0x184 ATTEN_CTL ATT_PIN RESERVED ATTEN_READ ADC Reset Control 0x188 ADCRE_THRH RESERVED ADCRE_THRH 0x189 ADCRE_PULSE_LEN RESERVED ADCRE_PULSE_LEN 0x18A ATTEN_STEP_RE RESERVED ATTEN_STEP_RE Peak Detector and AGC Flag Control 0x18F ADC_UNSTABLE RESERVED CLEAR_UNSTA UNSTABLE BLE FLAG FLAG 0x193 PKTHRH0_LSB PKTHRH0_LSB 0x194 PKTHRH0_MSB RESERVED PKTHRH0_MSB 0x195 PKTHRH1_LSB PKTHRH1_LSB Rev. D | Page 66 of 90 Reset 0x18 0x00 0x03 0xBB 0x00 0x00 0x56 0x04 RW RW R R R R R R 0x10 0x0E 0x2C 0x01 0x3C 0x00 0x14 0x05 0x05 0x00 0x40 RW RW RW RW RW RW RW RW RW RW RW 0x00 0x00 0x00 0x00 0x00 RW RW RW W RW 0x01 0x05 0x15 0x00 0x00 0x00 0x00 RW RW RW RW RW RW RW 0x02 RW 0x00 RW 0x00 RW 0xFF RW 0x00 0x0C 0x0C 0x00 0x0C RW RW RW RW R 0x05 RW 0x01 RW 0x06 RW 0x00 RW 0x00 RW 0x00 RW 0x00 RW Data Sheet Reg 0x196 0x197 0x198 0x199 Name Bit 7 PKTHRH1_MSB LOWTHRH_LSB LOWTHRH_MSB DWELL_TIME_MANTISSA 0x19A DWELL_TIME_EXP 0x19B FLAG0_SEL 0x19C FLAG1_SEL 0x19E EN_FLAG GPIO Configuration 0x1B0 FORCE_GPIO 0x1B1 FORCE_GPIO_OUT 0x1B2 FORCE_GPIO_VAL 0x1B3 READ_GPO 0x1B4 READ_GPI JESD204B Interface 0x1C0 DID 0x1C1 BID 0x1C3 L 0x1C4 F 0x1C5 K 0x1C6 M 0x1C9 S 0x1CB RES1 0x1CC RES2 0x1D0 LID0 0x1D1 LID1 0x1D8 FCHK0 0x1D9 FCHK1 0x1E0 EN_LFIFO 0x1E1 SWAP 0x1E2 LANE_PD 0x1E3 MIS1 0x1E4 SYNC_PIN 0x1E5 TEST_GEN 0x1E6 KF_ILAS 0x1E7 SYNCINB_CTRL 0x1E8 MIX_CTRL 0x1E9 K_OFFSET 0x1EA SYSREF 0x1EB SER1 0x1EC SER2 0x1EF PRE-EMPHASIS ADC Clock Synthesizer 0x2A0 CLKSYN_ENABLE 0x2A1 0x2A2 0x2A5 CLKSYN_INT_N_LSB CLKSYN_INT_N_MSB VCO_CAL_RESET 0x2AA 0x2AB 0x2AC 0x2AD 0x2B7 0x2BB CLKSYN_VCO_BIAS CLKSYN_VCO_CAL CLKSYN_I_CP EN_CP_CAL CLKSYN_VCO_VAR CLKSYN_R_DIV 0x2BC CLKSYN_STATUS 0x2DC JESDSYN_STATUS ADC Adaptive Shuffler Control 0x340 SHUFFLE_CTRL 0x342 0x343 AD6676 SHUFFLE_THREG_0 SHUFFLE_THREG_1 Bit 6 Bit 5 RESERVED Bit 4 Bit 3 Bit 2 Bit 1 PKTHRH1_MSB Bit 0 LOWTHRH_LSB RESERVED LOWTHRH_MSB DWELL_TIME_MANTISSA RESERVED RESERVED RESERVED RESERVED EN_OR RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED DWELL_TIME_EXP FLAG0_SEL FLAG1_SEL EN_FLAG1 EN_FLAG0 FORCE_GPIO FORCE_GPIO_OUT FORCE_GPIO_VAL READ_GPO READ_GPI DID RESERVED RESERVED SCR BID L F RESERVED K M RESERVED S RES1 RES2 RESERVED RESERVED LID0 LID1 FCHK0 FCHK1 RESERVED SWAP_CONV RESERVED RESERVED RESERVED RESERVED ILAS_DELAY TEST_SAMPLE_EN LSYNC_EN SYNC_PIN_INV TEST_GEN_SEL RESERVED MIX_USE_2ND MIX_NEXT RESERVED MIX_ALL SER_DRV_PS EN_EXTCK SER_ITRIM SER_EMP_IDAC1 EN_ADC_CK EN_SYNTH EN_VCO_ PTAT EN_VCO _ALC INT_N_LSB[7:0] RESERVED RESERVED RESERVED EN_LFIFO SWAP_LANE LANE_PD FACI_DISABLE RESERVED INV_10B RESERVED TEST_GEN_MODE KF_ILAS PD_SYSREF_RX LVDS_SYNCINB RESERVED RESERVED USE_2ND_ NEXT_SYSREF ALL_SYSREF SYSREF K_OFFSET SYSREF_WIN_POS RESERVED SER_RTRIM SER_EMP_PS0 SER_EMP_IDAC0 RESERVED SYSREF_WIN_NEG SER_EMP_PS1 RESERVED RESERVED ILAS_MODE RESERVED BIAS_TEMPCO INIT_ALC_VALUE EN_VCO EN_OVERRIDE BIAS RESERVED ID_SYNTH I_CP RESERVED VCO_VAR R_DIV RESERVED SYSREF_ CTRL PLL_LCK PLL_LCK RESERVED RESERVED RESERVED CLKIN_IMPED RESERVED RESERVED RESERVED SHUFFLE_TH2 SHUFFLE_TH4 SHUFFLE_TH1 SHUFFLE_TH3 Rev. D | Page 67 of 90 RESERVED VCO CAL BUSY VCO CAL BUSY RW RW RW RW RW 0x00 0x00 0x00 0x00 RW RW RW RW 0x00 0x00 0x00 0x00 0x00 RW RW RW R R 0x00 0x00 0x00 0x03 0x1F 0x01 0x00 0x00 0x00 0x00 0x01 0x44 0x45 0x00 0x00 0x00 0x14 0x00 0x00 0x00 0x00 0x00 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW 0x00 0x00 0x1C 0x9B 0x00 RW RW RW RW RW 0x00 RW 0x80 RW 0x00 RW 0x00 RW INT_N_MSB[10:8] RESERVED VCO_CAL_ RESET RESERVED ALC_DIS RESERVED EN_CP_CAL EN_OVERRIDE_ CAL Reset 0x00 0x00 0x00 0x00 0x37 0xC0 0x19 0x00 0xD0 0xB9 RW RW RW RW RW CP CAL DONE CP CAL DONE 0x80 R 0x80 R EN_ADAPTIVE_ SHUFFLE 0x03 RW 0xF5 0xFF RW RW AD6676 Data Sheet REGISTER DETAILS SPI Configuration Register Address: 0x000, Reset: 0x18, Name: SPI_CONFIG Table 33. Bit Descriptions for SPI_CONFIG Bits 7 Bit Name SW_RESET 6 4 LSB_FIRST SDIO_DIR Description Self-clearing bit causing software reset when set. Software reset returns all SPI registers to default state. When set, causes input and output data to be orientated as LSB first, per SPI standard. When set, causes SPI interface to be 4-wire with output data appearing on the SDO pin. Reset 0 Access RW 0 1 This register uses the first four bits to configure SPI interface/format thus Bit 0, Bit 1, and Bit 3 are mirror images of Bit 7, Bit 6, and Bit 4. Device Configuration Register Address: 0x002, Reset: 0x00, Name: DEVICE_CONFIG Table 34. Bit Descriptions for DEVICE_CONFIG Bits [7:2] Bit Name RESERVED [1:0] PD_MODE Description Reset 0x0 Access RW Power-down/standby control 0x0 RW 00 = normal operation 01 = not used. 10 = standby mode 11 = sleep (power-down) mode Chip Type Register Address: 0x003, Reset: 0x03, Name: CHIP_TYPE Table 35. Bit Descriptions for CHIP_TYPE Bits [7:0] Bit Name CHIP_TYPE Description Chip Type: High Speed ADC. Reset 0x03 Access R Reset 0xBB Access R Reset 0x00 Access R Chip ID 0 Register Address: 0x004, Reset: 0xBB, Name: CHIP_ID0 Table 36. Bit Descriptions for CHIP_ID0 Bits [7:0] Bit Name CHIP_ID0 Description Chip ID Low Byte. Chip ID 1 Register Address: 0x005, Reset: 0x00, Name: CHIP_ID1 Table 37. Bit Descriptions for CHIP_ID1 Bits [7:0] Bit Name CHIP_ID1 Description Chip ID High Byte. Rev. D | Page 68 of 90 Data Sheet AD6676 Chip Grade/Revision Register Address: 0x006, Reset: 0x00, Name: GRADE_REVISION Table 38. Bit Descriptions for GRADE_REVISION Bits [7:4] Bit Name REVISION [3:0] GRADE Description Reset 0x0 Access R 0x0 R Reset 0x56 Access R Reset 0x04 Access R Vendor ID 0 Register Address: 0x00C, Reset: 0x56, Name: VENDOR_ID0 Table 39. Bit Descriptions for VENDOR_ID0 Bits [7:0] Bit Name VENDOR_ID0 Description Vendor ID 1 Register Address: 0x00D, Reset: 0x04, Name: VENDOR_ID1 Table 40. Bit Descriptions for VENDOR_ID1 Bits [7:0] Bit Name VENDOR_ID1 Description ADC CLK Frequency LSB Register Address: 0x100, Reset: 0x10, Name: FADC_0 Table 41. Bit Descriptions for FADC_0 Bits [7:0] Bit Name FADC_0 Description Lower 8-bits of 16-bit value that defines the ADC CLK frequency to 1 MHz resolution. For example, the FADC_1 and FADC_0 settings for a 3200 MHz CLK frequency are 0x0C and 0x80, respectively. Reset 0x10 Access RW ADC CLK Frequency MSB Register 1 Address: 0x101, Reset: 0x0E, Name: FADC_1 Table 42. Bit Descriptions for FADC_1 Bits [7:0] Bit Name FADC_1 Description Upper 8-bits of 16-bit value that defines the ADC CLK frequency to 1 MHz. For example, the FADC_1 and FADC_0 settings for a 3200 MHz CLK frequency are 0x0C and 0x80, respectively. Reset 0x0E Access RW IF Frequency LSB Register 0 Address: 0x102, Reset: 0x2C, Name: FIF_0 Table 43. Bit Descriptions for FIF_0 Bits [7:0] Bit Name FIF_0 Description Lower 8-bits of 16-bit value that defines the target IF frequency to 1 MHz resolution. For example, the FIF_1 and FIF_0 settings for a 300 MHz IF frequency are 0x01 and 0x2C, respectively. Reset 0x2C Access RW IF Frequency MSB Register 1 Address: 0x103, Reset: 0x01, Name: FIF_1 Table 44. Bit Descriptions for F0_1 Bits [7:0] Bit Name FIF_1 Description Upper 8-bits of 16-bit value that defines the target IF frequency to 1 MHz resolution. For example, the FIF_1 and FIF_0 settings for a 300 MHz IF frequency would be 0x01 and 0x2C, respectively. Rev. D | Page 69 of 90 Reset 0x01 Access RW AD6676 Data Sheet BW LSB Register 0 Address: 0x104, Reset: 0x3C, Name: BW_0 Table 45. Bit Descriptions for BW_0 Bits [7:0] Bit Name BW_0 Description Lower 8-bits of 16-bit value that defines the target BW frequency to 1 MHz resolution. For example, the BW_1 and BW_0 settings for a 60 MHz BW would be 0x00 and 0x3C, respectively. Reset 0x3C Access RW BW MSB Register 1 Address: 0x105, Reset: 0x00, Name: BW_1 Table 46. Bit Descriptions for BW_1 Bits [7:0] Bit Name BW_1 Description Upper 8-bits of 16-bit value that defines the target BW frequency to 1 MHz resolution. This register should be kept to 0x00 default setting because maximum BW should be no greater than 160 MHz. Reset 0x00 Access RW External Inductance Value Register Address: 0x106, Reset: 0x14, Name: LEXT Table 47. Bit Descriptions for LEXT Bits [7:0] Bit Name LEXT Description External inductance in nH. Enter the external inductance value for the LC tank resonator. The default value of 0x14 corresponds to 20 nH Reset 0x14 Access RW Bandwidth Margin (Low End) Register Address: 0x107, Reset: 0x05, Name: MRGN_L Table 48. Bit Descriptions for MRGN_L Bits [7:0] Bit Name MRGN_L Description An 8-bit register defining the offset frequency (to 1 MHz resolution) to which the frequency of the lower resonator is offset from its theoretical ideal value. The default setting is 5 MHz. Increasing the value lowers the actual resonator frequency. Reset 0x05 Access RW Bandwidth Margin (Upper End) Register Address: 0x108, Reset: 0x05, Name: MRGN_U Table 49. Bit Descriptions for MRGN_U Bits [7:0] Bit Name MRGN_U Description An 8-bit register defining the offset frequency (to 1 MHz resolution) to which the frequency of the upper resonator is offset from its theoretical ideal value. The default setting is 5 MHz. Increasing the value increases the actual resonator frequency. Reset 0x05 Access RW Reset 0x00 Access RW Bandwidth Margin (IF) Register Address: 0x109, Reset: 0x00, Name: MRGN_IF Table 50. Bit Descriptions for MRGN_IF Bits [7:0] Bit Name MRGN_IF Description An 8-bit register defining the offset frequency (to 1 MHz resolution) to which the frequency of the LC resonator is offset from its theoretical ideal value. The default setting is 0 MHz. Increasing the value increases the actual resonator frequency. Rev. D | Page 70 of 90 Data Sheet AD6676 IDAC1FS Gain Scaling Register Address: 0x10A, Reset: 0x40, Name: IDAC1_FS Table 51. Bit Descriptions for IDAC1_FS Bits [7:0] Bit Name IDAC1_FS Description This parameter allows adjustment of the full-scale input power level of the ADC by adjusting the full-scale current of IDAC1. The nominal setting of 0x40 sets IDAC1FS value to 4 mA and corresponds to the largest full-scale level of approximately -3 dBm (with the IF attenuator set to 0 dB.) A setting of 0x20 or 0x10 results IDAC1FS value to 2 mA or 1 mA, thus resulting in a 6 dB or 12 dB reduction in PIN_0dBFS. Settings resulting in more than 12 dB reduction are not recommended. Reset 0x40 Access RW Calibration Control Register Address: 0x115, Reset: 0x00, Name: CAL_CTRL Table 52. Bit Descriptions for CAL_CTRL Bits [7:2] Bit Name RESERVED Description Reset 0x00 [1:0] CAL_PROFILE ADC profile to be calibrated. Select one of the four ADC profiles in which to store the results of the calibration. For example, to support multiple IF settings, the four profiles cover all registers in the range of 0x141 to 0x145. Access RW RW Calibration Command Register Address: 0x116, Reset: 0x00, Name: CAL_CMD Table 53. Bit Descriptions for CAL_CMD Bits [7:6] 5 4 3 2 1 0 Bit Name RESERVED INIT_NTF_OP INIT_JESD RESON1_CAL FLASH_CAL INIT_ADC TUNE_ADC Description Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access RWAC RWAC RWAC RWAC RWAC RWAC RWAC Setting a 1 in one or more of the bits in this register initiates the internal calibration. This register is cleared automatically at the end of calibration or by setting the FORCE_END_CAL bit. Calibration Done Register Address: 0x117, Reset: 0x00, Name: CAL_DONE Table 54. Bit Descriptions for ADC_PROFILE Bits [7:1] Bit Name RESERVED Description Reset 0x00 Access RW [0] CAL_DONE This bit indicates that the microcontroller has completed its calibration. It is automatically cleared by a new CAL_CMD. 0x0 RW Rev. D | Page 71 of 90 AD6676 Data Sheet ADC Profile Selection Register Address: 0x118, Reset: 0x00, Name: ADC_PROFILE Table 55. Bit Descriptions for ADC_PROFILE Bits [7:2] Bit Name RESERVED Description Reset 0x00 Access W [1:0] ADC_PROFILE ADC profile. Select which one of the four ADC profiles to use in operation. The user may switch between multiple profiles if calibration has taken place for each. Note that the four profiles also cover SPI Register 0x141 to SPI Register 0x145 if the digital mixer settings are varied between profiles. 0x0 W Reset 0x00 0x0 Access RW RW Force End of Calibration Register Address: 0x11A, Reset: 0x00, Name: FORCE_END_CAL Table 56. Bit Descriptions for FORCE_END_CAL Bits [7:1] 0 Bit Name RESERVED FORCE_END_CAL Description Setting this bit high and then low (two write operations) allows the user to terminate the calibration and hand control back to the SPI. This SPI operation should only be performed if the AD6676 fails to clear Register 0x116 after 400 ms. This is a user accessible SPI register only when the controller is performing a calibration. Decimation Mode Register Address: 0x140, Reset: 0x01, Name: DEC_MODE Table 57. Bit Descriptions for DEC_MODE Bits [7:3] [2:0] Bit Name RESERVED DEC_MODE Settings 001 010 011 100 Description Decimation Mode. Decimate by 32. Decimate by 24. Decimate by 16. Decimate by 12. Reset 0x00 0x01 Access RW RW Coarse NCO Tuning Register Address: 0x141, Reset: 0x05, Name: MIX1_TUNING Table 58. Bit Descriptions for MIX1_TUNING Bits [7:6] [5:0] Bit Name RESERVED MIX1_TUNING Description Mix1 Tuning. Coarse downconversion frequency, in units of FADC/64. For example, setting bits to 000011 downconverts by FADC x (3/64). Reset 0x0 0x5 Access RW RW This register has four copies, one for each of the ADC profiles. The default for Profile 0 is 0x05; the default for the other profiles is 0x00. At the default ADC clock rate of 3.2 GHz; the default Profile 0 downconversion frequency is (5/64) x 3.6 GHz = 250 MHz Rev. D | Page 72 of 90 Data Sheet AD6676 Fine NCO Tuning Register Address: 0x142, Reset: 0x15, Name: MIX2_TUNING Table 59. Bit Descriptions for MIX2_TUNING Bits [7:0] Bit Name MIX2_TUNING Description Mix2 Tuning. Fine down/upconversion frequency. For decimation Mode 1 and Mode 3, this twos complement number represents steps of FADC/4096. For decimation Mode 2 and Mode 4, it represents steps of FADC/3072. A positive number is a downconverion; a negative number is an upconversion. Reset 0x15 Access RW This register has four copies, one for each of the ADC profiles. The default for Profile 0 is 0x21; the default for the other profiles is 0x00. At the default ADC clock rate of 3.2 GHz, the default Profile 0 downconversion frequency is (33/4096) x 3.2 GHz = 25.78125 MHz Coarse NCO Initial Phase Register Address: 0x143, Reset: 0x00, Name: MIX1_INIT Table 60. Bit Descriptions for MIX1_INIT Bits [7:6] Bit Name RESERVED Description Reset 0x0 Access RW [5:0] MIX1_INIT NCO1 Initial Phase. Initial phase of the coarse resolution NCO after synchronization with SYSREF, in units of 1/64 of a cycle. 0x00 RW This register has four copies, one for each of the ADC profiles. The default for Profile 0 is 0x00. Fine NCO Initial Phase LSB Register Address: 0x144, Reset: 0x00, Name: MIX2_INIT_LSB Table 61. Bit Descriptions for MIX2_INIT_LSB Bits [7:0] Bit Name MIX2_INIT_LSB Description NCO2 Initial Phase. Initial phase of the fine resolution NCO after synchronization with SYSREF, in units of 1/1024 of a cycle. The two MSBs of the 10-bit value are in Register 0x145. Reset 0x00 Access RW This register has four copies, one for each of the ADC profiles. The default for Profile 0 is 0x00. Fine NCO Initial Phase MSB Register Address: 0x145, Reset: 0x00, Name: MIX2_INIT_MSB Table 62. Bit Descriptions for MIX2_INIT_MSB Bits [7:2] Bit Name RESERVED Description Reset 0x00 Access RW [1:0] MIX2_INIT_MSB NCO2 Initial Phase. Initial phase of the fine resolution NCO after synchronization with SYSREF, in units of 1/1024 of a cycle. The LSBs of the 10-bit value are in Register 0x144. 0x0 RW Reset 0x00 Access RW This register has four copies, one for each of the ADC profiles. The default for Profile 0 is 0x00. Datapath Controls Register Address: 0x146, Reset: 0x00, Name: DP_CTRL Table 63. Bit Descriptions for DP_CTRL Bits [7:1] 0 Bit Name RESERVED NOT_2S_COMPL Description Output Data Format: twos complement = 0; straight binary = 1 Rev. D | Page 73 of 90 AD6676 Data Sheet Standby Register Address: 0x150, Reset: 0x02, Name: STANDBY When bits in this register are set, the corresponding blocks enter a power-down state when the chip enters standby mode. Table 64. Bit Descriptions for STANDBY Bits 7 Bit Name RESERVED Description Reset 0x0 Access RW 6 STBY_VSS2GEN 1: power down negative supply (VSS2) generator during standby. 0x0 RW 5 STBY_CLK_PLL 1: power down main clock PLL during standby. 0x0 RW 4 3 STBY_JESD_PLL STBY_JESD_PHY 1: power down JESD interface PLL during standby. 1: power down JESD interface transmitters during standby. 0x0 0x0 RW RW 2 STBY_FRAMER 1: power down JESD interface framer logic during standby. 0x0 RW 1 STBY_DATAPATH 1: power down digital datapath during standby. 0x1 RW 0 STBY_DIGCLK 1: disable all digital clocks during standby. 0x0 RW Reset 0x00 0x0 0x0 0x0 Access RW RW RW RW Digital Power-Down Register Address: 0x151, Reset: 0x00, Name: PD_DIG Table 65. Bit Descriptions for PD_DIG Bits [7:3] 2 1 0 Bit Name RESERVED PD_FRAMER PD_DATAPATH PD_DIGCLK Description 1: power down JESD interface framer logic. 1: power down digital datapath. 1: power down all digital clocks. Standby Pin Control Register Address: 0x152, Reset: 0x00, Name: PD_PIN_CTRL Table 66. Bit Descriptions for PD_PIN_CTRL Bits [7:5] 4 Bit Name RESERVED PD_PIN_EN Settings Description 0 1 [3:2] [1:0] RESERVED PD_PIN_SEL 00 01 10 11 Enable Standby Mode Control from a GPIO Pin. Use only register 2 to select standby mode. Use Register 2 or the selected pin to select standby mode. Standby mode is the logical OR of the register setting and the pin state. Select GPIO pin for standby control. Use AGC1 for standby control. Use AGC2 for standby control. Use AGC3 for standby control. Use AGC4 for standby control. Reset 0x0 0x0 Access RW RW 0x0 0x0 RW RW Attenuator Mode Register Address: 0x180, Reset: 0x00, Name: ATTEN_MODE Table 67. Bit Descriptions for ATTEN_MODE Bits [7:1] 0 Bit Name RESERVED ATTEN_MODE Description Attenuator Mode. 0 = Use AGC2 pin to select between values in Register 0x0181 and Register 0x0182. 1 = Use AGC1 and AGC2 pins to decrement/increment attenuation value. Rev. D | Page 74 of 90 Reset 0x00 0x0 Access RW RW Data Sheet AD6676 Attenuator AGC2 Pin Low Value Register Address: 0x181, Reset: 0x0C, Name: ATTEN_VALUE_PIN0 Table 68. Bit Descriptions for ATTEN_VALUE_PIN1 Bits [7:0] Bit Name ATTEN_VALUE_PIN0 Description Attenuation value to be used in ATTEN_MODE = 0 when the AGC2 pin is low. Valid range is from 0 (minimum attenuation) to 27 (maximum attenuation). Value 28 to Value 31 disable the attenuator. Default is 12 dB attenuation. Reset 0x0C Access RW Reset 0x0C Access RW Reset 0x00 Access RW Reset 0x0 Access R 0x0 RW 0x0C R Reset 0x00 0x5 Access RW RW Attenuator AGC2 Pin High Value Register Address: 0x182, Reset: 0x0C, Name: ATTEN_VALUE_PIN1 Table 69. Bit Descriptions for ATTEN_VALUE_PIN1 Bits [7:0] Bit Name ATTEN_VALUE_PIN1 Description Attenuation value to be used in ATTEN_MODE = 0 when the AGC2 pin is high. Valid range is from 0 (minimum attenuation) to 27 (maximum attenuation). Value 28 to Value 31 disable the attenuator. Default is 12 dB attenuation. Attenuator Initialization Register Address: 0x183, Reset: 0x00, Name: ATTEN_INIT Table 70. Bit Descriptions for ATTEN_INIT Bits [7:0] Bit Name ATTEN_INIT Description Initialize the attenuator value when using ATTEN_MODE = 1. Attenuator Status Register Address: 0x184, Reset: 0x0C, Name: ATTEN_CTL Table 71. Bit Descriptions for ATTEN_CTL Bits 7 Bit Name ATT_PIN [6:5] RESERVED [4:0] ATTEN_READ Description Read back the state of the AGC2 pin. Read back the actual attenuation value in ATTEN_MODE. ADC Reset Threshold Register Address: 0x188, Reset: 0x05, Name: ADCRE_THRH Table 72. Bit Descriptions for ADCRE_THRH Bits [7:3] [2:0] Bit Name RESERVED ADCRE_THRH Description ADC Reset Threshold. The ADC reset triggers if more than threshold out of eight consecutive ADC samples have the full-scale value of 8. ADC Reset Pulse Length Register Address: 0x189, Reset: 0x01, Name: ADCRE_PULSE_LEN Table 73. Bit Descriptions for ADCRE_PULSE_LEN Bits [7:5] Bit Name RESERVED Description Reset 0x0 Access RW [4:0] ADCRE_PULSE_LEN The duration of the reset pulse to the ADC, (x + 1) x 8/FADC. 0x01 RW Rev. D | Page 75 of 90 AD6676 Data Sheet ADC Reset Attenuation Step Register Address: 0x18A, Reset: 0x06, Name: ATTEN_STEP_RE Table 74. Bit Descriptions for ATTEN_STEP_RE Bits [7:5] Bit Name RESERVED Description Reset 0x0 Access RW [4:0] ATTEN_STEP_RE The size of the increase in attenuation after a reset event, in dB. The attenuation is clipped to a maximum value of 27 dB. 0x06 RW ADC Unstable Flag Control Register Address: 0x18F, Reset: 0x00, Name: ADC_UNSTABLE Table 75. Bit Descriptions for ADC_UNSTABLE Bits [7:2] 1 Bit Name RESERVED CLEAR_UNSTABLE_FLAG 0 UNSTABLE_FLAG Description Clear unstable flag. Writing a 1 to this bit clears the UNSTABLE_FLAG. This bit is self clearing. Unstable flag. This is a sticky flag that indicates if an ADC reset condition has been detected. It is cleared only by the CLEAR_UNSTABLE_FLAG bit and the hardware/software resets. Reset 0x00 0x0 Access RW RW 0x0 R Peak Threshold 0 LSB Register Address: 0x193, Reset: 0x00, Name: PKTHRH0_LSB Table 76. Bit Descriptions for PKTHRH0_LSB Bits [7:0] Bit Name PKTHRH0_LSB Settings Description Peak Threshold 0 LSB. Reset 0x00 Access RW Reset 0x0 0x0 Access RW RW Reset 0x00 Access RW Reset 0x0 0x0 Access RW RW Peak Threshold 0 MSB Register Address: 0x194, Reset: 0x00, Name: PKTHRH0_MSB Table 77. Bit Descriptions for PKTHRH0_MSB Bits [7:4] [3:0] Bit Name RESERVED PKTHRH0_MSB Settings Description Peak Threshold 0 MSB. Peak Threshold 1 LSB Register Address: 0x195, Reset: 0x00, Name: PKTHRH1_LSB Table 78. Bit Descriptions for PKTHRH1_LSB Bits [7:0] Bit Name PKTHRH1_LSB Settings Description Peak Threshold 1 LSB. Peak Threshold 1 MSB Register Address: 0x196, Reset: 0x00, Name: PKTHRH1_MSB Table 79. Bit Descriptions for PKTHRH1_MSB Bits [7:4] [3:0] Bit Name RESERVED PKTHRH1_MSB Settings Description Peak Threshold 1 MSB. Rev. D | Page 76 of 90 Data Sheet AD6676 DEC Low Threshold LSB Register Address: 0x197, Reset: 0x00, Name: LOWTHRH_LSB Table 80. Bit Descriptions for LOWTHRH_LSB Bits [7:0] Bit Name LOWTHRH_LSB Settings Description Low Threshold LSB. Reset 0x00 Access RW Reset 0x0 0x0 Access RW RW Reset 0x00 Access RW Reset 0x0 0x0 Access RW RW Low Threshold MSB Register Address: 0x198, Reset: 0x00, Name: LOWTHRH_MSB Table 81. Bit Descriptions for LOWTHRH_MSB Bits [7:4] [3:0] Bit Name RESERVED LOWTHRH_MSB Settings Description Low Threshold MSB. Dwell Time Mantissa Register Address: 0x199, Reset: 0x00, Name: DWELL_TIME_MANTISSA Table 82. Bit Descriptions for DWELL_TIME_MANTISSA Bits [7:0] Bit Name DWELL_TIME_MANTISSA Settings Description Dwell Time mantissa. Dwell Time Exponent Register Address: 0x19A, Reset: 0x00, Name: DWELL_TIME_EXP Table 83. Bit Descriptions for DWELL_TIME_EXP Bits [7:4] [3:0] Bit Name RESERVED DWELL_TIME_EXP Settings Description Dwell Time Exponent. AGC Flag 0 Select Register Address: 0x19B, Reset: 0x00, Name: FLAG0_SEL Table 84. Bit Descriptions for FLAG0_SEL Bits [7:3] [2:0] Bit Name RESERVED FLAG0_SEL Description Select 1 of 4 flags to output on the AGC3 pin. 000 = ADC reset pulse. 100 = DEC peak above DEC Threshold 0. 101 = DEC peak above DEC Threshold 1. 110 = DEC peak below DEC low threshold for dwell time. Reset 0x00 0x0 Access RW RW Reset 0x00 0x0 Access RW RW AGC Flag 1 Select Register Address: 0x19C, Reset: 0x00, Name: FLAG1_SEL Table 85. Bit Descriptions for FLAG1_SEL Bits [7:3] [2:0] Bit Name RESERVED FLAG1_SEL Description Select one of four flags to output on the AGC4 pin. 000 = ADC reset pulse. 100 = DEC peak above DEC Threshold 0. 101 = DEC peak above DEC Threshold 1. 110 = DEC peak below DEC low threshold for dwell time. Rev. D | Page 77 of 90 AD6676 Data Sheet AGC Flag Enable Register Address: 0x19E, Reset: 0x00, Name: EN_FLAG Table 86. Bit Descriptions for EN_FLAG Bits [7:5] Bit Name RESERVED Description Reset 0x0 Access RW 4 EN_OR Combine ADC reset with peak detect. When asserted, this bit causes the ADC reset pulse (Flag Select Option 0) to be logically OR-ed with one of the peak-detect flags options specified in Register 0x19B or Register 0x19C. 0x0 RW 0x0 RW 0x0 RW 0x0 RW [3:2] RESERVED 1 EN_FLAG1 0 EN_FLAG0 Enable Flag 1. 0 = Force AGC4 pin low. 1 = Enable selected flag on AGC4 pin (see FLAG1_SEL). Enable Flag 0. 0 = Force AGC3 pin low. 1 = Enable selected flag on AGC3 pin (see FLAG0_SEL). Force GPIO Register Address: 0x1B0, Reset: 0x00, Name: FORCE_GPIO Table 87. Bit Descriptions for FORCE_GPIO Bits [7:4] [3:0] Bit Name RESERVED FORCE_GPIO Description Force GPIO use. Force one or more of the pins, AGC1 to AGC4, to be used as a GPIO rather than any other specified use. Bit 0: force AGC1 to be used as a GPIO. Bit 1: force AGC2 to be used as a GPIO. Bit 2: force AGC3 to be used as a GPIO. Bit 3: force AGC4 to be used as a GPIO. Reset 0x0 0x00 Access RW RW Force GPIO as Output Register Address: 0x1B1, Reset: 0x00, Name: FORCE_GPIO_OUT Table 88. Bit Descriptions for FORCE_GPIO_OUT Bits [7:4] [3:0] Bit Name RESERVED FORCE_GPIO_OUT Description Force GPIO use as an output. When used in conjunction with FORCE_GPIO, configure one or more of the pins, AGC1 to AGC4, to be used as a general purpose output or input. Bit 0 = 1: use AGC1 as an output. Bit 0 = 0: use AGC1 as an input. Bit 1 = 1: use AGC2 as an output. Bit 1 = 0: use AGC2 as an input. Bit 2 = 1: use AGC3 as an output. Bit 2 = 0: use AGC3 as an input. Bit 3 = 1: use AGC4 as an output. Bit 3 = 0: use AGC4 as an input. Rev. D | Page 78 of 90 Reset 0x0 0x00 Access RW RW Data Sheet AD6676 Force GPIO Value Register Address: 0x1B2, Reset: 0x00, Name: FORCE_GPIO_VAL Table 89. Bit Descriptions for FORCE_GPIO_VAL Bits [7:4] [3:0] Bit Name RESERVED FORCE_GPIO_VAL Description Force GPIO Value. When used in conjunction with FORCE_GPIO and FORCE_GPIO_OUT, configure the state of one or more of the pins, AGC1 to AGC4, when being used as a general purpose output. Bit [0]: state of AGC1 when being used as an output. Bit [1]: state of AGC2 when being used as an output. Bit [2]: state of AGC3 when being used as an output. Bit [3]: state of AGC4 when being used as an output. Reset 0x0 0x00 Access RW RW GPIO Output Status Register Address: 0x1B3, Reset: 0x00, Name: READ_GPO Table 90. Bit Descriptions for READ_GPO Bits [7:4] [3:0] Bit Name RESERVED READ_GPO Description Read back the status of the GPIO output bits. These are the same as the external pins, AGC1 through AGC4, if the GPIO are enabled and configured as outputs. Reset 0x0 0x00 Access RW R GPIO Input Status Register Address: 0x1B4, Reset: 0x00, Name: READ_GPI Table 91. Bit Descriptions for READ_GPI Bits [7:4] Bit Name RESERVED Description Reset 0x0 Access RW [3:0] READ_GPI Read back the status of the GPIO input bits. These are the same as the external pins, AGC1 through AGC4, if the GPIO are enabled and configured as inputs 0x00 R JESD204 DID Register Address: 0x1C0, Reset: 0x00, Name: DID Table 92. Bit Descriptions for DID Bits [7:0] Bit Name DID Description Device ID Reset 0x00 Access RW Reset 0x0 0x0 Access R RW JESD204 BID Register Address: 0x1C1, Reset: 0x00, Name: BID Table 93. Bit Descriptions for BID Bits [7:4] [3:0] Bit Name RESERVED BID Description Bank ID JESD204 L/SCR Register Address: 0x1C3, Reset: 0x00, Name: L Table 94. Bit Descriptions for L Bits 7 Bit Name SCR Settings 0 Description SCR Parameter. Scrambling disabled. Rev. D | Page 79 of 90 Reset 0x0 Access RW AD6676 Bits Bit Name Data Sheet Settings 1 [6:5] [4:0] RESERVED L 00000 00001 Description Scrambling enabled. Reset Access 0x0 0x00 RW RW Description Octest per Frame per Lane. F=2 F=4 Reset 0x03 Access RW Description Reset 0x0 0x1F Access RW RW Description M. Two converters (I/Q data). Reset 0x01 Access RW Description Reset 0x0 0x00 Access RW RW L Parameter. One lane. Two lanes. JESD204 F Register Address: 0x1C4, Reset: 0x03, Name: F Table 95. Bit Descriptions for F Bits [7:0] Bit Name F Settings 00000001 00000011 JESD204 K Register Address: 0x1C5, Reset: 0x1F, Name: K Table 96. Bit Descriptions for K Bits [7:5] [4:0] Bit Name RESERVED K Settings Frames per multiframe. Number of frames per multiframe is the register value plus one. JESD204 M Register Address: 0x1C6, Reset: 0x01, Name: M Table 97. Bit Descriptions for M Bits [7:0] Bit Name M Settings 00000001 JESD204 S Register Address: 0x1C9, Reset: 0x00, Name: S Table 98. Bit Descriptions for S Bits [7:5] [4:0] Bit Name RESERVED S Settings 00000 S. One sample per frame (the only valid option). JESD204 RES1 Register Address: 0x1CB, Reset: 0x00, Name: RES1 Table 99. Bit Descriptions for RES1 Bits [7:0] Bit Name RES1 Description Reset 0x00 Rev. D | Page 80 of 90 Access RW Data Sheet AD6676 JESD204 RES2 Register Address: 0x1CC, Reset: 0x00, Name: RES2 Table 100. Bit Descriptions for RES2 Bits [7:0] Bit Name RES2 Description Reset 0x00 Access RW JESD204 LID0 Register Address: 0x1D0, Reset: 0x00, Name: LID0 Table 101. Bit Descriptions for LID0 Bits [7:5] Bit Name RESERVED Description Reset 0x0 Access RW [4:0] LID0 Lane ID for Lane 0. 0x00 RW JESD204 LID1 Register Address: 0x1D1, Reset: 0x01, Name: LID1 Table 102. Bit Descriptions for LID1 Bits [7:5] Bit Name RESERVED Description Reset 0x0 Access RW [4:0] LID1 Lane ID for Lane 1. 0x01 RW Reset 0x44 Access RW Reset 0x45 Access RW JESD204 FCHK0 Register Address: 0x1D8, Reset: 0x44, Name: FCHK0 Table 103. Bit Descriptions for FCHK0 Bits [7:0] Bit Name FCHK0 Description Checksum for Lane 0. JESD204 FCHK1 Register Address: 0x1D9, Reset: 0x45, Name: FCHK1 Table 104. Bit Descriptions for FCHK1 Bits [7:0] Bit Name FCHK1 Description Checksum for Lane 1. Enable Lane FIFO Register Address: 0x1E0, Reset: 0x00, Name: EN_LFIFO Table 105. Bit Descriptions for EN_LFIFO Bits [7:1] Bit Name RESERVED Description Reset 0x00 Access RW 0 EN_LFIFO Lane FIFO Enable. Once the entire configuration of the framer has been completed, and the link is powered up, set this bit to start the lane FIFOs that manage the hand-off of data from the framer to the transmitter PHY. 0x0 RW Rev. D | Page 81 of 90 AD6676 Data Sheet Swap Register Address: 0x1E1, Reset: 0x00, Name: SWAP Table 106. Bit Descriptions for SWAP Bits [7:6] [5:4] [3:2] [1:0] Bit Name RESERVED SWAP_CONV Settings Description 00 01 10 11 Bit [4] swaps the source of Framer Converter 0 (default is I channel). Bit [5] swaps the source of Framer Converter 1 (default is Q channel). Framer Input 1 = Q channel; Framer Input 0 = I channel Framer Input 1 = Q channel; Framer Input 0 = Q channel Framer Input 1 = I channel; Framer Input 0 = I channel Framer Input 1 = I channel; Framer Input 0 = Q channel 00 01 10 11 Bit [0] swaps the source of physical output lane 0. Bit [1] swaps the source of physical output lane 1. Output Lane 1 = Famer lane 1; Output Lane 0 = Framer Lane 0 Output Lane 1 = Framer lane 1; Output Lane 0 = Framer Lane 1 Output Lane 1 = Framer lane 0; Output Lane 0 = Framer Lane 0 Output Lane 1 = Framer lane 0; Output Lane 0 = Framer Lane 1 RESERVED SWAP_LANE Reset 0x0 0x0 Access RW RW 0x0 0x0 RW RW Link/Lane Power-Down Register Address: 0x1E2, Reset: 0x00, Name: LANE_PD Table 107. Bit Descriptions for LANE_PD Bits [7:4] Bit Name ILAS_DELAY [3:2] [1:0] RESERVED LANE_PD Description ILAS Start Delay. Usually the ILAS starts on the first LMFC rising edge after SYNCINB goes high. This value delays the ILAS by the given number of LMFC periods (multiframe periods). Lane Power-down. Bit 0 powers down transmitter PHY for Lane 0. Bit 1 powers down transmitter PHY for Lane 1. Reset 0x0 Access RW 0x0 0x0 RW RW Interface Control 0 Register Address: 0x1E3, Reset: 0x14, Name: MIS1 Table 108. Bit Descriptions for MIS1 Bits [7:6] Bit Name RESERVED Description Reset 0x0 Access RW 5 TEST_SAMPLE_EN 0x0 RW 4 LSYNC_EN 0 = Disable transport layer test samples. 1 = Enable transport layer test samples. 0 = Disable lane synchronization. 1 = Enable lane synchronization (default). 0x1 RW [3:2] ILAS_MODE 0x1 RW 1 FACI_DISABLE 01 = Enable ILAS (default). 11 = ILAS always on; data link layer test mode. Control of Frame Alignment Characters. 0 = Enable frame alignment character insertion. 1 = Disable frame alignment character insertion. 0x0 RW 0 RESERVED 0x0 RW Rev. D | Page 82 of 90 Data Sheet AD6676 Interface Control 1 Register Address: 0x1E4, Reset: 0x00, Name: SYNC_PIN Table 109. Bit Descriptions for SYNC_PIN Bits [7:6] Bit Name RESERVED Description Reset 0x0 Access RW 5 SYNC_PIN_INV 0 = do not invert SYNCINB pin; SYNCINB is active low. 1 = invert SYNCINB pin; SYNCINB is active high. 0x0 RW [4:2] RESERVED 0x0 RW 1 INV_10B 0x0 RW 0 RESERVED 0x0 RW 0 = do not invert octets. 1 = invert all bits in 10-bit octets from framer. Setting the bit to 1 has the same effect as swapping the differential output data pins. Interface Test Register Address: 0x1E5, Reset: 0x00, Name: TEST_GEN Table 110. Bit Descriptions for TEST_GEN Bits [7:6] [5:4] Bit Name RESERVED TEST_GEN_SEL Settings Description 00 01 10 [3:0] TEST_GEN_MODE 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 Test Point. Insert test data at framer input (16 bits). Insert test data at PHY input (10 bits). Insert test data at scrambler input (8 bits). Test Mode. Normal mode; test disabled. Alternating checkerboard. 1/0 word toggle. Long PN sequence. Short PN sequence. Repeating user pattern mode. Single user pattern mode. Ramp. Note that in single lane mode the Q sample is 1 LSB less than the I sample. In other words, Q[n] = I[n] - 1 LSB, where n is nth IQ sample. Modified RPAT sequence. Not used. JSPAT sequence. JTSPAT sequence. Reset 0x0 0x0 Access RW RW 0x0 RW ILAS Count Register Address: 0x1E6, Reset: 0x00, Name: KF_ILAS Table 111. Bit Descriptions for KF_ILAS Bits [7:0] Bit Name KF_ILAS Description Initial Lane Assignment Sequence Count. The ILAS is transmitted (KF_ILAS + 1) times. Rev. D | Page 83 of 90 Reset 0x00 Access RW AD6676 Data Sheet SYNCINB and SYSREF Control Register Address: 0x1E7, Reset: 0x00, Name: SYNCINB_CTRL Table 112. Bit Descriptions for SYNCB_CTRL Bits [7:4] Bit Name RESERVED Description Reset 0x0 Access RW 3 2 PD_SYSREF_RX LVDS_SYNCINB Power down SYSREF receiver. Use LVDS for SYNCINB. (0 = CMOS, 1 = LVDS differential with 100 termination). 0x0 0x0 RW RW [1:0] RESERVED 0x0 RW Clock Synchronization Register Address: 0x1E8, Reset: 0x00, Name: MIX_CTRL Table 113. Bit Descriptions for MIX_CTRL Bits 7 Bit Name RESERVED Description Reset 0x0 Access RW 6 MIX_USE_2ND 0x0 RW 5 MIX_NEXT 0x0 RWAC 4 MIX_ALL When used in conjunction with Bit 5, setting this bit causes the second SYSREF that is used to align the clocks to also be used to reset the mixer NCO phases. This bit does not self-clear. This bit is only active when Bit 2 is also active. Once set, only the next SYSREF pulse that is used to align the clock dividers is also used to reset the mixers NCO phases. This bit self clears after use. This bit is only active when Bit 1 is also active. Any SYSREF that is used to align the clocks is also used to reset the mixers' NCO phases. This bit is only active when Bit 0 is also active. 0x0 RW 3 RESERVED 0x0 RW 2 USE_2ND_SYSREF 0x0 RW 1 NEXT_SYSREF 0x0 RWAC 0 ALL_SYSREF 0x0 RW When used in conjunction with Bit 1, setting this bit causes the second SYSREF to be used for alignment rather than the first. This bit does not self clear. Once set, only the next SYSREF pulse is used to align the clock dividers. This bit selfclears after the next SYSREF. All SYSREF pulses are used to align the clock dividers. LMFC Offset Register Address: 0x1E9, Reset: 0x00, Name: K_OFFSET Table 114. Bit Descriptions for K_OFFSET Bits [7:5] Bit Name RESERVED Description Reset 0x0 Access RW [4:0] K_OFFSET This register provides an offset that moves the position of the internal LMFC with respect to SYSREF. A larger value places the LMFC later in time. In units of frame periods. 0x00 RW Reset 0x0 Access RW 0x0 RW SYSREF Window Register Address: 0x1EA, Reset: 0x00, Name: SYSREF Table 115. Bit Descriptions for SYSREF Bits [7:4] Bit Name SYSREF_WIN_NEG [3:0] SYSREF_WIN_POS Description SYSREF_WIN_NEG. Do not align clocks if SYSREF is no earlier than register value before its expected position. In units of 2/FADC. SYSREF_WIN_POS. Do not align clocks if SYSREF is no later than register value after its expected position. In units of 2/FADC. Rev. D | Page 84 of 90 Data Sheet AD6676 PHY Control 0 Register Address: 0x1EB, Reset: 0x1C, Name: SER1 Table 116. Bit Descriptions for SER1 Bits 7 Bit Name SER_DRV_PS Description Serializer Polarity Selection. Reset 0x0 Access RW 0x1C RW 0 = Polarity not inverted. 1 = Polarity inverted. [6:0] RESERVED PHY Control 1 Register Address: 0x1EC, Reset: 0x00, Name: SER2 Table 117. Bit Descriptions for SER1 Bits [7:4] Bit Name SER_ITRIM Description Driver bias current trim with recommended setting of 0x0B. Reset 0x9 Access RW [3:0] SER_RTRIM Resistor termination code with recommended setting of 0x0D. 0xB RW PHY Control 3 Register Address: 0x1EF, Reset: 0x00, Name: PRE-EMPHASIS Table 118. Bit Descriptions for PRE-EMPHASIS Bits 7 Bit Name SER_EMP_PS1 Description Toggle Polarity of Lane 1 Emphasis. Reset 0x0 Access RW [6:4] SER_EMP_IDAC1 Lane 1 IDAC Setting. 00: 0 mV emphasis differential p-p. 0x0 RW 01: 160 mV emphasis differential p-p. 10: 80 mV emphasis differential p-p. 11: 40 mV emphasis differential p-p. 3 SER_EMP_PS0 Toggle polarity of Lane 0 emphasis. 0x0 RW [2:0] SER_EMP_IDAC0 Lane 0 IDAC Setting. 0x0 RW Reset 0xFF Access RW 00: 0 mV emphasis differential p-p. 01: 160 mV emphasis differential p-p. 10: 80 mV emphasis differential p-p. 11: 40 mV emphasis differential p-p. ADC Standby 0 Register Address: 0x250, Reset: 0xFF, Name: STBY_DAC Table 119. Bit Descriptions for STBY_DAC Bits [7:0] Bit Name STBY_DAC Description Setting register to 0x95 results in faster standby ADC recovery time. Rev. D | Page 85 of 90 AD6676 Data Sheet CLKSYN Enable Register Address: 0x2A0, Reset: 0x00, Name: CLKSYN_ENABLE Table 120. Bit Descriptions for CLKSYN_ENALBE Bits 7 6 5 4 3 2 1 0 Bit Name EN_EXTCK EN_ADC_CK EN_SYNTH EN_VCO_PTAT EN_VCO_ALC EN_VCO EN_OVERIDE_CAL EN_OVERIDE Description EXTCK Enable. ADC CK Enable. Synthesizer Enable. VCO PTAT Enable. VCO ALC Enable. VCO Enable. Override Calibration Enable. Override Enable. Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access RW RW RW RW RW RW RW RW Reset 0x80 Access RW Reset 0x0 0x0 Access RW RW CLKSYN Integer N LSB Register Address: 0x2A1, Reset: 0x80, Name: CLKSYN_INT_N_LSB Table 121. Bit Descriptions for CLKSYN_INT_N_LSB Bits [7:0] Bit Name INT_N_LSB Description Lower LSBs of 11-bit Integer-N Value. CLKSYN Integer N MSB Register Address: 0x2A2, Reset: 0x00, Name: CLKSYN_INT_N_MSB Table 122. Bit Descriptions for CLKSYN_INT_N_MSB Bits [7:3] [2:0] Bit Name RESERVED INT_N_MSB Description Upper 3 MSBs of 11-bit Integer N Value. CLKSYN VCO Calibration RESET Register Address: 0x2A5, Reset: 0x00, Name: VCO_CAL_RESET Table 123. Bit Descriptions for VCO_CAL_RESET Bits [7:4] Bit Name RESERVED Description Reset 0x0 Access RW 3 VCO_CAL_RESET Reset VCO Calibration. 0 RW [2:0] RESERVED 0x0 RW CLKSYN KVCO VCO Register Address: 0x2A9, Reset: 0x00, Name: CLKSYN_KVCO Table 124. Bit Descriptions for CLKSYN_KVCO Bits [7:4] Bit Name VCO KVCO VAR [3:0] VCO_ALC_LVL Description Rev. D | Page 86 of 90 Reset 0x0 Access RW 0xA RW Data Sheet AD6676 CLKSYN VCO Bias Register Address: 0x2AA, Reset: 0x37, Name: CLKSYN_VCO_BIAS Table 125. Bit Descriptions for CLKSYN_VCO_BIAS Bits [7:6] [5:4] 3 [2:0] Bit Name RESERVED BIAS_TEMPCO RESERVED BIAS Description VCO Bias Tempco Setting. VCO Bias Setting. Reset 0 0x3 0 0x7 Access RW RW RW RW Reset 0xC Access RW CLKSYN VCO Calibration Register Address: 0x2AB, Reset: 0xC0, Name: CLKSYN_VCO_CAL Table 126. Bit Descriptions for CLKSYN_VCO_CAL Bits [7:4] Bit Name INIT_ALC_VALUE Description Initial Automatic Level Control Value. 3 ALC_DIS ALC calibration Test Bit. [2:1] RESERVED 0 ID_SYNTH Initiates VCO Calibration. 0 RW 0 RW 0 RW CLKSYN Charge Pump Register Address: 0x2AC, Reset: 0x19, Name: CLKSYN_I_CP Table 127. Bit Descriptions for CLKSYN_I_CP Bits [7:6] Bit Name RESERVED Description Reset 0x0 Access RW [5:0] I_CP Charge Pump Current = min(63, 1.33 x 1028/(fPFD x FCLK2) - 1). 0x19 RW Reset 0x0 Access RW 0x0 RW Reset 0xD0 Access RW CLKSYN Charge Pump Calibration Register Address: 0x2AD, Reset: 0x00, Name: EN_CP_CAL Table 128. Bit Descriptions for EN_CP_CAL Bits [7:6] Bit Name EN_CP_CAL [6:0] RESERVED Description CLKSYN VCO Varactor Register Address: 0x2B7, Reset: 0xD0, Name: CLKSYN_VCO_VAR Table 129. Bit Descriptions for CLKSYN_VCO_VAR Bits [7:4] [3:0] Bit Name VCO_VAR RESERVED Description VCO Varactor Setting. Rev. D | Page 87 of 90 AD6676 Data Sheet CLKSYN Reference Divider and SYSREF Control Register Address: 0x2BB, Reset: 0xB9, Name: CLKSYN_R_DIV Table 130. Bit Descriptions for CLKSYN_R_DIV Bits [7:6] [5:4] 3 Bit Name R_DIV RESERVED SYSREF_CTRL 2 CLKIN_IMPED [1:0] RESERVED Description 00 = div-by-1; 01 = div-by-2; 10 = div-by-4; 11 = multiply-by-2. SYSREF Input Sampling Clock. 0 = use clock synthesizer reference clock. 1 = use internal clock at FADC/2 (use for nonclock synthesizer case). CLKIN Impedance. 0 = configure CLK as 100 termination, configuration for clock synthesizer disabled. 1 = configure CLK+ as high-Z, configuration for clock synthesizer enabled. Reset 10 0x3 1 Access RW RW RW 0 RW 0x1 RW Reset 0x8 0x0 0x0 0x0 0x0 Access R R R R R Reset 0x8 Access R CLKSYN Status Register Address: 0x2BC, Reset: 0x80, Name: CLKSYN_STATUS Table 131. Bit Descriptions for CLKSYN_STATUS Bits [7:4] 3 2 1 0 Bit Name RESERVED PLL_LCK RESERVED VCO CAL BUSY CP CAL DONE Description Clock Synthesizer Lock Bit (1 = lock). VCO Calibration Busy (0 = done). Charge Pump Calibration Done (1 = done). JESDSYN Status Register Address: 0x2DC, Reset: 0x80, Name: JESDSYN_STATUS Table 132. Bit Descriptions for JESDSYN_STATUS Bits [7:4] Bit Name RESERVED Description 3 PLL_LCK JESD204 PLL Synthesizer Lock Bit (1 = lock). 2 RESERVED 0x0 R 0x0 R 1 VCO CAL BUSY VCO Calibration Busy (0 = done). 0x0 R 0 CP CAL DONE Charge Pump Calibration Done (1 = done). 0x0 R Shuffler Control Register Address: 0x340, Reset: 0x03, Name: SHUFFLE_CTRL Table 133. Bit Descriptions for SHUFFLE_CTRL Bits [7:2] Bit Name RESERVED 1 RESERVED 0 EN_ADAPTIVE_SHUFFLE Description Enable Adaptive Flash Shuffling. Rev. D | Page 88 of 90 Reset 0x00 Access RW 1 RW 1 RW Data Sheet AD6676 Shuffler Threshold 1 and 2 Register Address: 0x342, Reset: 0xF5, Name: SHUFFLE_THREG_0 Table 134. Bit Descriptions for SHUFFLE_THREG_0 Bits [7:4] Bit Name SHUFFLE_TH2 [3:0] SHUFFLE_TH1 Description Threshold value for shuffling every two cycles. Shuffle-every-2 is triggered when the ADC data is greater than or equal to this threshold. Threshold value for shuffling every one cycle. Shuffle-every-1 is triggered when the ADC data is greater than or equal to this threshold Reset 0xF Access R 0x5 R Reset 0xF Access R 0xF R Shuffler Threshold 3 and 4 Register Address: 0x343, Reset: 0xFF, Name: SHUFFLE_THREG_1 Table 135. Bit Descriptions for SHUFFLE_THREG_1 Bits [7:4] Bit Name SHUFFLE_TH4 [3:0] SHUFFLE_TH3 Description Threshold value for shuffling every four cycles. Shuffle-every-4 is triggered when the ADC data is greater than or equal to this threshold. Threshold value for shuffling every three cycles. Shuffle-every-3 is triggered when the ADC data is greater than or equal to this threshold Rev. D | Page 89 of 90 AD6676 Data Sheet OUTLINE DIMENSIONS 4.33 4.29 4.25 0.27 8 7 6 5 4 3 2 1 A B BALL A1 IDENTIFIER C 5.08 5.04 5.00 D 4.50 REF E F G H J (BALL SIDE DOWN) SEATING PLANE SIDE VIEW BOTTOM VIEW 0.36 0.390 0.360 0.330 (BALL SIDE UP) 0.43 3.50 REF COPLANARITY 0.05 0.360 0.320 0.280 0.270 0.240 0.210 03-14-2013-A 0.660 0.600 0.540 K 0.50 BALL PITCH TOP VIEW Figure 151. 80-Ball Wafer Level Chip Scale Package [WLCSP] (CB-80-5) Dimensions shown in millimeters ORDERING GUIDE Model1 AD6676BCBZRL AD6676EBZ 1 Temperature Range -40C to +85C Package Description 80-Ball Wafer Level Chip Scale Package [WLCSP] Evaluation Board Z = RoHS Compliant Part. (c)2014-2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D12348-0-5/17(D) Rev. D | Page 90 of 90 Package Option CB-80-5