a
AD7884/AD7885
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Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.
REV. E
LC
2
MOS
16-Bit, High Speed Sampling ADCs
ⴞ3VINF
AD7884
TIMER CONTROL
DGND
CS
RD
BUSY
DB15
AGNDS AGNDF AVDD
GND
DB0
CONVST
VDD
9
9
9
16 16
VREF–
R3
3k⍀C1
SW1
SW2
9-BIT
ADC LATCH
+
ALU
O
U
T
P
U
T
D
R
I
V
E
R
S
16-BIT
ACCURATE
DAC
R2
3k⍀
ⴞ3VINS
R1
5k⍀
R5
4k⍀
A2
SW3
R6
2k⍀
R7
2k⍀
R8
2k⍀
ⴞ5VINF
ⴞ5VINS
AVSS VSS
VREF+FV
REF+SV
INV VREF–
R4
4k⍀
A1
AD7885
TIMER CONTROL
DGND
CS
RD
BUSY
DB7
AGNDS AGNDF AVDD
GND
DB0
CONVST
VDD
9
9
9
16 8
VREF–
R3
3k⍀C1
SW1
SW2
9-BIT
ADC LATCH
+
ALU
O
U
T
P
U
T
D
R
I
V
E
R
S
16-BIT
ACCURATE
DAC
R2
3k⍀
ⴞ3VIN
R1
5k⍀
R5
4k⍀
A2
SW3
R6
2k⍀
R7
2k⍀
R8
2k⍀
ⴞ5VINF
ⴞ5VINS
AVSS VSS
VREF+FV
REF+SV
INV VREF–
R4
4k⍀
HBEN
A1
FEATURES
Monolithic Construction
Fast Conversion: 5.3 ␮s
High Throughput Rate: 166 kSPS
Low Power: 250 mW
APPLICATIONS
Automatic Test Equipment
Medical Instrumentation
Industrial Control
Data Acquisition Systems
Robotics
GENERAL DESCRIPTION
The AD7884/AD7885 is a 16-bit monolithic analog-to-digital
converter with internal sample-and-hold and a conversion time
of 5.3 µs. The maximum throughput rate is 166 kSPS. It uses a
two-pass flash architecture to achieve this speed. Two input
ranges are available: ±5 V and ±3 V. Conversion is initiated by
the CONVST signal. The result can be read into a microprocessor
using the CS and RD inputs on the device. The AD7884 has a
16-bit parallel reading structure while the AD7885 has a byte reading
structure. The conversion result is in twos complement code.
The AD7884/AD7885 has its own internal oscillator that controls
conversion. It runs from ±5 V supplies and needs a V
REF+
of 3 V.
The AD7884 is available in a 40-lead CERDIP package and a
44-lead PLCC package.
The AD7885 is available in a 28-lead CERDIP package and the
AD7885A is available in a 44-lead PLCC package.
FUNCTIONAL BLOCK DIAGRAMS
REV. E
–2–
AD7884/AD7885/AD7885A–SPECIFICATIONS
(VDD = +5 V ⴞ 5%, VSS = –5 V ⴞ 5%,
VREF+S = 3 V, AGND = DGND = GND = 0 V, fSAMPLE = 166 kHz. All specifications TMIN to TMAX, unless otherwise noted.)
JAB
Parameter Version
1, 2, 3
Version
1, 2, 3
Version
1, 2, 3
Unit Test Conditions/Comments
DC ACCURACY
Resolution 16 16 16 Bits
Minimum Resolution for Which
No Missing Codes Are Guaranteed 16 16 16 Bits
Integral Nonlinearity ±0.0075 % FSR max Typically 0.003% FSR
Positive Gain Error ±0.1 ±0.03 ±0.03 % FSR typ AD7885AQ/BQ: 0.1% typ
Positive Gain Error ±0.05 % FSR max AD7885BQ: 0.2% max
Gain TC
4
±2±2±2ppm FSR/°C typ
Bipolar Zero Error ±0.05 ±0.05 ±0.05 % FSR typ
±0.15 % FSR max
Bipolar Zero TC
4
±8±8±8ppm FSR/°C typ
Negative Gain Error ±0.1 ±0.03 ±0.03 % FSR typ AD7885AQ/BQ: 0.1% typ
Negative Gain Error ±0.05 % FSR max AD7885BQ: 0.2% max
Offset TC
4
±2±2±2ppm FSR/°C typ
Noise 120 120 120 µV rms typ 78 µV rms Typical in ±3 V Input Range
DYNAMIC PERFORMANCE
Signal-to-(Noise + Distortion) Ratio 82 84 84 dB min Input Signal: ±5 V, 1 kHz Sine Wave, Typically 86 dB
82 82 82 dB typ Input Signal: ±5 V, 12 kHz Sine Wave
Total Harmonic Distortion –84 –88 –88 dB max Input Signal: ±5 V, 1 kHz Sine Wave
–84 –84 –84 dB typ Input Signal: ±5 V, 12 kHz Sine Wave
Peak Harmonic or Spurious Noise –88 –88 –88 dB max Input Signal: ±5 V, 1 kHz Sine Wave
Intermodulation Distortion (IMD)
Second Order Terms –84 –84 –84 dB typ f
A
= 11.5 kHz, f
B
= 12 kHz, f
SAMPLE
= 166 kHz
Third Order Terms –84 –84 –84 dB typ f
A
= 11.5 kHz, f
B
= 12 kHz, f
SAMPLE
= 166 kHz
CONVERSION TIME
Conversion Time 5.3 5.3 5.3 µs max
Acquisition Time 2.5 2.5 2.5 µs max
Throughput Rate 166 166 166 kSPS max There is an overlap between conversion and acquisition.
ANALOG INPUT
Voltage Range ±5±5±5V
±3±3±3V
Input Current ±4±4±4mA max
REFERENCE INPUT
Reference Input Current ±5±5±5mA max V
REF+
S = 3 V
LOGIC INPUTS
Input High Voltage, V
INH
2.4 2.4 2.4 V min V
DD
= 5 V ± 5%
Input Low Voltage, V
INL
0.8 0.8 0.8 V max V
DD
= 5 V ± 5%
Input Current, I
IN
±10 ±10 ±10 µA max Input Level = 0 V to V
DD
Input Capacitance, C
IN4
10 10 10 pF max
LOGIC OUTPUTS
Output High Voltage, V
OH
4.0 4.0 4.0 V min I
SOURCE
= 200 µA
Output Low Voltage, V
OL
0.4 0.4 0.4 V max I
SINK
= 1.6 mA
DB15–DB0
Floating-State Leakage Current 10 10 10 µA max
Floating-State Output Capacitance
4
15 15 15 pF max
POWER REQUIREMENTS
V
DD
555 V nom ±5% for Specified Performance
V
SS
–5 –5 –5 V nom ±5% for Specified Performance
I
DD
35 35 35 mA max Typically 25 mA
I
SS
30 30 30 mA max Typically 25 mA; AD7885/AD7885A
33 33 33 mA max Typically 25 mA; AD7884
Power Supply Rejection Ratio
∆Gain/∆V
DD
86 86 86 dB typ
∆Gain/∆V
SS
86 86 86 dB typ
Power Dissipation 325 325 325 mW max Typically 250
mW
NOTES
1
Temperature ranges are as follows: J, A, B Versions: –40°C to +85°C.
2
V
IN
= ±5 V.
3
The AD7885AAP has the same specifications as the AD7884AP. The AD7885ABP has the same specifications as the AD7884BP.
4
Sample tested to ensure compliance.
Specifications subject to change without notice.
REV. D –3–
AD7884/AD7885
TIMING CHARACTERISTICS
1
Limit at 25ⴗCLimit at T
MIN
, T
MAX
Parameter (All Versions) (A, B, and J Versions) Unit Conditions/Comments
t
1
50 50 ns min CONVST Pulsewidth
t
2
100 100 ns max CONVST to BUSY Low Delay
t
3
00 ns min CS to RD Setup Time
t
4
60 60 ns min RD Pulsewidth
t
5
00 ns min CS to RD Hold Time
t
62
57 57 ns max Data Access Time after RD
t
73
55 ns min Bus Relinquish Time after RD
50 50 ns max
t
8
40 40 ns min New Data Valid before Rising Edge of BUSY
t
9
10 80 ns min HBEN to RD Setup Time
t
10
25 25 ns min HBEN to RD Hold Time
t
11
60 60 ns min HBEN Low Pulse Duration
t
12
60 60 ns min HBEN High Pulse Duration
t
13
55 70 ns max Propagation Delay from HBEN Falling to Data Valid
t
14
55 70 ns max Propagation Delay from HBEN Rising to Data Valid
NOTES
1
Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
t
6
is measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
3
t
7
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time, t
7
, quoted in the Timing Characteristics
is the true bus relinquish time of the part and as such is independent of external bus loading capacitances.
Specifications subject to change without notice.
(VDD = +5 V ⴞ 5%, VSS = –5 V ⴞ 5%, AGND = DGND = GND = 0 V. See Figures 2, 3, 4, and 5.)
TO OUTPUT PIN 2.1V
C
L
100pF
200␮A I
OH
1.6mA I
OL
Figure 1. Load Circuit for Access Time and Bus
Relinquish Time
REV. E
AD7884/AD7885
–4–
t6
t2
CS
RD
DATA
BUSY
CONVST
HI-Z
t3
t1
t5
t7
tCONVERT
t4
HI-Z
DATA
VALID
Figure 2. AD7884 Timing Diagram, Using
CS
and
RD
DATA OLD DATA VALID NEW DATA VALID
BUSY
CONVST
t1
t2
t8
tCONVERT
Figure 3. AD7884 Timing Diagram, with
CS
and
RD
Permanently Low
HBEN
CS
RD
DATA
BUSY
CONVST
HI-Z HI-Z
DB0–DB7 DB8–DB15
HI-Z
t
2
DATA
VALID
t1
DATA
VALID
t9 t10
t3 t5
t6
t7
t4
tCONVERT
Figure 4. AD7885 Timing Diagram, Using
CS
and
RD
DATA
BUSY
HBEN
CONVST
t1
t11 t12
t2
t8t13 t14
tCONVERT
OLD DATA VALID
(DB8–DB1 5)
NEW DATA VALID
(DB8–DB1 5)
NEW DATA VALID
(DB0–DB7)
NEW DATA VALID
(DB8–DB1 5)
NEW DATA VALID
(DB0–DB7)
Figure 5. AD7885 Timing Diagram, with
CS
and
RD
Permanently Low
REV. E
AD7884/AD7885
–5–
ORDERING GUIDE
Linearity
Temperature Error SNR Package
Model Range (% FSR) (dB) Option
AD7884AP –40°C to +85°C84P-44A
AD7884BP –40°C to +85°C±0.0075 84 P-44A
AD7885AAP –40°C to +85°C84P-44A
AD7885ABP –40°C to +85°C±0.0075 84 P-44A
AD7884AQ –40°C to +85°C84Q-40
AD7884BQ –40°C to +85°C±0.0075 84 Q-40
AD7885JQ –40°C to +85°C82Q-28
AD7885AQ –40°C to +85°C84Q-28
AD7885BQ –40°C to +85°C±0.0075 84 Q-28
NOTE
P = Plastic Leaded Chip Carrier (PLCC); Q = CERDIP.
ABSOLUTE MAXIMUM RATINGS
1
V
DD
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AV
DD
to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
V
SS
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –7 V
AV
SS
to AGND . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –7 V
AGND Pins to DGND . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
AV
DD
to V
DD2
. . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AV
SS
to V
SS2
. . . . . . . . . . . . . . . . . . . . . . . . . .+0.3 V to –7 V
GND to DGND . . . . . . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
V
IN
S, V
IN
F to AGND . . . . . . . . . . V
SS
– 0.3 V to V
DD
+ 0.3 V
V
REF+
to AGND . . . . . . . . . . . . . . V
SS
– 0.3 V to V
DD
+ 0.3 V
V
REF–
to AGND . . . . . . . . . . . . . . . V
SS
– 0.3 V to V
DD
+ 0.3 V
V
INV
to AGND . . . . . . . . . . . . . . . V
SS
– 0.3 V to V
DD
+ 0.3 V
Digital Inputs to DGND . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
Digital Outputs to DGND . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
Operating Temperature Range
Commercial Plastic (A, B Versions) . . . . . –40°C to +85°C
Industrial CERDIP (J, A, B Versions) . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C
28-Lead CERDIP
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . 50.9°C/W
θ
JC
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 8.3°C/W
40-Lead CERDIP
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . 44.5°C/W
44-Lead PLCC
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . 47.7°C/W
θ
JC
Thermal Impedance . . . . . . . . . . . . . . . . . . . . 17.5°C/W
Power Dissipation (Any Package) to 75°C . . . . . . . . 1000 mW
Degradation above 75°C by . . . . . . . . . . . . . . . . . . 10 mW/°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
If the AD7884/AD7885 is being powered from separate analog and digital
supplies, AV
SS
should always come up before V
SS
. See Figure 12 for a recom-
mended protection circuit using Schottky diodes.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7884/AD7885 features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. E
AD7884/AD7885
–6–
PIN CONFIGURATIONS
CERDIP PLCC
TOP VIEW
(Not to Scale)
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
AD7884
RD
CS
C
ONVST
VDD
VSS
GND
AVSS
VINV
3VINF
5VINS
5VINF
AVDD
AGNDF
AGNDS
DB0
DB1
DB2
DB3
DGND
VREF+S
VREF+F
VDD
DB5
DB6
DB7
BUSY
VSS
VSS
GND
3VINS
VREF–
DB15
DB12
DB13
DB14
DB4
DB8
DB9
DB10
DB11
TOP VIEW
(Not to Scale)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
AD7885
RD
CS
C
ONVST
V
DD
V
SS
GND
AV
SS
V
REF–
3V
IN
5V
IN
S
5V
IN
F
AV
DD
AGNDF
AGNDS
HBEN
BUSY
DB0
DB1
DB2
DB3
DGND
V
INV
V
REF+
S
V
REF+
F
DB7
DB4
DB5
DB6
6 5 4 3 2 1 44 43 42 41 40
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
39
38
37
36
35
34
33
32
31
30
29
7
8
9
10
11
12
13
14
15
16
17
18
NC = NO CONNECT
DB12
DB11
DB10
DB9
DB8
NC
DGND
VDD
DB7
DB6
DB5
5VINF
AGNDS
AGNDF
AVDD
AVSS
NC
GND
GND
VSS
VSS
VDD
5VINS
3VINF
3VINS
VREF–
VINV
NC
VREF+S
CONVST
CS
RD
VSS
NC
DB0
DB1
DB2
DB3
DB4
BUSY
VREF+F
DB15
DB14
DB13
AD7884
19 20 21 22 23 24 25 26 27 28
6 5 4 3 2 1 44 43 42 41 40
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
39
38
37
36
35
34
33
32
31
30
29
7
8
9
10
11
12
13
14
15
16
17
18
NC = NO CONNECT
DB7
DB6
NC
DB5
DB4
NC
DGND
VDD
DB3
DB2
DB1
5VINF
AGNDS
AGNDF
AVDD
AVSS
NC
GND
GND
VSS
VSS
VDD
5VINS
3VINF
3VINS
VREF–
VINV
NC
VREF+S
CONVST
CS
RD
HBEN
NC
NC
NC
NC
NC
DB0
BUSY
VREF+F
NC
NC
NC
AD7885A
19 20 21 22 23 24 25 26 27 28
REV. E
AD7884/AD7885
–7–
PIN FUNCTION DESCRIPTIONS
AD7884 AD7885 AD7885A Description
V
INV
V
INV
V
INV
This pin is connected to the inverting terminal of an op amp, as in Figure 6, and allows
the inversion of the supplied 3 V reference.
V
REF–
V
REF–
V
REF–
This is the negative reference input and can be obtained by using an external amplifier to
invert the positive reference input. In this case, the amplifier output is connected to V
REF–
.
See Figure 6.
±3V
IN
S±3V
IN
SThis is the analog input sense pin for the ±3 V analog input range on the AD7884 and
AD7885A.
±3V
IN
F±3V
IN
FThis is the analog input force pin for the ±3 V analog input range on the AD7884 and
AD7885A. When using this input range, the ±5V
IN
F and ±5V
IN
S pins should be tied to
AGND.
±3V
IN
This is the analog input pin for the ±3 V analog input range on the AD7885. When using
this input range, the ±5V
IN
F and ±5V
IN
S pins should be tied to AGND.
±5V
IN
S±5V
IN
S±5V
IN
SThis is the analog input sense pin for the ±5 V analog input range on the AD7884, AD7885,
and AD7885A.
±5V
IN
F±5V
IN
F±5V
IN
FThis is the analog input force pin for the ±5 V analog input range on the AD7884, AD7885,
and AD7885A. When using this input range, the ±3V
IN
F and ±3V
IN
S pins should be tied
to AGND.
AGNDS AGNDS AGNDS This is the ground return sense pin for the 9-bit ADC and the on-chip residue amplifier.
AGNDF AGNDF AGNDF This is the ground return force pin for the 9-bit ADC and the on-chip residue amplifier.
AV
DD
AV
DD
AV
DD
Positive analog power rail for the sample-and-hold amplifier and the residue amplifier.
AV
SS
AV
SS
AV
SS
Negative analog power rail for the sample-and-hold amplifier and the residue amplifier.
GND GND GND This is the ground return for the sample-and-hold section.
V
SS
V
SS
V
SS
Negative Supply for the 9-Bit ADC
V
DD
V
DD
V
DD
Positive Supply for the 9-Bit ADC and All Device Logic
CONVST CONVST CONVST This asynchronous control input starts conversion.
CS CS CS Chip Select Control Input
RD RD RD Read Control Input. This is used in conjunction with CS to read the conversion result
from the device output latch.
HBEN HBEN High Byte Enable. Active high control input for the AD7885. It selects either the high or
the low byte of the conversion for reading.
BUSY BUSY BUSY Busy Output. The BUSY output goes low when the conversion begins and stays low until
it is completed, at which time it goes high.
DB0–DB15 16-Bit Parallel Data-Word Output on the AD7884
DB0–DB7 DB0–DB7 8-Bit Parallel Data Byte Output on the AD7885
DGND DGND DGND Ground Return for All Device Logic
V
REF+
FV
REF+
FV
REF+
FReference Force Input
V
REF+
SV
REF+
SV
REF+
SReference Sense Input. The device operates from a 3 V reference.
REV. E
AD7884/AD7885
–8–
TERMINOLOGY
Integral Nonlinearity
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function.
Differential Nonlinearity
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Bipolar Zero Error
This is the deviation of the midscale transition (all 0s to all 1s)
from the ideal (AGND).
Positive Gain Error
This is the deviation of the last code transition (01 . . . 110 to
01 . . . 111) from the ideal (+V
REF+
S – 1 LSB) after bipolar zero
error has been adjusted out.
Negative Gain Error
This is the deviation of the first code transition (10 . . . 000 to
10 . . . 001) from the ideal (–V
REF+
S + 1 LSB) after bipolar zero
error has been adjusted out.
Signal-to-(Noise + Distortion) Ratio
This is the measured ratio of signal-to-(noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the rms sum of all nonfundamental
signals up to half the sampling frequency (f
S
/2), excluding dc.
The ratio is dependent upon the number of quantization levels
in the digitization process; the more levels, the smaller the quan-
tization noise. The theoretical signal-to-(noise + distortion) ratio
for an ideal N-bit converter with a sine wave input is given by
Signal to Noise Distortion N dB−− +
()
=+
()
602 176..
Thus for an ideal 16-bit converter, this is 98 dB.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7884/AD7885, it is
defined as
THD dB VVVVV
V
() log=++++
20
2
2
3
2
4
2
5
2
6
2
1
where V
1
is the rms amplitude of the fundamental and V
2
, V
3
,
V
4
, V
5
, and V
6
are the rms amplitudes of the second through the
sixth harmonics.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the rms
value of the next largest component in the ADC output spectrum
(up to f
S
/2 and excluding dc) to the rms value of the fundamental.
Normally, the value of this specification is determined by the larg-
est harmonic in the spectrum, but for parts where the harmonics
are buried in the noise floor, it will be a noise peak.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, and so on. Intermodulation terms are those for
which neither m nor n are equal to zero. For example, the second
order terms include (fa + fb) and (fa – fb), while the third order
terms include (2fa + fb), (2fa – fb), (fa + 2fb), and (fa – 2fb).
The AD7884/AD7885 is tested using the CCIFF standard where
two input frequencies near the top end of the input bandwidth are
used. In this case, the second and third order terms are of different
significance. The second order terms are usually distanced in
frequency from the original sine waves while the third order terms
are usually at a frequency close to the input frequencies. As a
result, the second and third order terms are specified separately.
The calculation of the intermodulation distortion is as per the THD
specification, where it is the ratio of the rms sum of the individual
distortion products to the rms amplitude of the fundamental
expressed in dB.
Power Supply Rejection Ratio
This is the ratio of the change in positive gain error to the change
in V
DD
or V
SS
, in dB. It is a dc measurement.
OPERATIONAL DIAGRAM
An operational diagram for the AD7884/AD7885 is shown in
Figure 6. It is set up for an analog input range of ±5 V. If a ±3 V
input range is required, A1 should drive ±3V
IN
S and ±3V
IN
F
with ±5V
IN
S, ±5V
IN
F being tied to system AGND.
3V
IN
F
5V
IN
F
–5V
+5V
AD711, AD845,
OR AD817
AD817
AGNDS
AGNDF
AD7884/
AD7885
AD845, AD817,
OR EQUIVALENT
NOTE: POWER SUPPLY DECOUPLING NOT SHOWN
GND DGND
V
DD
= +5V
CONTROL
INPUTS
V
INV
V
REF+
S
V
REF+
F
V
REF–
3V
IN
S
5V
IN
S
AV
SS
V
DD
AV
DD
V
SS
V
IN
AD780
2
6
84
10␮F
A1
A2
A3
A4
DATA
OUTPUTS
AD845, AD817,
OR EQUIVALENT
Figure 6. AD7884/AD7885 Operational Diagram
The chosen input buffer amplifier (A1) should have low noise and
distortion and fast settling time for high bandwidth applications.
The AD711, AD845, and AD817 are suitable op amps.
A2 is the force, sense amplifier for AGND. The AGNDS pin
should be at zero potential. Therefore, the amplifier must have a
low input offset voltage and good noise performance. It must
also have the ability to deal with fast current transients on the
AGNDS pin. The AD817 has the required performance and is
the recommended amplifier.
If AGNDS and AGNDF are simply tied together to star
ground instead of buffering, the SNR and THD are not signifi-
cantly degraded. However, dc specifications like INL, bipolar
zero, and gain error will be degraded.
REV. E
AD7884/AD7885
–9–
The required 3 V reference is derived from the AD780 and
buffered by the high speed amplifier A3 (AD845, AD817, or
equivalent). A4 is a unity gain inverter that provides the –3 V
negative reference. The gain setting resistors are on-chip and are
factory trimmed to ensure precise tracking of V
REF+
. Figure 6
shows A3 and A4 as AD845s or AD817s. These have the ability to
respond to the rapidly changing reference input impedance.
CIRCUIT DESCRIPTION
Analog Input Section
The analog input section of the AD7884/AD7885 is shown in
Figure 7. It contains both the input signal conditioning and
sample-and-hold amplifier. Note that the analog input is truly
benign. When SW1
A
goes open circuit to put the SHA into the
hold mode, SW1
B
is closed. This means that the input resistors,
R1 and R2, are always connected to either virtual ground or
true ground.
R5
4k⍀
C1
SW1
A
A1
3V
IN
F
TO RESIDUE
AMPLIFIER A2
TO 9-BIT
ADC
V
REF–
SW1
B
R3
3k⍀
R6
2k⍀
R4
4k⍀
R2
5k⍀
R1
3k⍀
3V
IN
S
5V
IN
F
5V
IN
S
A1
Figure 7. AD7884/AD7885 Analog Input Section
When the ±3V
IN
S and ±3V
IN
F inputs are tied to 0 V, the
input section has a gain of –0.6 and transforms an input signal of
±5 V to the required ±3 V. When the ±5V
IN
S and ±5V
IN
F inputs
are grounded, the input section has a gain of –1 and so the analog
input range is now ±3 V. Resistors R4 and R5, at the amplifier
output, further condition the ±3 V signal to be 0 V to –3 V. This
is the required input for the 9-bit A/D converter section.
With SW1
A
closed, the output of A1 follows the input (the
sample-and-hold is in the track mode). On the rising edge of
the CONVST pulse, SW1
A
goes open circuit and capacitor C1
holds the voltage on the output of A1. The sample-and-hold is
now in the hold mode. The aperture delay time for the sample-
and-hold is nominally 50 ns.
A/D Converter Section
The AD7884/AD7885 uses a two-pass flash technique in order
to achieve the required speed and resolution. When the CONVST
control input goes from low to high, the sample-and-hold ampli-
fier goes into the hold mode and a 0 V to –3 V signal is presented
to the input of the 9-bit ADC. The first phase of conversion
generates the 9 MSBs of the 16-bit result and transfers these to
the latch and ALU combination. They are also fed back to the
9 MSBs of the 16-bit DAC. The 7 LSBs of the DAC are
permanently loaded with 0s. The DAC output is subtracted from
the analog input with the result being amplified and offset in the
Residue Amplifier section.
The signal at the output of A2 is proportional to the error
between the first phase result and the actual analog input
signal and is digitized in the second conversion phase. This
second phase begins when the 16-bit DAC and the residue
error amplifier have both settled. First, SW2 is turned off and
SW3 is turned on. Then, the SHA section of the residue
amplifier goes into hold mode. Next SW2 is turned off and
SW3 is turned on. The 9-bit result is transferred to the output
latch and ALU. An error correction algorithm now compensates
for the offset inserted in the residue amplifier section and
errors introduced in the first pass conversion and combines both
results to give the 16-bit answer.
9
9
VREF–
R4
4k⍀
R5
4k⍀
SW2
SW3
R6
2k⍀
A2
9-BIT
ADC LATCH
+
ALU 16
0 TO –3V
ⴞ3V SIGNAL
FROM INPUT
SHA
VREF+F
R7
2k⍀R8
2k⍀
+3V –3V
RESIDUE AMP
+ SHA
9
16-BIT
ACCURATE
DAC
VREF+S VINV V
REF–
Figure 8. A/D Converter Section
Timing and Control Section
Figure 9 shows the timing and control sequence for the AD7884/
AD7885. When the part receives a CONVST pulse, the con-
version begins. The input sample-and-hold goes into the hold
mode 50 ns after the rising edge of CONVST and BUSY goes
low. This is the first phase of conversion and takes 3.35 µs to
complete. The second phase of conversion begins when SW2 is
turned off and SW3 is turned on. The residue amplifier and
SHA section (A2 in Figure 8) goes into hold mode at this point
and allows the input sample-and-hold to go back into sample
mode. Thus, while the second phase of conversion is ongoing,
the input sample-and-hold is also acquiring the input signal for
the next conversion. This overlap between conversion and
acquisition allows throughput rates of 166 kSPS to be achieved.
CONVST
BUSY
HOLD
SAMPLE
INPUT
SHA
FIRST PHASE
3.5␮s
TACQ
2.5␮s
SECOND
PHASE
FIRST PHASE OF CONVERSION
FIRST 9-BIT CONVERSION
DAC SETTLING TIME
RESIDUE AMPLIFIER
SETTLING TIME
SECOND PHASE OF CONVERSION
SECOND 9-BIT CONVERSION
ERROR CORRECTION
OUTPUT LATCH UPDATE
1.8␮s
Figure 9. Timing and Control Sequence
REV. E
AD7884/AD7885
–10–
USING THE AD7884/AD7885 ANALOG INPUT RANGES
The AD7884/AD7885 can be set up to have either a ±3 V analog
input range or a ±5 V analog input range. Figures 10 and 11 show
the necessary corrections for each of these. The output code is
twos complement and the ideal code table for both input ranges
is shown in Table I.
Reference Considerations
The AD7884/AD7885 operates from a ±3 V reference. This can
be derived simply using the AD780 as shown in Figure 6.
5V
IN
S
5V
IN
F
3V
IN
S
3V
IN
F
V
INV
A1
Figure 10.
±
5 V Input Range Connection
3V
IN
S
3V
IN
F
5V
IN
S
5V
IN
F
V
INV
A1
Figure 11.
±
3 V Input Range Connections
The critical performance specification for a reference in a 16-bit
application is noise. The reference peak-to-peak noise should be
insignificant in comparison to the ADC noise. The AD7884/AD7885
has a typical rms noise of 120 µV. For example, a reasonable
target would be to keep the total rms noise less than 125 µV.
To do this the reference noise needs to be less than 35 µV rms.
In the 100 kHz band, the AD780 noise is less than 30 µV rms,
making it a very suitable reference.
The buffer amplifier used to drive the device V
REF+
should have
low enough noise performance so as not to affect the overall
system noise requirement. The AD845 and AD817 achieve this.
Decoupling and Grounding
The AD7884 and AD7885A have one AV
DD
pin and two V
DD
pins. They also have one AV
SS
pin and three V
SS
pins. The
AD7885 has one AV
DD
pin, one V
DD
pin, one AV
SS
pin, and
one V
SS
pin. Figure 6 shows how a common +5 V supply should
be used for the positive supply pins and a common –5 V supply
for the negative supply pins.
For decoupling purposes, the critical pins on both devices are
the AV
DD
and AV
SS
pins. Each of these should be decoupled to
system AGND with 10 µF tantalum and 0.1 µF ceramic capaci-
tors right at the pins. With the V
DD
and V
SS
pins, it is sufficient
to decouple each of these with ceramic 1 µF capacitors.
AGNDS, AGNDF are the ground return points for the on-chip
9-bit ADC. They should be driven by a buffer amplifier as shown
in Figure 6. If they are tied directly together and then to ground,
there will be a marginal degradation in linearity performance.
The GND pin is the analog ground return for the on-chip lin-
ear circuitry. It should be connected to system analog ground.
The DGND pin is the ground return for the on-chip digital
circuitry. It should be connected to the ground terminal of the
V
DD
and V
SS
supplies. If a common analog supply is used for
AV
DD
and V
DD
, then DGND should be connected to the com-
mon ground point.
Power Supply Sequencing
AV
DD
and V
DD
are connected to a common substrate and there is
typically 17 Ω resistance between them. If they are powered by
separate 5 V supplies, then these should come up simultaneously.
Otherwise, the one that comes up first will have to drive 5 V
into a 17 Ω load for a short period of time. However, the standard
short-circuit protection on regulators like the 7800 series will
ensure that there is no possibility of damage to the driving device.
AV
SS
should always come up either before or at the same
time as V
SS
. If this cannot be guaranteed, Schottky diodes
should be used to ensure that V
SS
never exceeds AV
SS
by
more than 0.3 V. Arranging the power supplies as in Figure 6
and using the recommended decoupling ensures that there
are no power supply sequencing issues as well as giving the
specified noise performance.
AVDD VDD AVSS VSS
+5V +5V –5V –5V
AD7884/AD7885
HP5082-2810
OR
EQUIVALENT
Figure 12. Schottky Diodes Used to Protect Against
Incorrect Power Supply Sequencing
Analog Input
ⴞ3 V ⴞ5 V Digital Output
In Terms of FSR
2
Range
3
Range
4
Code Transition
l
+FSR/2 – 1 LSB 2.999908 4.999847 011 . . . 111 to 111 . . . 110
+FSR/2 – 2 LSBs 2.999817 4.999695 011 . . . 110 to 011 . . . 101
+FSR/2 – 3 LSBs 2.999726 4.999543 011 . . . 101 to 011 . . . 100
AGND + 1 LSB 0.000092 0.000153 000 . . . 001 to 000 . . . 000
AGND 0.000000 0.000000 000 . . . 000 to 111 . . . 111
AGND – 1 LSB –0.000092 –0.000153 111 . . . 111 to 111 . . . 110
–(FSR/2 – 3 LSBs) –2.999726 –4.999543 100 . . . 011 to 100 . . . 010
–(FSR/2 – 2 LSBs) –2.999817 –4.999695 100 . . . 010 to 100 . . . 001
–(FSR/2 – 1 LSB) –2.999908 –4.999847 100 . . . 001 to 100 . . . 000
NOTES
1
This table applies for V
REF+
S = 3 V.
2
FSR (full-scale range) is 6 V for the ±3 V input range and 10 V for the
±5 V input range.
3
1 LSB on the ±3 V range is FSR/2
16
and is equal to 91.5 µV.
4
1 LSB on the ±5 V range is FSR/2
16
and is equal to 152.6 µV.
Table I. Ideal Output Code Table for the AD7884/AD7885
REV. E
AD7884/AD7885
–11–
AD7884/AD7885 PERFORMANCE
Linearity
The linearity of the AD7884/AD7885 is determined by the
on-chip 16-bit D/A converter. This is a segmented DAC that is
laser trimmed for 16-bit DNL performance to ensure that there
are no missing codes in the ADC transfer function. Figure 13
shows a typical INL plot for the AD7884/AD7885.
0 16384 32768 49152 65535
OUTPUT CODE
0
0.5
1.0
1.5
2.0
LINEARITY ERROR – LSBs
VDD = +5V
VSS = –5V
TA = 25ⴗC
Figure 13. AD7884/AD7885 Typical Linearity Performance
Noise
In an A/D converter, noise exhibits itself as code uncertainty in
dc applications and as the noise floor (in an FFT, for example)
in ac applications.
In a sampling A/D converter like the AD7884/AD7885, all
information about the analog input appears in the baseband
from dc to 1/2 the sampling frequency. An antialiasing filter will
remove unwanted signals above f
S
/2 in the input signal, but the
converter wideband noise will alias into the baseband. In the
AD7884/AD7885, this noise is made up of sample-and-hold noise
and A/D converter noise. The sample-and-hold section contrib-
utes 51 µV rms and the ADC section contributes 59 µV rms.
These add up to a total rms noise of 78 µV. This is the input
referred noise in the ±3 V analog input range. When operating
in the ±5 V input range, the input gain is reduced to –0.6. This
means that the input referred noise is now increased by a factor
of 1.66 to 120 µV rms.
Figure 14 shows a histogram plot for 5000 conversions of a dc
input using the AD7884/AD7885 in the ±5 V input range. The
analog input was set as close as possible to the center of a code
transition. All codes other than the center code are due to the
ADC noise. In this case, the spread is six codes.
3000
0
2000
1000
CODE FREQUENCY
(X – 2) (X – 1) (X) (X + 1) (X + 2) (X + 3)
CODE
Figure 14. Histogram of 5000 Conversions of a DC Input
If the noise in the converter is too high for an application, it can
be reduced by oversampling and digital filtering. This involves
sampling the input at a higher than the required word rate
and then averaging to arrive at the final result. The very fast
conversion time of the AD7884/AD7885 makes it very
suitable for oversampling. For example, if the required input
bandwidth is 40 kHz, the AD7884/AD7885 could be
oversampled by a factor of 2. This yields a 3 dB
improvement in the effective SNR performance.
The noise
performance in the ±5 V input range is now effectively 85 µV rms,
and the resultant spread of codes for 2500 conversions will be four.
This is shown in Figure 15.
1500
0
1000
500
CODE FREQUENCY
(X – 1) (X) (X + 1) (X + 2)
CODE
Figure 15. Histogram of 2500 Conversions of a DC Input
Using a
×
2 Oversampling Ratio
REV. E
AD7884/AD7885
–12–
Dynamic Performance
With a combined conversion and acquisition time of 6 µs, the
AD7884/AD7885 is ideal for wide bandwidth signal processing appli-
cations. Signal-to-(noise + distortion), total harmonic distortion,
peak harmonic or spurious noise, and intermodulation distortion
are all specified. Figure 16 shows a typical FFT plot of a 1.8 kHz,
±5 V input after being digitized by the AD7884/AD7885.
0
–150
–60
–120
–90
–30
2048 POINT FFT
dB
fIN = 1.8kHz, ⴞ5V SINE WAVE
fSAMPLE = 163kHz
SNR = 87dB
THD = –95dB
Figure 16. AD7884/AD7885 FFT Plot
Effective Number of Bits
The formula for SNR (see Terminology section) is related to
the resolution or number of bits in the converter. Rewriting the
formula, below, gives a measure of performance expressed in
effective number of bits (N).
N SNR=−
()
176 602..
16
10
80
13
11
20
12
0
15
14
60
40
FREQUENCY – kHz
EFFECTIVE NUMBER OF BITS
Figure 17. Effective Number of Bits vs. Frequency
The effective number of bits for a device can be calculated from
its measured SNR. Figure 17 shows a typical plot of effective
number of bits versus frequency for the AD7884. The sampling
frequency is 166 kHz.
MICROPROCESSOR INTERFACING
The AD7884/AD7885 is designed on a high speed process
that results in very fast interfacing timing (data access time of
57 ns max). The AD7884 has a full 16-bit parallel bus, and the
AD7885 has an 8-bit wide bus. The AD7884, with its parallel
interface, is suited to 16-bit parallel machines whereas the
AD7885, with its byte interface, is suited to 8-bit machines.
Some examples of typical interface configurations follow.
AD7884 to MC68000 Interface
Figure 18 shows a general interface diagram for the MC68000
16-bit microprocessor to the AD7884. In Figure 18, conversion
is initiated by bringing CSA low (i.e., writing to the appropriate
address). This allows the processor to maintain control over the
complete conversion process. In some cases, it may be more
desirable to control conversion independent from the processor.
This can be done by using an external sampling timer.
MC68000
AD7884
ADDRESS
DECODE LOGIC
CONVST
CS
RD
DB15–DB0
R/W
DATA BUS
ADDRESS BUS
A23–A1
D15–D0
DTACK
AS
CSA
CSB
Figure 18. AD7884 to MC68000 Interface
Once conversion has been started, the processor must wait until
it is completed before reading the result. There are two ways of
ensuring this. The first way is to simply use a software delay to
wait for 6.5 µs before bringing CS and RD low to read the data.
The second way is to use the BUSY output of the AD7884 to
generate an interrupt in the MC68000. Because of the nature of
its interrupts, the MC68000 requires additional logic (not shown
in Figure 18) to allow it to be interrupted correctly. For full
information on this, consult the MC68000 User’s Manual.
REV. E
AD7884/AD7885
–13–
AD7884 to 80286 Interface
The 80286 is an advanced high performance processor with
special capabilities aimed at multiuser and multitasking systems.
Figure 19 shows an interface configuration for the AD7884 to
such a system. Note that only signals relevant to the AD7884
are shown. For the full 80286 configuration, refer to the iAPX
286 data sheet (Basic System Configuration).
In Figure 19 conversion is started by writing to a selected
address and causing CS2 to go low. When conversion is complete,
BUSY goes high and initiates an interrupt. The processor can
then read the conversion result.
82288 BUS
CONTROLLER
MRDC
CLK
82284 CLOCK
GENERATOR
CLK
8282 OR
8283
LATCH
8286 OR 8287
TRANSCEIVER
DECODE
CIRCUITRY
8259A
INTERRUPT
CONTROLLER
CLK
D
15
–D
0
A23–A0
AD7884
RD
CS
CONVST
DB15
DB0
BUSY
IR
0
–IR
7
MEMORY READ
80286
CPU
CS1
CS2
Figure 19. AD7884 Interfacing to Basic iAPX 286 System
AD7885 to 8088 Interface
The AD7885, with its byte (8 + 8) data format, is ideal for use
with the 8088 microprocessor. Figure 20 is the interface diagram.
Conversion is started by enabling CSA. At the end of conversion,
data is read into the processor. The read instructions are:
MOV AX, C001 Read 8 MSBs of data
MOV AX, C000 Read 8 LSBs of data
8088
AD7885
ADDRESS
DECODE LOGIC
CONVST
CS
RD
DB7–DB0
MN/MX
DATA BUS
ADDRESS BUS
A15–A8
AD7–AD0
5V
A0
HBEN
RD
STB
8282
ALE
IO/M
CSB CSA
Figure 20. AD7885 to 8088 Interface
REV. E
AD7884/AD7885
–14–
AD7884 to ADSP-2101 Interface
Figure 21 shows an interface between the AD7884 and the
ADSP-2101. Conversion is initiated using a timer that allows
very accurate control of the sampling instant. The AD7884 BUSY
line provides an interrupt to the ADSP-2101 when conversion is
completed. The RD pulsewidth of the processor can be programmed
using the Data Memory Wait State Control register. The result
can then be read from the ADC using the following instruction:
MR DM ADC0=
()
where MR0 is the ADSP-2101 MR0 register, and ADC is the
AD7884 address.
ADSP-2101
AD7884
ADDRESS
DECODE LOGIC
CONVST
CS
BUSY
DB15–DB0
DATA BUS
ADDRESS BUS
DMA13–DMA0
DMD15–DMD0
IRQn
EN
DMS
TIMER
RDRD
Figure 21. AD7884 to ADSP-2101 Interface
Standalone Operation
If CS and RD are tied permanently low on the AD7884, then,
when a conversion is completed, output data will be valid on the
rising edge of BUSY. This makes the device very suitable for
standalone operation. All that is required to run the device is an
external CONVST pulse that can be supplied by a sample timer.
Figure 22 shows the AD7884 set up in this mode with the BUSY
signal providing the clock for the 74HC574 three-state latches.
TIMER
AD7884
CONVST
CS
RD
DB15–DB8
BUSY
HBEN
A0
74HC574
74HC574
CLK
CLK
DB7–DB0
Figure 22. Standalone Operation
Digital Feedthrough from an Active Bus
It is very important when using the AD7884/AD7885 in a
microprocessor based system to isolate the ADC data bus from
the active processor bus while a conversion is being executed.
This yields the best noise performance from the ADC. Latches
like the 74HC574 can be used to do this. If the device is connected
directly to an active bus, then the converter noise typically increases
by a factor of 30%.
REV. E
AD7884/AD7885
–15–
OUTLINE DIMENSIONS
28-Lead Ceramic DIP-Glass Hermetic Seal [CERDIP]
(Q-28)
Dimensions shown in inches and (millimeters)
28
114
15
0.610 (15.49)
0.500 (12.70)
PIN 1
0.005 (0.13)
MIN
0.100 (2.54)
MAX
15
0
0.620 (15.75)
0.590 (14.99)
0.018 (0.46)
0.008 (0.20)
SEATING
PLANE
0.225(5.72)
MAX
1.490 (37.85) MAX
0.150 (3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.015 (0.38)
MIN
0.026 (0.66)
0.014 (0.36)
0.100
(2.54)
BSC
0.070 (1.78)
0.030 (0.76)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
40-Lead Ceramic DIP-Glass Hermetic Seal [CERDIP]
(Q-40)
Dimensions shown in inches and (millimeters)
40
120
21
PIN 1
0.005 (0.13)
MIN
0.100 (2.54)
MAX
0.620 (15.75)
0.510 (12.95)
SEATING
PLANE
0.225 (5.72)
MAX
2.096 (52.23) MAX
0.200 (5.08)
0.125 (3.18)
0.026 (0.66)
0.014 (0.36)
0.100 (2.54)
BSC
0.065 (1.65)
0.045 (1.14)
0.070 (1.78)
0.015 (0.38)
15
0
0.63 (16.00)
0.59 (14.93)
0.018 (0.46)
0.008 (0.20)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
REV. E
–16–
C01353–0–2/03(E)
PRINTED IN U.S.A.
AD7884/AD7885
Revision History
Location Page
2/03—Data Sheet changed from REV. D to REV. E.
Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Data Sheet changed from REV. C to REV. D.
Addition of CERDIP package to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
“J” Column added to Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
CERDIP added to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Edit to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Addition of Q-28 Outline Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
OUTLINE DIMENSIONS
44-Lead Plastic Leaded Chip Carrier [PLCC]
(P-44A)
Dimensions shown in inches and (millimeters)
BOTTOM VIEW
(PINS UP)
6
PIN 1
IDENTIFIER
7
40
39
17
18
29
28
TOP VIEW
(PINS DOWN)
0.656 (16.66)
0.650 (16.51) SQ
0.048 (1.22)
0.042 (1.07)
0.050
(1.27)
BSC
0.695 (17.65)
0.685 (17.40) SQ
0.048 (1.22)
0.042 (1.07)
0.021 (0.53)
0.013 (0.33)
0.630 (16.00)
0.590 (14.99)
0.032 (0.81)
0.026 (0.66)
0.180 (4.57)
0.165 (4.19)
0.040 (1.02)
0.025 (0.64)
0.056 (1.42)
0.042 (1.07) 0.020 (0.51)
MIN
0.120 (3.05)
0.090 (2.29)
COMPLIANT TO JEDEC STANDARDS MO-047AC
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN