pM DPZ2MX8J3 Dense-Pac Microsystems, Inc. 2 MEG X 8 FLASH EEPROM J LEADED STACK MODULE PRELIMINARY DESCRIPTION: The DPZ2MxX8J3 STACK module is a revolutionary new memory subsystem using Dense-Pac Microsystems ceramic Stackable Leadless Chip Carriers (SLCC) stacked and leaded for surface mount applications. It offers 16 Megabits of FLASH EEPROM in an area of just under one-half square inch (0.463 in.*), while maintaining a height of only 0.765 inches. The DPZ2MxX8)J3 is built with eight stacked SLCC packages each containing two 128K x 8 FLASH memory devices. Each SLCC is hermetically sealed making the module suitable for commercial, industrial and military applications. By using SLCCs, the Stack family of modules offers a higher board density of memory than available with conventional through-hole, surface mount, module, or most hybrid techniques. FEATURES: * Organization: 2Meg x 8 PIN NAMES * Fast Access Times: 120, 150, 170, 200, 250ns (max.) AO-A16 Address Inputs * Fully Static Operation - No clock or refresh required 1/00 - 1/07 Data Input/Output * TTL Compatible Inputs and Outputs Cho. Chis Chip Enables Common Data Inputs and Outputs = . : WE Write Enable Automatic Erase Function - Reduces CPU overhead OE Output Enable * 10,000 Erase/Program Cycles (min.} Vpp Programming Voltage * 48 PIN J Leaded STACK Package (+12.5V) * Available in commercial only. ve Ss roun PIN-OUT DIAGRAM N.C. No Connect ct? 1 cE6 5 2 VPP CES 3 =) = CE4 FUNCTIONAL BLOCK DIAGRAM TE1 4 | eee = CE2 Ne. | Geeoeeey | res we 5G Ba fe cr a! as aE ae We tEI3 gf /00-1/07 azo 4a Ais tei $ 46 (10 0 p39 AB Chie a ug 38 Ag tE9 Ag 120 Fe37 All 8 M4 6 A3 130 36 OF TE? z A2 40 fP35 Ai CE6 2 Al 15 rp 34 CEO cr 5 4g 16 33 CEI5 eB: a 13 170 I> 32 CE14 C12 18 ro 31 CEI2 CES 1% ts iG 30 Cee CE2 3 VSS 289 29 CEB Ch Ble SHBG LY tp =] 3/2 08 21 | i 28 1/07 VPP e als 1/01 22 | 27 1/06 OE : 1/02 23 26 1/05 WE =} 3 1/03 24 25 1/04 AQA1G my 30A085-00 1DPZ2MX8jJ3 Dense-Pac Microsystems, Inc. PRELIMINARY DEVICE OPERATION: The FLASH devices are electrically erasable and program- mable memories that function similarly to an EPROM device, but can be erased without being removed from the system and exposed to ultraviolet light. Each 128K x 8 device can be erased individually eliminating the need to reprogram the entire module when partial code changes are required. READ: With Vpp = OV to Vpp (Verto), the devices are read-only memories and can be read like a standard EPROM, By selecting the device to be read (see Truth Table and Functional Block Diagram), the data programmed into the device will appear on the appropriate 1/O pins. When Vpp = +12.5V + 0.5V (Vept), reads can be accomplished in the same manner as described above but must be preceded by writing OOH to the command register prior to reading the device. When Vpp is raised to VprH the contents of the command register default to OOH and remain that way until the command register is altered. STANDBY: When the appropriate CEs are raised to a logic-high level, the standby operation disables the FLASH devices reducing the power consumption substantially. The outputs are placed in a high- impedance state, independent of the OF input. If the module is deselected during programming, erasure, or autoerase, the device upon which the operation was being performed will continue to draw active current until the operation is completed. PROGRAM: The programming and erasing functions are accessed via the command register when high voltage is applied to Vpp. The contents of the command register control the functions of the memory device (see Command Definition Table). The command register is not an addressable memory location. The register stores the address, data, and command informa- tion required to execute the command. When Vpp = VepLo the command register is reset to OOH returning the device to the read-only mode. The command register is written by enabling the device upon which that the operation is to be performed (see Functional Block Diagram). While the device is enabled bring WE to a logiclow (Vii). The address is latched on the falling edge of WE and datais latched on the rising edge of WE. Programming is initiated by writing 40H (program setup command) to the command register. On the next falling edge of WE the address to be programmed will be latched, followed by the data being latched on the rising edge of WE (see AC Operating and Characteristics Table). PROGRAM VERIFY: The FLASH devices are programmed one location at a time. Each location may be programmed sequentially or at random. Following each programming operation, the data written must be verified. To initiate the program-verify mode, COH must be written to the command register of the device just programmed. The programming operation is terminated on the rising edge of WE. The programverify command is then written to the command register. After the programverify command is written to the command register, the memory device applies an internally generated margin voltage to the location just written. After waiting 6ps the data written can be verified by doing a read. If true data is read from the device, the location write was successful and the next location may be programmed. If the device fails to verify, the program/verify operation is repeated up to 20 times. ERASE: The erase function is a command-only operation and can only be executed while Vpp = Vppri. To setup the chip-erase, 20H must be written to the command register. The chip-erase is then executed by once again writing 20H to the command register (see AC Operating and Charac- terstics Table). To ensure a reliable erasure, all bits in the device to be erased should be programmed to their charged state (data = OOH) prior to starting the erase operation. With the algorithm provided, this operation should take approximately 8 seconds (typ.). ERASE VERIFY: The erase operation erases all locations in the device selected in parallel. Upon completion of the erase operation, each location must be verified. This operation is initiated by writing AOH to the command register. The address to be verified must be supplied in order to be latched on the falling edge of WE. The memory device internally generates a margin voltage and applies it to the addressed location. If FFH is read from the device, it indicates the location is erased. The erase/verify command is issued prior to each location verification to latch the address of the location to be verified. This continues until FFH is not read from the device or the last address for the device being erased is read. If FFH is not read from the location being verified, an addition- al erase operation is performed. Verification then resumes from the last location verified. Once all locations in the device being erased are verified, the erase operation is complete. The verify opertation should now be terminated by writing a valid command such as program set-up to the command register. a 30A085-00 REV. ADense-Pac Microsystems, Inc. DPZ2MX8J3 PRELIMINARY AUTOMATIC ERASE: An automatic erase function is also available eliminating the need to program all locations to OOH or do an erase verify. The automatic erase will program all locations to OOH and do a continuous erase/verify until all locations in the device are erased. To setup the chip-erase, 30H must be written to the command register. The chip-erase is then executed by once again writing 30H to the command register (see AC Operating Charac- teristics Table). To determine if the automatic erase cycle is complete, the most-significant I/O pin for the device being erased (1/O7) is read. if the data on this bit = 0 the cycle is not complete. The erase cycle is complete when the data = 1 on 1/O7 for the device being erased. DESIGN CONSIDERATIONS: Ver traces should use trace widths and layout considerations comparable to that of the Vop power bus. The Vpp supply traces should also be decoupled to help decrease voltage spikes. Power-up sequencing should be such that Vpp doesnt go above Vpp + 2.0V before Vop reaches a steady state voltage, while on power-down Vpp should be below Vop + 2.0V before Voo is lowered. Itis recommended that a 4.7pF to 10pF electrolytic capacitor be placed near the memory module connected across Vop and Vss for bulk storage. Decoupling capacitors should also be placed near the module, connected across Vpp and Vss. COMMAND DEFINITION TABLE Bus First Bus Cycle Second Bus Cycle COMMAND Rad Operation Address Data Operation Address Data Read Memory 1 Write x 00H * : : Setup Erase / Erase 2 Write x 20H Write x 20H Erase Verify 2 Write EA AOH Read x EvD Setup Autoerase / Autoerase 2 Write x 30H Write xX 30H Setup Program / Program 2 Write x 40H Write PA PD Program Verify 2 Write x CoH Read~ x PvD Reset 2 Write xX FFH ' Write x FFH EA = Address to Verify PA = Address to Program EVD = Data Read from Location EA PD = Data to be Programmed at Location PA PVA = Data to be Read from Location PA at Program Verify TRUTH TABLE MODE DESCRIPTION CEn WE OE Vpp 1/O Pins Supply Current Not Selected H xX x Verto High-Z Standby breed Output Disable L H H Verio High-Z Active Read t H L Verto DOUT Active Not Selected H x xX Verran High-Z Standby COMMAND Output Disable L H H Veera High-Z Active PROGRAM Read t H L Vepri DOUT Active Write L L H Vera DIN Active 30A085-00 3 REV.ADPZ2MX8J3 PRELIMINARY Dense-Pac Microsystems, Inc. RECOMMENDED OPERATING RANGE! CAPACITANCE 5: T, = 25C, F = 1.0MHz Symbol Characteristic Min. | Typ.| Max. | Unit Symbol Parameter Max. | Unit | Condition Vop | Supply Voltage 4.5 | 5.0 5.5 Vv Caper | Address Input 100 Ver _} Programming Voltage? | 12.0|12.5} 13.0 Vv Cce_ | Chip Enable 25 Vit Input LOW Voltage 0.33 0.8 Vv Cwe_ | Write Enable 100 pF Vin? = OV Vin Input HIGH Voltage 2.2 Vop+1.0| V Coe | Output Enable 100 Ta _ | Operating Temp. -55 {+25} +125 | c Cyo_| Data Input/Output {| 140 ABSOLUTE MAXIMUM RATINGS Parameter to +150 Bias -55 to +125 0.6 to + DC OUTPUT CHARACTERISTICS Symbol| Parameter Conditions } Min. | Max.| Unit 0.6 to +14.0 Von | HIGH Voltage |lon-400pA| 2.4 : Vv 0.6 to +7.0 Vor | LOW Voltage low=2.1mMA - {0.451 V DC OPERATING CHARACTERISTICS: Over operating ranges Limits Symbol Characteristics Test Conditions Ke Min Max. Unit lin Input Leakage Current Vin = OV to Vpo : 30 +30 pA lout Output Vyo = OV to Vop, . : Leakage Current or OE = Vin, or WE = Vit 30 +30 HA lect Active CE = Vi, Vin = Via oF Ving Supply Current lout = OmA, f = OMHz 20 30 mA lec2 Operating CE = Vi, Vin = Va or Ving Supply Current lout = OmA, f = 8MHz 40 65 mA Icea Voo Programming Current Programming in Progress 15 35 mA loos Voo Erase Current Erasure in Progress 25 55 mA Isa Standby Current (TTL) CE = Vin 16 mA {sez Full Standby Supply Current (CMOS) | CE = Vpp -0.2V 3.2 mA lpps Vep Leakage Current Vee = Verto 320 HA tppr Ver Read Current Veep = Vern 20 mA lpp2 Vep Programming Current Vee = Ver, Programming in Progress 8 50 mA Ippa Vpp Erase Current Vep = Vppra, Erasure in Progress 40 100 mA * Typical measurements made at +25C, Cycle = min, Voo = 5.0V. 4 30A085-00 REV. ADense-Pac Microsystems, Inc. D PZ2 MX8J3 PRELIMINARY AC TEST CONDITIONS Input Pulse Levels OV to 3.0V Figure 1. Output Load Input Pulse Rise and Fall Times 5ns * Including Probe and jig Capacitance. Input and Output Timing Reference Levels 1.5V +BY Output Timing Reference Levels Durring Verify 0.8 and 2.4V 1.8KQ Dour OUTPUT LOAD a* 1.3KQ Load] Cr Parameters Measured T 1 100 pF | except tor >= > 2 30 pF] tor AC OPERATING CONDITIONS AND CHARACTERISTICS - READ CYCLE: Over operating ranges -120 -150 170 -200 -250 No.| Symbol Parameter Min, | Max.| Min.|Max.| Min,| Max,| Min.| Max.| Min.| Max. Unit 1 tce Chip Enable Access Time 120 150 170 200 250| ns 2 tacc Address Access Time 120 150 170 200 250] ns 3 toe Output Enabe Access Time 60 70 75 80 90 | ns 4 tor Output Disable to Output in HIGH-Z 5. 6 oO | 40] 0 | 50/ 0 | 55 60 70 | ns 5 ton Output Hold from Address Change 5 5 5 5 5 ns AC OPERATING CONDITIONS AND CHARACTERISTICS - WRITE CYCLE: Over operating ranges -120 -150 -170 -200 -250 No.| Symbol Parameter Min.} Max.| Min.}| Max.| Min.| Max.| Min.| Max] Min.| Max. Unit 6 tewc__| Write Cycle Time 120 150 170 200 250 ns 7 tas Address Setup Time 0 0 0 0 0 ns 8 taH Address Hold Time 60 60 60 60 60 ns 9 tos Data Setup Time 50 50 50 50 50 ns 10 toy Data Hold Time 10 10 10 10 10 ns 4 ices Chip Enable Setup Time 0 0 0 0 0 ns 12 tceH Chip Enable Hold Time 15 15 15 15 15 ns 13 tves Ver Setup Time 7, 8 100 100 100 100 100 ns 14 | __tvpH_ _| Veep Hold Time 7 8 100 100 100 100 100 ns 15 twee Write Enable Pulse Width 70 70 80 80 90 ns 16 tWeH Write Enable Pulse Width HIGH Time 20 20 20 20 20 ns Output Enable Setup Time before 171 loews | Command Programming 0 0 0 0 0 ns 18 | _ toers Output Enable Setup Time before Verify 6 6 6 6 6 ps 19 tva Verify Access Time 120 150 170 200 250} ns 20 | __toers Output Enable Setup Time before Status Polling | 20 20 20 20 20 ns 21 (sPA Status Polling Access Time 120 150 170 200 250} _ns 22 tppw Standby Time before Programming 25 25 25 25 25 ps 23 teT Standby Time in Erase VW a Wy] ~ YW 11 ms 24 tact Total Erase Time in Autoerase 9 05} 30}05) 30}0.5] 30/05} 30} 65 | 30 S 30A085-00 5 REV. ADP Z2MX8Jj3 Dense-Pac Microsystems, Inc. PRELIMINARY READ CYCLE TRC ADDRESS ADDRESS VALIO TCE CEO - CE1S DATA OUT HIGH-Z OUTPUT VALID PROGRAMMING CYCLE SETUP PROGRAM tm Pai PROGRAM VERY em= Voo (5.0V) TVPH TVPS 12.5V Vep 5.0V RRR ORRIN eee ADDRESS Qi RK RK KORA _vALuO TASse- TCEH -o < TCEH ~~ \ / CEo - CE15 \ L/ TCEH TCES =] hone Ices - oe Of \ 4 TCW a4 a TPP W__ any Let TOERS 0m TOEWS TWEH TWEP TWEP. WE \ x * t y TOs | 10H Tos | TDH 1s | 1H TVA Le DATA I/O sic-z { Comano DATA N Comm ano X ois SY 6 30A085-00Dense-Pac Microsystems, Inc. DPZ2 MX8J3 PRELIMINARY ERASE CYCLE pat- SETUP ERASE ERASE ERASE VERIFY -em Vp (5.0V) TVPH Tvs 12.5V Vep 5.0V TaS | TAH rrammaeeeererrernerenreenoeneeeeny ADDRESS VAI PRK RK RRR KIRK | TCEH _ TCEH TCEH CEo - CE15 N x TCES am TCES _ TCES se DE { \ / TCWC TET om Lae TOERS-] TOEWS| TWEH TWEP TWEP TWEP \ y N y \ yo WE NS LS WS VA TOF _ TDS | TOH tps | TDH Tos | ToH pe DATA I/O Hich-z { command COmMAND ComMan ott WAVEFORM KEY TM. _WMZ BRE Data Valid Transition from Transition from Data Undefined HIGH to LOW LOW to HIGH or Dont Care 30A085-00 REV.A 7DPZ2 MX8j 3 Dense-Pac Microsystems, Inc. PRELIMINARY AUTOMATIC ERASE CYCLE ~=*-_ SETUP AUTO ERASE pai-- AUTO ERASE & STATUS POQLUNG @4 Von (5.0V) TVPH WPS 12.5V Vpp 5.0V ADDRESS ol TCEH =~ TCEH CE0 - CE15 \ I TCES -=| jo ICES lee- |TCES Le OE K \ x Towe peneTOE PS a) TOEWS TWEH TAET TWEP TWEP we X t \ 10S | TOH tos | 1DH TSPA Or a -gd O7 vicn-2 f om Comuan f + pa STATUS POLLING -_e 1/00 - 1/06 HGH-2 coun cone NOTES: 1. All voltages are with respect to Vss. 2. When operating device at temperatures less than 0C (-55C to 0C) (Vep must be at 7.4 Vdc above Vpp durring Program/Erase functions, 3. -2.0V min. for pulse width less than 20ns (Vii min. = -0.6V at DC level). 4. Stresses greater than those under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. This parameter is guaranteed and not 100% tested. Transition is measured at the point of 500mV from steady state voltage. Vcc must be applied before Vep and removed after Vpp. . Vpp must not exceed 14V, including overshoot. . The total erase times shown are for one (1) 128Kx8 device, to erase the entire module would be 16x the times shown. CONAN REV.ADense-Pac Microsystems, Inc. DPZ2 MX8]J3 PRELIMINARY WRITE ALGORITHM START PROGRAMMING VPP = 12.5V : WRITE. SETUP PROGRAM COMMAND ! WRITE VALID DATA TIME OUT 25 ys WRITE PROGRAM VERIFY COMMAND TIME OUT 6 us READ DATA FROM DEVICE SET VPP = @V TO VOO +2.aV PROGRAM ERROR NO LAST ADDRESS q NEXT ADDRESS YES WRITE READ COMMAND 4 SET VPP = BV TO VDD +2.0V PROGRAMMING COMPLETED 30A085-00 9 REV. ADP Z2 MX8J3 Dense-Pac Microsystems, Inc. PRELIMINARY ERASE ALGORITHM START ERASURE Yes or NO ROGRAM LOCATIONS TO B@H ADDRESS = ADDRESS MIN, WRITE ERASE SETUP COMMAND WRITE ERASE COMMAND WRITE ERASE VERIFY COMMAND TIME OUT 6 us g 2 5 F READ DATA FROM DEWCE NO NO wc COUNT = 3026 7 YES ves SET vPP = NO @V TO VOD +2.8v ERASE ves ERROR WRITE READ COMMAND INCREMENT ADDRESS y VPP = @v TO VOD +2.eV ERASURE COMPLETED 10 30A085-00 REV.ADense-Pac Microsystems, Inc. PRELIMINARY DPZ2MX8jJ3 AUTOMATIC ERASE START AUTOMATIC ERASURE VPP = 12.5V WRITE AUTOERASE SETUP COMMAND WRITE AUTOERASE COMMAND STATUS POLLING ON 1/07 NO NO 38 1/07 =) SECONDS LATER ? YES YES WRITE READ COMMAND Fai SET VPP = @V TO VOD +2.8v ERASURE COMPLETED 30A085-00 REV. A 11DPZ2MX8J3 Dense-Pac Microsystems, Inc, aL PRELIMINARY ORDERING INFORMATION DP Z2MX8 J3 ~XX xX PREFIX DEVICE TYPE PACKAGE SPEED C COMMERCIAL BC to +70 1 INDUSTRIAL ~40C to +85'C M MILITARY ~55C to +125C B MiL~PROCESSED -55C to +125C DENSE=PAC 12. 12@ns (COMMERCIAL ONLY) 1 158ns 17. 178ns 28 28@ns 25 25@ns 48 PIN J-LEADED (3-D) STACK 2 MEG x 8 FLASH EEPROM MECHANICAL DRAWING G i # y i # er | LL ssee.cr0- -765 MAX, -@58 TYP, TE ena on +815 +328 2 "p95 Dense-Pac Microsystems, Inc. 7321 Lincoln Way @ Garden Grove, California 92641-1428 (714) 898-0007 @ (800) 642-4477 (Outside CA) @ FAX: (714) 897-1772 12 30A085-00 REV.A