SEMICONDUCTOR TECHNICAL DATA High-Performance Silicon-Gate CMOS The MC54/74HC573A is identical in pinout to the LS573. The devices are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. These latches appear transparent to data (i.e., the outputs change asynchronously) when Latch Enable is high. When Latch Enable goes low, data meeting the setup and hold time becomes latched. The HC573A is identical in function to the HCT373A but has the data inputs on the opposite side of the package from the outputs to facilitate PC board layout. The HC573A is the noninverting version of the HC563A. J SUFFIX CERAMIC PACKAGE CASE 732-03 20 1 N SUFFIX PLASTIC PACKAGE CASE 738-03 20 1 DW SUFFIX SOIC PACKAGE CASE 751D-04 20 1 * * * * * Output Drive Capability: 15 LSTTL Loads Outputs Directly Interface to CMOS, NMOS and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 A In Compliance with the Requirements Defined by JEDEC Standard No. 7A * Chip Complexity: 218 FETs or 54.5 Equivalent Gates DT SUFFIX TSSOP PACKAGE CASE 948E-02 20 1 ORDERING INFORMATION Ceramic Plastic SOIC TSSOP MC54HCXXXAJ MC74HCXXXAN MC74HCXXXADW MC74HCXXXADT LOGIC DIAGRAM D0 D1 D2 DATA INPUTS D3 D4 D5 D6 D7 LATCH ENABLE OUTPUT ENABLE 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 PIN ASSIGNMENT Q0 OUTPUT ENABLE D0 Q1 Q2 Q3 Q4 NONINVERTING OUTPUTS Q5 Q6 Q7 11 1 PIN 20 = VCC PIN 10 = GND Value Units Internal Gate Count* 54.5 ea. Internal Gate Propagation Delay 1.5 ns Internal Gate Power Dissipation 5.0 Speed Power Product 0.0075 20 VCC 2 19 Q0 D1 3 18 Q1 D2 4 17 Q2 D3 5 16 Q3 D4 6 15 Q4 D5 7 14 Q5 D6 8 13 Q6 D7 9 12 10 11 Q7 LATCH ENABLE GND IIIIIIIIII IIII III IIIIIIIIII IIII III IIIIIIIIII IIII III III IIIIIIIIII IIII IIIIIIIIII IIII III IIIIIIIIII IIII III IIIIIIIIII IIII III Design Criteria 1 FUNCTION TABLE Inputs W pJ * Equivalent to a two-input NAND gate. Latch Enable D Q L L L H H H L X H L X X H L No Change Z X = Don't Care Z = High Impedance 10/96 Motorola, Inc. 1996 1 REV 7 Output Output Enable MC54/74HC573A IIIIIIIIIIIIIIIIIIIIIII III IIIIIIIIIIIIII IIIIII III IIIIIIIIIIIIIIIIIIIIIII III IIIIIIIIIIIIII IIIIII III III IIIIIIIIIIIIII IIIIII III III IIIIIIIIIIIIII IIIIII III III IIIIIIIIIIIIII IIIIII III III IIIIIIIIIIIIII IIIIII III III IIIIIIIIIIIIII IIIIII III III IIIIIIIIIIIIII IIIIII III III IIIIIIIIIIIIII IIIIII III III IIIIIIIIIIIIII IIIIII III III IIIIIIIIIIIIII IIIIII III III IIIIIIIIIIIIII IIIIII III III IIIIIIIIIIIIII IIIIII III III IIIIIIIIIIIIII IIIIII III MAXIMUM RATINGS* Symbol VCC Parameter DC Supply Voltage (Referenced to GND) Value Unit - 0.5 to + 7.0 V Vin DC Input Voltage (Referenced to GND) - 0.5 to VCC + 0.5 V Vout DC Output Voltage (Referenced to GND) - 0.5 to VCC + 0.5 V DC Input Current, per Pin 20 mA DC Output Current, per Pin 35 mA DC Supply Current, VCC and GND Pins 75 mA 750 500 450 mW - 65 to + 150 _C Iin Iout ICC PD Tstg TL Power Dissipation in Still Air, Plastic or Ceramic DIP SOIC Package TSSOP Package Storage Temperature This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. v v _C Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP, TSSOP or SOIC Package) (Ceramic DIP) 260 300 * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C Ceramic DIP: - 10 mW/_C from 100_ to 125_C SOIC Package: - 7 mW/_C from 65_ to 125_C TSSOP Package: -6.1 mW/C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). IIII IIIIIIIIIIIIII III III III IIII IIIIIIIIIIIIII III III III IIII IIIIIIIIIIIIII III III III IIII IIIIIIIIIIIIII III III III IIII IIIIIIIIIIIIII III III III IIII IIIIIIIIIIIIII III III III IIII IIIIIIIIIIIIII III III III IIII IIIIIIIII IIIIIIIII IIII IIIIIIIII III IIII IIIIIIIII IIIIIIIII IIII III IIII IIII III IIIIIIIII v IIII v III IIII IIIIIIIII IIIIIIIII IIII III IIII III IIII IIIIIIIII IIIIIIIII IIII IIII IIII III v IIII IIIIIIIII IIIIIIIII IIII III IIII IIII III III IIII IIIIIIIII IIIIIIIII IIII IIII IIII III IIII IIIIIIIII IIIIIIIII IIII III IIII IIII III v III IIII IIIIIIIII IIIIIIIII IIII IIII IIII III III IIII IIIIIIIII IIIIIIIII IIII IIII IIII III v IIII IIIIIIIII IIIIIIIII IIII III IIII IIII III III IIII IIIIIIIII IIIIIIIII IIII IIII IIII III v IIII IIII IIIIIIIII IIIIIIIII III IIII IIII III v IIII IIIIIIIII IIIIIIIII IIIIIII IIII IIII III RECOMMENDED OPERATING CONDITIONS Symbol VCC Vin, Vout Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time (Figure 1) VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V Min Max Unit 2.0 6.0 V 0 VCC V - 55 + 125 _C 0 0 0 1000 500 400 ns DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Guaranteed Limit S b l Symbol P Parameter T Test C Conditions di i VCC V - 55 to 25_C 85_C 125_C U i Unit VIH Minimum High-Level Input Voltage Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A 2.0 3.0 4.5 6.0 1.5 2.1 3.15 4.2 1.5 2.1 3.15 4.2 1.5 2.1 3.15 4.2 V VIL Maximum Low-Level Input Voltage Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A 2.0 3.0 4.5 6.0 0.5 0.9 1.35 1.8 0.5 0.9 1.35 18 0.5 0.9 1.35 1.8 V Minimum High-Level Output Voltage Vin = VIH or VIL |Iout| 20 A 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V 3.0 4.5 6.0 2.48 3.98 5.48 2.34 3.84 5.34 2.2 3.7 5.2 VOH Vin = VIH or VIL |Iout| 2.4mA |Iout| 6.0 mA |Iout| 7.8 mA NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). MOTOROLA 2 High-Speed CMOS Logic Data DL129 -- Rev 6 MC54/74HC573A IIII IIIIIIIII IIIIIIIII IIII IIIIIIIII III IIII IIIIIIIII IIIIIIIII IIII III IIII IIII III IIIIIIIII IIII IIIIIIIII IIIIIIIII IIIIIII IIII v IIII v III III IIII IIIIIIIII IIIIIIIII IIII IIII IIII III v IIII IIIIIIIII IIIIIIIII IIII III IIII IIII III III IIII IIIIIIIII IIIIIIIII IIII IIII IIII III v IIII IIIIIIIII IIIIIIIII III IIII IIII III v IIII III IIII IIIIIIIII IIIIIIIII IIII IIII IIII III IIII IIIIIIIII IIIIIIIII IIII III IIII IIII III IIII IIIIIIIII IIIIIIIII IIII III IIII IIII III III IIII IIIIIIIII IIIIIIIII IIII IIII IIII III IIII IIIIIIIII IIIIIIIII IIII III IIII IIII III IIII IIIIIIIII IIIIIIIII IIIIIII IIII IIII III IIII IIIIIIIIIIIIIIIII IIII IIIIIIIII III IIII IIIIIIIIIIIIIIIII IIII III IIII IIII III IIIIIIIII IIII IIIIIIIIIIIIIIIII IIII III IIII v IIII v III III IIII IIIIIIIIIIIIIIIII IIII IIII IIII III IIII IIIIIIIIIIIIIIIII IIII III IIII IIII III III IIII IIIIIIIIIIIIIIIII IIII IIII IIII III III IIII IIIIIIIIIIIIIIIII IIII IIII IIII III IIII IIIIIIIIIIIIIIIII IIIIIII IIII IIII III III IIII IIIIIIIIIIIIIIIII IIII IIII IIII III III IIII IIIIIIIIIIIIIIIII IIII IIII IIII III IIII IIIIIIIIIIIIIIIII IIII III IIII IIII III III IIII IIIIIIIIIIIIIIIII IIII IIII IIII III III IIII IIIIIIIIIIIIIIIII IIII IIII IIII III IIII IIIIIIIIIIIIIIIII IIIIIII IIII IIII III III IIII IIIIIIIIIIIIIIIII IIII IIII IIII III III IIII IIIIIIIIIIIIIIIII IIII IIII IIII III IIII IIIIIIIIIIIIIIIII IIII III IIII IIII III III IIII IIIIIIIIIIIIIIIII IIII IIII IIII III IIIIIIIIIIIIIIIIIIII III IIII IIIIIIIIIIIIIIIII IIII IIII IIII III IIII IIIIIIIIIIIIIIIIIIII III IIII IIII III IIII IIIIIIIIIIIIIIIIIIII III IIII IIII III DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Guaranteed Limit S b l Symbol VOL P Parameter T Test C Conditions di i Maximum Low-Level Output Voltage Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A Vin = VIH or VIL |Iout| 2.4mA |Iout| 6.0 mA |Iout| 7.8 mA VCC V - 55 to 25_C 85_C 125_C 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 3.0 4.5 6.0 0.26 0.26 0.26 0.33 0.33 0.33 0.4 0.4 0.4 U i Unit V Iin Maximum Input Leakage Current Vin = VCC or GND 6.0 0.1 1.0 1.0 A IOZ Maximum Three-State Leakage Current Output in High-Impedance State Vin = VIL or VIH Vout = VCC or GND 6.0 - 0.5 - 5.0 - 10 A ICC Maximum Quiescent Supply Current (per Package) Vin = VCC or GND IIoutI = 0 A 6.0 4.0 40 160 A NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns) Guaranteed Limit S b l Symbol P Parameter VCC V - 55 to 25_C 85_C 125_C U i Unit tPLH, tPHL Maximum Propagation Delay, Input D to Q (Figures 1 and 5) 2.0 3.0 4.5 6.0 150 100 30 26 190 140 38 33 225 180 45 38 ns tPLH, tPHL Maximum Propagation Delay, Latch Enable to Q (Figures 2 and 5) 2.0 3.0 4.5 6.0 160 105 32 27 200 145 40 34 240 190 48 41 ns tPLZ, tPHZ Maximum Propagation Delay, Output Enable to Q (Figures 3 and 6) 2.0 3.0 4.5 6.0 150 100 30 26 190 125 38 33 225 150 45 38 ns tPZL, tPZH Maximum Propagation Delay, Output Enable to Q (Figures 3 and 6) 2.0 3.0 4.5 6.0 150 100 30 26 190 125 38 33 225 150 45 38 ns tTLH, tTHL Maximum Output Transition Time, Any Output (Figures 1 and 5) 2.0 3.0 4.5 6.0 60 27 12 10 75 32 15 13 90 36 18 15 ns Maximum Input Capacitance 10 10 10 pF Maximum Three-State Output Capacitance (Output in High-Impedance State) 15 15 15 pF Cin Cout NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High- Speed CMOS Data Book (DL129/D). Typical @ 25C, VCC = 5.0 V CPD P Power Di Dissipation i i C Capacitance i (P (Per E Enabled bl d O Output)* )* 23 pF F * Used to determine the no-load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). High-Speed CMOS Logic Data DL129 -- Rev 6 3 MOTOROLA MC54/74HC573A IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIII III III IIIIIIIIIIII III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIII III III IIIII IIIII IIII IIIIIIIIIIII v v III IIII IIIIIIIIIIIII III III III III III III III II III IIIII IIIII IIII IIII IIIIIIIIIIIII III III III III III III III II III II IIII IIIIIIIIIIIII III III III III III III III III IIII IIIIIIIIIIIII III III III III III III III II III II IIII IIIIIIIIIIIII III III III III III III III III II IIII IIIIIIIIIIIII III III III III III III III III IIII IIIIIIIIIIIII III III III III III III III II III II IIII IIIIIIIIIIIII III III III III III III III III II IIII IIIIIIIIIIIII III III III III III III III III IIII IIIIIIIIIIIII III III III III III III III II III II IIII IIIIIIIIIIIII III III III III III III III III II IIII IIIIIIIIIIIII III III III III III III III III IIII IIIIIIIIIIIII III III III III III III III III II IIII IIIIIIIIIIIII III III III III III III IIIII III TIMING REQUIREMENTS (CL = 50 pF, Input tr = tf = 6.0 ns) Guaranteed Limit Symbol S b l Parameter P Fig. Fi VCC Volts - 55 to 25_C Min Max 85_C Min Max 125_C Min Max Unit U i tsu Minimum Setup Time, Input D to Latch Enable 4 2.0 3.0 4.5 6.0 50 40 10 9.0 65 50 13 11 75 60 15 13 ns th Minimum Hold Time, Latch Enable to Input D 4 2.0 3.0 4.5 6.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 ns tw Minimum Pulse Width, Latch Enable 2 2.0 3.0 4.5 6.0 75 60 15 13 95 80 19 16 110 90 22 19 ns tr, tf Maximum Input Rise and Fall Times 1 2.0 3.0 4.5 6.0 MOTOROLA 4 1000 800 500 400 1000 800 500 400 1000 800 500 400 ns High-Speed CMOS Logic Data DL129 -- Rev 6 MC54/74HC573A SWITCHING WAVEFORMS VCC tr LATCH ENABLE tf VCC 90% 50% 10% INPUT D 50% GND tw GND tPLH tPHL 90% 50% 10% Q tPLH tTLH tTHL 50% Q Figure 1. OUTPUT ENABLE tPHL Figure 2. 3.0 V VALID 50% GND Q tPZH 10% tPHZ 90% Q GND HIGH IMPEDANCE 50% 1.3 V tSU VOL GND Figure 4. EXPANDED LOGIC DIAGRAM TEST POINT D0 OUTPUT DEVICE UNDER TEST D1 CL* D2 * Includes all probe and jig capacitance D3 2 3 4 5 Figure 5. Test Circuit D4 D5 TEST POINT OUTPUT 1 k CL* CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH. D6 D7 6 7 8 9 LATCH ENABLE * Includes all probe and jig capacitance OUTPUT ENABLE Figure 6. Test Circuit High-Speed CMOS Logic Data DL129 -- Rev 6 VCC HIGH IMPEDANCE Figure 3. DEVICE UNDER TEST th 50% LATCH ENABLE VOH VCC 50% INPUT D tPLZ tPZL 5 D Q LE 19 D Q LE 18 D Q LE 17 D Q LE 16 D Q LE 15 D Q LE 14 D Q LE 13 D Q LE 12 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 11 1 MOTOROLA MC54/74HC573A OUTLINE DIMENSIONS 20 11 1 10 J SUFFIX CERAMIC PACKAGE CASE 732-03 ISSUE E NOTES: 1. LEADS WITHIN 0.25 (0.010) DIAMETER, TRUE POSITION AT SEATING PLANE, AT MAXIMUM MATERIAL CONDITION. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSIONS A AND B INCLUDE MENISCUS. B A L C F DIM A B C D F G H J K L M N N H G D J K M MILLIMETERS MIN MAX 23.88 25.15 6.60 7.49 3.81 5.08 0.38 0.56 1.40 1.65 2.54 BSC 0.51 1.27 0.20 0.30 3.18 4.06 7.62 BSC 0_ 15 _ 0.25 1.02 INCHES MIN MAX 0.940 0.990 0.260 0.295 0.150 0.200 0.015 0.022 0.055 0.065 0.100 BSC 0.020 0.050 0.008 0.012 0.125 0.160 0.300 BSC 0_ 15_ 0.010 0.040 SEATING PLANE N SUFFIX PLASTIC PACKAGE CASE 738-03 ISSUE E -A- 20 11 1 10 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. B L C -T- K SEATING PLANE M N E G F J D M T A 11 -B- 10X P 0.010 (0.25) 1 M B M 10 20X D 0.010 (0.25) M T A B S J S F R X 45 _ C -T- 18X G K SEATING PLANE M T B M M DW SUFFIX PLASTIC SOIC PACKAGE CASE 751D-04 ISSUE E -A- 20 20 PL 0.25 (0.010) 20 PL 0.25 (0.010) MOTOROLA DIM A B C D E F G J K L M N INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.150 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 12.65 12.95 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0_ 7_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.499 0.510 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0_ 7_ 0.395 0.415 0.010 0.029 M 6 High-Speed CMOS Logic Data DL129 -- Rev 6 MC54/74HC573A OUTLINE DIMENSIONS DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948E-02 ISSUE A 20X 0.15 (0.006) T U K REF 0.10 (0.004) S M T U S V S K K1 2X L/2 20 IIII IIII IIII 11 J J1 B L -U- PIN 1 IDENT SECTION N-N 1 10 0.25 (0.010) N 0.15 (0.006) T U S NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. M A -V- N F DETAIL E -W- C G D H DETAIL E 0.100 (0.004) -T- SEATING DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ PLANE Motorola reserves the right to make changes without further notice to any products herein. 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How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1-800-441-2447 or 602-303-5454 JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-81-3521-8315 MFAX: RMFAX0@email.sps.mot.com - TOUCHTONE 602-244-6609 INTERNET: http://Design-NET.com ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 High-Speed CMOS Logic Data DL129 -- Rev 6 7 *MC74HC573A/D* MC74HC573A/D MOTOROLA