DATASHEET
4-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR 9FGV0431
IDT®
4-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR 1
9FGV0431 JUNE 22, 2017
Description
The 9FGV0431 is a 4-output very low-power clock
generator for PCIe Gen 1, 2, 3 and 4 applications. The
device has 4 output enables for clock management and
supports 2 different spread spectrum levels in addition to
spread off.
Recommended Application
PCIe Gen1-4 clock generation for Riser Cards, Storage,
Networking, JBOD, Communications, Access Points
Output Features
•4 – 0.7V low-power HCSL-compatible (LP-HCSL) DIF
pairs
•1 – 1.8V LVCMOS REF output w/Wake-On-Lan
Key Specifications
•DIF cycle-to-cycle jitter <50ps
•DIF output-to-output skew <50ps
•DIF phase jitter is PCIe Gen1-2-3-4 compliant
•REF phase jitter is < 1.5ps RMS
Features/Benefits
•1.8V operation; reduced power consumption
•OE# pins; support DIF power management
•LP-HCSL differential clock outputs; reduced power and
board space
•Programmable Slew rate for each output; allows tuning
for various line lengths
•Programmable output amplitude; allows tuning for
various application environments
•DIF outputs blocked until PLL is locked; clean system
start-up
•Selectable 0%, -0.25% or -0.5% spread on DIF outputs;
reduces EMI
•External 25MHz crystal; supports tight ppm with 0 ppm
synthesis error
•Configuration can be accomplished with strapping pins;
SMBus interface not required for device control
•3.3V tolerant SMBus interface works with legacy
controllers
•Space saving 32-pin 5x5 mm MLF; minimal board space
•Selectable SMBus addresses; multiple devices can
easily share an SMBus segment
Block Diagram
X1_25
X2
DIF(3:0)
CONTROL
LOGIC
SS_EN_tri
CKPWRGD_PD#
SDATA_3.3
SS Capable PLL
4
OSC
REF1.8
OE(3:0)#
SCLK_3.3
SADR
9FGV0431
4-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR
IDT®
4-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR 2
9FGV0431 JUNE 22, 2017
Pin Configuration
SMBus Address Selection Table
Power Management Table
Power Connections
vSS_EN_tri
^CKPWRGD_PD#
GND
vOE3#
DIF3#
DIF3
GND
VDDO1.8
32 31 30 29 28 27 26 25
GNDXTAL 1 24 vOE2#
XIN/CLKIN_25 2 23 DIF2#
X2 3 22 DIF2
VDDXTAL1.8 4 21 VDDA1.8
VDDREF1.8 5 20 GNDA
vSADR/REF1.8 6 19 DIF1#
GNDREF 718 DIF1
GNDDIG
817vOE1#
9 10111213141516
VDDDIG1.8
SCLK_3.3
SDATA_3.3
vOE0#
DIF0
DIF0#
GND
VDDO1.8
32-pin MLF, 5x5 mm, 0.5mm pitch
v prefix indicates internal 120KOhm pull down resistor
9FGV0431
^ prefix indicates internal 120KOhm pull up resisto
r
SADR Address
0 1101000
1 1101010
+ Read/Write Bit
x
x
State of SADR on first application
of CKPWRGD_PD#
OEx# True O/ P Com p. O/P
0XXLowLow
Hi-Z1
1 1 0 Running Running Running
1 0 1 Low Low Low
REF
CKPWRGD_PD# SMBus
OE bit DIFx
1. REF is Hi-Z until the 1st assertion of CKPWRGD_PD# high. After this, when
CKPWRG_PD# is low, REF is Low.
Pin Number
VDD GND
41
57
98, 30
16, 25 15, 26
21 20 PLL Analog
REF Output
Description
XTAL Analo
g
Di
g
ital Power
DIF outputs
9FGV0431
4-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR
IDT®
4-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR 3
9FGV0431 JUNE 22, 2017
Pin Descriptions
9FGV0431
4-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR
IDT®
4-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR 4
9FGV0431 JUNE 22, 2017
Test Loads
Alternate Terminations
Al te rnate Differential Output Te rm inations
Rs Zo Units
33 100
27 85 Ohms
Rs
Rs
Low-Power Differential Output Test Load
2pF 2pF
5 inches
Zo=100ohms
REF Output
33
REF Output Test Load
5pF
Zo = 50 ohms
LVDS CLK
Input
Zo
R8b
R7b
R8a
R7a
3.3 Volts
Cc
Cc
Rs
Rs
Driving LVDS
Driving LVDS inputs with the 9FGV0431
Receiver has
termination
Receiver does not
have termination
R7a, R7b 10K ohm 140 ohm
R8a, R8b 5.6K ohm 75 ohm
Cc 0.1 uF 0.1 uF
Vcm 1.2 volts 1.2 volts
Component
Value
Note
9FGV0431
4-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR
IDT®
4-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR 5
9FGV0431 JUNE 22, 2017
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9FGV0431. These ratings, which are standard
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over
the recommended operating temperature range.
Electrical Characteristics–Current Consumption
Electrical Characteristics–Output Duty Cycle, Jitter, and Skew Characteristics
PARAMETER SYMBOL CONDITIONS
MIN TYP MAX
UNITS NOTES
1.8V Supply Voltage VDDx1.8 Applies to All VDD pins -0.5 2.5 V 1,2
Input Voltage V
IN
-0.5 V
DD
+0.3V V 1, 3
Input High Voltage, SMBus V
IHSMB
SMBus clock and data pins 3.6V V 1
Storage Temperature Ts -65 150 °C
1
Junction Temperature Tj 125 °C 1
Input ESD protection ESD prot Human Body Model 2000 V 1
1Guaranteed by design and characterization, not 100% tested in production.
2 Operation under these conditions is neither implied nor guaranteed.
3
Not to exceed 2.5V.
TA = TCOM or TIND; Supply Voltage per VDD of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
I
DDAOP
VDDA, All outputs active @100MHz 68 mA 1
I
DDOP
VDD, All outputs active @100MHz 26 30 mA 1
Suspend Supply Current I
DDSUSP
VDDxxx, PD# = 0, Wake-On-LAN enabled 68 mA 1
Powerdown Current IDDPD PD#=0 0.6 1 mA 1, 2
1Guaranteed by design and characterization, not 100% tested in production.
2Assuming REF is not running in power down state
Operating Supply Current
TA = TCOM or TIND; Supply Voltage per VDD of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Duty Cycle t
DC
Measured differentially, PLL Mode 45 50.1 55 % 1
Skew, Output to Output t
sk3
V
T
= 50% 37 50 ps 1
Jitter, Cycle to cycle tjcyc-cyc PLL mode 12 50 ps 1,2
1Guaranteed by design and characterization, not 100% tested in production.
2 Measured from differential waveform
9FGV0431
4-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR
IDT®
4-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR 6
9FGV0431 JUNE 22, 2017
Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating
Conditions
TA = TCOM or TIND; Supply Voltage per VDD of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
1.8V Supply Voltage VDDx1.8 Supply voltage for core, analog and single-ended
LVCMOS outputs
1.7 1.8 1.9 V 1
T
COM
Commercial range 0 25 70 °C 1
T
IND
Industrial range -40 25 85 °C 1
Input High Voltage V
IH
Single-ended inputs, except SMBus 0.75 V
DD
V
DD
+ 0.3 V 1
Input Mid Voltage V
IM
Single-ended tri-level inputs ('_tri' suffix, if present) 0.4 V
DD
0.6 V
DD
V1
Input Low Voltage V
IL
Single-ended inputs, except SMBus -0.3 0.25 V
DD
V1
Schmitt Trigger Positive
Going Threshold Voltage VT+ Single-ended inputs, where indicated 0.4 VDD 0.7 VDD V1
Schmitt Trigger Negative
Goin
g
Threshold Volta
g
e
VT- Single-ended inputs, where indicated 0.1 VDD 0.4 VDD V1
Hysteresis Voltage V
H
V
T+
- V
T-
0.1 V
DD
0.4 V
DD
V1
Output High Voltage V
IH
Single-ended outputs, except SMBus. I
OH
= -2mA V
DD
-0.45 V 1
Output Low Voltage V
IL
Single-ended outputs, except SMBus. I
OL
= -2mA 0.45 V 1
I
IN
Single-ended inputs, V
IN
= GND, V
IN
= VDD -5 5 uA 1
IINP
Single-ended inputs
VIN
= 0 V; Inputs with internal pull-up resistors
V
IN
= VDD; Inputs with internal pull-down resistors
-200 200 uA 1
Input Frequency F
in
XTAL, or X1 input 23 25 27 MHz 1
Pin Inductance L
p
in
7nH1
C
IN
Logic Inputs, except DIF_IN 1.5 5 pF 1
C
OUT
Output pin capacitance 6 pF 1
Clk Stabilization TSTAB
From VDD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
0.6 1.8 ms 1,2
SS Modulation Frequency fMOD
Allowable Frequency
(Triangular Modulation) 31 31.6 32 kHz 1
OE# Latency tLATOE#
DIF start after OE# assertion
DIF stop after OE# deassertion 123clocks1,3
Tdrive_PD# tDRVPD
DIF output enable after
PD# de-assertion
300 us 1,3
Tfall t
F
Fall time of single-ended control inputs 5 ns 1,2
Trise t
R
Rise time of single-ended control inputs 5 ns 1,2
SMBus Input Low Voltage V
ILSMB
V
DDSMB
= 3.3V, see note 4 for V
DDSMB
< 3.3V 0.8 V 1,4
SMBus Input High Voltage V
IHSMB
V
DDSMB
= 3.3V, see note 5 for V
DDSMB
< 3.3V 2.1 3.6 V 1,5
SMBus Output Low Voltage V
OLSMB
@ I
PULLUP
0.4 V 1
SMBus Sink Current I
PULLUP
@ V
OL
4mA1
Nominal Bus Voltage V
DDSMB
1.7 3.6 V 1
SCLK/SDATA Rise Time t
RSMB
(Max VIL - 0.15) to (Min VIH + 0.15) 1000 ns 1
SCLK/SDATA Fall Time t
FSMB
(Min VIH + 0.15) to (Max VIL - 0.15) 300 ns 1
SMBus Operating
Frequency fMAXSMB Maximum SMBus operating frequency 400 kHz 1
1 Guaranteed by design and characterization, not 100% tested in production.
2 Control input must be monotonic from 20% to 80% of input swing.
5 For VDDSMB < 3.3V, VIHSMB >= 0.65VDDSMB
Capacitance
3
Time from deassertion until outputs are >200 mV
4 For VDDSMB < 3.3V, VILSMB <= 0.35VDDSMB
Input Current
Ambient Operating
Temperature
9FGV0431
4-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR
IDT®
4-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR 7
9FGV0431 JUNE 22, 2017
Electrical Characteristics–DIF 0.7V Low Power HCSL Output
Electrical Characteristics–Filtered Phase Jitter Parameters - PCIe Common
Clocked (CC) Architectures
TA = TCOM or TIND; Supply Voltage per VDD of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Scope avera
g
in
g
on 3.0V/ns settin
g
2.6 3.5 4.6
V/ns
1, 2, 3
Scope averaging on 2.0V/ns setting 1.5 2.5 3.5 V/ns 1, 2, 3
Slew rate matching
Δ
Trf Slew rate matching, Scope averaging on 820 %1,2,4
Voltage High VHI GH 660 797 850 1,8
Voltage Low VLOW -150 15 150 1
Max Voltage Vmax 833 1150 1
Min Voltage Vmin -300 -41 1
Vswin
g
Vswin
g
Scope avera
g
in
g
off 300
1564
mV 1,2
Crossing Voltage (abs) Vcross_abs Scope averaging off 300 427 550 mV 1,5
Crossing Voltage (var) Δ-Vcross Scope averaging off 15 140 mV 1,6
2 Measured from differential waveform
7 At default SMBus settings.
6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross
absolute) allowed. The intent is to limit Vcross induced modulation by setting Δ-Vcross to be smaller than Vcross absolute.
1Guaranteed by design and characterization, not 100% tested in production. CL = 2pF with RS = 33Ω for Zo = 50Ω (100Ω differential
trace impedance).
3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
Statistical measurement on single-ended signal
using oscilloscope math function. (Scope
averaging on)
mV
Measurement on single ended signal using
absolute value. (Scope averaging off) mV
4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on
the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations.
5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising
edge (i.e. Clock rising and Clock# falling).
Slew rate Trf
2
9FGV0431
4-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR
IDT®
4-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR 8
9FGV0431 JUNE 22, 2017
Electrical Characteristics–REF
Clock Periods–Differential Outputs with Spread Spectrum Disabled
Clock Periods–Differential Outputs with -0.5% Spread Spectrum Enabled
TA = TCOM or TIND
; Supply Voltage per VDD of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes
Long Accuracy ppm see Tperiod min-max values ppm 1,2
Clock period T
p
eriod
25 MHz output nominal 40 ns 1,2
Rise/Fall Slew Rate t
rf1
V
OH
= VDD-0.45V, V
OL
= 0.45V 0.5 1.3 2.5 V/ns 1,3
Duty Cycle d
tcd
V
T
= VDD/2 V 455355%1,4
Duty Cycle Distortion d
t1
V
T
= VDD/2 V 0 2 3 % 1,5
Jitter, cycle to cycle t
j
c
y
c-c
y
c
V
T
= VDD/2 V 20 250 ps 1,4
Noise floor t
j
dBc1k
1kHz offset -125 -119 dBc 1,4
Noise floor t
j
dBc10k
10kHz offset to Nyquist -140 -120 dBc 1,4
Jitter, phase tjphREF 12kHz to 5MHz 0.81 1.5 ps
(rms) 1,4
1Guaranteed by design and characterization, not 100% tested in production.
3 Typical value occurs when REF slew rate is set to default value
4 When driven by a crystal.
5 When driven by an external oscillator via the X1 pin. X2 should be floating in this case.
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is trimmed to 25.00 MHz
0
1 Clock 1us 0.1s 0.1s 0.1s 1us 1 Clock
-c2c jitter
AbsPer
Min
-SSC
Short-Term
Average
Min
- ppm
Long-Term
Average
Min
0 ppm
Period
Nominal
+ ppm
Long-Term
Average
Ma
x
+SSC
Short-Term
Average
Ma
x
+c2c jitter
AbsPer
Max
DIF 100.00 9.94900 9.99900 10.00000 10.00100 10.05100 ns 1,2
Measurement Window
UnitsSSC OFF
Center
Freq.
MHz
Notes
1 Clock 1us 0.1s 0.1s 0.1s 1us 1 Clock
-c2c jitter
AbsPer
Min
-SSC
Short-Term
Average
Min
- ppm
Long-Term
Average
Min
0 ppm
Period
Nominal
+ ppm
Long-Term
Average
Ma
x
+SSC
Short-Term
Average
Ma
x
+c2c jitter
AbsPer
Max
DIF 99.75 9.94906 9.99906 10.02406 10.02506 10.02607 10.05107 10.10107 ns 1,2
1Guaranteed by design and characterization, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is trimmed to 25.00 MHz
Measurement Window
UnitsSSC ON
Center
Freq.
MHz
Notes
9FGV0431
4-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR
IDT®
4-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR 9
9FGV0431 JUNE 22, 2017
General SMBus Serial Interface Information
How to Write
•Controller (host) sends a start bit
•Controller (host) sends the write address
•IDT clock will acknowledge
•Controller (host) sends the beginning byte location = N
•IDT clock will acknowledge
•Controller (host) sends the byte count = X
•IDT clock will acknowledge
•Controller (host) starts sending Byte N through Byte
N+X-1
•IDT clock will acknowledge each byte one at a time
•Controller (host) sends a Stop bit
Note: Read/Write address is latched on SADR pin.
How to Read
•Controller (host) will send a start bit
•Controller (host) sends the write address
•IDT clock will acknowledge
•Controller (host) sends the beginning byte location = N
•IDT clock will acknowledge
•Controller (host) will send a separate start bit
•Controller (host) sends the read address
•IDT clock will acknowledge
•IDT clock will send the data byte count = X
•IDT clock sends Byte N+X-1
•IDT clock sends Byte 0 through Byte X (if X(H) was
written to Byte 8)
•Controller (host) will need to acknowledge each byte
•Controller (host) will send a not acknowledge bit
•Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host) IDT (Slave/Receiver)
TstarT bit
Slave Address
WR WRite
ACK
Beginning Byte = N
ACK
Data Byte Count = X
ACK
Beginning Byte N
X Byte
ACK
O
OO
OO
O
Byte N + X - 1
ACK
PstoP bit
Index Block Read Operation
Controller (Host) IDT (Slave/Receiver)
TstarT bit
Slave Address
WR WRite
ACK
Beginning Byte = N
ACK
RT Repeat starT
Slave Address
RD ReaD
ACK
Data Byte Count=X
ACK
X Byte
Beginning Byte N
ACK
O
OO
OO
O
Byte N + X - 1
N Not acknowledge
PstoP bit
9FGV0431
4-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR
IDT®
4-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR 10
9FGV0431 JUNE 22, 2017
SM Bus Tabl e: Output Enable Re gi ste r
Byte 0 Na m e Control Function Type 0 1 De fa ul t
Bit 7 1
Bit 6 1
Bit 5 1
Bit 4 1
Bit 3 DIF OE3 Output Enable RW Low/Low Enabled 1
Bit 2 DIF OE3 Output Enable RW Low/Low Enabled 1
Bit 1 DIF OE2 Output Enable RW Low/Low Enabled 1
Bit 0 DIF OE1 Output Enable RW Low/Low Enabled 1
SM Bus Tabl e: SS Re adba ck a nd Vhi gh Control Regi ste r
Byte 1 Na m e Control Function Type 0 1 De fa ul t
Bit 7 SSENRB1 SS Enable Readback Bit1 RLatch
Bit 6 SSENRB1 SS Enable Readback Bit0 RLatch
Bit 5 SSEN_SWCNTRL Enable SW control of SS RW SS control locked Values in B1[4:3]
control SS amount. 0
Bit 4 SSENSW1 SS Enable Software Ctl Bit1 RW10
Bit 3 SSENSW0 SS Enable Software Ctl Bit0 RW10
Bit 2 1
Bit 1 AMPLITUDE 1 RW 00 = 0.6V 01 = 0.7V 1
Bit 0 AMPLITUDE 0 RW 10= 0.8V 11 = 0.9V 0
1. B1[5] must be set to a 1 for these bits to have any effect on the part.
SM Bus Ta bl e: DI F S l ew Ra te Control Re gi ste r
Byte 2 Na m e Control Function Type 0 1 De fa ul t
Bit 7 1
Bit 6 1
Bit 5 1
Bit 4 1
Bit 3 SLEWRATESEL DIF3 Adjust Slew Rate of DIF3 RW 2.0V/ns 3.0V/ns 1
Bit 2 SLEWRATESEL DIF2 Adjust Slew Rate of DIF2 RW 2.0V/ns 3.0V/ns 1
Bit 1 SLEWRATESEL DIF1 Adjust Slew Rate of DIF3 RW 2.0V/ns 3.0V/ns 1
Bit 0 SLEWRATESEL DIF0 Adjust Slew Rate of DIF1 RW 2.0V/ns 3.0V/ns 1
SM Bus Tabl e: REF Control Re gi ster
Byte 3 Na m e Control Function Type 0 1 De fa ul t
Bit 7 RW 00 = 0.9V/ns 01 =1.3V/ns 0
Bit 6 RW 10 = 1.6V/ns 11 = 1.8V/ns 1
Bit 5 REF Power Down Function Wake-on-Lan Enable for REF RW
REF does not run in
Power Down
REF runs in Power
Down 0
Bit 4 REF OE REF Output Enable RW Low Enabled 1
Bit 3 1
Bit 2 1
Bit 1 1
Bit 0 1
Byte 4 i s re serve d and re ads ba ck 'hFF'.
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
00' = SS Off, '01' = -0.25% SS,
'10' = Reserved, '11'= -0.5% SS
00' for SS_EN_tri = 0, '01' for SS_EN_tri
= 'M', '11 for SS_EN_tri = '1'
Reserved
Reserved
Reserved
Reserved
REF
Reserved
Controls Output Amplitude
Slew Rate Control
Reserved
Reserved
9FGV0431
4-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR
IDT®
4-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR 11
9FGV0431 JUNE 22, 2017
Recommended Crystal Characteristics (3225 package)
SM Bus Ta bl e: Revisi on a nd V endor ID Registe r
Byte 5 Na m e Control Function Type 0 1 De fa ul t
Bit 7 RID3 R0
Bit 6 RID2 R0
Bit 5 RID1 R0
Bit 4 RID0 R0
Bit 3 VID3 R0
Bit 2 VID2 R0
Bit 1 VID1 R0
Bit 0 VID0 R1
SM Bus Tabl e: Device Type / De vice I D
Byte 6 Na m e Control Function Type 0 1 De fa ul t
Bit 7 Device Type1 R0
Bit 6 Device Type0 R0
Bit 5 Device ID5 R0
Bit 4 Device ID4 R0
Bit 3 Device ID3 R0
Bit 2 Device ID2 R1
Bit 1 Device ID1 R0
Bit 0 Device ID0 R0
SM Bus Tabl e: Byte Count Re gi ste r
Byte 7 Na m e Control Function Type 0 1 De fa ul t
Bit 7 0
Bit 6 0
Bit 5 0
Bit 4 BC4 RW 0
Bit 3 BC3 RW 1
Bit 2 BC2 RW 0
Bit 1 BC1 RW 0
Bit 0 BC0 RW 0
A rev = 0000
VENDOR ID
Revision ID
Reserved
0001 = IDT
000100 binary or 04 hex
00 = FGV, 01 = DBV,
10 = DMV, 11= Reserved
Device Type
Byte Count Programming
Reserved
Device ID
Reserved
Writing to this register will configure how
many bytes will be read back, default is
= 8 bytes.
PARAMETER VALUE UNITS NOTES
Frequency 25 MHz 1
Resonance Mode Fundamental -1
Frequency Tolerance @ 25°C ±20 PPM Max 1
Frequency Stability, ref @ 25°C Over
Operating Temperature Range
±20 PPM Max 1
Temperature Range (commercial) 0~70 °C1
Temperature Range (industrial) -40~85 °
C
2
Equivalent Series Resistance (ESR) 50 Ω Max 1
Shunt Capacitance (C
O
)7pF Max1
Load Capacitance (C
L
)8pF Max1
Drive Level 0.3 mW Max 1
Aging per year ±5 PPM Max 1
Notes:
1. FOX 603-25-150.
2. For I-temp, FOX 603-25-261.
9FGV0431
4-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR
IDT®
4-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR 12
9FGV0431 JUNE 22, 2017
Thermal Characteristics
Marking Diagrams
Notes:
1. Line 2 is the truncated part number.
2. ‘L’ denotes RoHS compliant package.
3. ‘I’ denotes industrial temperature grade.
4. ‘YYWW’ is the last two digits of the year and week that the part was assembled.
5. ‘COO’ denotes country of origin.
6. ‘LOT’ is the lot number.
PARAMETER SYMBOL CONDITIONS PKG TYP. UNITS NOTES
θ
JC
Junction to Case 42 °C/W 1
θ
Jb
Junction to Base 2.4 °C/W 1
θ
JA0
Junction to Air, still air 39 °C/W 1
θ
JA1
Junction to Air, 1 m/s air flow 33 °C/W 1
θ
JA3
Junction to Air, 3 m/s air flow 28 °C/W 1
θJA5 Junction to Air, 5 m/s air flow 27 °C/W 1
1ePad soldered to board
Thermal Resistance NLG32
ICS
V0431AIL
YYWW
COO
LOT
ICS
GV0431AL
YYWW
COO
LOT
9FGV0431
4-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR
IDT®
4-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR 13
9FGV0431 JUNE 22, 2017
Package Outline and Dimensions (NLG32)
www.IDT.com
D
IT
9FGV0431
4-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR
IDT®
4-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR 14
9FGV0431 JUNE 22, 2017
Package Outline and Dimensions (NLG32), cont.
www.IDT.com
DIT
9FGV0431
4-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR
IDT®
4-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR 15
9FGV0431 JUNE 22, 2017
Ordering Information
“LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.
“A” is the device revision designator (will not correlate with the datasheet revision).
Revision History
Part / Order Number Shi ppi ng P acka gi ng P acka ge Tem pe rature
9FGV0431AKLF Trays 32-pin MLF 0 to +70° C
9FGV0431AKLFT Tape and Reel 32-pin MLF 0 to +70° C
9FGV0431AKILF Trays 32-pin MLF -40 to +85° C
9FGV0431AKILFT Tape and Reel 32-pin MLF -40 to +85° C
Rev. Issue Date Initiator Description Page #
E 10/18/2016 RDW
Removed IDT crystal part numbe
r
F 6/22/2017 RG
Updated front page Gendes to reflect the PCIe Gen4 updates.
Updated Electrical Characteristics - Filtered Phase Jitter Parameters -
PCIe Common Clocked (CC) Architectures and added PCIe Gen4 Data
1,7
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the right to modi fy the products
and/or specifications described herein at any time, without notice, at IDT’s sole discretion. Performance specifications and operating parameters of the
described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The
information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the
suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of
others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where
the failure or malfunction of an IDT produc t can be reas onabl y expec ted to significa ntly affe ct th e health or safety of users . Any one using an IDT produc t
in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other
countries. Other trademarks used herein are the property of IDT or their respective third party owners. For datasheet type definitions and a glossary of
common terms, visit www.idt.com/go/glossary. Integrated Device Technology, Inc.. All rights reserved.
Corporate Headquarters
Integrated Device Technology, Inc.
www.idt.com
For Sales
800-345-7015
408-284-8200
www.idt.com/go/sales
For Tech Support
www.idt.com/go/support
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
9FGV0431
4-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR SYNTHESIZERS