Description
These units are single, dual
and quad channel, hermetically
sealed optocouplers. The
products are capable of
operation and storage over the
full military temperature range
and can be purchased as
either standard product or
with full MIL-PRF-38534 Class
Level H or K testing or from
the appropriate DSCC Drawing.
All devices are manufactured
and tested on a MIL-PRF-
38534 certified line and are
included in the DSCC Qualified
Manufacturers List QML-38534
for Hybrid Microcircuits.
Hermetically Sealed, Transistor
Output Optocouplers for Analog and
Digital Applications
Technical Data
Agilent 4N55*, 5962-87679, HCPL-553X, HCPL-653X,
HCPL-257K, HCPL-655X, 5962-90854, HCPL-550X
*See matrix for available extensions.
Features
••
••
•Dual Marked with Device Part
Number and DSCC Drawing
Number
••
••
•Manufactured and Tested on a
MIL-PRF-38534 Certified Line
••
••
•QML-38534, Class H and K
••
••
•Five Hermetically Sealed Package
Configurations
••
••
•Performance Guaranteed, Over
-55°C to +125°C
••
••
•High Speed: Typically 400 kBit/s
••
••
•9 MHz Bandwidth
••
••
•Open Collector Output
••
••
•2-18 Volt VCC Range
••
••
•1500 Vdc Withstand Test Voltage
••
••
•High Radiation Immunity
••
••
•6N135, 6N136, HCPL-2530/2531,
Function Compatibility
••
••
•Reliability Data
The connection of a 0.1 µF bypass capacitor between VCC and GND is recommended.
Applications
••
••
•Military and Space
••
••
•High Reliability Systems
••
••
•Vehicle Command, Control, Life
Critical Systems
••
••
•Line Receivers
••
••
•Switching Power Supply
••
••
•Voltage Level Shifting
••
••
•Analog Signal Ground Isolation
(see Figures 7, 8, and 13)
••
••
•Isolated Input Line Receiver
••
••
•Isolated Output Line Driver
••
••
•Logic Ground Isolation
••
••
•Harsh Industrial Environments
••
••
•Isolation for Test Equipment
Systems
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
2
Truth Table
(Positive Logic)
Functional Diagram
Multiple Channel Devices
Available
Input Output
On (H) L
Off (L) H
V
CC
GND
V
O
V
B
Each channel contains a
GaAsP light emitting diode
which is optically coupled to
an integrated photon detector.
Separate connections for the
photodiodes and output
transistor collectors improve
the speed up to a hundred
times that of a conventional
phototransistor optocoupler by
reducing the base-collector
capacitance.
These devices are suitable for
wide bandwidth analog
applications, as well as for
interfacing TTL to LSTTL or
CMOS. Current Transfer Ratio
(CTR) is 9% minimum at IF =
16 mA. The 18 V VCC
capability will enable the
designer to interface any TTL
family to CMOS. The
availability of the base lead
allows optimized gain/
bandwidth adjustment in
analog applications. The
shallow depth of the IC
photodiode provides better
radiation immunity than
conventional phototransistor
couplers.
These products are also
available with the transistor
base node not connected to
improve common mode noise
immunity and ESD
susceptibility. In addition,
higher CTR minimums are
available by special request.
Package styles for these parts
are 8 and 16 pin DIP through
hole (case outlines P and E
respectively), 16 pin DIP flat
pack (case outline F), and
leadless ceramic chip carrier
(case outline 2). Devices may
be purchased with a variety of
lead bend and plating options,
see Selection Guide Table for
details. Standard Microcircuit
Drawing (SMD) parts are
available for each package and
lead style.
Because the same functional
die (emitters and detectors)
are used for each channel of
each device listed in this data
sheet, absolute maximum
ratings, recommended
operating conditions, electrical
specifications, and performance
characteristics shown in the
figures are identical for all
parts. Occasional exceptions
exist due to package variations
and limitations and are as
noted. Additionally, the same
package assembly processes
and materials are used in all
devices. These similarities give
justification for the use of data
obtained from one part to
represent other part’s
performance for die related
reliability and certain limited
radiation test results.
3
Selection Guide–Package Styles and Lead Configuration Options
Package
16 Pin DIP 8 Pin DIP 8 Pin DIP 16 Pin Flat
Pack
20 Pad LCCC
Lead Style Through Hole Through Hole Through Hole Unformed Leads Surface Mount
Channels 2 1 2 4 2
Common Channel Wiring None None VCC GND VCC GND None
Agilent Part No. and Options
Commercial 4N55(1) HCPL-5500 HCPL-5530 HCPL-6550 HCPL-6530
MIL-PRF-38534 Class H 4N55/883B HCPL-5501 HCPL-5531 HCPL-6551 HCPL-6531
MIL-PRF-38534 Class K HCPL-257K HCPL-550K HCPL-553K HCPL-655K HCPL-653K
Standard Lead Finish Gold Plate Gold Plate Gold Plate Gold Plate Solder Pads
Solder Dipped* Option 200 Option 200 Option 200
Butt Joint/Gold Plate Option 100 Option 100 Option 100
Gull Wing/Soldered* Option 300 Option 300 Option 300
Class H SMD Part #
Prescript for all below 5962- 5962- 5962- 5962- 5962-
Either Gold or Soldered 8767901EX 9085401HPX 8767902PX 8767904FX 87679032X
Gold Plate 8767901EC 9085401HPC 8767902PC 8767904FC
Solder Dipped* 8767901EA 9085401HPA 8767902PA 87679032A
Butt Joint/Gold Plate 8767901UC 9085401HYC 8767902YC
Butt Joint/Soldered* 8767901UA 9085401HYA 8767902YA
Gull Wing/Soldered* 8767901TA 9085401HXA 8767902XA
Class K SMD Part #
Prescript for all below 5962- 5962- 5962- 5962- 5962-
Either Gold or Soldered 8767905KEX 9085401KPX 8767906KPX 8767908KFX 8767907K2X
Gold Plate 8767905KEC 9085401KPC 8767906KPC 8767908KFC
Solder Dipped* 8767905KEA 9085401KPA 8767906KPA 8767907K2A
Butt Joint/Gold Plate 8767905KUC 9085401KYC 8767906KYC
Butt Joint/Soldered* 8767905KUA 9085401KYA 8767906KYA
Gull Wing/Soldered* 8767905KTA 9085401KXA 8767906KXA
1. JEDEC registered part.
* Solder contains lead
4
Outline Drawings
16 Pin DIP Through Hole, 2 Channels
8 Pin Ceramic DIP Single Channel Schematic
Note: 8 pin DIP and flat pack devices have common VCC and ground. 16 pin DIP and LCCC (leadless ceramic chip carrier) packages have isolated
channels with separate VCC and ground connections.
Functional Diagrams
ANODE
3
CATHODE
6
5
V
O
GND
I
O
I
F
2
+
-
V
F
8V
CC
7V
B
I
B
I
CC
16 Pin DIP 8 Pin DIP 8 Pin DIP 16 Pin Flat Pack 20 Pad LCCC
Through Hole Through Hole Through Hole Unformed Leads Surface Mount
2 Channels 1 Channel 2 Channels 4 Channels 2 Channels
1
3
2
4
8
6
7
5
V
CC
GND
V
OUT
V
B
1
3
2
4
8
6
7
5
V
CC
GND
V
O2
V
O1
5
7
6
8
12
10
11
9
GND
V
O4
V
O3
1
3
2
4
16
14
15
13
V
CC
V
O2
V
O1
GND
1
V
B2
19
20
2
3
V
O1
87
V
CC2
V
CC1
10
GND
2
15
13
12
14
V
O2
V
B1
9
5
7
6
8
12
10
11
9
GND
V
CC2
V
B2
1
3
2
4
16
14
15
13
V
CC1
GND
V
O1
V
O2
V
B1
0.20 (0.008)
0.33 (0.013)
4.45 (0.175)
MAX.
20.06 (0.790)
20.83 (0.820)
0.51 (0.020)
MAX.
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MIN.
0.89 (0.035)
1.65 (0.065)
8.13 (0.320)
MAX.
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
3.81 (0.150)
MIN.
Note, base is pin 7.
5
Leaded Device Marking Leadless Device Marking
Outline Drawings
16 Pin Flat Pack, 4 Channels
COMPLIANCE INDICATOR,*
DATE CODE, SUFFIX (IF NEEDED)
A QYYWWZ
XXXXXX
XXXXXXX
XXX XXX
50434
COUNTRY OF MFR.
Agilent CAGE CODE*
Agilent DESIGNATOR
DSCC SMD*
PIN ONE/
ESD IDENT
Agilent P/N
DSCC SMD*
* QUALIFIED PARTS ONLY
COMPLIANCE INDICATOR,*
DATE CODE, SUFFIX (IF NEEDED)
A QYYWWZ
XXXXXX
XXXX
XXXXXX
XXX 50434
DSCC SMD*
Agilent CAGE CODE*
Agilent DESIGNATOR
COUNTRY OF MFR.
Agilent P/N
PIN ONE/
ESD IDENT
DSCC SMD*
* QUALIFIED PARTS ONLY
8.13 (0.320)
MAX.
5.23
(0.206)
MAX.
2.29 (0.090)
MAX.
7.24 (0.285)
6.99 (0.275)
1.27 (0.050)
REF.
0.46 (0.018)
0.36 (0.014)
11.13 (0.438)
10.72 (0.422)
2.85 (0.112)
MAX.
0.89 (0.035)
0.69 (0.027)
0.31 (0.012)
0.23 (0.009)
0.88 (0.0345)
MIN.
9.02 (0.355)
8.76 (0.345)
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
20 Terminal LCCC Surface Mount, 2 Channels 8 Pin DIP Through Hole, 1 and 2 Channel
8.70 (0.342)
9.10 (0.358)
4.95 (0.195)
5.21 (0.205)
1.78 (0.070)
2.03 (0.080) 1.02 (0.040) (3 PLCS)
4.95 (0.195)
5.21 (0.205)
8.70 (0.342)
9.10 (0.358)
1.78 (0.070)
2.03 (0.080)
0.51 (0.020)
0.64
(0.025)
(20 PLCS)
1.52 (0.060)
2.03 (0.080)
METALIZED
CASTILLATIONS (20 PLCS)
2.16 (0.085)
TERMINAL 1 IDENTIFIER
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
SOLDER THICKNESS 0.127 (0.005) MAX.
1.14 (0.045)
1.40 (0.055)
3.81 (0.150)
MIN.
4.32 (0.170)
MAX.
9.40 (0.370)
9.91 (0.390)
0.51 (0.020)
MAX.
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MIN.
0.76 (0.030)
1.27 (0.050)
8.13 (0.320)
MAX.
7.36 (0.290)
7.87 (0.310)
0.20 (0.008)
0.33 (0.013)
7.16 (0.282)
7.57 (0.298)
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
6
Option Description
100 Surface mountable hermetic optocoupler with leads trimmed for butt joint assembly. This option is
available on commercial and hi-rel product in 8 and 16 pin DIP (see drawings below for details).
200 Lead finish is solder dipped rather than gold plated. This option is available on commercial and hi-rel
product in 8 and 16 pin DIP. DSCC drawing part numbers contain provisions for lead finish. All
leadless chip carrier devices are delivered with solder dipped terminals as a standard feature.
300 Surface mountable hermetic optocoupler with leads cut and bent for gull wing assembly. This option
is available on commercial and hi-rel product in 8 and 16 pin DIP (see drawings below for details).
This option has solder dipped leads.
Hermetic Optocoupler Options
1.14 (0.045)
1.40 (0.055)
4.32 (0.170)
MAX.
0.51 (0.020)
MAX.
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MIN.
7.36 (0.290)
7.87 (0.310)
0.20 (0.008)
0.33 (0.013)
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
1.14 (0.045)
1.40 (0.055)
4.32 (0.170)
MAX.
0.51 (0.020)
MAX.
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MIN.
1.40 (0.055)
1.65 (0.065)
4.57 (0.180)
MAX.
0.51 (0.020)
MAX.
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MIN.
0.51 (0.020)
MIN.
4.57 (0.180)
MAX.
0.51 (0.020)
MAX.
2.29 (0.090)
2.79 (0.110)
1.40 (0.055)
1.65 (0.065)
9.65 (0.380)
9.91 (0.390)
5˚ MAX.
4.57 (0.180)
MAX.
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
0.20 (0.008)
0.33 (0.013)
7
Recommended Operating Conditions
ESD Classification
(MIL-STD-883, Method 3015)
Single Channel 8 Pin, Dual Channel 16 Pin, and LCCC Only
Absolute Maximum Ratings
No derating required up to +125° C.
Parameter Symbol Min. Max. Units
Storage Temperature Range TS-65° +150° C
Operating Ambient Temperature TA-55° +125° C
Junction Temperature TJ+175° C
Case Temperature TC+170° C
Lead Solder Temperature (1.6 mm below seating plane) 260° for 10 s C
Average Input Forward Current IF AVG 20 mA
Peak Forward Input Current (each channel, ≤ 1 ms duration) IFPK 40 mA
Reverse Input Voltage BVRSee Electrical Characteristics
Average Output Current, each channel IO8mA
Peak Output Current, each channel IO16 mA
Supply Voltage VCC -0.5 20 V
Output Voltage VO-0.5 20 V
Input Power Dissipation, each channel 36 mW
Output Power Dissipation, each channel 50 mW
Package Power Dissipation, each channel PD200 mW
Emitter Base Reverse Voltage VEBO 3V
Base Current, each channel IB5mA
4N55, 4N55/883B, HCPL-257K, HCPL-5500/01/0K, and HCPL-6530/31/3K (∆), Class 1
HCPL-5530/31/3K, HCPL-6550/51/5K (Dot), Class 3
Parameter Symbol Min. Max. Units
Input Current, Low Level IFL 250 µA
Input Current, High Level IFH 12 20 mA
Supply Voltage, Output VCC 218V
8
Electrical Characteristics
TA = -55° C to +125° C, unless otherwise specified. See Note 12.
*All typical values are at VCC = 5 V, TA = 25°C.
Parameter Symbol Group A,
Sub-
group
Test Conditions Limits Units Fig. Notes
Min. Typ.* Max.
Current Transfer Ratio CTR 1, 2, 3 VO = 0.4V, IF = 16 mA, VCC = 4.5V 9 20 % 2, 3 1, 2, 10
Logic High Output Current IOH 1, 2, 3 IF = 0,
IF (other channels) = 20 mA
VO = VCC = 18 V
5 100 µA41
Output Leakage Current IOLeak 1, 2, 3 IF = 250 µA,
IF (other channels) = 20 mA,
VO = VCC = 18 V
30 250 µA41
Input-Output Insulation Leakage
Current
II-O 1V
I-O = 1500 Vdc,
RH ≤ 65%,
TA = 25°C, t = 5 s
1.0 µA3, 9
Input Forward Voltage VF1, 2, 3 IF = 20 mA 1.55 1.8 V 1 1, 14
1.9 1, 13
Reverse Breakdown Voltage BVR1, 2, 3 IR = 10 µA5 V1, 14
31, 13
Logic High Supply
Current
Single
Channel
ICCH 1, 2, 3 VCC = 18 V, IF = 0 mA 0.1 10 µA1
Dual
Channel
VCC = 18 V, IF = 0 mA (all channels) 0.2 20 1,4
Quad
Channel
VCC = 18 V, IF = 0 mA (all channels) 0.4 40 1
Logic Low Supply
Current
Single
Channel
ICCL 1, 2, 3 VCC = 18 V, IF = 20 mA 35 200 µA1
Dual
Channel
VCC = 18 V, IF1 = IF2 = 20 mA 70 400 1, 4
Quad
Channel
VCC = 18 V, IF1 = IF2 = IF3 = IF4 = 20
mA
140 800 1
Propagation Delay Time to Logic
High at Output
tPLH 9, 10, 11 RL = 8.2 kΩ,
CL = 50 pF,
IF = 16 mA,
VCC = 5 V
1.0 6.0 µs6, 9 1, 6
Propagation Delay Time to Logic
Low at Output
tPHL 0.4 2.0
9
Notes:
1. Each channel of a multi-channel device.
2. Current Transfer Ratio is defined as the ratio
of output collector current, IO, to the
forward LED input current, IF, times 100%.
CTR is known to degrade slightly over the
unit’s lifetime as a function of input current,
temperature, signal duty cycle, and system
on time. Refer to Application Note 1002 for
more detail. ln short, it is recommended that
designers allow at least 20-25% guardband
for CTR degradation.
3. All devices are considered two-terminal
devices; measured between all input leads
or terminals shorted together and all output
leads or terminals shorted together.
4. The 4N55, 4N55/883B, HCPL-257K, HCPL-
6530, HCPL-6531, and HCPL-653K dual
channel parts function as two independent
single channel units. Use the single channel
parameter limits. IF = 0 mA for channel
under test and IF = 20 mA for other
channels.
5. Measured between adjacent input pairs
shorted together for each multichannel
device.
Typical Characteristics
All typical values are at TA = 25°C, VCC = 5 V, unless otherwise specified.
6. tPHL propagation delay is measured from the
50% point on the leading edge of the input
pulse to the 1.5 V point on the leading edge
of the output pulse. The tPLH propagation
delay is measured from the 50% point on the
trailing edge of the input pulse to the 1.5 V
point on the trailing edge of the output
pulse.
7. CML is the maximum rate of rise of the
common mode voltage that can be
sustained with the output voltage in the
logic low state (VO < 0.8 V). CMH is the
maximum rate of fall of the common mode
voltage that can be sustained with the
output voltage in the logic high state (VO >
2.0 V).
8. Bandwidth is the frequency at which the ac
output voltage is 3 dB below the low
frequency asymptote. For the HCPL-5530
the typical bandwidth is 2 MHz.
9. This is a momentary withstand test, not an
operating condition.
10. Higher CTR minimums are available to
support special applications.
11. Measured between each input pair shorted
together and all output connections for that
channel shorted together.
12. Standard parts receive 100% testing at 25°C
(Subgroups 1 and 9). SMD and 883B parts
receive 100% testing at 25, 125, and -55°C
(Subgroups 1 and 9, 2 and 10, 3 and 11,
respectively).
13. Not required for 4N55, 4N55/883B, HCPL-
257K, 5962-8767901, and 5962-8767905
types.
14. Required for 4N55, 4N55/883B, HCPL-257K,
5962-8767901, and 5962-8767905 types only.
Parameter Symbol Test Conditions Typ. Units Fig. Notes
Input Capacitance CIN VF = 0 V, f = 1 MHz 60 pF 1
Input Diode Temperature Coefficient ∆VF/∆TAIF = 20 mA -1.5 mV/°C 1
Resistance (Input-Output) RI-O VI-O = 500 V 1012 Ω3
Capacitance (Input-Output) CI-O f = 1 MHz 1.0 pF 1, 11
Transistor DC Current Gain hFE VO = 5 V, IO = 3 mA 250 - 1
Small Signal Current Transfer Ratio ∆IO/∆IFVCC = 5 V, VO = 2 V 21 % 7 1
Common Mode Transient Immunity
at Logic High Level Output
|CMH|I
F = 0 mA, RL = 8.2 kΩ,
VO (min) = 2.0 V,
VCM = 10 VP-P
1000 V/µs10 1, 7
Common Mode Transient Immunity
at Logic Low Level Output
|CML|I
F = 16 mA, RL = 8.2 kΩ,
VO (max) = 0.8 V,
VCM = 10 VP-P
-1000 V/µs10 1, 7
Bandwidth BW 9 MHz 8 8
Multi-Channel Product Only
Parameter Symbol Test Conditions Typ. Units Notes
Input-Input Insulation Leakage Current II-I RH ≤ 65%, VI-I = 500 V, t = 5 s 1 pA 5, 9
Resistance (Input-Input) RI-I VI-I = 500 V 1012 Ω5
Capacitance (Input-Input) CI-I f=1 MHz 0.8 pF 5
10
Figure 1. Input Diode Forward Current vs.
Forward Voltage.
Figure 2. DC and Pulsed Transfer
Characteristic.
Figure 3. Normalized Current Transfer Ratio
vs. Input Diode Forward Current.
Figure 4. Logic High Output Current vs.
Temperature.
Figure 5. Logic Low Supply Current vs. Input
Diode Forward Current.
Figure 6. Propagation Delay vs. Temperature.
Figure 7. Normalized Small Signal Current
Transfer Ratio vs. Quiescent Input Current.
IOH - LOGIC HIGH OUTPUT CURRENT - µA
-60 140
100
0.001
TA - TEMPERATURE - ˚C
-40 20 40 60
10
1
0.1
120
0.01
-20 80
0 100
IF = 250 µA,
IF (OTHER CHANNELS) = 20 mA
IF = 0 µA,
IF (OTHER CHANNELS) = 20 mA
IF = IF (OTHER CHANNELS)
= 0 mA
VCC = VO = 18 V
11
Figure 8. Frequency Response.
Figure 9. Switching Test Circuit.*
*JEDEC Registered Data.
GND
VCC
IF+5 V
VO
D.U.T.
100 Ω
IF MONITOR
PULSE GEN.
ZO = 50 Ω
tr = 5 ns
CL* = 50 pF
10 % DUTY CYCLE
1/f < 100 µs
RL
NOTES:
* C L INCLUDES PROBE AND STRAY WIRING CAPACITANCE.
BASE LEAD NOT CONNECTED.
SINGLE CHANNEL
OR COMMON V CC DEVICES
GND
V
CC
+12 V
V
O
(1 M
Ω
, 12 pF
TEST INPUT)
D.U.T.
R
F
V
IN
9.1 k Ω
SINGLE CHANNEL TESTING,
INDEPENDENT V
CC
DEVICES
1 k Ω
2.1 k Ω
+12 V
Q
1
47 µF
0.01 µF
Q
3
Q
2
0.01 µF
1.2 k Ω
15 k Ω470
Ω
100 Ω
V
B
V
O
51 Ω
22 Ω
100 Ω
0.1 µF0.1 µF
TRIM FOR UNITY GAIN
Q
1
, Q
2
, Q
3
: 2N3904 TYPICAL LINEARITY = +3 % AT V
IN
= 1 V
P-P
TYPICAL SNR = 50 dB
TYPICAL R
F
= 375 Ω
TYPICAL V
O dc
= 3.8 V
TYPICAL I
F
= 9 mA
1N4150
GND
V
CC
+15 V
V
O
D.U.T.
100 Ω
AC INPUT
100 Ω
COMMON
V
CC
DEVICES
560 Ω
20 k Ω
+5 V
SET I
F
2N3053
1.6 Vdc
0.25 V
P-P
ac
0.1 µF
NORMALIZED RESPONSE - dB
0.1 100
+15
-20
f - FREQUENCY - MHz
+10
+5
-5
-15
1.0 10
-10
0
TA = 25 ˚C
INDEPENDENT
VCC DEVICES
COMMON VCC
DEVICES
12
Figure 11. Recommended Logic Interface.
Figure 12. Operating Circuit for Burn-In and
Steady State Life Tests. All Channels Tested
Simultaneously.
VFF GND
V
CC
I
F
VCM
RL
+5 V
VO
+
PULSE GEN.
NOTE: BASE LEAD NOT CONNECTED.
A
BD.U.T.
R
M
SINGLE CHANNEL OR
COMMON V
CC
DEVICES
-
Figure 10. Test Circuit for Transient Immunity and Typical Waveforms.
GND
V
CC
D.U.T. R
L
220 Ω
5 V V
CC
LOGIC GATE
0.01 µF
EACH CHANNEL
TTL
GND
V
CC
V
O
D.U.T.*
NOTE: BASE LEAD NOT CONNECTED.
T
A
= +125 ˚C
V
OC
NOMINAL CONDITIONS
PER CHANNEL: IF = 20 mA
IO = 4 mA
ICC = 30 µA
V
CC
V
IN
+
(EACH OUTPUT)
(EACH INPUT) 0.1 µF
-
*The equivalent output load resistance is affected by the LSTTL input current and is
approximately 8.2 kΩ. This is a worst case design which takes into account 25%
degradation of CTR. See App. Note 1002 to assess actual degradation and lifetime.
Logic Family LSTTL CMOS
Device No. 54LS14 CD40106BM
VCC 5 V 5 V 15 V
RL 5% Tolerance 18 kΩ *8.2 kΩ22 kΩ
13
MIL-PRF-38534 Class H, Class K, and
DSCC SMD Test Program
Agilent’s Hi-Rel Optocouplers
are in compliance with MIL-
PRF-38534 Classes H and K.
Class H and Class K devices
are also in compliance with
DSCC drawings 5962-87679,
and 5962-90854. Testing
consists of 100% screening and
quality conformance inspection
to MIL-PRF-38534.
Description
The schematic uses a
dualchannel, high-speed
optocoupler (HCPL-5530) to
function as a servo type dc
isolation amplifier. This circuit
operates on the principle that
two optocouplers will track
each other if their gain
changes by the same amount
over a specific operating
region.
Performance of Circuit
• 1% linearity for 10 V peak-
to-peak dynamic range
• Gain drift: -0.03%/°C
• Offset Drift: ± 1 mV/°C
• 25 kHz bandwidth (limited
by Op-Amps U1, U2)
Figure 13. Isolation Amplifier Application Circuit.
V
OUT
I
F
3
R
1
2
3
4
8
7
6
5
1
I
F2
V
IN
U
1
2
U
3
-15 V
-
+
-
+
I
C
2
-15 V
I
CC
6 mA
I
C
1
= K
1
I
F
1
I
n
1
I
C
2
= K
2
I
F
2
I
n
2
HCPL-5530
2
U
4
-
+
2
5 k Ω GAIN ADJUST
R
4
1 kΩ
5
R
5 k Ω
OFFSET ADJUST
I
C
1
220 Ω
R
2
2.7 k Ω
R
1
2.7 k Ω
+
U
2
-
+
-
U
1
, U
2
, U
3
, U
4
, LM307
50 k Ω
F
´
1
F
2
´
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semiconductors
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Data subject to change.
Copyright © 2004 Agilent Technologies, Inc.
December 10, 2004
5989-1659EN
