Rev. 1.2 6/12 Copyright © 2012 by Silico n Laboratories Si860x
Si860x
BIDIRECTIONAL I2C ISOLATORS WITH UNIDIRECTIONAL
DIGITAL CHANNELS
Features
Applications
Description
The Si860x series of isolators are single-package galvanic isolation solutions for I2C
and SMBus serial port applications. These products are based on Silicon Labs
proprietary RF isolation technology and offer shorter propagation delays, lower
power consumption, smaller installed size, and more stable operation with
temperature and age versus opto couplers or other digital isolators.
All devices in this family include hot-swap, bidirectional SDA and/or SCL isolation
channels with open-drain, 35 mA sink capability that operate to a maximum
frequency of 1.7 MHz. The 8-pin version (Si8600) supports bidirectional SDA and
SCL isolation; the Si8602 supports bidirectional SDA and unidirectional SCL
isolation, and the 16-pin versions (Si8605, Si8606) feature two unidirectional
isolation channels to support additional system signals, such as interrupts or resets.
All versions contain protection circuits to guard against data errors when an
unpowered device is inserted into a powered system.
Small size, low installed cost, low power consumption, and short propagation delays
make the Si860x family the optimum solution for isolating I2C and SMBus serial
ports.
Safety Regulatory Approval
Independent, bidirectional SDA and
SCL isolation channels
Open drain outputs with 35 mA
sink current
Supports I2C clocks up to 1.7 MHz
Unidirectional isolation channels
support additional system signals
(Si8605, Si8606)
Up to 5000 VRMS isolation
UL, CSA, VDE recognition
60-year life at rated working voltage
High electromagnetic immunity
Wide operating supply voltage
3.0 to 5.5 V
Wide temperature range
–40 to +125 °C
Transient immunity 50 kV/µs
AEC-Q100 qualification
RoHS-compliant packages
SOIC-8 narrow body
SOIC-16 wide body
SOIC-16 narrow body
Isolated I2C, PMBus, SMBus
Power over Ethernet
Motor Control Systems
Hot-swap applications
Intelligent Power systems
Isolated SMPS systems with PMBus
interfaces
UL 1577 recognized
Up to 5000 VRMS for 1 minute
CSA component notice 5A approval
IEC 60950-1, 61010-1, 60601-1
(reinforced insulation)
VDE certification conformity
IEC 60747-5-2
(VDE0884 Part 2)
EN60950-1 (reinforced insulation)
Ordering Information:
See page 26.
2 Rev. 1.2
Si860x
Rev. 1.2 3
Si860x
TABLE OF CONTENTS
Section Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.1. Test Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
2.1. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3. Typical Application Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.1. I2C Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.2. I2C Isolator Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.3. I2C Isolator Design Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
3.4. I2C Isolator Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
3.5. Typical Application Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
4. Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.1. Device Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.2. Undervoltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.3. Input and Output Characteristics for Non-I2C Digital Channels . . . . . . . . . . . . . . . .20
4.4. Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.5. Fail-Safe Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.6. Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
7. Package Outline: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
8. Land Pattern: 16-Pin Wide-Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
9. Package Outline: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
10. Land Pattern: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
11. Package Outline: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
12. Land Pattern: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
13. Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
13.1. Si860x Top Marking (16-Pin Wide Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . .35
13.2. Top Marking Explanation (16-Pin Wide Body SOIC) . . . . . . . . . . . . . . . . . . . . . . .35
13.3. Si860x Top Marking (8-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . .36
13.4. Top Marking Explanation (8-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . . . . .36
13.5. Si860x Top Marking (16-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . .37
13.6. Top Marking Explanation (16-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . . . .37
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
4 Rev. 1.2
Si860x
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter Symbol Test Condition Min Typ Max Unit
Ambient Operating Temperature* TA–40 25 125* °C
Supply Voltage AVDD 3.0 — 5.5 V
BVDD 3.0 — 5.5 V
*Note: The maximum ambient temperature is dependent on data frequency, output loading, number of operating channels,
and supply voltage.
Table 2. Si860x Power Characteristics*
3.0 V < VDD < 5.5 V. TA = –40 to +125 °C. Typical specs at 25 °C (See Figures 2 and 9 for test diagrams.)
Parameter Symbol Test Condition Min Typ Max Unit
Si8600 Supply Current
AVDD Current
BVDD Current Idda
Iddb All channels = 0 dc —
—5.4
4.3 7.6
6.5 mA
mA
AVDD Current
BVDD Current Idda
Iddb All channels = 1 dc —
—2.6
1.9 3.9
2.9 mA
mA
AVDD Current
BVDD Current Idda
Iddb All channels = 1.7 MHz —
—3.3
2.6 5.0
3.9 mA
mA
Si8602 Supply Current
AVDD Current
BVDD Current Idda
Iddb All channels = 0 dc —
—1.8
1.8 2.7
2.7 mA
mA
AVDD Current
BVDD Current Idda
Iddb All channels = 1 dc —
—4.7
3.1 7.1
4.7 mA
mA
AVDD Current
BVDD Current Idda
Iddb All channels = 1.7 MHz —
—2.5
2.1 3.8
3.2 mA
mA
Si8605 Supply Current
AVDD Current
BVDD Current Idda
Iddb All non-I2C channels = 0
All I2C channels = 1 —
—3.4
2.7 5.1
4.1 mA
mA
AVDD Current
BVDD Current Idda
Iddb All non-I2C channels = 1
All I2C channels = 0 —
—7.2
6.2 10.1
8.7 mA
mA
AVDD Current
BVDD Current Idda
Iddb All non-I2C channels = 5 MHz
All I2C channels = 1.7 MHz —
—4.2
3.6 6.3
5.4 mA
mA
*Note: All voltages are relative to respective ground.
Rev. 1.2 5
Si860x
Si8606 Supply Current
AVDD Current
BVDD Current Idda
Iddb All non-I2C channels = 0
All I2C channels = 1 —
—2.8
3.0 4.2
4.5 mA
mA
AVDD Current
BVDD Current Idda
Iddb All non-I2C channels = 1
All I2C channels = 0 —
—8.3
5.5 11.6
7.7 mA
mA
AVDD Current
BVDD Current Idda
Iddb All non-I2C channels = 5 MHz
All I2C channels = 1.7 MHz —
—4.1
3.5 6.2
5.3 mA
mA
Table 3. Si8600/02/05/06 Electrical Characteristics for Bidirectional I2C Channels1
3.0 V < VDD < 5.5 V. TA = –40 to +125 °C. Typical specs at 25 °C unless otherwise noted.
Parameter Symbol Test Condition Min Typ Max Unit
Logic Levels Side A
Logic Input Threshold2
Logic Low Output Voltages
Input/Output Logic Low Level
Difference3
I2CVT (Side A)
I2CVOL (Side A)
I2CV (Side A)
ISDAA, ISCLA
(>0.5 mA, <3.0 mA)
410
540
50
—
—
—
540
800
—
mV
mV
mV
mV
Logic Levels Side B
Logic Low Input Voltage
Logic High Input Voltage
Logic Low Output Voltage
I2CVIL (Side B)
I2CVIH (Side B)
I2CVOL (Side B) ISCLB = 35 mA
—
2.0
—
—
—
—
0.8
—
500
V
V
mV
SCL and SDA Logic High
Leakage Isdaa, Isdab
Iscla, Isclb SDAA, SCLA = VSSA
SDAB, SCLB = VSSB —2.010µA
Pin Capacitance SDAA, SCLA,
SDAB, SDBB CA
CB —
—10
10 —
—pF
pF
Notes:
1. All voltages are relative to respective ground.
2. VIL < 0.410 V, VIH > 0.540 V.
3. I2CV (Side A) = I2CVOL (Side A) – I2CVT (Side A). To en sure no latch-up on a given bus, I2CV (Side A) is the
minimum difference between the output logic low level of the driving device and the input logic threshold.
4. Side A measured at 0.6 V.
Table 2. Si860x Power Characteristics* (Continued)
3.0 V < VDD < 5.5 V. TA = –40 to +125 °C. Typical specs at 25 °C (See Figures 2 and 9 for test diagrams.)
Parameter Symbol Test Condition Min Typ Max Unit
*Note: All voltages are relative to respective ground.
6 Rev. 1.2
Si860x
Timing Specifications (Measured at 1.40 V Unless Otherwise Specified)
Maximum I2C Bus Frequency Fmax — — 1.7 MHz
Propagation Delay
5 V Operation
Side A to Side B Rising4
Side A to Side B Falling4
Side B to Side A Rising
Side B to Side A Falling
3.3 V Operation
Side A to Side B Rising4
Side A to Side B Falling4
Side B to Side A Rising
Side B to Side A Falling
Tphab
Tplab
Tphba
Tplba
Tphab
Tplab
Tphba
Tplba
No bus capacitance,
R1 = 1400,
R2 = 499,
See Figure 2
R1 = 806
R2 = 499
—
—
—
—
—
—
—
—
38
15
33
11
44
17
30
14
45
26
46
22
55
29
40
27
ns
ns
ns
ns
ns
ns
ns
ns
Pulse Width Distortion
5V
Side A Low to Side B Low4
Side B Low to Side A Low
3.3 V
Side A Low to Side B Low4
Side B Low to Side A Low
PWDAB
PWDBA
PWDAB
PWDBA
No bus capacitance,
R1 = 1400,
R2 = 499,
See Figure 2
R1 = 806,
R2 = 499
—
—
—
—
22
21
27
15
32
32
35
25
ns
ns
ns
ns
Table 3. Si8600/02/05/06 Electrical Characteristics for Bidirectional I2C Channels1 (Continued)
3.0 V < VDD < 5.5 V. TA = –40 to +125 °C. Typical specs at 25 °C unless otherwise noted.
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. All voltages are relative to respective ground.
2. VIL < 0.410 V, VIH > 0.540 V.
3. I2CV (Side A) = I2CVOL (Side A) – I2CVT (Side A). To en sure no latch-up on a given bus, I2CV (Side A) is the
minimum difference between the output logic low level of the driving device and the input logic threshold.
4. Side A measured at 0.6 V.
Rev. 1.2 7
Si860x
Table 4. Electrical Characteristics for Unidirectional Non-I2C Digital Channels (Si8602/05/06)
3.0 V < VDD < 5.5 V. TA = –40 to +125 °C. Typical specs at 25 °C
Parameter Symbol Test Condition Min Typ Max Unit
Positive-Going Input
Threshold VT+ All inputs rising 1.4 1.67 1.9 V
Negative-Going Input
Threshold VT– All inputs falling 1.0 1.23 1.4 V
Input Hysteres is VHYS 0.38 0.44 0.50 V
High Level Input Voltage VIH 2.0 — — V
Low Level Input Voltage VIL ——0.8V
High Level Output Voltage VOH loh = –4 mA AVD D, BVDD
–0.4 4.8 — V
Low Level Output Voltage VOL lol = 4 mA — 0.2 0.4 V
Input Leakag e Curr en t IL——±10µA
Output Impedance1ZO—50—
Timing Characteristics
Maximum Data Rate 0 — 10 Mbps
Minimum Pulse Width — — 40 ns
Propagation Delay tPHL, tPLH See Figure 1 — — 20 ns
Pulse Width Distortion
|tPLH – tPHL|PWD See Figure 1 — — 12 ns
Propagation Delay Skew2tPSK(P-P) — — 20 ns
Channel-Channel Skew tPSK — — 10 ns
Output Rise Time trC3=15pF
See Figure 1 and
Figure 2
—2.54.0ns
Output Fall Time tfC3=15pF
See Figure 1 and
Figure 2
—2.54.0ns
Peak Eye Diagram Jitter tJIT(PK) — 350 — ps
Notes:
1. The nominal output impedance of a non-I2C isolator driver channel is approximately 50 , ±40%, which is a
combination of the value of the on-chip seri es termination resistor and channel resistance of the output driver FET.
When driving loads where transmission line effects will be a factor , output pins should be appropriately terminated with
controlled impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
8 Rev. 1.2
Si860x
Figure 1. Propagation Delay Timing (Non-I2C Channels)
Table 5. Electrical Characteristics for All I2C and Non-I2C Channels
3.0 V < VDD < 5.5 V. TA = –40 to +125 °C. Typical specs at 25 °C
Parameter Symbol Test Condition Min Typ Max Unit
VDD Undervoltage Threshold VDDUV+ VDD1, VDD2 rising 1.95 2.24 2.375 V
VDD Undervoltage Threshold VD DUV– VDD1, VDD2 falling 1.88 2.16 2.325 V
VDD Negative-Going Locko ut
Hysteresis VDDHYS 50 70 95 mV
Common Mode Transient
Immunity CMTI VI=V
DD or 0 V 35 50 — kV/µs
Shut Down Time from UVLO tSD —3.0—µs
Start-up Time*tSTART —1540µs
*Note: Start-u p time is the time period from the application of power to valid data at the output.
Typical
Input tPLH tPHL
Typical
Output trtf
90%
10%
90%
10%
1.4 V
1.4 V
Rev. 1.2 9
Si860x
1.1. Test Circuits
Figure 2 depicts the timing test diagram.
Figure 2. Simplified Timing Test Diagram
Table 6. Regulatory Information*
CSA
The Si860x is certified under CSA Component Acceptance Notice 5A. For more details, see File 232873.
61010-1: Up to 600 VRMS reinforced insulation working voltage; up to 600 VRMS basic insulation working voltage.
60950-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working volt-
age.
60601-1: Up to 125 VRMS reinforced insulation working voltage; up to 380 VRMS basic insulation working voltage.
VDE
The Si860x is certified according to IEC 60747-5-2. For more details, see File 5006301-4880-0001.
60747-5-2: Up to 1200 Vpeak for basic insulation working voltage.
60950-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working volt-
age.
UL
The Si860x is certified under UL1577 component recognition program. For more details, see File E257455.
Rated up to 5000 V RMS isolation voltage for basic protection.
*Note: Regulatory Certifications apply to 3.75 kVRMS rated devices which are production tested to 4.5 kVRMS for 1 sec.
Regulatory Certifications apply to 5.0 kVRMS rated devices which are production tested to 6.0 kVRMS for 1 sec.
For more information, see "6.Ordering Guide " on page 26.
AVDD
NC
BVDD
NC
NC NC
ADOUT BDIN
ASDA BSDA
ASCL BSCL
ADIN BDOUT
AGND BGND
Si8605
C1C1C3
R1R1R2
R2
C3C2C2
10 Rev. 1.2
Si860x
Table 7. Insulation and Safety-Related Specifications
Parameter Symbol Test Co ndition Value Unit
NB
SOIC-8 NB
SOIC-16 WB
SOIC-16
Nominal Air Gap (Clearance)1L(1O1) 4.9 4.9 8.0 mm
Nominal External Tracking
(Creepage)1L(1O2) 4.01 4.01 8.0 mm
Minimum Internal Gap
(Internal Clearance) 0.011 0.011 0.014 mm
Tracking Resistance
(Proof Tracking Index) PTI IEC60112 600 600 600 VRMS
Erosion Depth ED 0.040 0.019 0.019 mm
Resistance (Input-Output)2RIO 1012 1012 1012
Capacitance (Input-Output)2CIO f = 1 MHz 1.0 2.0 2.0 pF
Input Capacitance3CINon-I2C Channel 4.0 4.0 4.0 pF
I2C Channel 10 10 10 pF
Notes:
1. VDE certifies the clearance and creepage limits as 4.7 mm minimum for the NB SOIC-8 and SOIC-16 packages and
8.5 mm minimum for the WB SOIC-16 package. UL does not impose a clearance and creepage minimum for
component level certifications. CSA certifies the clearance and creepage limits as 3.9 mm minimum for the NB SOIC-8
and SOIC-16 packages and 7.6 mm minimum for the WB SOIC-16 package.
2. To determine resistance and capacitance, the Si860x, SO-16, is converted into a 2-terminal device. Pins 1–8 (1–4, SO-
8) are shorted together to form the first terminal and pins 9–16 (5–8, SO-8) are shorted together to form the second
terminal. The parameters are then measured between these two terminals.
3. Measured from input pin to ground.
Table 8. IEC 60664-1 (VDE 0844 Part 2) Ratings
Parameter Test Conditions Specification
NB SOIC-8
SOIC-16 WB SOIC-16
Basic Isolation Group Material Group I I
Installation Classification
Rated Mains Voltages < 150 VRMS I-IV I-IV
Rated Mains Voltages < 300 VRMS I-III I-IV
Rated Mains Voltages < 400 VRMS I-II I-III
Rated Mains Voltages < 600 VRMS I-II I-III
Rev. 1.2 11
Si860x
Table 9. IEC 60747-5-2 Insulation Char acteristics for Si86xxxx*
Parameter Symbol Test Condition Characteristic Unit
WB
SOIC-16 NB SOIC-8
SOIC-16
Maximum Working Insulation
Voltage VIORM 1200 630 Vpeak
Input to Output Test Voltage VPR
Method b1
(VIORM x1.875=V
PR, 100%
Production Test, tm= 1 sec,
Partial Discharge < 5 pC)
2250 1182 Vpeak
Transient Overvoltage VIOTM t = 60 sec 6000 6000 Vpeak
Pollution Degree
(DIN VDE 0110, Table 1) 22
Insulation Resistance at TS,
VIO =500V RS>109>109
*Note: Maintenance of the safety data is ensured by protective circuits. The Si86xxxx provides a climate classification of
40/125/21.
Table 10. IEC Safety Limiting Values1
Parameter Symbol Test Condition NB
SOIC-8 NB
SOIC-16 WB
SOIC-16 Unit
Case Temperature TS150 150 150 °C
Safety Input Current IS
JA = 100 °C/W (WB SOIC-16),
105 °C/W (NB SOIC-16), 140 °C/W
(NB SOIC-8)
AVDD, BVDD = 5.5 V,
TJ=150°C, T
A=25°C
160 210 220 mA
Device Power Dissipation2PD220 275 275 W
Notes:
1. Maximum value allowed in the event of a failure. Refer to the thermal derating curve in Figures 3, 4, and 5.
2. The Si86xx is tested with AVDD, BVDD = 5.5 V; TJ=150ºC; C
1, C2=0.1µF; C
3= 15 pF; R1, R2 = 3kinput 1 MHz
50% duty cycle square wave.
12 Rev. 1.2
Si860x
Figure 3. NB SOIC-8 Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-2
Figure 4. NB SOIC-16 Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-2
Table 11. Thermal Characteristics
Parameter Symbol Test Condition NB
SOIC-8 NB
SOIC-16 WB
SOIC-16 Unit
IC Junction-to-Air Thermal Resistance JA 140 105 100 °C/W
0 20015010050
400
200
100
0
Case Temperature (ºC)
Safety-Limiting Values (mA)
300
AVDD, BVDD = 3.6 V
AVDD, BVDD = 5.5 V
270
160
020015010050
500
400
200
100
0
Temperature (ºC)
Safety-Limiting Current (mA)
300
350
210 AVDD , BVDD = 3.6 V
AVDD , BVDD = 5.5 V
Rev. 1.2 13
Si860x
Figure 5. WB SOIC-16 Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-2
Table 12. Absolute Maximum Ratings1
Parameter Symbol Min Typ Max Unit
Storage Temperature2TSTG –65 — 150 ºC
Ambient Tem p er a tur e Unde r Bias TA–40 — 125 ºC
Junction Temperature TJ——150°C
Supply Voltage VDD –0.5 — 7.0 V
Input Voltage VI–0.5 — VDD + 0.5 V
Output Voltage VO–0.5 — VDD + 0.5 V
Output Current Drive (non-I2C channels) IO——±10mA
Side A output current drive (I2C channels) IO——±15mA
Side B output current drive (I2C channels) IO——±75mA
Lead Solder Temperature (10 s) — — 260 ºC
Maximum Isolation (Input to Output) (1 sec)
NB SOIC-8, SOIC-16 — — 4500 VRMS
Maximum Isolation (Input to Output) (1 sec)
WB SOIC-16 — — 6500 VRMS
Notes:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
restricted to conditions as specified in the operational sections of this data sheet.
2. VDE certifies storage temperature from –40 to 150 °C.
020015010050
500
400
200
100
0
Temperature (ºC)
Safety-Limiting Current (mA)
300
350
220 AVDD , BVDD = 3.6 V
AVDD , BVDD = 5.5 V
14 Rev. 1.2
Si860x
2. Functional Description
2.1. Theory of Operation
The operation of an Si86xx channel is analogous to that of an opto coupler, except an RF carrier is modulated
instead of light. This simple architecture provides a robust isolated data path and requires no special
considerations or initialization at start-up. A simplified block diagram for a single unidirectional Si86xx channel is
shown in Fig ure 6.
Figure 6. Simplified Channel Diagram
A channel consists of an RF Transmitter and RF Receiver separated by a semiconductor-based isolation barrier.
Referring to the Transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying. The
Receiver contains a demodulat or that decodes the input state according to its RF energy content and applies the
result to output B via the output driver. This RF on/off keying scheme is superior to pulse code schemes as it
provides best-in-class noise immunity, low power consumption, and better immunity to magnetic fields. See
Figure 7 for more details.
Figure 7. Modulation Scheme
RF
OSCILLATOR
MODULATOR DEMODULATOR
A B
Semiconductor-
Based Isolation
Barrier
Transmitter Receiver
Input Signal
Output Signal
Modulation Signal
Rev. 1.2 15
Si860x
3. Typical Application Overview
3.1. I2C Background
In many applications, I2C, SMBus, and PMBus interfaces require galvanic isolation for safety or ground loop
elimination. For example, Power over Ethernet (PoE) applications typically use an I2C interface for communication
between the PoE power sourcing device (PSE), and the earth ground referenced system controller. Galvanic
isolation is required both by standard and also as a practical matter to prevent ground loops in Ethernet connected
equipment.
The physical interface consists of two wires: serial data (SDA) and serial clock (SCL). These wires are connected
to open collector drivers th at serve as both inputs and outputs. At first glance, it app ears that SDA and SCL can be
isolated simply by placing two unidirectional isolators in parallel, and in opposite directions. However, this
technique creates feedback that latches the bus line low when a logic low asserted by either master or slave. This
problem can be remedied by adding anti-latch circuits, but results in a larger and more expensive solution. The
Si860x products offer a single-chip, anti-latch solution to the problem of isolating I2C/SMBus applications and
require no external components except the I2C/SMBus pull-up resistors. In addition, they provide isolation to a
maximum of 5.0 kVRMS, support I2C clock stretching, and operate to a maximum I2C bus speed of 1.7 Mbps.
3.2. I2C Isolator Operation
Without anti-latch protection, bidirectional I2C isolators latch when an isolator output logic low propagates back
through an ad jacent isolator ch annel creating a stable latche d low condition on both sides. Anti-la tch protection is
typically added to one side of the isolator to avoid this condition (the “A” side for the Si8600/02/05 /06).
The following examples illustrate typical circuit configurations using the Si8600/02/05/06.
Figure 8. Isolated Bus Overview (I2C Channels Only)
The “A side” output low (VOL) and input low (VIL) levels are designed such that the isolator VOL is greater than the
isolator VIL to pr e ven t th e la tch condition.
I2C/SMBus
Unit 1 Si8600/02/05/06
I2C/SMBus
Unit 2
ISO1
ISO2
VOL
VIL
+
-
VOL
VIL
A Side
B Side
16 Rev. 1.2
Si860x
3.3. I2C Isolator Design Constraints
Table 13 lists the I2C isolator design constraints.
3.4. I2C Isolator Design Considerations
The first step in applying an I2C isolator is to choose which side of the bus w ill be connected to the isolator A side.
Ideally, it should be the side which:
1. Is compatible with the range of bus pu ll up spec ifie d by th e ma nuf act ur er. Fo r exa m ple , th e Si86 00 /0 2 /0 5/ 06
isolators are normally used with a pull up of 0.5 mA to 3 mA.
2. Has the highest input low level for devices on the bus. Some devices may specify an input low of 0.9 V and
other devices might require an input low of 0.3 x Vdd. Assuming a 3.3 V minimum power supply, the side with
an input low of 0.3 x Vdd is the better side because this side has an input low level of 1.0 V.
3. Have devices on the bus that can pull down below the isola to r inp ut low level. Fo r exa m ple , th e Si86 0x inpu t
level is 0.41 V. As most CMOS devices can pull to within 0.4 V of GND this is generally not an issue.
4. Has the lowest noise. Due to the special logic levels, noise margins can be as low as 50 mV.
Table 13. Design Constraints
Design Constra in t Data Sheet Value s Effect of Bus Pull-up Strength
and Temperature
To prevent the latch condition, the
isolator output low level must be
greater than the isolator input low
level.
Isolator VOL 0.7 V typical
Isolator VIL 0.5 V typical
Input/Output Logic Low Level
Difference
∆VSDA1, ∆VSCL1 = 50 mV minimum
This is normally guaranteed by the
isolator data sheet. However, if the
pull up strength is too weak, the out-
put low voltage will fall and can get
too close to the input low logic level.
These track over temperature.
The bus output low must be less
than the isolator input low logic
level.
Bus VOL =0.4V maximum
Isolator VIL = 0.41 V minimum
If the pull up strength is too large,
the devices on the bus might not pull
the voltage below the input low
range. These have opposite temper-
ature coefficients. Worst case is hot
temperature.
The isolator output low must be
less than the bus input low.
Bus VIL 0.3 x VDD = 1.0 V minimum for
VDD =3.3V
Isolator VOL = 0.8 V maximum
If the pull up strength is too large,
the isolator might not pull below the
bus input low voltage.
Si8600/02/05/06 Vol: –1.8 mV/C
CMOS buffer: –0.6 mV/C
This provides some temperature
tracking, but worst case is cold tem-
perature.
Rev. 1.2 17
Si860x
3.5. Typical Application Schematics
Figures 9 through 14 illustrate typical circuit configurations using the Si8600, Si8602, Si8605, and Si8606.
Figure 9. Typical Si8600 Application Diagram
Figure 10. Typical Si8602 Application Diagram
Figure 11. Typical Si8600 Application Diagram
1
2 7
Si8600
3
8
AVDD
ASDA
ASCL
AGND BGND
BSCL
BSDA
BVDD
3k 3k
0.1 µF
0.1 µF
3k 3k
I2C
Bus
6
5
4
1
2 7
Si8602
3
8
AVDD
ASDA
ASCL
AGND BGND
BSCL
BSDA
BVDD
3k0.1 µF
0.1 µF
3k
I2C
Bus
6
5
4
1
2
3
4
5
6
7
15
14
13
12
11
10
8 9
Si8600
3
16
AVDD
ASDA
ASCL
AGND BGND
BSCL
BSDA
BVDD
3k 3k
0.1 µF
0.1 µF
3k 3k I2C
Bus
AGND BGND
18 Rev. 1.2
Si860x
Figure 12. Typical Si8602 Application Diagram
Figure 13. Typical Si8605 Application Diagram
Figure 14. Typical Si8606 Application Diagram
1
2
3
4
5
6
7
15
14
13
12
11
10
8 9
Si8602
3
16
AVDD
ASDA
ASCL
AGND BGND
BSCL
BSDA
BVDD
3k
0.1 µF
0.1 µF
3k I2C
Bus
AGND BGND
1
2
3
4
5
6
7
15
14
13
12
11
10
8 9
Si8605
3
16
AVDD
ASDA
ASCL
AGND
Micro-
controller
Micro-
controller
BGND
BSCL
BSDA
BVDD
3k 3k
0.1 µF
0.1 µF
3k 3k
I2C
Bus
RESET
INT
1
2
3
4
5
6
7
15
14
13
12
11
10
8 9
Si8606
3
16
AVDD
ASDA
ASCL
AGND
Micro-
controller
BGND
BSCL
BSDA
BVDD
3k 3k
0.1 µF
0.1 µF
3k 3k
I2C
Bus
RESET
INT
Rev. 1.2 19
Si860x
4. Device Operation
Device behavior during start-up, normal operation, and shutdown is shown in Figure 15, where UVLO+ and UVLO-
are the positive-going and negative-going thresholds respectively. Refer to Table 14 to determine outputs when
power supply (VDD) is not present.
4.1. Device Startup
Outputs are held low during powerup until VDD is above the UVLO threshold for time period tSTART. Following
this, the outputs follow the states of inputs.
4.2. Undervoltage Lockout
Undervoltage Lockout (UVLO) is provided to prevent erroneous operation during device startup and shutdown or
when VDD is below its specified operating circuits range. Both Side A and Side B each have their own
undervoltage lockout monitors. Each side can enter or exit UVLO independently. For example, Side A
unconditionally enters UVLO when AVDD falls below AVDDUVLO– and exits UVLO when AVDD rises above
AVDDUVLO+. Side B operates the same as Side A with respect to its BVDD supply.
Figure 15. Device Behavior during Normal Operation
INPUT
AVDD
UVLO-
BVDD
UVLO+
UVLO-
UVLO+
OUTPUT
tSTART tSTART tSTART tPHL tPLH
tSD
20 Rev. 1.2
Si860x
4.3. Input and Output Characteristics for Non-I2C Digital Channels
The unidirectional Si86 xx input s and output s are st anda rd CMOS drivers/receivers. The no minal output impedance
of an isolator d river cha nne l is appr oxima tel y 50 , ±40%, which is a comb inatio n o f th e va lue of the on -chip seri es
termination resistor and channel resistance of the output driver FET. When driving loads where transmission line
effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces.
Table 14 details powered and unpowered operation of the Si86xx’s non-I2C digital ch anne ls.
Table 14. Si86xx Operation Table
VI Input1,4VDDI State1,2,3VDDO State1,2,3VO Output1,4Comments
HP P H
Normal operation.
LP P L
X5UP P L6
H6,7 Upon transition of VDDI from unpowered to pow-
ered, VO returns to the same state as VI in less
than 1 µs.
X5P UP Undetermined Upon transition of VDDO from unpowered to pow-
ered, VO returns to the same state as VI within
1µs.
Notes:
1. VDDI and VDDO are the input and output power supplies. VI and VO are the respective input and output terminals.
2. Powered (P) state is defined as 3.0 V < VDD < 5.5 V.
3. Unpowered (UP) state is defined as VDD = 0 V.
4. X = not applicable; H = L ogic High; L = L ogic Low.
5. Note that an I/O can power the die for a given side through an internal diode if its source has adequate current.
6. See "6.Ordering Guide" on page 26 for details. This is the sel ectable fail-safe operating mode (ordering option). Some
devices have default output state = H, and some have de fault output state = L, depending on the ordering part number
(OPN). For default high devices, the data channels have pull-ups on inputs/outputs. For default low devices, the data
channels have pull-downs on inputs/outputs.
7. For I2C channels, the outputs for a given side go to Hi-Z when power is lost on the opposite side.
Rev. 1.2 21
Si860x
4.4. Layout Recommendations
To ensure safety in the end user application, high voltage circuits (i.e., circuits with >30 VAC) must be physically
separated from the safety extra-low voltage circuits (SELV is a circuit with <30 VAC) by a certain distance
(creepage/clear ance). I f a com ponent, such as a digital isolator, straddles this isolation barrier, it must meet those
creepage/clearance requirements and also provide a sufficiently large high-voltage breakdown protection rating
(commonly referred to as workin g voltage protection). Table 6 on p age 9 and Table 7 on page 10 det a il the wo rking
voltage and creepage/clearance capabilities of the Si86xx. These tables also detail the component standards
(UL1577, IEC60747, CSA 5A), which ar e readily accepted by certification bodies to provide proof for end-system
specifications requirements. Refer to the end-system specification (61010-1, 60950-1, 60601-1, etc.) requirements
before starting any desig n tha t us es a dig ital isolator.
4.4.1. Supply Bypass
The Si860x family requires a 0.1 µF bypass capacitor between AVDD and AGND and BVDD and BGND. The
capacitor should be placed as close as possible to the package. To enhance the robustne ss of a design, the user
may also include resistors (50–300 ) in series with the inputs and outputs if the system is excessively noisy.
4.4.2. Output Pin Termination
The nominal output impe dance of an non-I 2C isolator channel is appr oximately 50 , ±40%, which is a combination
of the value of the on-chip series termination resistor and cha nnel resist ance of the output driver FET. When driving
loads where transmission line effect s will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
4.5. Fail-Safe Operating Mode
Si86xx devices feature a selectable (by ordering option) mode whereby the default output state (when the input
supply is unpowered) can either be a logic high or logic low when the output supply is powered. See Table 14 on
page 20 and "6.Ordering Guide" on page 26 for more information.
22 Rev. 1.2
Si860x
4.6. Typical Performance Characteristics
The typical performance ch ar acteristics depicted in the following diagra ms are for informa tio n p urpose s only. Refer
to Tables 2, 3, 4, and 5 for actual specification limits.
Figure 16. I2C Side A Pulling Down
(1100 Pull-Up)
Figure 17. I2C Side B Pulling Down
Figure 18. I2C Side B Pulling Up, Side A
Following
Figure 19. I2C Side A Pulling Up, Side B
Following
Figure 20. Non I2C Channel Prop ag ation Delay
vs. Temperature
Side B
Side A
Side B
Side A
Side B
Side A
Side B Side A
5.0
6.0
7.0
8.0
9.0
10.0
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110120
Delay (ns)
Temperature (Degrees C)
Rev. 1.2 23
Si860x
5. Pin Descriptions
Table 15. Si8600/02 in SOIC-8 Package
Pin Name Description
1 AVDD Side A power supply terminal; connect to a source of 3.0 to 5.5 V.
2 ASDA Side A data (open drain) input or output.
3 ASCL Side A clock input or output.
Open drain I/O for Si8600. Standard CMOS input for Si8602.
4 AGND Side A ground terminal.
5 BGND Side B ground terminal.
6 BSCL Side B clock input or output.
Open drain I/O for Si8600. Push-pull output for Si8602.
7 BSDA Side B data (open drain) input or output.
8 BVDD Side B power supply terminal; connect to a source of 3.0 to 5.5 V.
Bidirectional
Isolator Channel
Bidirectional
Isolator Channel
ASDA BSDA
ASCL BSCL
AGND BGND
AVDD BVDD
Si8600
1
2
3
4
8
7
6
5
B idire ction al
Isolator Channel
U nid ire c tio n al
Isolator Channel
ASDA BSDA
ASCL BSCL
AGND BGND
AVDD BVDD
Si8602
1
2
3
4
8
7
6
5
24 Rev. 1.2
Si860x
Table 16. Si8600/02 in Narrow and Wide-Body SOIC-16 Packages
Pin Name Description
1 AGND Side A Ground Terminal.
2 NC No connection.
3 AVDD Side A power supply terminal. Connect to a source of 3.0 to 5.5 V.
4 NC No connection.
5 ASDA Side A data open drain input or output.
6ASCL
Side A data open drain input or output.
7 AGND Side A Ground Terminal.
8 NC No connection.
9 BGND Side B Ground Terminal.
10 NC No connection.
11 BSCL Side B data open drain input or output.
12 BSDA Side B data open drain input or output.
13 NC No connection.
14 BVDD Side B power supply terminal. Connect to a source of 3.0 to 5.5 V.
15 NC No connection.
16 BGND Side B Ground Terminal.
Bidirectional
Isolator Channel
AVDD
NC
BVDD
NC
NC NC
ASDA BSDA
ASCL BSCL
Si8602
AGND
BGND
1
2
3
4
5
6
7
8
10
9
11
12
13
14
15
16
NC
AGND
BGND
Unidirectional
Isolator Channel
NC
Bidirectional
Isolator Channel
AVDD
NC
BVDD
NC
NC NC
ASDA BSDA
ASCL BSCL
Si8600
AGND
BGND
Bidirectional
Isolator Channel
1
2
3
4
5
6
7
8
10
9
11
12
13
14
15
16
NC
AGND
BGND
NC
Rev. 1.2 25
Si860x
Table 17. Si8605/06 in Narrow and Wide-Body SOIC-16 Packages
Pin Name Description
1 AVDD Side A power supply terminal. Connect to a source of 3.0 to 5.5 V.
2 NC No connection.
3 ASDA Side A data (open drain) input or output.
4ADIN/ADIN1
Side A standard CMOS digital input (non I2C).
5 ADOUT/ADIN2 Side A digital input/output (non I2C)
Standard CMOS digital input for Si8606.
Push-Pull output for Si860 5.
6ASCL
Side A clock input or output.
Open drain I/O for Si8605/06.
7 NC No connection.
8 AGND Side A Ground Terminal.
9 BGND Side B Ground Terminal.
10 NC No connection.
11 BSCL Side B clock input or output.
Open drain I/O for Si8605/06.
12 BDIN/BDOUT2 Side B digital input/output (non I2C)
Standard CMOS digital input for Si8605.
Push-Pull output for Si860 6.
13 BDOUT/BDOUT1 Side B digital push-pull output (non I2C).
14 BSDA Side B data open drain input or outp ut.
15 NC No connection.
16 BVDD Side B power supply terminal. Connect to a source of 3.0 to 5.5 V.
Bidirectional
Isolator Channel
AVDD
NC
BVDD
NC
NC NC
ADIN2 BDOUT2
ASDA BSDA
Unidirectional
Isolator Channel
ASCL BSCL
ADIN1 BDOUT1
Si8606
AGND BGND
Unidirectional
Isolator Channel
Bidirectional
Isolator Channel
1
2
3
4
5
6
7
8
10
9
11
12
13
14
15
16
Bidirectional
Isolator Channel
AVDD
NC
BVDD
NC
NC NC
ADOUT BDIN
ASDA BSDA
Unidirectional
Isolator Channel
ASCL BSCL
ADIN BDOUT
Si8605
AGND BGND
Unidirectional
Isolator Channel
Bidirectional
Isolator Channel
1
2
3
4
5
6
7
8
10
9
11
12
13
14
15
16
26 Rev. 1.2
Si860x
6. Ordering Guide
Table 18. Ordering Guide1,2
Ordering Part
Number (OPN) Number of
Bidirectional
I2C Chann e ls
Max I2C Bus
Speed (MHz) Number of
Unidirectional
Non-I2C
Channels
Max Data Rate
of
Non-I2C
Unidirectional
Channels
(Mbps)
Isolation
Ratings
(kVrms)
Temp
Range (C) Package
Si8600AC-B-IS 2 1.7 0 — 3.75 –40 to 125 NB SOIC-8
Si8600AD-B-IS 2 1.7 0 — 5.0 –40 to 125 WB SOIC-16
Si8602AC-B-IS 1 1.7 1 10 3.75 –40 to 125 NB SOIC-8
Si8602AD-B-IS 1 1.7 1 10 5.0 –40 to 125 WB SOIC-16
Si8605AC-B-IS1 2 1.7 1 Forward
1 Reverse 10 3.75 –40 to 125 NB SOIC-16
Si8605AD-B-IS 2 1.7 1 Forward
1 Reverse 10 5.0 –40 to 125 WB SOIC-16
Si8606AC-B-IS1 2 1.7 2 Forward 10 3.75 –40 to 125 NB SOIC-16
Si8606AD-B-IS 2 1.7 2 Fo rward 10 5.0 –40 to 125 WB SOIC-16
Notes:
1. All packages are RoHS-compliant with peak reflow temperature of 260 °C according to the JEDEC industry standard
classifications and peak solder temperature.
Moisture sensitivity level is MSL3 for wide-body SOIC-16 packages.
Moisture sensitivity level is MSL2A for narrow-body SOIC-16 packages.
Moisture sensitivity level is MSL2A for narrow-body SOIC-8 packages.
2. All devices >1 kVRMS are AEC-Q100 qualified.
28 Rev. 1.2
Si860x
Table 19. Package Diagram Dimensions
Dimension Min Max
A — 2.65
A1 0.10 0.30
A2 2.05 —
b 0.31 0.51
c 0.20 0.33
D 10.30 BSC
E 10.30 BSC
E1 7.50 BSC
e1.27 BSC
L 0.40 1.27
h 0.25 0.75
0° 8°
aaa —0.10
bbb — 0.33
ccc —0.10
ddd — 0.25
eee —0.10
fff —0.20
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC Outline MS-013, Variation AA.
4. Recommended reflow profile per JEDEC J-STD-020C specification for
small body, lead-free components.
Rev. 1.2 29
Si860x
8. Land Pattern: 16-Pin Wide-Body SOIC
Figure 22 illustrates the recommended land pattern details for the Si860x in a 16-pin wide-body SOIC. Table 20
lists the values for the dimensions shown in the illustration.
Figure 22. 16-Pin SOIC Land Pattern
Table 20. 16-Pin Wide Body SOIC Land Pattern Dimensions
Dimension Feature (mm)
C1 Pad Column Spacing 9.40
E Pad Row Pitch 1. 27
X1 Pad Width 0.60
Y1 Pad Length 1.90
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P1032X265-16AN
for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card
fabrication tolerance of 0.05 mm is assumed.
30 Rev. 1.2
Si860x
9. Package Outline: 8-Pin Narrow Body SOIC
Figure 23 illustrates the package details for the Si860x in an 8-pin SOIC (SO-8). Table 21 lists the values for the
dimensions shown in the illustration.
Figure 23. 8-pin Small Outline Integrated Circuit (SOIC) Package
Table 21. Package Diagram Dimensions
Symbol Millimeters
Min Max
A 1.35 1.75
A1 0.10 0.25
A2 1.40 REF 1.55 REF
B 0.33 0.51
C 0.19 0.25
D 4.80 5.00
E 3.80 4.00
e 1.27 BSC
H 5.80 6.20
h 0.25 0.50
L 0.40 1.27
08
Rev. 1.2 31
Si860x
10. Land Pattern: 8-Pin Narrow Body SOIC
Figure 24 illustrates the recommended land pattern details for the Si860x in an 8-pin narrow-body SOIC. Table 22
lists the values for the dimensions shown in the illustration.
Figure 24. PCB Land Pattern: 8-Pin Narrow Body SOIC
Table 22. PCM Land Pattern Dimensions (8-Pin Narrow Body SOIC)
Dimension Feature (mm)
C1 Pad Column Spacing 5.40
E Pad Row Pitch 1.27
X1 Pad Width 0.60
Y1 Pad Length 1.55
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X173-8 N for
Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card
fabrication tolerance of 0.05 mm is assumed.
Rev. 1.2 33
Si860x
Table 23. Package Diagram Dimensions
Dimension Min Max
A — 1.75
A1 0.10 0.25
A2 1.25 —
b 0.31 0.51
c 0.17 0.25
D 9.90 BSC
E 6.00 BSC
E1 3.90 BSC
e 1.27 BSC
L 0.40 1.27
L2 0.25 BSC
h 0.25 0.50
θ0° 8°
aaa 0.10
bbb 0.20
ccc 0.10
ddd 0.25
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Ou tline MS-012,
Variation AC.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for Small Body Components.
34 Rev. 1.2
Si860x
12. Land Pattern: 16-Pin Narrow Body SOIC
Figure 26 illustrates the recommended land pattern details for the Si860x in a 16-pin narrow-body SOIC. Table 24
lists the values for the dimensions shown in the illustration.
Figure 26. 16-Pin Narrow Body SOIC PCB Land Pattern
Table 24. 16-Pin Narrow Body SOIC Land Pattern Dimensions
Dimension Feature (mm)
C1 Pad Column Spacing 5.40
E Pad Row Pitch 1. 27
X1 Pad Width 0.60
Y1 Pad Length 1.55
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X165-16N
for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card
fabrication tolerance of 0.05 mm is assumed.
Rev. 1.2 35
Si860x
13. Top Markings
13.1. Si860x Top Marking (16-Pin W ide Body SOIC)
13.2. Top Marking Explanation (16-Pin Wide Body SOIC)
Line 1 Marking: Base Part Number
Ordering Options
(See Ordering Guide fo r mo re
information).
Si86 = Isolator product series
XY = Channel Configuration
05 = Bidirectional SCL, SDA; 1- forward and
1-reverse unidirectional channel
06 = Bidirectional SCL, SDA; 2- forward
unidirectional chan nels
S = Speed Grade
A=1.7Mbps
V = Isolation rating
A = 1 kV; B = 2.5 kV ; C = 3.75 kV; D = 5.0 kV
Line 2 Marking: YY = Year
WW = Workweek Assigned by assembly subcontractor. Corresponds to the
year and workweek of the mold date.
RTTTTT = Mfg Code Manufacturing code from assembly ho use
“R” indicates revision
Line 3 Marking: Circle = 1.5 mm Diameter
(Center-Justified) “e3” Pb-Free Symbol
Country of Origin ISO Code
Abbreviation TW = Taiwan
Si86XYSV
YYWWRTTTTT
TW
e3
36 Rev. 1.2
Si860x
13.3. Si860x Top Marking (8-Pin Narrow Body SOIC)
13.4. Top Marking Explanation (8-Pin Narrow Body SOIC)
Line 1 Marking: Base Part Number
Ordering Options
(See Ordering Guide for more
information).
Si86 = Isolator I2C Product Series:
XY = Channel Configuration
00 = Bidirectional SCL and SDA channels
02 = Bidirectional SDA channel;
Unidirectional SCL channel
S = Speed Grade
A=1.7Mbps
V = Isolation rating
A = 1 kV; B = 2.5 kV; C = 3.75 kV
Line 2 Marking: YY = Year
WW = Work week Assigned by asse mb ly co ntr a cto r. Co rr esp o nd s to th e
year and work week of the mold date.
R = Product Rev
F=Wafer Fab First two characters of the manufacturing code from
Assembly.
Line 3 Marking: Circle = 1.1 mm Diameter
Left-Justified “e3” Pb-Free Symbol
A = Assembly Site
I = Internal Code
XX = Serial Lot Number
Last four characters of the manufacturing code from
assembly.
Si86XYSV
YYWWRF
AIXX
e3
Rev. 1.2 37
Si860x
13.5. Si860x Top Marking (16-Pin Narrow Body SOIC)
13.6. Top Marking Explanation (16-Pin Narrow Body SOIC)
Line 1 Marking: Base Part Number
Ordering Options Si86 = Isolator product series
XY = Channel Configuration
05 = Bidirectional SCL, SDA; 1- forward and
1-reverse unidirectional channel
06 = Bidirectional SCL, SDA; 2- forward
unidirectional channels
S = Speed Grade
A=1.7Mbps
V = Isola tio n ra tin g
A=1kV; B=2.5kV; C=3.75kV
Line 2 Marking: Circle = 1.2 mm Diameter “e3” Pb-Free Symbol
YY = Year
WW = Work Week Assigned by the Assembly House. Correspo n ds to the
year and work week of the mold date.
RTTTT T = Mfg Code Manufacturing code from assembly house
“R” indicates revision
Circle = 1.2 mm diameter “e3” Pb-Free Symbol.
Si86XYSV
YYWWRTTTTT
e3
38 Rev. 1.2
Si860x
DOCUMENT CHANGE LIST
Revision 0.1 to Revision 0.2
Si8601 replaced by Si8602 througho ut.
Added chip graphics on page 1.
Moved Table 12 to page 13.
Updated Table 3, “Si8600/02/05/06 Electrical
Characteristics for Bidirectional I2C Channels1,” on
page 5.
Updated Table 7, “Insulation and Safety-Related
Specifications,” on page 10.
Updated Table 9, “IEC 60747-5-2 Insulation
Characteristics for Si86xxxx*,” on page 11.
Moved “3. Typical Application Overview” to page 15 .
Moved “Typical Performance Characteristics” to
page 22.
Updated "5.Pin Descriptions" on page 23.
Updated "6.Ordering Guide" on page 26.
Revision 0.2 to Revision 0.3
Added chip graphics on page 1.
Moved Tables 1 and 2 to page 4.
Updated Table 7, “Insulation and Safety-Related
Specifications,” on page 10.
Updated Table 9, “IEC 60747-5-2 Insulation
Characteristics for Si86xxxx*,” on page 11.
Moved Table 13 to page 16.
Moved Table 14 to page 20.
Updated "5.Pin Descriptions" on page 23.
Updated "6.Ordering Guide" on page 26.
Revision 0.3 to Revision 1.0
Reordered spec tables to conform to new
convention.
Removed “pending” throughout docume nt.
Revision 1.0 to Revision 1.1
Updated Figu re s 11 and 12.
Updated Pin 7 AGND connection.
Updated "6.Ordering Guide" on page 26 to include
MSL2A.
Revision 1.1 to Revision 1.2
Updated Table 12 on page 13.
Added junction temperature spec.
Updated "4.4.1.Supply Byp ass" on page 21.
Updated "6.Ordering Guide" on page 26.
Removed Rev A devices.
Updated "7.Package Outline: 16-Pin Wide Body
SOIC" on page 27.
Updated Top Marks.
Added revision description.
Rev. 1.2 39
Si860x
NOTES:
40 Rev. 1.2
Si860x
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