L9822E
OCTAL SERIAL SOLENOID DRIVER
ADVANCE DATA
.EIGHTLOWRDSon DMOSOUTPUTS
(0.5ΩATIO=1A@25°CV
CC =5V±5%)
.8 BITSERIALINPUT DATA(SPI)
.8 BIT SERIAL DIAGNOSTIC OUTPUT FOR
OVERLOADANDOPENCIRCUITCONDITIONS
.OUTPUTSHORTCIRCUIT PROTECTION
.CHIPENABLESELECTFUNCTION(activelow)
.INTERNAL 36V CLAMPING FOR EACH OUT-
PUT
.CASCADABLE WITH ANOTHER OCTAL
DRIVER
.LOWQUIESCENTCURRENT (10mAMAX.)
.PACKAGE MULTIWATT15, PowerSO20 AND
SO20L
DESCRIPTION
TheL9822E is an octal low side solenoiddriver
realized in Multipower-BCDtechnologyparticularly
suitedfor drivinglamps,relaysand solenoidsin au-
BLOCK DIAGRAM
PowerSO20 SO20L(16+2+2) Multiwatt15
ORDERING NUMBERS: L9822E (Multiwatt15)
L9822EPD (Power SO20)
L9822ED(SO20L )
tomotive environment. The DMOS outpts L9822E
has a verylow powerconsumption.
Data is transmitted serially to the device using the
SerialPeripheralInterface(SPI)protocol.
The L9822Efeaturestheoutputsstatusmonitoring
function.
MULTIPOWER BCD TECHNOLOGY
September 1994
Thisis advanced information ona new product nowin development or undergoing evaluation. Detailsare subject to changewithoutnotice.
1/11
PowerSO20 Multiwatt15
SO20L
PIN CONNECTIONS (topview)
THERMAL DATA
Symbol Parameter Multiwatt15 SO20L PowerSO20 Unit
Rth j-case Thermal Resistance Junction-Case Max. 2 25 1.5 °C/W
Rth j-amb Thermal Resistance Junction-Ambient Max. 35 70 60 °C/W
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
VCC DC Logic Supply – 0.7 7 V
VOOutput Voltage – 0.7 40 V
IIInput Transient Current
(CE, SI, SCLK, RESET, SO) :
Duration Time t = 1s,
VI<0
V
I>V
CC
–25 +25 mA
mA
IOdc Continous Output Current (for each output) Int. Limited A
Tj,T
stg Junction and Storage Temperature Range – 40 150 °C
GND
SO
VDD
RESET
OUT7
OUT5
OUT6
OUT4
N.C. N.C.
OUT3
OUT2
OUT0
OUT1
CE
SCLK
SI
GND1
3
2
4
5
6
7
8
9
18
17
16
15
14
12
13
11
19
10
20
GND GND
D94AT119
OUT6
OUT5
OUT4
N.C.
GND
N.C.
GND
OUT3
OUT2 CE
SLCK
SI
GND
GND
SO
VDD
RESET
OUT71
3
2
4
5
6
7
8
9
18
17
16
15
14
12
13
11
19
10
20
OUT1 OUT0
D94AT118
L9822E
2/11
VCC
Logicsupply voltage - nominally 5V
GROUND
DeviceGround.Thisgroundappliesforthelogiccir-
cuitsas well asthe poweroutputstages.
RESET
Asynchronousresetfortheoutputstages,theparal-
lellatch and the shiftregister inside theL9822ESP.
Thispin isactivelowandit mustnotbe leftfloating.
Apoweronclearfunctionmaybeimplementedcon-
nectingthispin to VCC withan externalresistorand
to groundwith an externalcapacitor.
CE
ChipEnable.Datais transferredfromthe shift regi-
sterstotheoutputsontherising edgeof thissignal.
Thefalling edge of this signalsets the shift register
with the outputvoltagesensebits coming from the
output stages. The output driver for the SO pin is
enabledwhenthis pinis low.
SO
Serial Output. This pin is the serial output from the
shift register and it is tri-stated when CE is high.A
highfor a data biton thispin indicatesthat the par-
ticularoutputis high. A low on this pinfor a data bit
indicatesthat the outputis low.
Comparing the serial output bits with the previous
serial input bits the external microcontroller imple-
ments thediagnosticdata supplied by the L9822.
SI
Serial Input.This pin is the serialdata input.A high
onthispinwillprogramaparticularoutputtobeOFF,
whilea lowwill turn it ON.
SCLK
Serial Clock. This pin clocks the shift register.New
SO datawill appearoneveryrising edgeof thispin
andnewSIdatawillbelatchedoneverySCLK’sfal-
ling edgeinto the shift register.
OUTPUTS00-07
Poweroutputpins.Theinputandoutputbitscorres-
pondingto07 aresentandreceivedfirstviatheSPI
busand00is thelast.Theoutputsareprovidedwith
currentlimitingandvoltagesensefunctionsforfault
indicationand protection.Thenominalload current
for theseoutputsis 500mA, but the current limiting
issettoaminimumof1.05A.Theoutputsalsohave
on boardclamps set at about 36V for recirculation
of inductiveload current.
PIN DESCRIPTION
ELECTRICAL CHARACTERISTICS (VCC =5V±5%.Tj=– 40 to 125°C ; unlessotherwise speciifed)
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VOC Output Clamping Volt. IO= 0.5A, Output Programmed OFF 30 40 V
EOC Out. Clamping Energy IO= 0.5A, When ON 20 mJ
IOleak Out. Leakage Current VO= 24V, Output Progr. OFF 1 mA
RDSon On Resistance Output Progr. ON
IO= 0.5A
IO= 0.8A
IO=1A
With Fault Reset Disabled
0.55
0.55
0.55
1
1
1
Ω
Ω
Ω
IOL Out. Self Limiting
Current Output Progr. ON 1.05 A
tPHL Turn-on Delay IO= 500mA
No Reactive Load 10 µs
tPTurn-off Delay IO= 500mA
No Reactive Load 10 µs
VOREF Fault Refer. Voltage Output Progr. OFF
Fault detected if VO>V
OREF 1.6 2 V
tUD Fault Reset Delay
(after CE L to H
transition)
See fig. 3 75 250 µs
VOFF Output OFF Voltage Output Pin Floating.cOutput Progr. OFF, 1.0 V
L9822E
3/11
ELECTRICAL CHARACTERISTICS (Continued)
Symbol Parameter Test Conditions Min. Typ. Max. Unit
INPUT BUFFER(SI, CE,SCLK and RESETpins)
VT– Threshold Voltage at
Falling Edge
SCLK only
VCC =5V±10% 0.2VCC
0.6
V
V
VT+ Threshold Voltage at
Rising Edge
SCLK only
VCC =5V±10% 0.7VCC
4.15
V
V
VHHysteresis Voltage VT+ –V
T– 0.85 2.5 V
IIInput Current VCC = 5.50V, 0 < VI<V
CC –10 +10 µ
A
C
IInput Capacitance 0 < VI<V
CC 20 nF
OUTPUT BUFFER(SO pin)
VSOL Output LOW Voltage IO= 1.6mA 0.4 V
VSOH Output HIGH Voltage IO= 0.8mA VCC
– 1.3V V
ISOtl Output Tristate Leakage
Current 0<V
O<V
CC, CE Pin Held High,
VCC = 5.25V –20 20 µ
A
C
SO Output Capacitance 0 < VO<V
CC
CE Pin Held High 20 pF
ICC Quiescent Supply
Current at VCC Pin All Outputs Progr. ON. IO= 0.5A
per Output Simultaneously 10 mA
SERIALPERIPHERAL INTERFACE (see fig. 2, timingdiagram)
fop Operating Frequency D.C. 2 MHz
tlead Enable Lead Time 250 ns
tlag Enable Lag Time 250 ns
twSCKH Clock HIGH Time 200 ns
twSCKL Clock LOW Time 200 ns
tsu Data Setup Time 75 ns
tHData Hold Time 75 ns
tEN Enable Time 250 ns
tDIS Disable Time 250 ns
tVData Valid Time 100 ns
trSO Rise Time (SO output) VCC = 20 to 70% CL= 200pF 50 ns
tfSO Fall Time (SO output) VCC = 70 to 20% CL= 200pF 50 ns
trSI Rise Time SPI
Inputs (SCK, SI, CE) VCC = 20 to 70% CL= 200pF 200 ns
tfSI Fall Time SPI
Inputs (SCLK, SI, CE) VCC = 70 to 20% CL= 200pF 200 ns
tho Output Data Hold Time 0 µs
L9822E
4/11
TheL9822ESPDMOSoutputis a lowoperatingpo-
werdevicefeatu-ring,eight 1ΩRDSONDMOSdrivers
with transient protection circuits in output stages.
Eachchannelisindependentlycontrolledbyanout-
putlatchanda commonRESETlinewhichdisables
all eight outputs.The driver has low saturation and
shortcircuitprotectionandcandriveinductiveandre-
sistive loads such as solenoids, lamps and relais.
DataistransmittedtothedeviceseriallyusingtheSe-
rialPeripheralInterface(SPI)protocol.Thecircuitre-
ceives 8 bit serial data by means of theserial input
(SI) which is stored in an internal registerto control
theoutputdrivers.Theserialoutput(SO)provides8
bit of diagnosticdata representingthe voltage level
at the driver output.This allows the microprocessor
to diagnosethe conditionof the outputdrivers.
The output saturation voltage is monitored by a
comparatorfor an outof saturationconditionandis
abletounlatchtheparticulardriverthroughthefault
reset line. This circuit is also cascadablewith ano-
ther octal driver in order to jam 8 bit multiple data.
The device is selected when the chip enable (CE)
lineis low.
Additionally the (SO) is placed in a tri-state mode
when the deviceis deselected.The negativeedge
of the (CE) transfersthe voltagelevel of thedrivers
totheshiftregisterandthepositiveedgeofthe(CE)
latchesthenewdatafromtheshiftregistertothedri-
vers. When CE is Low, data bit containedinto the
shift register is transferred to SO output at every
SCLKpositivetransitionwhile databitpresentatSI
inputislatchedintotheshiftregisteron everySCLK
negativetransition.
Internal BlocksDescription
The internal architectureof the deviceis basedon
the threeinternalmajorblocks: the octalshift regi-
sterfortalkingtothe SPIbus,theoctallatchforhol-
dingcontrolbits writtenintothedeviceandthe octal
load driver array.
Shift Register
The shiftregister has bothserial andparallelinputs
and serial and parallel outputs.The serial inputac-
ceptsdatafromthe SPIbusand theserial outputsi-
multaneously sends data into the SPI bus. The
paralleloutputsarelatchedinto theparallellatchin-
sidetheL9822ESPattheendofadatatransfer.The
parallelinputs jam diagnosticdata into the shift re-
gisterat thebeginningof a datatransfercycle.
ParallelLatch
The parallellatchholds theinputdatafrom theshift
register.This datathen actuatestheoutputstages.
Individual registers in the latch may be cleared by
fault conditions in order to protect the overloaded
outputstages.Theentirelatchmayalsobecleared
by theRESET signal.
Output Stages
Theoutputstagesprovideanactivelowdrivesignal
suitable for 0.75A continuous loads. Each output
has a currentlimit circuit which limits the maximum
outputcurrent to at least1.05Ato allowfor high in-
rushcurrents.Additionally,theoutputshaveinternal
zenersset to 36 voltsto clamp inductivetransients
at turn-off.Each output also has a voltage compa-
ratorobservingtheoutputnode.If thevoltageexce-
eds 1.8V on an ON output pin, a fault condition is
assumedand the latch driving this particular stage
is reset, turning the outputOFF to protectit. The ti-
ming of this action is described below. Thesecom-
parators also provide diagnostic feedback data to
theshiftregister.Additionally,thecomparatorscon-
tainaninternalpulldowncurrentwhichwillcausethe
cell to indicate a low output voltageif the output is
programmedOFFandtheoutputpinisopencircui-
ted.
TIMING DATA TRANSFER
Figure #2 showsthe overalltiming diagramfrom a
byte transfer to and from the L9822ESP using the
SPIbus.
CE Highto Low Transition
TheactionbeginswhentheChipEnable(CE)pinis
pulledlow.Thetri-stateSerialOutput(SO)pindriver
willbe enabledentire time thatCE islow. Atthefal-
lingedgeoftheCEpin,thediagnosticdatafromthe
voltagecomparatorsin theoutputstageswillbelat-
ched into the shift register.If a particular output is
high, a logic one willbe jammed intothat bit in the
shiftregister.Iftheoutputis low,a logiczerowillbe
loadedthere.Themostsignificantbit(07)shouldbe
presentedat theSerial Input (SI) pin.A zero at this
pin will programan outputON, while a onewill pro-
gramthe outputOFF.
SCLK Transitions
The Serial Clock(SCLK) pin shouldthenbe pulled
high.Atthispointthediagnosticbitfromthemostsi-
gnificantoutput(07)willappearattheSOpin.Ahigh
here indicates that the 07 pin is higher than 1.8V.
TheSCLKpinshouldthenbetoggledlowthenhigh.
NewSOdatawillappearfollowingeveryrisingedge
of SCLK and new SI data will be latched into the
L9822ESPshiftregisteronthefallingedges.Anun-
limited amount of data may be shiftedthrough the
FUNCTIONAL DESCRIPTION
L9822E
5/11
device shift register (into the SI pin and out the SO
pin), allowing the otherSPI devicesto becascaded
in a daisychain with the L9822ESP.
CELow to High Transition
Once the last data bit has been shifted into the
L9822ESP,the CEpin shouldbe pulledhigh.
At therising edgeof CEthe shiftregisterdataislat-
chedintotheparallellatchandtheoutputstageswill
beactuatedbythe new data.Aninternal160µsde-
laytimerwill also bestartedat thisrisingedge (see
tUD). During the 160µs period, the outputs will be
protectedonlyby theanalogcurrentlimiting circuits
since the resetting of the parallel latches by faults
conditionswillbeinhibitedduringthisperiod.Thisal-
lowsthe partto overcomeany high inrushcurrents
that may flow immediately after turn on. Once the
delay period has elapsed, the output voltages are
sensedbythecomparatorsandanyoutputwithvol-
tageshigherthan1.8VarelatchedOFF.Itshouldbe
notedthatthe SCLK pin shouldbe lowatboth tran-
sitionsof the CE pin to avoid any false clocking of
theshiftregister.TheSCLKinputisgatedby theCE
pin, so that the SCLK pin is ignoredwhenever the
CE pinis high.
FAULTCONDITIONSCHECK
Checkingforfaultconditionsmaybedoneinthefol-
lowing way. Clock in a new control byte. Wait 160
microseconds or so to allow the outputs to settle.
Clockinthesamecontrolbyteandobservethediag-
nostic datathat comes out of thedevice.The diag-
nostic bits should be identical to the bits that were
firstclockedin.Anydifferenceswouldpointtoa fault
on thatoutput.If theoutputwasprogrammedONby
clockingin a zero,anda one camebackas thedia-
gnosticbitforthatoutput,theoutputpinwasstillhigh
anda shortcircuit oroverloadconditionexists.Ifthe
outputwasprogrammedOFF byclocking in a one,
and a zerocameback as the diagnosticbit for that
output,nothinghadpulledtheoutputpinhighandit
Figure 1 : Byte Timing with AsynchronousReset.
L9822E
6/11
Figure 2 : TimingDiagram.
Figure 3 : TypicalApplicationCircuit.
L9822E
7/11
MULTIWATT15 PACKAGE MECHANICAL DATA
DIM. mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A 5 0.197
B 2.65 0.104
C 1.6 0.063
D 1 0.039
E 0.49 0.55 0.019 0.022
F 0.66 0.75 0.026 0.030
G 1.02 1.27 1.52 0.040 0.050 0.060
G1 17.53 17.78 18.03 0.690 0.700 0.710
H1 19.6 0.772
H2 20.2 0.795
L 21.9 22.2 22.5 0.862 0.874 0.886
L1 21.7 22.1 22.5 0.854 0.870 0.886
L2 17.65 18.1 0.695 0.713
L3 17.25 17.5 17.75 0.679 0.689 0.699
L4 10.3 10.7 10.9 0.406 0.421 0.429
L7 2.65 2.9 0.104 0.114
M 4.25 4.55 4.85 0.167 0.179 0.191
M1 4.63 5.08 5.53 0.182 0.200 0.218
S 1.9 2.6 0.075 0.102
S1 1.9 2.6 0.075 0.102
Dia1 3.65 3.85 0.144 0.152
L9822E
8/11
e
a2 A
Ea1
PSO20MEC
DETAILA
T
D
110
1120
E1
E2
hx45°
DETAILA
lead
slug
a3
S
Gage Plane 0.35
L
DETAILB
R
DETAILB
(COPLANARITY)
GC
-C-
SEATING PLANE
e3
b
c
NN
PowerSO20 PACKAGE MECHANICAL DATA
DIM. mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A 3.60 0.1417
a1 0.10 0.30 0.0039 0.0118
a2 3.30 0.1299
a3 0 0.10 0 0.0039
b 0.40 0.53 0.0157 0.0209
c 0.23 0.32 0.009 0.0126
D (1) 15.80 16.00 0.6220 0.6299
E 13.90 14.50 0.5472 0.570
e 1.27 0.050
e3 11.43 0.450
E1 (1) 10.90 11.10 0.4291 0.437
E2 2.90 0.1141
G 0 0.10 0 0.0039
h 1.10 0.0433
L 0.80 1.10 0.0314 0.0433
N10°(max.)
S8
°
(max.)
T 10.0 0.3937
(1) ”D and F” do not include mold flash or protrusions
- Mold flash or protrusions shall not exceed 0.15mm (0.006”)
L9822E
9/11
SO20 PACKAGE MECHANICAL DATA
DIM. mm inch
MIN TYP MAX MIN TYP MAX
A 2.65 0.104
a1 0.1 0.2 0.004 0.008
a2 2.45 0.096
b 0.35 0.49 0.014 0.019
b1 0.23 0.32 0.009 0.013
C 0.5 0.020
c1 45°(typ.)
D 1 12.6 0.039 0.496
E 10 10.65 0.394 0.419
e 1.27 0.050
e3 11.43 0.450
F 1 7.4 0.039 0.291
G 8.8 9.15 0.346 0.360
L 0.5 1.27 0.020 0.050
M 0.75 0.030
S8°(max.)
L9822E
10/11
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for
the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its
use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specification
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously
supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems
without express written approval of SGS-THOMSON Microelectronics.
1996 SGS-THOMSON Microelectronics – Printed in Italy – All Rights Reserved
MULTIWATTis a Registered Trademark of SGS-THOMSON Microelectronics
PowerSO-20is a Trademark of SGS-THOMSON Microelectronics
SGS-THOMSON Microelectronics GROUP OF COMPANIES
Australia - Brazil - Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco -
The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
L9822E
11/11
