GMF05LC-HSF
www.vishay.com Vishay Semiconductors
Rev. 1.6, 04-Jan-2019 1Document Number: 81200
For technical questions, contact: ESDprotection@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
5-Line ESD Protection Diode Array in LLP75-6L
MARKING (example only)
Dot = pin 1 marking
XX = date code
YY = type code (see table below)
DESIGN SUPPORT TOOLS
FEATURES
• Ultra compact LLP75-6L package
• Low package profile < 0.6 mm
• 5-line ESD protection
• Low leakage current IR < 0.1 μA
• Low load capacitance of typ. 43 pF at VR = 0 V
• ESD immunity acc. IEC 61000-4-2
± 30 kV contact discharge
± 30 kV air discharge
• Working voltage range VRWM = 5 V
• e4 - precious metal (e.g. Ag, Au, NiPd, NiPdAu) (no Sn)
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
19957
1
19956
123
654
21001
XX
YY
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Available
Models
ORDERING INFORMATION
DEVICE NAME ORDERING CODE TAPED UNITS PER REEL
(8 mm TAPE ON 7" REEL) MINIMUM ORDER QUANTITY
GMF05LC-HSF GMF05LC-HSF-GS08 3000 15 000
PACKAGE DATA
DEVICE NAME PACKAGE
NAME
TYPE
CODE WEIGHT MOLDING COMPOUND
FLAMMABILITY RATING
MOISTURE
SENSITIVITY LEVEL SOLDERING CONDITIONS
GMF05LC-HSF LLP75-6L 1B 4.2 mg UL 94 V-0 MSL level 1
(according J-STD-020) Peak temperature max. 260 °C
ABSOLUTE MAXIMUM RATINGS GMF05LC-HSF
PARAMETER TEST CONDITIONS SYMBOL VALUE UNIT
Peak pulse current BiAs-mode: each input (pin 1; 3 to pin 6) to ground (pin 2);
acc. IEC 61000-4-5; tp = 8/20 μs; single shot IPPM 5A
Peak pulse power BiAs-mode: each input (pin 1; 3 to pin 6) to ground (pin 2);
acc. IEC 61000-4-5; tp = 8/20 μs; single shot PPP 70 W
ESD immunity
BiAs-mode: each input (pin 1; 3 to pin 6) to
ground (pin 2);
acc. IEC 61000-4-2; 10 pulses
Contact
discharge VESD
± 30 kV
Air
discharge ± 30 kV
Operating temperature Junction temperature TJ-55 to +125 °C
Storage temperature TSTG -55 to +150 °C
GMF05LC-HSF
www.vishay.com Vishay Semiconductors
Rev. 1.6, 04-Jan-2019 2Document Number: 81200
For technical questions, contact: ESDprotection@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
BiAs-MODE (5-line bidirectional asymmetrical protection mode)
With the GMF05LC-HSF up to 5 signal- or data-lines (L1 to L5) can be protected against voltage transients. With pin 2
connected to ground and pin 1; pin 3 up to pin 6 connected to a signal- or data-line which has to be protected. As long as the
voltage level on the data- or signal-line is between 0 V (ground level) and the specified maximum reverse working voltage (VRWM)
the protection diode between data-line and ground offer a high isolation to the ground line. The protection device behaves like
an open switch.
As soon as any positive transient voltage signal exceeds the break through voltage level of the protection diode, the diode
becomes conductive and shorts the transient current to ground. Now the protection device behaves like a closed switch. The
clamping voltage (VC) is defined by the breakthrough voltage (VBR) level plus the voltage drop at the series impedance
(resistance and inductance) of the protection device.
Any negative transient signal will be clamped accordingly. The negative transient current is flowing in the forward direction of
the protection diode. The low forward voltage (VF) clamps the negative transient close to the ground level.
Due to the different clamping levels in forward and reverse direction the GMF05LC-HSF clamping behavior is bidirectional and
asymmetrical (BiAs).
Note
• Ratings at 25 °C ambient temperature, unless otherwise specified. BiAs mode: each input (pin 1, 2, 3, to 6) to ground (pin 2).
If a higher surge current or peak pulse current (IPP) is needed, some protection diodes in the GMF05LC-HSF can also be used
in parallel in order to “multiply” the performance.
If two diodes are switched in parallel you get
• double surge power = double peak pulse current (2 x IPPM)
• half of the line inductance = reduced clamping voltage
• half of the line resistance = reduced clamping voltage
• double line capacitance (2 x CD)
• double reverse leakage current (2 x IR)
L4
L5
L3
L1
L2
3
2
1
3
4
5
BiAs
Ground
20739
ELECTRICAL CHARACTERISTICS GMF05LC-HSF
PARAMETER TEST CONDITIONS/REMARKS SYMBOL MIN. TYP. MAX. UNIT
Protection paths Number of lines which can be protected Nchannel - - 5 lines
Reverse stand-off voltage at IR = 1 μA VRWM --5V
Reverse current at VR = VRWM = 5 V IR- 0.01 0.1 μA
Reverse breakdown voltage at IR = 1 mA VBR 6-8V
Reverse clamping voltage at IPP = 1 A acc. IEC 61000-4-5 VC
-89.5V
at IPP = IPPM = 5 A acc. IEC 61000-4-5 - 11.5 12.5 V
Forward clamping voltage at IF = 1 A acc. IEC 61000-4-5 VF
-1.52 V
at IPP = IPPM = 5 A acc. IEC 61000-4-5 - 3.1 4 V
Capacitance at VR = 0 V; f = 1 MHz CD
-4350pF
at VR = 2.5 V; f = 1 MHz - 25 - pF
L1 L2
L3
20740
1
3
6
5
4
2
Ground
GMF05LC-HSF
www.vishay.com Vishay Semiconductors
Rev. 1.6, 04-Jan-2019 3Document Number: 81200
For technical questions, contact: ESDprotection@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
TYPICAL CHARACTERISTICS
Tamb = 25 °C, unless otherwise specified
Fig. 1 - ESD Discharge Current Wave Form
acc. IEC 61000-4-2 (330 /150 pF)
Fig. 2 - 8/20 μs Peak Pulse Current Wave Form
acc. IEC 61000-4-5
Fig. 3 - Typical Capacitance CD vs. Reverse Voltage VR
Fig. 4 - Typical Forward Current IF vs. Forward Voltage VF
Fig. 5 - Typical Reverse Voltage VR vs. Reverse Current IR
Fig. 6 - Typical Peak Clamping Voltage VC vs.
Peak Pulse Current IPP
0 %
20 %
40 %
60 %
80 %
100 %
120 %
-10 0 102030405060708090100
Time (ns)
Discharge Current I
ESD
Rise time = 0.7 ns to 1 ns
53 %
27 %
20557
0
5
10
15
20
25
30
35
40
45
50
0123456
f = 1 MHz
BiAs-mode
BiSy-mode
20281
VR (V)
CD (pF)
0.001
0.01
0.1
1
10
100
0.5 0.6 0.7 0.8 0.9 1
VF (V)
I
F
(mA)
BiAs-mode
20282
0
1
2
3
4
5
6
7
8
9
10
0.01 0.1 1 10 100 1000 10 000
IR (µA)
VR (V)
BiAs-mode
BiSy-mode
20283
0
2
4
6
8
10
12
14
16
0123456
IPP (A)
VC (V)
Measured acc. IEC 61000-4-5 (8/20µs - wave form)
VC
BiAs-mode
BiSy-mode
20284
GMF05LC-HSF
www.vishay.com Vishay Semiconductors
Rev. 1.6, 04-Jan-2019 4Document Number: 81200
For technical questions, contact: ESDprotection@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Fig. 7 - Typical Clamping Performance at + 8 kV
Contact Discharge (acc. IEC 61000-4-2)
Fig. 8 - Typical Clamping Performance at - 8 kV
Contact Discharge (acc. IEC 61000-4-2)
Fig. 9 - Typical Peak Clamping Voltage at ESD
Contact Discharge (acc. IEC 61000-4-2)
- 60
- 40
- 20
0
20
40
60
80
- 10 0 10 20 30 40 50 60 70 80 90
Acc. IEC 61000-4-2
+ 8 kV
contact discharge
t (ns)
V
C-ESD
(V)
21105
- 80
- 60
- 40
- 20
0
20
40
60
- 10 0 10 20 30 40 50 60 70 80 90
Acc. IEC 61000-4-2
- 8 kV
contact discharge
t (ns)
V
C-ESD
(V)
21106
- 300
- 200
- 100
0
100
200
300
0 5 10 15 20 25 30
VESD (kV)
VC-ESD (V)
21107
Acc. IEC 61000-4-2 contact discharge
VC-ESD
Positive discharge
Negative discharge
GMF05LC-HSF
www.vishay.com Vishay Semiconductors
Rev. 1.6, 04-Jan-2019 5Document Number: 81200
For technical questions, contact: ESDprotection@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
PACKAGE DIMENSIONS in millimeters (inches): LLP75-6L
1.05 (0.041)
0.5 (0.020)
0.95 (0.037)
Heat sink
0.3 (0.012)
0.2 (0.008)
0.3 (0.012)
0.2 (0.008)
0.3 (0.012)
0.2 (0.008)
0.55 (0.022)
0.45 (0.018)
0.6 (0.024)
0.25 (0.010)
0.05 (0.002)
0 (0.000)
0.15 (0.006)
0.60 (0.023)
0.54 (0.021)
1.65 (0.065)
1.55 (0.061)
1.65 (0.065)
1.55 (0.061)
Pin 1 marking
0.5 (0.020) 0.5 (0.020)
0.3 (0.012) 0.3 (0.012)
0.15 (0.006) 0.15 (0.006)
0.5 (0.020)
0.5 (0.020)
1 (0.039)
0.25 (0.010)
Solder resist mask
Solder pad
Document no.:S8-V-3906.02-010 (4)
Rev. 4 - Date: 21. March 2006
20454
Created - Date: 04. MAY 2005
Foot print recommendation:
1 (0.039)
1 (0.039)
GMF05LC-HSF
www.vishay.com Vishay Semiconductors
Rev. 1.6, 04-Jan-2019 6Document Number: 81200
For technical questions, contact: ESDprotection@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
LLP75-6x
F 5
S 9
Pin 1 - location
Pad layout - view from top / seen at bottom side
S8-V-3906.02-004 (4)
10.01.2005
Legal Disclaimer Notice
www.vishay.com Vishay
Revision: 08-Feb-17 1Document Number: 91000
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